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Searched refs:MEMCTRL (Results 1 – 25 of 27) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/hashcrypt/
Dfsl_hashcrypt.c228 base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(1); in hashcrypt_sha_ldm_stm_16_words()
431 base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(size / 16U); in hashcrypt_aes_one_block_aligned()
488 base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(actSz / 16U); in hashcrypt_aes_one_block_unaligned()
743 … base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(SHA_MAX_BLOCK_COUNT); in hashcrypt_sha_process_message_data()
766 base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(blkNum); in hashcrypt_sha_process_message_data()
1190 base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(numBlocks); in HASHCRYPT_SHA_UpdateNonBlocking()
1811 base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(1) | HASHCRYPT_MEMCTRL_COUNT(numBlocks); in HASHCRYPT_DriverIRQHandler()
1816 base->MEMCTRL = HASHCRYPT_MEMCTRL_MASTER(0); in HASHCRYPT_DriverIRQHandler()
/hal_nxp-latest/mcux/mcux-sdk/drivers/sha/
Dfsl_sha.c389 base->MEMCTRL = SHA_MEMCTRL_MASTER(1) | SHA_MEMCTRL_COUNT(blkNum); in sha_process_message_data_master()
758 base->MEMCTRL = SHA_MEMCTRL_MASTER(1) | SHA_MEMCTRL_COUNT(numBlocks); in SHA_UpdateNonBlocking()
812 base->MEMCTRL = SHA_MEMCTRL_MASTER(1) | SHA_MEMCTRL_COUNT(numBlocks); in SHA_DriverIRQHandler()
817 base->MEMCTRL = SHA_MEMCTRL_MASTER(0); in SHA_DriverIRQHandler()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S005/
DLPC54S005.h10824 __IO uint32_t MEMCTRL; /**< Memory Control register, offset: 0x10 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54005/
DLPC54005.h10032 __IO uint32_t MEMCTRL; /**< Memory Control register, offset: 0x10 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54016/
DLPC54016.h13466 __IO uint32_t MEMCTRL; /**< Memory Control register, offset: 0x10 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018M/
DLPC54018M.h14925 __IO uint32_t MEMCTRL; /**< Memory Control register, offset: 0x10 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54628/
DLPC54628.h15231 __IO uint32_t MEMCTRL; /**< Memory Control register, offset: 0x10 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S018/
DLPC54S018.h15717 __IO uint32_t MEMCTRL; /**< Memory Control register, offset: 0x10 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018/
DLPC54018.h14925 __IO uint32_t MEMCTRL; /**< Memory Control register, offset: 0x10 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S016/
DLPC54S016.h14172 __IO uint32_t MEMCTRL; /**< Memory Control register, offset: 0x10 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S018M/
DLPC54S018M.h15717 __IO uint32_t MEMCTRL; /**< Memory Control register, offset: 0x10 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S06/
DLPC55S06.h12965 …__IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available)… member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S04/
DLPC55S04.h12965 …__IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available)… member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S26/
DLPC55S26.h10185 …__IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available)… member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S28/
DLPC55S28.h10184 …__IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available)… member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S16/
DLPC55S16.h13403 …__IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available)… member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S14/
DLPC55S14.h13402 …__IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available)… member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S66/
DLPC55S66_cm33_core1.h10185 …__IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available)… member
DLPC55S66_cm33_core0.h10185 …__IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available)… member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S69/
DLPC55S69_cm33_core1.h10184 …__IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available)… member
DLPC55S69_cm33_core0.h10184 …__IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available)… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h14622 …__IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available)… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_cm33.h14622 …__IO uint32_t MEMCTRL; /**< Setup Master to access memory (if available)… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h17628 __IO uint32_t MEMCTRL; /**< Memory Control, offset: 0x10 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h24316 __IO uint32_t MEMCTRL; /**< Memory Control, offset: 0x10 */ member

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