1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_MDM_AP.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_MDM_AP 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_MDM_AP_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_MDM_AP_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- MDM_AP Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup MDM_AP_Peripheral_Access_Layer MDM_AP Peripheral Access Layer 68 * @{ 69 */ 70 71 /** MDM_AP - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t STATUS; /**< MDM_AP status, offset: 0x0 */ 74 __IO uint32_t CONTROL; /**< MDM_AP control, offset: 0x4 */ 75 uint8_t RESERVED_0[56]; 76 __I uint32_t STATUS2; /**< MDM_AP status 2, offset: 0x40 */ 77 __IO uint32_t CONTROL2; /**< MDM_AP Control 2, offset: 0x44 */ 78 uint8_t RESERVED_1[4]; 79 __IO uint32_t CONTROL3; /**< MDM_AP Control 3, offset: 0x4C */ 80 uint8_t RESERVED_2[32]; 81 __IO uint32_t RTU0_CORE_0_IP_DBG; /**< RTU0 core 0 debug, offset: 0x70 */ 82 __IO uint32_t RTU0_CORE_1_IP_DBG; /**< RTU0 core 1 debug, offset: 0x74 */ 83 __IO uint32_t RTU0_CORE_2_IP_DBG; /**< RTU0 core 2 debug, offset: 0x78 */ 84 __IO uint32_t RTU0_CORE_3_IP_DBG; /**< RTU0 core 3 debug, offset: 0x7C */ 85 __IO uint32_t RTU1_CORE_0_IP_DBG; /**< RTU1 core 0 debug, offset: 0x80 */ 86 __IO uint32_t RTU1_CORE_1_IP_DBG; /**< RTU1 core 1 debug, offset: 0x84 */ 87 __IO uint32_t RTU1_CORE_2_IP_DBG; /**< RTU1 core 2 debug, offset: 0x88 */ 88 __IO uint32_t RTU1_CORE_3_IP_DBG; /**< RTU1 core 3 debug, offset: 0x8C */ 89 __IO uint32_t SMU_CORTEX_M33_IP_DBG; /**< Cortex-M33 Core Debug, offset: 0x90 */ 90 __IO uint32_t CE_CORTEX_M33_0_IP_DBG; /**< CE Cortex-M33 Core 0 Debug, offset: 0x94 */ 91 __IO uint32_t CE_CORTEX_M33_1_IP_DBG; /**< CE Cortex-M33 Core 1 Debug, offset: 0x98 */ 92 uint8_t RESERVED_3[4]; 93 __IO uint32_t RTU0_SWTMASK_IP_DBG; /**< RTU0 SWT debug mask register, offset: 0xA0 */ 94 __IO uint32_t RTU1_SWTMASK_IP_DBG; /**< RTU1 SWT debug mask register, offset: 0xA4 */ 95 uint8_t RESERVED_4[8]; 96 __IO uint32_t RTU0_STMMASK_IP_DBG; /**< RTU0 STM debug mask register, offset: 0xB0 */ 97 __IO uint32_t RTU1_STMMASK_IP_DBG; /**< RTU1 STM debug mask register, offset: 0xB4 */ 98 uint8_t RESERVED_5[8]; 99 __IO uint32_t DBGENCNTRL; /**< Debug enable control, offset: 0xC0 */ 100 uint8_t RESERVED_6[4]; 101 __IO uint32_t DBGENCNTRL2; /**< Debug enable control 2, offset: 0xC8 */ 102 uint8_t RESERVED_7[4]; 103 __IO uint32_t DBGENCNTRL3; /**< Debug enable control 3, offset: 0xD0 */ 104 uint8_t RESERVED_8[44]; 105 __IO uint32_t DTS_ENABLE; /**< DTS output enable register, offset: 0x100 */ 106 uint8_t RESERVED_9[12]; 107 __IO uint32_t DTS_STARTUP; /**< DTS startup register, offset: 0x110 */ 108 __IO uint32_t DTS_STARTUP_B; /**< DTS startup register B, offset: 0x114 */ 109 __IO uint32_t DTS_STARTUP_C; /**< DTS startup register C, offset: 0x118 */ 110 __IO uint32_t DTS_STARTUP_D; /**< DTS startup register D, offset: 0x11C */ 111 __IO uint32_t DTS_SEMAPHORE; /**< DTS SEMAPHORE register, offset: 0x120 */ 112 uint8_t RESERVED_10[12]; 113 __IO uint32_t DTS_SEMAPHORE_B; /**< DTS SEMAPHORE_B register, offset: 0x130 */ 114 uint8_t RESERVED_11[12]; 115 __IO uint32_t DTS_SEMAPHORE_C; /**< DTS SEMAPHORE_C register, offset: 0x140 */ 116 uint8_t RESERVED_12[12]; 117 __IO uint32_t DTS_SEMAPHORE_D; /**< DTS SEMAPHORE_D register, offset: 0x150 */ 118 uint8_t RESERVED_13[3240]; 119 __I uint32_t IDR; /**< Identification Register, offset: 0xDFC */ 120 uint8_t RESERVED_14[444]; 121 __I uint32_t DEVARCH; /**< CoreSight Device Architecture Register, offset: 0xFBC */ 122 uint8_t RESERVED_15[12]; 123 __I uint32_t DEVTYPE; /**< CoreSight Device Type Identifier Register, offset: 0xFCC */ 124 __I uint32_t PIDR4; /**< CoreSight Peripheral Identification Register 4, offset: 0xFD0 */ 125 uint8_t RESERVED_16[12]; 126 __I uint32_t PIDR0; /**< CoreSight Peripheral Identification Register 0, offset: 0xFE0 */ 127 __I uint32_t PIDR1; /**< CoreSight Peripheral Identification Register 1, offset: 0xFE4 */ 128 __I uint32_t PIDR2; /**< CoreSight Peripheral Identification Register 2, offset: 0xFE8 */ 129 __I uint32_t PIDR3; /**< CoreSight Peripheral Identification Register 3, offset: 0xFEC */ 130 __I uint32_t CIDR0; /**< CoreSight Component Identification Register 0, offset: 0xFF0 */ 131 __I uint32_t CIDR1; /**< CoreSight Component Identification Register 1, offset: 0xFF4 */ 132 __I uint32_t CIDR2; /**< CoreSight Component Identification Register 2, offset: 0xFF8 */ 133 __I uint32_t CIDR3; /**< CoreSight Component Identification Register 3, offset: 0xFFC */ 134 } MDM_AP_Type, *MDM_AP_MemMapPtr; 135 136 /** Number of instances of the MDM_AP module. */ 137 #define MDM_AP_INSTANCE_COUNT (1u) 138 139 /* MDM_AP - Peripheral instance base addresses */ 140 /** Peripheral MDM_AP base address */ 141 #define IP_MDM_AP_BASE (0x4DC11000u) 142 /** Peripheral MDM_AP base pointer */ 143 #define IP_MDM_AP ((MDM_AP_Type *)IP_MDM_AP_BASE) 144 /** Array initializer of MDM_AP peripheral base addresses */ 145 #define IP_MDM_AP_BASE_ADDRS { IP_MDM_AP_BASE } 146 /** Array initializer of MDM_AP peripheral base pointers */ 147 #define IP_MDM_AP_BASE_PTRS { IP_MDM_AP } 148 149 /* ---------------------------------------------------------------------------- 150 -- MDM_AP Register Masks 151 ---------------------------------------------------------------------------- */ 152 153 /*! 154 * @addtogroup MDM_AP_Register_Masks MDM_AP Register Masks 155 * @{ 156 */ 157 158 /*! @name STATUS - MDM_AP status */ 159 /*! @{ */ 160 161 #define MDM_AP_STATUS_SYSTEM_RESET_MASK (0x4U) 162 #define MDM_AP_STATUS_SYSTEM_RESET_SHIFT (2U) 163 #define MDM_AP_STATUS_SYSTEM_RESET_WIDTH (1U) 164 #define MDM_AP_STATUS_SYSTEM_RESET(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS_SYSTEM_RESET_SHIFT)) & MDM_AP_STATUS_SYSTEM_RESET_MASK) 165 166 #define MDM_AP_STATUS_CSYSPWRUPREQ_MASK (0x40U) 167 #define MDM_AP_STATUS_CSYSPWRUPREQ_SHIFT (6U) 168 #define MDM_AP_STATUS_CSYSPWRUPREQ_WIDTH (1U) 169 #define MDM_AP_STATUS_CSYSPWRUPREQ(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS_CSYSPWRUPREQ_SHIFT)) & MDM_AP_STATUS_CSYSPWRUPREQ_MASK) 170 171 #define MDM_AP_STATUS_CDBGPWRUPREQ_MASK (0x80U) 172 #define MDM_AP_STATUS_CDBGPWRUPREQ_SHIFT (7U) 173 #define MDM_AP_STATUS_CDBGPWRUPREQ_WIDTH (1U) 174 #define MDM_AP_STATUS_CDBGPWRUPREQ(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS_CDBGPWRUPREQ_SHIFT)) & MDM_AP_STATUS_CDBGPWRUPREQ_MASK) 175 176 #define MDM_AP_STATUS_JTAG_ACTIVE_MASK (0x100U) 177 #define MDM_AP_STATUS_JTAG_ACTIVE_SHIFT (8U) 178 #define MDM_AP_STATUS_JTAG_ACTIVE_WIDTH (1U) 179 #define MDM_AP_STATUS_JTAG_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS_JTAG_ACTIVE_SHIFT)) & MDM_AP_STATUS_JTAG_ACTIVE_MASK) 180 181 #define MDM_AP_STATUS_SMU_HALTED_MASK (0x1000U) 182 #define MDM_AP_STATUS_SMU_HALTED_SHIFT (12U) 183 #define MDM_AP_STATUS_SMU_HALTED_WIDTH (1U) 184 #define MDM_AP_STATUS_SMU_HALTED(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS_SMU_HALTED_SHIFT)) & MDM_AP_STATUS_SMU_HALTED_MASK) 185 186 #define MDM_AP_STATUS_CE_A_HALTED_MASK (0x2000U) 187 #define MDM_AP_STATUS_CE_A_HALTED_SHIFT (13U) 188 #define MDM_AP_STATUS_CE_A_HALTED_WIDTH (1U) 189 #define MDM_AP_STATUS_CE_A_HALTED(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS_CE_A_HALTED_SHIFT)) & MDM_AP_STATUS_CE_A_HALTED_MASK) 190 191 #define MDM_AP_STATUS_CE_B_HALTED_MASK (0x4000U) 192 #define MDM_AP_STATUS_CE_B_HALTED_SHIFT (14U) 193 #define MDM_AP_STATUS_CE_B_HALTED_WIDTH (1U) 194 #define MDM_AP_STATUS_CE_B_HALTED(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS_CE_B_HALTED_SHIFT)) & MDM_AP_STATUS_CE_B_HALTED_MASK) 195 196 #define MDM_AP_STATUS_SMU_SLEEPDEEP_MASK (0x10000U) 197 #define MDM_AP_STATUS_SMU_SLEEPDEEP_SHIFT (16U) 198 #define MDM_AP_STATUS_SMU_SLEEPDEEP_WIDTH (1U) 199 #define MDM_AP_STATUS_SMU_SLEEPDEEP(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS_SMU_SLEEPDEEP_SHIFT)) & MDM_AP_STATUS_SMU_SLEEPDEEP_MASK) 200 201 #define MDM_AP_STATUS_CE_A_SLEEPDEEP_MASK (0x20000U) 202 #define MDM_AP_STATUS_CE_A_SLEEPDEEP_SHIFT (17U) 203 #define MDM_AP_STATUS_CE_A_SLEEPDEEP_WIDTH (1U) 204 #define MDM_AP_STATUS_CE_A_SLEEPDEEP(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS_CE_A_SLEEPDEEP_SHIFT)) & MDM_AP_STATUS_CE_A_SLEEPDEEP_MASK) 205 206 #define MDM_AP_STATUS_CE_B_SLEEPDEEP_MASK (0x40000U) 207 #define MDM_AP_STATUS_CE_B_SLEEPDEEP_SHIFT (18U) 208 #define MDM_AP_STATUS_CE_B_SLEEPDEEP_WIDTH (1U) 209 #define MDM_AP_STATUS_CE_B_SLEEPDEEP(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS_CE_B_SLEEPDEEP_SHIFT)) & MDM_AP_STATUS_CE_B_SLEEPDEEP_MASK) 210 211 #define MDM_AP_STATUS_SMU_SLEEPING_MASK (0x100000U) 212 #define MDM_AP_STATUS_SMU_SLEEPING_SHIFT (20U) 213 #define MDM_AP_STATUS_SMU_SLEEPING_WIDTH (1U) 214 #define MDM_AP_STATUS_SMU_SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS_SMU_SLEEPING_SHIFT)) & MDM_AP_STATUS_SMU_SLEEPING_MASK) 215 216 #define MDM_AP_STATUS_CE_A_SLEEPING_MASK (0x200000U) 217 #define MDM_AP_STATUS_CE_A_SLEEPING_SHIFT (21U) 218 #define MDM_AP_STATUS_CE_A_SLEEPING_WIDTH (1U) 219 #define MDM_AP_STATUS_CE_A_SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS_CE_A_SLEEPING_SHIFT)) & MDM_AP_STATUS_CE_A_SLEEPING_MASK) 220 221 #define MDM_AP_STATUS_CE_B_SLEEPING_MASK (0x400000U) 222 #define MDM_AP_STATUS_CE_B_SLEEPING_SHIFT (22U) 223 #define MDM_AP_STATUS_CE_B_SLEEPING_WIDTH (1U) 224 #define MDM_AP_STATUS_CE_B_SLEEPING(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS_CE_B_SLEEPING_SHIFT)) & MDM_AP_STATUS_CE_B_SLEEPING_MASK) 225 226 #define MDM_AP_STATUS_SMU_DBGRSTRTS_MASK (0x10000000U) 227 #define MDM_AP_STATUS_SMU_DBGRSTRTS_SHIFT (28U) 228 #define MDM_AP_STATUS_SMU_DBGRSTRTS_WIDTH (1U) 229 #define MDM_AP_STATUS_SMU_DBGRSTRTS(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS_SMU_DBGRSTRTS_SHIFT)) & MDM_AP_STATUS_SMU_DBGRSTRTS_MASK) 230 231 #define MDM_AP_STATUS_CE_A_DBGRSTRTS_MASK (0x20000000U) 232 #define MDM_AP_STATUS_CE_A_DBGRSTRTS_SHIFT (29U) 233 #define MDM_AP_STATUS_CE_A_DBGRSTRTS_WIDTH (1U) 234 #define MDM_AP_STATUS_CE_A_DBGRSTRTS(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS_CE_A_DBGRSTRTS_SHIFT)) & MDM_AP_STATUS_CE_A_DBGRSTRTS_MASK) 235 236 #define MDM_AP_STATUS_CE_B_DBGRSTRTS_MASK (0x40000000U) 237 #define MDM_AP_STATUS_CE_B_DBGRSTRTS_SHIFT (30U) 238 #define MDM_AP_STATUS_CE_B_DBGRSTRTS_WIDTH (1U) 239 #define MDM_AP_STATUS_CE_B_DBGRSTRTS(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS_CE_B_DBGRSTRTS_SHIFT)) & MDM_AP_STATUS_CE_B_DBGRSTRTS_MASK) 240 /*! @} */ 241 242 /*! @name CONTROL - MDM_AP control */ 243 /*! @{ */ 244 245 #define MDM_AP_CONTROL_ETR_HANDSHAKE_0_MASK (0x40U) 246 #define MDM_AP_CONTROL_ETR_HANDSHAKE_0_SHIFT (6U) 247 #define MDM_AP_CONTROL_ETR_HANDSHAKE_0_WIDTH (1U) 248 #define MDM_AP_CONTROL_ETR_HANDSHAKE_0(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL_ETR_HANDSHAKE_0_SHIFT)) & MDM_AP_CONTROL_ETR_HANDSHAKE_0_MASK) 249 250 #define MDM_AP_CONTROL_ETR_HANDSHAKE_1_MASK (0x80U) 251 #define MDM_AP_CONTROL_ETR_HANDSHAKE_1_SHIFT (7U) 252 #define MDM_AP_CONTROL_ETR_HANDSHAKE_1_WIDTH (1U) 253 #define MDM_AP_CONTROL_ETR_HANDSHAKE_1(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL_ETR_HANDSHAKE_1_SHIFT)) & MDM_AP_CONTROL_ETR_HANDSHAKE_1_MASK) 254 255 #define MDM_AP_CONTROL_SMU_EDBGREQ_MASK (0x100U) 256 #define MDM_AP_CONTROL_SMU_EDBGREQ_SHIFT (8U) 257 #define MDM_AP_CONTROL_SMU_EDBGREQ_WIDTH (1U) 258 #define MDM_AP_CONTROL_SMU_EDBGREQ(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL_SMU_EDBGREQ_SHIFT)) & MDM_AP_CONTROL_SMU_EDBGREQ_MASK) 259 260 #define MDM_AP_CONTROL_COMMS_0_EDBGREQ_MASK (0x200U) 261 #define MDM_AP_CONTROL_COMMS_0_EDBGREQ_SHIFT (9U) 262 #define MDM_AP_CONTROL_COMMS_0_EDBGREQ_WIDTH (1U) 263 #define MDM_AP_CONTROL_COMMS_0_EDBGREQ(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL_COMMS_0_EDBGREQ_SHIFT)) & MDM_AP_CONTROL_COMMS_0_EDBGREQ_MASK) 264 265 #define MDM_AP_CONTROL_COMMS_1_EDBGREQ_MASK (0x400U) 266 #define MDM_AP_CONTROL_COMMS_1_EDBGREQ_SHIFT (10U) 267 #define MDM_AP_CONTROL_COMMS_1_EDBGREQ_WIDTH (1U) 268 #define MDM_AP_CONTROL_COMMS_1_EDBGREQ(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL_COMMS_1_EDBGREQ_SHIFT)) & MDM_AP_CONTROL_COMMS_1_EDBGREQ_MASK) 269 270 #define MDM_AP_CONTROL_DIS_POR_WDOG_MSK_MASK (0x8000U) 271 #define MDM_AP_CONTROL_DIS_POR_WDOG_MSK_SHIFT (15U) 272 #define MDM_AP_CONTROL_DIS_POR_WDOG_MSK_WIDTH (1U) 273 #define MDM_AP_CONTROL_DIS_POR_WDOG_MSK(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL_DIS_POR_WDOG_MSK_SHIFT)) & MDM_AP_CONTROL_DIS_POR_WDOG_MSK_MASK) 274 275 #define MDM_AP_CONTROL_TPIU_OVERRIDE_MASK (0x100000U) 276 #define MDM_AP_CONTROL_TPIU_OVERRIDE_SHIFT (20U) 277 #define MDM_AP_CONTROL_TPIU_OVERRIDE_WIDTH (1U) 278 #define MDM_AP_CONTROL_TPIU_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL_TPIU_OVERRIDE_SHIFT)) & MDM_AP_CONTROL_TPIU_OVERRIDE_MASK) 279 280 #define MDM_AP_CONTROL_ETR_OVERRIDE_SMU_MASK (0x200000U) 281 #define MDM_AP_CONTROL_ETR_OVERRIDE_SMU_SHIFT (21U) 282 #define MDM_AP_CONTROL_ETR_OVERRIDE_SMU_WIDTH (1U) 283 #define MDM_AP_CONTROL_ETR_OVERRIDE_SMU(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL_ETR_OVERRIDE_SMU_SHIFT)) & MDM_AP_CONTROL_ETR_OVERRIDE_SMU_MASK) 284 285 #define MDM_AP_CONTROL_MSK_DBG_FAULT_MASK (0x800000U) 286 #define MDM_AP_CONTROL_MSK_DBG_FAULT_SHIFT (23U) 287 #define MDM_AP_CONTROL_MSK_DBG_FAULT_WIDTH (1U) 288 #define MDM_AP_CONTROL_MSK_DBG_FAULT(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL_MSK_DBG_FAULT_SHIFT)) & MDM_AP_CONTROL_MSK_DBG_FAULT_MASK) 289 290 #define MDM_AP_CONTROL_MSK_FCCU_RST_TRIGGER_MASK (0x1000000U) 291 #define MDM_AP_CONTROL_MSK_FCCU_RST_TRIGGER_SHIFT (24U) 292 #define MDM_AP_CONTROL_MSK_FCCU_RST_TRIGGER_WIDTH (1U) 293 #define MDM_AP_CONTROL_MSK_FCCU_RST_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL_MSK_FCCU_RST_TRIGGER_SHIFT)) & MDM_AP_CONTROL_MSK_FCCU_RST_TRIGGER_MASK) 294 295 #define MDM_AP_CONTROL_SMU_DBGRSTRT_MASK (0x10000000U) 296 #define MDM_AP_CONTROL_SMU_DBGRSTRT_SHIFT (28U) 297 #define MDM_AP_CONTROL_SMU_DBGRSTRT_WIDTH (1U) 298 #define MDM_AP_CONTROL_SMU_DBGRSTRT(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL_SMU_DBGRSTRT_SHIFT)) & MDM_AP_CONTROL_SMU_DBGRSTRT_MASK) 299 300 #define MDM_AP_CONTROL_CE_A_DBGRSTRT_MASK (0x20000000U) 301 #define MDM_AP_CONTROL_CE_A_DBGRSTRT_SHIFT (29U) 302 #define MDM_AP_CONTROL_CE_A_DBGRSTRT_WIDTH (1U) 303 #define MDM_AP_CONTROL_CE_A_DBGRSTRT(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL_CE_A_DBGRSTRT_SHIFT)) & MDM_AP_CONTROL_CE_A_DBGRSTRT_MASK) 304 305 #define MDM_AP_CONTROL_CE_B_DBGRSTRT_MASK (0x40000000U) 306 #define MDM_AP_CONTROL_CE_B_DBGRSTRT_SHIFT (30U) 307 #define MDM_AP_CONTROL_CE_B_DBGRSTRT_WIDTH (1U) 308 #define MDM_AP_CONTROL_CE_B_DBGRSTRT(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL_CE_B_DBGRSTRT_SHIFT)) & MDM_AP_CONTROL_CE_B_DBGRSTRT_MASK) 309 /*! @} */ 310 311 /*! @name STATUS2 - MDM_AP status 2 */ 312 /*! @{ */ 313 314 #define MDM_AP_STATUS2_CR52_RTU0_0_DBGMODE_MASK (0x1U) 315 #define MDM_AP_STATUS2_CR52_RTU0_0_DBGMODE_SHIFT (0U) 316 #define MDM_AP_STATUS2_CR52_RTU0_0_DBGMODE_WIDTH (1U) 317 #define MDM_AP_STATUS2_CR52_RTU0_0_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU0_0_DBGMODE_SHIFT)) & MDM_AP_STATUS2_CR52_RTU0_0_DBGMODE_MASK) 318 319 #define MDM_AP_STATUS2_CR52_RTU0_1_DBGMODE_MASK (0x2U) 320 #define MDM_AP_STATUS2_CR52_RTU0_1_DBGMODE_SHIFT (1U) 321 #define MDM_AP_STATUS2_CR52_RTU0_1_DBGMODE_WIDTH (1U) 322 #define MDM_AP_STATUS2_CR52_RTU0_1_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU0_1_DBGMODE_SHIFT)) & MDM_AP_STATUS2_CR52_RTU0_1_DBGMODE_MASK) 323 324 #define MDM_AP_STATUS2_CR52_RTU0_2_DBGMODE_MASK (0x4U) 325 #define MDM_AP_STATUS2_CR52_RTU0_2_DBGMODE_SHIFT (2U) 326 #define MDM_AP_STATUS2_CR52_RTU0_2_DBGMODE_WIDTH (1U) 327 #define MDM_AP_STATUS2_CR52_RTU0_2_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU0_2_DBGMODE_SHIFT)) & MDM_AP_STATUS2_CR52_RTU0_2_DBGMODE_MASK) 328 329 #define MDM_AP_STATUS2_CR52_RTU0_3_DBGMODE_MASK (0x8U) 330 #define MDM_AP_STATUS2_CR52_RTU0_3_DBGMODE_SHIFT (3U) 331 #define MDM_AP_STATUS2_CR52_RTU0_3_DBGMODE_WIDTH (1U) 332 #define MDM_AP_STATUS2_CR52_RTU0_3_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU0_3_DBGMODE_SHIFT)) & MDM_AP_STATUS2_CR52_RTU0_3_DBGMODE_MASK) 333 334 #define MDM_AP_STATUS2_CR52_RTU0_0_WFI_MASK (0x10U) 335 #define MDM_AP_STATUS2_CR52_RTU0_0_WFI_SHIFT (4U) 336 #define MDM_AP_STATUS2_CR52_RTU0_0_WFI_WIDTH (1U) 337 #define MDM_AP_STATUS2_CR52_RTU0_0_WFI(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU0_0_WFI_SHIFT)) & MDM_AP_STATUS2_CR52_RTU0_0_WFI_MASK) 338 339 #define MDM_AP_STATUS2_CR52_RTU0_1_WFI_MASK (0x20U) 340 #define MDM_AP_STATUS2_CR52_RTU0_1_WFI_SHIFT (5U) 341 #define MDM_AP_STATUS2_CR52_RTU0_1_WFI_WIDTH (1U) 342 #define MDM_AP_STATUS2_CR52_RTU0_1_WFI(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU0_1_WFI_SHIFT)) & MDM_AP_STATUS2_CR52_RTU0_1_WFI_MASK) 343 344 #define MDM_AP_STATUS2_CR52_RTU0_2_WFI_MASK (0x40U) 345 #define MDM_AP_STATUS2_CR52_RTU0_2_WFI_SHIFT (6U) 346 #define MDM_AP_STATUS2_CR52_RTU0_2_WFI_WIDTH (1U) 347 #define MDM_AP_STATUS2_CR52_RTU0_2_WFI(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU0_2_WFI_SHIFT)) & MDM_AP_STATUS2_CR52_RTU0_2_WFI_MASK) 348 349 #define MDM_AP_STATUS2_CR52_RTU0_3_WFI_MASK (0x80U) 350 #define MDM_AP_STATUS2_CR52_RTU0_3_WFI_SHIFT (7U) 351 #define MDM_AP_STATUS2_CR52_RTU0_3_WFI_WIDTH (1U) 352 #define MDM_AP_STATUS2_CR52_RTU0_3_WFI(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU0_3_WFI_SHIFT)) & MDM_AP_STATUS2_CR52_RTU0_3_WFI_MASK) 353 354 #define MDM_AP_STATUS2_CR52_RTU0_0_WFE_MASK (0x100U) 355 #define MDM_AP_STATUS2_CR52_RTU0_0_WFE_SHIFT (8U) 356 #define MDM_AP_STATUS2_CR52_RTU0_0_WFE_WIDTH (1U) 357 #define MDM_AP_STATUS2_CR52_RTU0_0_WFE(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU0_0_WFE_SHIFT)) & MDM_AP_STATUS2_CR52_RTU0_0_WFE_MASK) 358 359 #define MDM_AP_STATUS2_CR52_RTU0_1_WFE_MASK (0x200U) 360 #define MDM_AP_STATUS2_CR52_RTU0_1_WFE_SHIFT (9U) 361 #define MDM_AP_STATUS2_CR52_RTU0_1_WFE_WIDTH (1U) 362 #define MDM_AP_STATUS2_CR52_RTU0_1_WFE(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU0_1_WFE_SHIFT)) & MDM_AP_STATUS2_CR52_RTU0_1_WFE_MASK) 363 364 #define MDM_AP_STATUS2_CR52_RTU0_2_WFE_MASK (0x400U) 365 #define MDM_AP_STATUS2_CR52_RTU0_2_WFE_SHIFT (10U) 366 #define MDM_AP_STATUS2_CR52_RTU0_2_WFE_WIDTH (1U) 367 #define MDM_AP_STATUS2_CR52_RTU0_2_WFE(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU0_2_WFE_SHIFT)) & MDM_AP_STATUS2_CR52_RTU0_2_WFE_MASK) 368 369 #define MDM_AP_STATUS2_CR52_RTU0_3_WFE_MASK (0x800U) 370 #define MDM_AP_STATUS2_CR52_RTU0_3_WFE_SHIFT (11U) 371 #define MDM_AP_STATUS2_CR52_RTU0_3_WFE_WIDTH (1U) 372 #define MDM_AP_STATUS2_CR52_RTU0_3_WFE(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU0_3_WFE_SHIFT)) & MDM_AP_STATUS2_CR52_RTU0_3_WFE_MASK) 373 374 #define MDM_AP_STATUS2_CR52_RTU1_0_DBGMODE_MASK (0x10000U) 375 #define MDM_AP_STATUS2_CR52_RTU1_0_DBGMODE_SHIFT (16U) 376 #define MDM_AP_STATUS2_CR52_RTU1_0_DBGMODE_WIDTH (1U) 377 #define MDM_AP_STATUS2_CR52_RTU1_0_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU1_0_DBGMODE_SHIFT)) & MDM_AP_STATUS2_CR52_RTU1_0_DBGMODE_MASK) 378 379 #define MDM_AP_STATUS2_CR52_RTU1_1_DBGMODE_MASK (0x20000U) 380 #define MDM_AP_STATUS2_CR52_RTU1_1_DBGMODE_SHIFT (17U) 381 #define MDM_AP_STATUS2_CR52_RTU1_1_DBGMODE_WIDTH (1U) 382 #define MDM_AP_STATUS2_CR52_RTU1_1_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU1_1_DBGMODE_SHIFT)) & MDM_AP_STATUS2_CR52_RTU1_1_DBGMODE_MASK) 383 384 #define MDM_AP_STATUS2_CR52_RTU1_2_DBGMODE_MASK (0x40000U) 385 #define MDM_AP_STATUS2_CR52_RTU1_2_DBGMODE_SHIFT (18U) 386 #define MDM_AP_STATUS2_CR52_RTU1_2_DBGMODE_WIDTH (1U) 387 #define MDM_AP_STATUS2_CR52_RTU1_2_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU1_2_DBGMODE_SHIFT)) & MDM_AP_STATUS2_CR52_RTU1_2_DBGMODE_MASK) 388 389 #define MDM_AP_STATUS2_CR52_RTU1_3_DBGMODE_MASK (0x80000U) 390 #define MDM_AP_STATUS2_CR52_RTU1_3_DBGMODE_SHIFT (19U) 391 #define MDM_AP_STATUS2_CR52_RTU1_3_DBGMODE_WIDTH (1U) 392 #define MDM_AP_STATUS2_CR52_RTU1_3_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU1_3_DBGMODE_SHIFT)) & MDM_AP_STATUS2_CR52_RTU1_3_DBGMODE_MASK) 393 394 #define MDM_AP_STATUS2_CR52_RTU1_0_WFI_MASK (0x100000U) 395 #define MDM_AP_STATUS2_CR52_RTU1_0_WFI_SHIFT (20U) 396 #define MDM_AP_STATUS2_CR52_RTU1_0_WFI_WIDTH (1U) 397 #define MDM_AP_STATUS2_CR52_RTU1_0_WFI(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU1_0_WFI_SHIFT)) & MDM_AP_STATUS2_CR52_RTU1_0_WFI_MASK) 398 399 #define MDM_AP_STATUS2_CR52_RTU1_1_WFI_MASK (0x200000U) 400 #define MDM_AP_STATUS2_CR52_RTU1_1_WFI_SHIFT (21U) 401 #define MDM_AP_STATUS2_CR52_RTU1_1_WFI_WIDTH (1U) 402 #define MDM_AP_STATUS2_CR52_RTU1_1_WFI(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU1_1_WFI_SHIFT)) & MDM_AP_STATUS2_CR52_RTU1_1_WFI_MASK) 403 404 #define MDM_AP_STATUS2_CR52_RTU1_2_WFI_MASK (0x400000U) 405 #define MDM_AP_STATUS2_CR52_RTU1_2_WFI_SHIFT (22U) 406 #define MDM_AP_STATUS2_CR52_RTU1_2_WFI_WIDTH (1U) 407 #define MDM_AP_STATUS2_CR52_RTU1_2_WFI(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU1_2_WFI_SHIFT)) & MDM_AP_STATUS2_CR52_RTU1_2_WFI_MASK) 408 409 #define MDM_AP_STATUS2_CR52_RTU1_3_WFI_MASK (0x800000U) 410 #define MDM_AP_STATUS2_CR52_RTU1_3_WFI_SHIFT (23U) 411 #define MDM_AP_STATUS2_CR52_RTU1_3_WFI_WIDTH (1U) 412 #define MDM_AP_STATUS2_CR52_RTU1_3_WFI(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU1_3_WFI_SHIFT)) & MDM_AP_STATUS2_CR52_RTU1_3_WFI_MASK) 413 414 #define MDM_AP_STATUS2_CR52_RTU1_0_WFE_MASK (0x1000000U) 415 #define MDM_AP_STATUS2_CR52_RTU1_0_WFE_SHIFT (24U) 416 #define MDM_AP_STATUS2_CR52_RTU1_0_WFE_WIDTH (1U) 417 #define MDM_AP_STATUS2_CR52_RTU1_0_WFE(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU1_0_WFE_SHIFT)) & MDM_AP_STATUS2_CR52_RTU1_0_WFE_MASK) 418 419 #define MDM_AP_STATUS2_CR52_RTU1_1_WFE_MASK (0x2000000U) 420 #define MDM_AP_STATUS2_CR52_RTU1_1_WFE_SHIFT (25U) 421 #define MDM_AP_STATUS2_CR52_RTU1_1_WFE_WIDTH (1U) 422 #define MDM_AP_STATUS2_CR52_RTU1_1_WFE(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU1_1_WFE_SHIFT)) & MDM_AP_STATUS2_CR52_RTU1_1_WFE_MASK) 423 424 #define MDM_AP_STATUS2_CR52_RTU1_2_WFE_MASK (0x4000000U) 425 #define MDM_AP_STATUS2_CR52_RTU1_2_WFE_SHIFT (26U) 426 #define MDM_AP_STATUS2_CR52_RTU1_2_WFE_WIDTH (1U) 427 #define MDM_AP_STATUS2_CR52_RTU1_2_WFE(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU1_2_WFE_SHIFT)) & MDM_AP_STATUS2_CR52_RTU1_2_WFE_MASK) 428 429 #define MDM_AP_STATUS2_CR52_RTU1_3_WFE_MASK (0x8000000U) 430 #define MDM_AP_STATUS2_CR52_RTU1_3_WFE_SHIFT (27U) 431 #define MDM_AP_STATUS2_CR52_RTU1_3_WFE_WIDTH (1U) 432 #define MDM_AP_STATUS2_CR52_RTU1_3_WFE(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_STATUS2_CR52_RTU1_3_WFE_SHIFT)) & MDM_AP_STATUS2_CR52_RTU1_3_WFE_MASK) 433 /*! @} */ 434 435 /*! @name CONTROL2 - MDM_AP Control 2 */ 436 /*! @{ */ 437 438 #define MDM_AP_CONTROL2_RTU0_ETR_HANDSHAKE_0_MASK (0x40U) 439 #define MDM_AP_CONTROL2_RTU0_ETR_HANDSHAKE_0_SHIFT (6U) 440 #define MDM_AP_CONTROL2_RTU0_ETR_HANDSHAKE_0_WIDTH (1U) 441 #define MDM_AP_CONTROL2_RTU0_ETR_HANDSHAKE_0(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL2_RTU0_ETR_HANDSHAKE_0_SHIFT)) & MDM_AP_CONTROL2_RTU0_ETR_HANDSHAKE_0_MASK) 442 443 #define MDM_AP_CONTROL2_RTU0_ETR_HANDSHAKE_1_MASK (0x80U) 444 #define MDM_AP_CONTROL2_RTU0_ETR_HANDSHAKE_1_SHIFT (7U) 445 #define MDM_AP_CONTROL2_RTU0_ETR_HANDSHAKE_1_WIDTH (1U) 446 #define MDM_AP_CONTROL2_RTU0_ETR_HANDSHAKE_1(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL2_RTU0_ETR_HANDSHAKE_1_SHIFT)) & MDM_AP_CONTROL2_RTU0_ETR_HANDSHAKE_1_MASK) 447 448 #define MDM_AP_CONTROL2_CR52_RTU0_0_EDBGREQ_MASK (0x10000U) 449 #define MDM_AP_CONTROL2_CR52_RTU0_0_EDBGREQ_SHIFT (16U) 450 #define MDM_AP_CONTROL2_CR52_RTU0_0_EDBGREQ_WIDTH (1U) 451 #define MDM_AP_CONTROL2_CR52_RTU0_0_EDBGREQ(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL2_CR52_RTU0_0_EDBGREQ_SHIFT)) & MDM_AP_CONTROL2_CR52_RTU0_0_EDBGREQ_MASK) 452 453 #define MDM_AP_CONTROL2_CR52_RTU0_1_EDBGREQ_MASK (0x20000U) 454 #define MDM_AP_CONTROL2_CR52_RTU0_1_EDBGREQ_SHIFT (17U) 455 #define MDM_AP_CONTROL2_CR52_RTU0_1_EDBGREQ_WIDTH (1U) 456 #define MDM_AP_CONTROL2_CR52_RTU0_1_EDBGREQ(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL2_CR52_RTU0_1_EDBGREQ_SHIFT)) & MDM_AP_CONTROL2_CR52_RTU0_1_EDBGREQ_MASK) 457 458 #define MDM_AP_CONTROL2_CR52_RTU0_2_EDBGREQ_MASK (0x40000U) 459 #define MDM_AP_CONTROL2_CR52_RTU0_2_EDBGREQ_SHIFT (18U) 460 #define MDM_AP_CONTROL2_CR52_RTU0_2_EDBGREQ_WIDTH (1U) 461 #define MDM_AP_CONTROL2_CR52_RTU0_2_EDBGREQ(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL2_CR52_RTU0_2_EDBGREQ_SHIFT)) & MDM_AP_CONTROL2_CR52_RTU0_2_EDBGREQ_MASK) 462 463 #define MDM_AP_CONTROL2_CR52_RTU0_3_EDBGREQ_MASK (0x80000U) 464 #define MDM_AP_CONTROL2_CR52_RTU0_3_EDBGREQ_SHIFT (19U) 465 #define MDM_AP_CONTROL2_CR52_RTU0_3_EDBGREQ_WIDTH (1U) 466 #define MDM_AP_CONTROL2_CR52_RTU0_3_EDBGREQ(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL2_CR52_RTU0_3_EDBGREQ_SHIFT)) & MDM_AP_CONTROL2_CR52_RTU0_3_EDBGREQ_MASK) 467 /*! @} */ 468 469 /*! @name CONTROL3 - MDM_AP Control 3 */ 470 /*! @{ */ 471 472 #define MDM_AP_CONTROL3_RTU1_ETR_HANDSHAKE_0_MASK (0x40U) 473 #define MDM_AP_CONTROL3_RTU1_ETR_HANDSHAKE_0_SHIFT (6U) 474 #define MDM_AP_CONTROL3_RTU1_ETR_HANDSHAKE_0_WIDTH (1U) 475 #define MDM_AP_CONTROL3_RTU1_ETR_HANDSHAKE_0(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL3_RTU1_ETR_HANDSHAKE_0_SHIFT)) & MDM_AP_CONTROL3_RTU1_ETR_HANDSHAKE_0_MASK) 476 477 #define MDM_AP_CONTROL3_RTU1_ETR_HANDSHAKE_1_MASK (0x80U) 478 #define MDM_AP_CONTROL3_RTU1_ETR_HANDSHAKE_1_SHIFT (7U) 479 #define MDM_AP_CONTROL3_RTU1_ETR_HANDSHAKE_1_WIDTH (1U) 480 #define MDM_AP_CONTROL3_RTU1_ETR_HANDSHAKE_1(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL3_RTU1_ETR_HANDSHAKE_1_SHIFT)) & MDM_AP_CONTROL3_RTU1_ETR_HANDSHAKE_1_MASK) 481 482 #define MDM_AP_CONTROL3_CR52_RTU1_0_EDBGREQ_MASK (0x10000U) 483 #define MDM_AP_CONTROL3_CR52_RTU1_0_EDBGREQ_SHIFT (16U) 484 #define MDM_AP_CONTROL3_CR52_RTU1_0_EDBGREQ_WIDTH (1U) 485 #define MDM_AP_CONTROL3_CR52_RTU1_0_EDBGREQ(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL3_CR52_RTU1_0_EDBGREQ_SHIFT)) & MDM_AP_CONTROL3_CR52_RTU1_0_EDBGREQ_MASK) 486 487 #define MDM_AP_CONTROL3_CR52_RTU1_1_EDBGREQ_MASK (0x20000U) 488 #define MDM_AP_CONTROL3_CR52_RTU1_1_EDBGREQ_SHIFT (17U) 489 #define MDM_AP_CONTROL3_CR52_RTU1_1_EDBGREQ_WIDTH (1U) 490 #define MDM_AP_CONTROL3_CR52_RTU1_1_EDBGREQ(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL3_CR52_RTU1_1_EDBGREQ_SHIFT)) & MDM_AP_CONTROL3_CR52_RTU1_1_EDBGREQ_MASK) 491 492 #define MDM_AP_CONTROL3_CR52_RTU1_2_EDBGREQ_MASK (0x40000U) 493 #define MDM_AP_CONTROL3_CR52_RTU1_2_EDBGREQ_SHIFT (18U) 494 #define MDM_AP_CONTROL3_CR52_RTU1_2_EDBGREQ_WIDTH (1U) 495 #define MDM_AP_CONTROL3_CR52_RTU1_2_EDBGREQ(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL3_CR52_RTU1_2_EDBGREQ_SHIFT)) & MDM_AP_CONTROL3_CR52_RTU1_2_EDBGREQ_MASK) 496 497 #define MDM_AP_CONTROL3_CR52_RTU1_3_EDBGREQ_MASK (0x80000U) 498 #define MDM_AP_CONTROL3_CR52_RTU1_3_EDBGREQ_SHIFT (19U) 499 #define MDM_AP_CONTROL3_CR52_RTU1_3_EDBGREQ_WIDTH (1U) 500 #define MDM_AP_CONTROL3_CR52_RTU1_3_EDBGREQ(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CONTROL3_CR52_RTU1_3_EDBGREQ_SHIFT)) & MDM_AP_CONTROL3_CR52_RTU1_3_EDBGREQ_MASK) 501 /*! @} */ 502 503 /*! @name RTU0_CORE_0_IP_DBG - RTU0 core 0 debug */ 504 /*! @{ */ 505 506 #define MDM_AP_RTU0_CORE_0_IP_DBG_RTU0_0_IP_DBGDIS_MASK (0x1U) 507 #define MDM_AP_RTU0_CORE_0_IP_DBG_RTU0_0_IP_DBGDIS_SHIFT (0U) 508 #define MDM_AP_RTU0_CORE_0_IP_DBG_RTU0_0_IP_DBGDIS_WIDTH (1U) 509 #define MDM_AP_RTU0_CORE_0_IP_DBG_RTU0_0_IP_DBGDIS(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU0_CORE_0_IP_DBG_RTU0_0_IP_DBGDIS_SHIFT)) & MDM_AP_RTU0_CORE_0_IP_DBG_RTU0_0_IP_DBGDIS_MASK) 510 /*! @} */ 511 512 /*! @name RTU0_CORE_1_IP_DBG - RTU0 core 1 debug */ 513 /*! @{ */ 514 515 #define MDM_AP_RTU0_CORE_1_IP_DBG_RTU0_1_IP_DBGDIS_MASK (0x1U) 516 #define MDM_AP_RTU0_CORE_1_IP_DBG_RTU0_1_IP_DBGDIS_SHIFT (0U) 517 #define MDM_AP_RTU0_CORE_1_IP_DBG_RTU0_1_IP_DBGDIS_WIDTH (1U) 518 #define MDM_AP_RTU0_CORE_1_IP_DBG_RTU0_1_IP_DBGDIS(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU0_CORE_1_IP_DBG_RTU0_1_IP_DBGDIS_SHIFT)) & MDM_AP_RTU0_CORE_1_IP_DBG_RTU0_1_IP_DBGDIS_MASK) 519 /*! @} */ 520 521 /*! @name RTU0_CORE_2_IP_DBG - RTU0 core 2 debug */ 522 /*! @{ */ 523 524 #define MDM_AP_RTU0_CORE_2_IP_DBG_RTU0_2_IP_DBGDIS_MASK (0x1U) 525 #define MDM_AP_RTU0_CORE_2_IP_DBG_RTU0_2_IP_DBGDIS_SHIFT (0U) 526 #define MDM_AP_RTU0_CORE_2_IP_DBG_RTU0_2_IP_DBGDIS_WIDTH (1U) 527 #define MDM_AP_RTU0_CORE_2_IP_DBG_RTU0_2_IP_DBGDIS(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU0_CORE_2_IP_DBG_RTU0_2_IP_DBGDIS_SHIFT)) & MDM_AP_RTU0_CORE_2_IP_DBG_RTU0_2_IP_DBGDIS_MASK) 528 /*! @} */ 529 530 /*! @name RTU0_CORE_3_IP_DBG - RTU0 core 3 debug */ 531 /*! @{ */ 532 533 #define MDM_AP_RTU0_CORE_3_IP_DBG_RTU0_3_IP_DBGDIS_MASK (0x1U) 534 #define MDM_AP_RTU0_CORE_3_IP_DBG_RTU0_3_IP_DBGDIS_SHIFT (0U) 535 #define MDM_AP_RTU0_CORE_3_IP_DBG_RTU0_3_IP_DBGDIS_WIDTH (1U) 536 #define MDM_AP_RTU0_CORE_3_IP_DBG_RTU0_3_IP_DBGDIS(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU0_CORE_3_IP_DBG_RTU0_3_IP_DBGDIS_SHIFT)) & MDM_AP_RTU0_CORE_3_IP_DBG_RTU0_3_IP_DBGDIS_MASK) 537 /*! @} */ 538 539 /*! @name RTU1_CORE_0_IP_DBG - RTU1 core 0 debug */ 540 /*! @{ */ 541 542 #define MDM_AP_RTU1_CORE_0_IP_DBG_RTU1_0_IP_DBGDIS_MASK (0x1U) 543 #define MDM_AP_RTU1_CORE_0_IP_DBG_RTU1_0_IP_DBGDIS_SHIFT (0U) 544 #define MDM_AP_RTU1_CORE_0_IP_DBG_RTU1_0_IP_DBGDIS_WIDTH (1U) 545 #define MDM_AP_RTU1_CORE_0_IP_DBG_RTU1_0_IP_DBGDIS(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU1_CORE_0_IP_DBG_RTU1_0_IP_DBGDIS_SHIFT)) & MDM_AP_RTU1_CORE_0_IP_DBG_RTU1_0_IP_DBGDIS_MASK) 546 /*! @} */ 547 548 /*! @name RTU1_CORE_1_IP_DBG - RTU1 core 1 debug */ 549 /*! @{ */ 550 551 #define MDM_AP_RTU1_CORE_1_IP_DBG_RTU1_1_IP_DBGDIS_MASK (0x1U) 552 #define MDM_AP_RTU1_CORE_1_IP_DBG_RTU1_1_IP_DBGDIS_SHIFT (0U) 553 #define MDM_AP_RTU1_CORE_1_IP_DBG_RTU1_1_IP_DBGDIS_WIDTH (1U) 554 #define MDM_AP_RTU1_CORE_1_IP_DBG_RTU1_1_IP_DBGDIS(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU1_CORE_1_IP_DBG_RTU1_1_IP_DBGDIS_SHIFT)) & MDM_AP_RTU1_CORE_1_IP_DBG_RTU1_1_IP_DBGDIS_MASK) 555 /*! @} */ 556 557 /*! @name RTU1_CORE_2_IP_DBG - RTU1 core 2 debug */ 558 /*! @{ */ 559 560 #define MDM_AP_RTU1_CORE_2_IP_DBG_RTU1_2_IP_DBGDIS_MASK (0x1U) 561 #define MDM_AP_RTU1_CORE_2_IP_DBG_RTU1_2_IP_DBGDIS_SHIFT (0U) 562 #define MDM_AP_RTU1_CORE_2_IP_DBG_RTU1_2_IP_DBGDIS_WIDTH (1U) 563 #define MDM_AP_RTU1_CORE_2_IP_DBG_RTU1_2_IP_DBGDIS(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU1_CORE_2_IP_DBG_RTU1_2_IP_DBGDIS_SHIFT)) & MDM_AP_RTU1_CORE_2_IP_DBG_RTU1_2_IP_DBGDIS_MASK) 564 /*! @} */ 565 566 /*! @name RTU1_CORE_3_IP_DBG - RTU1 core 3 debug */ 567 /*! @{ */ 568 569 #define MDM_AP_RTU1_CORE_3_IP_DBG_RTU1_3_IP_DBGDIS_MASK (0x1U) 570 #define MDM_AP_RTU1_CORE_3_IP_DBG_RTU1_3_IP_DBGDIS_SHIFT (0U) 571 #define MDM_AP_RTU1_CORE_3_IP_DBG_RTU1_3_IP_DBGDIS_WIDTH (1U) 572 #define MDM_AP_RTU1_CORE_3_IP_DBG_RTU1_3_IP_DBGDIS(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU1_CORE_3_IP_DBG_RTU1_3_IP_DBGDIS_SHIFT)) & MDM_AP_RTU1_CORE_3_IP_DBG_RTU1_3_IP_DBGDIS_MASK) 573 /*! @} */ 574 575 /*! @name SMU_CORTEX_M33_IP_DBG - Cortex-M33 Core Debug */ 576 /*! @{ */ 577 578 #define MDM_AP_SMU_CORTEX_M33_IP_DBG_CM33_SMU_IP_DBGDIS_MASK (0x1U) 579 #define MDM_AP_SMU_CORTEX_M33_IP_DBG_CM33_SMU_IP_DBGDIS_SHIFT (0U) 580 #define MDM_AP_SMU_CORTEX_M33_IP_DBG_CM33_SMU_IP_DBGDIS_WIDTH (1U) 581 #define MDM_AP_SMU_CORTEX_M33_IP_DBG_CM33_SMU_IP_DBGDIS(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_SMU_CORTEX_M33_IP_DBG_CM33_SMU_IP_DBGDIS_SHIFT)) & MDM_AP_SMU_CORTEX_M33_IP_DBG_CM33_SMU_IP_DBGDIS_MASK) 582 /*! @} */ 583 584 /*! @name CE_CORTEX_M33_0_IP_DBG - CE Cortex-M33 Core 0 Debug */ 585 /*! @{ */ 586 587 #define MDM_AP_CE_CORTEX_M33_0_IP_DBG_CE_CM33_0_IP_DBGDIS_MASK (0x1U) 588 #define MDM_AP_CE_CORTEX_M33_0_IP_DBG_CE_CM33_0_IP_DBGDIS_SHIFT (0U) 589 #define MDM_AP_CE_CORTEX_M33_0_IP_DBG_CE_CM33_0_IP_DBGDIS_WIDTH (1U) 590 #define MDM_AP_CE_CORTEX_M33_0_IP_DBG_CE_CM33_0_IP_DBGDIS(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CE_CORTEX_M33_0_IP_DBG_CE_CM33_0_IP_DBGDIS_SHIFT)) & MDM_AP_CE_CORTEX_M33_0_IP_DBG_CE_CM33_0_IP_DBGDIS_MASK) 591 /*! @} */ 592 593 /*! @name CE_CORTEX_M33_1_IP_DBG - CE Cortex-M33 Core 1 Debug */ 594 /*! @{ */ 595 596 #define MDM_AP_CE_CORTEX_M33_1_IP_DBG_CE_CM33_1_IP_DBGDIS_MASK (0x1U) 597 #define MDM_AP_CE_CORTEX_M33_1_IP_DBG_CE_CM33_1_IP_DBGDIS_SHIFT (0U) 598 #define MDM_AP_CE_CORTEX_M33_1_IP_DBG_CE_CM33_1_IP_DBGDIS_WIDTH (1U) 599 #define MDM_AP_CE_CORTEX_M33_1_IP_DBG_CE_CM33_1_IP_DBGDIS(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CE_CORTEX_M33_1_IP_DBG_CE_CM33_1_IP_DBGDIS_SHIFT)) & MDM_AP_CE_CORTEX_M33_1_IP_DBG_CE_CM33_1_IP_DBGDIS_MASK) 600 /*! @} */ 601 602 /*! @name RTU0_SWTMASK_IP_DBG - RTU0 SWT debug mask register */ 603 /*! @{ */ 604 605 #define MDM_AP_RTU0_SWTMASK_IP_DBG_SWT0_MASK_DBG_MASK (0x1U) 606 #define MDM_AP_RTU0_SWTMASK_IP_DBG_SWT0_MASK_DBG_SHIFT (0U) 607 #define MDM_AP_RTU0_SWTMASK_IP_DBG_SWT0_MASK_DBG_WIDTH (1U) 608 #define MDM_AP_RTU0_SWTMASK_IP_DBG_SWT0_MASK_DBG(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU0_SWTMASK_IP_DBG_SWT0_MASK_DBG_SHIFT)) & MDM_AP_RTU0_SWTMASK_IP_DBG_SWT0_MASK_DBG_MASK) 609 610 #define MDM_AP_RTU0_SWTMASK_IP_DBG_SWT1_MASK_DBG_MASK (0x2U) 611 #define MDM_AP_RTU0_SWTMASK_IP_DBG_SWT1_MASK_DBG_SHIFT (1U) 612 #define MDM_AP_RTU0_SWTMASK_IP_DBG_SWT1_MASK_DBG_WIDTH (1U) 613 #define MDM_AP_RTU0_SWTMASK_IP_DBG_SWT1_MASK_DBG(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU0_SWTMASK_IP_DBG_SWT1_MASK_DBG_SHIFT)) & MDM_AP_RTU0_SWTMASK_IP_DBG_SWT1_MASK_DBG_MASK) 614 615 #define MDM_AP_RTU0_SWTMASK_IP_DBG_SWT2_MASK_DBG_MASK (0x4U) 616 #define MDM_AP_RTU0_SWTMASK_IP_DBG_SWT2_MASK_DBG_SHIFT (2U) 617 #define MDM_AP_RTU0_SWTMASK_IP_DBG_SWT2_MASK_DBG_WIDTH (1U) 618 #define MDM_AP_RTU0_SWTMASK_IP_DBG_SWT2_MASK_DBG(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU0_SWTMASK_IP_DBG_SWT2_MASK_DBG_SHIFT)) & MDM_AP_RTU0_SWTMASK_IP_DBG_SWT2_MASK_DBG_MASK) 619 620 #define MDM_AP_RTU0_SWTMASK_IP_DBG_SWT3_MASK_DBG_MASK (0x8U) 621 #define MDM_AP_RTU0_SWTMASK_IP_DBG_SWT3_MASK_DBG_SHIFT (3U) 622 #define MDM_AP_RTU0_SWTMASK_IP_DBG_SWT3_MASK_DBG_WIDTH (1U) 623 #define MDM_AP_RTU0_SWTMASK_IP_DBG_SWT3_MASK_DBG(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU0_SWTMASK_IP_DBG_SWT3_MASK_DBG_SHIFT)) & MDM_AP_RTU0_SWTMASK_IP_DBG_SWT3_MASK_DBG_MASK) 624 625 #define MDM_AP_RTU0_SWTMASK_IP_DBG_SWT4_MASK_DBG_MASK (0x10U) 626 #define MDM_AP_RTU0_SWTMASK_IP_DBG_SWT4_MASK_DBG_SHIFT (4U) 627 #define MDM_AP_RTU0_SWTMASK_IP_DBG_SWT4_MASK_DBG_WIDTH (1U) 628 #define MDM_AP_RTU0_SWTMASK_IP_DBG_SWT4_MASK_DBG(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU0_SWTMASK_IP_DBG_SWT4_MASK_DBG_SHIFT)) & MDM_AP_RTU0_SWTMASK_IP_DBG_SWT4_MASK_DBG_MASK) 629 /*! @} */ 630 631 /*! @name RTU1_SWTMASK_IP_DBG - RTU1 SWT debug mask register */ 632 /*! @{ */ 633 634 #define MDM_AP_RTU1_SWTMASK_IP_DBG_SWT0_MASK_DBG_MASK (0x1U) 635 #define MDM_AP_RTU1_SWTMASK_IP_DBG_SWT0_MASK_DBG_SHIFT (0U) 636 #define MDM_AP_RTU1_SWTMASK_IP_DBG_SWT0_MASK_DBG_WIDTH (1U) 637 #define MDM_AP_RTU1_SWTMASK_IP_DBG_SWT0_MASK_DBG(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU1_SWTMASK_IP_DBG_SWT0_MASK_DBG_SHIFT)) & MDM_AP_RTU1_SWTMASK_IP_DBG_SWT0_MASK_DBG_MASK) 638 639 #define MDM_AP_RTU1_SWTMASK_IP_DBG_SWT1_MASK_DBG_MASK (0x2U) 640 #define MDM_AP_RTU1_SWTMASK_IP_DBG_SWT1_MASK_DBG_SHIFT (1U) 641 #define MDM_AP_RTU1_SWTMASK_IP_DBG_SWT1_MASK_DBG_WIDTH (1U) 642 #define MDM_AP_RTU1_SWTMASK_IP_DBG_SWT1_MASK_DBG(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU1_SWTMASK_IP_DBG_SWT1_MASK_DBG_SHIFT)) & MDM_AP_RTU1_SWTMASK_IP_DBG_SWT1_MASK_DBG_MASK) 643 644 #define MDM_AP_RTU1_SWTMASK_IP_DBG_SWT2_MASK_DBG_MASK (0x4U) 645 #define MDM_AP_RTU1_SWTMASK_IP_DBG_SWT2_MASK_DBG_SHIFT (2U) 646 #define MDM_AP_RTU1_SWTMASK_IP_DBG_SWT2_MASK_DBG_WIDTH (1U) 647 #define MDM_AP_RTU1_SWTMASK_IP_DBG_SWT2_MASK_DBG(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU1_SWTMASK_IP_DBG_SWT2_MASK_DBG_SHIFT)) & MDM_AP_RTU1_SWTMASK_IP_DBG_SWT2_MASK_DBG_MASK) 648 649 #define MDM_AP_RTU1_SWTMASK_IP_DBG_SWT3_MASK_DBG_MASK (0x8U) 650 #define MDM_AP_RTU1_SWTMASK_IP_DBG_SWT3_MASK_DBG_SHIFT (3U) 651 #define MDM_AP_RTU1_SWTMASK_IP_DBG_SWT3_MASK_DBG_WIDTH (1U) 652 #define MDM_AP_RTU1_SWTMASK_IP_DBG_SWT3_MASK_DBG(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU1_SWTMASK_IP_DBG_SWT3_MASK_DBG_SHIFT)) & MDM_AP_RTU1_SWTMASK_IP_DBG_SWT3_MASK_DBG_MASK) 653 654 #define MDM_AP_RTU1_SWTMASK_IP_DBG_SWT4_MASK_DBG_MASK (0x10U) 655 #define MDM_AP_RTU1_SWTMASK_IP_DBG_SWT4_MASK_DBG_SHIFT (4U) 656 #define MDM_AP_RTU1_SWTMASK_IP_DBG_SWT4_MASK_DBG_WIDTH (1U) 657 #define MDM_AP_RTU1_SWTMASK_IP_DBG_SWT4_MASK_DBG(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU1_SWTMASK_IP_DBG_SWT4_MASK_DBG_SHIFT)) & MDM_AP_RTU1_SWTMASK_IP_DBG_SWT4_MASK_DBG_MASK) 658 /*! @} */ 659 660 /*! @name RTU0_STMMASK_IP_DBG - RTU0 STM debug mask register */ 661 /*! @{ */ 662 663 #define MDM_AP_RTU0_STMMASK_IP_DBG_STM0_MASK_DBG_MASK (0x1U) 664 #define MDM_AP_RTU0_STMMASK_IP_DBG_STM0_MASK_DBG_SHIFT (0U) 665 #define MDM_AP_RTU0_STMMASK_IP_DBG_STM0_MASK_DBG_WIDTH (1U) 666 #define MDM_AP_RTU0_STMMASK_IP_DBG_STM0_MASK_DBG(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU0_STMMASK_IP_DBG_STM0_MASK_DBG_SHIFT)) & MDM_AP_RTU0_STMMASK_IP_DBG_STM0_MASK_DBG_MASK) 667 668 #define MDM_AP_RTU0_STMMASK_IP_DBG_STM1_MASK_DBG_MASK (0x2U) 669 #define MDM_AP_RTU0_STMMASK_IP_DBG_STM1_MASK_DBG_SHIFT (1U) 670 #define MDM_AP_RTU0_STMMASK_IP_DBG_STM1_MASK_DBG_WIDTH (1U) 671 #define MDM_AP_RTU0_STMMASK_IP_DBG_STM1_MASK_DBG(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU0_STMMASK_IP_DBG_STM1_MASK_DBG_SHIFT)) & MDM_AP_RTU0_STMMASK_IP_DBG_STM1_MASK_DBG_MASK) 672 673 #define MDM_AP_RTU0_STMMASK_IP_DBG_STM2_MASK_DBG_MASK (0x4U) 674 #define MDM_AP_RTU0_STMMASK_IP_DBG_STM2_MASK_DBG_SHIFT (2U) 675 #define MDM_AP_RTU0_STMMASK_IP_DBG_STM2_MASK_DBG_WIDTH (1U) 676 #define MDM_AP_RTU0_STMMASK_IP_DBG_STM2_MASK_DBG(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU0_STMMASK_IP_DBG_STM2_MASK_DBG_SHIFT)) & MDM_AP_RTU0_STMMASK_IP_DBG_STM2_MASK_DBG_MASK) 677 678 #define MDM_AP_RTU0_STMMASK_IP_DBG_STM3_MASK_DBG_MASK (0x8U) 679 #define MDM_AP_RTU0_STMMASK_IP_DBG_STM3_MASK_DBG_SHIFT (3U) 680 #define MDM_AP_RTU0_STMMASK_IP_DBG_STM3_MASK_DBG_WIDTH (1U) 681 #define MDM_AP_RTU0_STMMASK_IP_DBG_STM3_MASK_DBG(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU0_STMMASK_IP_DBG_STM3_MASK_DBG_SHIFT)) & MDM_AP_RTU0_STMMASK_IP_DBG_STM3_MASK_DBG_MASK) 682 /*! @} */ 683 684 /*! @name RTU1_STMMASK_IP_DBG - RTU1 STM debug mask register */ 685 /*! @{ */ 686 687 #define MDM_AP_RTU1_STMMASK_IP_DBG_STM0_MASK_DBG_MASK (0x1U) 688 #define MDM_AP_RTU1_STMMASK_IP_DBG_STM0_MASK_DBG_SHIFT (0U) 689 #define MDM_AP_RTU1_STMMASK_IP_DBG_STM0_MASK_DBG_WIDTH (1U) 690 #define MDM_AP_RTU1_STMMASK_IP_DBG_STM0_MASK_DBG(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU1_STMMASK_IP_DBG_STM0_MASK_DBG_SHIFT)) & MDM_AP_RTU1_STMMASK_IP_DBG_STM0_MASK_DBG_MASK) 691 692 #define MDM_AP_RTU1_STMMASK_IP_DBG_STM1_MASK_DBG_MASK (0x2U) 693 #define MDM_AP_RTU1_STMMASK_IP_DBG_STM1_MASK_DBG_SHIFT (1U) 694 #define MDM_AP_RTU1_STMMASK_IP_DBG_STM1_MASK_DBG_WIDTH (1U) 695 #define MDM_AP_RTU1_STMMASK_IP_DBG_STM1_MASK_DBG(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU1_STMMASK_IP_DBG_STM1_MASK_DBG_SHIFT)) & MDM_AP_RTU1_STMMASK_IP_DBG_STM1_MASK_DBG_MASK) 696 697 #define MDM_AP_RTU1_STMMASK_IP_DBG_STM2_MASK_DBG_MASK (0x4U) 698 #define MDM_AP_RTU1_STMMASK_IP_DBG_STM2_MASK_DBG_SHIFT (2U) 699 #define MDM_AP_RTU1_STMMASK_IP_DBG_STM2_MASK_DBG_WIDTH (1U) 700 #define MDM_AP_RTU1_STMMASK_IP_DBG_STM2_MASK_DBG(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU1_STMMASK_IP_DBG_STM2_MASK_DBG_SHIFT)) & MDM_AP_RTU1_STMMASK_IP_DBG_STM2_MASK_DBG_MASK) 701 702 #define MDM_AP_RTU1_STMMASK_IP_DBG_STM3_MASK_DBG_MASK (0x8U) 703 #define MDM_AP_RTU1_STMMASK_IP_DBG_STM3_MASK_DBG_SHIFT (3U) 704 #define MDM_AP_RTU1_STMMASK_IP_DBG_STM3_MASK_DBG_WIDTH (1U) 705 #define MDM_AP_RTU1_STMMASK_IP_DBG_STM3_MASK_DBG(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_RTU1_STMMASK_IP_DBG_STM3_MASK_DBG_SHIFT)) & MDM_AP_RTU1_STMMASK_IP_DBG_STM3_MASK_DBG_MASK) 706 /*! @} */ 707 708 /*! @name DBGENCNTRL - Debug enable control */ 709 /*! @{ */ 710 711 #define MDM_AP_DBGENCNTRL_RTU0_HIDEN3_MASK (0x100U) 712 #define MDM_AP_DBGENCNTRL_RTU0_HIDEN3_SHIFT (8U) 713 #define MDM_AP_DBGENCNTRL_RTU0_HIDEN3_WIDTH (1U) 714 #define MDM_AP_DBGENCNTRL_RTU0_HIDEN3(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL_RTU0_HIDEN3_SHIFT)) & MDM_AP_DBGENCNTRL_RTU0_HIDEN3_MASK) 715 716 #define MDM_AP_DBGENCNTRL_RTU0_HNIDEN3_MASK (0x200U) 717 #define MDM_AP_DBGENCNTRL_RTU0_HNIDEN3_SHIFT (9U) 718 #define MDM_AP_DBGENCNTRL_RTU0_HNIDEN3_WIDTH (1U) 719 #define MDM_AP_DBGENCNTRL_RTU0_HNIDEN3(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL_RTU0_HNIDEN3_SHIFT)) & MDM_AP_DBGENCNTRL_RTU0_HNIDEN3_MASK) 720 721 #define MDM_AP_DBGENCNTRL_RTU0_DBGEN3_MASK (0x400U) 722 #define MDM_AP_DBGENCNTRL_RTU0_DBGEN3_SHIFT (10U) 723 #define MDM_AP_DBGENCNTRL_RTU0_DBGEN3_WIDTH (1U) 724 #define MDM_AP_DBGENCNTRL_RTU0_DBGEN3(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL_RTU0_DBGEN3_SHIFT)) & MDM_AP_DBGENCNTRL_RTU0_DBGEN3_MASK) 725 726 #define MDM_AP_DBGENCNTRL_RTU0_NIDEN3_MASK (0x800U) 727 #define MDM_AP_DBGENCNTRL_RTU0_NIDEN3_SHIFT (11U) 728 #define MDM_AP_DBGENCNTRL_RTU0_NIDEN3_WIDTH (1U) 729 #define MDM_AP_DBGENCNTRL_RTU0_NIDEN3(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL_RTU0_NIDEN3_SHIFT)) & MDM_AP_DBGENCNTRL_RTU0_NIDEN3_MASK) 730 731 #define MDM_AP_DBGENCNTRL_RTU0_HIDEN2_MASK (0x4000U) 732 #define MDM_AP_DBGENCNTRL_RTU0_HIDEN2_SHIFT (14U) 733 #define MDM_AP_DBGENCNTRL_RTU0_HIDEN2_WIDTH (1U) 734 #define MDM_AP_DBGENCNTRL_RTU0_HIDEN2(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL_RTU0_HIDEN2_SHIFT)) & MDM_AP_DBGENCNTRL_RTU0_HIDEN2_MASK) 735 736 #define MDM_AP_DBGENCNTRL_RTU0_HNIDEN2_MASK (0x8000U) 737 #define MDM_AP_DBGENCNTRL_RTU0_HNIDEN2_SHIFT (15U) 738 #define MDM_AP_DBGENCNTRL_RTU0_HNIDEN2_WIDTH (1U) 739 #define MDM_AP_DBGENCNTRL_RTU0_HNIDEN2(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL_RTU0_HNIDEN2_SHIFT)) & MDM_AP_DBGENCNTRL_RTU0_HNIDEN2_MASK) 740 741 #define MDM_AP_DBGENCNTRL_RTU0_DBGEN2_MASK (0x10000U) 742 #define MDM_AP_DBGENCNTRL_RTU0_DBGEN2_SHIFT (16U) 743 #define MDM_AP_DBGENCNTRL_RTU0_DBGEN2_WIDTH (1U) 744 #define MDM_AP_DBGENCNTRL_RTU0_DBGEN2(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL_RTU0_DBGEN2_SHIFT)) & MDM_AP_DBGENCNTRL_RTU0_DBGEN2_MASK) 745 746 #define MDM_AP_DBGENCNTRL_RTU0_NIDEN2_MASK (0x20000U) 747 #define MDM_AP_DBGENCNTRL_RTU0_NIDEN2_SHIFT (17U) 748 #define MDM_AP_DBGENCNTRL_RTU0_NIDEN2_WIDTH (1U) 749 #define MDM_AP_DBGENCNTRL_RTU0_NIDEN2(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL_RTU0_NIDEN2_SHIFT)) & MDM_AP_DBGENCNTRL_RTU0_NIDEN2_MASK) 750 751 #define MDM_AP_DBGENCNTRL_RTU0_HIDEN1_MASK (0x100000U) 752 #define MDM_AP_DBGENCNTRL_RTU0_HIDEN1_SHIFT (20U) 753 #define MDM_AP_DBGENCNTRL_RTU0_HIDEN1_WIDTH (1U) 754 #define MDM_AP_DBGENCNTRL_RTU0_HIDEN1(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL_RTU0_HIDEN1_SHIFT)) & MDM_AP_DBGENCNTRL_RTU0_HIDEN1_MASK) 755 756 #define MDM_AP_DBGENCNTRL_RTU0_HNIDEN1_MASK (0x200000U) 757 #define MDM_AP_DBGENCNTRL_RTU0_HNIDEN1_SHIFT (21U) 758 #define MDM_AP_DBGENCNTRL_RTU0_HNIDEN1_WIDTH (1U) 759 #define MDM_AP_DBGENCNTRL_RTU0_HNIDEN1(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL_RTU0_HNIDEN1_SHIFT)) & MDM_AP_DBGENCNTRL_RTU0_HNIDEN1_MASK) 760 761 #define MDM_AP_DBGENCNTRL_RTU0_DBGEN1_MASK (0x400000U) 762 #define MDM_AP_DBGENCNTRL_RTU0_DBGEN1_SHIFT (22U) 763 #define MDM_AP_DBGENCNTRL_RTU0_DBGEN1_WIDTH (1U) 764 #define MDM_AP_DBGENCNTRL_RTU0_DBGEN1(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL_RTU0_DBGEN1_SHIFT)) & MDM_AP_DBGENCNTRL_RTU0_DBGEN1_MASK) 765 766 #define MDM_AP_DBGENCNTRL_RTU0_NIDEN1_MASK (0x800000U) 767 #define MDM_AP_DBGENCNTRL_RTU0_NIDEN1_SHIFT (23U) 768 #define MDM_AP_DBGENCNTRL_RTU0_NIDEN1_WIDTH (1U) 769 #define MDM_AP_DBGENCNTRL_RTU0_NIDEN1(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL_RTU0_NIDEN1_SHIFT)) & MDM_AP_DBGENCNTRL_RTU0_NIDEN1_MASK) 770 771 #define MDM_AP_DBGENCNTRL_RTU0_HIDEN0_MASK (0x4000000U) 772 #define MDM_AP_DBGENCNTRL_RTU0_HIDEN0_SHIFT (26U) 773 #define MDM_AP_DBGENCNTRL_RTU0_HIDEN0_WIDTH (1U) 774 #define MDM_AP_DBGENCNTRL_RTU0_HIDEN0(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL_RTU0_HIDEN0_SHIFT)) & MDM_AP_DBGENCNTRL_RTU0_HIDEN0_MASK) 775 776 #define MDM_AP_DBGENCNTRL_RTU0_HNIDEN0_MASK (0x8000000U) 777 #define MDM_AP_DBGENCNTRL_RTU0_HNIDEN0_SHIFT (27U) 778 #define MDM_AP_DBGENCNTRL_RTU0_HNIDEN0_WIDTH (1U) 779 #define MDM_AP_DBGENCNTRL_RTU0_HNIDEN0(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL_RTU0_HNIDEN0_SHIFT)) & MDM_AP_DBGENCNTRL_RTU0_HNIDEN0_MASK) 780 781 #define MDM_AP_DBGENCNTRL_RTU0_DBGEN0_MASK (0x10000000U) 782 #define MDM_AP_DBGENCNTRL_RTU0_DBGEN0_SHIFT (28U) 783 #define MDM_AP_DBGENCNTRL_RTU0_DBGEN0_WIDTH (1U) 784 #define MDM_AP_DBGENCNTRL_RTU0_DBGEN0(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL_RTU0_DBGEN0_SHIFT)) & MDM_AP_DBGENCNTRL_RTU0_DBGEN0_MASK) 785 786 #define MDM_AP_DBGENCNTRL_RTU0_NIDEN0_MASK (0x20000000U) 787 #define MDM_AP_DBGENCNTRL_RTU0_NIDEN0_SHIFT (29U) 788 #define MDM_AP_DBGENCNTRL_RTU0_NIDEN0_WIDTH (1U) 789 #define MDM_AP_DBGENCNTRL_RTU0_NIDEN0(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL_RTU0_NIDEN0_SHIFT)) & MDM_AP_DBGENCNTRL_RTU0_NIDEN0_MASK) 790 /*! @} */ 791 792 /*! @name DBGENCNTRL2 - Debug enable control 2 */ 793 /*! @{ */ 794 795 #define MDM_AP_DBGENCNTRL2_RTU1_HIDEN3_MASK (0x100U) 796 #define MDM_AP_DBGENCNTRL2_RTU1_HIDEN3_SHIFT (8U) 797 #define MDM_AP_DBGENCNTRL2_RTU1_HIDEN3_WIDTH (1U) 798 #define MDM_AP_DBGENCNTRL2_RTU1_HIDEN3(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL2_RTU1_HIDEN3_SHIFT)) & MDM_AP_DBGENCNTRL2_RTU1_HIDEN3_MASK) 799 800 #define MDM_AP_DBGENCNTRL2_RTU1_HNIDEN3_MASK (0x200U) 801 #define MDM_AP_DBGENCNTRL2_RTU1_HNIDEN3_SHIFT (9U) 802 #define MDM_AP_DBGENCNTRL2_RTU1_HNIDEN3_WIDTH (1U) 803 #define MDM_AP_DBGENCNTRL2_RTU1_HNIDEN3(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL2_RTU1_HNIDEN3_SHIFT)) & MDM_AP_DBGENCNTRL2_RTU1_HNIDEN3_MASK) 804 805 #define MDM_AP_DBGENCNTRL2_RTU1_DBGEN3_MASK (0x400U) 806 #define MDM_AP_DBGENCNTRL2_RTU1_DBGEN3_SHIFT (10U) 807 #define MDM_AP_DBGENCNTRL2_RTU1_DBGEN3_WIDTH (1U) 808 #define MDM_AP_DBGENCNTRL2_RTU1_DBGEN3(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL2_RTU1_DBGEN3_SHIFT)) & MDM_AP_DBGENCNTRL2_RTU1_DBGEN3_MASK) 809 810 #define MDM_AP_DBGENCNTRL2_RTU1_NIDEN3_MASK (0x800U) 811 #define MDM_AP_DBGENCNTRL2_RTU1_NIDEN3_SHIFT (11U) 812 #define MDM_AP_DBGENCNTRL2_RTU1_NIDEN3_WIDTH (1U) 813 #define MDM_AP_DBGENCNTRL2_RTU1_NIDEN3(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL2_RTU1_NIDEN3_SHIFT)) & MDM_AP_DBGENCNTRL2_RTU1_NIDEN3_MASK) 814 815 #define MDM_AP_DBGENCNTRL2_RTU1_HIDEN2_MASK (0x4000U) 816 #define MDM_AP_DBGENCNTRL2_RTU1_HIDEN2_SHIFT (14U) 817 #define MDM_AP_DBGENCNTRL2_RTU1_HIDEN2_WIDTH (1U) 818 #define MDM_AP_DBGENCNTRL2_RTU1_HIDEN2(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL2_RTU1_HIDEN2_SHIFT)) & MDM_AP_DBGENCNTRL2_RTU1_HIDEN2_MASK) 819 820 #define MDM_AP_DBGENCNTRL2_RTU1_HNIDEN2_MASK (0x8000U) 821 #define MDM_AP_DBGENCNTRL2_RTU1_HNIDEN2_SHIFT (15U) 822 #define MDM_AP_DBGENCNTRL2_RTU1_HNIDEN2_WIDTH (1U) 823 #define MDM_AP_DBGENCNTRL2_RTU1_HNIDEN2(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL2_RTU1_HNIDEN2_SHIFT)) & MDM_AP_DBGENCNTRL2_RTU1_HNIDEN2_MASK) 824 825 #define MDM_AP_DBGENCNTRL2_RTU1_DBGEN2_MASK (0x10000U) 826 #define MDM_AP_DBGENCNTRL2_RTU1_DBGEN2_SHIFT (16U) 827 #define MDM_AP_DBGENCNTRL2_RTU1_DBGEN2_WIDTH (1U) 828 #define MDM_AP_DBGENCNTRL2_RTU1_DBGEN2(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL2_RTU1_DBGEN2_SHIFT)) & MDM_AP_DBGENCNTRL2_RTU1_DBGEN2_MASK) 829 830 #define MDM_AP_DBGENCNTRL2_RTU1_NIDEN2_MASK (0x20000U) 831 #define MDM_AP_DBGENCNTRL2_RTU1_NIDEN2_SHIFT (17U) 832 #define MDM_AP_DBGENCNTRL2_RTU1_NIDEN2_WIDTH (1U) 833 #define MDM_AP_DBGENCNTRL2_RTU1_NIDEN2(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL2_RTU1_NIDEN2_SHIFT)) & MDM_AP_DBGENCNTRL2_RTU1_NIDEN2_MASK) 834 835 #define MDM_AP_DBGENCNTRL2_RTU1_HIDEN1_MASK (0x100000U) 836 #define MDM_AP_DBGENCNTRL2_RTU1_HIDEN1_SHIFT (20U) 837 #define MDM_AP_DBGENCNTRL2_RTU1_HIDEN1_WIDTH (1U) 838 #define MDM_AP_DBGENCNTRL2_RTU1_HIDEN1(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL2_RTU1_HIDEN1_SHIFT)) & MDM_AP_DBGENCNTRL2_RTU1_HIDEN1_MASK) 839 840 #define MDM_AP_DBGENCNTRL2_RTU1_HNIDEN1_MASK (0x200000U) 841 #define MDM_AP_DBGENCNTRL2_RTU1_HNIDEN1_SHIFT (21U) 842 #define MDM_AP_DBGENCNTRL2_RTU1_HNIDEN1_WIDTH (1U) 843 #define MDM_AP_DBGENCNTRL2_RTU1_HNIDEN1(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL2_RTU1_HNIDEN1_SHIFT)) & MDM_AP_DBGENCNTRL2_RTU1_HNIDEN1_MASK) 844 845 #define MDM_AP_DBGENCNTRL2_RTU1_DBGEN1_MASK (0x400000U) 846 #define MDM_AP_DBGENCNTRL2_RTU1_DBGEN1_SHIFT (22U) 847 #define MDM_AP_DBGENCNTRL2_RTU1_DBGEN1_WIDTH (1U) 848 #define MDM_AP_DBGENCNTRL2_RTU1_DBGEN1(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL2_RTU1_DBGEN1_SHIFT)) & MDM_AP_DBGENCNTRL2_RTU1_DBGEN1_MASK) 849 850 #define MDM_AP_DBGENCNTRL2_RTU1_NIDEN1_MASK (0x800000U) 851 #define MDM_AP_DBGENCNTRL2_RTU1_NIDEN1_SHIFT (23U) 852 #define MDM_AP_DBGENCNTRL2_RTU1_NIDEN1_WIDTH (1U) 853 #define MDM_AP_DBGENCNTRL2_RTU1_NIDEN1(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL2_RTU1_NIDEN1_SHIFT)) & MDM_AP_DBGENCNTRL2_RTU1_NIDEN1_MASK) 854 855 #define MDM_AP_DBGENCNTRL2_RTU1_HIDEN0_MASK (0x4000000U) 856 #define MDM_AP_DBGENCNTRL2_RTU1_HIDEN0_SHIFT (26U) 857 #define MDM_AP_DBGENCNTRL2_RTU1_HIDEN0_WIDTH (1U) 858 #define MDM_AP_DBGENCNTRL2_RTU1_HIDEN0(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL2_RTU1_HIDEN0_SHIFT)) & MDM_AP_DBGENCNTRL2_RTU1_HIDEN0_MASK) 859 860 #define MDM_AP_DBGENCNTRL2_RTU1_HNIDEN0_MASK (0x8000000U) 861 #define MDM_AP_DBGENCNTRL2_RTU1_HNIDEN0_SHIFT (27U) 862 #define MDM_AP_DBGENCNTRL2_RTU1_HNIDEN0_WIDTH (1U) 863 #define MDM_AP_DBGENCNTRL2_RTU1_HNIDEN0(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL2_RTU1_HNIDEN0_SHIFT)) & MDM_AP_DBGENCNTRL2_RTU1_HNIDEN0_MASK) 864 865 #define MDM_AP_DBGENCNTRL2_RTU1_DBGEN0_MASK (0x10000000U) 866 #define MDM_AP_DBGENCNTRL2_RTU1_DBGEN0_SHIFT (28U) 867 #define MDM_AP_DBGENCNTRL2_RTU1_DBGEN0_WIDTH (1U) 868 #define MDM_AP_DBGENCNTRL2_RTU1_DBGEN0(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL2_RTU1_DBGEN0_SHIFT)) & MDM_AP_DBGENCNTRL2_RTU1_DBGEN0_MASK) 869 870 #define MDM_AP_DBGENCNTRL2_RTU1_NIDEN0_MASK (0x20000000U) 871 #define MDM_AP_DBGENCNTRL2_RTU1_NIDEN0_SHIFT (29U) 872 #define MDM_AP_DBGENCNTRL2_RTU1_NIDEN0_WIDTH (1U) 873 #define MDM_AP_DBGENCNTRL2_RTU1_NIDEN0(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL2_RTU1_NIDEN0_SHIFT)) & MDM_AP_DBGENCNTRL2_RTU1_NIDEN0_MASK) 874 /*! @} */ 875 876 /*! @name DBGENCNTRL3 - Debug enable control 3 */ 877 /*! @{ */ 878 879 #define MDM_AP_DBGENCNTRL3_GDBGEN_MASK (0x10U) 880 #define MDM_AP_DBGENCNTRL3_GDBGEN_SHIFT (4U) 881 #define MDM_AP_DBGENCNTRL3_GDBGEN_WIDTH (1U) 882 #define MDM_AP_DBGENCNTRL3_GDBGEN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL3_GDBGEN_SHIFT)) & MDM_AP_DBGENCNTRL3_GDBGEN_MASK) 883 884 #define MDM_AP_DBGENCNTRL3_GNIDEN_MASK (0x20U) 885 #define MDM_AP_DBGENCNTRL3_GNIDEN_SHIFT (5U) 886 #define MDM_AP_DBGENCNTRL3_GNIDEN_WIDTH (1U) 887 #define MDM_AP_DBGENCNTRL3_GNIDEN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL3_GNIDEN_SHIFT)) & MDM_AP_DBGENCNTRL3_GNIDEN_MASK) 888 889 #define MDM_AP_DBGENCNTRL3_GSPIDEN_MASK (0x40U) 890 #define MDM_AP_DBGENCNTRL3_GSPIDEN_SHIFT (6U) 891 #define MDM_AP_DBGENCNTRL3_GSPIDEN_WIDTH (1U) 892 #define MDM_AP_DBGENCNTRL3_GSPIDEN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL3_GSPIDEN_SHIFT)) & MDM_AP_DBGENCNTRL3_GSPIDEN_MASK) 893 894 #define MDM_AP_DBGENCNTRL3_GSPNIDEN_MASK (0x80U) 895 #define MDM_AP_DBGENCNTRL3_GSPNIDEN_SHIFT (7U) 896 #define MDM_AP_DBGENCNTRL3_GSPNIDEN_WIDTH (1U) 897 #define MDM_AP_DBGENCNTRL3_GSPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL3_GSPNIDEN_SHIFT)) & MDM_AP_DBGENCNTRL3_GSPNIDEN_MASK) 898 899 #define MDM_AP_DBGENCNTRL3_CEVA_SPF2_DBGEN_MASK (0x400U) 900 #define MDM_AP_DBGENCNTRL3_CEVA_SPF2_DBGEN_SHIFT (10U) 901 #define MDM_AP_DBGENCNTRL3_CEVA_SPF2_DBGEN_WIDTH (1U) 902 #define MDM_AP_DBGENCNTRL3_CEVA_SPF2_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL3_CEVA_SPF2_DBGEN_SHIFT)) & MDM_AP_DBGENCNTRL3_CEVA_SPF2_DBGEN_MASK) 903 904 #define MDM_AP_DBGENCNTRL3_CEVA_SPF2_NIDEN_MASK (0x800U) 905 #define MDM_AP_DBGENCNTRL3_CEVA_SPF2_NIDEN_SHIFT (11U) 906 #define MDM_AP_DBGENCNTRL3_CEVA_SPF2_NIDEN_WIDTH (1U) 907 #define MDM_AP_DBGENCNTRL3_CEVA_SPF2_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL3_CEVA_SPF2_NIDEN_SHIFT)) & MDM_AP_DBGENCNTRL3_CEVA_SPF2_NIDEN_MASK) 908 909 #define MDM_AP_DBGENCNTRL3_CEVA_SPF2_SPIDEN_MASK (0x1000U) 910 #define MDM_AP_DBGENCNTRL3_CEVA_SPF2_SPIDEN_SHIFT (12U) 911 #define MDM_AP_DBGENCNTRL3_CEVA_SPF2_SPIDEN_WIDTH (1U) 912 #define MDM_AP_DBGENCNTRL3_CEVA_SPF2_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL3_CEVA_SPF2_SPIDEN_SHIFT)) & MDM_AP_DBGENCNTRL3_CEVA_SPF2_SPIDEN_MASK) 913 914 #define MDM_AP_DBGENCNTRL3_CEVA_SPF2_SPNIDEN_MASK (0x2000U) 915 #define MDM_AP_DBGENCNTRL3_CEVA_SPF2_SPNIDEN_SHIFT (13U) 916 #define MDM_AP_DBGENCNTRL3_CEVA_SPF2_SPNIDEN_WIDTH (1U) 917 #define MDM_AP_DBGENCNTRL3_CEVA_SPF2_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL3_CEVA_SPF2_SPNIDEN_SHIFT)) & MDM_AP_DBGENCNTRL3_CEVA_SPF2_SPNIDEN_MASK) 918 919 #define MDM_AP_DBGENCNTRL3_GTM_DBGEN_MASK (0x8000U) 920 #define MDM_AP_DBGENCNTRL3_GTM_DBGEN_SHIFT (15U) 921 #define MDM_AP_DBGENCNTRL3_GTM_DBGEN_WIDTH (1U) 922 #define MDM_AP_DBGENCNTRL3_GTM_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL3_GTM_DBGEN_SHIFT)) & MDM_AP_DBGENCNTRL3_GTM_DBGEN_MASK) 923 924 #define MDM_AP_DBGENCNTRL3_CE_A_DBGEN_MASK (0x100000U) 925 #define MDM_AP_DBGENCNTRL3_CE_A_DBGEN_SHIFT (20U) 926 #define MDM_AP_DBGENCNTRL3_CE_A_DBGEN_WIDTH (1U) 927 #define MDM_AP_DBGENCNTRL3_CE_A_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL3_CE_A_DBGEN_SHIFT)) & MDM_AP_DBGENCNTRL3_CE_A_DBGEN_MASK) 928 929 #define MDM_AP_DBGENCNTRL3_CE_A_NIDEN_MASK (0x200000U) 930 #define MDM_AP_DBGENCNTRL3_CE_A_NIDEN_SHIFT (21U) 931 #define MDM_AP_DBGENCNTRL3_CE_A_NIDEN_WIDTH (1U) 932 #define MDM_AP_DBGENCNTRL3_CE_A_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL3_CE_A_NIDEN_SHIFT)) & MDM_AP_DBGENCNTRL3_CE_A_NIDEN_MASK) 933 934 #define MDM_AP_DBGENCNTRL3_CE_A_SPIDEN_MASK (0x400000U) 935 #define MDM_AP_DBGENCNTRL3_CE_A_SPIDEN_SHIFT (22U) 936 #define MDM_AP_DBGENCNTRL3_CE_A_SPIDEN_WIDTH (1U) 937 #define MDM_AP_DBGENCNTRL3_CE_A_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL3_CE_A_SPIDEN_SHIFT)) & MDM_AP_DBGENCNTRL3_CE_A_SPIDEN_MASK) 938 939 #define MDM_AP_DBGENCNTRL3_CE_A_SPNIDEN_MASK (0x800000U) 940 #define MDM_AP_DBGENCNTRL3_CE_A_SPNIDEN_SHIFT (23U) 941 #define MDM_AP_DBGENCNTRL3_CE_A_SPNIDEN_WIDTH (1U) 942 #define MDM_AP_DBGENCNTRL3_CE_A_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL3_CE_A_SPNIDEN_SHIFT)) & MDM_AP_DBGENCNTRL3_CE_A_SPNIDEN_MASK) 943 944 #define MDM_AP_DBGENCNTRL3_CE_B_DBGEN_MASK (0x1000000U) 945 #define MDM_AP_DBGENCNTRL3_CE_B_DBGEN_SHIFT (24U) 946 #define MDM_AP_DBGENCNTRL3_CE_B_DBGEN_WIDTH (1U) 947 #define MDM_AP_DBGENCNTRL3_CE_B_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL3_CE_B_DBGEN_SHIFT)) & MDM_AP_DBGENCNTRL3_CE_B_DBGEN_MASK) 948 949 #define MDM_AP_DBGENCNTRL3_CE_B_NIDEN_MASK (0x2000000U) 950 #define MDM_AP_DBGENCNTRL3_CE_B_NIDEN_SHIFT (25U) 951 #define MDM_AP_DBGENCNTRL3_CE_B_NIDEN_WIDTH (1U) 952 #define MDM_AP_DBGENCNTRL3_CE_B_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL3_CE_B_NIDEN_SHIFT)) & MDM_AP_DBGENCNTRL3_CE_B_NIDEN_MASK) 953 954 #define MDM_AP_DBGENCNTRL3_CE_B_SPIDEN_MASK (0x4000000U) 955 #define MDM_AP_DBGENCNTRL3_CE_B_SPIDEN_SHIFT (26U) 956 #define MDM_AP_DBGENCNTRL3_CE_B_SPIDEN_WIDTH (1U) 957 #define MDM_AP_DBGENCNTRL3_CE_B_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL3_CE_B_SPIDEN_SHIFT)) & MDM_AP_DBGENCNTRL3_CE_B_SPIDEN_MASK) 958 959 #define MDM_AP_DBGENCNTRL3_CE_B_SPNIDEN_MASK (0x8000000U) 960 #define MDM_AP_DBGENCNTRL3_CE_B_SPNIDEN_SHIFT (27U) 961 #define MDM_AP_DBGENCNTRL3_CE_B_SPNIDEN_WIDTH (1U) 962 #define MDM_AP_DBGENCNTRL3_CE_B_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL3_CE_B_SPNIDEN_SHIFT)) & MDM_AP_DBGENCNTRL3_CE_B_SPNIDEN_MASK) 963 964 #define MDM_AP_DBGENCNTRL3_SYSM_DBGEN_MASK (0x10000000U) 965 #define MDM_AP_DBGENCNTRL3_SYSM_DBGEN_SHIFT (28U) 966 #define MDM_AP_DBGENCNTRL3_SYSM_DBGEN_WIDTH (1U) 967 #define MDM_AP_DBGENCNTRL3_SYSM_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL3_SYSM_DBGEN_SHIFT)) & MDM_AP_DBGENCNTRL3_SYSM_DBGEN_MASK) 968 969 #define MDM_AP_DBGENCNTRL3_SYSM_NIDEN_MASK (0x20000000U) 970 #define MDM_AP_DBGENCNTRL3_SYSM_NIDEN_SHIFT (29U) 971 #define MDM_AP_DBGENCNTRL3_SYSM_NIDEN_WIDTH (1U) 972 #define MDM_AP_DBGENCNTRL3_SYSM_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL3_SYSM_NIDEN_SHIFT)) & MDM_AP_DBGENCNTRL3_SYSM_NIDEN_MASK) 973 974 #define MDM_AP_DBGENCNTRL3_SYSM_SPIDEN_MASK (0x40000000U) 975 #define MDM_AP_DBGENCNTRL3_SYSM_SPIDEN_SHIFT (30U) 976 #define MDM_AP_DBGENCNTRL3_SYSM_SPIDEN_WIDTH (1U) 977 #define MDM_AP_DBGENCNTRL3_SYSM_SPIDEN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL3_SYSM_SPIDEN_SHIFT)) & MDM_AP_DBGENCNTRL3_SYSM_SPIDEN_MASK) 978 979 #define MDM_AP_DBGENCNTRL3_SYSM_SPNIDEN_MASK (0x80000000U) 980 #define MDM_AP_DBGENCNTRL3_SYSM_SPNIDEN_SHIFT (31U) 981 #define MDM_AP_DBGENCNTRL3_SYSM_SPNIDEN_WIDTH (1U) 982 #define MDM_AP_DBGENCNTRL3_SYSM_SPNIDEN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DBGENCNTRL3_SYSM_SPNIDEN_SHIFT)) & MDM_AP_DBGENCNTRL3_SYSM_SPNIDEN_MASK) 983 /*! @} */ 984 985 /*! @name DTS_ENABLE - DTS output enable register */ 986 /*! @{ */ 987 988 #define MDM_AP_DTS_ENABLE_DTS_EN_MASK (0x1U) 989 #define MDM_AP_DTS_ENABLE_DTS_EN_SHIFT (0U) 990 #define MDM_AP_DTS_ENABLE_DTS_EN_WIDTH (1U) 991 #define MDM_AP_DTS_ENABLE_DTS_EN(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DTS_ENABLE_DTS_EN_SHIFT)) & MDM_AP_DTS_ENABLE_DTS_EN_MASK) 992 993 #define MDM_AP_DTS_ENABLE_DTS_EN_B_MASK (0x2U) 994 #define MDM_AP_DTS_ENABLE_DTS_EN_B_SHIFT (1U) 995 #define MDM_AP_DTS_ENABLE_DTS_EN_B_WIDTH (1U) 996 #define MDM_AP_DTS_ENABLE_DTS_EN_B(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DTS_ENABLE_DTS_EN_B_SHIFT)) & MDM_AP_DTS_ENABLE_DTS_EN_B_MASK) 997 998 #define MDM_AP_DTS_ENABLE_DTS_EN_C_MASK (0x4U) 999 #define MDM_AP_DTS_ENABLE_DTS_EN_C_SHIFT (2U) 1000 #define MDM_AP_DTS_ENABLE_DTS_EN_C_WIDTH (1U) 1001 #define MDM_AP_DTS_ENABLE_DTS_EN_C(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DTS_ENABLE_DTS_EN_C_SHIFT)) & MDM_AP_DTS_ENABLE_DTS_EN_C_MASK) 1002 1003 #define MDM_AP_DTS_ENABLE_DTS_EN_D_MASK (0x8U) 1004 #define MDM_AP_DTS_ENABLE_DTS_EN_D_SHIFT (3U) 1005 #define MDM_AP_DTS_ENABLE_DTS_EN_D_WIDTH (1U) 1006 #define MDM_AP_DTS_ENABLE_DTS_EN_D(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DTS_ENABLE_DTS_EN_D_SHIFT)) & MDM_AP_DTS_ENABLE_DTS_EN_D_MASK) 1007 /*! @} */ 1008 1009 /*! @name DTS_STARTUP - DTS startup register */ 1010 /*! @{ */ 1011 1012 #define MDM_AP_DTS_STARTUP_AD_MASK (0xFFFFFFFFU) 1013 #define MDM_AP_DTS_STARTUP_AD_SHIFT (0U) 1014 #define MDM_AP_DTS_STARTUP_AD_WIDTH (32U) 1015 #define MDM_AP_DTS_STARTUP_AD(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DTS_STARTUP_AD_SHIFT)) & MDM_AP_DTS_STARTUP_AD_MASK) 1016 /*! @} */ 1017 1018 /*! @name DTS_STARTUP_B - DTS startup register B */ 1019 /*! @{ */ 1020 1021 #define MDM_AP_DTS_STARTUP_B_AD_MASK (0xFFFFFFFFU) 1022 #define MDM_AP_DTS_STARTUP_B_AD_SHIFT (0U) 1023 #define MDM_AP_DTS_STARTUP_B_AD_WIDTH (32U) 1024 #define MDM_AP_DTS_STARTUP_B_AD(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DTS_STARTUP_B_AD_SHIFT)) & MDM_AP_DTS_STARTUP_B_AD_MASK) 1025 /*! @} */ 1026 1027 /*! @name DTS_STARTUP_C - DTS startup register C */ 1028 /*! @{ */ 1029 1030 #define MDM_AP_DTS_STARTUP_C_AD_MASK (0xFFFFFFFFU) 1031 #define MDM_AP_DTS_STARTUP_C_AD_SHIFT (0U) 1032 #define MDM_AP_DTS_STARTUP_C_AD_WIDTH (32U) 1033 #define MDM_AP_DTS_STARTUP_C_AD(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DTS_STARTUP_C_AD_SHIFT)) & MDM_AP_DTS_STARTUP_C_AD_MASK) 1034 /*! @} */ 1035 1036 /*! @name DTS_STARTUP_D - DTS startup register D */ 1037 /*! @{ */ 1038 1039 #define MDM_AP_DTS_STARTUP_D_AD_MASK (0xFFFFFFFFU) 1040 #define MDM_AP_DTS_STARTUP_D_AD_SHIFT (0U) 1041 #define MDM_AP_DTS_STARTUP_D_AD_WIDTH (32U) 1042 #define MDM_AP_DTS_STARTUP_D_AD(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DTS_STARTUP_D_AD_SHIFT)) & MDM_AP_DTS_STARTUP_D_AD_MASK) 1043 /*! @} */ 1044 1045 /*! @name DTS_SEMAPHORE - DTS SEMAPHORE register */ 1046 /*! @{ */ 1047 1048 #define MDM_AP_DTS_SEMAPHORE_ST_MASK (0xFFFFFFFFU) 1049 #define MDM_AP_DTS_SEMAPHORE_ST_SHIFT (0U) 1050 #define MDM_AP_DTS_SEMAPHORE_ST_WIDTH (32U) 1051 #define MDM_AP_DTS_SEMAPHORE_ST(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DTS_SEMAPHORE_ST_SHIFT)) & MDM_AP_DTS_SEMAPHORE_ST_MASK) 1052 /*! @} */ 1053 1054 /*! @name DTS_SEMAPHORE_B - DTS SEMAPHORE_B register */ 1055 /*! @{ */ 1056 1057 #define MDM_AP_DTS_SEMAPHORE_B_ST_B_MASK (0xFFFFFFFFU) 1058 #define MDM_AP_DTS_SEMAPHORE_B_ST_B_SHIFT (0U) 1059 #define MDM_AP_DTS_SEMAPHORE_B_ST_B_WIDTH (32U) 1060 #define MDM_AP_DTS_SEMAPHORE_B_ST_B(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DTS_SEMAPHORE_B_ST_B_SHIFT)) & MDM_AP_DTS_SEMAPHORE_B_ST_B_MASK) 1061 /*! @} */ 1062 1063 /*! @name DTS_SEMAPHORE_C - DTS SEMAPHORE_C register */ 1064 /*! @{ */ 1065 1066 #define MDM_AP_DTS_SEMAPHORE_C_ST_C_MASK (0xFFFFFFFFU) 1067 #define MDM_AP_DTS_SEMAPHORE_C_ST_C_SHIFT (0U) 1068 #define MDM_AP_DTS_SEMAPHORE_C_ST_C_WIDTH (32U) 1069 #define MDM_AP_DTS_SEMAPHORE_C_ST_C(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DTS_SEMAPHORE_C_ST_C_SHIFT)) & MDM_AP_DTS_SEMAPHORE_C_ST_C_MASK) 1070 /*! @} */ 1071 1072 /*! @name DTS_SEMAPHORE_D - DTS SEMAPHORE_D register */ 1073 /*! @{ */ 1074 1075 #define MDM_AP_DTS_SEMAPHORE_D_ST_D_MASK (0xFFFFFFFFU) 1076 #define MDM_AP_DTS_SEMAPHORE_D_ST_D_SHIFT (0U) 1077 #define MDM_AP_DTS_SEMAPHORE_D_ST_D_WIDTH (32U) 1078 #define MDM_AP_DTS_SEMAPHORE_D_ST_D(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DTS_SEMAPHORE_D_ST_D_SHIFT)) & MDM_AP_DTS_SEMAPHORE_D_ST_D_MASK) 1079 /*! @} */ 1080 1081 /*! @name IDR - Identification Register */ 1082 /*! @{ */ 1083 1084 #define MDM_AP_IDR_Type_MASK (0xFU) 1085 #define MDM_AP_IDR_Type_SHIFT (0U) 1086 #define MDM_AP_IDR_Type_WIDTH (4U) 1087 #define MDM_AP_IDR_Type(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_IDR_Type_SHIFT)) & MDM_AP_IDR_Type_MASK) 1088 1089 #define MDM_AP_IDR_Variant_MASK (0xF0U) 1090 #define MDM_AP_IDR_Variant_SHIFT (4U) 1091 #define MDM_AP_IDR_Variant_WIDTH (4U) 1092 #define MDM_AP_IDR_Variant(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_IDR_Variant_SHIFT)) & MDM_AP_IDR_Variant_MASK) 1093 1094 #define MDM_AP_IDR_Class_MASK (0x1E000U) 1095 #define MDM_AP_IDR_Class_SHIFT (13U) 1096 #define MDM_AP_IDR_Class_WIDTH (4U) 1097 #define MDM_AP_IDR_Class(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_IDR_Class_SHIFT)) & MDM_AP_IDR_Class_MASK) 1098 1099 #define MDM_AP_IDR_JEDEC_code_MASK (0xFE0000U) 1100 #define MDM_AP_IDR_JEDEC_code_SHIFT (17U) 1101 #define MDM_AP_IDR_JEDEC_code_WIDTH (7U) 1102 #define MDM_AP_IDR_JEDEC_code(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_IDR_JEDEC_code_SHIFT)) & MDM_AP_IDR_JEDEC_code_MASK) 1103 1104 #define MDM_AP_IDR_JEDEC_bank_MASK (0xF000000U) 1105 #define MDM_AP_IDR_JEDEC_bank_SHIFT (24U) 1106 #define MDM_AP_IDR_JEDEC_bank_WIDTH (4U) 1107 #define MDM_AP_IDR_JEDEC_bank(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_IDR_JEDEC_bank_SHIFT)) & MDM_AP_IDR_JEDEC_bank_MASK) 1108 1109 #define MDM_AP_IDR_REVISION_MASK (0xF0000000U) 1110 #define MDM_AP_IDR_REVISION_SHIFT (28U) 1111 #define MDM_AP_IDR_REVISION_WIDTH (4U) 1112 #define MDM_AP_IDR_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_IDR_REVISION_SHIFT)) & MDM_AP_IDR_REVISION_MASK) 1113 /*! @} */ 1114 1115 /*! @name DEVARCH - CoreSight Device Architecture Register */ 1116 /*! @{ */ 1117 1118 #define MDM_AP_DEVARCH_ARCHID_MASK (0xFFFFU) 1119 #define MDM_AP_DEVARCH_ARCHID_SHIFT (0U) 1120 #define MDM_AP_DEVARCH_ARCHID_WIDTH (16U) 1121 #define MDM_AP_DEVARCH_ARCHID(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DEVARCH_ARCHID_SHIFT)) & MDM_AP_DEVARCH_ARCHID_MASK) 1122 1123 #define MDM_AP_DEVARCH_REVISION_MASK (0xF0000U) 1124 #define MDM_AP_DEVARCH_REVISION_SHIFT (16U) 1125 #define MDM_AP_DEVARCH_REVISION_WIDTH (4U) 1126 #define MDM_AP_DEVARCH_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DEVARCH_REVISION_SHIFT)) & MDM_AP_DEVARCH_REVISION_MASK) 1127 1128 #define MDM_AP_DEVARCH_PRESENT_MASK (0x100000U) 1129 #define MDM_AP_DEVARCH_PRESENT_SHIFT (20U) 1130 #define MDM_AP_DEVARCH_PRESENT_WIDTH (1U) 1131 #define MDM_AP_DEVARCH_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DEVARCH_PRESENT_SHIFT)) & MDM_AP_DEVARCH_PRESENT_MASK) 1132 1133 #define MDM_AP_DEVARCH_ARCHITECT_MASK (0xFFE00000U) 1134 #define MDM_AP_DEVARCH_ARCHITECT_SHIFT (21U) 1135 #define MDM_AP_DEVARCH_ARCHITECT_WIDTH (11U) 1136 #define MDM_AP_DEVARCH_ARCHITECT(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DEVARCH_ARCHITECT_SHIFT)) & MDM_AP_DEVARCH_ARCHITECT_MASK) 1137 /*! @} */ 1138 1139 /*! @name DEVTYPE - CoreSight Device Type Identifier Register */ 1140 /*! @{ */ 1141 1142 #define MDM_AP_DEVTYPE_MAJOR_MASK (0xFU) 1143 #define MDM_AP_DEVTYPE_MAJOR_SHIFT (0U) 1144 #define MDM_AP_DEVTYPE_MAJOR_WIDTH (4U) 1145 #define MDM_AP_DEVTYPE_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DEVTYPE_MAJOR_SHIFT)) & MDM_AP_DEVTYPE_MAJOR_MASK) 1146 1147 #define MDM_AP_DEVTYPE_SUB_MASK (0xF0U) 1148 #define MDM_AP_DEVTYPE_SUB_SHIFT (4U) 1149 #define MDM_AP_DEVTYPE_SUB_WIDTH (4U) 1150 #define MDM_AP_DEVTYPE_SUB(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_DEVTYPE_SUB_SHIFT)) & MDM_AP_DEVTYPE_SUB_MASK) 1151 /*! @} */ 1152 1153 /*! @name PIDR4 - CoreSight Peripheral Identification Register 4 */ 1154 /*! @{ */ 1155 1156 #define MDM_AP_PIDR4_DES_2_MASK (0xFU) 1157 #define MDM_AP_PIDR4_DES_2_SHIFT (0U) 1158 #define MDM_AP_PIDR4_DES_2_WIDTH (4U) 1159 #define MDM_AP_PIDR4_DES_2(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_PIDR4_DES_2_SHIFT)) & MDM_AP_PIDR4_DES_2_MASK) 1160 1161 #define MDM_AP_PIDR4_SIZE_MASK (0xF0U) 1162 #define MDM_AP_PIDR4_SIZE_SHIFT (4U) 1163 #define MDM_AP_PIDR4_SIZE_WIDTH (4U) 1164 #define MDM_AP_PIDR4_SIZE(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_PIDR4_SIZE_SHIFT)) & MDM_AP_PIDR4_SIZE_MASK) 1165 /*! @} */ 1166 1167 /*! @name PIDR0 - CoreSight Peripheral Identification Register 0 */ 1168 /*! @{ */ 1169 1170 #define MDM_AP_PIDR0_PART_0_MASK (0xFFU) 1171 #define MDM_AP_PIDR0_PART_0_SHIFT (0U) 1172 #define MDM_AP_PIDR0_PART_0_WIDTH (8U) 1173 #define MDM_AP_PIDR0_PART_0(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_PIDR0_PART_0_SHIFT)) & MDM_AP_PIDR0_PART_0_MASK) 1174 /*! @} */ 1175 1176 /*! @name PIDR1 - CoreSight Peripheral Identification Register 1 */ 1177 /*! @{ */ 1178 1179 #define MDM_AP_PIDR1_PART_1_MASK (0xFU) 1180 #define MDM_AP_PIDR1_PART_1_SHIFT (0U) 1181 #define MDM_AP_PIDR1_PART_1_WIDTH (4U) 1182 #define MDM_AP_PIDR1_PART_1(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_PIDR1_PART_1_SHIFT)) & MDM_AP_PIDR1_PART_1_MASK) 1183 1184 #define MDM_AP_PIDR1_DES_0_MASK (0xF0U) 1185 #define MDM_AP_PIDR1_DES_0_SHIFT (4U) 1186 #define MDM_AP_PIDR1_DES_0_WIDTH (4U) 1187 #define MDM_AP_PIDR1_DES_0(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_PIDR1_DES_0_SHIFT)) & MDM_AP_PIDR1_DES_0_MASK) 1188 /*! @} */ 1189 1190 /*! @name PIDR2 - CoreSight Peripheral Identification Register 2 */ 1191 /*! @{ */ 1192 1193 #define MDM_AP_PIDR2_DES_1_MASK (0x7U) 1194 #define MDM_AP_PIDR2_DES_1_SHIFT (0U) 1195 #define MDM_AP_PIDR2_DES_1_WIDTH (3U) 1196 #define MDM_AP_PIDR2_DES_1(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_PIDR2_DES_1_SHIFT)) & MDM_AP_PIDR2_DES_1_MASK) 1197 1198 #define MDM_AP_PIDR2_JEDEC_MASK (0x8U) 1199 #define MDM_AP_PIDR2_JEDEC_SHIFT (3U) 1200 #define MDM_AP_PIDR2_JEDEC_WIDTH (1U) 1201 #define MDM_AP_PIDR2_JEDEC(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_PIDR2_JEDEC_SHIFT)) & MDM_AP_PIDR2_JEDEC_MASK) 1202 1203 #define MDM_AP_PIDR2_REVISION_MASK (0xF0U) 1204 #define MDM_AP_PIDR2_REVISION_SHIFT (4U) 1205 #define MDM_AP_PIDR2_REVISION_WIDTH (4U) 1206 #define MDM_AP_PIDR2_REVISION(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_PIDR2_REVISION_SHIFT)) & MDM_AP_PIDR2_REVISION_MASK) 1207 /*! @} */ 1208 1209 /*! @name PIDR3 - CoreSight Peripheral Identification Register 3 */ 1210 /*! @{ */ 1211 1212 #define MDM_AP_PIDR3_CMOD_MASK (0xFU) 1213 #define MDM_AP_PIDR3_CMOD_SHIFT (0U) 1214 #define MDM_AP_PIDR3_CMOD_WIDTH (4U) 1215 #define MDM_AP_PIDR3_CMOD(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_PIDR3_CMOD_SHIFT)) & MDM_AP_PIDR3_CMOD_MASK) 1216 1217 #define MDM_AP_PIDR3_REVAND_MASK (0xF0U) 1218 #define MDM_AP_PIDR3_REVAND_SHIFT (4U) 1219 #define MDM_AP_PIDR3_REVAND_WIDTH (4U) 1220 #define MDM_AP_PIDR3_REVAND(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_PIDR3_REVAND_SHIFT)) & MDM_AP_PIDR3_REVAND_MASK) 1221 /*! @} */ 1222 1223 /*! @name CIDR0 - CoreSight Component Identification Register 0 */ 1224 /*! @{ */ 1225 1226 #define MDM_AP_CIDR0_PRMBL_0_MASK (0xFFU) 1227 #define MDM_AP_CIDR0_PRMBL_0_SHIFT (0U) 1228 #define MDM_AP_CIDR0_PRMBL_0_WIDTH (8U) 1229 #define MDM_AP_CIDR0_PRMBL_0(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CIDR0_PRMBL_0_SHIFT)) & MDM_AP_CIDR0_PRMBL_0_MASK) 1230 /*! @} */ 1231 1232 /*! @name CIDR1 - CoreSight Component Identification Register 1 */ 1233 /*! @{ */ 1234 1235 #define MDM_AP_CIDR1_PRMBL_1_MASK (0xFU) 1236 #define MDM_AP_CIDR1_PRMBL_1_SHIFT (0U) 1237 #define MDM_AP_CIDR1_PRMBL_1_WIDTH (4U) 1238 #define MDM_AP_CIDR1_PRMBL_1(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CIDR1_PRMBL_1_SHIFT)) & MDM_AP_CIDR1_PRMBL_1_MASK) 1239 1240 #define MDM_AP_CIDR1_CLASS_MASK (0xF0U) 1241 #define MDM_AP_CIDR1_CLASS_SHIFT (4U) 1242 #define MDM_AP_CIDR1_CLASS_WIDTH (4U) 1243 #define MDM_AP_CIDR1_CLASS(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CIDR1_CLASS_SHIFT)) & MDM_AP_CIDR1_CLASS_MASK) 1244 /*! @} */ 1245 1246 /*! @name CIDR2 - CoreSight Component Identification Register 2 */ 1247 /*! @{ */ 1248 1249 #define MDM_AP_CIDR2_PRMBL_2_MASK (0xFFU) 1250 #define MDM_AP_CIDR2_PRMBL_2_SHIFT (0U) 1251 #define MDM_AP_CIDR2_PRMBL_2_WIDTH (8U) 1252 #define MDM_AP_CIDR2_PRMBL_2(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CIDR2_PRMBL_2_SHIFT)) & MDM_AP_CIDR2_PRMBL_2_MASK) 1253 /*! @} */ 1254 1255 /*! @name CIDR3 - CoreSight Component Identification Register 3 */ 1256 /*! @{ */ 1257 1258 #define MDM_AP_CIDR3_PRMBL_3_MASK (0xFFU) 1259 #define MDM_AP_CIDR3_PRMBL_3_SHIFT (0U) 1260 #define MDM_AP_CIDR3_PRMBL_3_WIDTH (8U) 1261 #define MDM_AP_CIDR3_PRMBL_3(x) (((uint32_t)(((uint32_t)(x)) << MDM_AP_CIDR3_PRMBL_3_SHIFT)) & MDM_AP_CIDR3_PRMBL_3_MASK) 1262 /*! @} */ 1263 1264 /*! 1265 * @} 1266 */ /* end of group MDM_AP_Register_Masks */ 1267 1268 /*! 1269 * @} 1270 */ /* end of group MDM_AP_Peripheral_Access_Layer */ 1271 1272 #endif /* #if !defined(S32Z2_MDM_AP_H_) */ 1273
