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Searched refs:MCTRL (Results 1 – 25 of 103) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/pwm/
Dfsl_pwm.c321 base->MCTRL &= ~((uint16_t)1U << (PWM_MCTRL_IPOL_SHIFT + (uint16_t)subModule)); in PWM_Init()
324 base->MCTRL |= ((uint16_t)1U << (PWM_MCTRL_IPOL_SHIFT + (uint16_t)subModule)); in PWM_Init()
390 base->MCTRL &= ~((uint16_t)1U << (PWM_MCTRL_RUN_SHIFT + (uint16_t)subModule)); in PWM_Deinit()
613 if (0U != (base->MCTRL & PWM_MCTRL_LDOK(1UL << (uint8_t)subModule))) in PWM_SetupPwmPhaseShift()
615 base->MCTRL |= PWM_MCTRL_CLDOK(1UL << (uint8_t)subModule); in PWM_SetupPwmPhaseShift()
654 base->MCTRL |= PWM_MCTRL_LDOK(1UL << (uint8_t)subModule); in PWM_SetupPwmPhaseShift()
1174 if (0U != (base->MCTRL & PWM_MCTRL_LDOK(1UL << (uint8_t)subModule))) in PWM_SetOutputToIdle()
1176 base->MCTRL |= PWM_MCTRL_CLDOK(1UL << (uint8_t)subModule); in PWM_SetOutputToIdle()
1240 base->MCTRL |= PWM_MCTRL_LDOK(1UL << (uint8_t)subModule); in PWM_SetOutputToIdle()
1276 if (0U != (base->MCTRL & PWM_MCTRL_LDOK(1UL << (uint8_t)subModule))) in PWM_SetClockMode()
[all …]
Dfsl_pwm.h859 base->MCTRL |= PWM_MCTRL_RUN(subModulesToStart); in PWM_StartTimer()
874 base->MCTRL &= ~(PWM_MCTRL_RUN(subModulesToStop)); in PWM_StopTimer()
1062 base->MCTRL |= PWM_MCTRL_LDOK(subModulesToUpdate); in PWM_SetPwmLdok()
1066 base->MCTRL |= PWM_MCTRL_CLDOK(subModulesToUpdate); in PWM_SetPwmLdok()
/hal_nxp-latest/mcux/mcux-sdk/drivers/i3c/
Dfsl_i3c.c701 …base->MCTRL = (base->MCTRL & ~(I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_RDTERM_MASK… in I3C_MasterEmitStop()
1281 mctrlVal = base->MCTRL; in I3C_MasterRepeatedStartWithRxSize()
1287 base->MCTRL = mctrlVal; in I3C_MasterRepeatedStartWithRxSize()
1317 uint32_t mctrlReg = base->MCTRL; in I3C_MasterEmitRequest()
1328 base->MCTRL = mctrlReg; in I3C_MasterEmitRequest()
1468 base->MCTRL |= I3C_MCTRL_RDTERM(1U); in I3C_MasterReceive()
1701 …base->MCTRL = (base->MCTRL & ~(I3C_MCTRL_REQUEST_MASK | I3C_MCTRL_DIR_MASK | I3C_MCTRL_RDTERM_MASK… in I3C_MasterProcessDAASpecifiedBaudrate()
2244 base->MCTRL |= I3C_MCTRL_RDTERM(1UL); in I3C_TransferStateMachineTransferDataState()
2475 base->MCTRL |= I3C_MCTRL_RDTERM(handle->remainingBytes); in I3C_InitTransferStateMachine()
2520 base->MCTRL &= ~I3C_MCTRL_IBIRESP_MASK; in I3C_MasterTransferNonBlocking()
[all …]
Dfsl_i3c_edma.c92 i3cHandle->base->MCTRL |= I3C_MCTRL_RDTERM(1U); in I3C_MasterTransferEDMACallbackRx()
600 base->MCTRL &= ~I3C_MCTRL_IBIRESP_MASK; in I3C_MasterTransferEDMA()
601 base->MCTRL |= I3C_MCTRL_IBIRESP(transfer->ibiResponse); in I3C_MasterTransferEDMA()
Dfsl_i3c_dma.c136 i3cHandle->base->MCTRL |= I3C_MCTRL_RDTERM(1U); in I3C_MasterTransferDMACallbackRx()
737 base->MCTRL &= ~I3C_MCTRL_IBIRESP_MASK; in I3C_MasterTransferDMA()
738 base->MCTRL |= I3C_MCTRL_IBIRESP(transfer->ibiResponse); in I3C_MasterTransferDMA()
Dfsl_i3c.h1252 uint32_t ctrlVal = base->MCTRL; in I3C_MasterEmitIBIResponse()
1255 base->MCTRL = ctrlVal; in I3C_MasterEmitIBIResponse()
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_I3C.h106 __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC865/
DLPC865.h4690 …__IO uint32_t MCTRL; /**< Controller Main Control Register, offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC864/
DLPC864.h4688 …__IO uint32_t MCTRL; /**< Controller Main Control Register, offset: 0x… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/
DMCXA142.h12291 __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ member
23407 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/
DMCXA143.h12291 __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ member
23407 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/
DMCXA153.h12291 __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ member
23407 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/
DMCXA152.h12291 __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ member
23407 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h15350 __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ member
30648 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/
DMCXA145.h15350 __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ member
30648 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/
DMCXA144.h15350 __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ member
30648 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/
DMCXA156.h15354 __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ member
31266 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/
DMCXA154.h15354 __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ member
31266 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/
DMCXA155.h15354 __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ member
31266 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h21984 __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ member
34412 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h21984 __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ member
34412 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV56F24/
DMKV56F24.h19954 __IO uint16_t MCTRL; /**< Master Control Register 0, offset: 0x188 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV58F24/
DMKV58F24.h21720 __IO uint16_t MCTRL; /**< Master Control Register 0, offset: 0x188 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h21983 __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ member
36635 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/
DMCXN236.h24323 __IO uint32_t MCTRL; /**< Controller Control, offset: 0x84 */ member
46496 __IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */ member

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