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Searched refs:MCG_C2_RANGE0_MASK (Results 1 – 25 of 77) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MKM33ZA5/
Dsystem_MKM33ZA5.c103 … if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
168 … if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34Z7/
Dsystem_MKM34Z7.c108 … if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) in SystemCoreClockUpdate()
189 … if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34ZA5/
Dsystem_MKM34ZA5.c99 … if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
164 … if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM14ZA5/
Dsystem_MKM14ZA5.c101 … if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
166 … if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM35Z7/
Dsystem_MKM35Z7.c109 … if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
174 … if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW41Z4/drivers/
Dfsl_clock.c73 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
74 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
115 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z7/drivers/
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
69 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV11Z7/drivers/
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
69 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z1287/drivers/
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
69 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK02F12810/drivers/
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
69 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F12810/drivers/
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
69 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV30F12810/drivers/
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
69 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F12810/drivers/
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
69 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL25Z4/
Dsystem_MKL25Z4.c144 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) { in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL25Z4/drivers/
Dfsl_clock.c45 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
46 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
87 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW22D5/drivers/
Dfsl_clock.c45 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
46 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
87 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW24D5/drivers/
Dfsl_clock.c45 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
46 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
87 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW22D5/
Dsystem_MKW22D5.c157 … if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW24D5/
Dsystem_MKW24D5.c157 … if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34Z7/drivers/
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
69 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV58F24/drivers/
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
69 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV56F24/drivers/
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
69 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F51212/drivers/
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
69 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F25612/drivers/
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
69 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F12/drivers/
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK macro
69 #define OSC_MODE_MASK (MCG_C2_EREFS0_MASK | MCG_C2_HGO0_MASK | MCG_C2_RANGE0_MASK)

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