1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_L_VFCCU.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_L_VFCCU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_L_VFCCU_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_L_VFCCU_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- L_VFCCU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup L_VFCCU_Peripheral_Access_Layer L_VFCCU Peripheral Access Layer 68 * @{ 69 */ 70 71 /** L_VFCCU - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t GDFHID_C0; /**< Global DID-FHID Map, offset: 0x0 */ 74 __IO uint32_t GDFHID_C1; /**< Global DID-FHID Map, offset: 0x4 */ 75 uint8_t RESERVED_0[24]; 76 __IO uint32_t GFLTPO_C0; /**< Global Fault Polarity, offset: 0x20 */ 77 uint8_t RESERVED_1[60]; 78 __IO uint32_t GFLTRC_C0; /**< Global Fault Recovery, offset: 0x60 */ 79 uint8_t RESERVED_2[60]; 80 __IO uint32_t GFLTOVDC0; /**< Global Fault Overflow Detection, offset: 0xA0 */ 81 uint8_t RESERVED_3[140]; 82 __IO uint32_t GCTRL; /**< Global Space Control, offset: 0x130 */ 83 __IO uint32_t GINTOVFS; /**< Global DID FSM Status, offset: 0x134 */ 84 uint8_t RESERVED_4[428]; 85 __IO uint32_t GDBGCFG; /**< Global Debug, offset: 0x2E4 */ 86 __I uint32_t GDBGSTAT; /**< Global Debug Status, offset: 0x2E8 */ 87 uint8_t RESERVED_5[64788]; 88 __IO uint32_t FHCFG0; /**< Fault Handler, offset: 0x10000 */ 89 __I uint32_t FHSRVDS0; /**< Fault Handler Status, offset: 0x10004 */ 90 uint8_t RESERVED_6[8]; 91 __IO uint32_t FHFLTENC00; /**< Fault Enable, offset: 0x10010 */ 92 uint8_t RESERVED_7[60]; 93 __IO uint32_t FHFLTS00; /**< Fault Status, offset: 0x10050 */ 94 uint8_t RESERVED_8[60]; 95 __IO uint32_t FHFLTRKC00; /**< Fault Reaction Set Configuration, offset: 0x10090 */ 96 __IO uint32_t FHFLTRKC01; /**< Fault Reaction Set Configuration, offset: 0x10094 */ 97 __IO uint32_t FHFLTRKC02; /**< Fault Reaction Set Configuration, offset: 0x10098 */ 98 __IO uint32_t FHFLTRKC03; /**< Fault Reaction Set Configuration, offset: 0x1009C, available only on: L_VFCCU_3, L_VFCCU_5 (missing on L_VFCCU_0, L_VFCCU_1, L_VFCCU_2, L_VFCCU_4, L_VFCCU_6) */ 99 uint8_t RESERVED_9[240]; 100 __IO uint32_t FHIMRKC0_00; /**< Immediate Reaction Configuration, offset: 0x10190 */ 101 uint8_t RESERVED_10[12]; 102 __IO uint32_t FHIMRKC0_10; /**< Immediate Reaction Configuration, offset: 0x101A0 */ 103 uint8_t RESERVED_11[12]; 104 __IO uint32_t FHIMRKC0_20; /**< Immediate Reaction Configuration, offset: 0x101B0 */ 105 uint8_t RESERVED_12[12]; 106 __IO uint32_t FHIMRKC0_30; /**< Immediate Reaction Configuration, offset: 0x101C0 */ 107 uint8_t RESERVED_13[12]; 108 __IO uint32_t FHIMRKC0_40; /**< Immediate Reaction Configuration, offset: 0x101D0 */ 109 uint8_t RESERVED_14[12]; 110 __IO uint32_t FHIMRKC0_50; /**< Immediate Reaction Configuration, offset: 0x101E0 */ 111 } L_VFCCU_Type, *L_VFCCU_MemMapPtr; 112 113 /** Number of instances of the L_VFCCU module. */ 114 #define L_VFCCU_INSTANCE_COUNT (7u) 115 116 /* L_VFCCU - Peripheral instance base addresses */ 117 /** Peripheral L_VFCCU_0 base address */ 118 #define IP_L_VFCCU_0_BASE (0x40410000u) 119 /** Peripheral L_VFCCU_0 base pointer */ 120 #define IP_L_VFCCU_0 ((L_VFCCU_Type *)IP_L_VFCCU_0_BASE) 121 /** Peripheral L_VFCCU_1 base address */ 122 #define IP_L_VFCCU_1_BASE (0x40C10000u) 123 /** Peripheral L_VFCCU_1 base pointer */ 124 #define IP_L_VFCCU_1 ((L_VFCCU_Type *)IP_L_VFCCU_1_BASE) 125 /** Peripheral L_VFCCU_2 base address */ 126 #define IP_L_VFCCU_2_BASE (0x410E0000u) 127 /** Peripheral L_VFCCU_2 base pointer */ 128 #define IP_L_VFCCU_2 ((L_VFCCU_Type *)IP_L_VFCCU_2_BASE) 129 /** Peripheral L_VFCCU_3 base address */ 130 #define IP_L_VFCCU_3_BASE (0x41C10000u) 131 /** Peripheral L_VFCCU_3 base pointer */ 132 #define IP_L_VFCCU_3 ((L_VFCCU_Type *)IP_L_VFCCU_3_BASE) 133 /** Peripheral L_VFCCU_4 base address */ 134 #define IP_L_VFCCU_4_BASE (0x42410000u) 135 /** Peripheral L_VFCCU_4 base pointer */ 136 #define IP_L_VFCCU_4 ((L_VFCCU_Type *)IP_L_VFCCU_4_BASE) 137 /** Peripheral L_VFCCU_5 base address */ 138 #define IP_L_VFCCU_5_BASE (0x42C10000u) 139 /** Peripheral L_VFCCU_5 base pointer */ 140 #define IP_L_VFCCU_5 ((L_VFCCU_Type *)IP_L_VFCCU_5_BASE) 141 /** Peripheral L_VFCCU_6 base address */ 142 #define IP_L_VFCCU_6_BASE (0x440E0000u) 143 /** Peripheral L_VFCCU_6 base pointer */ 144 #define IP_L_VFCCU_6 ((L_VFCCU_Type *)IP_L_VFCCU_6_BASE) 145 /** Array initializer of L_VFCCU peripheral base addresses */ 146 #define IP_L_VFCCU_BASE_ADDRS { IP_L_VFCCU_0_BASE, IP_L_VFCCU_1_BASE, IP_L_VFCCU_2_BASE, IP_L_VFCCU_3_BASE, IP_L_VFCCU_4_BASE, IP_L_VFCCU_5_BASE, IP_L_VFCCU_6_BASE } 147 /** Array initializer of L_VFCCU peripheral base pointers */ 148 #define IP_L_VFCCU_BASE_PTRS { IP_L_VFCCU_0, IP_L_VFCCU_1, IP_L_VFCCU_2, IP_L_VFCCU_3, IP_L_VFCCU_4, IP_L_VFCCU_5, IP_L_VFCCU_6 } 149 150 /* ---------------------------------------------------------------------------- 151 -- L_VFCCU Register Masks 152 ---------------------------------------------------------------------------- */ 153 154 /*! 155 * @addtogroup L_VFCCU_Register_Masks L_VFCCU Register Masks 156 * @{ 157 */ 158 159 /*! @name GDFHID_C0 - Global DID-FHID Map */ 160 /*! @{ */ 161 162 #define L_VFCCU_GDFHID_C0_FHDID0_MASK (0x7U) 163 #define L_VFCCU_GDFHID_C0_FHDID0_SHIFT (0U) 164 #define L_VFCCU_GDFHID_C0_FHDID0_WIDTH (3U) 165 #define L_VFCCU_GDFHID_C0_FHDID0(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GDFHID_C0_FHDID0_SHIFT)) & L_VFCCU_GDFHID_C0_FHDID0_MASK) 166 167 #define L_VFCCU_GDFHID_C0_FHDID1_MASK (0x70U) 168 #define L_VFCCU_GDFHID_C0_FHDID1_SHIFT (4U) 169 #define L_VFCCU_GDFHID_C0_FHDID1_WIDTH (3U) 170 #define L_VFCCU_GDFHID_C0_FHDID1(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GDFHID_C0_FHDID1_SHIFT)) & L_VFCCU_GDFHID_C0_FHDID1_MASK) 171 172 #define L_VFCCU_GDFHID_C0_FHDID2_MASK (0x700U) 173 #define L_VFCCU_GDFHID_C0_FHDID2_SHIFT (8U) 174 #define L_VFCCU_GDFHID_C0_FHDID2_WIDTH (3U) 175 #define L_VFCCU_GDFHID_C0_FHDID2(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GDFHID_C0_FHDID2_SHIFT)) & L_VFCCU_GDFHID_C0_FHDID2_MASK) 176 177 #define L_VFCCU_GDFHID_C0_FHDID3_MASK (0x7000U) 178 #define L_VFCCU_GDFHID_C0_FHDID3_SHIFT (12U) 179 #define L_VFCCU_GDFHID_C0_FHDID3_WIDTH (3U) 180 #define L_VFCCU_GDFHID_C0_FHDID3(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GDFHID_C0_FHDID3_SHIFT)) & L_VFCCU_GDFHID_C0_FHDID3_MASK) 181 182 #define L_VFCCU_GDFHID_C0_FHDID4_MASK (0x70000U) 183 #define L_VFCCU_GDFHID_C0_FHDID4_SHIFT (16U) 184 #define L_VFCCU_GDFHID_C0_FHDID4_WIDTH (3U) 185 #define L_VFCCU_GDFHID_C0_FHDID4(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GDFHID_C0_FHDID4_SHIFT)) & L_VFCCU_GDFHID_C0_FHDID4_MASK) 186 187 #define L_VFCCU_GDFHID_C0_FHDID5_MASK (0x700000U) 188 #define L_VFCCU_GDFHID_C0_FHDID5_SHIFT (20U) 189 #define L_VFCCU_GDFHID_C0_FHDID5_WIDTH (3U) 190 #define L_VFCCU_GDFHID_C0_FHDID5(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GDFHID_C0_FHDID5_SHIFT)) & L_VFCCU_GDFHID_C0_FHDID5_MASK) 191 192 #define L_VFCCU_GDFHID_C0_FHDID6_MASK (0x7000000U) 193 #define L_VFCCU_GDFHID_C0_FHDID6_SHIFT (24U) 194 #define L_VFCCU_GDFHID_C0_FHDID6_WIDTH (3U) 195 #define L_VFCCU_GDFHID_C0_FHDID6(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GDFHID_C0_FHDID6_SHIFT)) & L_VFCCU_GDFHID_C0_FHDID6_MASK) 196 197 #define L_VFCCU_GDFHID_C0_FHDID7_MASK (0x70000000U) 198 #define L_VFCCU_GDFHID_C0_FHDID7_SHIFT (28U) 199 #define L_VFCCU_GDFHID_C0_FHDID7_WIDTH (3U) 200 #define L_VFCCU_GDFHID_C0_FHDID7(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GDFHID_C0_FHDID7_SHIFT)) & L_VFCCU_GDFHID_C0_FHDID7_MASK) 201 /*! @} */ 202 203 /*! @name GDFHID_C1 - Global DID-FHID Map */ 204 /*! @{ */ 205 206 #define L_VFCCU_GDFHID_C1_FHDID8_MASK (0x7U) 207 #define L_VFCCU_GDFHID_C1_FHDID8_SHIFT (0U) 208 #define L_VFCCU_GDFHID_C1_FHDID8_WIDTH (3U) 209 #define L_VFCCU_GDFHID_C1_FHDID8(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GDFHID_C1_FHDID8_SHIFT)) & L_VFCCU_GDFHID_C1_FHDID8_MASK) 210 211 #define L_VFCCU_GDFHID_C1_FHDID9_MASK (0x70U) 212 #define L_VFCCU_GDFHID_C1_FHDID9_SHIFT (4U) 213 #define L_VFCCU_GDFHID_C1_FHDID9_WIDTH (3U) 214 #define L_VFCCU_GDFHID_C1_FHDID9(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GDFHID_C1_FHDID9_SHIFT)) & L_VFCCU_GDFHID_C1_FHDID9_MASK) 215 216 #define L_VFCCU_GDFHID_C1_FHDID10_MASK (0x700U) 217 #define L_VFCCU_GDFHID_C1_FHDID10_SHIFT (8U) 218 #define L_VFCCU_GDFHID_C1_FHDID10_WIDTH (3U) 219 #define L_VFCCU_GDFHID_C1_FHDID10(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GDFHID_C1_FHDID10_SHIFT)) & L_VFCCU_GDFHID_C1_FHDID10_MASK) 220 221 #define L_VFCCU_GDFHID_C1_FHDID11_MASK (0x7000U) 222 #define L_VFCCU_GDFHID_C1_FHDID11_SHIFT (12U) 223 #define L_VFCCU_GDFHID_C1_FHDID11_WIDTH (3U) 224 #define L_VFCCU_GDFHID_C1_FHDID11(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GDFHID_C1_FHDID11_SHIFT)) & L_VFCCU_GDFHID_C1_FHDID11_MASK) 225 226 #define L_VFCCU_GDFHID_C1_FHDID12_MASK (0x70000U) 227 #define L_VFCCU_GDFHID_C1_FHDID12_SHIFT (16U) 228 #define L_VFCCU_GDFHID_C1_FHDID12_WIDTH (3U) 229 #define L_VFCCU_GDFHID_C1_FHDID12(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GDFHID_C1_FHDID12_SHIFT)) & L_VFCCU_GDFHID_C1_FHDID12_MASK) 230 231 #define L_VFCCU_GDFHID_C1_FHDID13_MASK (0x700000U) 232 #define L_VFCCU_GDFHID_C1_FHDID13_SHIFT (20U) 233 #define L_VFCCU_GDFHID_C1_FHDID13_WIDTH (3U) 234 #define L_VFCCU_GDFHID_C1_FHDID13(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GDFHID_C1_FHDID13_SHIFT)) & L_VFCCU_GDFHID_C1_FHDID13_MASK) 235 236 #define L_VFCCU_GDFHID_C1_FHDID14_MASK (0x7000000U) 237 #define L_VFCCU_GDFHID_C1_FHDID14_SHIFT (24U) 238 #define L_VFCCU_GDFHID_C1_FHDID14_WIDTH (3U) 239 #define L_VFCCU_GDFHID_C1_FHDID14(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GDFHID_C1_FHDID14_SHIFT)) & L_VFCCU_GDFHID_C1_FHDID14_MASK) 240 241 #define L_VFCCU_GDFHID_C1_FHDID15_MASK (0x70000000U) 242 #define L_VFCCU_GDFHID_C1_FHDID15_SHIFT (28U) 243 #define L_VFCCU_GDFHID_C1_FHDID15_WIDTH (3U) 244 #define L_VFCCU_GDFHID_C1_FHDID15(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GDFHID_C1_FHDID15_SHIFT)) & L_VFCCU_GDFHID_C1_FHDID15_MASK) 245 /*! @} */ 246 247 /*! @name GFLTPO_C0 - Global Fault Polarity */ 248 /*! @{ */ 249 250 #define L_VFCCU_GFLTPO_C0_PS0_MASK (0x1U) 251 #define L_VFCCU_GFLTPO_C0_PS0_SHIFT (0U) 252 #define L_VFCCU_GFLTPO_C0_PS0_WIDTH (1U) 253 #define L_VFCCU_GFLTPO_C0_PS0(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS0_SHIFT)) & L_VFCCU_GFLTPO_C0_PS0_MASK) 254 255 #define L_VFCCU_GFLTPO_C0_PS1_MASK (0x2U) 256 #define L_VFCCU_GFLTPO_C0_PS1_SHIFT (1U) 257 #define L_VFCCU_GFLTPO_C0_PS1_WIDTH (1U) 258 #define L_VFCCU_GFLTPO_C0_PS1(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS1_SHIFT)) & L_VFCCU_GFLTPO_C0_PS1_MASK) 259 260 #define L_VFCCU_GFLTPO_C0_PS2_MASK (0x4U) 261 #define L_VFCCU_GFLTPO_C0_PS2_SHIFT (2U) 262 #define L_VFCCU_GFLTPO_C0_PS2_WIDTH (1U) 263 #define L_VFCCU_GFLTPO_C0_PS2(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS2_SHIFT)) & L_VFCCU_GFLTPO_C0_PS2_MASK) 264 265 #define L_VFCCU_GFLTPO_C0_PS3_MASK (0x8U) 266 #define L_VFCCU_GFLTPO_C0_PS3_SHIFT (3U) 267 #define L_VFCCU_GFLTPO_C0_PS3_WIDTH (1U) 268 #define L_VFCCU_GFLTPO_C0_PS3(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS3_SHIFT)) & L_VFCCU_GFLTPO_C0_PS3_MASK) 269 270 #define L_VFCCU_GFLTPO_C0_PS4_MASK (0x10U) 271 #define L_VFCCU_GFLTPO_C0_PS4_SHIFT (4U) 272 #define L_VFCCU_GFLTPO_C0_PS4_WIDTH (1U) 273 #define L_VFCCU_GFLTPO_C0_PS4(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS4_SHIFT)) & L_VFCCU_GFLTPO_C0_PS4_MASK) 274 275 #define L_VFCCU_GFLTPO_C0_PS5_MASK (0x20U) 276 #define L_VFCCU_GFLTPO_C0_PS5_SHIFT (5U) 277 #define L_VFCCU_GFLTPO_C0_PS5_WIDTH (1U) 278 #define L_VFCCU_GFLTPO_C0_PS5(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS5_SHIFT)) & L_VFCCU_GFLTPO_C0_PS5_MASK) 279 280 #define L_VFCCU_GFLTPO_C0_PS6_MASK (0x40U) 281 #define L_VFCCU_GFLTPO_C0_PS6_SHIFT (6U) 282 #define L_VFCCU_GFLTPO_C0_PS6_WIDTH (1U) 283 #define L_VFCCU_GFLTPO_C0_PS6(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS6_SHIFT)) & L_VFCCU_GFLTPO_C0_PS6_MASK) 284 285 #define L_VFCCU_GFLTPO_C0_PS7_MASK (0x80U) 286 #define L_VFCCU_GFLTPO_C0_PS7_SHIFT (7U) 287 #define L_VFCCU_GFLTPO_C0_PS7_WIDTH (1U) 288 #define L_VFCCU_GFLTPO_C0_PS7(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS7_SHIFT)) & L_VFCCU_GFLTPO_C0_PS7_MASK) 289 290 #define L_VFCCU_GFLTPO_C0_PS8_MASK (0x100U) 291 #define L_VFCCU_GFLTPO_C0_PS8_SHIFT (8U) 292 #define L_VFCCU_GFLTPO_C0_PS8_WIDTH (1U) 293 #define L_VFCCU_GFLTPO_C0_PS8(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS8_SHIFT)) & L_VFCCU_GFLTPO_C0_PS8_MASK) 294 295 #define L_VFCCU_GFLTPO_C0_PS9_MASK (0x200U) 296 #define L_VFCCU_GFLTPO_C0_PS9_SHIFT (9U) 297 #define L_VFCCU_GFLTPO_C0_PS9_WIDTH (1U) 298 #define L_VFCCU_GFLTPO_C0_PS9(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS9_SHIFT)) & L_VFCCU_GFLTPO_C0_PS9_MASK) 299 300 #define L_VFCCU_GFLTPO_C0_PS10_MASK (0x400U) 301 #define L_VFCCU_GFLTPO_C0_PS10_SHIFT (10U) 302 #define L_VFCCU_GFLTPO_C0_PS10_WIDTH (1U) 303 #define L_VFCCU_GFLTPO_C0_PS10(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS10_SHIFT)) & L_VFCCU_GFLTPO_C0_PS10_MASK) 304 305 #define L_VFCCU_GFLTPO_C0_PS11_MASK (0x800U) 306 #define L_VFCCU_GFLTPO_C0_PS11_SHIFT (11U) 307 #define L_VFCCU_GFLTPO_C0_PS11_WIDTH (1U) 308 #define L_VFCCU_GFLTPO_C0_PS11(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS11_SHIFT)) & L_VFCCU_GFLTPO_C0_PS11_MASK) 309 310 #define L_VFCCU_GFLTPO_C0_PS12_MASK (0x1000U) 311 #define L_VFCCU_GFLTPO_C0_PS12_SHIFT (12U) 312 #define L_VFCCU_GFLTPO_C0_PS12_WIDTH (1U) 313 #define L_VFCCU_GFLTPO_C0_PS12(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS12_SHIFT)) & L_VFCCU_GFLTPO_C0_PS12_MASK) 314 315 #define L_VFCCU_GFLTPO_C0_PS13_MASK (0x2000U) 316 #define L_VFCCU_GFLTPO_C0_PS13_SHIFT (13U) 317 #define L_VFCCU_GFLTPO_C0_PS13_WIDTH (1U) 318 #define L_VFCCU_GFLTPO_C0_PS13(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS13_SHIFT)) & L_VFCCU_GFLTPO_C0_PS13_MASK) 319 320 #define L_VFCCU_GFLTPO_C0_PS14_MASK (0x4000U) 321 #define L_VFCCU_GFLTPO_C0_PS14_SHIFT (14U) 322 #define L_VFCCU_GFLTPO_C0_PS14_WIDTH (1U) 323 #define L_VFCCU_GFLTPO_C0_PS14(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS14_SHIFT)) & L_VFCCU_GFLTPO_C0_PS14_MASK) 324 325 #define L_VFCCU_GFLTPO_C0_PS15_MASK (0x8000U) 326 #define L_VFCCU_GFLTPO_C0_PS15_SHIFT (15U) 327 #define L_VFCCU_GFLTPO_C0_PS15_WIDTH (1U) 328 #define L_VFCCU_GFLTPO_C0_PS15(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS15_SHIFT)) & L_VFCCU_GFLTPO_C0_PS15_MASK) 329 330 #define L_VFCCU_GFLTPO_C0_PS16_MASK (0x10000U) 331 #define L_VFCCU_GFLTPO_C0_PS16_SHIFT (16U) 332 #define L_VFCCU_GFLTPO_C0_PS16_WIDTH (1U) 333 #define L_VFCCU_GFLTPO_C0_PS16(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS16_SHIFT)) & L_VFCCU_GFLTPO_C0_PS16_MASK) 334 335 #define L_VFCCU_GFLTPO_C0_PS17_MASK (0x20000U) 336 #define L_VFCCU_GFLTPO_C0_PS17_SHIFT (17U) 337 #define L_VFCCU_GFLTPO_C0_PS17_WIDTH (1U) 338 #define L_VFCCU_GFLTPO_C0_PS17(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS17_SHIFT)) & L_VFCCU_GFLTPO_C0_PS17_MASK) 339 340 #define L_VFCCU_GFLTPO_C0_PS18_MASK (0x40000U) 341 #define L_VFCCU_GFLTPO_C0_PS18_SHIFT (18U) 342 #define L_VFCCU_GFLTPO_C0_PS18_WIDTH (1U) 343 #define L_VFCCU_GFLTPO_C0_PS18(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS18_SHIFT)) & L_VFCCU_GFLTPO_C0_PS18_MASK) 344 345 #define L_VFCCU_GFLTPO_C0_PS19_MASK (0x80000U) 346 #define L_VFCCU_GFLTPO_C0_PS19_SHIFT (19U) 347 #define L_VFCCU_GFLTPO_C0_PS19_WIDTH (1U) 348 #define L_VFCCU_GFLTPO_C0_PS19(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS19_SHIFT)) & L_VFCCU_GFLTPO_C0_PS19_MASK) 349 350 #define L_VFCCU_GFLTPO_C0_PS20_MASK (0x100000U) 351 #define L_VFCCU_GFLTPO_C0_PS20_SHIFT (20U) 352 #define L_VFCCU_GFLTPO_C0_PS20_WIDTH (1U) 353 #define L_VFCCU_GFLTPO_C0_PS20(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS20_SHIFT)) & L_VFCCU_GFLTPO_C0_PS20_MASK) 354 355 #define L_VFCCU_GFLTPO_C0_PS21_MASK (0x200000U) 356 #define L_VFCCU_GFLTPO_C0_PS21_SHIFT (21U) 357 #define L_VFCCU_GFLTPO_C0_PS21_WIDTH (1U) 358 #define L_VFCCU_GFLTPO_C0_PS21(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS21_SHIFT)) & L_VFCCU_GFLTPO_C0_PS21_MASK) 359 360 #define L_VFCCU_GFLTPO_C0_PS22_MASK (0x400000U) 361 #define L_VFCCU_GFLTPO_C0_PS22_SHIFT (22U) 362 #define L_VFCCU_GFLTPO_C0_PS22_WIDTH (1U) 363 #define L_VFCCU_GFLTPO_C0_PS22(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS22_SHIFT)) & L_VFCCU_GFLTPO_C0_PS22_MASK) 364 365 #define L_VFCCU_GFLTPO_C0_PS23_MASK (0x800000U) 366 #define L_VFCCU_GFLTPO_C0_PS23_SHIFT (23U) 367 #define L_VFCCU_GFLTPO_C0_PS23_WIDTH (1U) 368 #define L_VFCCU_GFLTPO_C0_PS23(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS23_SHIFT)) & L_VFCCU_GFLTPO_C0_PS23_MASK) 369 370 #define L_VFCCU_GFLTPO_C0_PS24_MASK (0x1000000U) 371 #define L_VFCCU_GFLTPO_C0_PS24_SHIFT (24U) 372 #define L_VFCCU_GFLTPO_C0_PS24_WIDTH (1U) 373 #define L_VFCCU_GFLTPO_C0_PS24(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS24_SHIFT)) & L_VFCCU_GFLTPO_C0_PS24_MASK) 374 375 #define L_VFCCU_GFLTPO_C0_PS25_MASK (0x2000000U) 376 #define L_VFCCU_GFLTPO_C0_PS25_SHIFT (25U) 377 #define L_VFCCU_GFLTPO_C0_PS25_WIDTH (1U) 378 #define L_VFCCU_GFLTPO_C0_PS25(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS25_SHIFT)) & L_VFCCU_GFLTPO_C0_PS25_MASK) 379 380 #define L_VFCCU_GFLTPO_C0_PS26_MASK (0x4000000U) 381 #define L_VFCCU_GFLTPO_C0_PS26_SHIFT (26U) 382 #define L_VFCCU_GFLTPO_C0_PS26_WIDTH (1U) 383 #define L_VFCCU_GFLTPO_C0_PS26(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS26_SHIFT)) & L_VFCCU_GFLTPO_C0_PS26_MASK) 384 385 #define L_VFCCU_GFLTPO_C0_PS27_MASK (0x8000000U) 386 #define L_VFCCU_GFLTPO_C0_PS27_SHIFT (27U) 387 #define L_VFCCU_GFLTPO_C0_PS27_WIDTH (1U) 388 #define L_VFCCU_GFLTPO_C0_PS27(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS27_SHIFT)) & L_VFCCU_GFLTPO_C0_PS27_MASK) 389 390 #define L_VFCCU_GFLTPO_C0_PS28_MASK (0x10000000U) 391 #define L_VFCCU_GFLTPO_C0_PS28_SHIFT (28U) 392 #define L_VFCCU_GFLTPO_C0_PS28_WIDTH (1U) 393 #define L_VFCCU_GFLTPO_C0_PS28(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS28_SHIFT)) & L_VFCCU_GFLTPO_C0_PS28_MASK) 394 395 #define L_VFCCU_GFLTPO_C0_PS29_MASK (0x20000000U) 396 #define L_VFCCU_GFLTPO_C0_PS29_SHIFT (29U) 397 #define L_VFCCU_GFLTPO_C0_PS29_WIDTH (1U) 398 #define L_VFCCU_GFLTPO_C0_PS29(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS29_SHIFT)) & L_VFCCU_GFLTPO_C0_PS29_MASK) 399 400 #define L_VFCCU_GFLTPO_C0_PS30_MASK (0x40000000U) 401 #define L_VFCCU_GFLTPO_C0_PS30_SHIFT (30U) 402 #define L_VFCCU_GFLTPO_C0_PS30_WIDTH (1U) 403 #define L_VFCCU_GFLTPO_C0_PS30(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS30_SHIFT)) & L_VFCCU_GFLTPO_C0_PS30_MASK) 404 405 #define L_VFCCU_GFLTPO_C0_PS31_MASK (0x80000000U) 406 #define L_VFCCU_GFLTPO_C0_PS31_SHIFT (31U) 407 #define L_VFCCU_GFLTPO_C0_PS31_WIDTH (1U) 408 #define L_VFCCU_GFLTPO_C0_PS31(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTPO_C0_PS31_SHIFT)) & L_VFCCU_GFLTPO_C0_PS31_MASK) 409 /*! @} */ 410 411 /*! @name GFLTRC_C0 - Global Fault Recovery */ 412 /*! @{ */ 413 414 #define L_VFCCU_GFLTRC_C0_RHWSW0_MASK (0x1U) 415 #define L_VFCCU_GFLTRC_C0_RHWSW0_SHIFT (0U) 416 #define L_VFCCU_GFLTRC_C0_RHWSW0_WIDTH (1U) 417 #define L_VFCCU_GFLTRC_C0_RHWSW0(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW0_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW0_MASK) 418 419 #define L_VFCCU_GFLTRC_C0_RHWSW1_MASK (0x2U) 420 #define L_VFCCU_GFLTRC_C0_RHWSW1_SHIFT (1U) 421 #define L_VFCCU_GFLTRC_C0_RHWSW1_WIDTH (1U) 422 #define L_VFCCU_GFLTRC_C0_RHWSW1(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW1_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW1_MASK) 423 424 #define L_VFCCU_GFLTRC_C0_RHWSW2_MASK (0x4U) 425 #define L_VFCCU_GFLTRC_C0_RHWSW2_SHIFT (2U) 426 #define L_VFCCU_GFLTRC_C0_RHWSW2_WIDTH (1U) 427 #define L_VFCCU_GFLTRC_C0_RHWSW2(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW2_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW2_MASK) 428 429 #define L_VFCCU_GFLTRC_C0_RHWSW3_MASK (0x8U) 430 #define L_VFCCU_GFLTRC_C0_RHWSW3_SHIFT (3U) 431 #define L_VFCCU_GFLTRC_C0_RHWSW3_WIDTH (1U) 432 #define L_VFCCU_GFLTRC_C0_RHWSW3(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW3_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW3_MASK) 433 434 #define L_VFCCU_GFLTRC_C0_RHWSW4_MASK (0x10U) 435 #define L_VFCCU_GFLTRC_C0_RHWSW4_SHIFT (4U) 436 #define L_VFCCU_GFLTRC_C0_RHWSW4_WIDTH (1U) 437 #define L_VFCCU_GFLTRC_C0_RHWSW4(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW4_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW4_MASK) 438 439 #define L_VFCCU_GFLTRC_C0_RHWSW5_MASK (0x20U) 440 #define L_VFCCU_GFLTRC_C0_RHWSW5_SHIFT (5U) 441 #define L_VFCCU_GFLTRC_C0_RHWSW5_WIDTH (1U) 442 #define L_VFCCU_GFLTRC_C0_RHWSW5(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW5_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW5_MASK) 443 444 #define L_VFCCU_GFLTRC_C0_RHWSW6_MASK (0x40U) 445 #define L_VFCCU_GFLTRC_C0_RHWSW6_SHIFT (6U) 446 #define L_VFCCU_GFLTRC_C0_RHWSW6_WIDTH (1U) 447 #define L_VFCCU_GFLTRC_C0_RHWSW6(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW6_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW6_MASK) 448 449 #define L_VFCCU_GFLTRC_C0_RHWSW7_MASK (0x80U) 450 #define L_VFCCU_GFLTRC_C0_RHWSW7_SHIFT (7U) 451 #define L_VFCCU_GFLTRC_C0_RHWSW7_WIDTH (1U) 452 #define L_VFCCU_GFLTRC_C0_RHWSW7(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW7_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW7_MASK) 453 454 #define L_VFCCU_GFLTRC_C0_RHWSW8_MASK (0x100U) 455 #define L_VFCCU_GFLTRC_C0_RHWSW8_SHIFT (8U) 456 #define L_VFCCU_GFLTRC_C0_RHWSW8_WIDTH (1U) 457 #define L_VFCCU_GFLTRC_C0_RHWSW8(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW8_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW8_MASK) 458 459 #define L_VFCCU_GFLTRC_C0_RHWSW9_MASK (0x200U) 460 #define L_VFCCU_GFLTRC_C0_RHWSW9_SHIFT (9U) 461 #define L_VFCCU_GFLTRC_C0_RHWSW9_WIDTH (1U) 462 #define L_VFCCU_GFLTRC_C0_RHWSW9(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW9_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW9_MASK) 463 464 #define L_VFCCU_GFLTRC_C0_RHWSW10_MASK (0x400U) 465 #define L_VFCCU_GFLTRC_C0_RHWSW10_SHIFT (10U) 466 #define L_VFCCU_GFLTRC_C0_RHWSW10_WIDTH (1U) 467 #define L_VFCCU_GFLTRC_C0_RHWSW10(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW10_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW10_MASK) 468 469 #define L_VFCCU_GFLTRC_C0_RHWSW11_MASK (0x800U) 470 #define L_VFCCU_GFLTRC_C0_RHWSW11_SHIFT (11U) 471 #define L_VFCCU_GFLTRC_C0_RHWSW11_WIDTH (1U) 472 #define L_VFCCU_GFLTRC_C0_RHWSW11(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW11_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW11_MASK) 473 474 #define L_VFCCU_GFLTRC_C0_RHWSW12_MASK (0x1000U) 475 #define L_VFCCU_GFLTRC_C0_RHWSW12_SHIFT (12U) 476 #define L_VFCCU_GFLTRC_C0_RHWSW12_WIDTH (1U) 477 #define L_VFCCU_GFLTRC_C0_RHWSW12(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW12_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW12_MASK) 478 479 #define L_VFCCU_GFLTRC_C0_RHWSW13_MASK (0x2000U) 480 #define L_VFCCU_GFLTRC_C0_RHWSW13_SHIFT (13U) 481 #define L_VFCCU_GFLTRC_C0_RHWSW13_WIDTH (1U) 482 #define L_VFCCU_GFLTRC_C0_RHWSW13(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW13_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW13_MASK) 483 484 #define L_VFCCU_GFLTRC_C0_RHWSW14_MASK (0x4000U) 485 #define L_VFCCU_GFLTRC_C0_RHWSW14_SHIFT (14U) 486 #define L_VFCCU_GFLTRC_C0_RHWSW14_WIDTH (1U) 487 #define L_VFCCU_GFLTRC_C0_RHWSW14(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW14_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW14_MASK) 488 489 #define L_VFCCU_GFLTRC_C0_RHWSW15_MASK (0x8000U) 490 #define L_VFCCU_GFLTRC_C0_RHWSW15_SHIFT (15U) 491 #define L_VFCCU_GFLTRC_C0_RHWSW15_WIDTH (1U) 492 #define L_VFCCU_GFLTRC_C0_RHWSW15(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW15_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW15_MASK) 493 494 #define L_VFCCU_GFLTRC_C0_RHWSW16_MASK (0x10000U) 495 #define L_VFCCU_GFLTRC_C0_RHWSW16_SHIFT (16U) 496 #define L_VFCCU_GFLTRC_C0_RHWSW16_WIDTH (1U) 497 #define L_VFCCU_GFLTRC_C0_RHWSW16(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW16_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW16_MASK) 498 499 #define L_VFCCU_GFLTRC_C0_RHWSW17_MASK (0x20000U) 500 #define L_VFCCU_GFLTRC_C0_RHWSW17_SHIFT (17U) 501 #define L_VFCCU_GFLTRC_C0_RHWSW17_WIDTH (1U) 502 #define L_VFCCU_GFLTRC_C0_RHWSW17(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW17_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW17_MASK) 503 504 #define L_VFCCU_GFLTRC_C0_RHWSW18_MASK (0x40000U) 505 #define L_VFCCU_GFLTRC_C0_RHWSW18_SHIFT (18U) 506 #define L_VFCCU_GFLTRC_C0_RHWSW18_WIDTH (1U) 507 #define L_VFCCU_GFLTRC_C0_RHWSW18(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW18_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW18_MASK) 508 509 #define L_VFCCU_GFLTRC_C0_RHWSW19_MASK (0x80000U) 510 #define L_VFCCU_GFLTRC_C0_RHWSW19_SHIFT (19U) 511 #define L_VFCCU_GFLTRC_C0_RHWSW19_WIDTH (1U) 512 #define L_VFCCU_GFLTRC_C0_RHWSW19(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW19_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW19_MASK) 513 514 #define L_VFCCU_GFLTRC_C0_RHWSW20_MASK (0x100000U) 515 #define L_VFCCU_GFLTRC_C0_RHWSW20_SHIFT (20U) 516 #define L_VFCCU_GFLTRC_C0_RHWSW20_WIDTH (1U) 517 #define L_VFCCU_GFLTRC_C0_RHWSW20(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW20_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW20_MASK) 518 519 #define L_VFCCU_GFLTRC_C0_RHWSW21_MASK (0x200000U) 520 #define L_VFCCU_GFLTRC_C0_RHWSW21_SHIFT (21U) 521 #define L_VFCCU_GFLTRC_C0_RHWSW21_WIDTH (1U) 522 #define L_VFCCU_GFLTRC_C0_RHWSW21(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW21_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW21_MASK) 523 524 #define L_VFCCU_GFLTRC_C0_RHWSW22_MASK (0x400000U) 525 #define L_VFCCU_GFLTRC_C0_RHWSW22_SHIFT (22U) 526 #define L_VFCCU_GFLTRC_C0_RHWSW22_WIDTH (1U) 527 #define L_VFCCU_GFLTRC_C0_RHWSW22(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW22_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW22_MASK) 528 529 #define L_VFCCU_GFLTRC_C0_RHWSW23_MASK (0x800000U) 530 #define L_VFCCU_GFLTRC_C0_RHWSW23_SHIFT (23U) 531 #define L_VFCCU_GFLTRC_C0_RHWSW23_WIDTH (1U) 532 #define L_VFCCU_GFLTRC_C0_RHWSW23(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW23_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW23_MASK) 533 534 #define L_VFCCU_GFLTRC_C0_RHWSW24_MASK (0x1000000U) 535 #define L_VFCCU_GFLTRC_C0_RHWSW24_SHIFT (24U) 536 #define L_VFCCU_GFLTRC_C0_RHWSW24_WIDTH (1U) 537 #define L_VFCCU_GFLTRC_C0_RHWSW24(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW24_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW24_MASK) 538 539 #define L_VFCCU_GFLTRC_C0_RHWSW25_MASK (0x2000000U) 540 #define L_VFCCU_GFLTRC_C0_RHWSW25_SHIFT (25U) 541 #define L_VFCCU_GFLTRC_C0_RHWSW25_WIDTH (1U) 542 #define L_VFCCU_GFLTRC_C0_RHWSW25(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW25_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW25_MASK) 543 544 #define L_VFCCU_GFLTRC_C0_RHWSW26_MASK (0x4000000U) 545 #define L_VFCCU_GFLTRC_C0_RHWSW26_SHIFT (26U) 546 #define L_VFCCU_GFLTRC_C0_RHWSW26_WIDTH (1U) 547 #define L_VFCCU_GFLTRC_C0_RHWSW26(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW26_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW26_MASK) 548 549 #define L_VFCCU_GFLTRC_C0_RHWSW27_MASK (0x8000000U) 550 #define L_VFCCU_GFLTRC_C0_RHWSW27_SHIFT (27U) 551 #define L_VFCCU_GFLTRC_C0_RHWSW27_WIDTH (1U) 552 #define L_VFCCU_GFLTRC_C0_RHWSW27(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW27_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW27_MASK) 553 554 #define L_VFCCU_GFLTRC_C0_RHWSW28_MASK (0x10000000U) 555 #define L_VFCCU_GFLTRC_C0_RHWSW28_SHIFT (28U) 556 #define L_VFCCU_GFLTRC_C0_RHWSW28_WIDTH (1U) 557 #define L_VFCCU_GFLTRC_C0_RHWSW28(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW28_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW28_MASK) 558 559 #define L_VFCCU_GFLTRC_C0_RHWSW29_MASK (0x20000000U) 560 #define L_VFCCU_GFLTRC_C0_RHWSW29_SHIFT (29U) 561 #define L_VFCCU_GFLTRC_C0_RHWSW29_WIDTH (1U) 562 #define L_VFCCU_GFLTRC_C0_RHWSW29(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW29_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW29_MASK) 563 564 #define L_VFCCU_GFLTRC_C0_RHWSW30_MASK (0x40000000U) 565 #define L_VFCCU_GFLTRC_C0_RHWSW30_SHIFT (30U) 566 #define L_VFCCU_GFLTRC_C0_RHWSW30_WIDTH (1U) 567 #define L_VFCCU_GFLTRC_C0_RHWSW30(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW30_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW30_MASK) 568 569 #define L_VFCCU_GFLTRC_C0_RHWSW31_MASK (0x80000000U) 570 #define L_VFCCU_GFLTRC_C0_RHWSW31_SHIFT (31U) 571 #define L_VFCCU_GFLTRC_C0_RHWSW31_WIDTH (1U) 572 #define L_VFCCU_GFLTRC_C0_RHWSW31(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTRC_C0_RHWSW31_SHIFT)) & L_VFCCU_GFLTRC_C0_RHWSW31_MASK) 573 /*! @} */ 574 575 /*! @name GFLTOVDC0 - Global Fault Overflow Detection */ 576 /*! @{ */ 577 578 #define L_VFCCU_GFLTOVDC0_OVF_DIS0_MASK (0x1U) 579 #define L_VFCCU_GFLTOVDC0_OVF_DIS0_SHIFT (0U) 580 #define L_VFCCU_GFLTOVDC0_OVF_DIS0_WIDTH (1U) 581 #define L_VFCCU_GFLTOVDC0_OVF_DIS0(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS0_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS0_MASK) 582 583 #define L_VFCCU_GFLTOVDC0_OVF_DIS1_MASK (0x2U) 584 #define L_VFCCU_GFLTOVDC0_OVF_DIS1_SHIFT (1U) 585 #define L_VFCCU_GFLTOVDC0_OVF_DIS1_WIDTH (1U) 586 #define L_VFCCU_GFLTOVDC0_OVF_DIS1(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS1_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS1_MASK) 587 588 #define L_VFCCU_GFLTOVDC0_OVF_DIS2_MASK (0x4U) 589 #define L_VFCCU_GFLTOVDC0_OVF_DIS2_SHIFT (2U) 590 #define L_VFCCU_GFLTOVDC0_OVF_DIS2_WIDTH (1U) 591 #define L_VFCCU_GFLTOVDC0_OVF_DIS2(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS2_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS2_MASK) 592 593 #define L_VFCCU_GFLTOVDC0_OVF_DIS3_MASK (0x8U) 594 #define L_VFCCU_GFLTOVDC0_OVF_DIS3_SHIFT (3U) 595 #define L_VFCCU_GFLTOVDC0_OVF_DIS3_WIDTH (1U) 596 #define L_VFCCU_GFLTOVDC0_OVF_DIS3(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS3_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS3_MASK) 597 598 #define L_VFCCU_GFLTOVDC0_OVF_DIS4_MASK (0x10U) 599 #define L_VFCCU_GFLTOVDC0_OVF_DIS4_SHIFT (4U) 600 #define L_VFCCU_GFLTOVDC0_OVF_DIS4_WIDTH (1U) 601 #define L_VFCCU_GFLTOVDC0_OVF_DIS4(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS4_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS4_MASK) 602 603 #define L_VFCCU_GFLTOVDC0_OVF_DIS5_MASK (0x20U) 604 #define L_VFCCU_GFLTOVDC0_OVF_DIS5_SHIFT (5U) 605 #define L_VFCCU_GFLTOVDC0_OVF_DIS5_WIDTH (1U) 606 #define L_VFCCU_GFLTOVDC0_OVF_DIS5(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS5_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS5_MASK) 607 608 #define L_VFCCU_GFLTOVDC0_OVF_DIS6_MASK (0x40U) 609 #define L_VFCCU_GFLTOVDC0_OVF_DIS6_SHIFT (6U) 610 #define L_VFCCU_GFLTOVDC0_OVF_DIS6_WIDTH (1U) 611 #define L_VFCCU_GFLTOVDC0_OVF_DIS6(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS6_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS6_MASK) 612 613 #define L_VFCCU_GFLTOVDC0_OVF_DIS7_MASK (0x80U) 614 #define L_VFCCU_GFLTOVDC0_OVF_DIS7_SHIFT (7U) 615 #define L_VFCCU_GFLTOVDC0_OVF_DIS7_WIDTH (1U) 616 #define L_VFCCU_GFLTOVDC0_OVF_DIS7(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS7_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS7_MASK) 617 618 #define L_VFCCU_GFLTOVDC0_OVF_DIS8_MASK (0x100U) 619 #define L_VFCCU_GFLTOVDC0_OVF_DIS8_SHIFT (8U) 620 #define L_VFCCU_GFLTOVDC0_OVF_DIS8_WIDTH (1U) 621 #define L_VFCCU_GFLTOVDC0_OVF_DIS8(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS8_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS8_MASK) 622 623 #define L_VFCCU_GFLTOVDC0_OVF_DIS9_MASK (0x200U) 624 #define L_VFCCU_GFLTOVDC0_OVF_DIS9_SHIFT (9U) 625 #define L_VFCCU_GFLTOVDC0_OVF_DIS9_WIDTH (1U) 626 #define L_VFCCU_GFLTOVDC0_OVF_DIS9(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS9_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS9_MASK) 627 628 #define L_VFCCU_GFLTOVDC0_OVF_DIS10_MASK (0x400U) 629 #define L_VFCCU_GFLTOVDC0_OVF_DIS10_SHIFT (10U) 630 #define L_VFCCU_GFLTOVDC0_OVF_DIS10_WIDTH (1U) 631 #define L_VFCCU_GFLTOVDC0_OVF_DIS10(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS10_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS10_MASK) 632 633 #define L_VFCCU_GFLTOVDC0_OVF_DIS11_MASK (0x800U) 634 #define L_VFCCU_GFLTOVDC0_OVF_DIS11_SHIFT (11U) 635 #define L_VFCCU_GFLTOVDC0_OVF_DIS11_WIDTH (1U) 636 #define L_VFCCU_GFLTOVDC0_OVF_DIS11(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS11_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS11_MASK) 637 638 #define L_VFCCU_GFLTOVDC0_OVF_DIS12_MASK (0x1000U) 639 #define L_VFCCU_GFLTOVDC0_OVF_DIS12_SHIFT (12U) 640 #define L_VFCCU_GFLTOVDC0_OVF_DIS12_WIDTH (1U) 641 #define L_VFCCU_GFLTOVDC0_OVF_DIS12(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS12_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS12_MASK) 642 643 #define L_VFCCU_GFLTOVDC0_OVF_DIS13_MASK (0x2000U) 644 #define L_VFCCU_GFLTOVDC0_OVF_DIS13_SHIFT (13U) 645 #define L_VFCCU_GFLTOVDC0_OVF_DIS13_WIDTH (1U) 646 #define L_VFCCU_GFLTOVDC0_OVF_DIS13(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS13_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS13_MASK) 647 648 #define L_VFCCU_GFLTOVDC0_OVF_DIS14_MASK (0x4000U) 649 #define L_VFCCU_GFLTOVDC0_OVF_DIS14_SHIFT (14U) 650 #define L_VFCCU_GFLTOVDC0_OVF_DIS14_WIDTH (1U) 651 #define L_VFCCU_GFLTOVDC0_OVF_DIS14(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS14_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS14_MASK) 652 653 #define L_VFCCU_GFLTOVDC0_OVF_DIS15_MASK (0x8000U) 654 #define L_VFCCU_GFLTOVDC0_OVF_DIS15_SHIFT (15U) 655 #define L_VFCCU_GFLTOVDC0_OVF_DIS15_WIDTH (1U) 656 #define L_VFCCU_GFLTOVDC0_OVF_DIS15(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS15_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS15_MASK) 657 658 #define L_VFCCU_GFLTOVDC0_OVF_DIS16_MASK (0x10000U) 659 #define L_VFCCU_GFLTOVDC0_OVF_DIS16_SHIFT (16U) 660 #define L_VFCCU_GFLTOVDC0_OVF_DIS16_WIDTH (1U) 661 #define L_VFCCU_GFLTOVDC0_OVF_DIS16(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS16_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS16_MASK) 662 663 #define L_VFCCU_GFLTOVDC0_OVF_DIS17_MASK (0x20000U) 664 #define L_VFCCU_GFLTOVDC0_OVF_DIS17_SHIFT (17U) 665 #define L_VFCCU_GFLTOVDC0_OVF_DIS17_WIDTH (1U) 666 #define L_VFCCU_GFLTOVDC0_OVF_DIS17(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS17_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS17_MASK) 667 668 #define L_VFCCU_GFLTOVDC0_OVF_DIS18_MASK (0x40000U) 669 #define L_VFCCU_GFLTOVDC0_OVF_DIS18_SHIFT (18U) 670 #define L_VFCCU_GFLTOVDC0_OVF_DIS18_WIDTH (1U) 671 #define L_VFCCU_GFLTOVDC0_OVF_DIS18(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS18_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS18_MASK) 672 673 #define L_VFCCU_GFLTOVDC0_OVF_DIS19_MASK (0x80000U) 674 #define L_VFCCU_GFLTOVDC0_OVF_DIS19_SHIFT (19U) 675 #define L_VFCCU_GFLTOVDC0_OVF_DIS19_WIDTH (1U) 676 #define L_VFCCU_GFLTOVDC0_OVF_DIS19(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS19_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS19_MASK) 677 678 #define L_VFCCU_GFLTOVDC0_OVF_DIS20_MASK (0x100000U) 679 #define L_VFCCU_GFLTOVDC0_OVF_DIS20_SHIFT (20U) 680 #define L_VFCCU_GFLTOVDC0_OVF_DIS20_WIDTH (1U) 681 #define L_VFCCU_GFLTOVDC0_OVF_DIS20(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS20_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS20_MASK) 682 683 #define L_VFCCU_GFLTOVDC0_OVF_DIS21_MASK (0x200000U) 684 #define L_VFCCU_GFLTOVDC0_OVF_DIS21_SHIFT (21U) 685 #define L_VFCCU_GFLTOVDC0_OVF_DIS21_WIDTH (1U) 686 #define L_VFCCU_GFLTOVDC0_OVF_DIS21(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS21_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS21_MASK) 687 688 #define L_VFCCU_GFLTOVDC0_OVF_DIS22_MASK (0x400000U) 689 #define L_VFCCU_GFLTOVDC0_OVF_DIS22_SHIFT (22U) 690 #define L_VFCCU_GFLTOVDC0_OVF_DIS22_WIDTH (1U) 691 #define L_VFCCU_GFLTOVDC0_OVF_DIS22(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS22_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS22_MASK) 692 693 #define L_VFCCU_GFLTOVDC0_OVF_DIS23_MASK (0x800000U) 694 #define L_VFCCU_GFLTOVDC0_OVF_DIS23_SHIFT (23U) 695 #define L_VFCCU_GFLTOVDC0_OVF_DIS23_WIDTH (1U) 696 #define L_VFCCU_GFLTOVDC0_OVF_DIS23(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS23_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS23_MASK) 697 698 #define L_VFCCU_GFLTOVDC0_OVF_DIS24_MASK (0x1000000U) 699 #define L_VFCCU_GFLTOVDC0_OVF_DIS24_SHIFT (24U) 700 #define L_VFCCU_GFLTOVDC0_OVF_DIS24_WIDTH (1U) 701 #define L_VFCCU_GFLTOVDC0_OVF_DIS24(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS24_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS24_MASK) 702 703 #define L_VFCCU_GFLTOVDC0_OVF_DIS25_MASK (0x2000000U) 704 #define L_VFCCU_GFLTOVDC0_OVF_DIS25_SHIFT (25U) 705 #define L_VFCCU_GFLTOVDC0_OVF_DIS25_WIDTH (1U) 706 #define L_VFCCU_GFLTOVDC0_OVF_DIS25(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS25_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS25_MASK) 707 708 #define L_VFCCU_GFLTOVDC0_OVF_DIS26_MASK (0x4000000U) 709 #define L_VFCCU_GFLTOVDC0_OVF_DIS26_SHIFT (26U) 710 #define L_VFCCU_GFLTOVDC0_OVF_DIS26_WIDTH (1U) 711 #define L_VFCCU_GFLTOVDC0_OVF_DIS26(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS26_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS26_MASK) 712 713 #define L_VFCCU_GFLTOVDC0_OVF_DIS27_MASK (0x8000000U) 714 #define L_VFCCU_GFLTOVDC0_OVF_DIS27_SHIFT (27U) 715 #define L_VFCCU_GFLTOVDC0_OVF_DIS27_WIDTH (1U) 716 #define L_VFCCU_GFLTOVDC0_OVF_DIS27(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS27_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS27_MASK) 717 718 #define L_VFCCU_GFLTOVDC0_OVF_DIS28_MASK (0x10000000U) 719 #define L_VFCCU_GFLTOVDC0_OVF_DIS28_SHIFT (28U) 720 #define L_VFCCU_GFLTOVDC0_OVF_DIS28_WIDTH (1U) 721 #define L_VFCCU_GFLTOVDC0_OVF_DIS28(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS28_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS28_MASK) 722 723 #define L_VFCCU_GFLTOVDC0_OVF_DIS29_MASK (0x20000000U) 724 #define L_VFCCU_GFLTOVDC0_OVF_DIS29_SHIFT (29U) 725 #define L_VFCCU_GFLTOVDC0_OVF_DIS29_WIDTH (1U) 726 #define L_VFCCU_GFLTOVDC0_OVF_DIS29(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS29_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS29_MASK) 727 728 #define L_VFCCU_GFLTOVDC0_OVF_DIS30_MASK (0x40000000U) 729 #define L_VFCCU_GFLTOVDC0_OVF_DIS30_SHIFT (30U) 730 #define L_VFCCU_GFLTOVDC0_OVF_DIS30_WIDTH (1U) 731 #define L_VFCCU_GFLTOVDC0_OVF_DIS30(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS30_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS30_MASK) 732 733 #define L_VFCCU_GFLTOVDC0_OVF_DIS31_MASK (0x80000000U) 734 #define L_VFCCU_GFLTOVDC0_OVF_DIS31_SHIFT (31U) 735 #define L_VFCCU_GFLTOVDC0_OVF_DIS31_WIDTH (1U) 736 #define L_VFCCU_GFLTOVDC0_OVF_DIS31(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GFLTOVDC0_OVF_DIS31_SHIFT)) & L_VFCCU_GFLTOVDC0_OVF_DIS31_MASK) 737 /*! @} */ 738 739 /*! @name GCTRL - Global Space Control */ 740 /*! @{ */ 741 742 #define L_VFCCU_GCTRL_OVF_EN_MASK (0x1U) 743 #define L_VFCCU_GCTRL_OVF_EN_SHIFT (0U) 744 #define L_VFCCU_GCTRL_OVF_EN_WIDTH (1U) 745 #define L_VFCCU_GCTRL_OVF_EN(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GCTRL_OVF_EN_SHIFT)) & L_VFCCU_GCTRL_OVF_EN_MASK) 746 /*! @} */ 747 748 /*! @name GINTOVFS - Global DID FSM Status */ 749 /*! @{ */ 750 751 #define L_VFCCU_GINTOVFS_FLTSERV_MASK (0x80U) 752 #define L_VFCCU_GINTOVFS_FLTSERV_SHIFT (7U) 753 #define L_VFCCU_GINTOVFS_FLTSERV_WIDTH (1U) 754 #define L_VFCCU_GINTOVFS_FLTSERV(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GINTOVFS_FLTSERV_SHIFT)) & L_VFCCU_GINTOVFS_FLTSERV_MASK) 755 756 #define L_VFCCU_GINTOVFS_OVF_DET_MASK (0x100U) 757 #define L_VFCCU_GINTOVFS_OVF_DET_SHIFT (8U) 758 #define L_VFCCU_GINTOVFS_OVF_DET_WIDTH (1U) 759 #define L_VFCCU_GINTOVFS_OVF_DET(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GINTOVFS_OVF_DET_SHIFT)) & L_VFCCU_GINTOVFS_OVF_DET_MASK) 760 761 #define L_VFCCU_GINTOVFS_SERV_DID_MASK (0xF0000U) 762 #define L_VFCCU_GINTOVFS_SERV_DID_SHIFT (16U) 763 #define L_VFCCU_GINTOVFS_SERV_DID_WIDTH (4U) 764 #define L_VFCCU_GINTOVFS_SERV_DID(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GINTOVFS_SERV_DID_SHIFT)) & L_VFCCU_GINTOVFS_SERV_DID_MASK) 765 766 #define L_VFCCU_GINTOVFS_OVF_DID_MASK (0xF000000U) 767 #define L_VFCCU_GINTOVFS_OVF_DID_SHIFT (24U) 768 #define L_VFCCU_GINTOVFS_OVF_DID_WIDTH (4U) 769 #define L_VFCCU_GINTOVFS_OVF_DID(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GINTOVFS_OVF_DID_SHIFT)) & L_VFCCU_GINTOVFS_OVF_DID_MASK) 770 /*! @} */ 771 772 /*! @name GDBGCFG - Global Debug */ 773 /*! @{ */ 774 775 #define L_VFCCU_GDBGCFG_FRZ_MASK (0x10000U) 776 #define L_VFCCU_GDBGCFG_FRZ_SHIFT (16U) 777 #define L_VFCCU_GDBGCFG_FRZ_WIDTH (1U) 778 #define L_VFCCU_GDBGCFG_FRZ(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GDBGCFG_FRZ_SHIFT)) & L_VFCCU_GDBGCFG_FRZ_MASK) 779 /*! @} */ 780 781 /*! @name GDBGSTAT - Global Debug Status */ 782 /*! @{ */ 783 784 #define L_VFCCU_GDBGSTAT_FLTIND_MASK (0xFFU) 785 #define L_VFCCU_GDBGSTAT_FLTIND_SHIFT (0U) 786 #define L_VFCCU_GDBGSTAT_FLTIND_WIDTH (8U) 787 #define L_VFCCU_GDBGSTAT_FLTIND(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_GDBGSTAT_FLTIND_SHIFT)) & L_VFCCU_GDBGSTAT_FLTIND_MASK) 788 /*! @} */ 789 790 /*! @name FHCFG0 - Fault Handler */ 791 /*! @{ */ 792 793 #define L_VFCCU_FHCFG0_FHIDEN_MASK (0x1U) 794 #define L_VFCCU_FHCFG0_FHIDEN_SHIFT (0U) 795 #define L_VFCCU_FHCFG0_FHIDEN_WIDTH (1U) 796 #define L_VFCCU_FHCFG0_FHIDEN(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHCFG0_FHIDEN_SHIFT)) & L_VFCCU_FHCFG0_FHIDEN_MASK) 797 /*! @} */ 798 799 /*! @name FHSRVDS0 - Fault Handler Status */ 800 /*! @{ */ 801 802 #define L_VFCCU_FHSRVDS0_SERV_DID_MASK (0xFU) 803 #define L_VFCCU_FHSRVDS0_SERV_DID_SHIFT (0U) 804 #define L_VFCCU_FHSRVDS0_SERV_DID_WIDTH (4U) 805 #define L_VFCCU_FHSRVDS0_SERV_DID(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHSRVDS0_SERV_DID_SHIFT)) & L_VFCCU_FHSRVDS0_SERV_DID_MASK) 806 807 #define L_VFCCU_FHSRVDS0_AGGFLTS_MASK (0x10U) 808 #define L_VFCCU_FHSRVDS0_AGGFLTS_SHIFT (4U) 809 #define L_VFCCU_FHSRVDS0_AGGFLTS_WIDTH (1U) 810 #define L_VFCCU_FHSRVDS0_AGGFLTS(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHSRVDS0_AGGFLTS_SHIFT)) & L_VFCCU_FHSRVDS0_AGGFLTS_MASK) 811 /*! @} */ 812 813 /*! @name FHFLTENC00 - Fault Enable */ 814 /*! @{ */ 815 816 #define L_VFCCU_FHFLTENC00_EN0_MASK (0x1U) 817 #define L_VFCCU_FHFLTENC00_EN0_SHIFT (0U) 818 #define L_VFCCU_FHFLTENC00_EN0_WIDTH (1U) 819 #define L_VFCCU_FHFLTENC00_EN0(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN0_SHIFT)) & L_VFCCU_FHFLTENC00_EN0_MASK) 820 821 #define L_VFCCU_FHFLTENC00_EN1_MASK (0x2U) 822 #define L_VFCCU_FHFLTENC00_EN1_SHIFT (1U) 823 #define L_VFCCU_FHFLTENC00_EN1_WIDTH (1U) 824 #define L_VFCCU_FHFLTENC00_EN1(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN1_SHIFT)) & L_VFCCU_FHFLTENC00_EN1_MASK) 825 826 #define L_VFCCU_FHFLTENC00_EN2_MASK (0x4U) 827 #define L_VFCCU_FHFLTENC00_EN2_SHIFT (2U) 828 #define L_VFCCU_FHFLTENC00_EN2_WIDTH (1U) 829 #define L_VFCCU_FHFLTENC00_EN2(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN2_SHIFT)) & L_VFCCU_FHFLTENC00_EN2_MASK) 830 831 #define L_VFCCU_FHFLTENC00_EN3_MASK (0x8U) 832 #define L_VFCCU_FHFLTENC00_EN3_SHIFT (3U) 833 #define L_VFCCU_FHFLTENC00_EN3_WIDTH (1U) 834 #define L_VFCCU_FHFLTENC00_EN3(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN3_SHIFT)) & L_VFCCU_FHFLTENC00_EN3_MASK) 835 836 #define L_VFCCU_FHFLTENC00_EN4_MASK (0x10U) 837 #define L_VFCCU_FHFLTENC00_EN4_SHIFT (4U) 838 #define L_VFCCU_FHFLTENC00_EN4_WIDTH (1U) 839 #define L_VFCCU_FHFLTENC00_EN4(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN4_SHIFT)) & L_VFCCU_FHFLTENC00_EN4_MASK) 840 841 #define L_VFCCU_FHFLTENC00_EN5_MASK (0x20U) 842 #define L_VFCCU_FHFLTENC00_EN5_SHIFT (5U) 843 #define L_VFCCU_FHFLTENC00_EN5_WIDTH (1U) 844 #define L_VFCCU_FHFLTENC00_EN5(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN5_SHIFT)) & L_VFCCU_FHFLTENC00_EN5_MASK) 845 846 #define L_VFCCU_FHFLTENC00_EN6_MASK (0x40U) 847 #define L_VFCCU_FHFLTENC00_EN6_SHIFT (6U) 848 #define L_VFCCU_FHFLTENC00_EN6_WIDTH (1U) 849 #define L_VFCCU_FHFLTENC00_EN6(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN6_SHIFT)) & L_VFCCU_FHFLTENC00_EN6_MASK) 850 851 #define L_VFCCU_FHFLTENC00_EN7_MASK (0x80U) 852 #define L_VFCCU_FHFLTENC00_EN7_SHIFT (7U) 853 #define L_VFCCU_FHFLTENC00_EN7_WIDTH (1U) 854 #define L_VFCCU_FHFLTENC00_EN7(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN7_SHIFT)) & L_VFCCU_FHFLTENC00_EN7_MASK) 855 856 #define L_VFCCU_FHFLTENC00_EN8_MASK (0x100U) 857 #define L_VFCCU_FHFLTENC00_EN8_SHIFT (8U) 858 #define L_VFCCU_FHFLTENC00_EN8_WIDTH (1U) 859 #define L_VFCCU_FHFLTENC00_EN8(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN8_SHIFT)) & L_VFCCU_FHFLTENC00_EN8_MASK) 860 861 #define L_VFCCU_FHFLTENC00_EN9_MASK (0x200U) 862 #define L_VFCCU_FHFLTENC00_EN9_SHIFT (9U) 863 #define L_VFCCU_FHFLTENC00_EN9_WIDTH (1U) 864 #define L_VFCCU_FHFLTENC00_EN9(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN9_SHIFT)) & L_VFCCU_FHFLTENC00_EN9_MASK) 865 866 #define L_VFCCU_FHFLTENC00_EN10_MASK (0x400U) 867 #define L_VFCCU_FHFLTENC00_EN10_SHIFT (10U) 868 #define L_VFCCU_FHFLTENC00_EN10_WIDTH (1U) 869 #define L_VFCCU_FHFLTENC00_EN10(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN10_SHIFT)) & L_VFCCU_FHFLTENC00_EN10_MASK) 870 871 #define L_VFCCU_FHFLTENC00_EN11_MASK (0x800U) 872 #define L_VFCCU_FHFLTENC00_EN11_SHIFT (11U) 873 #define L_VFCCU_FHFLTENC00_EN11_WIDTH (1U) 874 #define L_VFCCU_FHFLTENC00_EN11(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN11_SHIFT)) & L_VFCCU_FHFLTENC00_EN11_MASK) 875 876 #define L_VFCCU_FHFLTENC00_EN12_MASK (0x1000U) 877 #define L_VFCCU_FHFLTENC00_EN12_SHIFT (12U) 878 #define L_VFCCU_FHFLTENC00_EN12_WIDTH (1U) 879 #define L_VFCCU_FHFLTENC00_EN12(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN12_SHIFT)) & L_VFCCU_FHFLTENC00_EN12_MASK) 880 881 #define L_VFCCU_FHFLTENC00_EN13_MASK (0x2000U) 882 #define L_VFCCU_FHFLTENC00_EN13_SHIFT (13U) 883 #define L_VFCCU_FHFLTENC00_EN13_WIDTH (1U) 884 #define L_VFCCU_FHFLTENC00_EN13(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN13_SHIFT)) & L_VFCCU_FHFLTENC00_EN13_MASK) 885 886 #define L_VFCCU_FHFLTENC00_EN14_MASK (0x4000U) 887 #define L_VFCCU_FHFLTENC00_EN14_SHIFT (14U) 888 #define L_VFCCU_FHFLTENC00_EN14_WIDTH (1U) 889 #define L_VFCCU_FHFLTENC00_EN14(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN14_SHIFT)) & L_VFCCU_FHFLTENC00_EN14_MASK) 890 891 #define L_VFCCU_FHFLTENC00_EN15_MASK (0x8000U) 892 #define L_VFCCU_FHFLTENC00_EN15_SHIFT (15U) 893 #define L_VFCCU_FHFLTENC00_EN15_WIDTH (1U) 894 #define L_VFCCU_FHFLTENC00_EN15(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN15_SHIFT)) & L_VFCCU_FHFLTENC00_EN15_MASK) 895 896 #define L_VFCCU_FHFLTENC00_EN16_MASK (0x10000U) 897 #define L_VFCCU_FHFLTENC00_EN16_SHIFT (16U) 898 #define L_VFCCU_FHFLTENC00_EN16_WIDTH (1U) 899 #define L_VFCCU_FHFLTENC00_EN16(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN16_SHIFT)) & L_VFCCU_FHFLTENC00_EN16_MASK) 900 901 #define L_VFCCU_FHFLTENC00_EN17_MASK (0x20000U) 902 #define L_VFCCU_FHFLTENC00_EN17_SHIFT (17U) 903 #define L_VFCCU_FHFLTENC00_EN17_WIDTH (1U) 904 #define L_VFCCU_FHFLTENC00_EN17(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN17_SHIFT)) & L_VFCCU_FHFLTENC00_EN17_MASK) 905 906 #define L_VFCCU_FHFLTENC00_EN18_MASK (0x40000U) 907 #define L_VFCCU_FHFLTENC00_EN18_SHIFT (18U) 908 #define L_VFCCU_FHFLTENC00_EN18_WIDTH (1U) 909 #define L_VFCCU_FHFLTENC00_EN18(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN18_SHIFT)) & L_VFCCU_FHFLTENC00_EN18_MASK) 910 911 #define L_VFCCU_FHFLTENC00_EN19_MASK (0x80000U) 912 #define L_VFCCU_FHFLTENC00_EN19_SHIFT (19U) 913 #define L_VFCCU_FHFLTENC00_EN19_WIDTH (1U) 914 #define L_VFCCU_FHFLTENC00_EN19(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN19_SHIFT)) & L_VFCCU_FHFLTENC00_EN19_MASK) 915 916 #define L_VFCCU_FHFLTENC00_EN20_MASK (0x100000U) 917 #define L_VFCCU_FHFLTENC00_EN20_SHIFT (20U) 918 #define L_VFCCU_FHFLTENC00_EN20_WIDTH (1U) 919 #define L_VFCCU_FHFLTENC00_EN20(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN20_SHIFT)) & L_VFCCU_FHFLTENC00_EN20_MASK) 920 921 #define L_VFCCU_FHFLTENC00_EN21_MASK (0x200000U) 922 #define L_VFCCU_FHFLTENC00_EN21_SHIFT (21U) 923 #define L_VFCCU_FHFLTENC00_EN21_WIDTH (1U) 924 #define L_VFCCU_FHFLTENC00_EN21(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN21_SHIFT)) & L_VFCCU_FHFLTENC00_EN21_MASK) 925 926 #define L_VFCCU_FHFLTENC00_EN22_MASK (0x400000U) 927 #define L_VFCCU_FHFLTENC00_EN22_SHIFT (22U) 928 #define L_VFCCU_FHFLTENC00_EN22_WIDTH (1U) 929 #define L_VFCCU_FHFLTENC00_EN22(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN22_SHIFT)) & L_VFCCU_FHFLTENC00_EN22_MASK) 930 931 #define L_VFCCU_FHFLTENC00_EN23_MASK (0x800000U) 932 #define L_VFCCU_FHFLTENC00_EN23_SHIFT (23U) 933 #define L_VFCCU_FHFLTENC00_EN23_WIDTH (1U) 934 #define L_VFCCU_FHFLTENC00_EN23(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN23_SHIFT)) & L_VFCCU_FHFLTENC00_EN23_MASK) 935 936 #define L_VFCCU_FHFLTENC00_EN24_MASK (0x1000000U) 937 #define L_VFCCU_FHFLTENC00_EN24_SHIFT (24U) 938 #define L_VFCCU_FHFLTENC00_EN24_WIDTH (1U) 939 #define L_VFCCU_FHFLTENC00_EN24(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN24_SHIFT)) & L_VFCCU_FHFLTENC00_EN24_MASK) 940 941 #define L_VFCCU_FHFLTENC00_EN25_MASK (0x2000000U) 942 #define L_VFCCU_FHFLTENC00_EN25_SHIFT (25U) 943 #define L_VFCCU_FHFLTENC00_EN25_WIDTH (1U) 944 #define L_VFCCU_FHFLTENC00_EN25(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN25_SHIFT)) & L_VFCCU_FHFLTENC00_EN25_MASK) 945 946 #define L_VFCCU_FHFLTENC00_EN26_MASK (0x4000000U) 947 #define L_VFCCU_FHFLTENC00_EN26_SHIFT (26U) 948 #define L_VFCCU_FHFLTENC00_EN26_WIDTH (1U) 949 #define L_VFCCU_FHFLTENC00_EN26(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN26_SHIFT)) & L_VFCCU_FHFLTENC00_EN26_MASK) 950 951 #define L_VFCCU_FHFLTENC00_EN27_MASK (0x8000000U) 952 #define L_VFCCU_FHFLTENC00_EN27_SHIFT (27U) 953 #define L_VFCCU_FHFLTENC00_EN27_WIDTH (1U) 954 #define L_VFCCU_FHFLTENC00_EN27(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN27_SHIFT)) & L_VFCCU_FHFLTENC00_EN27_MASK) 955 956 #define L_VFCCU_FHFLTENC00_EN28_MASK (0x10000000U) 957 #define L_VFCCU_FHFLTENC00_EN28_SHIFT (28U) 958 #define L_VFCCU_FHFLTENC00_EN28_WIDTH (1U) 959 #define L_VFCCU_FHFLTENC00_EN28(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN28_SHIFT)) & L_VFCCU_FHFLTENC00_EN28_MASK) 960 961 #define L_VFCCU_FHFLTENC00_EN29_MASK (0x20000000U) 962 #define L_VFCCU_FHFLTENC00_EN29_SHIFT (29U) 963 #define L_VFCCU_FHFLTENC00_EN29_WIDTH (1U) 964 #define L_VFCCU_FHFLTENC00_EN29(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN29_SHIFT)) & L_VFCCU_FHFLTENC00_EN29_MASK) 965 966 #define L_VFCCU_FHFLTENC00_EN30_MASK (0x40000000U) 967 #define L_VFCCU_FHFLTENC00_EN30_SHIFT (30U) 968 #define L_VFCCU_FHFLTENC00_EN30_WIDTH (1U) 969 #define L_VFCCU_FHFLTENC00_EN30(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN30_SHIFT)) & L_VFCCU_FHFLTENC00_EN30_MASK) 970 971 #define L_VFCCU_FHFLTENC00_EN31_MASK (0x80000000U) 972 #define L_VFCCU_FHFLTENC00_EN31_SHIFT (31U) 973 #define L_VFCCU_FHFLTENC00_EN31_WIDTH (1U) 974 #define L_VFCCU_FHFLTENC00_EN31(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTENC00_EN31_SHIFT)) & L_VFCCU_FHFLTENC00_EN31_MASK) 975 /*! @} */ 976 977 /*! @name FHFLTS00 - Fault Status */ 978 /*! @{ */ 979 980 #define L_VFCCU_FHFLTS00_STAT0_MASK (0x1U) 981 #define L_VFCCU_FHFLTS00_STAT0_SHIFT (0U) 982 #define L_VFCCU_FHFLTS00_STAT0_WIDTH (1U) 983 #define L_VFCCU_FHFLTS00_STAT0(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT0_SHIFT)) & L_VFCCU_FHFLTS00_STAT0_MASK) 984 985 #define L_VFCCU_FHFLTS00_STAT1_MASK (0x2U) 986 #define L_VFCCU_FHFLTS00_STAT1_SHIFT (1U) 987 #define L_VFCCU_FHFLTS00_STAT1_WIDTH (1U) 988 #define L_VFCCU_FHFLTS00_STAT1(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT1_SHIFT)) & L_VFCCU_FHFLTS00_STAT1_MASK) 989 990 #define L_VFCCU_FHFLTS00_STAT2_MASK (0x4U) 991 #define L_VFCCU_FHFLTS00_STAT2_SHIFT (2U) 992 #define L_VFCCU_FHFLTS00_STAT2_WIDTH (1U) 993 #define L_VFCCU_FHFLTS00_STAT2(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT2_SHIFT)) & L_VFCCU_FHFLTS00_STAT2_MASK) 994 995 #define L_VFCCU_FHFLTS00_STAT3_MASK (0x8U) 996 #define L_VFCCU_FHFLTS00_STAT3_SHIFT (3U) 997 #define L_VFCCU_FHFLTS00_STAT3_WIDTH (1U) 998 #define L_VFCCU_FHFLTS00_STAT3(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT3_SHIFT)) & L_VFCCU_FHFLTS00_STAT3_MASK) 999 1000 #define L_VFCCU_FHFLTS00_STAT4_MASK (0x10U) 1001 #define L_VFCCU_FHFLTS00_STAT4_SHIFT (4U) 1002 #define L_VFCCU_FHFLTS00_STAT4_WIDTH (1U) 1003 #define L_VFCCU_FHFLTS00_STAT4(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT4_SHIFT)) & L_VFCCU_FHFLTS00_STAT4_MASK) 1004 1005 #define L_VFCCU_FHFLTS00_STAT5_MASK (0x20U) 1006 #define L_VFCCU_FHFLTS00_STAT5_SHIFT (5U) 1007 #define L_VFCCU_FHFLTS00_STAT5_WIDTH (1U) 1008 #define L_VFCCU_FHFLTS00_STAT5(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT5_SHIFT)) & L_VFCCU_FHFLTS00_STAT5_MASK) 1009 1010 #define L_VFCCU_FHFLTS00_STAT6_MASK (0x40U) 1011 #define L_VFCCU_FHFLTS00_STAT6_SHIFT (6U) 1012 #define L_VFCCU_FHFLTS00_STAT6_WIDTH (1U) 1013 #define L_VFCCU_FHFLTS00_STAT6(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT6_SHIFT)) & L_VFCCU_FHFLTS00_STAT6_MASK) 1014 1015 #define L_VFCCU_FHFLTS00_STAT7_MASK (0x80U) 1016 #define L_VFCCU_FHFLTS00_STAT7_SHIFT (7U) 1017 #define L_VFCCU_FHFLTS00_STAT7_WIDTH (1U) 1018 #define L_VFCCU_FHFLTS00_STAT7(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT7_SHIFT)) & L_VFCCU_FHFLTS00_STAT7_MASK) 1019 1020 #define L_VFCCU_FHFLTS00_STAT8_MASK (0x100U) 1021 #define L_VFCCU_FHFLTS00_STAT8_SHIFT (8U) 1022 #define L_VFCCU_FHFLTS00_STAT8_WIDTH (1U) 1023 #define L_VFCCU_FHFLTS00_STAT8(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT8_SHIFT)) & L_VFCCU_FHFLTS00_STAT8_MASK) 1024 1025 #define L_VFCCU_FHFLTS00_STAT9_MASK (0x200U) 1026 #define L_VFCCU_FHFLTS00_STAT9_SHIFT (9U) 1027 #define L_VFCCU_FHFLTS00_STAT9_WIDTH (1U) 1028 #define L_VFCCU_FHFLTS00_STAT9(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT9_SHIFT)) & L_VFCCU_FHFLTS00_STAT9_MASK) 1029 1030 #define L_VFCCU_FHFLTS00_STAT10_MASK (0x400U) 1031 #define L_VFCCU_FHFLTS00_STAT10_SHIFT (10U) 1032 #define L_VFCCU_FHFLTS00_STAT10_WIDTH (1U) 1033 #define L_VFCCU_FHFLTS00_STAT10(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT10_SHIFT)) & L_VFCCU_FHFLTS00_STAT10_MASK) 1034 1035 #define L_VFCCU_FHFLTS00_STAT11_MASK (0x800U) 1036 #define L_VFCCU_FHFLTS00_STAT11_SHIFT (11U) 1037 #define L_VFCCU_FHFLTS00_STAT11_WIDTH (1U) 1038 #define L_VFCCU_FHFLTS00_STAT11(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT11_SHIFT)) & L_VFCCU_FHFLTS00_STAT11_MASK) 1039 1040 #define L_VFCCU_FHFLTS00_STAT12_MASK (0x1000U) 1041 #define L_VFCCU_FHFLTS00_STAT12_SHIFT (12U) 1042 #define L_VFCCU_FHFLTS00_STAT12_WIDTH (1U) 1043 #define L_VFCCU_FHFLTS00_STAT12(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT12_SHIFT)) & L_VFCCU_FHFLTS00_STAT12_MASK) 1044 1045 #define L_VFCCU_FHFLTS00_STAT13_MASK (0x2000U) 1046 #define L_VFCCU_FHFLTS00_STAT13_SHIFT (13U) 1047 #define L_VFCCU_FHFLTS00_STAT13_WIDTH (1U) 1048 #define L_VFCCU_FHFLTS00_STAT13(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT13_SHIFT)) & L_VFCCU_FHFLTS00_STAT13_MASK) 1049 1050 #define L_VFCCU_FHFLTS00_STAT14_MASK (0x4000U) 1051 #define L_VFCCU_FHFLTS00_STAT14_SHIFT (14U) 1052 #define L_VFCCU_FHFLTS00_STAT14_WIDTH (1U) 1053 #define L_VFCCU_FHFLTS00_STAT14(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT14_SHIFT)) & L_VFCCU_FHFLTS00_STAT14_MASK) 1054 1055 #define L_VFCCU_FHFLTS00_STAT15_MASK (0x8000U) 1056 #define L_VFCCU_FHFLTS00_STAT15_SHIFT (15U) 1057 #define L_VFCCU_FHFLTS00_STAT15_WIDTH (1U) 1058 #define L_VFCCU_FHFLTS00_STAT15(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT15_SHIFT)) & L_VFCCU_FHFLTS00_STAT15_MASK) 1059 1060 #define L_VFCCU_FHFLTS00_STAT16_MASK (0x10000U) 1061 #define L_VFCCU_FHFLTS00_STAT16_SHIFT (16U) 1062 #define L_VFCCU_FHFLTS00_STAT16_WIDTH (1U) 1063 #define L_VFCCU_FHFLTS00_STAT16(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT16_SHIFT)) & L_VFCCU_FHFLTS00_STAT16_MASK) 1064 1065 #define L_VFCCU_FHFLTS00_STAT17_MASK (0x20000U) 1066 #define L_VFCCU_FHFLTS00_STAT17_SHIFT (17U) 1067 #define L_VFCCU_FHFLTS00_STAT17_WIDTH (1U) 1068 #define L_VFCCU_FHFLTS00_STAT17(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT17_SHIFT)) & L_VFCCU_FHFLTS00_STAT17_MASK) 1069 1070 #define L_VFCCU_FHFLTS00_STAT18_MASK (0x40000U) 1071 #define L_VFCCU_FHFLTS00_STAT18_SHIFT (18U) 1072 #define L_VFCCU_FHFLTS00_STAT18_WIDTH (1U) 1073 #define L_VFCCU_FHFLTS00_STAT18(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT18_SHIFT)) & L_VFCCU_FHFLTS00_STAT18_MASK) 1074 1075 #define L_VFCCU_FHFLTS00_STAT19_MASK (0x80000U) 1076 #define L_VFCCU_FHFLTS00_STAT19_SHIFT (19U) 1077 #define L_VFCCU_FHFLTS00_STAT19_WIDTH (1U) 1078 #define L_VFCCU_FHFLTS00_STAT19(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT19_SHIFT)) & L_VFCCU_FHFLTS00_STAT19_MASK) 1079 1080 #define L_VFCCU_FHFLTS00_STAT20_MASK (0x100000U) 1081 #define L_VFCCU_FHFLTS00_STAT20_SHIFT (20U) 1082 #define L_VFCCU_FHFLTS00_STAT20_WIDTH (1U) 1083 #define L_VFCCU_FHFLTS00_STAT20(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT20_SHIFT)) & L_VFCCU_FHFLTS00_STAT20_MASK) 1084 1085 #define L_VFCCU_FHFLTS00_STAT21_MASK (0x200000U) 1086 #define L_VFCCU_FHFLTS00_STAT21_SHIFT (21U) 1087 #define L_VFCCU_FHFLTS00_STAT21_WIDTH (1U) 1088 #define L_VFCCU_FHFLTS00_STAT21(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT21_SHIFT)) & L_VFCCU_FHFLTS00_STAT21_MASK) 1089 1090 #define L_VFCCU_FHFLTS00_STAT22_MASK (0x400000U) 1091 #define L_VFCCU_FHFLTS00_STAT22_SHIFT (22U) 1092 #define L_VFCCU_FHFLTS00_STAT22_WIDTH (1U) 1093 #define L_VFCCU_FHFLTS00_STAT22(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT22_SHIFT)) & L_VFCCU_FHFLTS00_STAT22_MASK) 1094 1095 #define L_VFCCU_FHFLTS00_STAT23_MASK (0x800000U) 1096 #define L_VFCCU_FHFLTS00_STAT23_SHIFT (23U) 1097 #define L_VFCCU_FHFLTS00_STAT23_WIDTH (1U) 1098 #define L_VFCCU_FHFLTS00_STAT23(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT23_SHIFT)) & L_VFCCU_FHFLTS00_STAT23_MASK) 1099 1100 #define L_VFCCU_FHFLTS00_STAT24_MASK (0x1000000U) 1101 #define L_VFCCU_FHFLTS00_STAT24_SHIFT (24U) 1102 #define L_VFCCU_FHFLTS00_STAT24_WIDTH (1U) 1103 #define L_VFCCU_FHFLTS00_STAT24(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT24_SHIFT)) & L_VFCCU_FHFLTS00_STAT24_MASK) 1104 1105 #define L_VFCCU_FHFLTS00_STAT25_MASK (0x2000000U) 1106 #define L_VFCCU_FHFLTS00_STAT25_SHIFT (25U) 1107 #define L_VFCCU_FHFLTS00_STAT25_WIDTH (1U) 1108 #define L_VFCCU_FHFLTS00_STAT25(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT25_SHIFT)) & L_VFCCU_FHFLTS00_STAT25_MASK) 1109 1110 #define L_VFCCU_FHFLTS00_STAT26_MASK (0x4000000U) 1111 #define L_VFCCU_FHFLTS00_STAT26_SHIFT (26U) 1112 #define L_VFCCU_FHFLTS00_STAT26_WIDTH (1U) 1113 #define L_VFCCU_FHFLTS00_STAT26(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT26_SHIFT)) & L_VFCCU_FHFLTS00_STAT26_MASK) 1114 1115 #define L_VFCCU_FHFLTS00_STAT27_MASK (0x8000000U) 1116 #define L_VFCCU_FHFLTS00_STAT27_SHIFT (27U) 1117 #define L_VFCCU_FHFLTS00_STAT27_WIDTH (1U) 1118 #define L_VFCCU_FHFLTS00_STAT27(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT27_SHIFT)) & L_VFCCU_FHFLTS00_STAT27_MASK) 1119 1120 #define L_VFCCU_FHFLTS00_STAT28_MASK (0x10000000U) 1121 #define L_VFCCU_FHFLTS00_STAT28_SHIFT (28U) 1122 #define L_VFCCU_FHFLTS00_STAT28_WIDTH (1U) 1123 #define L_VFCCU_FHFLTS00_STAT28(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT28_SHIFT)) & L_VFCCU_FHFLTS00_STAT28_MASK) 1124 1125 #define L_VFCCU_FHFLTS00_STAT29_MASK (0x20000000U) 1126 #define L_VFCCU_FHFLTS00_STAT29_SHIFT (29U) 1127 #define L_VFCCU_FHFLTS00_STAT29_WIDTH (1U) 1128 #define L_VFCCU_FHFLTS00_STAT29(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT29_SHIFT)) & L_VFCCU_FHFLTS00_STAT29_MASK) 1129 1130 #define L_VFCCU_FHFLTS00_STAT30_MASK (0x40000000U) 1131 #define L_VFCCU_FHFLTS00_STAT30_SHIFT (30U) 1132 #define L_VFCCU_FHFLTS00_STAT30_WIDTH (1U) 1133 #define L_VFCCU_FHFLTS00_STAT30(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT30_SHIFT)) & L_VFCCU_FHFLTS00_STAT30_MASK) 1134 1135 #define L_VFCCU_FHFLTS00_STAT31_MASK (0x80000000U) 1136 #define L_VFCCU_FHFLTS00_STAT31_SHIFT (31U) 1137 #define L_VFCCU_FHFLTS00_STAT31_WIDTH (1U) 1138 #define L_VFCCU_FHFLTS00_STAT31(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTS00_STAT31_SHIFT)) & L_VFCCU_FHFLTS00_STAT31_MASK) 1139 /*! @} */ 1140 1141 /*! @name FHFLTRKC00 - Fault Reaction Set Configuration */ 1142 /*! @{ */ 1143 1144 #define L_VFCCU_FHFLTRKC00_RKNSEL0_MASK (0x7U) 1145 #define L_VFCCU_FHFLTRKC00_RKNSEL0_SHIFT (0U) 1146 #define L_VFCCU_FHFLTRKC00_RKNSEL0_WIDTH (3U) 1147 #define L_VFCCU_FHFLTRKC00_RKNSEL0(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC00_RKNSEL0_SHIFT)) & L_VFCCU_FHFLTRKC00_RKNSEL0_MASK) 1148 1149 #define L_VFCCU_FHFLTRKC00_RKNSEL1_MASK (0x70U) 1150 #define L_VFCCU_FHFLTRKC00_RKNSEL1_SHIFT (4U) 1151 #define L_VFCCU_FHFLTRKC00_RKNSEL1_WIDTH (3U) 1152 #define L_VFCCU_FHFLTRKC00_RKNSEL1(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC00_RKNSEL1_SHIFT)) & L_VFCCU_FHFLTRKC00_RKNSEL1_MASK) 1153 1154 #define L_VFCCU_FHFLTRKC00_RKNSEL2_MASK (0x700U) 1155 #define L_VFCCU_FHFLTRKC00_RKNSEL2_SHIFT (8U) 1156 #define L_VFCCU_FHFLTRKC00_RKNSEL2_WIDTH (3U) 1157 #define L_VFCCU_FHFLTRKC00_RKNSEL2(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC00_RKNSEL2_SHIFT)) & L_VFCCU_FHFLTRKC00_RKNSEL2_MASK) 1158 1159 #define L_VFCCU_FHFLTRKC00_RKNSEL3_MASK (0x7000U) 1160 #define L_VFCCU_FHFLTRKC00_RKNSEL3_SHIFT (12U) 1161 #define L_VFCCU_FHFLTRKC00_RKNSEL3_WIDTH (3U) 1162 #define L_VFCCU_FHFLTRKC00_RKNSEL3(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC00_RKNSEL3_SHIFT)) & L_VFCCU_FHFLTRKC00_RKNSEL3_MASK) 1163 1164 #define L_VFCCU_FHFLTRKC00_RKNSEL4_MASK (0x70000U) 1165 #define L_VFCCU_FHFLTRKC00_RKNSEL4_SHIFT (16U) 1166 #define L_VFCCU_FHFLTRKC00_RKNSEL4_WIDTH (3U) 1167 #define L_VFCCU_FHFLTRKC00_RKNSEL4(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC00_RKNSEL4_SHIFT)) & L_VFCCU_FHFLTRKC00_RKNSEL4_MASK) 1168 1169 #define L_VFCCU_FHFLTRKC00_RKNSEL5_MASK (0x700000U) 1170 #define L_VFCCU_FHFLTRKC00_RKNSEL5_SHIFT (20U) 1171 #define L_VFCCU_FHFLTRKC00_RKNSEL5_WIDTH (3U) 1172 #define L_VFCCU_FHFLTRKC00_RKNSEL5(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC00_RKNSEL5_SHIFT)) & L_VFCCU_FHFLTRKC00_RKNSEL5_MASK) 1173 1174 #define L_VFCCU_FHFLTRKC00_RKNSEL6_MASK (0x7000000U) 1175 #define L_VFCCU_FHFLTRKC00_RKNSEL6_SHIFT (24U) 1176 #define L_VFCCU_FHFLTRKC00_RKNSEL6_WIDTH (3U) 1177 #define L_VFCCU_FHFLTRKC00_RKNSEL6(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC00_RKNSEL6_SHIFT)) & L_VFCCU_FHFLTRKC00_RKNSEL6_MASK) 1178 1179 #define L_VFCCU_FHFLTRKC00_RKNSEL7_MASK (0x70000000U) 1180 #define L_VFCCU_FHFLTRKC00_RKNSEL7_SHIFT (28U) 1181 #define L_VFCCU_FHFLTRKC00_RKNSEL7_WIDTH (3U) 1182 #define L_VFCCU_FHFLTRKC00_RKNSEL7(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC00_RKNSEL7_SHIFT)) & L_VFCCU_FHFLTRKC00_RKNSEL7_MASK) 1183 /*! @} */ 1184 1185 /*! @name FHFLTRKC01 - Fault Reaction Set Configuration */ 1186 /*! @{ */ 1187 1188 #define L_VFCCU_FHFLTRKC01_RKNSEL8_MASK (0x7U) 1189 #define L_VFCCU_FHFLTRKC01_RKNSEL8_SHIFT (0U) 1190 #define L_VFCCU_FHFLTRKC01_RKNSEL8_WIDTH (3U) 1191 #define L_VFCCU_FHFLTRKC01_RKNSEL8(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC01_RKNSEL8_SHIFT)) & L_VFCCU_FHFLTRKC01_RKNSEL8_MASK) 1192 1193 #define L_VFCCU_FHFLTRKC01_RKNSEL9_MASK (0x70U) 1194 #define L_VFCCU_FHFLTRKC01_RKNSEL9_SHIFT (4U) 1195 #define L_VFCCU_FHFLTRKC01_RKNSEL9_WIDTH (3U) 1196 #define L_VFCCU_FHFLTRKC01_RKNSEL9(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC01_RKNSEL9_SHIFT)) & L_VFCCU_FHFLTRKC01_RKNSEL9_MASK) 1197 1198 #define L_VFCCU_FHFLTRKC01_RKNSEL10_MASK (0x700U) 1199 #define L_VFCCU_FHFLTRKC01_RKNSEL10_SHIFT (8U) 1200 #define L_VFCCU_FHFLTRKC01_RKNSEL10_WIDTH (3U) 1201 #define L_VFCCU_FHFLTRKC01_RKNSEL10(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC01_RKNSEL10_SHIFT)) & L_VFCCU_FHFLTRKC01_RKNSEL10_MASK) 1202 1203 #define L_VFCCU_FHFLTRKC01_RKNSEL11_MASK (0x7000U) 1204 #define L_VFCCU_FHFLTRKC01_RKNSEL11_SHIFT (12U) 1205 #define L_VFCCU_FHFLTRKC01_RKNSEL11_WIDTH (3U) 1206 #define L_VFCCU_FHFLTRKC01_RKNSEL11(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC01_RKNSEL11_SHIFT)) & L_VFCCU_FHFLTRKC01_RKNSEL11_MASK) 1207 1208 #define L_VFCCU_FHFLTRKC01_RKNSEL12_MASK (0x70000U) 1209 #define L_VFCCU_FHFLTRKC01_RKNSEL12_SHIFT (16U) 1210 #define L_VFCCU_FHFLTRKC01_RKNSEL12_WIDTH (3U) 1211 #define L_VFCCU_FHFLTRKC01_RKNSEL12(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC01_RKNSEL12_SHIFT)) & L_VFCCU_FHFLTRKC01_RKNSEL12_MASK) 1212 1213 #define L_VFCCU_FHFLTRKC01_RKNSEL13_MASK (0x700000U) 1214 #define L_VFCCU_FHFLTRKC01_RKNSEL13_SHIFT (20U) 1215 #define L_VFCCU_FHFLTRKC01_RKNSEL13_WIDTH (3U) 1216 #define L_VFCCU_FHFLTRKC01_RKNSEL13(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC01_RKNSEL13_SHIFT)) & L_VFCCU_FHFLTRKC01_RKNSEL13_MASK) 1217 1218 #define L_VFCCU_FHFLTRKC01_RKNSEL14_MASK (0x7000000U) 1219 #define L_VFCCU_FHFLTRKC01_RKNSEL14_SHIFT (24U) 1220 #define L_VFCCU_FHFLTRKC01_RKNSEL14_WIDTH (3U) 1221 #define L_VFCCU_FHFLTRKC01_RKNSEL14(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC01_RKNSEL14_SHIFT)) & L_VFCCU_FHFLTRKC01_RKNSEL14_MASK) 1222 1223 #define L_VFCCU_FHFLTRKC01_RKNSEL15_MASK (0x70000000U) 1224 #define L_VFCCU_FHFLTRKC01_RKNSEL15_SHIFT (28U) 1225 #define L_VFCCU_FHFLTRKC01_RKNSEL15_WIDTH (3U) 1226 #define L_VFCCU_FHFLTRKC01_RKNSEL15(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC01_RKNSEL15_SHIFT)) & L_VFCCU_FHFLTRKC01_RKNSEL15_MASK) 1227 /*! @} */ 1228 1229 /*! @name FHFLTRKC02 - Fault Reaction Set Configuration */ 1230 /*! @{ */ 1231 1232 #define L_VFCCU_FHFLTRKC02_RKNSEL16_MASK (0x7U) 1233 #define L_VFCCU_FHFLTRKC02_RKNSEL16_SHIFT (0U) 1234 #define L_VFCCU_FHFLTRKC02_RKNSEL16_WIDTH (3U) 1235 #define L_VFCCU_FHFLTRKC02_RKNSEL16(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC02_RKNSEL16_SHIFT)) & L_VFCCU_FHFLTRKC02_RKNSEL16_MASK) 1236 1237 #define L_VFCCU_FHFLTRKC02_RKNSEL17_MASK (0x70U) 1238 #define L_VFCCU_FHFLTRKC02_RKNSEL17_SHIFT (4U) 1239 #define L_VFCCU_FHFLTRKC02_RKNSEL17_WIDTH (3U) 1240 #define L_VFCCU_FHFLTRKC02_RKNSEL17(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC02_RKNSEL17_SHIFT)) & L_VFCCU_FHFLTRKC02_RKNSEL17_MASK) 1241 1242 #define L_VFCCU_FHFLTRKC02_RKNSEL18_MASK (0x700U) 1243 #define L_VFCCU_FHFLTRKC02_RKNSEL18_SHIFT (8U) 1244 #define L_VFCCU_FHFLTRKC02_RKNSEL18_WIDTH (3U) 1245 #define L_VFCCU_FHFLTRKC02_RKNSEL18(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC02_RKNSEL18_SHIFT)) & L_VFCCU_FHFLTRKC02_RKNSEL18_MASK) 1246 1247 #define L_VFCCU_FHFLTRKC02_RKNSEL19_MASK (0x7000U) 1248 #define L_VFCCU_FHFLTRKC02_RKNSEL19_SHIFT (12U) 1249 #define L_VFCCU_FHFLTRKC02_RKNSEL19_WIDTH (3U) 1250 #define L_VFCCU_FHFLTRKC02_RKNSEL19(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC02_RKNSEL19_SHIFT)) & L_VFCCU_FHFLTRKC02_RKNSEL19_MASK) 1251 1252 #define L_VFCCU_FHFLTRKC02_RKNSEL20_MASK (0x70000U) 1253 #define L_VFCCU_FHFLTRKC02_RKNSEL20_SHIFT (16U) 1254 #define L_VFCCU_FHFLTRKC02_RKNSEL20_WIDTH (3U) 1255 #define L_VFCCU_FHFLTRKC02_RKNSEL20(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC02_RKNSEL20_SHIFT)) & L_VFCCU_FHFLTRKC02_RKNSEL20_MASK) 1256 1257 #define L_VFCCU_FHFLTRKC02_RKNSEL21_MASK (0x700000U) 1258 #define L_VFCCU_FHFLTRKC02_RKNSEL21_SHIFT (20U) 1259 #define L_VFCCU_FHFLTRKC02_RKNSEL21_WIDTH (3U) 1260 #define L_VFCCU_FHFLTRKC02_RKNSEL21(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC02_RKNSEL21_SHIFT)) & L_VFCCU_FHFLTRKC02_RKNSEL21_MASK) 1261 1262 #define L_VFCCU_FHFLTRKC02_RKNSEL22_MASK (0x7000000U) 1263 #define L_VFCCU_FHFLTRKC02_RKNSEL22_SHIFT (24U) 1264 #define L_VFCCU_FHFLTRKC02_RKNSEL22_WIDTH (3U) 1265 #define L_VFCCU_FHFLTRKC02_RKNSEL22(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC02_RKNSEL22_SHIFT)) & L_VFCCU_FHFLTRKC02_RKNSEL22_MASK) 1266 1267 #define L_VFCCU_FHFLTRKC02_RKNSEL23_MASK (0x70000000U) 1268 #define L_VFCCU_FHFLTRKC02_RKNSEL23_SHIFT (28U) 1269 #define L_VFCCU_FHFLTRKC02_RKNSEL23_WIDTH (3U) 1270 #define L_VFCCU_FHFLTRKC02_RKNSEL23(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC02_RKNSEL23_SHIFT)) & L_VFCCU_FHFLTRKC02_RKNSEL23_MASK) 1271 /*! @} */ 1272 1273 /*! @name FHFLTRKC03 - Fault Reaction Set Configuration */ 1274 /*! @{ */ 1275 1276 #define L_VFCCU_FHFLTRKC03_RKNSEL24_MASK (0x7U) 1277 #define L_VFCCU_FHFLTRKC03_RKNSEL24_SHIFT (0U) 1278 #define L_VFCCU_FHFLTRKC03_RKNSEL24_WIDTH (3U) 1279 #define L_VFCCU_FHFLTRKC03_RKNSEL24(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC03_RKNSEL24_SHIFT)) & L_VFCCU_FHFLTRKC03_RKNSEL24_MASK) 1280 1281 #define L_VFCCU_FHFLTRKC03_RKNSEL25_MASK (0x70U) 1282 #define L_VFCCU_FHFLTRKC03_RKNSEL25_SHIFT (4U) 1283 #define L_VFCCU_FHFLTRKC03_RKNSEL25_WIDTH (3U) 1284 #define L_VFCCU_FHFLTRKC03_RKNSEL25(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC03_RKNSEL25_SHIFT)) & L_VFCCU_FHFLTRKC03_RKNSEL25_MASK) 1285 1286 #define L_VFCCU_FHFLTRKC03_RKNSEL26_MASK (0x700U) 1287 #define L_VFCCU_FHFLTRKC03_RKNSEL26_SHIFT (8U) 1288 #define L_VFCCU_FHFLTRKC03_RKNSEL26_WIDTH (3U) 1289 #define L_VFCCU_FHFLTRKC03_RKNSEL26(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC03_RKNSEL26_SHIFT)) & L_VFCCU_FHFLTRKC03_RKNSEL26_MASK) 1290 1291 #define L_VFCCU_FHFLTRKC03_RKNSEL27_MASK (0x7000U) 1292 #define L_VFCCU_FHFLTRKC03_RKNSEL27_SHIFT (12U) 1293 #define L_VFCCU_FHFLTRKC03_RKNSEL27_WIDTH (3U) 1294 #define L_VFCCU_FHFLTRKC03_RKNSEL27(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC03_RKNSEL27_SHIFT)) & L_VFCCU_FHFLTRKC03_RKNSEL27_MASK) 1295 1296 #define L_VFCCU_FHFLTRKC03_RKNSEL28_MASK (0x70000U) 1297 #define L_VFCCU_FHFLTRKC03_RKNSEL28_SHIFT (16U) 1298 #define L_VFCCU_FHFLTRKC03_RKNSEL28_WIDTH (3U) 1299 #define L_VFCCU_FHFLTRKC03_RKNSEL28(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC03_RKNSEL28_SHIFT)) & L_VFCCU_FHFLTRKC03_RKNSEL28_MASK) 1300 1301 #define L_VFCCU_FHFLTRKC03_RKNSEL29_MASK (0x700000U) 1302 #define L_VFCCU_FHFLTRKC03_RKNSEL29_SHIFT (20U) 1303 #define L_VFCCU_FHFLTRKC03_RKNSEL29_WIDTH (3U) 1304 #define L_VFCCU_FHFLTRKC03_RKNSEL29(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC03_RKNSEL29_SHIFT)) & L_VFCCU_FHFLTRKC03_RKNSEL29_MASK) 1305 1306 #define L_VFCCU_FHFLTRKC03_RKNSEL30_MASK (0x7000000U) 1307 #define L_VFCCU_FHFLTRKC03_RKNSEL30_SHIFT (24U) 1308 #define L_VFCCU_FHFLTRKC03_RKNSEL30_WIDTH (3U) 1309 #define L_VFCCU_FHFLTRKC03_RKNSEL30(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC03_RKNSEL30_SHIFT)) & L_VFCCU_FHFLTRKC03_RKNSEL30_MASK) 1310 1311 #define L_VFCCU_FHFLTRKC03_RKNSEL31_MASK (0x70000000U) 1312 #define L_VFCCU_FHFLTRKC03_RKNSEL31_SHIFT (28U) 1313 #define L_VFCCU_FHFLTRKC03_RKNSEL31_WIDTH (3U) 1314 #define L_VFCCU_FHFLTRKC03_RKNSEL31(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHFLTRKC03_RKNSEL31_SHIFT)) & L_VFCCU_FHFLTRKC03_RKNSEL31_MASK) 1315 /*! @} */ 1316 1317 /*! @name FHIMRKC0_00 - Immediate Reaction Configuration */ 1318 /*! @{ */ 1319 1320 #define L_VFCCU_FHIMRKC0_00_RKNEN0_MASK (0x1U) 1321 #define L_VFCCU_FHIMRKC0_00_RKNEN0_SHIFT (0U) 1322 #define L_VFCCU_FHIMRKC0_00_RKNEN0_WIDTH (1U) 1323 #define L_VFCCU_FHIMRKC0_00_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_00_RKNEN0_SHIFT)) & L_VFCCU_FHIMRKC0_00_RKNEN0_MASK) 1324 1325 #define L_VFCCU_FHIMRKC0_00_RKNEN1_MASK (0x2U) 1326 #define L_VFCCU_FHIMRKC0_00_RKNEN1_SHIFT (1U) 1327 #define L_VFCCU_FHIMRKC0_00_RKNEN1_WIDTH (1U) 1328 #define L_VFCCU_FHIMRKC0_00_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_00_RKNEN1_SHIFT)) & L_VFCCU_FHIMRKC0_00_RKNEN1_MASK) 1329 1330 #define L_VFCCU_FHIMRKC0_00_RKNEN2_MASK (0x4U) 1331 #define L_VFCCU_FHIMRKC0_00_RKNEN2_SHIFT (2U) 1332 #define L_VFCCU_FHIMRKC0_00_RKNEN2_WIDTH (1U) 1333 #define L_VFCCU_FHIMRKC0_00_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_00_RKNEN2_SHIFT)) & L_VFCCU_FHIMRKC0_00_RKNEN2_MASK) 1334 1335 #define L_VFCCU_FHIMRKC0_00_RKNEN3_MASK (0x8U) 1336 #define L_VFCCU_FHIMRKC0_00_RKNEN3_SHIFT (3U) 1337 #define L_VFCCU_FHIMRKC0_00_RKNEN3_WIDTH (1U) 1338 #define L_VFCCU_FHIMRKC0_00_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_00_RKNEN3_SHIFT)) & L_VFCCU_FHIMRKC0_00_RKNEN3_MASK) 1339 1340 #define L_VFCCU_FHIMRKC0_00_RKNEN4_MASK (0x10U) 1341 #define L_VFCCU_FHIMRKC0_00_RKNEN4_SHIFT (4U) 1342 #define L_VFCCU_FHIMRKC0_00_RKNEN4_WIDTH (1U) 1343 #define L_VFCCU_FHIMRKC0_00_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_00_RKNEN4_SHIFT)) & L_VFCCU_FHIMRKC0_00_RKNEN4_MASK) 1344 1345 #define L_VFCCU_FHIMRKC0_00_RKNEN5_MASK (0x20U) 1346 #define L_VFCCU_FHIMRKC0_00_RKNEN5_SHIFT (5U) 1347 #define L_VFCCU_FHIMRKC0_00_RKNEN5_WIDTH (1U) 1348 #define L_VFCCU_FHIMRKC0_00_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_00_RKNEN5_SHIFT)) & L_VFCCU_FHIMRKC0_00_RKNEN5_MASK) 1349 /*! @} */ 1350 1351 /*! @name FHIMRKC0_10 - Immediate Reaction Configuration */ 1352 /*! @{ */ 1353 1354 #define L_VFCCU_FHIMRKC0_10_RKNEN0_MASK (0x1U) 1355 #define L_VFCCU_FHIMRKC0_10_RKNEN0_SHIFT (0U) 1356 #define L_VFCCU_FHIMRKC0_10_RKNEN0_WIDTH (1U) 1357 #define L_VFCCU_FHIMRKC0_10_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_10_RKNEN0_SHIFT)) & L_VFCCU_FHIMRKC0_10_RKNEN0_MASK) 1358 1359 #define L_VFCCU_FHIMRKC0_10_RKNEN1_MASK (0x2U) 1360 #define L_VFCCU_FHIMRKC0_10_RKNEN1_SHIFT (1U) 1361 #define L_VFCCU_FHIMRKC0_10_RKNEN1_WIDTH (1U) 1362 #define L_VFCCU_FHIMRKC0_10_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_10_RKNEN1_SHIFT)) & L_VFCCU_FHIMRKC0_10_RKNEN1_MASK) 1363 1364 #define L_VFCCU_FHIMRKC0_10_RKNEN2_MASK (0x4U) 1365 #define L_VFCCU_FHIMRKC0_10_RKNEN2_SHIFT (2U) 1366 #define L_VFCCU_FHIMRKC0_10_RKNEN2_WIDTH (1U) 1367 #define L_VFCCU_FHIMRKC0_10_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_10_RKNEN2_SHIFT)) & L_VFCCU_FHIMRKC0_10_RKNEN2_MASK) 1368 1369 #define L_VFCCU_FHIMRKC0_10_RKNEN3_MASK (0x8U) 1370 #define L_VFCCU_FHIMRKC0_10_RKNEN3_SHIFT (3U) 1371 #define L_VFCCU_FHIMRKC0_10_RKNEN3_WIDTH (1U) 1372 #define L_VFCCU_FHIMRKC0_10_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_10_RKNEN3_SHIFT)) & L_VFCCU_FHIMRKC0_10_RKNEN3_MASK) 1373 1374 #define L_VFCCU_FHIMRKC0_10_RKNEN4_MASK (0x10U) 1375 #define L_VFCCU_FHIMRKC0_10_RKNEN4_SHIFT (4U) 1376 #define L_VFCCU_FHIMRKC0_10_RKNEN4_WIDTH (1U) 1377 #define L_VFCCU_FHIMRKC0_10_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_10_RKNEN4_SHIFT)) & L_VFCCU_FHIMRKC0_10_RKNEN4_MASK) 1378 1379 #define L_VFCCU_FHIMRKC0_10_RKNEN5_MASK (0x20U) 1380 #define L_VFCCU_FHIMRKC0_10_RKNEN5_SHIFT (5U) 1381 #define L_VFCCU_FHIMRKC0_10_RKNEN5_WIDTH (1U) 1382 #define L_VFCCU_FHIMRKC0_10_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_10_RKNEN5_SHIFT)) & L_VFCCU_FHIMRKC0_10_RKNEN5_MASK) 1383 /*! @} */ 1384 1385 /*! @name FHIMRKC0_20 - Immediate Reaction Configuration */ 1386 /*! @{ */ 1387 1388 #define L_VFCCU_FHIMRKC0_20_RKNEN0_MASK (0x1U) 1389 #define L_VFCCU_FHIMRKC0_20_RKNEN0_SHIFT (0U) 1390 #define L_VFCCU_FHIMRKC0_20_RKNEN0_WIDTH (1U) 1391 #define L_VFCCU_FHIMRKC0_20_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_20_RKNEN0_SHIFT)) & L_VFCCU_FHIMRKC0_20_RKNEN0_MASK) 1392 1393 #define L_VFCCU_FHIMRKC0_20_RKNEN1_MASK (0x2U) 1394 #define L_VFCCU_FHIMRKC0_20_RKNEN1_SHIFT (1U) 1395 #define L_VFCCU_FHIMRKC0_20_RKNEN1_WIDTH (1U) 1396 #define L_VFCCU_FHIMRKC0_20_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_20_RKNEN1_SHIFT)) & L_VFCCU_FHIMRKC0_20_RKNEN1_MASK) 1397 1398 #define L_VFCCU_FHIMRKC0_20_RKNEN2_MASK (0x4U) 1399 #define L_VFCCU_FHIMRKC0_20_RKNEN2_SHIFT (2U) 1400 #define L_VFCCU_FHIMRKC0_20_RKNEN2_WIDTH (1U) 1401 #define L_VFCCU_FHIMRKC0_20_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_20_RKNEN2_SHIFT)) & L_VFCCU_FHIMRKC0_20_RKNEN2_MASK) 1402 1403 #define L_VFCCU_FHIMRKC0_20_RKNEN3_MASK (0x8U) 1404 #define L_VFCCU_FHIMRKC0_20_RKNEN3_SHIFT (3U) 1405 #define L_VFCCU_FHIMRKC0_20_RKNEN3_WIDTH (1U) 1406 #define L_VFCCU_FHIMRKC0_20_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_20_RKNEN3_SHIFT)) & L_VFCCU_FHIMRKC0_20_RKNEN3_MASK) 1407 1408 #define L_VFCCU_FHIMRKC0_20_RKNEN4_MASK (0x10U) 1409 #define L_VFCCU_FHIMRKC0_20_RKNEN4_SHIFT (4U) 1410 #define L_VFCCU_FHIMRKC0_20_RKNEN4_WIDTH (1U) 1411 #define L_VFCCU_FHIMRKC0_20_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_20_RKNEN4_SHIFT)) & L_VFCCU_FHIMRKC0_20_RKNEN4_MASK) 1412 1413 #define L_VFCCU_FHIMRKC0_20_RKNEN5_MASK (0x20U) 1414 #define L_VFCCU_FHIMRKC0_20_RKNEN5_SHIFT (5U) 1415 #define L_VFCCU_FHIMRKC0_20_RKNEN5_WIDTH (1U) 1416 #define L_VFCCU_FHIMRKC0_20_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_20_RKNEN5_SHIFT)) & L_VFCCU_FHIMRKC0_20_RKNEN5_MASK) 1417 /*! @} */ 1418 1419 /*! @name FHIMRKC0_30 - Immediate Reaction Configuration */ 1420 /*! @{ */ 1421 1422 #define L_VFCCU_FHIMRKC0_30_RKNEN0_MASK (0x1U) 1423 #define L_VFCCU_FHIMRKC0_30_RKNEN0_SHIFT (0U) 1424 #define L_VFCCU_FHIMRKC0_30_RKNEN0_WIDTH (1U) 1425 #define L_VFCCU_FHIMRKC0_30_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_30_RKNEN0_SHIFT)) & L_VFCCU_FHIMRKC0_30_RKNEN0_MASK) 1426 1427 #define L_VFCCU_FHIMRKC0_30_RKNEN1_MASK (0x2U) 1428 #define L_VFCCU_FHIMRKC0_30_RKNEN1_SHIFT (1U) 1429 #define L_VFCCU_FHIMRKC0_30_RKNEN1_WIDTH (1U) 1430 #define L_VFCCU_FHIMRKC0_30_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_30_RKNEN1_SHIFT)) & L_VFCCU_FHIMRKC0_30_RKNEN1_MASK) 1431 1432 #define L_VFCCU_FHIMRKC0_30_RKNEN2_MASK (0x4U) 1433 #define L_VFCCU_FHIMRKC0_30_RKNEN2_SHIFT (2U) 1434 #define L_VFCCU_FHIMRKC0_30_RKNEN2_WIDTH (1U) 1435 #define L_VFCCU_FHIMRKC0_30_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_30_RKNEN2_SHIFT)) & L_VFCCU_FHIMRKC0_30_RKNEN2_MASK) 1436 1437 #define L_VFCCU_FHIMRKC0_30_RKNEN3_MASK (0x8U) 1438 #define L_VFCCU_FHIMRKC0_30_RKNEN3_SHIFT (3U) 1439 #define L_VFCCU_FHIMRKC0_30_RKNEN3_WIDTH (1U) 1440 #define L_VFCCU_FHIMRKC0_30_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_30_RKNEN3_SHIFT)) & L_VFCCU_FHIMRKC0_30_RKNEN3_MASK) 1441 1442 #define L_VFCCU_FHIMRKC0_30_RKNEN4_MASK (0x10U) 1443 #define L_VFCCU_FHIMRKC0_30_RKNEN4_SHIFT (4U) 1444 #define L_VFCCU_FHIMRKC0_30_RKNEN4_WIDTH (1U) 1445 #define L_VFCCU_FHIMRKC0_30_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_30_RKNEN4_SHIFT)) & L_VFCCU_FHIMRKC0_30_RKNEN4_MASK) 1446 1447 #define L_VFCCU_FHIMRKC0_30_RKNEN5_MASK (0x20U) 1448 #define L_VFCCU_FHIMRKC0_30_RKNEN5_SHIFT (5U) 1449 #define L_VFCCU_FHIMRKC0_30_RKNEN5_WIDTH (1U) 1450 #define L_VFCCU_FHIMRKC0_30_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_30_RKNEN5_SHIFT)) & L_VFCCU_FHIMRKC0_30_RKNEN5_MASK) 1451 /*! @} */ 1452 1453 /*! @name FHIMRKC0_40 - Immediate Reaction Configuration */ 1454 /*! @{ */ 1455 1456 #define L_VFCCU_FHIMRKC0_40_RKNEN0_MASK (0x1U) 1457 #define L_VFCCU_FHIMRKC0_40_RKNEN0_SHIFT (0U) 1458 #define L_VFCCU_FHIMRKC0_40_RKNEN0_WIDTH (1U) 1459 #define L_VFCCU_FHIMRKC0_40_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_40_RKNEN0_SHIFT)) & L_VFCCU_FHIMRKC0_40_RKNEN0_MASK) 1460 1461 #define L_VFCCU_FHIMRKC0_40_RKNEN1_MASK (0x2U) 1462 #define L_VFCCU_FHIMRKC0_40_RKNEN1_SHIFT (1U) 1463 #define L_VFCCU_FHIMRKC0_40_RKNEN1_WIDTH (1U) 1464 #define L_VFCCU_FHIMRKC0_40_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_40_RKNEN1_SHIFT)) & L_VFCCU_FHIMRKC0_40_RKNEN1_MASK) 1465 1466 #define L_VFCCU_FHIMRKC0_40_RKNEN2_MASK (0x4U) 1467 #define L_VFCCU_FHIMRKC0_40_RKNEN2_SHIFT (2U) 1468 #define L_VFCCU_FHIMRKC0_40_RKNEN2_WIDTH (1U) 1469 #define L_VFCCU_FHIMRKC0_40_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_40_RKNEN2_SHIFT)) & L_VFCCU_FHIMRKC0_40_RKNEN2_MASK) 1470 1471 #define L_VFCCU_FHIMRKC0_40_RKNEN3_MASK (0x8U) 1472 #define L_VFCCU_FHIMRKC0_40_RKNEN3_SHIFT (3U) 1473 #define L_VFCCU_FHIMRKC0_40_RKNEN3_WIDTH (1U) 1474 #define L_VFCCU_FHIMRKC0_40_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_40_RKNEN3_SHIFT)) & L_VFCCU_FHIMRKC0_40_RKNEN3_MASK) 1475 1476 #define L_VFCCU_FHIMRKC0_40_RKNEN4_MASK (0x10U) 1477 #define L_VFCCU_FHIMRKC0_40_RKNEN4_SHIFT (4U) 1478 #define L_VFCCU_FHIMRKC0_40_RKNEN4_WIDTH (1U) 1479 #define L_VFCCU_FHIMRKC0_40_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_40_RKNEN4_SHIFT)) & L_VFCCU_FHIMRKC0_40_RKNEN4_MASK) 1480 1481 #define L_VFCCU_FHIMRKC0_40_RKNEN5_MASK (0x20U) 1482 #define L_VFCCU_FHIMRKC0_40_RKNEN5_SHIFT (5U) 1483 #define L_VFCCU_FHIMRKC0_40_RKNEN5_WIDTH (1U) 1484 #define L_VFCCU_FHIMRKC0_40_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_40_RKNEN5_SHIFT)) & L_VFCCU_FHIMRKC0_40_RKNEN5_MASK) 1485 /*! @} */ 1486 1487 /*! @name FHIMRKC0_50 - Immediate Reaction Configuration */ 1488 /*! @{ */ 1489 1490 #define L_VFCCU_FHIMRKC0_50_RKNEN0_MASK (0x1U) 1491 #define L_VFCCU_FHIMRKC0_50_RKNEN0_SHIFT (0U) 1492 #define L_VFCCU_FHIMRKC0_50_RKNEN0_WIDTH (1U) 1493 #define L_VFCCU_FHIMRKC0_50_RKNEN0(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_50_RKNEN0_SHIFT)) & L_VFCCU_FHIMRKC0_50_RKNEN0_MASK) 1494 1495 #define L_VFCCU_FHIMRKC0_50_RKNEN1_MASK (0x2U) 1496 #define L_VFCCU_FHIMRKC0_50_RKNEN1_SHIFT (1U) 1497 #define L_VFCCU_FHIMRKC0_50_RKNEN1_WIDTH (1U) 1498 #define L_VFCCU_FHIMRKC0_50_RKNEN1(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_50_RKNEN1_SHIFT)) & L_VFCCU_FHIMRKC0_50_RKNEN1_MASK) 1499 1500 #define L_VFCCU_FHIMRKC0_50_RKNEN2_MASK (0x4U) 1501 #define L_VFCCU_FHIMRKC0_50_RKNEN2_SHIFT (2U) 1502 #define L_VFCCU_FHIMRKC0_50_RKNEN2_WIDTH (1U) 1503 #define L_VFCCU_FHIMRKC0_50_RKNEN2(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_50_RKNEN2_SHIFT)) & L_VFCCU_FHIMRKC0_50_RKNEN2_MASK) 1504 1505 #define L_VFCCU_FHIMRKC0_50_RKNEN3_MASK (0x8U) 1506 #define L_VFCCU_FHIMRKC0_50_RKNEN3_SHIFT (3U) 1507 #define L_VFCCU_FHIMRKC0_50_RKNEN3_WIDTH (1U) 1508 #define L_VFCCU_FHIMRKC0_50_RKNEN3(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_50_RKNEN3_SHIFT)) & L_VFCCU_FHIMRKC0_50_RKNEN3_MASK) 1509 1510 #define L_VFCCU_FHIMRKC0_50_RKNEN4_MASK (0x10U) 1511 #define L_VFCCU_FHIMRKC0_50_RKNEN4_SHIFT (4U) 1512 #define L_VFCCU_FHIMRKC0_50_RKNEN4_WIDTH (1U) 1513 #define L_VFCCU_FHIMRKC0_50_RKNEN4(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_50_RKNEN4_SHIFT)) & L_VFCCU_FHIMRKC0_50_RKNEN4_MASK) 1514 1515 #define L_VFCCU_FHIMRKC0_50_RKNEN5_MASK (0x20U) 1516 #define L_VFCCU_FHIMRKC0_50_RKNEN5_SHIFT (5U) 1517 #define L_VFCCU_FHIMRKC0_50_RKNEN5_WIDTH (1U) 1518 #define L_VFCCU_FHIMRKC0_50_RKNEN5(x) (((uint32_t)(((uint32_t)(x)) << L_VFCCU_FHIMRKC0_50_RKNEN5_SHIFT)) & L_VFCCU_FHIMRKC0_50_RKNEN5_MASK) 1519 /*! @} */ 1520 1521 /*! 1522 * @} 1523 */ /* end of group L_VFCCU_Register_Masks */ 1524 1525 /*! 1526 * @} 1527 */ /* end of group L_VFCCU_Peripheral_Access_Layer */ 1528 1529 #endif /* #if !defined(S32Z2_L_VFCCU_H_) */ 1530
