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Searched refs:LTC_VID1_IP_ID_MASK (Results 1 – 14 of 14) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MKW31Z4/
DMKW31Z4.h4229 #define LTC_VID1_IP_ID_MASK (0xFFFF0000U) macro
4231 … (((uint32_t)(((uint32_t)(x)) << LTC_VID1_IP_ID_SHIFT)) & LTC_VID1_IP_ID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW30Z4/
DMKW30Z4.h4210 #define LTC_VID1_IP_ID_MASK 0xFFFF0000u macro
4213 …x) (((uint32_t)(((uint32_t)(x))<<LTC_VID1_IP_ID_SHIFT))&LTC_VID1_IP_ID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW21Z4/
DMKW21Z4.h4158 #define LTC_VID1_IP_ID_MASK (0xFFFF0000U) macro
4160 … (((uint32_t)(((uint32_t)(x)) << LTC_VID1_IP_ID_SHIFT)) & LTC_VID1_IP_ID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW20Z4/
DMKW20Z4.h4210 #define LTC_VID1_IP_ID_MASK 0xFFFF0000u macro
4213 …x) (((uint32_t)(((uint32_t)(x))<<LTC_VID1_IP_ID_SHIFT))&LTC_VID1_IP_ID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW41Z4/
DMKW41Z4.h4229 #define LTC_VID1_IP_ID_MASK (0xFFFF0000U) macro
4231 … (((uint32_t)(((uint32_t)(x)) << LTC_VID1_IP_ID_SHIFT)) & LTC_VID1_IP_ID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW40Z4/
DMKW40Z4.h4210 #define LTC_VID1_IP_ID_MASK 0xFFFF0000u macro
4213 …x) (((uint32_t)(((uint32_t)(x))<<LTC_VID1_IP_ID_SHIFT))&LTC_VID1_IP_ID_MASK)
DMKW40Z4_extension.h13297 #define LTC_RD_VID1_IP_ID(base) ((LTC_VID1_REG(base) & LTC_VID1_IP_ID_MASK) >> LTC_VID1_IP_ID_SHIFT)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h16802 #define LTC_VID1_IP_ID_MASK (0xFFFF0000U) macro
16804 … (((uint32_t)(((uint32_t)(x)) << LTC_VID1_IP_ID_SHIFT)) & LTC_VID1_IP_ID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h16822 #define LTC_VID1_IP_ID_MASK (0xFFFF0000U) macro
16824 … (((uint32_t)(((uint32_t)(x)) << LTC_VID1_IP_ID_SHIFT)) & LTC_VID1_IP_ID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h16823 #define LTC_VID1_IP_ID_MASK (0xFFFF0000U) macro
16825 … (((uint32_t)(((uint32_t)(x)) << LTC_VID1_IP_ID_SHIFT)) & LTC_VID1_IP_ID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/
DMCXW716A.h22928 #define LTC_VID1_IP_ID_MASK (0xFFFF0000U) macro
22930 … (((uint32_t)(((uint32_t)(x)) << LTC_VID1_IP_ID_SHIFT)) & LTC_VID1_IP_ID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/
DMCXW716C.h25097 #define LTC_VID1_IP_ID_MASK (0xFFFF0000U) macro
25099 … (((uint32_t)(((uint32_t)(x)) << LTC_VID1_IP_ID_SHIFT)) & LTC_VID1_IP_ID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/
DMCXW727C_cm33_core0.h26002 #define LTC_VID1_IP_ID_MASK (0xFFFF0000U) macro
26005 … (((uint32_t)(((uint32_t)(x)) << LTC_VID1_IP_ID_SHIFT)) & LTC_VID1_IP_ID_MASK)
DMCXW727C_cm33_core1.h34303 #define LTC_VID1_IP_ID_MASK (0xFFFF0000U) macro
34306 … (((uint32_t)(((uint32_t)(x)) << LTC_VID1_IP_ID_SHIFT)) & LTC_VID1_IP_ID_MASK)