1 /*
2 ** ###################################################################
3 **     Compilers:           Keil ARM C/C++ Compiler
4 **                          Freescale C/C++ for Embedded ARM
5 **                          GNU C Compiler
6 **                          GNU C Compiler - CodeSourcery Sourcery G++
7 **                          IAR ANSI C/C++ Compiler for ARM
8 **
9 **     Reference manual:    MKW40Z160RM, Rev. 1.1, 4/2015
10 **     Version:             rev. 1.2, 2015-05-07
11 **     Build:               b150713
12 **
13 **     Abstract:
14 **         Extension to the CMSIS register access layer header.
15 **
16 **     Copyright (c) 2015 Freescale Semiconductor, Inc.
17 **     All rights reserved.
18 **
19 **     Redistribution and use in source and binary forms, with or without modification,
20 **     are permitted provided that the following conditions are met:
21 **
22 **     o Redistributions of source code must retain the above copyright notice, this list
23 **       of conditions and the following disclaimer.
24 **
25 **     o Redistributions in binary form must reproduce the above copyright notice, this
26 **       list of conditions and the following disclaimer in the documentation and/or
27 **       other materials provided with the distribution.
28 **
29 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
30 **       contributors may be used to endorse or promote products derived from this
31 **       software without specific prior written permission.
32 **
33 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
34 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
35 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
36 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
37 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
39 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
40 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
42 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43 **
44 **     http:                 www.freescale.com
45 **     mail:                 support@freescale.com
46 **
47 **     Revisions:
48 **     - rev. 1.0 (2014-07-17)
49 **         Initial version.
50 **     - rev. 1.1 (2015-03-05)
51 **         Update with reference manual rev 1.0
52 **     - rev. 1.2 (2015-05-07)
53 **         Update with reference manual rev 1.1
54 **
55 ** ###################################################################
56 */
57 
58 /*
59  * WARNING! DO NOT EDIT THIS FILE DIRECTLY!
60  *
61  * This file was generated automatically and any changes may be lost.
62  */
63 #ifndef __MKW40Z4_EXTENSION_H__
64 #define __MKW40Z4_EXTENSION_H__
65 
66 #include "MKW40Z4.h"
67 #include "fsl_bitaccess.h"
68 
69 #if defined(__IAR_SYSTEMS_ICC__)
70   /*
71    * Suppress "Error[Pm008]: sections of code should not be 'commented out' (MISRA C 2004 rule 2.4)"
72    * as some register descriptions contain code examples
73    */
74   #pragma diag_suppress=pm008
75 #endif
76 
77 /*
78  * MKW40Z4 ADC
79  *
80  * Analog-to-Digital Converter
81  *
82  * Registers defined in this header file:
83  * - ADC_SC1 - ADC Status and Control Registers 1
84  * - ADC_CFG1 - ADC Configuration Register 1
85  * - ADC_CFG2 - ADC Configuration Register 2
86  * - ADC_R - ADC Data Result Register
87  * - ADC_CV1 - Compare Value Registers
88  * - ADC_CV2 - Compare Value Registers
89  * - ADC_SC2 - Status and Control Register 2
90  * - ADC_SC3 - Status and Control Register 3
91  * - ADC_OFS - ADC Offset Correction Register
92  * - ADC_PG - ADC Plus-Side Gain Register
93  * - ADC_MG - ADC Minus-Side Gain Register
94  * - ADC_CLPD - ADC Plus-Side General Calibration Value Register
95  * - ADC_CLPS - ADC Plus-Side General Calibration Value Register
96  * - ADC_CLP4 - ADC Plus-Side General Calibration Value Register
97  * - ADC_CLP3 - ADC Plus-Side General Calibration Value Register
98  * - ADC_CLP2 - ADC Plus-Side General Calibration Value Register
99  * - ADC_CLP1 - ADC Plus-Side General Calibration Value Register
100  * - ADC_CLP0 - ADC Plus-Side General Calibration Value Register
101  * - ADC_CLMD - ADC Minus-Side General Calibration Value Register
102  * - ADC_CLMS - ADC Minus-Side General Calibration Value Register
103  * - ADC_CLM4 - ADC Minus-Side General Calibration Value Register
104  * - ADC_CLM3 - ADC Minus-Side General Calibration Value Register
105  * - ADC_CLM2 - ADC Minus-Side General Calibration Value Register
106  * - ADC_CLM1 - ADC Minus-Side General Calibration Value Register
107  * - ADC_CLM0 - ADC Minus-Side General Calibration Value Register
108  */
109 
110 #define ADC_INSTANCE_COUNT (1U) /*!< Number of instances of the ADC module. */
111 #define ADC0_IDX (0U) /*!< Instance number for ADC0. */
112 
113 /*******************************************************************************
114  * ADC_SC1 - ADC Status and Control Registers 1
115  ******************************************************************************/
116 
117 /*!
118  * @brief ADC_SC1 - ADC Status and Control Registers 1 (RW)
119  *
120  * Reset value: 0x0000001FU
121  *
122  * SC1A is used for both software and hardware trigger modes of operation. To
123  * allow sequential conversions of the ADC to be triggered by internal peripherals,
124  * the ADC can have more than one status and control register: one for each
125  * conversion. The SC1B-SC1n registers indicate potentially multiple SC1 registers
126  * for use only in hardware trigger mode. See the chip configuration information
127  * about the number of SC1n registers specific to this device. The SC1n registers
128  * have identical fields, and are used in a "ping-pong" approach to control ADC
129  * operation. At any one point in time, only one of the SC1n registers is actively
130  * controlling ADC conversions. Updating SC1A while SC1n is actively controlling
131  * a conversion is allowed, and vice-versa for any of the SC1n registers specific
132  * to this MCU. Writing SC1A while SC1A is actively controlling a conversion
133  * aborts the current conversion. In Software Trigger mode, when SC2[ADTRG]=0,
134  * writes to SC1A subsequently initiate a new conversion, if SC1[ADCH] contains a
135  * value other than all 1s (module disabled). Writing any of the SC1n registers while
136  * that specific SC1n register is actively controlling a conversion aborts the
137  * current conversion. None of the SC1B-SC1n registers are used for software
138  * trigger operation and therefore writes to the SC1B-SC1n registers do not initiate a
139  * new conversion.
140  */
141 /*!
142  * @name Constants and macros for entire ADC_SC1 register
143  */
144 /*@{*/
145 #define ADC_RD_SC1(base, index)  (ADC_SC1_REG(base, index))
146 #define ADC_WR_SC1(base, index, value) (ADC_SC1_REG(base, index) = (value))
147 #define ADC_RMW_SC1(base, index, mask, value) (ADC_WR_SC1(base, index, (ADC_RD_SC1(base, index) & ~(mask)) | (value)))
148 #define ADC_SET_SC1(base, index, value) (BME_OR32(&ADC_SC1_REG(base, index), (uint32_t)(value)))
149 #define ADC_CLR_SC1(base, index, value) (BME_AND32(&ADC_SC1_REG(base, index), (uint32_t)(~(value))))
150 #define ADC_TOG_SC1(base, index, value) (BME_XOR32(&ADC_SC1_REG(base, index), (uint32_t)(value)))
151 /*@}*/
152 
153 /*
154  * Constants & macros for individual ADC_SC1 bitfields
155  */
156 
157 /*!
158  * @name Register ADC_SC1, field ADCH[4:0] (RW)
159  *
160  * Selects one of the input channels. The input channel decode depends on the
161  * value of DIFF. DAD0-DAD3 are associated with the input pin pairs DADPx and
162  * DADMx. Some of the input channel options in the bitfield-setting descriptions might
163  * not be available for your device. For the actual ADC channel assignments for
164  * your device, see the Chip Configuration details. The successive approximation
165  * converter subsystem is turned off when the channel select bits are all set,
166  * that is, ADCH = 11111. This feature allows explicit disabling of the ADC and
167  * isolation of the input channel from all sources. Terminating continuous
168  * conversions this way prevents an additional single conversion from being performed. It
169  * is not necessary to set ADCH to all 1s to place the ADC in a low-power state
170  * when continuous conversions are not enabled because the module automatically
171  * enters a low-power state when a conversion completes.
172  *
173  * Values:
174  * - 0b00000 - When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is
175  *     selected as input.
176  * - 0b00001 - When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is
177  *     selected as input.
178  * - 0b00010 - When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is
179  *     selected as input.
180  * - 0b00011 - When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is
181  *     selected as input.
182  * - 0b00100 - When DIFF=0, AD4 is selected as input; when DIFF=1, it is
183  *     reserved.
184  * - 0b00101 - When DIFF=0, AD5 is selected as input; when DIFF=1, it is
185  *     reserved.
186  * - 0b00110 - When DIFF=0, AD6 is selected as input; when DIFF=1, it is
187  *     reserved.
188  * - 0b00111 - When DIFF=0, AD7 is selected as input; when DIFF=1, it is
189  *     reserved.
190  * - 0b01000 - When DIFF=0, AD8 is selected as input; when DIFF=1, it is
191  *     reserved.
192  * - 0b01001 - When DIFF=0, AD9 is selected as input; when DIFF=1, it is
193  *     reserved.
194  * - 0b01010 - When DIFF=0, AD10 is selected as input; when DIFF=1, it is
195  *     reserved.
196  * - 0b01011 - When DIFF=0, AD11 is selected as input; when DIFF=1, it is
197  *     reserved.
198  * - 0b01100 - When DIFF=0, AD12 is selected as input; when DIFF=1, it is
199  *     reserved.
200  * - 0b01101 - When DIFF=0, AD13 is selected as input; when DIFF=1, it is
201  *     reserved.
202  * - 0b01110 - When DIFF=0, AD14 is selected as input; when DIFF=1, it is
203  *     reserved.
204  * - 0b01111 - When DIFF=0, AD15 is selected as input; when DIFF=1, it is
205  *     reserved.
206  * - 0b10000 - When DIFF=0, AD16 is selected as input; when DIFF=1, it is
207  *     reserved.
208  * - 0b10001 - When DIFF=0, AD17 is selected as input; when DIFF=1, it is
209  *     reserved.
210  * - 0b10010 - When DIFF=0, AD18 is selected as input; when DIFF=1, it is
211  *     reserved.
212  * - 0b10011 - When DIFF=0, AD19 is selected as input; when DIFF=1, it is
213  *     reserved.
214  * - 0b10100 - When DIFF=0, AD20 is selected as input; when DIFF=1, it is
215  *     reserved.
216  * - 0b10101 - When DIFF=0, AD21 is selected as input; when DIFF=1, it is
217  *     reserved.
218  * - 0b10110 - When DIFF=0, AD22 is selected as input; when DIFF=1, it is
219  *     reserved.
220  * - 0b10111 - When DIFF=0, AD23 is selected as input; when DIFF=1, it is
221  *     reserved.
222  * - 0b11000 - Reserved.
223  * - 0b11001 - Reserved.
224  * - 0b11010 - When DIFF=0, Temp Sensor (single-ended) is selected as input;
225  *     when DIFF=1, Temp Sensor (differential) is selected as input.
226  * - 0b11011 - When DIFF=0, Bandgap (single-ended) is selected as input; when
227  *     DIFF=1, Bandgap (differential) is selected as input.
228  * - 0b11100 - Reserved.
229  * - 0b11101 - When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH
230  *     (differential) is selected as input. Voltage reference selected is determined
231  *     by SC2[REFSEL].
232  * - 0b11110 - When DIFF=0,VREFSL is selected as input; when DIFF=1, it is
233  *     reserved. Voltage reference selected is determined by SC2[REFSEL].
234  * - 0b11111 - Module is disabled.
235  */
236 /*@{*/
237 /*! @brief Read current value of the ADC_SC1_ADCH field. */
238 #define ADC_RD_SC1_ADCH(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_ADCH_MASK) >> ADC_SC1_ADCH_SHIFT)
239 #define ADC_BRD_SC1_ADCH(base, index) (BME_UBFX32(&ADC_SC1_REG(base, index), ADC_SC1_ADCH_SHIFT, ADC_SC1_ADCH_WIDTH))
240 
241 /*! @brief Set the ADCH field to a new value. */
242 #define ADC_WR_SC1_ADCH(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_ADCH_MASK, ADC_SC1_ADCH(value)))
243 #define ADC_BWR_SC1_ADCH(base, index, value) (BME_BFI32(&ADC_SC1_REG(base, index), ((uint32_t)(value) << ADC_SC1_ADCH_SHIFT), ADC_SC1_ADCH_SHIFT, ADC_SC1_ADCH_WIDTH))
244 /*@}*/
245 
246 /*!
247  * @name Register ADC_SC1, field DIFF[5] (RW)
248  *
249  * Configures the ADC to operate in differential mode. When enabled, this mode
250  * automatically selects from the differential channels, and changes the
251  * conversion algorithm and the number of cycles to complete a conversion.
252  *
253  * Values:
254  * - 0b0 - Single-ended conversions and input channels are selected.
255  * - 0b1 - Differential conversions and input channels are selected.
256  */
257 /*@{*/
258 /*! @brief Read current value of the ADC_SC1_DIFF field. */
259 #define ADC_RD_SC1_DIFF(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_DIFF_MASK) >> ADC_SC1_DIFF_SHIFT)
260 #define ADC_BRD_SC1_DIFF(base, index) (BME_UBFX32(&ADC_SC1_REG(base, index), ADC_SC1_DIFF_SHIFT, ADC_SC1_DIFF_WIDTH))
261 
262 /*! @brief Set the DIFF field to a new value. */
263 #define ADC_WR_SC1_DIFF(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_DIFF_MASK, ADC_SC1_DIFF(value)))
264 #define ADC_BWR_SC1_DIFF(base, index, value) (BME_BFI32(&ADC_SC1_REG(base, index), ((uint32_t)(value) << ADC_SC1_DIFF_SHIFT), ADC_SC1_DIFF_SHIFT, ADC_SC1_DIFF_WIDTH))
265 /*@}*/
266 
267 /*!
268  * @name Register ADC_SC1, field AIEN[6] (RW)
269  *
270  * Enables conversion complete interrupts. When COCO becomes set while the
271  * respective AIEN is high, an interrupt is asserted.
272  *
273  * Values:
274  * - 0b0 - Conversion complete interrupt is disabled.
275  * - 0b1 - Conversion complete interrupt is enabled.
276  */
277 /*@{*/
278 /*! @brief Read current value of the ADC_SC1_AIEN field. */
279 #define ADC_RD_SC1_AIEN(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_AIEN_MASK) >> ADC_SC1_AIEN_SHIFT)
280 #define ADC_BRD_SC1_AIEN(base, index) (BME_UBFX32(&ADC_SC1_REG(base, index), ADC_SC1_AIEN_SHIFT, ADC_SC1_AIEN_WIDTH))
281 
282 /*! @brief Set the AIEN field to a new value. */
283 #define ADC_WR_SC1_AIEN(base, index, value) (ADC_RMW_SC1(base, index, ADC_SC1_AIEN_MASK, ADC_SC1_AIEN(value)))
284 #define ADC_BWR_SC1_AIEN(base, index, value) (BME_BFI32(&ADC_SC1_REG(base, index), ((uint32_t)(value) << ADC_SC1_AIEN_SHIFT), ADC_SC1_AIEN_SHIFT, ADC_SC1_AIEN_WIDTH))
285 /*@}*/
286 
287 /*!
288  * @name Register ADC_SC1, field COCO[7] (RO)
289  *
290  * This is a read-only field that is set each time a conversion is completed
291  * when the compare function is disabled, or SC2[ACFE]=0 and the hardware average
292  * function is disabled, or SC3[AVGE]=0. When the compare function is enabled, or
293  * SC2[ACFE]=1, COCO is set upon completion of a conversion only if the compare
294  * result is true. When the hardware average function is enabled, or SC3[AVGE]=1,
295  * COCO is set upon completion of the selected number of conversions (determined
296  * by AVGS). COCO in SC1A is also set at the completion of a calibration sequence.
297  * COCO is cleared when the respective SC1n register is written or when the
298  * respective Rn register is read.
299  *
300  * Values:
301  * - 0b0 - Conversion is not completed.
302  * - 0b1 - Conversion is completed.
303  */
304 /*@{*/
305 /*! @brief Read current value of the ADC_SC1_COCO field. */
306 #define ADC_RD_SC1_COCO(base, index) ((ADC_SC1_REG(base, index) & ADC_SC1_COCO_MASK) >> ADC_SC1_COCO_SHIFT)
307 #define ADC_BRD_SC1_COCO(base, index) (BME_UBFX32(&ADC_SC1_REG(base, index), ADC_SC1_COCO_SHIFT, ADC_SC1_COCO_WIDTH))
308 /*@}*/
309 
310 /*******************************************************************************
311  * ADC_CFG1 - ADC Configuration Register 1
312  ******************************************************************************/
313 
314 /*!
315  * @brief ADC_CFG1 - ADC Configuration Register 1 (RW)
316  *
317  * Reset value: 0x00000000U
318  *
319  * The configuration Register 1 (CFG1) selects the mode of operation, clock
320  * source, clock divide, and configuration for low power or long sample time.
321  */
322 /*!
323  * @name Constants and macros for entire ADC_CFG1 register
324  */
325 /*@{*/
326 #define ADC_RD_CFG1(base)        (ADC_CFG1_REG(base))
327 #define ADC_WR_CFG1(base, value) (ADC_CFG1_REG(base) = (value))
328 #define ADC_RMW_CFG1(base, mask, value) (ADC_WR_CFG1(base, (ADC_RD_CFG1(base) & ~(mask)) | (value)))
329 #define ADC_SET_CFG1(base, value) (BME_OR32(&ADC_CFG1_REG(base), (uint32_t)(value)))
330 #define ADC_CLR_CFG1(base, value) (BME_AND32(&ADC_CFG1_REG(base), (uint32_t)(~(value))))
331 #define ADC_TOG_CFG1(base, value) (BME_XOR32(&ADC_CFG1_REG(base), (uint32_t)(value)))
332 /*@}*/
333 
334 /*
335  * Constants & macros for individual ADC_CFG1 bitfields
336  */
337 
338 /*!
339  * @name Register ADC_CFG1, field ADICLK[1:0] (RW)
340  *
341  * Selects the input clock source to generate the internal clock, ADCK. Note
342  * that when the ADACK clock source is selected, it is not required to be active
343  * prior to conversion start. When it is selected and it is not active prior to a
344  * conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at
345  * the start of a conversion and deactivated when conversions are terminated. In
346  * this case, there is an associated clock startup delay each time the clock
347  * source is re-activated.
348  *
349  * Values:
350  * - 0b00 - Bus clock
351  * - 0b01 - Bus clock divided by 2(BUSCLK/2)
352  * - 0b10 - Alternate clock (ALTCLK)
353  * - 0b11 - Asynchronous clock (ADACK)
354  */
355 /*@{*/
356 /*! @brief Read current value of the ADC_CFG1_ADICLK field. */
357 #define ADC_RD_CFG1_ADICLK(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADICLK_MASK) >> ADC_CFG1_ADICLK_SHIFT)
358 #define ADC_BRD_CFG1_ADICLK(base) (BME_UBFX32(&ADC_CFG1_REG(base), ADC_CFG1_ADICLK_SHIFT, ADC_CFG1_ADICLK_WIDTH))
359 
360 /*! @brief Set the ADICLK field to a new value. */
361 #define ADC_WR_CFG1_ADICLK(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADICLK_MASK, ADC_CFG1_ADICLK(value)))
362 #define ADC_BWR_CFG1_ADICLK(base, value) (BME_BFI32(&ADC_CFG1_REG(base), ((uint32_t)(value) << ADC_CFG1_ADICLK_SHIFT), ADC_CFG1_ADICLK_SHIFT, ADC_CFG1_ADICLK_WIDTH))
363 /*@}*/
364 
365 /*!
366  * @name Register ADC_CFG1, field MODE[3:2] (RW)
367  *
368  * Selects the ADC resolution mode.
369  *
370  * Values:
371  * - 0b00 - When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is
372  *     differential 9-bit conversion with 2's complement output.
373  * - 0b01 - When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it
374  *     is differential 13-bit conversion with 2's complement output.
375  * - 0b10 - When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it
376  *     is differential 11-bit conversion with 2's complement output
377  * - 0b11 - When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it
378  *     is differential 16-bit conversion with 2's complement output
379  */
380 /*@{*/
381 /*! @brief Read current value of the ADC_CFG1_MODE field. */
382 #define ADC_RD_CFG1_MODE(base) ((ADC_CFG1_REG(base) & ADC_CFG1_MODE_MASK) >> ADC_CFG1_MODE_SHIFT)
383 #define ADC_BRD_CFG1_MODE(base) (BME_UBFX32(&ADC_CFG1_REG(base), ADC_CFG1_MODE_SHIFT, ADC_CFG1_MODE_WIDTH))
384 
385 /*! @brief Set the MODE field to a new value. */
386 #define ADC_WR_CFG1_MODE(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_MODE_MASK, ADC_CFG1_MODE(value)))
387 #define ADC_BWR_CFG1_MODE(base, value) (BME_BFI32(&ADC_CFG1_REG(base), ((uint32_t)(value) << ADC_CFG1_MODE_SHIFT), ADC_CFG1_MODE_SHIFT, ADC_CFG1_MODE_WIDTH))
388 /*@}*/
389 
390 /*!
391  * @name Register ADC_CFG1, field ADLSMP[4] (RW)
392  *
393  * Selects between different sample times based on the conversion mode selected.
394  * This field adjusts the sample period to allow higher impedance inputs to be
395  * accurately sampled or to maximize conversion speed for lower impedance inputs.
396  * Longer sample times can also be used to lower overall power consumption if
397  * continuous conversions are enabled and high conversion rates are not required.
398  * When ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the
399  * extent of the long sample time.
400  *
401  * Values:
402  * - 0b0 - Short sample time.
403  * - 0b1 - Long sample time.
404  */
405 /*@{*/
406 /*! @brief Read current value of the ADC_CFG1_ADLSMP field. */
407 #define ADC_RD_CFG1_ADLSMP(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADLSMP_MASK) >> ADC_CFG1_ADLSMP_SHIFT)
408 #define ADC_BRD_CFG1_ADLSMP(base) (BME_UBFX32(&ADC_CFG1_REG(base), ADC_CFG1_ADLSMP_SHIFT, ADC_CFG1_ADLSMP_WIDTH))
409 
410 /*! @brief Set the ADLSMP field to a new value. */
411 #define ADC_WR_CFG1_ADLSMP(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADLSMP_MASK, ADC_CFG1_ADLSMP(value)))
412 #define ADC_BWR_CFG1_ADLSMP(base, value) (BME_BFI32(&ADC_CFG1_REG(base), ((uint32_t)(value) << ADC_CFG1_ADLSMP_SHIFT), ADC_CFG1_ADLSMP_SHIFT, ADC_CFG1_ADLSMP_WIDTH))
413 /*@}*/
414 
415 /*!
416  * @name Register ADC_CFG1, field ADIV[6:5] (RW)
417  *
418  * Selects the divide ratio used by the ADC to generate the internal clock ADCK.
419  *
420  * Values:
421  * - 0b00 - The divide ratio is 1 and the clock rate is input clock.
422  * - 0b01 - The divide ratio is 2 and the clock rate is (input clock)/2.
423  * - 0b10 - The divide ratio is 4 and the clock rate is (input clock)/4.
424  * - 0b11 - The divide ratio is 8 and the clock rate is (input clock)/8.
425  */
426 /*@{*/
427 /*! @brief Read current value of the ADC_CFG1_ADIV field. */
428 #define ADC_RD_CFG1_ADIV(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADIV_MASK) >> ADC_CFG1_ADIV_SHIFT)
429 #define ADC_BRD_CFG1_ADIV(base) (BME_UBFX32(&ADC_CFG1_REG(base), ADC_CFG1_ADIV_SHIFT, ADC_CFG1_ADIV_WIDTH))
430 
431 /*! @brief Set the ADIV field to a new value. */
432 #define ADC_WR_CFG1_ADIV(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADIV_MASK, ADC_CFG1_ADIV(value)))
433 #define ADC_BWR_CFG1_ADIV(base, value) (BME_BFI32(&ADC_CFG1_REG(base), ((uint32_t)(value) << ADC_CFG1_ADIV_SHIFT), ADC_CFG1_ADIV_SHIFT, ADC_CFG1_ADIV_WIDTH))
434 /*@}*/
435 
436 /*!
437  * @name Register ADC_CFG1, field ADLPC[7] (RW)
438  *
439  * Controls the power configuration of the successive approximation converter.
440  * This optimizes power consumption when higher sample rates are not required.
441  *
442  * Values:
443  * - 0b0 - Normal power configuration.
444  * - 0b1 - Low-power configuration. The power is reduced at the expense of
445  *     maximum clock speed.
446  */
447 /*@{*/
448 /*! @brief Read current value of the ADC_CFG1_ADLPC field. */
449 #define ADC_RD_CFG1_ADLPC(base) ((ADC_CFG1_REG(base) & ADC_CFG1_ADLPC_MASK) >> ADC_CFG1_ADLPC_SHIFT)
450 #define ADC_BRD_CFG1_ADLPC(base) (BME_UBFX32(&ADC_CFG1_REG(base), ADC_CFG1_ADLPC_SHIFT, ADC_CFG1_ADLPC_WIDTH))
451 
452 /*! @brief Set the ADLPC field to a new value. */
453 #define ADC_WR_CFG1_ADLPC(base, value) (ADC_RMW_CFG1(base, ADC_CFG1_ADLPC_MASK, ADC_CFG1_ADLPC(value)))
454 #define ADC_BWR_CFG1_ADLPC(base, value) (BME_BFI32(&ADC_CFG1_REG(base), ((uint32_t)(value) << ADC_CFG1_ADLPC_SHIFT), ADC_CFG1_ADLPC_SHIFT, ADC_CFG1_ADLPC_WIDTH))
455 /*@}*/
456 
457 /*******************************************************************************
458  * ADC_CFG2 - ADC Configuration Register 2
459  ******************************************************************************/
460 
461 /*!
462  * @brief ADC_CFG2 - ADC Configuration Register 2 (RW)
463  *
464  * Reset value: 0x00000000U
465  *
466  * Configuration Register 2 (CFG2) selects the special high-speed configuration
467  * for very high speed conversions and selects the long sample time duration
468  * during long sample mode.
469  */
470 /*!
471  * @name Constants and macros for entire ADC_CFG2 register
472  */
473 /*@{*/
474 #define ADC_RD_CFG2(base)        (ADC_CFG2_REG(base))
475 #define ADC_WR_CFG2(base, value) (ADC_CFG2_REG(base) = (value))
476 #define ADC_RMW_CFG2(base, mask, value) (ADC_WR_CFG2(base, (ADC_RD_CFG2(base) & ~(mask)) | (value)))
477 #define ADC_SET_CFG2(base, value) (BME_OR32(&ADC_CFG2_REG(base), (uint32_t)(value)))
478 #define ADC_CLR_CFG2(base, value) (BME_AND32(&ADC_CFG2_REG(base), (uint32_t)(~(value))))
479 #define ADC_TOG_CFG2(base, value) (BME_XOR32(&ADC_CFG2_REG(base), (uint32_t)(value)))
480 /*@}*/
481 
482 /*
483  * Constants & macros for individual ADC_CFG2 bitfields
484  */
485 
486 /*!
487  * @name Register ADC_CFG2, field ADLSTS[1:0] (RW)
488  *
489  * Selects between the extended sample times when long sample time is selected,
490  * that is, when CFG1[ADLSMP]=1. This allows higher impedance inputs to be
491  * accurately sampled or to maximize conversion speed for lower impedance inputs.
492  * Longer sample times can also be used to lower overall power consumption when
493  * continuous conversions are enabled if high conversion rates are not required.
494  *
495  * Values:
496  * - 0b00 - Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles
497  *     total.
498  * - 0b01 - 12 extra ADCK cycles; 16 ADCK cycles total sample time.
499  * - 0b10 - 6 extra ADCK cycles; 10 ADCK cycles total sample time.
500  * - 0b11 - 2 extra ADCK cycles; 6 ADCK cycles total sample time.
501  */
502 /*@{*/
503 /*! @brief Read current value of the ADC_CFG2_ADLSTS field. */
504 #define ADC_RD_CFG2_ADLSTS(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADLSTS_MASK) >> ADC_CFG2_ADLSTS_SHIFT)
505 #define ADC_BRD_CFG2_ADLSTS(base) (BME_UBFX32(&ADC_CFG2_REG(base), ADC_CFG2_ADLSTS_SHIFT, ADC_CFG2_ADLSTS_WIDTH))
506 
507 /*! @brief Set the ADLSTS field to a new value. */
508 #define ADC_WR_CFG2_ADLSTS(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADLSTS_MASK, ADC_CFG2_ADLSTS(value)))
509 #define ADC_BWR_CFG2_ADLSTS(base, value) (BME_BFI32(&ADC_CFG2_REG(base), ((uint32_t)(value) << ADC_CFG2_ADLSTS_SHIFT), ADC_CFG2_ADLSTS_SHIFT, ADC_CFG2_ADLSTS_WIDTH))
510 /*@}*/
511 
512 /*!
513  * @name Register ADC_CFG2, field ADHSC[2] (RW)
514  *
515  * Configures the ADC for very high-speed operation. The conversion sequence is
516  * altered with 2 ADCK cycles added to the conversion time to allow higher speed
517  * conversion clocks.
518  *
519  * Values:
520  * - 0b0 - Normal conversion sequence selected.
521  * - 0b1 - High-speed conversion sequence selected with 2 additional ADCK cycles
522  *     to total conversion time.
523  */
524 /*@{*/
525 /*! @brief Read current value of the ADC_CFG2_ADHSC field. */
526 #define ADC_RD_CFG2_ADHSC(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADHSC_MASK) >> ADC_CFG2_ADHSC_SHIFT)
527 #define ADC_BRD_CFG2_ADHSC(base) (BME_UBFX32(&ADC_CFG2_REG(base), ADC_CFG2_ADHSC_SHIFT, ADC_CFG2_ADHSC_WIDTH))
528 
529 /*! @brief Set the ADHSC field to a new value. */
530 #define ADC_WR_CFG2_ADHSC(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADHSC_MASK, ADC_CFG2_ADHSC(value)))
531 #define ADC_BWR_CFG2_ADHSC(base, value) (BME_BFI32(&ADC_CFG2_REG(base), ((uint32_t)(value) << ADC_CFG2_ADHSC_SHIFT), ADC_CFG2_ADHSC_SHIFT, ADC_CFG2_ADHSC_WIDTH))
532 /*@}*/
533 
534 /*!
535  * @name Register ADC_CFG2, field ADACKEN[3] (RW)
536  *
537  * Enables the asynchronous clock source and the clock source output regardless
538  * of the conversion and status of CFG1[ADICLK]. Based on MCU configuration, the
539  * asynchronous clock may be used by other modules. See chip configuration
540  * information. Setting this field allows the clock to be used even while the ADC is
541  * idle or operating from a different clock source. Also, latency of initiating a
542  * single or first-continuous conversion with the asynchronous clock selected is
543  * reduced because the ADACK clock is already operational.
544  *
545  * Values:
546  * - 0b0 - Asynchronous clock output disabled; Asynchronous clock is enabled
547  *     only if selected by ADICLK and a conversion is active.
548  * - 0b1 - Asynchronous clock and clock output is enabled regardless of the
549  *     state of the ADC.
550  */
551 /*@{*/
552 /*! @brief Read current value of the ADC_CFG2_ADACKEN field. */
553 #define ADC_RD_CFG2_ADACKEN(base) ((ADC_CFG2_REG(base) & ADC_CFG2_ADACKEN_MASK) >> ADC_CFG2_ADACKEN_SHIFT)
554 #define ADC_BRD_CFG2_ADACKEN(base) (BME_UBFX32(&ADC_CFG2_REG(base), ADC_CFG2_ADACKEN_SHIFT, ADC_CFG2_ADACKEN_WIDTH))
555 
556 /*! @brief Set the ADACKEN field to a new value. */
557 #define ADC_WR_CFG2_ADACKEN(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_ADACKEN_MASK, ADC_CFG2_ADACKEN(value)))
558 #define ADC_BWR_CFG2_ADACKEN(base, value) (BME_BFI32(&ADC_CFG2_REG(base), ((uint32_t)(value) << ADC_CFG2_ADACKEN_SHIFT), ADC_CFG2_ADACKEN_SHIFT, ADC_CFG2_ADACKEN_WIDTH))
559 /*@}*/
560 
561 /*!
562  * @name Register ADC_CFG2, field MUXSEL[4] (RW)
563  *
564  * Changes the ADC mux setting to select between alternate sets of ADC channels.
565  *
566  * Values:
567  * - 0b0 - ADxxa channels are selected.
568  * - 0b1 - ADxxb channels are selected.
569  */
570 /*@{*/
571 /*! @brief Read current value of the ADC_CFG2_MUXSEL field. */
572 #define ADC_RD_CFG2_MUXSEL(base) ((ADC_CFG2_REG(base) & ADC_CFG2_MUXSEL_MASK) >> ADC_CFG2_MUXSEL_SHIFT)
573 #define ADC_BRD_CFG2_MUXSEL(base) (BME_UBFX32(&ADC_CFG2_REG(base), ADC_CFG2_MUXSEL_SHIFT, ADC_CFG2_MUXSEL_WIDTH))
574 
575 /*! @brief Set the MUXSEL field to a new value. */
576 #define ADC_WR_CFG2_MUXSEL(base, value) (ADC_RMW_CFG2(base, ADC_CFG2_MUXSEL_MASK, ADC_CFG2_MUXSEL(value)))
577 #define ADC_BWR_CFG2_MUXSEL(base, value) (BME_BFI32(&ADC_CFG2_REG(base), ((uint32_t)(value) << ADC_CFG2_MUXSEL_SHIFT), ADC_CFG2_MUXSEL_SHIFT, ADC_CFG2_MUXSEL_WIDTH))
578 /*@}*/
579 
580 /*******************************************************************************
581  * ADC_R - ADC Data Result Register
582  ******************************************************************************/
583 
584 /*!
585  * @brief ADC_R - ADC Data Result Register (RO)
586  *
587  * Reset value: 0x00000000U
588  *
589  * The data result registers (Rn) contain the result of an ADC conversion of the
590  * channel selected by the corresponding status and channel control register
591  * (SC1A:SC1n). For every status and channel control register, there is a
592  * corresponding data result register. Final result value stored in the data result
593  * register (R) will include the conversion result whose raw result is affected by a
594  * shift value that varies on mode configurations (see the table below), the OFS
595  * offset value, CLP/CLPM calibration values, and a factor of 1/32 (0x0800) that
596  * gets added upon certain conditions. Final conversion equation result is: Conv.
597  * Result = Raw conv. result (RCR) + shift - OFS - sum(CLPx) + sum(CLMx) - 0x0800 +
598  * CLPD RCR = Plus-side conversion - Minus-side conversion In equation above,
599  * the sum of CLPx does not include CLPD value and CLMD never has any affect on
600  * final conversion result. The factor of 0x0800 only gets subtracted only if plus
601  * compare output is a logic 1 after completion of minus-side conversion and prior
602  * to start of plus-side conversion. Shift values Mode Shift value 00 0x0040 01
603  * 0x0004 10 0x0010 11 0x0000 Unused bits in R n are cleared in unsigned
604  * right-aligned modes and carry the sign bit (MSB) in sign-extended 2's complement
605  * modes. For example, when configured for 10-bit single-ended mode, D[15:10] are
606  * cleared. When configured for 11-bit differential mode, D[15:10] carry the sign
607  * bit, that is, bit 10 extended through bit 15. The following table describes the
608  * behavior of the data result registers in the different modes of operation. Data
609  * result register description Conversion mode D15 D14 D13 D12 D11 D10 D9 D8 D7
610  * D6 D5 D4 D3 D2 D1 D0 Format 16-bit differential S D D D D D D D D D D D D D D
611  * D Signed 2's complement 16-bit single-ended D D D D D D D D D D D D D D D D
612  * Unsigned right justified 13-bit differential S S S S D D D D D D D D D D D D
613  * Sign-extended 2's complement 12-bit single-ended 0 0 0 0 D D D D D D D D D D D D
614  * Unsigned right-justified 11-bit differential S S S S S S D D D D D D D D D D
615  * Sign-extended 2's complement 10-bit single-ended 0 0 0 0 0 0 D D D D D D D D D
616  * D Unsigned right-justified 9-bit differential S S S S S S S S D D D D D D D D
617  * Sign-extended 2's complement 8-bit single-ended 0 0 0 0 0 0 0 0 D D D D D D D
618  * D Unsigned right-justified S: Sign bit or sign bit extension; D: Data, which
619  * is 2's complement data if indicated
620  */
621 /*!
622  * @name Constants and macros for entire ADC_R register
623  */
624 /*@{*/
625 #define ADC_RD_R(base, index)    (ADC_R_REG(base, index))
626 /*@}*/
627 
628 /*
629  * Constants & macros for individual ADC_R bitfields
630  */
631 
632 /*!
633  * @name Register ADC_R, field D[15:0] (RO)
634  */
635 /*@{*/
636 /*! @brief Read current value of the ADC_R_D field. */
637 #define ADC_RD_R_D(base, index) ((ADC_R_REG(base, index) & ADC_R_D_MASK) >> ADC_R_D_SHIFT)
638 #define ADC_BRD_R_D(base, index) (BME_UBFX32(&ADC_R_REG(base, index), ADC_R_D_SHIFT, ADC_R_D_WIDTH))
639 /*@}*/
640 
641 /*******************************************************************************
642  * ADC_CV1 - Compare Value Registers
643  ******************************************************************************/
644 
645 /*!
646  * @brief ADC_CV1 - Compare Value Registers (RW)
647  *
648  * Reset value: 0x00000000U
649  *
650  * The Compare Value Registers (CV1 and CV2) contain a compare value used to
651  * compare the conversion result when the compare function is enabled, that is,
652  * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
653  * different modes of operation for both bit position definition and value format
654  * using unsigned or sign-extended 2's complement. Therefore, the compare function
655  * uses only the CVn fields that are related to the ADC mode of operation. The
656  * compare value 2 register (CV2) is used only when the compare range function is
657  * enabled, that is, SC2[ACREN]=1.
658  */
659 /*!
660  * @name Constants and macros for entire ADC_CV1 register
661  */
662 /*@{*/
663 #define ADC_RD_CV1(base)         (ADC_CV1_REG(base))
664 #define ADC_WR_CV1(base, value)  (ADC_CV1_REG(base) = (value))
665 #define ADC_RMW_CV1(base, mask, value) (ADC_WR_CV1(base, (ADC_RD_CV1(base) & ~(mask)) | (value)))
666 #define ADC_SET_CV1(base, value) (BME_OR32(&ADC_CV1_REG(base), (uint32_t)(value)))
667 #define ADC_CLR_CV1(base, value) (BME_AND32(&ADC_CV1_REG(base), (uint32_t)(~(value))))
668 #define ADC_TOG_CV1(base, value) (BME_XOR32(&ADC_CV1_REG(base), (uint32_t)(value)))
669 /*@}*/
670 
671 /*
672  * Constants & macros for individual ADC_CV1 bitfields
673  */
674 
675 /*!
676  * @name Register ADC_CV1, field CV[15:0] (RW)
677  */
678 /*@{*/
679 /*! @brief Read current value of the ADC_CV1_CV field. */
680 #define ADC_RD_CV1_CV(base)  ((ADC_CV1_REG(base) & ADC_CV1_CV_MASK) >> ADC_CV1_CV_SHIFT)
681 #define ADC_BRD_CV1_CV(base) (BME_UBFX32(&ADC_CV1_REG(base), ADC_CV1_CV_SHIFT, ADC_CV1_CV_WIDTH))
682 
683 /*! @brief Set the CV field to a new value. */
684 #define ADC_WR_CV1_CV(base, value) (ADC_RMW_CV1(base, ADC_CV1_CV_MASK, ADC_CV1_CV(value)))
685 #define ADC_BWR_CV1_CV(base, value) (BME_BFI32(&ADC_CV1_REG(base), ((uint32_t)(value) << ADC_CV1_CV_SHIFT), ADC_CV1_CV_SHIFT, ADC_CV1_CV_WIDTH))
686 /*@}*/
687 
688 /*******************************************************************************
689  * ADC_CV2 - Compare Value Registers
690  ******************************************************************************/
691 
692 /*!
693  * @brief ADC_CV2 - Compare Value Registers (RW)
694  *
695  * Reset value: 0x00000000U
696  *
697  * The Compare Value Registers (CV1 and CV2) contain a compare value used to
698  * compare the conversion result when the compare function is enabled, that is,
699  * SC2[ACFE]=1. This register is formatted in the same way as the Rn registers in
700  * different modes of operation for both bit position definition and value format
701  * using unsigned or sign-extended 2's complement. Therefore, the compare function
702  * uses only the CVn fields that are related to the ADC mode of operation. The
703  * compare value 2 register (CV2) is used only when the compare range function is
704  * enabled, that is, SC2[ACREN]=1.
705  */
706 /*!
707  * @name Constants and macros for entire ADC_CV2 register
708  */
709 /*@{*/
710 #define ADC_RD_CV2(base)         (ADC_CV2_REG(base))
711 #define ADC_WR_CV2(base, value)  (ADC_CV2_REG(base) = (value))
712 #define ADC_RMW_CV2(base, mask, value) (ADC_WR_CV2(base, (ADC_RD_CV2(base) & ~(mask)) | (value)))
713 #define ADC_SET_CV2(base, value) (BME_OR32(&ADC_CV2_REG(base), (uint32_t)(value)))
714 #define ADC_CLR_CV2(base, value) (BME_AND32(&ADC_CV2_REG(base), (uint32_t)(~(value))))
715 #define ADC_TOG_CV2(base, value) (BME_XOR32(&ADC_CV2_REG(base), (uint32_t)(value)))
716 /*@}*/
717 
718 /*
719  * Constants & macros for individual ADC_CV2 bitfields
720  */
721 
722 /*!
723  * @name Register ADC_CV2, field CV[15:0] (RW)
724  */
725 /*@{*/
726 /*! @brief Read current value of the ADC_CV2_CV field. */
727 #define ADC_RD_CV2_CV(base)  ((ADC_CV2_REG(base) & ADC_CV2_CV_MASK) >> ADC_CV2_CV_SHIFT)
728 #define ADC_BRD_CV2_CV(base) (BME_UBFX32(&ADC_CV2_REG(base), ADC_CV2_CV_SHIFT, ADC_CV2_CV_WIDTH))
729 
730 /*! @brief Set the CV field to a new value. */
731 #define ADC_WR_CV2_CV(base, value) (ADC_RMW_CV2(base, ADC_CV2_CV_MASK, ADC_CV2_CV(value)))
732 #define ADC_BWR_CV2_CV(base, value) (BME_BFI32(&ADC_CV2_REG(base), ((uint32_t)(value) << ADC_CV2_CV_SHIFT), ADC_CV2_CV_SHIFT, ADC_CV2_CV_WIDTH))
733 /*@}*/
734 
735 /*******************************************************************************
736  * ADC_SC2 - Status and Control Register 2
737  ******************************************************************************/
738 
739 /*!
740  * @brief ADC_SC2 - Status and Control Register 2 (RW)
741  *
742  * Reset value: 0x00000000U
743  *
744  * The status and control register 2 (SC2) contains the conversion active,
745  * hardware/software trigger select, compare function, and voltage reference select of
746  * the ADC module.
747  */
748 /*!
749  * @name Constants and macros for entire ADC_SC2 register
750  */
751 /*@{*/
752 #define ADC_RD_SC2(base)         (ADC_SC2_REG(base))
753 #define ADC_WR_SC2(base, value)  (ADC_SC2_REG(base) = (value))
754 #define ADC_RMW_SC2(base, mask, value) (ADC_WR_SC2(base, (ADC_RD_SC2(base) & ~(mask)) | (value)))
755 #define ADC_SET_SC2(base, value) (BME_OR32(&ADC_SC2_REG(base), (uint32_t)(value)))
756 #define ADC_CLR_SC2(base, value) (BME_AND32(&ADC_SC2_REG(base), (uint32_t)(~(value))))
757 #define ADC_TOG_SC2(base, value) (BME_XOR32(&ADC_SC2_REG(base), (uint32_t)(value)))
758 /*@}*/
759 
760 /*
761  * Constants & macros for individual ADC_SC2 bitfields
762  */
763 
764 /*!
765  * @name Register ADC_SC2, field REFSEL[1:0] (RW)
766  *
767  * Selects the voltage reference source used for conversions.
768  *
769  * Values:
770  * - 0b00 - Default voltage reference pin pair, that is, external pins VREFH and
771  *     VREFL
772  * - 0b01 - Alternate reference pair, that is, VALTH and VALTL . This pair may
773  *     be additional external pins or internal sources depending on the MCU
774  *     configuration. See the chip configuration information for details specific to
775  *     this MCU
776  * - 0b10 - Reserved
777  * - 0b11 - Reserved - Selects default voltage reference (V REFH and V REFL )
778  *     pin pair.
779  */
780 /*@{*/
781 /*! @brief Read current value of the ADC_SC2_REFSEL field. */
782 #define ADC_RD_SC2_REFSEL(base) ((ADC_SC2_REG(base) & ADC_SC2_REFSEL_MASK) >> ADC_SC2_REFSEL_SHIFT)
783 #define ADC_BRD_SC2_REFSEL(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_REFSEL_SHIFT, ADC_SC2_REFSEL_WIDTH))
784 
785 /*! @brief Set the REFSEL field to a new value. */
786 #define ADC_WR_SC2_REFSEL(base, value) (ADC_RMW_SC2(base, ADC_SC2_REFSEL_MASK, ADC_SC2_REFSEL(value)))
787 #define ADC_BWR_SC2_REFSEL(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2_REFSEL_SHIFT), ADC_SC2_REFSEL_SHIFT, ADC_SC2_REFSEL_WIDTH))
788 /*@}*/
789 
790 /*!
791  * @name Register ADC_SC2, field DMAEN[2] (RW)
792  *
793  * Values:
794  * - 0b0 - DMA is disabled.
795  * - 0b1 - DMA is enabled and will assert the ADC DMA request during an ADC
796  *     conversion complete event noted when any of the SC1n[COCO] flags is asserted.
797  */
798 /*@{*/
799 /*! @brief Read current value of the ADC_SC2_DMAEN field. */
800 #define ADC_RD_SC2_DMAEN(base) ((ADC_SC2_REG(base) & ADC_SC2_DMAEN_MASK) >> ADC_SC2_DMAEN_SHIFT)
801 #define ADC_BRD_SC2_DMAEN(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_DMAEN_SHIFT, ADC_SC2_DMAEN_WIDTH))
802 
803 /*! @brief Set the DMAEN field to a new value. */
804 #define ADC_WR_SC2_DMAEN(base, value) (ADC_RMW_SC2(base, ADC_SC2_DMAEN_MASK, ADC_SC2_DMAEN(value)))
805 #define ADC_BWR_SC2_DMAEN(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2_DMAEN_SHIFT), ADC_SC2_DMAEN_SHIFT, ADC_SC2_DMAEN_WIDTH))
806 /*@}*/
807 
808 /*!
809  * @name Register ADC_SC2, field ACREN[3] (RW)
810  *
811  * Configures the compare function to check if the conversion result of the
812  * input being monitored is either between or outside the range formed by CV1 and CV2
813  * determined by the value of ACFGT. ACFE must be set for ACFGT to have any
814  * effect.
815  *
816  * Values:
817  * - 0b0 - Range function disabled. Only CV1 is compared.
818  * - 0b1 - Range function enabled. Both CV1 and CV2 are compared.
819  */
820 /*@{*/
821 /*! @brief Read current value of the ADC_SC2_ACREN field. */
822 #define ADC_RD_SC2_ACREN(base) ((ADC_SC2_REG(base) & ADC_SC2_ACREN_MASK) >> ADC_SC2_ACREN_SHIFT)
823 #define ADC_BRD_SC2_ACREN(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_ACREN_SHIFT, ADC_SC2_ACREN_WIDTH))
824 
825 /*! @brief Set the ACREN field to a new value. */
826 #define ADC_WR_SC2_ACREN(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACREN_MASK, ADC_SC2_ACREN(value)))
827 #define ADC_BWR_SC2_ACREN(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2_ACREN_SHIFT), ADC_SC2_ACREN_SHIFT, ADC_SC2_ACREN_WIDTH))
828 /*@}*/
829 
830 /*!
831  * @name Register ADC_SC2, field ACFGT[4] (RW)
832  *
833  * Configures the compare function to check the conversion result relative to
834  * the CV1 and CV2 based upon the value of ACREN. ACFE must be set for ACFGT to
835  * have any effect.
836  *
837  * Values:
838  * - 0b0 - Configures less than threshold, outside range not inclusive and
839  *     inside range not inclusive; functionality based on the values placed in CV1 and
840  *     CV2.
841  * - 0b1 - Configures greater than or equal to threshold, outside and inside
842  *     ranges inclusive; functionality based on the values placed in CV1 and CV2.
843  */
844 /*@{*/
845 /*! @brief Read current value of the ADC_SC2_ACFGT field. */
846 #define ADC_RD_SC2_ACFGT(base) ((ADC_SC2_REG(base) & ADC_SC2_ACFGT_MASK) >> ADC_SC2_ACFGT_SHIFT)
847 #define ADC_BRD_SC2_ACFGT(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_ACFGT_SHIFT, ADC_SC2_ACFGT_WIDTH))
848 
849 /*! @brief Set the ACFGT field to a new value. */
850 #define ADC_WR_SC2_ACFGT(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACFGT_MASK, ADC_SC2_ACFGT(value)))
851 #define ADC_BWR_SC2_ACFGT(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2_ACFGT_SHIFT), ADC_SC2_ACFGT_SHIFT, ADC_SC2_ACFGT_WIDTH))
852 /*@}*/
853 
854 /*!
855  * @name Register ADC_SC2, field ACFE[5] (RW)
856  *
857  * Enables the compare function.
858  *
859  * Values:
860  * - 0b0 - Compare function disabled.
861  * - 0b1 - Compare function enabled.
862  */
863 /*@{*/
864 /*! @brief Read current value of the ADC_SC2_ACFE field. */
865 #define ADC_RD_SC2_ACFE(base) ((ADC_SC2_REG(base) & ADC_SC2_ACFE_MASK) >> ADC_SC2_ACFE_SHIFT)
866 #define ADC_BRD_SC2_ACFE(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_ACFE_SHIFT, ADC_SC2_ACFE_WIDTH))
867 
868 /*! @brief Set the ACFE field to a new value. */
869 #define ADC_WR_SC2_ACFE(base, value) (ADC_RMW_SC2(base, ADC_SC2_ACFE_MASK, ADC_SC2_ACFE(value)))
870 #define ADC_BWR_SC2_ACFE(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2_ACFE_SHIFT), ADC_SC2_ACFE_SHIFT, ADC_SC2_ACFE_WIDTH))
871 /*@}*/
872 
873 /*!
874  * @name Register ADC_SC2, field ADTRG[6] (RW)
875  *
876  * Selects the type of trigger used for initiating a conversion. Two types of
877  * trigger are selectable: Software trigger: When software trigger is selected, a
878  * conversion is initiated following a write to SC1A. Hardware trigger: When
879  * hardware trigger is selected, a conversion is initiated following the assertion of
880  * the ADHWT input after a pulse of the ADHWTSn input.
881  *
882  * Values:
883  * - 0b0 - Software trigger selected.
884  * - 0b1 - Hardware trigger selected.
885  */
886 /*@{*/
887 /*! @brief Read current value of the ADC_SC2_ADTRG field. */
888 #define ADC_RD_SC2_ADTRG(base) ((ADC_SC2_REG(base) & ADC_SC2_ADTRG_MASK) >> ADC_SC2_ADTRG_SHIFT)
889 #define ADC_BRD_SC2_ADTRG(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_ADTRG_SHIFT, ADC_SC2_ADTRG_WIDTH))
890 
891 /*! @brief Set the ADTRG field to a new value. */
892 #define ADC_WR_SC2_ADTRG(base, value) (ADC_RMW_SC2(base, ADC_SC2_ADTRG_MASK, ADC_SC2_ADTRG(value)))
893 #define ADC_BWR_SC2_ADTRG(base, value) (BME_BFI32(&ADC_SC2_REG(base), ((uint32_t)(value) << ADC_SC2_ADTRG_SHIFT), ADC_SC2_ADTRG_SHIFT, ADC_SC2_ADTRG_WIDTH))
894 /*@}*/
895 
896 /*!
897  * @name Register ADC_SC2, field ADACT[7] (RO)
898  *
899  * Indicates that a conversion or hardware averaging is in progress. ADACT is
900  * set when a conversion is initiated and cleared when a conversion is completed or
901  * aborted.
902  *
903  * Values:
904  * - 0b0 - Conversion not in progress.
905  * - 0b1 - Conversion in progress.
906  */
907 /*@{*/
908 /*! @brief Read current value of the ADC_SC2_ADACT field. */
909 #define ADC_RD_SC2_ADACT(base) ((ADC_SC2_REG(base) & ADC_SC2_ADACT_MASK) >> ADC_SC2_ADACT_SHIFT)
910 #define ADC_BRD_SC2_ADACT(base) (BME_UBFX32(&ADC_SC2_REG(base), ADC_SC2_ADACT_SHIFT, ADC_SC2_ADACT_WIDTH))
911 /*@}*/
912 
913 /*******************************************************************************
914  * ADC_SC3 - Status and Control Register 3
915  ******************************************************************************/
916 
917 /*!
918  * @brief ADC_SC3 - Status and Control Register 3 (RW)
919  *
920  * Reset value: 0x00000000U
921  *
922  * The Status and Control Register 3 (SC3) controls the calibration, continuous
923  * convert, and hardware averaging functions of the ADC module.
924  */
925 /*!
926  * @name Constants and macros for entire ADC_SC3 register
927  */
928 /*@{*/
929 #define ADC_RD_SC3(base)         (ADC_SC3_REG(base))
930 #define ADC_WR_SC3(base, value)  (ADC_SC3_REG(base) = (value))
931 #define ADC_RMW_SC3(base, mask, value) (ADC_WR_SC3(base, (ADC_RD_SC3(base) & ~(mask)) | (value)))
932 #define ADC_SET_SC3(base, value) (BME_OR32(&ADC_SC3_REG(base), (uint32_t)(value)))
933 #define ADC_CLR_SC3(base, value) (BME_AND32(&ADC_SC3_REG(base), (uint32_t)(~(value))))
934 #define ADC_TOG_SC3(base, value) (BME_XOR32(&ADC_SC3_REG(base), (uint32_t)(value)))
935 /*@}*/
936 
937 /*
938  * Constants & macros for individual ADC_SC3 bitfields
939  */
940 
941 /*!
942  * @name Register ADC_SC3, field AVGS[1:0] (RW)
943  *
944  * Determines how many ADC conversions will be averaged to create the ADC
945  * average result.
946  *
947  * Values:
948  * - 0b00 - 4 samples averaged.
949  * - 0b01 - 8 samples averaged.
950  * - 0b10 - 16 samples averaged.
951  * - 0b11 - 32 samples averaged.
952  */
953 /*@{*/
954 /*! @brief Read current value of the ADC_SC3_AVGS field. */
955 #define ADC_RD_SC3_AVGS(base) ((ADC_SC3_REG(base) & ADC_SC3_AVGS_MASK) >> ADC_SC3_AVGS_SHIFT)
956 #define ADC_BRD_SC3_AVGS(base) (BME_UBFX32(&ADC_SC3_REG(base), ADC_SC3_AVGS_SHIFT, ADC_SC3_AVGS_WIDTH))
957 
958 /*! @brief Set the AVGS field to a new value. */
959 #define ADC_WR_SC3_AVGS(base, value) (ADC_RMW_SC3(base, (ADC_SC3_AVGS_MASK | ADC_SC3_CALF_MASK), ADC_SC3_AVGS(value)))
960 #define ADC_BWR_SC3_AVGS(base, value) (BME_BFI32(&ADC_SC3_REG(base), ((uint32_t)(value) << ADC_SC3_AVGS_SHIFT), ADC_SC3_AVGS_SHIFT, ADC_SC3_AVGS_WIDTH))
961 /*@}*/
962 
963 /*!
964  * @name Register ADC_SC3, field AVGE[2] (RW)
965  *
966  * Enables the hardware average function of the ADC.
967  *
968  * Values:
969  * - 0b0 - Hardware average function disabled.
970  * - 0b1 - Hardware average function enabled.
971  */
972 /*@{*/
973 /*! @brief Read current value of the ADC_SC3_AVGE field. */
974 #define ADC_RD_SC3_AVGE(base) ((ADC_SC3_REG(base) & ADC_SC3_AVGE_MASK) >> ADC_SC3_AVGE_SHIFT)
975 #define ADC_BRD_SC3_AVGE(base) (BME_UBFX32(&ADC_SC3_REG(base), ADC_SC3_AVGE_SHIFT, ADC_SC3_AVGE_WIDTH))
976 
977 /*! @brief Set the AVGE field to a new value. */
978 #define ADC_WR_SC3_AVGE(base, value) (ADC_RMW_SC3(base, (ADC_SC3_AVGE_MASK | ADC_SC3_CALF_MASK), ADC_SC3_AVGE(value)))
979 #define ADC_BWR_SC3_AVGE(base, value) (BME_BFI32(&ADC_SC3_REG(base), ((uint32_t)(value) << ADC_SC3_AVGE_SHIFT), ADC_SC3_AVGE_SHIFT, ADC_SC3_AVGE_WIDTH))
980 /*@}*/
981 
982 /*!
983  * @name Register ADC_SC3, field ADCO[3] (RW)
984  *
985  * Enables continuous conversions.
986  *
987  * Values:
988  * - 0b0 - One conversion or one set of conversions if the hardware average
989  *     function is enabled, that is, AVGE=1, after initiating a conversion.
990  * - 0b1 - Continuous conversions or sets of conversions if the hardware average
991  *     function is enabled, that is, AVGE=1, after initiating a conversion.
992  */
993 /*@{*/
994 /*! @brief Read current value of the ADC_SC3_ADCO field. */
995 #define ADC_RD_SC3_ADCO(base) ((ADC_SC3_REG(base) & ADC_SC3_ADCO_MASK) >> ADC_SC3_ADCO_SHIFT)
996 #define ADC_BRD_SC3_ADCO(base) (BME_UBFX32(&ADC_SC3_REG(base), ADC_SC3_ADCO_SHIFT, ADC_SC3_ADCO_WIDTH))
997 
998 /*! @brief Set the ADCO field to a new value. */
999 #define ADC_WR_SC3_ADCO(base, value) (ADC_RMW_SC3(base, (ADC_SC3_ADCO_MASK | ADC_SC3_CALF_MASK), ADC_SC3_ADCO(value)))
1000 #define ADC_BWR_SC3_ADCO(base, value) (BME_BFI32(&ADC_SC3_REG(base), ((uint32_t)(value) << ADC_SC3_ADCO_SHIFT), ADC_SC3_ADCO_SHIFT, ADC_SC3_ADCO_WIDTH))
1001 /*@}*/
1002 
1003 /*!
1004  * @name Register ADC_SC3, field CALF[6] (W1C)
1005  *
1006  * Displays the result of the calibration sequence. The calibration sequence
1007  * will fail if SC2[ADTRG] = 1, any ADC register is written, or any stop mode is
1008  * entered before the calibration sequence completes. Writing 1 to CALF clears it.
1009  *
1010  * Values:
1011  * - 0b0 - Calibration completed normally.
1012  * - 0b1 - Calibration failed. ADC accuracy specifications are not guaranteed.
1013  */
1014 /*@{*/
1015 /*! @brief Read current value of the ADC_SC3_CALF field. */
1016 #define ADC_RD_SC3_CALF(base) ((ADC_SC3_REG(base) & ADC_SC3_CALF_MASK) >> ADC_SC3_CALF_SHIFT)
1017 #define ADC_BRD_SC3_CALF(base) (BME_UBFX32(&ADC_SC3_REG(base), ADC_SC3_CALF_SHIFT, ADC_SC3_CALF_WIDTH))
1018 
1019 /*! @brief Set the CALF field to a new value. */
1020 #define ADC_WR_SC3_CALF(base, value) (ADC_RMW_SC3(base, ADC_SC3_CALF_MASK, ADC_SC3_CALF(value)))
1021 #define ADC_BWR_SC3_CALF(base, value) (BME_BFI32(&ADC_SC3_REG(base), ((uint32_t)(value) << ADC_SC3_CALF_SHIFT), ADC_SC3_CALF_SHIFT, ADC_SC3_CALF_WIDTH))
1022 /*@}*/
1023 
1024 /*!
1025  * @name Register ADC_SC3, field CAL[7] (RW)
1026  *
1027  * Begins the calibration sequence when set. This field stays set while the
1028  * calibration is in progress and is cleared when the calibration sequence is
1029  * completed. CALF must be checked to determine the result of the calibration sequence.
1030  * Once started, the calibration routine cannot be interrupted by writes to the
1031  * ADC registers or the results will be invalid and CALF will set. Setting CAL
1032  * will abort any current conversion.
1033  */
1034 /*@{*/
1035 /*! @brief Read current value of the ADC_SC3_CAL field. */
1036 #define ADC_RD_SC3_CAL(base) ((ADC_SC3_REG(base) & ADC_SC3_CAL_MASK) >> ADC_SC3_CAL_SHIFT)
1037 #define ADC_BRD_SC3_CAL(base) (BME_UBFX32(&ADC_SC3_REG(base), ADC_SC3_CAL_SHIFT, ADC_SC3_CAL_WIDTH))
1038 
1039 /*! @brief Set the CAL field to a new value. */
1040 #define ADC_WR_SC3_CAL(base, value) (ADC_RMW_SC3(base, (ADC_SC3_CAL_MASK | ADC_SC3_CALF_MASK), ADC_SC3_CAL(value)))
1041 #define ADC_BWR_SC3_CAL(base, value) (BME_BFI32(&ADC_SC3_REG(base), ((uint32_t)(value) << ADC_SC3_CAL_SHIFT), ADC_SC3_CAL_SHIFT, ADC_SC3_CAL_WIDTH))
1042 /*@}*/
1043 
1044 /*******************************************************************************
1045  * ADC_OFS - ADC Offset Correction Register
1046  ******************************************************************************/
1047 
1048 /*!
1049  * @brief ADC_OFS - ADC Offset Correction Register (RW)
1050  *
1051  * Reset value: 0x00000004U
1052  *
1053  * The ADC Offset Correction Register (OFS) contains the user-selected or
1054  * calibration-generated offset error correction value. This register is a 2's
1055  * complement, left-justified, 16-bit value . The value in OFS is subtracted from the
1056  * conversion and the result is transferred into the result registers, Rn. If the
1057  * result is greater than the maximum or less than the minimum result value, it is
1058  * forced to the appropriate limit for the current mode of operation. It is
1059  * forced to 0xFFFF if over and 0x0000 if lower The formatting of the ADC offset
1060  * correction register is different from the data result registers (Rn) to preserve
1061  * the resolution of the calibration value regardless of the conversion mode
1062  * selected. Lower order bits are ignored in lower resolution modes. For example, in
1063  * 8-bit single-ended mode, the bits OFS[14:7] are subtracted from D[7:0]; bit
1064  * OFS[15] indicates the sign (negative numbers are effectively added to the result)
1065  * and bits OFS[6:0] are ignored. The same bits are used in 9-bit differential
1066  * mode since bit OFS[15] indicates the sign bit, which maps to bit D[8]. For
1067  * 16-bit differential mode, all bits OFS[15:0] are directly subtracted from the
1068  * conversion result data D[15:0]. Finally, in 16-bit single-ended mode, there is no
1069  * bit in the ADC offset correction register corresponding to the least
1070  * significant result bit D[0], so odd values (-1 or +1, and so on) cannot be subtracted
1071  * from the result. There is an effective limit to the offset values that can be
1072  * set by the user. If the magnitude of the offset is too great the results of the
1073  * conversions will cap off at the limits. OFS is automatically set according to
1074  * calibration requirements once the self calibration sequence is done (CAL is
1075  * cleared). The user may write OFS to override the calibration result if desired.
1076  * If the ADC offset correction register is written by the user to a value that
1077  * is different from the calibration value, the ADC error specifications may not
1078  * be met. It is recommended that the value generated by the calibration function
1079  * be stored in memory before overwriting with a user specified value. For more
1080  * information regarding the calibration procedure, please refer to the
1081  * Calibration functionThe ADC contains a self-calibration function that is required to
1082  * achieve the specified accuracy. section.
1083  */
1084 /*!
1085  * @name Constants and macros for entire ADC_OFS register
1086  */
1087 /*@{*/
1088 #define ADC_RD_OFS(base)         (ADC_OFS_REG(base))
1089 #define ADC_WR_OFS(base, value)  (ADC_OFS_REG(base) = (value))
1090 #define ADC_RMW_OFS(base, mask, value) (ADC_WR_OFS(base, (ADC_RD_OFS(base) & ~(mask)) | (value)))
1091 #define ADC_SET_OFS(base, value) (BME_OR32(&ADC_OFS_REG(base), (uint32_t)(value)))
1092 #define ADC_CLR_OFS(base, value) (BME_AND32(&ADC_OFS_REG(base), (uint32_t)(~(value))))
1093 #define ADC_TOG_OFS(base, value) (BME_XOR32(&ADC_OFS_REG(base), (uint32_t)(value)))
1094 /*@}*/
1095 
1096 /*
1097  * Constants & macros for individual ADC_OFS bitfields
1098  */
1099 
1100 /*!
1101  * @name Register ADC_OFS, field OFS[15:0] (RW)
1102  */
1103 /*@{*/
1104 /*! @brief Read current value of the ADC_OFS_OFS field. */
1105 #define ADC_RD_OFS_OFS(base) ((ADC_OFS_REG(base) & ADC_OFS_OFS_MASK) >> ADC_OFS_OFS_SHIFT)
1106 #define ADC_BRD_OFS_OFS(base) (BME_UBFX32(&ADC_OFS_REG(base), ADC_OFS_OFS_SHIFT, ADC_OFS_OFS_WIDTH))
1107 
1108 /*! @brief Set the OFS field to a new value. */
1109 #define ADC_WR_OFS_OFS(base, value) (ADC_RMW_OFS(base, ADC_OFS_OFS_MASK, ADC_OFS_OFS(value)))
1110 #define ADC_BWR_OFS_OFS(base, value) (BME_BFI32(&ADC_OFS_REG(base), ((uint32_t)(value) << ADC_OFS_OFS_SHIFT), ADC_OFS_OFS_SHIFT, ADC_OFS_OFS_WIDTH))
1111 /*@}*/
1112 
1113 /*******************************************************************************
1114  * ADC_PG - ADC Plus-Side Gain Register
1115  ******************************************************************************/
1116 
1117 /*!
1118  * @brief ADC_PG - ADC Plus-Side Gain Register (RW)
1119  *
1120  * Reset value: 0x00008200U
1121  *
1122  * In non-16-bit half-sample mode (Mode[1:0] not equal to 11), the plus-side
1123  * gain is automatically loaded from CLP4[9:0] and the MSBs are forced to half (bits
1124  * 16-10 = 0100000). The Plus-Side Gain Register (PG) contains the gain error
1125  * correction for the plus-side input in differential mode or the overall
1126  * conversion in single-ended mode. PG, a 16-bit real number in binary format, is the gain
1127  * adjustment factor, with the radix point fixed between PG[15] and PG[14]. This
1128  * register must be written by the user with the value described in the
1129  * calibration procedure. Otherwise, the gain error specifications may not be met. The
1130  * allowable range is from 0.25 (PGH:PGL = 0x2000) to 1.03122 (PGH:PGL = 0x83FF).
1131  * If this register is written to values outside this range the ADC will not
1132  * operate correctly. For more information regarding the calibration procedure, please
1133  * refer to the Calibration functionThe ADC contains a self-calibration function
1134  * that is required to achieve the specified accuracy. section.
1135  */
1136 /*!
1137  * @name Constants and macros for entire ADC_PG register
1138  */
1139 /*@{*/
1140 #define ADC_RD_PG(base)          (ADC_PG_REG(base))
1141 #define ADC_WR_PG(base, value)   (ADC_PG_REG(base) = (value))
1142 #define ADC_RMW_PG(base, mask, value) (ADC_WR_PG(base, (ADC_RD_PG(base) & ~(mask)) | (value)))
1143 #define ADC_SET_PG(base, value)  (BME_OR32(&ADC_PG_REG(base), (uint32_t)(value)))
1144 #define ADC_CLR_PG(base, value)  (BME_AND32(&ADC_PG_REG(base), (uint32_t)(~(value))))
1145 #define ADC_TOG_PG(base, value)  (BME_XOR32(&ADC_PG_REG(base), (uint32_t)(value)))
1146 /*@}*/
1147 
1148 /*
1149  * Constants & macros for individual ADC_PG bitfields
1150  */
1151 
1152 /*!
1153  * @name Register ADC_PG, field PG[15:0] (RW)
1154  */
1155 /*@{*/
1156 /*! @brief Read current value of the ADC_PG_PG field. */
1157 #define ADC_RD_PG_PG(base)   ((ADC_PG_REG(base) & ADC_PG_PG_MASK) >> ADC_PG_PG_SHIFT)
1158 #define ADC_BRD_PG_PG(base)  (BME_UBFX32(&ADC_PG_REG(base), ADC_PG_PG_SHIFT, ADC_PG_PG_WIDTH))
1159 
1160 /*! @brief Set the PG field to a new value. */
1161 #define ADC_WR_PG_PG(base, value) (ADC_RMW_PG(base, ADC_PG_PG_MASK, ADC_PG_PG(value)))
1162 #define ADC_BWR_PG_PG(base, value) (BME_BFI32(&ADC_PG_REG(base), ((uint32_t)(value) << ADC_PG_PG_SHIFT), ADC_PG_PG_SHIFT, ADC_PG_PG_WIDTH))
1163 /*@}*/
1164 
1165 /*******************************************************************************
1166  * ADC_MG - ADC Minus-Side Gain Register
1167  ******************************************************************************/
1168 
1169 /*!
1170  * @brief ADC_MG - ADC Minus-Side Gain Register (RW)
1171  *
1172  * Reset value: 0x00008200U
1173  *
1174  * The Minus-Side Gain Register (MG) contains the gain error correction for the
1175  * minus-side input in differential mode. This register is ignored in
1176  * single-ended mode. MG, a 16-bit real number in binary format, is the gain adjustment
1177  * factor, with the radix point fixed between MG[15] and MG[14]. This register must
1178  * be written by the user with the value described in the calibration procedure.
1179  * Otherwise, the gain error specifications may not be met. The allowable range is
1180  * from 0.25 (MG = 0x2000) to 1.03122 (MG = 0x83FF). If this register is written
1181  * to values outside this range the ADC will not operate correctly. For more
1182  * information regarding the calibration procedure, please refer to the Calibration
1183  * functionThe ADC contains a self-calibration function that is required to
1184  * achieve the specified accuracy. section.
1185  */
1186 /*!
1187  * @name Constants and macros for entire ADC_MG register
1188  */
1189 /*@{*/
1190 #define ADC_RD_MG(base)          (ADC_MG_REG(base))
1191 #define ADC_WR_MG(base, value)   (ADC_MG_REG(base) = (value))
1192 #define ADC_RMW_MG(base, mask, value) (ADC_WR_MG(base, (ADC_RD_MG(base) & ~(mask)) | (value)))
1193 #define ADC_SET_MG(base, value)  (BME_OR32(&ADC_MG_REG(base), (uint32_t)(value)))
1194 #define ADC_CLR_MG(base, value)  (BME_AND32(&ADC_MG_REG(base), (uint32_t)(~(value))))
1195 #define ADC_TOG_MG(base, value)  (BME_XOR32(&ADC_MG_REG(base), (uint32_t)(value)))
1196 /*@}*/
1197 
1198 /*
1199  * Constants & macros for individual ADC_MG bitfields
1200  */
1201 
1202 /*!
1203  * @name Register ADC_MG, field MG[15:0] (RW)
1204  */
1205 /*@{*/
1206 /*! @brief Read current value of the ADC_MG_MG field. */
1207 #define ADC_RD_MG_MG(base)   ((ADC_MG_REG(base) & ADC_MG_MG_MASK) >> ADC_MG_MG_SHIFT)
1208 #define ADC_BRD_MG_MG(base)  (BME_UBFX32(&ADC_MG_REG(base), ADC_MG_MG_SHIFT, ADC_MG_MG_WIDTH))
1209 
1210 /*! @brief Set the MG field to a new value. */
1211 #define ADC_WR_MG_MG(base, value) (ADC_RMW_MG(base, ADC_MG_MG_MASK, ADC_MG_MG(value)))
1212 #define ADC_BWR_MG_MG(base, value) (BME_BFI32(&ADC_MG_REG(base), ((uint32_t)(value) << ADC_MG_MG_SHIFT), ADC_MG_MG_SHIFT, ADC_MG_MG_WIDTH))
1213 /*@}*/
1214 
1215 /*******************************************************************************
1216  * ADC_CLPD - ADC Plus-Side General Calibration Value Register
1217  ******************************************************************************/
1218 
1219 /*!
1220  * @brief ADC_CLPD - ADC Plus-Side General Calibration Value Register (RW)
1221  *
1222  * Reset value: 0x0000000AU
1223  *
1224  * The Plus-Side General Calibration Value Registers (CLPx) contain calibration
1225  * information that is generated by the calibration function. These registers
1226  * contain seven calibration values of varying widths: CLP0[5:0], CLP1[6:0],
1227  * CLP2[7:0], CLP3[8:0], CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set
1228  * when the self-calibration sequence is done, that is, CAL is cleared. If these
1229  * registers are written by the user after calibration, the linearity error
1230  * specifications may not be met. These calibration values (CLPx) will affect the end
1231  * conversion result by having there values subtracted from the conversion
1232  * before end result is transferred into the result register. (CLP4 is only subtracted
1233  * from conversion result if the compare output value from ADC hard block is
1234  * equal to logic 0 during the 1st and 2nd compare cycle. CLPS register value is
1235  * subtracted from conversion result if ADC is configured in 16-bit Mode and the
1236  * compare output value from the ADC hard block is equal to logic 0 during 1st, 2nd,
1237  * 3rd, and the 4th compare cycles.) For more information regarding the
1238  * calibration procedure, please refer to the Calibration functionThe ADC contains a
1239  * self-calibration function that is required to achieve the specified accuracy.
1240  * section.
1241  */
1242 /*!
1243  * @name Constants and macros for entire ADC_CLPD register
1244  */
1245 /*@{*/
1246 #define ADC_RD_CLPD(base)        (ADC_CLPD_REG(base))
1247 #define ADC_WR_CLPD(base, value) (ADC_CLPD_REG(base) = (value))
1248 #define ADC_RMW_CLPD(base, mask, value) (ADC_WR_CLPD(base, (ADC_RD_CLPD(base) & ~(mask)) | (value)))
1249 #define ADC_SET_CLPD(base, value) (BME_OR32(&ADC_CLPD_REG(base), (uint32_t)(value)))
1250 #define ADC_CLR_CLPD(base, value) (BME_AND32(&ADC_CLPD_REG(base), (uint32_t)(~(value))))
1251 #define ADC_TOG_CLPD(base, value) (BME_XOR32(&ADC_CLPD_REG(base), (uint32_t)(value)))
1252 /*@}*/
1253 
1254 /*
1255  * Constants & macros for individual ADC_CLPD bitfields
1256  */
1257 
1258 /*!
1259  * @name Register ADC_CLPD, field CLPD[5:0] (RW)
1260  *
1261  * Calibration Value
1262  */
1263 /*@{*/
1264 /*! @brief Read current value of the ADC_CLPD_CLPD field. */
1265 #define ADC_RD_CLPD_CLPD(base) ((ADC_CLPD_REG(base) & ADC_CLPD_CLPD_MASK) >> ADC_CLPD_CLPD_SHIFT)
1266 #define ADC_BRD_CLPD_CLPD(base) (BME_UBFX32(&ADC_CLPD_REG(base), ADC_CLPD_CLPD_SHIFT, ADC_CLPD_CLPD_WIDTH))
1267 
1268 /*! @brief Set the CLPD field to a new value. */
1269 #define ADC_WR_CLPD_CLPD(base, value) (ADC_RMW_CLPD(base, ADC_CLPD_CLPD_MASK, ADC_CLPD_CLPD(value)))
1270 #define ADC_BWR_CLPD_CLPD(base, value) (BME_BFI32(&ADC_CLPD_REG(base), ((uint32_t)(value) << ADC_CLPD_CLPD_SHIFT), ADC_CLPD_CLPD_SHIFT, ADC_CLPD_CLPD_WIDTH))
1271 /*@}*/
1272 
1273 /*******************************************************************************
1274  * ADC_CLPS - ADC Plus-Side General Calibration Value Register
1275  ******************************************************************************/
1276 
1277 /*!
1278  * @brief ADC_CLPS - ADC Plus-Side General Calibration Value Register (RW)
1279  *
1280  * Reset value: 0x00000020U
1281  *
1282  * For more information, see CLPD register description.
1283  */
1284 /*!
1285  * @name Constants and macros for entire ADC_CLPS register
1286  */
1287 /*@{*/
1288 #define ADC_RD_CLPS(base)        (ADC_CLPS_REG(base))
1289 #define ADC_WR_CLPS(base, value) (ADC_CLPS_REG(base) = (value))
1290 #define ADC_RMW_CLPS(base, mask, value) (ADC_WR_CLPS(base, (ADC_RD_CLPS(base) & ~(mask)) | (value)))
1291 #define ADC_SET_CLPS(base, value) (BME_OR32(&ADC_CLPS_REG(base), (uint32_t)(value)))
1292 #define ADC_CLR_CLPS(base, value) (BME_AND32(&ADC_CLPS_REG(base), (uint32_t)(~(value))))
1293 #define ADC_TOG_CLPS(base, value) (BME_XOR32(&ADC_CLPS_REG(base), (uint32_t)(value)))
1294 /*@}*/
1295 
1296 /*
1297  * Constants & macros for individual ADC_CLPS bitfields
1298  */
1299 
1300 /*!
1301  * @name Register ADC_CLPS, field CLPS[5:0] (RW)
1302  *
1303  * Calibration Value
1304  */
1305 /*@{*/
1306 /*! @brief Read current value of the ADC_CLPS_CLPS field. */
1307 #define ADC_RD_CLPS_CLPS(base) ((ADC_CLPS_REG(base) & ADC_CLPS_CLPS_MASK) >> ADC_CLPS_CLPS_SHIFT)
1308 #define ADC_BRD_CLPS_CLPS(base) (BME_UBFX32(&ADC_CLPS_REG(base), ADC_CLPS_CLPS_SHIFT, ADC_CLPS_CLPS_WIDTH))
1309 
1310 /*! @brief Set the CLPS field to a new value. */
1311 #define ADC_WR_CLPS_CLPS(base, value) (ADC_RMW_CLPS(base, ADC_CLPS_CLPS_MASK, ADC_CLPS_CLPS(value)))
1312 #define ADC_BWR_CLPS_CLPS(base, value) (BME_BFI32(&ADC_CLPS_REG(base), ((uint32_t)(value) << ADC_CLPS_CLPS_SHIFT), ADC_CLPS_CLPS_SHIFT, ADC_CLPS_CLPS_WIDTH))
1313 /*@}*/
1314 
1315 /*******************************************************************************
1316  * ADC_CLP4 - ADC Plus-Side General Calibration Value Register
1317  ******************************************************************************/
1318 
1319 /*!
1320  * @brief ADC_CLP4 - ADC Plus-Side General Calibration Value Register (RW)
1321  *
1322  * Reset value: 0x00000200U
1323  *
1324  * For more information, see CLPD register description.
1325  */
1326 /*!
1327  * @name Constants and macros for entire ADC_CLP4 register
1328  */
1329 /*@{*/
1330 #define ADC_RD_CLP4(base)        (ADC_CLP4_REG(base))
1331 #define ADC_WR_CLP4(base, value) (ADC_CLP4_REG(base) = (value))
1332 #define ADC_RMW_CLP4(base, mask, value) (ADC_WR_CLP4(base, (ADC_RD_CLP4(base) & ~(mask)) | (value)))
1333 #define ADC_SET_CLP4(base, value) (BME_OR32(&ADC_CLP4_REG(base), (uint32_t)(value)))
1334 #define ADC_CLR_CLP4(base, value) (BME_AND32(&ADC_CLP4_REG(base), (uint32_t)(~(value))))
1335 #define ADC_TOG_CLP4(base, value) (BME_XOR32(&ADC_CLP4_REG(base), (uint32_t)(value)))
1336 /*@}*/
1337 
1338 /*
1339  * Constants & macros for individual ADC_CLP4 bitfields
1340  */
1341 
1342 /*!
1343  * @name Register ADC_CLP4, field CLP4[9:0] (RW)
1344  *
1345  * Calibration Value
1346  */
1347 /*@{*/
1348 /*! @brief Read current value of the ADC_CLP4_CLP4 field. */
1349 #define ADC_RD_CLP4_CLP4(base) ((ADC_CLP4_REG(base) & ADC_CLP4_CLP4_MASK) >> ADC_CLP4_CLP4_SHIFT)
1350 #define ADC_BRD_CLP4_CLP4(base) (BME_UBFX32(&ADC_CLP4_REG(base), ADC_CLP4_CLP4_SHIFT, ADC_CLP4_CLP4_WIDTH))
1351 
1352 /*! @brief Set the CLP4 field to a new value. */
1353 #define ADC_WR_CLP4_CLP4(base, value) (ADC_RMW_CLP4(base, ADC_CLP4_CLP4_MASK, ADC_CLP4_CLP4(value)))
1354 #define ADC_BWR_CLP4_CLP4(base, value) (BME_BFI32(&ADC_CLP4_REG(base), ((uint32_t)(value) << ADC_CLP4_CLP4_SHIFT), ADC_CLP4_CLP4_SHIFT, ADC_CLP4_CLP4_WIDTH))
1355 /*@}*/
1356 
1357 /*******************************************************************************
1358  * ADC_CLP3 - ADC Plus-Side General Calibration Value Register
1359  ******************************************************************************/
1360 
1361 /*!
1362  * @brief ADC_CLP3 - ADC Plus-Side General Calibration Value Register (RW)
1363  *
1364  * Reset value: 0x00000100U
1365  *
1366  * For more information, see CLPD register description.
1367  */
1368 /*!
1369  * @name Constants and macros for entire ADC_CLP3 register
1370  */
1371 /*@{*/
1372 #define ADC_RD_CLP3(base)        (ADC_CLP3_REG(base))
1373 #define ADC_WR_CLP3(base, value) (ADC_CLP3_REG(base) = (value))
1374 #define ADC_RMW_CLP3(base, mask, value) (ADC_WR_CLP3(base, (ADC_RD_CLP3(base) & ~(mask)) | (value)))
1375 #define ADC_SET_CLP3(base, value) (BME_OR32(&ADC_CLP3_REG(base), (uint32_t)(value)))
1376 #define ADC_CLR_CLP3(base, value) (BME_AND32(&ADC_CLP3_REG(base), (uint32_t)(~(value))))
1377 #define ADC_TOG_CLP3(base, value) (BME_XOR32(&ADC_CLP3_REG(base), (uint32_t)(value)))
1378 /*@}*/
1379 
1380 /*
1381  * Constants & macros for individual ADC_CLP3 bitfields
1382  */
1383 
1384 /*!
1385  * @name Register ADC_CLP3, field CLP3[8:0] (RW)
1386  *
1387  * Calibration Value
1388  */
1389 /*@{*/
1390 /*! @brief Read current value of the ADC_CLP3_CLP3 field. */
1391 #define ADC_RD_CLP3_CLP3(base) ((ADC_CLP3_REG(base) & ADC_CLP3_CLP3_MASK) >> ADC_CLP3_CLP3_SHIFT)
1392 #define ADC_BRD_CLP3_CLP3(base) (BME_UBFX32(&ADC_CLP3_REG(base), ADC_CLP3_CLP3_SHIFT, ADC_CLP3_CLP3_WIDTH))
1393 
1394 /*! @brief Set the CLP3 field to a new value. */
1395 #define ADC_WR_CLP3_CLP3(base, value) (ADC_RMW_CLP3(base, ADC_CLP3_CLP3_MASK, ADC_CLP3_CLP3(value)))
1396 #define ADC_BWR_CLP3_CLP3(base, value) (BME_BFI32(&ADC_CLP3_REG(base), ((uint32_t)(value) << ADC_CLP3_CLP3_SHIFT), ADC_CLP3_CLP3_SHIFT, ADC_CLP3_CLP3_WIDTH))
1397 /*@}*/
1398 
1399 /*******************************************************************************
1400  * ADC_CLP2 - ADC Plus-Side General Calibration Value Register
1401  ******************************************************************************/
1402 
1403 /*!
1404  * @brief ADC_CLP2 - ADC Plus-Side General Calibration Value Register (RW)
1405  *
1406  * Reset value: 0x00000080U
1407  *
1408  * For more information, see CLPD register description.
1409  */
1410 /*!
1411  * @name Constants and macros for entire ADC_CLP2 register
1412  */
1413 /*@{*/
1414 #define ADC_RD_CLP2(base)        (ADC_CLP2_REG(base))
1415 #define ADC_WR_CLP2(base, value) (ADC_CLP2_REG(base) = (value))
1416 #define ADC_RMW_CLP2(base, mask, value) (ADC_WR_CLP2(base, (ADC_RD_CLP2(base) & ~(mask)) | (value)))
1417 #define ADC_SET_CLP2(base, value) (BME_OR32(&ADC_CLP2_REG(base), (uint32_t)(value)))
1418 #define ADC_CLR_CLP2(base, value) (BME_AND32(&ADC_CLP2_REG(base), (uint32_t)(~(value))))
1419 #define ADC_TOG_CLP2(base, value) (BME_XOR32(&ADC_CLP2_REG(base), (uint32_t)(value)))
1420 /*@}*/
1421 
1422 /*
1423  * Constants & macros for individual ADC_CLP2 bitfields
1424  */
1425 
1426 /*!
1427  * @name Register ADC_CLP2, field CLP2[7:0] (RW)
1428  *
1429  * Calibration Value
1430  */
1431 /*@{*/
1432 /*! @brief Read current value of the ADC_CLP2_CLP2 field. */
1433 #define ADC_RD_CLP2_CLP2(base) ((ADC_CLP2_REG(base) & ADC_CLP2_CLP2_MASK) >> ADC_CLP2_CLP2_SHIFT)
1434 #define ADC_BRD_CLP2_CLP2(base) (BME_UBFX32(&ADC_CLP2_REG(base), ADC_CLP2_CLP2_SHIFT, ADC_CLP2_CLP2_WIDTH))
1435 
1436 /*! @brief Set the CLP2 field to a new value. */
1437 #define ADC_WR_CLP2_CLP2(base, value) (ADC_RMW_CLP2(base, ADC_CLP2_CLP2_MASK, ADC_CLP2_CLP2(value)))
1438 #define ADC_BWR_CLP2_CLP2(base, value) (BME_BFI32(&ADC_CLP2_REG(base), ((uint32_t)(value) << ADC_CLP2_CLP2_SHIFT), ADC_CLP2_CLP2_SHIFT, ADC_CLP2_CLP2_WIDTH))
1439 /*@}*/
1440 
1441 /*******************************************************************************
1442  * ADC_CLP1 - ADC Plus-Side General Calibration Value Register
1443  ******************************************************************************/
1444 
1445 /*!
1446  * @brief ADC_CLP1 - ADC Plus-Side General Calibration Value Register (RW)
1447  *
1448  * Reset value: 0x00000040U
1449  *
1450  * For more information, see CLPD register description.
1451  */
1452 /*!
1453  * @name Constants and macros for entire ADC_CLP1 register
1454  */
1455 /*@{*/
1456 #define ADC_RD_CLP1(base)        (ADC_CLP1_REG(base))
1457 #define ADC_WR_CLP1(base, value) (ADC_CLP1_REG(base) = (value))
1458 #define ADC_RMW_CLP1(base, mask, value) (ADC_WR_CLP1(base, (ADC_RD_CLP1(base) & ~(mask)) | (value)))
1459 #define ADC_SET_CLP1(base, value) (BME_OR32(&ADC_CLP1_REG(base), (uint32_t)(value)))
1460 #define ADC_CLR_CLP1(base, value) (BME_AND32(&ADC_CLP1_REG(base), (uint32_t)(~(value))))
1461 #define ADC_TOG_CLP1(base, value) (BME_XOR32(&ADC_CLP1_REG(base), (uint32_t)(value)))
1462 /*@}*/
1463 
1464 /*
1465  * Constants & macros for individual ADC_CLP1 bitfields
1466  */
1467 
1468 /*!
1469  * @name Register ADC_CLP1, field CLP1[6:0] (RW)
1470  *
1471  * Calibration Value
1472  */
1473 /*@{*/
1474 /*! @brief Read current value of the ADC_CLP1_CLP1 field. */
1475 #define ADC_RD_CLP1_CLP1(base) ((ADC_CLP1_REG(base) & ADC_CLP1_CLP1_MASK) >> ADC_CLP1_CLP1_SHIFT)
1476 #define ADC_BRD_CLP1_CLP1(base) (BME_UBFX32(&ADC_CLP1_REG(base), ADC_CLP1_CLP1_SHIFT, ADC_CLP1_CLP1_WIDTH))
1477 
1478 /*! @brief Set the CLP1 field to a new value. */
1479 #define ADC_WR_CLP1_CLP1(base, value) (ADC_RMW_CLP1(base, ADC_CLP1_CLP1_MASK, ADC_CLP1_CLP1(value)))
1480 #define ADC_BWR_CLP1_CLP1(base, value) (BME_BFI32(&ADC_CLP1_REG(base), ((uint32_t)(value) << ADC_CLP1_CLP1_SHIFT), ADC_CLP1_CLP1_SHIFT, ADC_CLP1_CLP1_WIDTH))
1481 /*@}*/
1482 
1483 /*******************************************************************************
1484  * ADC_CLP0 - ADC Plus-Side General Calibration Value Register
1485  ******************************************************************************/
1486 
1487 /*!
1488  * @brief ADC_CLP0 - ADC Plus-Side General Calibration Value Register (RW)
1489  *
1490  * Reset value: 0x00000020U
1491  *
1492  * For more information, see CLPD register description.
1493  */
1494 /*!
1495  * @name Constants and macros for entire ADC_CLP0 register
1496  */
1497 /*@{*/
1498 #define ADC_RD_CLP0(base)        (ADC_CLP0_REG(base))
1499 #define ADC_WR_CLP0(base, value) (ADC_CLP0_REG(base) = (value))
1500 #define ADC_RMW_CLP0(base, mask, value) (ADC_WR_CLP0(base, (ADC_RD_CLP0(base) & ~(mask)) | (value)))
1501 #define ADC_SET_CLP0(base, value) (BME_OR32(&ADC_CLP0_REG(base), (uint32_t)(value)))
1502 #define ADC_CLR_CLP0(base, value) (BME_AND32(&ADC_CLP0_REG(base), (uint32_t)(~(value))))
1503 #define ADC_TOG_CLP0(base, value) (BME_XOR32(&ADC_CLP0_REG(base), (uint32_t)(value)))
1504 /*@}*/
1505 
1506 /*
1507  * Constants & macros for individual ADC_CLP0 bitfields
1508  */
1509 
1510 /*!
1511  * @name Register ADC_CLP0, field CLP0[5:0] (RW)
1512  *
1513  * Calibration Value
1514  */
1515 /*@{*/
1516 /*! @brief Read current value of the ADC_CLP0_CLP0 field. */
1517 #define ADC_RD_CLP0_CLP0(base) ((ADC_CLP0_REG(base) & ADC_CLP0_CLP0_MASK) >> ADC_CLP0_CLP0_SHIFT)
1518 #define ADC_BRD_CLP0_CLP0(base) (BME_UBFX32(&ADC_CLP0_REG(base), ADC_CLP0_CLP0_SHIFT, ADC_CLP0_CLP0_WIDTH))
1519 
1520 /*! @brief Set the CLP0 field to a new value. */
1521 #define ADC_WR_CLP0_CLP0(base, value) (ADC_RMW_CLP0(base, ADC_CLP0_CLP0_MASK, ADC_CLP0_CLP0(value)))
1522 #define ADC_BWR_CLP0_CLP0(base, value) (BME_BFI32(&ADC_CLP0_REG(base), ((uint32_t)(value) << ADC_CLP0_CLP0_SHIFT), ADC_CLP0_CLP0_SHIFT, ADC_CLP0_CLP0_WIDTH))
1523 /*@}*/
1524 
1525 /*******************************************************************************
1526  * ADC_CLMD - ADC Minus-Side General Calibration Value Register
1527  ******************************************************************************/
1528 
1529 /*!
1530  * @brief ADC_CLMD - ADC Minus-Side General Calibration Value Register (RW)
1531  *
1532  * Reset value: 0x0000000AU
1533  *
1534  * The Minus-Side General Calibration Value (CLMx) registers contain calibration
1535  * information that is generated by the calibration function. These registers
1536  * contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],
1537  * CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are automatically
1538  * set when the self-calibration sequence is done, that is, CAL is cleared. If
1539  * these registers are written by the user after calibration, the linearity error
1540  * specifications may not be met. If Differential is enabled (DIFF=1), these
1541  * calibration values (CLMx) with the exception of CLMD will affect the end conversion
1542  * result by having there values subtracted from the conversion before end result
1543  * is transferred into the result register. (CLM4 is only subtracted from
1544  * conversion result if the compare output value from ADC hard block is equal to logic 0
1545  * during the 1st and 2nd compare cycle. CLMS register value is subtracted from
1546  * conversion result if ADC is configured in 16-bit Mode and the compare output
1547  * value from the ADC hard block is equal to logic 0 during 1st, 2nd, 3rd, and the
1548  * 4th compare cycles.) For more information regarding the calibration
1549  * procedure, please refer to the Calibration functionThe ADC contains a self-calibration
1550  * function that is required to achieve the specified accuracy. section.
1551  */
1552 /*!
1553  * @name Constants and macros for entire ADC_CLMD register
1554  */
1555 /*@{*/
1556 #define ADC_RD_CLMD(base)        (ADC_CLMD_REG(base))
1557 #define ADC_WR_CLMD(base, value) (ADC_CLMD_REG(base) = (value))
1558 #define ADC_RMW_CLMD(base, mask, value) (ADC_WR_CLMD(base, (ADC_RD_CLMD(base) & ~(mask)) | (value)))
1559 #define ADC_SET_CLMD(base, value) (BME_OR32(&ADC_CLMD_REG(base), (uint32_t)(value)))
1560 #define ADC_CLR_CLMD(base, value) (BME_AND32(&ADC_CLMD_REG(base), (uint32_t)(~(value))))
1561 #define ADC_TOG_CLMD(base, value) (BME_XOR32(&ADC_CLMD_REG(base), (uint32_t)(value)))
1562 /*@}*/
1563 
1564 /*
1565  * Constants & macros for individual ADC_CLMD bitfields
1566  */
1567 
1568 /*!
1569  * @name Register ADC_CLMD, field CLMD[5:0] (RW)
1570  *
1571  * Calibration Value
1572  */
1573 /*@{*/
1574 /*! @brief Read current value of the ADC_CLMD_CLMD field. */
1575 #define ADC_RD_CLMD_CLMD(base) ((ADC_CLMD_REG(base) & ADC_CLMD_CLMD_MASK) >> ADC_CLMD_CLMD_SHIFT)
1576 #define ADC_BRD_CLMD_CLMD(base) (BME_UBFX32(&ADC_CLMD_REG(base), ADC_CLMD_CLMD_SHIFT, ADC_CLMD_CLMD_WIDTH))
1577 
1578 /*! @brief Set the CLMD field to a new value. */
1579 #define ADC_WR_CLMD_CLMD(base, value) (ADC_RMW_CLMD(base, ADC_CLMD_CLMD_MASK, ADC_CLMD_CLMD(value)))
1580 #define ADC_BWR_CLMD_CLMD(base, value) (BME_BFI32(&ADC_CLMD_REG(base), ((uint32_t)(value) << ADC_CLMD_CLMD_SHIFT), ADC_CLMD_CLMD_SHIFT, ADC_CLMD_CLMD_WIDTH))
1581 /*@}*/
1582 
1583 /*******************************************************************************
1584  * ADC_CLMS - ADC Minus-Side General Calibration Value Register
1585  ******************************************************************************/
1586 
1587 /*!
1588  * @brief ADC_CLMS - ADC Minus-Side General Calibration Value Register (RW)
1589  *
1590  * Reset value: 0x00000020U
1591  *
1592  * For more information, see CLMD register description.
1593  */
1594 /*!
1595  * @name Constants and macros for entire ADC_CLMS register
1596  */
1597 /*@{*/
1598 #define ADC_RD_CLMS(base)        (ADC_CLMS_REG(base))
1599 #define ADC_WR_CLMS(base, value) (ADC_CLMS_REG(base) = (value))
1600 #define ADC_RMW_CLMS(base, mask, value) (ADC_WR_CLMS(base, (ADC_RD_CLMS(base) & ~(mask)) | (value)))
1601 #define ADC_SET_CLMS(base, value) (BME_OR32(&ADC_CLMS_REG(base), (uint32_t)(value)))
1602 #define ADC_CLR_CLMS(base, value) (BME_AND32(&ADC_CLMS_REG(base), (uint32_t)(~(value))))
1603 #define ADC_TOG_CLMS(base, value) (BME_XOR32(&ADC_CLMS_REG(base), (uint32_t)(value)))
1604 /*@}*/
1605 
1606 /*
1607  * Constants & macros for individual ADC_CLMS bitfields
1608  */
1609 
1610 /*!
1611  * @name Register ADC_CLMS, field CLMS[5:0] (RW)
1612  *
1613  * Calibration Value
1614  */
1615 /*@{*/
1616 /*! @brief Read current value of the ADC_CLMS_CLMS field. */
1617 #define ADC_RD_CLMS_CLMS(base) ((ADC_CLMS_REG(base) & ADC_CLMS_CLMS_MASK) >> ADC_CLMS_CLMS_SHIFT)
1618 #define ADC_BRD_CLMS_CLMS(base) (BME_UBFX32(&ADC_CLMS_REG(base), ADC_CLMS_CLMS_SHIFT, ADC_CLMS_CLMS_WIDTH))
1619 
1620 /*! @brief Set the CLMS field to a new value. */
1621 #define ADC_WR_CLMS_CLMS(base, value) (ADC_RMW_CLMS(base, ADC_CLMS_CLMS_MASK, ADC_CLMS_CLMS(value)))
1622 #define ADC_BWR_CLMS_CLMS(base, value) (BME_BFI32(&ADC_CLMS_REG(base), ((uint32_t)(value) << ADC_CLMS_CLMS_SHIFT), ADC_CLMS_CLMS_SHIFT, ADC_CLMS_CLMS_WIDTH))
1623 /*@}*/
1624 
1625 /*******************************************************************************
1626  * ADC_CLM4 - ADC Minus-Side General Calibration Value Register
1627  ******************************************************************************/
1628 
1629 /*!
1630  * @brief ADC_CLM4 - ADC Minus-Side General Calibration Value Register (RW)
1631  *
1632  * Reset value: 0x00000200U
1633  *
1634  * For more information, see CLMD register description.
1635  */
1636 /*!
1637  * @name Constants and macros for entire ADC_CLM4 register
1638  */
1639 /*@{*/
1640 #define ADC_RD_CLM4(base)        (ADC_CLM4_REG(base))
1641 #define ADC_WR_CLM4(base, value) (ADC_CLM4_REG(base) = (value))
1642 #define ADC_RMW_CLM4(base, mask, value) (ADC_WR_CLM4(base, (ADC_RD_CLM4(base) & ~(mask)) | (value)))
1643 #define ADC_SET_CLM4(base, value) (BME_OR32(&ADC_CLM4_REG(base), (uint32_t)(value)))
1644 #define ADC_CLR_CLM4(base, value) (BME_AND32(&ADC_CLM4_REG(base), (uint32_t)(~(value))))
1645 #define ADC_TOG_CLM4(base, value) (BME_XOR32(&ADC_CLM4_REG(base), (uint32_t)(value)))
1646 /*@}*/
1647 
1648 /*
1649  * Constants & macros for individual ADC_CLM4 bitfields
1650  */
1651 
1652 /*!
1653  * @name Register ADC_CLM4, field CLM4[9:0] (RW)
1654  *
1655  * Calibration Value
1656  */
1657 /*@{*/
1658 /*! @brief Read current value of the ADC_CLM4_CLM4 field. */
1659 #define ADC_RD_CLM4_CLM4(base) ((ADC_CLM4_REG(base) & ADC_CLM4_CLM4_MASK) >> ADC_CLM4_CLM4_SHIFT)
1660 #define ADC_BRD_CLM4_CLM4(base) (BME_UBFX32(&ADC_CLM4_REG(base), ADC_CLM4_CLM4_SHIFT, ADC_CLM4_CLM4_WIDTH))
1661 
1662 /*! @brief Set the CLM4 field to a new value. */
1663 #define ADC_WR_CLM4_CLM4(base, value) (ADC_RMW_CLM4(base, ADC_CLM4_CLM4_MASK, ADC_CLM4_CLM4(value)))
1664 #define ADC_BWR_CLM4_CLM4(base, value) (BME_BFI32(&ADC_CLM4_REG(base), ((uint32_t)(value) << ADC_CLM4_CLM4_SHIFT), ADC_CLM4_CLM4_SHIFT, ADC_CLM4_CLM4_WIDTH))
1665 /*@}*/
1666 
1667 /*******************************************************************************
1668  * ADC_CLM3 - ADC Minus-Side General Calibration Value Register
1669  ******************************************************************************/
1670 
1671 /*!
1672  * @brief ADC_CLM3 - ADC Minus-Side General Calibration Value Register (RW)
1673  *
1674  * Reset value: 0x00000100U
1675  *
1676  * For more information, see CLMD register description.
1677  */
1678 /*!
1679  * @name Constants and macros for entire ADC_CLM3 register
1680  */
1681 /*@{*/
1682 #define ADC_RD_CLM3(base)        (ADC_CLM3_REG(base))
1683 #define ADC_WR_CLM3(base, value) (ADC_CLM3_REG(base) = (value))
1684 #define ADC_RMW_CLM3(base, mask, value) (ADC_WR_CLM3(base, (ADC_RD_CLM3(base) & ~(mask)) | (value)))
1685 #define ADC_SET_CLM3(base, value) (BME_OR32(&ADC_CLM3_REG(base), (uint32_t)(value)))
1686 #define ADC_CLR_CLM3(base, value) (BME_AND32(&ADC_CLM3_REG(base), (uint32_t)(~(value))))
1687 #define ADC_TOG_CLM3(base, value) (BME_XOR32(&ADC_CLM3_REG(base), (uint32_t)(value)))
1688 /*@}*/
1689 
1690 /*
1691  * Constants & macros for individual ADC_CLM3 bitfields
1692  */
1693 
1694 /*!
1695  * @name Register ADC_CLM3, field CLM3[8:0] (RW)
1696  *
1697  * Calibration Value
1698  */
1699 /*@{*/
1700 /*! @brief Read current value of the ADC_CLM3_CLM3 field. */
1701 #define ADC_RD_CLM3_CLM3(base) ((ADC_CLM3_REG(base) & ADC_CLM3_CLM3_MASK) >> ADC_CLM3_CLM3_SHIFT)
1702 #define ADC_BRD_CLM3_CLM3(base) (BME_UBFX32(&ADC_CLM3_REG(base), ADC_CLM3_CLM3_SHIFT, ADC_CLM3_CLM3_WIDTH))
1703 
1704 /*! @brief Set the CLM3 field to a new value. */
1705 #define ADC_WR_CLM3_CLM3(base, value) (ADC_RMW_CLM3(base, ADC_CLM3_CLM3_MASK, ADC_CLM3_CLM3(value)))
1706 #define ADC_BWR_CLM3_CLM3(base, value) (BME_BFI32(&ADC_CLM3_REG(base), ((uint32_t)(value) << ADC_CLM3_CLM3_SHIFT), ADC_CLM3_CLM3_SHIFT, ADC_CLM3_CLM3_WIDTH))
1707 /*@}*/
1708 
1709 /*******************************************************************************
1710  * ADC_CLM2 - ADC Minus-Side General Calibration Value Register
1711  ******************************************************************************/
1712 
1713 /*!
1714  * @brief ADC_CLM2 - ADC Minus-Side General Calibration Value Register (RW)
1715  *
1716  * Reset value: 0x00000080U
1717  *
1718  * For more information, see CLMD register description.
1719  */
1720 /*!
1721  * @name Constants and macros for entire ADC_CLM2 register
1722  */
1723 /*@{*/
1724 #define ADC_RD_CLM2(base)        (ADC_CLM2_REG(base))
1725 #define ADC_WR_CLM2(base, value) (ADC_CLM2_REG(base) = (value))
1726 #define ADC_RMW_CLM2(base, mask, value) (ADC_WR_CLM2(base, (ADC_RD_CLM2(base) & ~(mask)) | (value)))
1727 #define ADC_SET_CLM2(base, value) (BME_OR32(&ADC_CLM2_REG(base), (uint32_t)(value)))
1728 #define ADC_CLR_CLM2(base, value) (BME_AND32(&ADC_CLM2_REG(base), (uint32_t)(~(value))))
1729 #define ADC_TOG_CLM2(base, value) (BME_XOR32(&ADC_CLM2_REG(base), (uint32_t)(value)))
1730 /*@}*/
1731 
1732 /*
1733  * Constants & macros for individual ADC_CLM2 bitfields
1734  */
1735 
1736 /*!
1737  * @name Register ADC_CLM2, field CLM2[7:0] (RW)
1738  *
1739  * Calibration Value
1740  */
1741 /*@{*/
1742 /*! @brief Read current value of the ADC_CLM2_CLM2 field. */
1743 #define ADC_RD_CLM2_CLM2(base) ((ADC_CLM2_REG(base) & ADC_CLM2_CLM2_MASK) >> ADC_CLM2_CLM2_SHIFT)
1744 #define ADC_BRD_CLM2_CLM2(base) (BME_UBFX32(&ADC_CLM2_REG(base), ADC_CLM2_CLM2_SHIFT, ADC_CLM2_CLM2_WIDTH))
1745 
1746 /*! @brief Set the CLM2 field to a new value. */
1747 #define ADC_WR_CLM2_CLM2(base, value) (ADC_RMW_CLM2(base, ADC_CLM2_CLM2_MASK, ADC_CLM2_CLM2(value)))
1748 #define ADC_BWR_CLM2_CLM2(base, value) (BME_BFI32(&ADC_CLM2_REG(base), ((uint32_t)(value) << ADC_CLM2_CLM2_SHIFT), ADC_CLM2_CLM2_SHIFT, ADC_CLM2_CLM2_WIDTH))
1749 /*@}*/
1750 
1751 /*******************************************************************************
1752  * ADC_CLM1 - ADC Minus-Side General Calibration Value Register
1753  ******************************************************************************/
1754 
1755 /*!
1756  * @brief ADC_CLM1 - ADC Minus-Side General Calibration Value Register (RW)
1757  *
1758  * Reset value: 0x00000040U
1759  *
1760  * For more information, see CLMD register description.
1761  */
1762 /*!
1763  * @name Constants and macros for entire ADC_CLM1 register
1764  */
1765 /*@{*/
1766 #define ADC_RD_CLM1(base)        (ADC_CLM1_REG(base))
1767 #define ADC_WR_CLM1(base, value) (ADC_CLM1_REG(base) = (value))
1768 #define ADC_RMW_CLM1(base, mask, value) (ADC_WR_CLM1(base, (ADC_RD_CLM1(base) & ~(mask)) | (value)))
1769 #define ADC_SET_CLM1(base, value) (BME_OR32(&ADC_CLM1_REG(base), (uint32_t)(value)))
1770 #define ADC_CLR_CLM1(base, value) (BME_AND32(&ADC_CLM1_REG(base), (uint32_t)(~(value))))
1771 #define ADC_TOG_CLM1(base, value) (BME_XOR32(&ADC_CLM1_REG(base), (uint32_t)(value)))
1772 /*@}*/
1773 
1774 /*
1775  * Constants & macros for individual ADC_CLM1 bitfields
1776  */
1777 
1778 /*!
1779  * @name Register ADC_CLM1, field CLM1[6:0] (RW)
1780  *
1781  * Calibration Value
1782  */
1783 /*@{*/
1784 /*! @brief Read current value of the ADC_CLM1_CLM1 field. */
1785 #define ADC_RD_CLM1_CLM1(base) ((ADC_CLM1_REG(base) & ADC_CLM1_CLM1_MASK) >> ADC_CLM1_CLM1_SHIFT)
1786 #define ADC_BRD_CLM1_CLM1(base) (BME_UBFX32(&ADC_CLM1_REG(base), ADC_CLM1_CLM1_SHIFT, ADC_CLM1_CLM1_WIDTH))
1787 
1788 /*! @brief Set the CLM1 field to a new value. */
1789 #define ADC_WR_CLM1_CLM1(base, value) (ADC_RMW_CLM1(base, ADC_CLM1_CLM1_MASK, ADC_CLM1_CLM1(value)))
1790 #define ADC_BWR_CLM1_CLM1(base, value) (BME_BFI32(&ADC_CLM1_REG(base), ((uint32_t)(value) << ADC_CLM1_CLM1_SHIFT), ADC_CLM1_CLM1_SHIFT, ADC_CLM1_CLM1_WIDTH))
1791 /*@}*/
1792 
1793 /*******************************************************************************
1794  * ADC_CLM0 - ADC Minus-Side General Calibration Value Register
1795  ******************************************************************************/
1796 
1797 /*!
1798  * @brief ADC_CLM0 - ADC Minus-Side General Calibration Value Register (RW)
1799  *
1800  * Reset value: 0x00000020U
1801  *
1802  * For more information, see CLMD register description.
1803  */
1804 /*!
1805  * @name Constants and macros for entire ADC_CLM0 register
1806  */
1807 /*@{*/
1808 #define ADC_RD_CLM0(base)        (ADC_CLM0_REG(base))
1809 #define ADC_WR_CLM0(base, value) (ADC_CLM0_REG(base) = (value))
1810 #define ADC_RMW_CLM0(base, mask, value) (ADC_WR_CLM0(base, (ADC_RD_CLM0(base) & ~(mask)) | (value)))
1811 #define ADC_SET_CLM0(base, value) (BME_OR32(&ADC_CLM0_REG(base), (uint32_t)(value)))
1812 #define ADC_CLR_CLM0(base, value) (BME_AND32(&ADC_CLM0_REG(base), (uint32_t)(~(value))))
1813 #define ADC_TOG_CLM0(base, value) (BME_XOR32(&ADC_CLM0_REG(base), (uint32_t)(value)))
1814 /*@}*/
1815 
1816 /*
1817  * Constants & macros for individual ADC_CLM0 bitfields
1818  */
1819 
1820 /*!
1821  * @name Register ADC_CLM0, field CLM0[5:0] (RW)
1822  *
1823  * Calibration Value
1824  */
1825 /*@{*/
1826 /*! @brief Read current value of the ADC_CLM0_CLM0 field. */
1827 #define ADC_RD_CLM0_CLM0(base) ((ADC_CLM0_REG(base) & ADC_CLM0_CLM0_MASK) >> ADC_CLM0_CLM0_SHIFT)
1828 #define ADC_BRD_CLM0_CLM0(base) (BME_UBFX32(&ADC_CLM0_REG(base), ADC_CLM0_CLM0_SHIFT, ADC_CLM0_CLM0_WIDTH))
1829 
1830 /*! @brief Set the CLM0 field to a new value. */
1831 #define ADC_WR_CLM0_CLM0(base, value) (ADC_RMW_CLM0(base, ADC_CLM0_CLM0_MASK, ADC_CLM0_CLM0(value)))
1832 #define ADC_BWR_CLM0_CLM0(base, value) (BME_BFI32(&ADC_CLM0_REG(base), ((uint32_t)(value) << ADC_CLM0_CLM0_SHIFT), ADC_CLM0_CLM0_SHIFT, ADC_CLM0_CLM0_WIDTH))
1833 /*@}*/
1834 
1835 /*
1836  * MKW40Z4 BLE_RF_REGS
1837  *
1838  * Bluetooth Low Energy RF Registers
1839  *
1840  * Registers defined in this header file:
1841  * - BLE_RF_REGS_BLE_PART_ID - Bluetooth Low Energy Part ID
1842  * - BLE_RF_REGS_DSM_STATUS - DSM Status
1843  * - BLE_RF_REGS_BLE_AFC - Bluetooth Low Energy AFC
1844  * - BLE_RF_REGS_BLE_BSM - Bluetooth Low Energy BSM
1845  */
1846 
1847 #define BLE_RF_REGS_INSTANCE_COUNT (1U) /*!< Number of instances of the BLE_RF_REGS module. */
1848 #define BLE_RF_REGS_IDX (0U) /*!< Instance number for BLE_RF_REGS. */
1849 
1850 /*******************************************************************************
1851  * BLE_RF_REGS_BLE_PART_ID - Bluetooth Low Energy Part ID
1852  ******************************************************************************/
1853 
1854 /*!
1855  * @brief BLE_RF_REGS_BLE_PART_ID - Bluetooth Low Energy Part ID (RO)
1856  *
1857  * Reset value: 0x0001U
1858  */
1859 /*!
1860  * @name Constants and macros for entire BLE_RF_REGS_BLE_PART_ID register
1861  */
1862 /*@{*/
1863 #define BLE_RF_REGS_RD_BLE_PART_ID(base) (BLE_RF_REGS_BLE_PART_ID_REG(base))
1864 /*@}*/
1865 
1866 /*******************************************************************************
1867  * BLE_RF_REGS_DSM_STATUS - DSM Status
1868  ******************************************************************************/
1869 
1870 /*!
1871  * @brief BLE_RF_REGS_DSM_STATUS - DSM Status (RO)
1872  *
1873  * Reset value: 0x0000U
1874  */
1875 /*!
1876  * @name Constants and macros for entire BLE_RF_REGS_DSM_STATUS register
1877  */
1878 /*@{*/
1879 #define BLE_RF_REGS_RD_DSM_STATUS(base) (BLE_RF_REGS_DSM_STATUS_REG(base))
1880 /*@}*/
1881 
1882 /*
1883  * Constants & macros for individual BLE_RF_REGS_DSM_STATUS bitfields
1884  */
1885 
1886 /*!
1887  * @name Register BLE_RF_REGS_DSM_STATUS, field ORF_SYSCLK_REQ[0] (RO)
1888  *
1889  * Reflects the state of the BLE LL output of the same name, the control signal
1890  * used to enable/disable the RF Oscillator for entry and exit from DSM (deep
1891  * sleep mode).
1892  */
1893 /*@{*/
1894 /*! @brief Read current value of the BLE_RF_REGS_DSM_STATUS_ORF_SYSCLK_REQ field. */
1895 #define BLE_RF_REGS_RD_DSM_STATUS_ORF_SYSCLK_REQ(base) ((BLE_RF_REGS_DSM_STATUS_REG(base) & BLE_RF_REGS_DSM_STATUS_ORF_SYSCLK_REQ_MASK) >> BLE_RF_REGS_DSM_STATUS_ORF_SYSCLK_REQ_SHIFT)
1896 #define BLE_RF_REGS_BRD_DSM_STATUS_ORF_SYSCLK_REQ(base) (BME_UBFX16(&BLE_RF_REGS_DSM_STATUS_REG(base), BLE_RF_REGS_DSM_STATUS_ORF_SYSCLK_REQ_SHIFT, BLE_RF_REGS_DSM_STATUS_ORF_SYSCLK_REQ_WIDTH))
1897 /*@}*/
1898 
1899 /*!
1900  * @name Register BLE_RF_REGS_DSM_STATUS, field RIF_LL_ACTIVE[1] (RO)
1901  *
1902  * Reflects the state of the BLE LL output of the same name, the signal to be
1903  * used by the host as an 'early' indication to prevent host to do any operations
1904  * while the BLE block is doing transceiver operations, so as to reduce the peak
1905  * power and noise.
1906  */
1907 /*@{*/
1908 /*! @brief Read current value of the BLE_RF_REGS_DSM_STATUS_RIF_LL_ACTIVE field. */
1909 #define BLE_RF_REGS_RD_DSM_STATUS_RIF_LL_ACTIVE(base) ((BLE_RF_REGS_DSM_STATUS_REG(base) & BLE_RF_REGS_DSM_STATUS_RIF_LL_ACTIVE_MASK) >> BLE_RF_REGS_DSM_STATUS_RIF_LL_ACTIVE_SHIFT)
1910 #define BLE_RF_REGS_BRD_DSM_STATUS_RIF_LL_ACTIVE(base) (BME_UBFX16(&BLE_RF_REGS_DSM_STATUS_REG(base), BLE_RF_REGS_DSM_STATUS_RIF_LL_ACTIVE_SHIFT, BLE_RF_REGS_DSM_STATUS_RIF_LL_ACTIVE_WIDTH))
1911 /*@}*/
1912 
1913 /*******************************************************************************
1914  * BLE_RF_REGS_BLE_AFC - Bluetooth Low Energy AFC
1915  ******************************************************************************/
1916 
1917 /*!
1918  * @brief BLE_RF_REGS_BLE_AFC - Bluetooth Low Energy AFC (RW)
1919  *
1920  * Reset value: 0x0000U
1921  */
1922 /*!
1923  * @name Constants and macros for entire BLE_RF_REGS_BLE_AFC register
1924  */
1925 /*@{*/
1926 #define BLE_RF_REGS_RD_BLE_AFC(base) (BLE_RF_REGS_BLE_AFC_REG(base))
1927 #define BLE_RF_REGS_WR_BLE_AFC(base, value) (BLE_RF_REGS_BLE_AFC_REG(base) = (value))
1928 #define BLE_RF_REGS_RMW_BLE_AFC(base, mask, value) (BLE_RF_REGS_WR_BLE_AFC(base, (BLE_RF_REGS_RD_BLE_AFC(base) & ~(mask)) | (value)))
1929 #define BLE_RF_REGS_SET_BLE_AFC(base, value) (BME_OR16(&BLE_RF_REGS_BLE_AFC_REG(base), (uint16_t)(value)))
1930 #define BLE_RF_REGS_CLR_BLE_AFC(base, value) (BME_AND16(&BLE_RF_REGS_BLE_AFC_REG(base), (uint16_t)(~(value))))
1931 #define BLE_RF_REGS_TOG_BLE_AFC(base, value) (BME_XOR16(&BLE_RF_REGS_BLE_AFC_REG(base), (uint16_t)(value)))
1932 /*@}*/
1933 
1934 /*
1935  * Constants & macros for individual BLE_RF_REGS_BLE_AFC bitfields
1936  */
1937 
1938 /*!
1939  * @name Register BLE_RF_REGS_BLE_AFC, field BLE_AFC[13:0] (RO)
1940  *
1941  * This field holds the result of the most recent BLE RX AFC (Automatic
1942  * Frequency Correction) estimation. A new AFC estimation will be generated whenever
1943  * preamble is detected. If LATCH_AFC_ON_ACCESS_MATCH=1, BLE_AFC will be latched on
1944  * access address match, and will not change until the next access address match.
1945  * Otherwise, BLE_AFC will be updated whenever preamble is detected. This is a
1946  * 14-bit, signed, two's complement value.
1947  */
1948 /*@{*/
1949 /*! @brief Read current value of the BLE_RF_REGS_BLE_AFC_BLE_AFC field. */
1950 #define BLE_RF_REGS_RD_BLE_AFC_BLE_AFC(base) ((BLE_RF_REGS_BLE_AFC_REG(base) & BLE_RF_REGS_BLE_AFC_BLE_AFC_MASK) >> BLE_RF_REGS_BLE_AFC_BLE_AFC_SHIFT)
1951 #define BLE_RF_REGS_BRD_BLE_AFC_BLE_AFC(base) (BME_UBFX16(&BLE_RF_REGS_BLE_AFC_REG(base), BLE_RF_REGS_BLE_AFC_BLE_AFC_SHIFT, BLE_RF_REGS_BLE_AFC_BLE_AFC_WIDTH))
1952 /*@}*/
1953 
1954 /*!
1955  * @name Register BLE_RF_REGS_BLE_AFC, field LATCH_AFC_ON_ACCESS_MATCH[15] (RW)
1956  *
1957  * Values:
1958  * - 0b0 - BLE_AFC[13:0] is updated whenever preamble is detected
1959  * - 0b1 - BLE_AFC[13:0] is latched at access address match, and will not be
1960  *     updated until the next access address match.
1961  */
1962 /*@{*/
1963 /*! @brief Read current value of the BLE_RF_REGS_BLE_AFC_LATCH_AFC_ON_ACCESS_MATCH field. */
1964 #define BLE_RF_REGS_RD_BLE_AFC_LATCH_AFC_ON_ACCESS_MATCH(base) ((BLE_RF_REGS_BLE_AFC_REG(base) & BLE_RF_REGS_BLE_AFC_LATCH_AFC_ON_ACCESS_MATCH_MASK) >> BLE_RF_REGS_BLE_AFC_LATCH_AFC_ON_ACCESS_MATCH_SHIFT)
1965 #define BLE_RF_REGS_BRD_BLE_AFC_LATCH_AFC_ON_ACCESS_MATCH(base) (BME_UBFX16(&BLE_RF_REGS_BLE_AFC_REG(base), BLE_RF_REGS_BLE_AFC_LATCH_AFC_ON_ACCESS_MATCH_SHIFT, BLE_RF_REGS_BLE_AFC_LATCH_AFC_ON_ACCESS_MATCH_WIDTH))
1966 
1967 /*! @brief Set the LATCH_AFC_ON_ACCESS_MATCH field to a new value. */
1968 #define BLE_RF_REGS_WR_BLE_AFC_LATCH_AFC_ON_ACCESS_MATCH(base, value) (BLE_RF_REGS_RMW_BLE_AFC(base, BLE_RF_REGS_BLE_AFC_LATCH_AFC_ON_ACCESS_MATCH_MASK, BLE_RF_REGS_BLE_AFC_LATCH_AFC_ON_ACCESS_MATCH(value)))
1969 #define BLE_RF_REGS_BWR_BLE_AFC_LATCH_AFC_ON_ACCESS_MATCH(base, value) (BME_BFI16(&BLE_RF_REGS_BLE_AFC_REG(base), ((uint16_t)(value) << BLE_RF_REGS_BLE_AFC_LATCH_AFC_ON_ACCESS_MATCH_SHIFT), BLE_RF_REGS_BLE_AFC_LATCH_AFC_ON_ACCESS_MATCH_SHIFT, BLE_RF_REGS_BLE_AFC_LATCH_AFC_ON_ACCESS_MATCH_WIDTH))
1970 /*@}*/
1971 
1972 /*******************************************************************************
1973  * BLE_RF_REGS_BLE_BSM - Bluetooth Low Energy BSM
1974  ******************************************************************************/
1975 
1976 /*!
1977  * @brief BLE_RF_REGS_BLE_BSM - Bluetooth Low Energy BSM (RW)
1978  *
1979  * Reset value: 0x0000U
1980  */
1981 /*!
1982  * @name Constants and macros for entire BLE_RF_REGS_BLE_BSM register
1983  */
1984 /*@{*/
1985 #define BLE_RF_REGS_RD_BLE_BSM(base) (BLE_RF_REGS_BLE_BSM_REG(base))
1986 #define BLE_RF_REGS_WR_BLE_BSM(base, value) (BLE_RF_REGS_BLE_BSM_REG(base) = (value))
1987 #define BLE_RF_REGS_RMW_BLE_BSM(base, mask, value) (BLE_RF_REGS_WR_BLE_BSM(base, (BLE_RF_REGS_RD_BLE_BSM(base) & ~(mask)) | (value)))
1988 #define BLE_RF_REGS_SET_BLE_BSM(base, value) (BME_OR16(&BLE_RF_REGS_BLE_BSM_REG(base), (uint16_t)(value)))
1989 #define BLE_RF_REGS_CLR_BLE_BSM(base, value) (BME_AND16(&BLE_RF_REGS_BLE_BSM_REG(base), (uint16_t)(~(value))))
1990 #define BLE_RF_REGS_TOG_BLE_BSM(base, value) (BME_XOR16(&BLE_RF_REGS_BLE_BSM_REG(base), (uint16_t)(value)))
1991 /*@}*/
1992 
1993 /*
1994  * Constants & macros for individual BLE_RF_REGS_BLE_BSM bitfields
1995  */
1996 
1997 /*!
1998  * @name Register BLE_RF_REGS_BLE_BSM, field BSM_EN_BLE[0] (RW)
1999  *
2000  * When enabled, the 3 BSM outputs (BSM_DATA, BSM_FRAME, and BSM_BLK) appear on
2001  * the BSM interface pins of the SoC. In Apache, these are alternate, muxed-GPIO
2002  * pins, so the appropriate port programming is required.
2003  *
2004  * Values:
2005  * - 0b0 - BLE Bit Streaming Mode disabled
2006  * - 0b1 - BLE Bit Streaming Mode enabled
2007  */
2008 /*@{*/
2009 /*! @brief Read current value of the BLE_RF_REGS_BLE_BSM_BSM_EN_BLE field. */
2010 #define BLE_RF_REGS_RD_BLE_BSM_BSM_EN_BLE(base) ((BLE_RF_REGS_BLE_BSM_REG(base) & BLE_RF_REGS_BLE_BSM_BSM_EN_BLE_MASK) >> BLE_RF_REGS_BLE_BSM_BSM_EN_BLE_SHIFT)
2011 #define BLE_RF_REGS_BRD_BLE_BSM_BSM_EN_BLE(base) (BME_UBFX16(&BLE_RF_REGS_BLE_BSM_REG(base), BLE_RF_REGS_BLE_BSM_BSM_EN_BLE_SHIFT, BLE_RF_REGS_BLE_BSM_BSM_EN_BLE_WIDTH))
2012 
2013 /*! @brief Set the BSM_EN_BLE field to a new value. */
2014 #define BLE_RF_REGS_WR_BLE_BSM_BSM_EN_BLE(base, value) (BLE_RF_REGS_RMW_BLE_BSM(base, BLE_RF_REGS_BLE_BSM_BSM_EN_BLE_MASK, BLE_RF_REGS_BLE_BSM_BSM_EN_BLE(value)))
2015 #define BLE_RF_REGS_BWR_BLE_BSM_BSM_EN_BLE(base, value) (BME_BFI16(&BLE_RF_REGS_BLE_BSM_REG(base), ((uint16_t)(value) << BLE_RF_REGS_BLE_BSM_BSM_EN_BLE_SHIFT), BLE_RF_REGS_BLE_BSM_BSM_EN_BLE_SHIFT, BLE_RF_REGS_BLE_BSM_BSM_EN_BLE_WIDTH))
2016 /*@}*/
2017 
2018 /*
2019  * MKW40Z4 CMP
2020  *
2021  * High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
2022  *
2023  * Registers defined in this header file:
2024  * - CMP_CR0 - CMP Control Register 0
2025  * - CMP_CR1 - CMP Control Register 1
2026  * - CMP_FPR - CMP Filter Period Register
2027  * - CMP_SCR - CMP Status and Control Register
2028  * - CMP_DACCR - DAC Control Register
2029  * - CMP_MUXCR - MUX Control Register
2030  */
2031 
2032 #define CMP_INSTANCE_COUNT (1U) /*!< Number of instances of the CMP module. */
2033 #define CMP0_IDX (0U) /*!< Instance number for CMP0. */
2034 
2035 /*******************************************************************************
2036  * CMP_CR0 - CMP Control Register 0
2037  ******************************************************************************/
2038 
2039 /*!
2040  * @brief CMP_CR0 - CMP Control Register 0 (RW)
2041  *
2042  * Reset value: 0x00U
2043  */
2044 /*!
2045  * @name Constants and macros for entire CMP_CR0 register
2046  */
2047 /*@{*/
2048 #define CMP_RD_CR0(base)         (CMP_CR0_REG(base))
2049 #define CMP_WR_CR0(base, value)  (CMP_CR0_REG(base) = (value))
2050 #define CMP_RMW_CR0(base, mask, value) (CMP_WR_CR0(base, (CMP_RD_CR0(base) & ~(mask)) | (value)))
2051 #define CMP_SET_CR0(base, value) (BME_OR8(&CMP_CR0_REG(base), (uint8_t)(value)))
2052 #define CMP_CLR_CR0(base, value) (BME_AND8(&CMP_CR0_REG(base), (uint8_t)(~(value))))
2053 #define CMP_TOG_CR0(base, value) (BME_XOR8(&CMP_CR0_REG(base), (uint8_t)(value)))
2054 /*@}*/
2055 
2056 /*
2057  * Constants & macros for individual CMP_CR0 bitfields
2058  */
2059 
2060 /*!
2061  * @name Register CMP_CR0, field HYSTCTR[1:0] (RW)
2062  *
2063  * Defines the programmable hysteresis level. The hysteresis values associated
2064  * with each level are device-specific. See the Data Sheet of the device for the
2065  * exact values.
2066  *
2067  * Values:
2068  * - 0b00 - Level 0 The hard block output has no hysteresis internally.
2069  * - 0b01 - Level 1 The hard block output has 20 mv hysteresis internally.
2070  * - 0b10 - Level 2 The hard block output has 40 mv hysteresis internally.
2071  * - 0b11 - Level 3 The hard block output has 60 mv hysteresis internally.
2072  */
2073 /*@{*/
2074 /*! @brief Read current value of the CMP_CR0_HYSTCTR field. */
2075 #define CMP_RD_CR0_HYSTCTR(base) ((CMP_CR0_REG(base) & CMP_CR0_HYSTCTR_MASK) >> CMP_CR0_HYSTCTR_SHIFT)
2076 #define CMP_BRD_CR0_HYSTCTR(base) (BME_UBFX8(&CMP_CR0_REG(base), CMP_CR0_HYSTCTR_SHIFT, CMP_CR0_HYSTCTR_WIDTH))
2077 
2078 /*! @brief Set the HYSTCTR field to a new value. */
2079 #define CMP_WR_CR0_HYSTCTR(base, value) (CMP_RMW_CR0(base, CMP_CR0_HYSTCTR_MASK, CMP_CR0_HYSTCTR(value)))
2080 #define CMP_BWR_CR0_HYSTCTR(base, value) (BME_BFI8(&CMP_CR0_REG(base), ((uint8_t)(value) << CMP_CR0_HYSTCTR_SHIFT), CMP_CR0_HYSTCTR_SHIFT, CMP_CR0_HYSTCTR_WIDTH))
2081 /*@}*/
2082 
2083 /*!
2084  * @name Register CMP_CR0, field FILTER_CNT[6:4] (RW)
2085  *
2086  * Represents the number of consecutive samples that must agree prior to the
2087  * comparator ouput filter accepting a new output state. For information regarding
2088  * filter programming and latency, see the Functional descriptionThe CMP module
2089  * can be used to compare two analog input voltages applied to INP and INM. .
2090  *
2091  * Values:
2092  * - 0b000 - Filter is disabled. SE = 0, COUT = COUTA.
2093  * - 0b001 - One sample must agree. The comparator output is simply sampled.
2094  * - 0b010 - 2 consecutive samples must agree.
2095  * - 0b011 - 3 consecutive samples must agree.
2096  * - 0b100 - 4 consecutive samples must agree.
2097  * - 0b101 - 5 consecutive samples must agree.
2098  * - 0b110 - 6 consecutive samples must agree.
2099  * - 0b111 - 7 consecutive samples must agree.
2100  */
2101 /*@{*/
2102 /*! @brief Read current value of the CMP_CR0_FILTER_CNT field. */
2103 #define CMP_RD_CR0_FILTER_CNT(base) ((CMP_CR0_REG(base) & CMP_CR0_FILTER_CNT_MASK) >> CMP_CR0_FILTER_CNT_SHIFT)
2104 #define CMP_BRD_CR0_FILTER_CNT(base) (BME_UBFX8(&CMP_CR0_REG(base), CMP_CR0_FILTER_CNT_SHIFT, CMP_CR0_FILTER_CNT_WIDTH))
2105 
2106 /*! @brief Set the FILTER_CNT field to a new value. */
2107 #define CMP_WR_CR0_FILTER_CNT(base, value) (CMP_RMW_CR0(base, CMP_CR0_FILTER_CNT_MASK, CMP_CR0_FILTER_CNT(value)))
2108 #define CMP_BWR_CR0_FILTER_CNT(base, value) (BME_BFI8(&CMP_CR0_REG(base), ((uint8_t)(value) << CMP_CR0_FILTER_CNT_SHIFT), CMP_CR0_FILTER_CNT_SHIFT, CMP_CR0_FILTER_CNT_WIDTH))
2109 /*@}*/
2110 
2111 /*******************************************************************************
2112  * CMP_CR1 - CMP Control Register 1
2113  ******************************************************************************/
2114 
2115 /*!
2116  * @brief CMP_CR1 - CMP Control Register 1 (RW)
2117  *
2118  * Reset value: 0x00U
2119  */
2120 /*!
2121  * @name Constants and macros for entire CMP_CR1 register
2122  */
2123 /*@{*/
2124 #define CMP_RD_CR1(base)         (CMP_CR1_REG(base))
2125 #define CMP_WR_CR1(base, value)  (CMP_CR1_REG(base) = (value))
2126 #define CMP_RMW_CR1(base, mask, value) (CMP_WR_CR1(base, (CMP_RD_CR1(base) & ~(mask)) | (value)))
2127 #define CMP_SET_CR1(base, value) (BME_OR8(&CMP_CR1_REG(base), (uint8_t)(value)))
2128 #define CMP_CLR_CR1(base, value) (BME_AND8(&CMP_CR1_REG(base), (uint8_t)(~(value))))
2129 #define CMP_TOG_CR1(base, value) (BME_XOR8(&CMP_CR1_REG(base), (uint8_t)(value)))
2130 /*@}*/
2131 
2132 /*
2133  * Constants & macros for individual CMP_CR1 bitfields
2134  */
2135 
2136 /*!
2137  * @name Register CMP_CR1, field EN[0] (RW)
2138  *
2139  * Enables the Analog Comparator module. When the module is not enabled, it
2140  * remains in the off state, and consumes no power. When the user selects the same
2141  * input from analog mux to the positive and negative port, the comparator is
2142  * disabled automatically.
2143  *
2144  * Values:
2145  * - 0b0 - Analog Comparator is disabled.
2146  * - 0b1 - Analog Comparator is enabled.
2147  */
2148 /*@{*/
2149 /*! @brief Read current value of the CMP_CR1_EN field. */
2150 #define CMP_RD_CR1_EN(base)  ((CMP_CR1_REG(base) & CMP_CR1_EN_MASK) >> CMP_CR1_EN_SHIFT)
2151 #define CMP_BRD_CR1_EN(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_EN_SHIFT, CMP_CR1_EN_WIDTH))
2152 
2153 /*! @brief Set the EN field to a new value. */
2154 #define CMP_WR_CR1_EN(base, value) (CMP_RMW_CR1(base, CMP_CR1_EN_MASK, CMP_CR1_EN(value)))
2155 #define CMP_BWR_CR1_EN(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_EN_SHIFT), CMP_CR1_EN_SHIFT, CMP_CR1_EN_WIDTH))
2156 /*@}*/
2157 
2158 /*!
2159  * @name Register CMP_CR1, field OPE[1] (RW)
2160  *
2161  * Operation of the OPE bit varies, depending on how it is encapsulated within
2162  * the system. There are two cases.
2163  *
2164  * Values:
2165  * - 0b0 - CMPO is not available on the associated CMPO output pin. For devices
2166  *     that use explicit muxing control to I/O pin functions (DSC and non-Flexis
2167  *     ColdFire devices): If the comparator does not own the pin, this field has
2168  *     no effect.
2169  * - 0b1 - CMPO is available on the associated CMPO output pin. For devices that
2170  *     use explicit muxing control to I/O pin functions (DSC and non-Flexis
2171  *     ColdFire devices): The comparator output (CMPO) is driven out on the
2172  *     associated CMPO output pin if the comparator owns the pin. If the comparator does
2173  *     not own the field, this bit has no effect.
2174  */
2175 /*@{*/
2176 /*! @brief Read current value of the CMP_CR1_OPE field. */
2177 #define CMP_RD_CR1_OPE(base) ((CMP_CR1_REG(base) & CMP_CR1_OPE_MASK) >> CMP_CR1_OPE_SHIFT)
2178 #define CMP_BRD_CR1_OPE(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_OPE_SHIFT, CMP_CR1_OPE_WIDTH))
2179 
2180 /*! @brief Set the OPE field to a new value. */
2181 #define CMP_WR_CR1_OPE(base, value) (CMP_RMW_CR1(base, CMP_CR1_OPE_MASK, CMP_CR1_OPE(value)))
2182 #define CMP_BWR_CR1_OPE(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_OPE_SHIFT), CMP_CR1_OPE_SHIFT, CMP_CR1_OPE_WIDTH))
2183 /*@}*/
2184 
2185 /*!
2186  * @name Register CMP_CR1, field COS[2] (RW)
2187  *
2188  * Values:
2189  * - 0b0 - Set the filtered comparator output (CMPO) to equal COUT.
2190  * - 0b1 - Set the unfiltered comparator output (CMPO) to equal COUTA.
2191  */
2192 /*@{*/
2193 /*! @brief Read current value of the CMP_CR1_COS field. */
2194 #define CMP_RD_CR1_COS(base) ((CMP_CR1_REG(base) & CMP_CR1_COS_MASK) >> CMP_CR1_COS_SHIFT)
2195 #define CMP_BRD_CR1_COS(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_COS_SHIFT, CMP_CR1_COS_WIDTH))
2196 
2197 /*! @brief Set the COS field to a new value. */
2198 #define CMP_WR_CR1_COS(base, value) (CMP_RMW_CR1(base, CMP_CR1_COS_MASK, CMP_CR1_COS(value)))
2199 #define CMP_BWR_CR1_COS(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_COS_SHIFT), CMP_CR1_COS_SHIFT, CMP_CR1_COS_WIDTH))
2200 /*@}*/
2201 
2202 /*!
2203  * @name Register CMP_CR1, field INV[3] (RW)
2204  *
2205  * Allows selection of the polarity of the analog comparator function. It is
2206  * also driven to the COUT output, on both the device pin and as SCR[COUT], when
2207  * OPE=0.
2208  *
2209  * Values:
2210  * - 0b0 - Does not invert the comparator output.
2211  * - 0b1 - Inverts the comparator output.
2212  */
2213 /*@{*/
2214 /*! @brief Read current value of the CMP_CR1_INV field. */
2215 #define CMP_RD_CR1_INV(base) ((CMP_CR1_REG(base) & CMP_CR1_INV_MASK) >> CMP_CR1_INV_SHIFT)
2216 #define CMP_BRD_CR1_INV(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_INV_SHIFT, CMP_CR1_INV_WIDTH))
2217 
2218 /*! @brief Set the INV field to a new value. */
2219 #define CMP_WR_CR1_INV(base, value) (CMP_RMW_CR1(base, CMP_CR1_INV_MASK, CMP_CR1_INV(value)))
2220 #define CMP_BWR_CR1_INV(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_INV_SHIFT), CMP_CR1_INV_SHIFT, CMP_CR1_INV_WIDTH))
2221 /*@}*/
2222 
2223 /*!
2224  * @name Register CMP_CR1, field PMODE[4] (RW)
2225  *
2226  * See the electrical specifications table in the device Data Sheet for details.
2227  *
2228  * Values:
2229  * - 0b0 - Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower
2230  *     output propagation delay and lower current consumption.
2231  * - 0b1 - High-Speed (HS) Comparison mode selected. In this mode, CMP has
2232  *     faster output propagation delay and higher current consumption.
2233  */
2234 /*@{*/
2235 /*! @brief Read current value of the CMP_CR1_PMODE field. */
2236 #define CMP_RD_CR1_PMODE(base) ((CMP_CR1_REG(base) & CMP_CR1_PMODE_MASK) >> CMP_CR1_PMODE_SHIFT)
2237 #define CMP_BRD_CR1_PMODE(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_PMODE_SHIFT, CMP_CR1_PMODE_WIDTH))
2238 
2239 /*! @brief Set the PMODE field to a new value. */
2240 #define CMP_WR_CR1_PMODE(base, value) (CMP_RMW_CR1(base, CMP_CR1_PMODE_MASK, CMP_CR1_PMODE(value)))
2241 #define CMP_BWR_CR1_PMODE(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_PMODE_SHIFT), CMP_CR1_PMODE_SHIFT, CMP_CR1_PMODE_WIDTH))
2242 /*@}*/
2243 
2244 /*!
2245  * @name Register CMP_CR1, field TRIGM[5] (RW)
2246  *
2247  * CMP and DAC are configured to CMP Trigger mode when CMP_CR1[TRIGM] is set to
2248  * 1. In addition, the CMP should be enabled. If the DAC is to be used as a
2249  * reference to the CMP, it should also be enabled. CMP Trigger mode depends on an
2250  * external timer resource to periodically enable the CMP and 6-bit DAC in order to
2251  * generate a triggered compare. Upon setting TRIGM, the CMP and DAC are placed
2252  * in a standby state until an external timer resource trigger is received. See
2253  * the chip configuration for details about the external timer resource.
2254  *
2255  * Values:
2256  * - 0b0 - Trigger mode is disabled.
2257  * - 0b1 - Trigger mode is enabled.
2258  */
2259 /*@{*/
2260 /*! @brief Read current value of the CMP_CR1_TRIGM field. */
2261 #define CMP_RD_CR1_TRIGM(base) ((CMP_CR1_REG(base) & CMP_CR1_TRIGM_MASK) >> CMP_CR1_TRIGM_SHIFT)
2262 #define CMP_BRD_CR1_TRIGM(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_TRIGM_SHIFT, CMP_CR1_TRIGM_WIDTH))
2263 
2264 /*! @brief Set the TRIGM field to a new value. */
2265 #define CMP_WR_CR1_TRIGM(base, value) (CMP_RMW_CR1(base, CMP_CR1_TRIGM_MASK, CMP_CR1_TRIGM(value)))
2266 #define CMP_BWR_CR1_TRIGM(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_TRIGM_SHIFT), CMP_CR1_TRIGM_SHIFT, CMP_CR1_TRIGM_WIDTH))
2267 /*@}*/
2268 
2269 /*!
2270  * @name Register CMP_CR1, field WE[6] (RW)
2271  *
2272  * The CMP does not support window compare function and a 0 must always be
2273  * written to WE.
2274  *
2275  * Values:
2276  * - 0b0 - Windowing mode is not selected.
2277  * - 0b1 - Windowing mode is selected.
2278  */
2279 /*@{*/
2280 /*! @brief Read current value of the CMP_CR1_WE field. */
2281 #define CMP_RD_CR1_WE(base)  ((CMP_CR1_REG(base) & CMP_CR1_WE_MASK) >> CMP_CR1_WE_SHIFT)
2282 #define CMP_BRD_CR1_WE(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_WE_SHIFT, CMP_CR1_WE_WIDTH))
2283 
2284 /*! @brief Set the WE field to a new value. */
2285 #define CMP_WR_CR1_WE(base, value) (CMP_RMW_CR1(base, CMP_CR1_WE_MASK, CMP_CR1_WE(value)))
2286 #define CMP_BWR_CR1_WE(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_WE_SHIFT), CMP_CR1_WE_SHIFT, CMP_CR1_WE_WIDTH))
2287 /*@}*/
2288 
2289 /*!
2290  * @name Register CMP_CR1, field SE[7] (RW)
2291  *
2292  * SE must be clear to 0 and usage of sample operation is limited to a divided
2293  * version of the bus clock.
2294  *
2295  * Values:
2296  * - 0b0 - Sampling mode is not selected.
2297  * - 0b1 - Sampling mode is selected.
2298  */
2299 /*@{*/
2300 /*! @brief Read current value of the CMP_CR1_SE field. */
2301 #define CMP_RD_CR1_SE(base)  ((CMP_CR1_REG(base) & CMP_CR1_SE_MASK) >> CMP_CR1_SE_SHIFT)
2302 #define CMP_BRD_CR1_SE(base) (BME_UBFX8(&CMP_CR1_REG(base), CMP_CR1_SE_SHIFT, CMP_CR1_SE_WIDTH))
2303 
2304 /*! @brief Set the SE field to a new value. */
2305 #define CMP_WR_CR1_SE(base, value) (CMP_RMW_CR1(base, CMP_CR1_SE_MASK, CMP_CR1_SE(value)))
2306 #define CMP_BWR_CR1_SE(base, value) (BME_BFI8(&CMP_CR1_REG(base), ((uint8_t)(value) << CMP_CR1_SE_SHIFT), CMP_CR1_SE_SHIFT, CMP_CR1_SE_WIDTH))
2307 /*@}*/
2308 
2309 /*******************************************************************************
2310  * CMP_FPR - CMP Filter Period Register
2311  ******************************************************************************/
2312 
2313 /*!
2314  * @brief CMP_FPR - CMP Filter Period Register (RW)
2315  *
2316  * Reset value: 0x00U
2317  */
2318 /*!
2319  * @name Constants and macros for entire CMP_FPR register
2320  */
2321 /*@{*/
2322 #define CMP_RD_FPR(base)         (CMP_FPR_REG(base))
2323 #define CMP_WR_FPR(base, value)  (CMP_FPR_REG(base) = (value))
2324 #define CMP_RMW_FPR(base, mask, value) (CMP_WR_FPR(base, (CMP_RD_FPR(base) & ~(mask)) | (value)))
2325 #define CMP_SET_FPR(base, value) (BME_OR8(&CMP_FPR_REG(base), (uint8_t)(value)))
2326 #define CMP_CLR_FPR(base, value) (BME_AND8(&CMP_FPR_REG(base), (uint8_t)(~(value))))
2327 #define CMP_TOG_FPR(base, value) (BME_XOR8(&CMP_FPR_REG(base), (uint8_t)(value)))
2328 /*@}*/
2329 
2330 /*******************************************************************************
2331  * CMP_SCR - CMP Status and Control Register
2332  ******************************************************************************/
2333 
2334 /*!
2335  * @brief CMP_SCR - CMP Status and Control Register (RW)
2336  *
2337  * Reset value: 0x00U
2338  */
2339 /*!
2340  * @name Constants and macros for entire CMP_SCR register
2341  */
2342 /*@{*/
2343 #define CMP_RD_SCR(base)         (CMP_SCR_REG(base))
2344 #define CMP_WR_SCR(base, value)  (CMP_SCR_REG(base) = (value))
2345 #define CMP_RMW_SCR(base, mask, value) (CMP_WR_SCR(base, (CMP_RD_SCR(base) & ~(mask)) | (value)))
2346 #define CMP_SET_SCR(base, value) (BME_OR8(&CMP_SCR_REG(base), (uint8_t)(value)))
2347 #define CMP_CLR_SCR(base, value) (BME_AND8(&CMP_SCR_REG(base), (uint8_t)(~(value))))
2348 #define CMP_TOG_SCR(base, value) (BME_XOR8(&CMP_SCR_REG(base), (uint8_t)(value)))
2349 /*@}*/
2350 
2351 /*
2352  * Constants & macros for individual CMP_SCR bitfields
2353  */
2354 
2355 /*!
2356  * @name Register CMP_SCR, field COUT[0] (RO)
2357  *
2358  * Returns the current value of the Analog Comparator output, when read. The
2359  * field is reset to 0 and will read as CR1[INV] when the Analog Comparator module
2360  * is disabled, that is, when CR1[EN] = 0. Writes to this field are ignored.
2361  */
2362 /*@{*/
2363 /*! @brief Read current value of the CMP_SCR_COUT field. */
2364 #define CMP_RD_SCR_COUT(base) ((CMP_SCR_REG(base) & CMP_SCR_COUT_MASK) >> CMP_SCR_COUT_SHIFT)
2365 #define CMP_BRD_SCR_COUT(base) (BME_UBFX8(&CMP_SCR_REG(base), CMP_SCR_COUT_SHIFT, CMP_SCR_COUT_WIDTH))
2366 /*@}*/
2367 
2368 /*!
2369  * @name Register CMP_SCR, field CFF[1] (W1C)
2370  *
2371  * Detects a falling-edge on COUT, when set, during normal operation. CFF is
2372  * cleared by writing 1 to it. During Stop modes, CFF is level sensitive .
2373  *
2374  * Values:
2375  * - 0b0 - Falling-edge on COUT has not been detected.
2376  * - 0b1 - Falling-edge on COUT has occurred.
2377  */
2378 /*@{*/
2379 /*! @brief Read current value of the CMP_SCR_CFF field. */
2380 #define CMP_RD_SCR_CFF(base) ((CMP_SCR_REG(base) & CMP_SCR_CFF_MASK) >> CMP_SCR_CFF_SHIFT)
2381 #define CMP_BRD_SCR_CFF(base) (BME_UBFX8(&CMP_SCR_REG(base), CMP_SCR_CFF_SHIFT, CMP_SCR_CFF_WIDTH))
2382 
2383 /*! @brief Set the CFF field to a new value. */
2384 #define CMP_WR_SCR_CFF(base, value) (CMP_RMW_SCR(base, (CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_CFF(value)))
2385 #define CMP_BWR_SCR_CFF(base, value) (BME_BFI8(&CMP_SCR_REG(base), ((uint8_t)(value) << CMP_SCR_CFF_SHIFT), CMP_SCR_CFF_SHIFT, CMP_SCR_CFF_WIDTH))
2386 /*@}*/
2387 
2388 /*!
2389  * @name Register CMP_SCR, field CFR[2] (W1C)
2390  *
2391  * Detects a rising-edge on COUT, when set, during normal operation. CFR is
2392  * cleared by writing 1 to it. During Stop modes, CFR is level sensitive .
2393  *
2394  * Values:
2395  * - 0b0 - Rising-edge on COUT has not been detected.
2396  * - 0b1 - Rising-edge on COUT has occurred.
2397  */
2398 /*@{*/
2399 /*! @brief Read current value of the CMP_SCR_CFR field. */
2400 #define CMP_RD_SCR_CFR(base) ((CMP_SCR_REG(base) & CMP_SCR_CFR_MASK) >> CMP_SCR_CFR_SHIFT)
2401 #define CMP_BRD_SCR_CFR(base) (BME_UBFX8(&CMP_SCR_REG(base), CMP_SCR_CFR_SHIFT, CMP_SCR_CFR_WIDTH))
2402 
2403 /*! @brief Set the CFR field to a new value. */
2404 #define CMP_WR_SCR_CFR(base, value) (CMP_RMW_SCR(base, (CMP_SCR_CFR_MASK | CMP_SCR_CFF_MASK), CMP_SCR_CFR(value)))
2405 #define CMP_BWR_SCR_CFR(base, value) (BME_BFI8(&CMP_SCR_REG(base), ((uint8_t)(value) << CMP_SCR_CFR_SHIFT), CMP_SCR_CFR_SHIFT, CMP_SCR_CFR_WIDTH))
2406 /*@}*/
2407 
2408 /*!
2409  * @name Register CMP_SCR, field IEF[3] (RW)
2410  *
2411  * Enables the CFF interrupt from the CMP. When this field is set, an interrupt
2412  * will be asserted when CFF is set.
2413  *
2414  * Values:
2415  * - 0b0 - Interrupt is disabled.
2416  * - 0b1 - Interrupt is enabled.
2417  */
2418 /*@{*/
2419 /*! @brief Read current value of the CMP_SCR_IEF field. */
2420 #define CMP_RD_SCR_IEF(base) ((CMP_SCR_REG(base) & CMP_SCR_IEF_MASK) >> CMP_SCR_IEF_SHIFT)
2421 #define CMP_BRD_SCR_IEF(base) (BME_UBFX8(&CMP_SCR_REG(base), CMP_SCR_IEF_SHIFT, CMP_SCR_IEF_WIDTH))
2422 
2423 /*! @brief Set the IEF field to a new value. */
2424 #define CMP_WR_SCR_IEF(base, value) (CMP_RMW_SCR(base, (CMP_SCR_IEF_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_IEF(value)))
2425 #define CMP_BWR_SCR_IEF(base, value) (BME_BFI8(&CMP_SCR_REG(base), ((uint8_t)(value) << CMP_SCR_IEF_SHIFT), CMP_SCR_IEF_SHIFT, CMP_SCR_IEF_WIDTH))
2426 /*@}*/
2427 
2428 /*!
2429  * @name Register CMP_SCR, field IER[4] (RW)
2430  *
2431  * Enables the CFR interrupt from the CMP. When this field is set, an interrupt
2432  * will be asserted when CFR is set.
2433  *
2434  * Values:
2435  * - 0b0 - Interrupt is disabled.
2436  * - 0b1 - Interrupt is enabled.
2437  */
2438 /*@{*/
2439 /*! @brief Read current value of the CMP_SCR_IER field. */
2440 #define CMP_RD_SCR_IER(base) ((CMP_SCR_REG(base) & CMP_SCR_IER_MASK) >> CMP_SCR_IER_SHIFT)
2441 #define CMP_BRD_SCR_IER(base) (BME_UBFX8(&CMP_SCR_REG(base), CMP_SCR_IER_SHIFT, CMP_SCR_IER_WIDTH))
2442 
2443 /*! @brief Set the IER field to a new value. */
2444 #define CMP_WR_SCR_IER(base, value) (CMP_RMW_SCR(base, (CMP_SCR_IER_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_IER(value)))
2445 #define CMP_BWR_SCR_IER(base, value) (BME_BFI8(&CMP_SCR_REG(base), ((uint8_t)(value) << CMP_SCR_IER_SHIFT), CMP_SCR_IER_SHIFT, CMP_SCR_IER_WIDTH))
2446 /*@}*/
2447 
2448 /*!
2449  * @name Register CMP_SCR, field DMAEN[6] (RW)
2450  *
2451  * Enables the DMA transfer triggered from the CMP module. When this field is
2452  * set, a DMA request is asserted when CFR or CFF is set.
2453  *
2454  * Values:
2455  * - 0b0 - DMA is disabled.
2456  * - 0b1 - DMA is enabled.
2457  */
2458 /*@{*/
2459 /*! @brief Read current value of the CMP_SCR_DMAEN field. */
2460 #define CMP_RD_SCR_DMAEN(base) ((CMP_SCR_REG(base) & CMP_SCR_DMAEN_MASK) >> CMP_SCR_DMAEN_SHIFT)
2461 #define CMP_BRD_SCR_DMAEN(base) (BME_UBFX8(&CMP_SCR_REG(base), CMP_SCR_DMAEN_SHIFT, CMP_SCR_DMAEN_WIDTH))
2462 
2463 /*! @brief Set the DMAEN field to a new value. */
2464 #define CMP_WR_SCR_DMAEN(base, value) (CMP_RMW_SCR(base, (CMP_SCR_DMAEN_MASK | CMP_SCR_CFF_MASK | CMP_SCR_CFR_MASK), CMP_SCR_DMAEN(value)))
2465 #define CMP_BWR_SCR_DMAEN(base, value) (BME_BFI8(&CMP_SCR_REG(base), ((uint8_t)(value) << CMP_SCR_DMAEN_SHIFT), CMP_SCR_DMAEN_SHIFT, CMP_SCR_DMAEN_WIDTH))
2466 /*@}*/
2467 
2468 /*******************************************************************************
2469  * CMP_DACCR - DAC Control Register
2470  ******************************************************************************/
2471 
2472 /*!
2473  * @brief CMP_DACCR - DAC Control Register (RW)
2474  *
2475  * Reset value: 0x00U
2476  */
2477 /*!
2478  * @name Constants and macros for entire CMP_DACCR register
2479  */
2480 /*@{*/
2481 #define CMP_RD_DACCR(base)       (CMP_DACCR_REG(base))
2482 #define CMP_WR_DACCR(base, value) (CMP_DACCR_REG(base) = (value))
2483 #define CMP_RMW_DACCR(base, mask, value) (CMP_WR_DACCR(base, (CMP_RD_DACCR(base) & ~(mask)) | (value)))
2484 #define CMP_SET_DACCR(base, value) (BME_OR8(&CMP_DACCR_REG(base), (uint8_t)(value)))
2485 #define CMP_CLR_DACCR(base, value) (BME_AND8(&CMP_DACCR_REG(base), (uint8_t)(~(value))))
2486 #define CMP_TOG_DACCR(base, value) (BME_XOR8(&CMP_DACCR_REG(base), (uint8_t)(value)))
2487 /*@}*/
2488 
2489 /*
2490  * Constants & macros for individual CMP_DACCR bitfields
2491  */
2492 
2493 /*!
2494  * @name Register CMP_DACCR, field VOSEL[5:0] (RW)
2495  *
2496  * Selects an output voltage from one of 64 distinct levels. DACO = (V in /64) *
2497  * (VOSEL[5:0] + 1) , so the DACO range is from V in /64 to V in .
2498  */
2499 /*@{*/
2500 /*! @brief Read current value of the CMP_DACCR_VOSEL field. */
2501 #define CMP_RD_DACCR_VOSEL(base) ((CMP_DACCR_REG(base) & CMP_DACCR_VOSEL_MASK) >> CMP_DACCR_VOSEL_SHIFT)
2502 #define CMP_BRD_DACCR_VOSEL(base) (BME_UBFX8(&CMP_DACCR_REG(base), CMP_DACCR_VOSEL_SHIFT, CMP_DACCR_VOSEL_WIDTH))
2503 
2504 /*! @brief Set the VOSEL field to a new value. */
2505 #define CMP_WR_DACCR_VOSEL(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_VOSEL_MASK, CMP_DACCR_VOSEL(value)))
2506 #define CMP_BWR_DACCR_VOSEL(base, value) (BME_BFI8(&CMP_DACCR_REG(base), ((uint8_t)(value) << CMP_DACCR_VOSEL_SHIFT), CMP_DACCR_VOSEL_SHIFT, CMP_DACCR_VOSEL_WIDTH))
2507 /*@}*/
2508 
2509 /*!
2510  * @name Register CMP_DACCR, field VRSEL[6] (RW)
2511  *
2512  * Values:
2513  * - 0b0 - Vin1 is selected as resistor ladder network supply reference.
2514  * - 0b1 - Vin2 is selected as resistor ladder network supply reference.
2515  */
2516 /*@{*/
2517 /*! @brief Read current value of the CMP_DACCR_VRSEL field. */
2518 #define CMP_RD_DACCR_VRSEL(base) ((CMP_DACCR_REG(base) & CMP_DACCR_VRSEL_MASK) >> CMP_DACCR_VRSEL_SHIFT)
2519 #define CMP_BRD_DACCR_VRSEL(base) (BME_UBFX8(&CMP_DACCR_REG(base), CMP_DACCR_VRSEL_SHIFT, CMP_DACCR_VRSEL_WIDTH))
2520 
2521 /*! @brief Set the VRSEL field to a new value. */
2522 #define CMP_WR_DACCR_VRSEL(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_VRSEL_MASK, CMP_DACCR_VRSEL(value)))
2523 #define CMP_BWR_DACCR_VRSEL(base, value) (BME_BFI8(&CMP_DACCR_REG(base), ((uint8_t)(value) << CMP_DACCR_VRSEL_SHIFT), CMP_DACCR_VRSEL_SHIFT, CMP_DACCR_VRSEL_WIDTH))
2524 /*@}*/
2525 
2526 /*!
2527  * @name Register CMP_DACCR, field DACEN[7] (RW)
2528  *
2529  * Enables the DAC. When the DAC is disabled, it is powered down to conserve
2530  * power.
2531  *
2532  * Values:
2533  * - 0b0 - DAC is disabled.
2534  * - 0b1 - DAC is enabled.
2535  */
2536 /*@{*/
2537 /*! @brief Read current value of the CMP_DACCR_DACEN field. */
2538 #define CMP_RD_DACCR_DACEN(base) ((CMP_DACCR_REG(base) & CMP_DACCR_DACEN_MASK) >> CMP_DACCR_DACEN_SHIFT)
2539 #define CMP_BRD_DACCR_DACEN(base) (BME_UBFX8(&CMP_DACCR_REG(base), CMP_DACCR_DACEN_SHIFT, CMP_DACCR_DACEN_WIDTH))
2540 
2541 /*! @brief Set the DACEN field to a new value. */
2542 #define CMP_WR_DACCR_DACEN(base, value) (CMP_RMW_DACCR(base, CMP_DACCR_DACEN_MASK, CMP_DACCR_DACEN(value)))
2543 #define CMP_BWR_DACCR_DACEN(base, value) (BME_BFI8(&CMP_DACCR_REG(base), ((uint8_t)(value) << CMP_DACCR_DACEN_SHIFT), CMP_DACCR_DACEN_SHIFT, CMP_DACCR_DACEN_WIDTH))
2544 /*@}*/
2545 
2546 /*******************************************************************************
2547  * CMP_MUXCR - MUX Control Register
2548  ******************************************************************************/
2549 
2550 /*!
2551  * @brief CMP_MUXCR - MUX Control Register (RW)
2552  *
2553  * Reset value: 0x00U
2554  */
2555 /*!
2556  * @name Constants and macros for entire CMP_MUXCR register
2557  */
2558 /*@{*/
2559 #define CMP_RD_MUXCR(base)       (CMP_MUXCR_REG(base))
2560 #define CMP_WR_MUXCR(base, value) (CMP_MUXCR_REG(base) = (value))
2561 #define CMP_RMW_MUXCR(base, mask, value) (CMP_WR_MUXCR(base, (CMP_RD_MUXCR(base) & ~(mask)) | (value)))
2562 #define CMP_SET_MUXCR(base, value) (BME_OR8(&CMP_MUXCR_REG(base), (uint8_t)(value)))
2563 #define CMP_CLR_MUXCR(base, value) (BME_AND8(&CMP_MUXCR_REG(base), (uint8_t)(~(value))))
2564 #define CMP_TOG_MUXCR(base, value) (BME_XOR8(&CMP_MUXCR_REG(base), (uint8_t)(value)))
2565 /*@}*/
2566 
2567 /*
2568  * Constants & macros for individual CMP_MUXCR bitfields
2569  */
2570 
2571 /*!
2572  * @name Register CMP_MUXCR, field MSEL[2:0] (RW)
2573  *
2574  * Determines which input is selected for the minus input of the comparator. For
2575  * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
2576  * operation selects the same input for both muxes, the comparator automatically
2577  * shuts down to prevent itself from becoming a noise generator.
2578  *
2579  * Values:
2580  * - 0b000 - IN0
2581  * - 0b001 - IN1
2582  * - 0b010 - IN2
2583  * - 0b011 - IN3
2584  * - 0b100 - IN4
2585  * - 0b101 - IN5
2586  * - 0b110 - IN6
2587  * - 0b111 - IN7
2588  */
2589 /*@{*/
2590 /*! @brief Read current value of the CMP_MUXCR_MSEL field. */
2591 #define CMP_RD_MUXCR_MSEL(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_MSEL_MASK) >> CMP_MUXCR_MSEL_SHIFT)
2592 #define CMP_BRD_MUXCR_MSEL(base) (BME_UBFX8(&CMP_MUXCR_REG(base), CMP_MUXCR_MSEL_SHIFT, CMP_MUXCR_MSEL_WIDTH))
2593 
2594 /*! @brief Set the MSEL field to a new value. */
2595 #define CMP_WR_MUXCR_MSEL(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_MSEL_MASK, CMP_MUXCR_MSEL(value)))
2596 #define CMP_BWR_MUXCR_MSEL(base, value) (BME_BFI8(&CMP_MUXCR_REG(base), ((uint8_t)(value) << CMP_MUXCR_MSEL_SHIFT), CMP_MUXCR_MSEL_SHIFT, CMP_MUXCR_MSEL_WIDTH))
2597 /*@}*/
2598 
2599 /*!
2600  * @name Register CMP_MUXCR, field PSEL[5:3] (RW)
2601  *
2602  * Determines which input is selected for the plus input of the comparator. For
2603  * INx inputs, see CMP, DAC, and ANMUX block diagrams. When an inappropriate
2604  * operation selects the same input for both muxes, the comparator automatically
2605  * shuts down to prevent itself from becoming a noise generator.
2606  *
2607  * Values:
2608  * - 0b000 - IN0
2609  * - 0b001 - IN1
2610  * - 0b010 - IN2
2611  * - 0b011 - IN3
2612  * - 0b100 - IN4
2613  * - 0b101 - IN5
2614  * - 0b110 - IN6
2615  * - 0b111 - IN7
2616  */
2617 /*@{*/
2618 /*! @brief Read current value of the CMP_MUXCR_PSEL field. */
2619 #define CMP_RD_MUXCR_PSEL(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_PSEL_MASK) >> CMP_MUXCR_PSEL_SHIFT)
2620 #define CMP_BRD_MUXCR_PSEL(base) (BME_UBFX8(&CMP_MUXCR_REG(base), CMP_MUXCR_PSEL_SHIFT, CMP_MUXCR_PSEL_WIDTH))
2621 
2622 /*! @brief Set the PSEL field to a new value. */
2623 #define CMP_WR_MUXCR_PSEL(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_PSEL_MASK, CMP_MUXCR_PSEL(value)))
2624 #define CMP_BWR_MUXCR_PSEL(base, value) (BME_BFI8(&CMP_MUXCR_REG(base), ((uint8_t)(value) << CMP_MUXCR_PSEL_SHIFT), CMP_MUXCR_PSEL_SHIFT, CMP_MUXCR_PSEL_WIDTH))
2625 /*@}*/
2626 
2627 /*!
2628  * @name Register CMP_MUXCR, field PSTM[7] (RW)
2629  *
2630  * This bit is used to enable to MUX pass through mode. Pass through mode is
2631  * always available but for some devices this feature must be always disabled due to
2632  * the lack of package pins.
2633  *
2634  * Values:
2635  * - 0b0 - Pass Through Mode is disabled.
2636  * - 0b1 - Pass Through Mode is enabled.
2637  */
2638 /*@{*/
2639 /*! @brief Read current value of the CMP_MUXCR_PSTM field. */
2640 #define CMP_RD_MUXCR_PSTM(base) ((CMP_MUXCR_REG(base) & CMP_MUXCR_PSTM_MASK) >> CMP_MUXCR_PSTM_SHIFT)
2641 #define CMP_BRD_MUXCR_PSTM(base) (BME_UBFX8(&CMP_MUXCR_REG(base), CMP_MUXCR_PSTM_SHIFT, CMP_MUXCR_PSTM_WIDTH))
2642 
2643 /*! @brief Set the PSTM field to a new value. */
2644 #define CMP_WR_MUXCR_PSTM(base, value) (CMP_RMW_MUXCR(base, CMP_MUXCR_PSTM_MASK, CMP_MUXCR_PSTM(value)))
2645 #define CMP_BWR_MUXCR_PSTM(base, value) (BME_BFI8(&CMP_MUXCR_REG(base), ((uint8_t)(value) << CMP_MUXCR_PSTM_SHIFT), CMP_MUXCR_PSTM_SHIFT, CMP_MUXCR_PSTM_WIDTH))
2646 /*@}*/
2647 
2648 /*
2649  * MKW40Z4 CMT
2650  *
2651  * Carrier Modulator Transmitter
2652  *
2653  * Registers defined in this header file:
2654  * - CMT_CGH1 - CMT Carrier Generator High Data Register 1
2655  * - CMT_CGL1 - CMT Carrier Generator Low Data Register 1
2656  * - CMT_CGH2 - CMT Carrier Generator High Data Register 2
2657  * - CMT_CGL2 - CMT Carrier Generator Low Data Register 2
2658  * - CMT_OC - CMT Output Control Register
2659  * - CMT_MSC - CMT Modulator Status and Control Register
2660  * - CMT_CMD1 - CMT Modulator Data Register Mark High
2661  * - CMT_CMD2 - CMT Modulator Data Register Mark Low
2662  * - CMT_CMD3 - CMT Modulator Data Register Space High
2663  * - CMT_CMD4 - CMT Modulator Data Register Space Low
2664  * - CMT_PPS - CMT Primary Prescaler Register
2665  * - CMT_DMA - CMT Direct Memory Access Register
2666  */
2667 
2668 #define CMT_INSTANCE_COUNT (1U) /*!< Number of instances of the CMT module. */
2669 #define CMT_IDX (0U) /*!< Instance number for CMT. */
2670 
2671 /*******************************************************************************
2672  * CMT_CGH1 - CMT Carrier Generator High Data Register 1
2673  ******************************************************************************/
2674 
2675 /*!
2676  * @brief CMT_CGH1 - CMT Carrier Generator High Data Register 1 (RW)
2677  *
2678  * Reset value: 0x00U
2679  *
2680  * This data register contains the primary high value for generating the carrier
2681  * output.
2682  */
2683 /*!
2684  * @name Constants and macros for entire CMT_CGH1 register
2685  */
2686 /*@{*/
2687 #define CMT_RD_CGH1(base)        (CMT_CGH1_REG(base))
2688 #define CMT_WR_CGH1(base, value) (CMT_CGH1_REG(base) = (value))
2689 #define CMT_RMW_CGH1(base, mask, value) (CMT_WR_CGH1(base, (CMT_RD_CGH1(base) & ~(mask)) | (value)))
2690 #define CMT_SET_CGH1(base, value) (BME_OR8(&CMT_CGH1_REG(base), (uint8_t)(value)))
2691 #define CMT_CLR_CGH1(base, value) (BME_AND8(&CMT_CGH1_REG(base), (uint8_t)(~(value))))
2692 #define CMT_TOG_CGH1(base, value) (BME_XOR8(&CMT_CGH1_REG(base), (uint8_t)(value)))
2693 /*@}*/
2694 
2695 /*******************************************************************************
2696  * CMT_CGL1 - CMT Carrier Generator Low Data Register 1
2697  ******************************************************************************/
2698 
2699 /*!
2700  * @brief CMT_CGL1 - CMT Carrier Generator Low Data Register 1 (RW)
2701  *
2702  * Reset value: 0x00U
2703  *
2704  * This data register contains the primary low value for generating the carrier
2705  * output.
2706  */
2707 /*!
2708  * @name Constants and macros for entire CMT_CGL1 register
2709  */
2710 /*@{*/
2711 #define CMT_RD_CGL1(base)        (CMT_CGL1_REG(base))
2712 #define CMT_WR_CGL1(base, value) (CMT_CGL1_REG(base) = (value))
2713 #define CMT_RMW_CGL1(base, mask, value) (CMT_WR_CGL1(base, (CMT_RD_CGL1(base) & ~(mask)) | (value)))
2714 #define CMT_SET_CGL1(base, value) (BME_OR8(&CMT_CGL1_REG(base), (uint8_t)(value)))
2715 #define CMT_CLR_CGL1(base, value) (BME_AND8(&CMT_CGL1_REG(base), (uint8_t)(~(value))))
2716 #define CMT_TOG_CGL1(base, value) (BME_XOR8(&CMT_CGL1_REG(base), (uint8_t)(value)))
2717 /*@}*/
2718 
2719 /*******************************************************************************
2720  * CMT_CGH2 - CMT Carrier Generator High Data Register 2
2721  ******************************************************************************/
2722 
2723 /*!
2724  * @brief CMT_CGH2 - CMT Carrier Generator High Data Register 2 (RW)
2725  *
2726  * Reset value: 0x00U
2727  *
2728  * This data register contains the secondary high value for generating the
2729  * carrier output.
2730  */
2731 /*!
2732  * @name Constants and macros for entire CMT_CGH2 register
2733  */
2734 /*@{*/
2735 #define CMT_RD_CGH2(base)        (CMT_CGH2_REG(base))
2736 #define CMT_WR_CGH2(base, value) (CMT_CGH2_REG(base) = (value))
2737 #define CMT_RMW_CGH2(base, mask, value) (CMT_WR_CGH2(base, (CMT_RD_CGH2(base) & ~(mask)) | (value)))
2738 #define CMT_SET_CGH2(base, value) (BME_OR8(&CMT_CGH2_REG(base), (uint8_t)(value)))
2739 #define CMT_CLR_CGH2(base, value) (BME_AND8(&CMT_CGH2_REG(base), (uint8_t)(~(value))))
2740 #define CMT_TOG_CGH2(base, value) (BME_XOR8(&CMT_CGH2_REG(base), (uint8_t)(value)))
2741 /*@}*/
2742 
2743 /*******************************************************************************
2744  * CMT_CGL2 - CMT Carrier Generator Low Data Register 2
2745  ******************************************************************************/
2746 
2747 /*!
2748  * @brief CMT_CGL2 - CMT Carrier Generator Low Data Register 2 (RW)
2749  *
2750  * Reset value: 0x00U
2751  *
2752  * This data register contains the secondary low value for generating the
2753  * carrier output.
2754  */
2755 /*!
2756  * @name Constants and macros for entire CMT_CGL2 register
2757  */
2758 /*@{*/
2759 #define CMT_RD_CGL2(base)        (CMT_CGL2_REG(base))
2760 #define CMT_WR_CGL2(base, value) (CMT_CGL2_REG(base) = (value))
2761 #define CMT_RMW_CGL2(base, mask, value) (CMT_WR_CGL2(base, (CMT_RD_CGL2(base) & ~(mask)) | (value)))
2762 #define CMT_SET_CGL2(base, value) (BME_OR8(&CMT_CGL2_REG(base), (uint8_t)(value)))
2763 #define CMT_CLR_CGL2(base, value) (BME_AND8(&CMT_CGL2_REG(base), (uint8_t)(~(value))))
2764 #define CMT_TOG_CGL2(base, value) (BME_XOR8(&CMT_CGL2_REG(base), (uint8_t)(value)))
2765 /*@}*/
2766 
2767 /*******************************************************************************
2768  * CMT_OC - CMT Output Control Register
2769  ******************************************************************************/
2770 
2771 /*!
2772  * @brief CMT_OC - CMT Output Control Register (RW)
2773  *
2774  * Reset value: 0x00U
2775  *
2776  * This register is used to control the IRO signal of the CMT module.
2777  */
2778 /*!
2779  * @name Constants and macros for entire CMT_OC register
2780  */
2781 /*@{*/
2782 #define CMT_RD_OC(base)          (CMT_OC_REG(base))
2783 #define CMT_WR_OC(base, value)   (CMT_OC_REG(base) = (value))
2784 #define CMT_RMW_OC(base, mask, value) (CMT_WR_OC(base, (CMT_RD_OC(base) & ~(mask)) | (value)))
2785 #define CMT_SET_OC(base, value)  (BME_OR8(&CMT_OC_REG(base), (uint8_t)(value)))
2786 #define CMT_CLR_OC(base, value)  (BME_AND8(&CMT_OC_REG(base), (uint8_t)(~(value))))
2787 #define CMT_TOG_OC(base, value)  (BME_XOR8(&CMT_OC_REG(base), (uint8_t)(value)))
2788 /*@}*/
2789 
2790 /*
2791  * Constants & macros for individual CMT_OC bitfields
2792  */
2793 
2794 /*!
2795  * @name Register CMT_OC, field IROPEN[5] (RW)
2796  *
2797  * Enables and disables the IRO signal. When the IRO signal is enabled, it is an
2798  * output that drives out either the CMT transmitter output or the state of IROL
2799  * depending on whether MSC[MCGEN] is set or not. Also, the state of output is
2800  * either inverted or non-inverted, depending on the state of CMTPOL. When the IRO
2801  * signal is disabled, it is in a high-impedance state and is unable to draw any
2802  * current. This signal is disabled during reset.
2803  *
2804  * Values:
2805  * - 0b0 - The IRO signal is disabled.
2806  * - 0b1 - The IRO signal is enabled as output.
2807  */
2808 /*@{*/
2809 /*! @brief Read current value of the CMT_OC_IROPEN field. */
2810 #define CMT_RD_OC_IROPEN(base) ((CMT_OC_REG(base) & CMT_OC_IROPEN_MASK) >> CMT_OC_IROPEN_SHIFT)
2811 #define CMT_BRD_OC_IROPEN(base) (BME_UBFX8(&CMT_OC_REG(base), CMT_OC_IROPEN_SHIFT, CMT_OC_IROPEN_WIDTH))
2812 
2813 /*! @brief Set the IROPEN field to a new value. */
2814 #define CMT_WR_OC_IROPEN(base, value) (CMT_RMW_OC(base, CMT_OC_IROPEN_MASK, CMT_OC_IROPEN(value)))
2815 #define CMT_BWR_OC_IROPEN(base, value) (BME_BFI8(&CMT_OC_REG(base), ((uint8_t)(value) << CMT_OC_IROPEN_SHIFT), CMT_OC_IROPEN_SHIFT, CMT_OC_IROPEN_WIDTH))
2816 /*@}*/
2817 
2818 /*!
2819  * @name Register CMT_OC, field CMTPOL[6] (RW)
2820  *
2821  * Controls the polarity of the IRO signal.
2822  *
2823  * Values:
2824  * - 0b0 - The IRO signal is active-low.
2825  * - 0b1 - The IRO signal is active-high.
2826  */
2827 /*@{*/
2828 /*! @brief Read current value of the CMT_OC_CMTPOL field. */
2829 #define CMT_RD_OC_CMTPOL(base) ((CMT_OC_REG(base) & CMT_OC_CMTPOL_MASK) >> CMT_OC_CMTPOL_SHIFT)
2830 #define CMT_BRD_OC_CMTPOL(base) (BME_UBFX8(&CMT_OC_REG(base), CMT_OC_CMTPOL_SHIFT, CMT_OC_CMTPOL_WIDTH))
2831 
2832 /*! @brief Set the CMTPOL field to a new value. */
2833 #define CMT_WR_OC_CMTPOL(base, value) (CMT_RMW_OC(base, CMT_OC_CMTPOL_MASK, CMT_OC_CMTPOL(value)))
2834 #define CMT_BWR_OC_CMTPOL(base, value) (BME_BFI8(&CMT_OC_REG(base), ((uint8_t)(value) << CMT_OC_CMTPOL_SHIFT), CMT_OC_CMTPOL_SHIFT, CMT_OC_CMTPOL_WIDTH))
2835 /*@}*/
2836 
2837 /*!
2838  * @name Register CMT_OC, field IROL[7] (RW)
2839  *
2840  * Reads the state of the IRO latch. Writing to IROL changes the state of the
2841  * IRO signal when MSC[MCGEN] is cleared and IROPEN is set.
2842  */
2843 /*@{*/
2844 /*! @brief Read current value of the CMT_OC_IROL field. */
2845 #define CMT_RD_OC_IROL(base) ((CMT_OC_REG(base) & CMT_OC_IROL_MASK) >> CMT_OC_IROL_SHIFT)
2846 #define CMT_BRD_OC_IROL(base) (BME_UBFX8(&CMT_OC_REG(base), CMT_OC_IROL_SHIFT, CMT_OC_IROL_WIDTH))
2847 
2848 /*! @brief Set the IROL field to a new value. */
2849 #define CMT_WR_OC_IROL(base, value) (CMT_RMW_OC(base, CMT_OC_IROL_MASK, CMT_OC_IROL(value)))
2850 #define CMT_BWR_OC_IROL(base, value) (BME_BFI8(&CMT_OC_REG(base), ((uint8_t)(value) << CMT_OC_IROL_SHIFT), CMT_OC_IROL_SHIFT, CMT_OC_IROL_WIDTH))
2851 /*@}*/
2852 
2853 /*******************************************************************************
2854  * CMT_MSC - CMT Modulator Status and Control Register
2855  ******************************************************************************/
2856 
2857 /*!
2858  * @brief CMT_MSC - CMT Modulator Status and Control Register (RW)
2859  *
2860  * Reset value: 0x00U
2861  *
2862  * This register contains the modulator and carrier generator enable (MCGEN),
2863  * end of cycle interrupt enable (EOCIE), FSK mode select (FSK), baseband enable
2864  * (BASE), extended space (EXSPC), prescaler (CMTDIV) bits, and the end of cycle
2865  * (EOCF) status bit.
2866  */
2867 /*!
2868  * @name Constants and macros for entire CMT_MSC register
2869  */
2870 /*@{*/
2871 #define CMT_RD_MSC(base)         (CMT_MSC_REG(base))
2872 #define CMT_WR_MSC(base, value)  (CMT_MSC_REG(base) = (value))
2873 #define CMT_RMW_MSC(base, mask, value) (CMT_WR_MSC(base, (CMT_RD_MSC(base) & ~(mask)) | (value)))
2874 #define CMT_SET_MSC(base, value) (BME_OR8(&CMT_MSC_REG(base), (uint8_t)(value)))
2875 #define CMT_CLR_MSC(base, value) (BME_AND8(&CMT_MSC_REG(base), (uint8_t)(~(value))))
2876 #define CMT_TOG_MSC(base, value) (BME_XOR8(&CMT_MSC_REG(base), (uint8_t)(value)))
2877 /*@}*/
2878 
2879 /*
2880  * Constants & macros for individual CMT_MSC bitfields
2881  */
2882 
2883 /*!
2884  * @name Register CMT_MSC, field MCGEN[0] (RW)
2885  *
2886  * Setting MCGEN will initialize the carrier generator and modulator and will
2887  * enable all clocks. When enabled, the carrier generator and modulator will
2888  * function continuously. When MCGEN is cleared, the current modulator cycle will be
2889  * allowed to expire before all carrier and modulator clocks are disabled to save
2890  * power and the modulator output is forced low. To prevent spurious operation,
2891  * the user should initialize all data and control registers before enabling the
2892  * system.
2893  *
2894  * Values:
2895  * - 0b0 - Modulator and carrier generator disabled
2896  * - 0b1 - Modulator and carrier generator enabled
2897  */
2898 /*@{*/
2899 /*! @brief Read current value of the CMT_MSC_MCGEN field. */
2900 #define CMT_RD_MSC_MCGEN(base) ((CMT_MSC_REG(base) & CMT_MSC_MCGEN_MASK) >> CMT_MSC_MCGEN_SHIFT)
2901 #define CMT_BRD_MSC_MCGEN(base) (BME_UBFX8(&CMT_MSC_REG(base), CMT_MSC_MCGEN_SHIFT, CMT_MSC_MCGEN_WIDTH))
2902 
2903 /*! @brief Set the MCGEN field to a new value. */
2904 #define CMT_WR_MSC_MCGEN(base, value) (CMT_RMW_MSC(base, CMT_MSC_MCGEN_MASK, CMT_MSC_MCGEN(value)))
2905 #define CMT_BWR_MSC_MCGEN(base, value) (BME_BFI8(&CMT_MSC_REG(base), ((uint8_t)(value) << CMT_MSC_MCGEN_SHIFT), CMT_MSC_MCGEN_SHIFT, CMT_MSC_MCGEN_WIDTH))
2906 /*@}*/
2907 
2908 /*!
2909  * @name Register CMT_MSC, field EOCIE[1] (RW)
2910  *
2911  * Requests to enable a CPU interrupt when EOCF is set if EOCIE is high.
2912  *
2913  * Values:
2914  * - 0b0 - CPU interrupt is disabled.
2915  * - 0b1 - CPU interrupt is enabled.
2916  */
2917 /*@{*/
2918 /*! @brief Read current value of the CMT_MSC_EOCIE field. */
2919 #define CMT_RD_MSC_EOCIE(base) ((CMT_MSC_REG(base) & CMT_MSC_EOCIE_MASK) >> CMT_MSC_EOCIE_SHIFT)
2920 #define CMT_BRD_MSC_EOCIE(base) (BME_UBFX8(&CMT_MSC_REG(base), CMT_MSC_EOCIE_SHIFT, CMT_MSC_EOCIE_WIDTH))
2921 
2922 /*! @brief Set the EOCIE field to a new value. */
2923 #define CMT_WR_MSC_EOCIE(base, value) (CMT_RMW_MSC(base, CMT_MSC_EOCIE_MASK, CMT_MSC_EOCIE(value)))
2924 #define CMT_BWR_MSC_EOCIE(base, value) (BME_BFI8(&CMT_MSC_REG(base), ((uint8_t)(value) << CMT_MSC_EOCIE_SHIFT), CMT_MSC_EOCIE_SHIFT, CMT_MSC_EOCIE_WIDTH))
2925 /*@}*/
2926 
2927 /*!
2928  * @name Register CMT_MSC, field FSK[2] (RW)
2929  *
2930  * Enables FSK operation.
2931  *
2932  * Values:
2933  * - 0b0 - The CMT operates in Time or Baseband mode.
2934  * - 0b1 - The CMT operates in FSK mode.
2935  */
2936 /*@{*/
2937 /*! @brief Read current value of the CMT_MSC_FSK field. */
2938 #define CMT_RD_MSC_FSK(base) ((CMT_MSC_REG(base) & CMT_MSC_FSK_MASK) >> CMT_MSC_FSK_SHIFT)
2939 #define CMT_BRD_MSC_FSK(base) (BME_UBFX8(&CMT_MSC_REG(base), CMT_MSC_FSK_SHIFT, CMT_MSC_FSK_WIDTH))
2940 
2941 /*! @brief Set the FSK field to a new value. */
2942 #define CMT_WR_MSC_FSK(base, value) (CMT_RMW_MSC(base, CMT_MSC_FSK_MASK, CMT_MSC_FSK(value)))
2943 #define CMT_BWR_MSC_FSK(base, value) (BME_BFI8(&CMT_MSC_REG(base), ((uint8_t)(value) << CMT_MSC_FSK_SHIFT), CMT_MSC_FSK_SHIFT, CMT_MSC_FSK_WIDTH))
2944 /*@}*/
2945 
2946 /*!
2947  * @name Register CMT_MSC, field BASE[3] (RW)
2948  *
2949  * When set, BASE disables the carrier generator and forces the carrier output
2950  * high for generation of baseband protocols. When BASE is cleared, the carrier
2951  * generator is enabled and the carrier output toggles at the frequency determined
2952  * by values stored in the carrier data registers. This field is cleared by
2953  * reset. This field is not double-buffered and must not be written to during a
2954  * transmission.
2955  *
2956  * Values:
2957  * - 0b0 - Baseband mode is disabled.
2958  * - 0b1 - Baseband mode is enabled.
2959  */
2960 /*@{*/
2961 /*! @brief Read current value of the CMT_MSC_BASE field. */
2962 #define CMT_RD_MSC_BASE(base) ((CMT_MSC_REG(base) & CMT_MSC_BASE_MASK) >> CMT_MSC_BASE_SHIFT)
2963 #define CMT_BRD_MSC_BASE(base) (BME_UBFX8(&CMT_MSC_REG(base), CMT_MSC_BASE_SHIFT, CMT_MSC_BASE_WIDTH))
2964 
2965 /*! @brief Set the BASE field to a new value. */
2966 #define CMT_WR_MSC_BASE(base, value) (CMT_RMW_MSC(base, CMT_MSC_BASE_MASK, CMT_MSC_BASE(value)))
2967 #define CMT_BWR_MSC_BASE(base, value) (BME_BFI8(&CMT_MSC_REG(base), ((uint8_t)(value) << CMT_MSC_BASE_SHIFT), CMT_MSC_BASE_SHIFT, CMT_MSC_BASE_WIDTH))
2968 /*@}*/
2969 
2970 /*!
2971  * @name Register CMT_MSC, field EXSPC[4] (RW)
2972  *
2973  * Enables the extended space operation.
2974  *
2975  * Values:
2976  * - 0b0 - Extended space is disabled.
2977  * - 0b1 - Extended space is enabled.
2978  */
2979 /*@{*/
2980 /*! @brief Read current value of the CMT_MSC_EXSPC field. */
2981 #define CMT_RD_MSC_EXSPC(base) ((CMT_MSC_REG(base) & CMT_MSC_EXSPC_MASK) >> CMT_MSC_EXSPC_SHIFT)
2982 #define CMT_BRD_MSC_EXSPC(base) (BME_UBFX8(&CMT_MSC_REG(base), CMT_MSC_EXSPC_SHIFT, CMT_MSC_EXSPC_WIDTH))
2983 
2984 /*! @brief Set the EXSPC field to a new value. */
2985 #define CMT_WR_MSC_EXSPC(base, value) (CMT_RMW_MSC(base, CMT_MSC_EXSPC_MASK, CMT_MSC_EXSPC(value)))
2986 #define CMT_BWR_MSC_EXSPC(base, value) (BME_BFI8(&CMT_MSC_REG(base), ((uint8_t)(value) << CMT_MSC_EXSPC_SHIFT), CMT_MSC_EXSPC_SHIFT, CMT_MSC_EXSPC_WIDTH))
2987 /*@}*/
2988 
2989 /*!
2990  * @name Register CMT_MSC, field CMTDIV[6:5] (RW)
2991  *
2992  * Causes the CMT to be clocked at the IF signal frequency, or the IF frequency
2993  * divided by 2 ,4, or 8 . This field must not be changed during a transmission
2994  * because it is not double-buffered.
2995  *
2996  * Values:
2997  * - 0b00 - IF * 1
2998  * - 0b01 - IF * 2
2999  * - 0b10 - IF * 4
3000  * - 0b11 - IF * 8
3001  */
3002 /*@{*/
3003 /*! @brief Read current value of the CMT_MSC_CMTDIV field. */
3004 #define CMT_RD_MSC_CMTDIV(base) ((CMT_MSC_REG(base) & CMT_MSC_CMTDIV_MASK) >> CMT_MSC_CMTDIV_SHIFT)
3005 #define CMT_BRD_MSC_CMTDIV(base) (BME_UBFX8(&CMT_MSC_REG(base), CMT_MSC_CMTDIV_SHIFT, CMT_MSC_CMTDIV_WIDTH))
3006 
3007 /*! @brief Set the CMTDIV field to a new value. */
3008 #define CMT_WR_MSC_CMTDIV(base, value) (CMT_RMW_MSC(base, CMT_MSC_CMTDIV_MASK, CMT_MSC_CMTDIV(value)))
3009 #define CMT_BWR_MSC_CMTDIV(base, value) (BME_BFI8(&CMT_MSC_REG(base), ((uint8_t)(value) << CMT_MSC_CMTDIV_SHIFT), CMT_MSC_CMTDIV_SHIFT, CMT_MSC_CMTDIV_WIDTH))
3010 /*@}*/
3011 
3012 /*!
3013  * @name Register CMT_MSC, field EOCF[7] (RO)
3014  *
3015  * Sets when: The modulator is not currently active and MCGEN is set to begin
3016  * the initial CMT transmission. At the end of each modulation cycle while MCGEN is
3017  * set. This is recognized when a match occurs between the contents of the space
3018  * period register and the down counter. At this time, the counter is
3019  * initialized with, possibly new contents of the mark period buffer, CMD1 and CMD2, and
3020  * the space period register is loaded with, possibly new contents of the space
3021  * period buffer, CMD3 and CMD4. This flag is cleared by reading MSC followed by an
3022  * access of CMD2 or CMD4, or by the DMA transfer.
3023  *
3024  * Values:
3025  * - 0b0 - End of modulation cycle has not occured since the flag last cleared.
3026  * - 0b1 - End of modulator cycle has occurred.
3027  */
3028 /*@{*/
3029 /*! @brief Read current value of the CMT_MSC_EOCF field. */
3030 #define CMT_RD_MSC_EOCF(base) ((CMT_MSC_REG(base) & CMT_MSC_EOCF_MASK) >> CMT_MSC_EOCF_SHIFT)
3031 #define CMT_BRD_MSC_EOCF(base) (BME_UBFX8(&CMT_MSC_REG(base), CMT_MSC_EOCF_SHIFT, CMT_MSC_EOCF_WIDTH))
3032 /*@}*/
3033 
3034 /*******************************************************************************
3035  * CMT_CMD1 - CMT Modulator Data Register Mark High
3036  ******************************************************************************/
3037 
3038 /*!
3039  * @brief CMT_CMD1 - CMT Modulator Data Register Mark High (RW)
3040  *
3041  * Reset value: 0x00U
3042  *
3043  * The contents of this register are transferred to the modulator down counter
3044  * upon the completion of a modulation period.
3045  */
3046 /*!
3047  * @name Constants and macros for entire CMT_CMD1 register
3048  */
3049 /*@{*/
3050 #define CMT_RD_CMD1(base)        (CMT_CMD1_REG(base))
3051 #define CMT_WR_CMD1(base, value) (CMT_CMD1_REG(base) = (value))
3052 #define CMT_RMW_CMD1(base, mask, value) (CMT_WR_CMD1(base, (CMT_RD_CMD1(base) & ~(mask)) | (value)))
3053 #define CMT_SET_CMD1(base, value) (BME_OR8(&CMT_CMD1_REG(base), (uint8_t)(value)))
3054 #define CMT_CLR_CMD1(base, value) (BME_AND8(&CMT_CMD1_REG(base), (uint8_t)(~(value))))
3055 #define CMT_TOG_CMD1(base, value) (BME_XOR8(&CMT_CMD1_REG(base), (uint8_t)(value)))
3056 /*@}*/
3057 
3058 /*******************************************************************************
3059  * CMT_CMD2 - CMT Modulator Data Register Mark Low
3060  ******************************************************************************/
3061 
3062 /*!
3063  * @brief CMT_CMD2 - CMT Modulator Data Register Mark Low (RW)
3064  *
3065  * Reset value: 0x00U
3066  *
3067  * The contents of this register are transferred to the modulator down counter
3068  * upon the completion of a modulation period.
3069  */
3070 /*!
3071  * @name Constants and macros for entire CMT_CMD2 register
3072  */
3073 /*@{*/
3074 #define CMT_RD_CMD2(base)        (CMT_CMD2_REG(base))
3075 #define CMT_WR_CMD2(base, value) (CMT_CMD2_REG(base) = (value))
3076 #define CMT_RMW_CMD2(base, mask, value) (CMT_WR_CMD2(base, (CMT_RD_CMD2(base) & ~(mask)) | (value)))
3077 #define CMT_SET_CMD2(base, value) (BME_OR8(&CMT_CMD2_REG(base), (uint8_t)(value)))
3078 #define CMT_CLR_CMD2(base, value) (BME_AND8(&CMT_CMD2_REG(base), (uint8_t)(~(value))))
3079 #define CMT_TOG_CMD2(base, value) (BME_XOR8(&CMT_CMD2_REG(base), (uint8_t)(value)))
3080 /*@}*/
3081 
3082 /*******************************************************************************
3083  * CMT_CMD3 - CMT Modulator Data Register Space High
3084  ******************************************************************************/
3085 
3086 /*!
3087  * @brief CMT_CMD3 - CMT Modulator Data Register Space High (RW)
3088  *
3089  * Reset value: 0x00U
3090  *
3091  * The contents of this register are transferred to the space period register
3092  * upon the completion of a modulation period.
3093  */
3094 /*!
3095  * @name Constants and macros for entire CMT_CMD3 register
3096  */
3097 /*@{*/
3098 #define CMT_RD_CMD3(base)        (CMT_CMD3_REG(base))
3099 #define CMT_WR_CMD3(base, value) (CMT_CMD3_REG(base) = (value))
3100 #define CMT_RMW_CMD3(base, mask, value) (CMT_WR_CMD3(base, (CMT_RD_CMD3(base) & ~(mask)) | (value)))
3101 #define CMT_SET_CMD3(base, value) (BME_OR8(&CMT_CMD3_REG(base), (uint8_t)(value)))
3102 #define CMT_CLR_CMD3(base, value) (BME_AND8(&CMT_CMD3_REG(base), (uint8_t)(~(value))))
3103 #define CMT_TOG_CMD3(base, value) (BME_XOR8(&CMT_CMD3_REG(base), (uint8_t)(value)))
3104 /*@}*/
3105 
3106 /*******************************************************************************
3107  * CMT_CMD4 - CMT Modulator Data Register Space Low
3108  ******************************************************************************/
3109 
3110 /*!
3111  * @brief CMT_CMD4 - CMT Modulator Data Register Space Low (RW)
3112  *
3113  * Reset value: 0x00U
3114  *
3115  * The contents of this register are transferred to the space period register
3116  * upon the completion of a modulation period.
3117  */
3118 /*!
3119  * @name Constants and macros for entire CMT_CMD4 register
3120  */
3121 /*@{*/
3122 #define CMT_RD_CMD4(base)        (CMT_CMD4_REG(base))
3123 #define CMT_WR_CMD4(base, value) (CMT_CMD4_REG(base) = (value))
3124 #define CMT_RMW_CMD4(base, mask, value) (CMT_WR_CMD4(base, (CMT_RD_CMD4(base) & ~(mask)) | (value)))
3125 #define CMT_SET_CMD4(base, value) (BME_OR8(&CMT_CMD4_REG(base), (uint8_t)(value)))
3126 #define CMT_CLR_CMD4(base, value) (BME_AND8(&CMT_CMD4_REG(base), (uint8_t)(~(value))))
3127 #define CMT_TOG_CMD4(base, value) (BME_XOR8(&CMT_CMD4_REG(base), (uint8_t)(value)))
3128 /*@}*/
3129 
3130 /*******************************************************************************
3131  * CMT_PPS - CMT Primary Prescaler Register
3132  ******************************************************************************/
3133 
3134 /*!
3135  * @brief CMT_PPS - CMT Primary Prescaler Register (RW)
3136  *
3137  * Reset value: 0x00U
3138  *
3139  * This register is used to set the Primary Prescaler Divider field (PPSDIV).
3140  */
3141 /*!
3142  * @name Constants and macros for entire CMT_PPS register
3143  */
3144 /*@{*/
3145 #define CMT_RD_PPS(base)         (CMT_PPS_REG(base))
3146 #define CMT_WR_PPS(base, value)  (CMT_PPS_REG(base) = (value))
3147 #define CMT_RMW_PPS(base, mask, value) (CMT_WR_PPS(base, (CMT_RD_PPS(base) & ~(mask)) | (value)))
3148 #define CMT_SET_PPS(base, value) (BME_OR8(&CMT_PPS_REG(base), (uint8_t)(value)))
3149 #define CMT_CLR_PPS(base, value) (BME_AND8(&CMT_PPS_REG(base), (uint8_t)(~(value))))
3150 #define CMT_TOG_PPS(base, value) (BME_XOR8(&CMT_PPS_REG(base), (uint8_t)(value)))
3151 /*@}*/
3152 
3153 /*
3154  * Constants & macros for individual CMT_PPS bitfields
3155  */
3156 
3157 /*!
3158  * @name Register CMT_PPS, field PPSDIV[3:0] (RW)
3159  *
3160  * Divides the CMT clock to generate the Intermediate Frequency clock enable to
3161  * the secondary prescaler.
3162  *
3163  * Values:
3164  * - 0b0000 - Bus clock * 1
3165  * - 0b0001 - Bus clock * 2
3166  * - 0b0010 - Bus clock * 3
3167  * - 0b0011 - Bus clock * 4
3168  * - 0b0100 - Bus clock * 5
3169  * - 0b0101 - Bus clock * 6
3170  * - 0b0110 - Bus clock * 7
3171  * - 0b0111 - Bus clock * 8
3172  * - 0b1000 - Bus clock * 9
3173  * - 0b1001 - Bus clock * 10
3174  * - 0b1010 - Bus clock * 11
3175  * - 0b1011 - Bus clock * 12
3176  * - 0b1100 - Bus clock * 13
3177  * - 0b1101 - Bus clock * 14
3178  * - 0b1110 - Bus clock * 15
3179  * - 0b1111 - Bus clock * 16
3180  */
3181 /*@{*/
3182 /*! @brief Read current value of the CMT_PPS_PPSDIV field. */
3183 #define CMT_RD_PPS_PPSDIV(base) ((CMT_PPS_REG(base) & CMT_PPS_PPSDIV_MASK) >> CMT_PPS_PPSDIV_SHIFT)
3184 #define CMT_BRD_PPS_PPSDIV(base) (BME_UBFX8(&CMT_PPS_REG(base), CMT_PPS_PPSDIV_SHIFT, CMT_PPS_PPSDIV_WIDTH))
3185 
3186 /*! @brief Set the PPSDIV field to a new value. */
3187 #define CMT_WR_PPS_PPSDIV(base, value) (CMT_RMW_PPS(base, CMT_PPS_PPSDIV_MASK, CMT_PPS_PPSDIV(value)))
3188 #define CMT_BWR_PPS_PPSDIV(base, value) (BME_BFI8(&CMT_PPS_REG(base), ((uint8_t)(value) << CMT_PPS_PPSDIV_SHIFT), CMT_PPS_PPSDIV_SHIFT, CMT_PPS_PPSDIV_WIDTH))
3189 /*@}*/
3190 
3191 /*******************************************************************************
3192  * CMT_DMA - CMT Direct Memory Access Register
3193  ******************************************************************************/
3194 
3195 /*!
3196  * @brief CMT_DMA - CMT Direct Memory Access Register (RW)
3197  *
3198  * Reset value: 0x00U
3199  *
3200  * This register is used to enable/disable direct memory access (DMA).
3201  */
3202 /*!
3203  * @name Constants and macros for entire CMT_DMA register
3204  */
3205 /*@{*/
3206 #define CMT_RD_DMA(base)         (CMT_DMA_REG(base))
3207 #define CMT_WR_DMA(base, value)  (CMT_DMA_REG(base) = (value))
3208 #define CMT_RMW_DMA(base, mask, value) (CMT_WR_DMA(base, (CMT_RD_DMA(base) & ~(mask)) | (value)))
3209 #define CMT_SET_DMA(base, value) (BME_OR8(&CMT_DMA_REG(base), (uint8_t)(value)))
3210 #define CMT_CLR_DMA(base, value) (BME_AND8(&CMT_DMA_REG(base), (uint8_t)(~(value))))
3211 #define CMT_TOG_DMA(base, value) (BME_XOR8(&CMT_DMA_REG(base), (uint8_t)(value)))
3212 /*@}*/
3213 
3214 /*
3215  * Constants & macros for individual CMT_DMA bitfields
3216  */
3217 
3218 /*!
3219  * @name Register CMT_DMA, field DMA[0] (RW)
3220  *
3221  * Enables the DMA protocol.
3222  *
3223  * Values:
3224  * - 0b0 - DMA transfer request and done are disabled.
3225  * - 0b1 - DMA transfer request and done are enabled.
3226  */
3227 /*@{*/
3228 /*! @brief Read current value of the CMT_DMA_DMA field. */
3229 #define CMT_RD_DMA_DMA(base) ((CMT_DMA_REG(base) & CMT_DMA_DMA_MASK) >> CMT_DMA_DMA_SHIFT)
3230 #define CMT_BRD_DMA_DMA(base) (BME_UBFX8(&CMT_DMA_REG(base), CMT_DMA_DMA_SHIFT, CMT_DMA_DMA_WIDTH))
3231 
3232 /*! @brief Set the DMA field to a new value. */
3233 #define CMT_WR_DMA_DMA(base, value) (CMT_RMW_DMA(base, CMT_DMA_DMA_MASK, CMT_DMA_DMA(value)))
3234 #define CMT_BWR_DMA_DMA(base, value) (BME_BFI8(&CMT_DMA_REG(base), ((uint8_t)(value) << CMT_DMA_DMA_SHIFT), CMT_DMA_DMA_SHIFT, CMT_DMA_DMA_WIDTH))
3235 /*@}*/
3236 
3237 /*
3238  * MKW40Z4 DAC
3239  *
3240  * 12-Bit Digital-to-Analog Converter
3241  *
3242  * Registers defined in this header file:
3243  * - DAC_DATL - DAC Data Low Register
3244  * - DAC_DATH - DAC Data High Register
3245  * - DAC_SR - DAC Status Register
3246  * - DAC_C0 - DAC Control Register
3247  * - DAC_C1 - DAC Control Register 1
3248  * - DAC_C2 - DAC Control Register 2
3249  */
3250 
3251 #define DAC_INSTANCE_COUNT (1U) /*!< Number of instances of the DAC module. */
3252 #define DAC0_IDX (0U) /*!< Instance number for DAC0. */
3253 
3254 /*******************************************************************************
3255  * DAC_DATL - DAC Data Low Register
3256  ******************************************************************************/
3257 
3258 /*!
3259  * @brief DAC_DATL - DAC Data Low Register (RW)
3260  *
3261  * Reset value: 0x00U
3262  */
3263 /*!
3264  * @name Constants and macros for entire DAC_DATL register
3265  */
3266 /*@{*/
3267 #define DAC_RD_DATL(base, index) (DAC_DATL_REG(base, index))
3268 #define DAC_WR_DATL(base, index, value) (DAC_DATL_REG(base, index) = (value))
3269 #define DAC_RMW_DATL(base, index, mask, value) (DAC_WR_DATL(base, index, (DAC_RD_DATL(base, index) & ~(mask)) | (value)))
3270 #define DAC_SET_DATL(base, index, value) (BME_OR8(&DAC_DATL_REG(base, index), (uint8_t)(value)))
3271 #define DAC_CLR_DATL(base, index, value) (BME_AND8(&DAC_DATL_REG(base, index), (uint8_t)(~(value))))
3272 #define DAC_TOG_DATL(base, index, value) (BME_XOR8(&DAC_DATL_REG(base, index), (uint8_t)(value)))
3273 /*@}*/
3274 
3275 /*******************************************************************************
3276  * DAC_DATH - DAC Data High Register
3277  ******************************************************************************/
3278 
3279 /*!
3280  * @brief DAC_DATH - DAC Data High Register (RW)
3281  *
3282  * Reset value: 0x00U
3283  */
3284 /*!
3285  * @name Constants and macros for entire DAC_DATH register
3286  */
3287 /*@{*/
3288 #define DAC_RD_DATH(base, index) (DAC_DATH_REG(base, index))
3289 #define DAC_WR_DATH(base, index, value) (DAC_DATH_REG(base, index) = (value))
3290 #define DAC_RMW_DATH(base, index, mask, value) (DAC_WR_DATH(base, index, (DAC_RD_DATH(base, index) & ~(mask)) | (value)))
3291 #define DAC_SET_DATH(base, index, value) (BME_OR8(&DAC_DATH_REG(base, index), (uint8_t)(value)))
3292 #define DAC_CLR_DATH(base, index, value) (BME_AND8(&DAC_DATH_REG(base, index), (uint8_t)(~(value))))
3293 #define DAC_TOG_DATH(base, index, value) (BME_XOR8(&DAC_DATH_REG(base, index), (uint8_t)(value)))
3294 /*@}*/
3295 
3296 /*
3297  * Constants & macros for individual DAC_DATH bitfields
3298  */
3299 
3300 /*!
3301  * @name Register DAC_DATH, field DATA1[3:0] (RW)
3302  *
3303  * When the DAC Buffer is not enabled, DATA[11:0] controls the output voltage
3304  * based on the following formula. V out = V in * (1 + DACDAT0[11:0])/4096 When the
3305  * DAC buffer is enabled, DATA[11:0] is mapped to the 16-word buffer.
3306  */
3307 /*@{*/
3308 /*! @brief Read current value of the DAC_DATH_DATA1 field. */
3309 #define DAC_RD_DATH_DATA1(base, index) ((DAC_DATH_REG(base, index) & DAC_DATH_DATA1_MASK) >> DAC_DATH_DATA1_SHIFT)
3310 #define DAC_BRD_DATH_DATA1(base, index) (BME_UBFX8(&DAC_DATH_REG(base, index), DAC_DATH_DATA1_SHIFT, DAC_DATH_DATA1_WIDTH))
3311 
3312 /*! @brief Set the DATA1 field to a new value. */
3313 #define DAC_WR_DATH_DATA1(base, index, value) (DAC_RMW_DATH(base, index, DAC_DATH_DATA1_MASK, DAC_DATH_DATA1(value)))
3314 #define DAC_BWR_DATH_DATA1(base, index, value) (BME_BFI8(&DAC_DATH_REG(base, index), ((uint8_t)(value) << DAC_DATH_DATA1_SHIFT), DAC_DATH_DATA1_SHIFT, DAC_DATH_DATA1_WIDTH))
3315 /*@}*/
3316 
3317 /*******************************************************************************
3318  * DAC_SR - DAC Status Register
3319  ******************************************************************************/
3320 
3321 /*!
3322  * @brief DAC_SR - DAC Status Register (RW)
3323  *
3324  * Reset value: 0x02U
3325  *
3326  * If DMA is enabled, the flags can be cleared automatically by DMA when the DMA
3327  * request is done. Writing 0 to a field clears it whereas writing 1 has no
3328  * effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
3329  * The flags are set only when the data buffer status is changed. Do not use
3330  * 32/16-bit accesses to this register.
3331  */
3332 /*!
3333  * @name Constants and macros for entire DAC_SR register
3334  */
3335 /*@{*/
3336 #define DAC_RD_SR(base)          (DAC_SR_REG(base))
3337 #define DAC_WR_SR(base, value)   (DAC_SR_REG(base) = (value))
3338 #define DAC_RMW_SR(base, mask, value) (DAC_WR_SR(base, (DAC_RD_SR(base) & ~(mask)) | (value)))
3339 #define DAC_SET_SR(base, value)  (BME_OR8(&DAC_SR_REG(base), (uint8_t)(value)))
3340 #define DAC_CLR_SR(base, value)  (BME_AND8(&DAC_SR_REG(base), (uint8_t)(~(value))))
3341 #define DAC_TOG_SR(base, value)  (BME_XOR8(&DAC_SR_REG(base), (uint8_t)(value)))
3342 /*@}*/
3343 
3344 /*
3345  * Constants & macros for individual DAC_SR bitfields
3346  */
3347 
3348 /*!
3349  * @name Register DAC_SR, field DACBFRPBF[0] (RW)
3350  *
3351  * Values:
3352  * - 0b0 - The DAC buffer read pointer is not equal to C2[DACBFUP].
3353  * - 0b1 - The DAC buffer read pointer is equal to C2[DACBFUP].
3354  */
3355 /*@{*/
3356 /*! @brief Read current value of the DAC_SR_DACBFRPBF field. */
3357 #define DAC_RD_SR_DACBFRPBF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFRPBF_MASK) >> DAC_SR_DACBFRPBF_SHIFT)
3358 #define DAC_BRD_SR_DACBFRPBF(base) (BME_UBFX8(&DAC_SR_REG(base), DAC_SR_DACBFRPBF_SHIFT, DAC_SR_DACBFRPBF_WIDTH))
3359 
3360 /*! @brief Set the DACBFRPBF field to a new value. */
3361 #define DAC_WR_SR_DACBFRPBF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFRPBF_MASK, DAC_SR_DACBFRPBF(value)))
3362 #define DAC_BWR_SR_DACBFRPBF(base, value) (BME_BFI8(&DAC_SR_REG(base), ((uint8_t)(value) << DAC_SR_DACBFRPBF_SHIFT), DAC_SR_DACBFRPBF_SHIFT, DAC_SR_DACBFRPBF_WIDTH))
3363 /*@}*/
3364 
3365 /*!
3366  * @name Register DAC_SR, field DACBFRPTF[1] (RW)
3367  *
3368  * Values:
3369  * - 0b0 - The DAC buffer read pointer is not zero.
3370  * - 0b1 - The DAC buffer read pointer is zero.
3371  */
3372 /*@{*/
3373 /*! @brief Read current value of the DAC_SR_DACBFRPTF field. */
3374 #define DAC_RD_SR_DACBFRPTF(base) ((DAC_SR_REG(base) & DAC_SR_DACBFRPTF_MASK) >> DAC_SR_DACBFRPTF_SHIFT)
3375 #define DAC_BRD_SR_DACBFRPTF(base) (BME_UBFX8(&DAC_SR_REG(base), DAC_SR_DACBFRPTF_SHIFT, DAC_SR_DACBFRPTF_WIDTH))
3376 
3377 /*! @brief Set the DACBFRPTF field to a new value. */
3378 #define DAC_WR_SR_DACBFRPTF(base, value) (DAC_RMW_SR(base, DAC_SR_DACBFRPTF_MASK, DAC_SR_DACBFRPTF(value)))
3379 #define DAC_BWR_SR_DACBFRPTF(base, value) (BME_BFI8(&DAC_SR_REG(base), ((uint8_t)(value) << DAC_SR_DACBFRPTF_SHIFT), DAC_SR_DACBFRPTF_SHIFT, DAC_SR_DACBFRPTF_WIDTH))
3380 /*@}*/
3381 
3382 /*******************************************************************************
3383  * DAC_C0 - DAC Control Register
3384  ******************************************************************************/
3385 
3386 /*!
3387  * @brief DAC_C0 - DAC Control Register (RW)
3388  *
3389  * Reset value: 0x00U
3390  *
3391  * Do not use 32- or 16-bit accesses to this register.
3392  */
3393 /*!
3394  * @name Constants and macros for entire DAC_C0 register
3395  */
3396 /*@{*/
3397 #define DAC_RD_C0(base)          (DAC_C0_REG(base))
3398 #define DAC_WR_C0(base, value)   (DAC_C0_REG(base) = (value))
3399 #define DAC_RMW_C0(base, mask, value) (DAC_WR_C0(base, (DAC_RD_C0(base) & ~(mask)) | (value)))
3400 #define DAC_SET_C0(base, value)  (BME_OR8(&DAC_C0_REG(base), (uint8_t)(value)))
3401 #define DAC_CLR_C0(base, value)  (BME_AND8(&DAC_C0_REG(base), (uint8_t)(~(value))))
3402 #define DAC_TOG_C0(base, value)  (BME_XOR8(&DAC_C0_REG(base), (uint8_t)(value)))
3403 /*@}*/
3404 
3405 /*
3406  * Constants & macros for individual DAC_C0 bitfields
3407  */
3408 
3409 /*!
3410  * @name Register DAC_C0, field DACBBIEN[0] (RW)
3411  *
3412  * Values:
3413  * - 0b0 - The DAC buffer read pointer bottom flag interrupt is disabled.
3414  * - 0b1 - The DAC buffer read pointer bottom flag interrupt is enabled.
3415  */
3416 /*@{*/
3417 /*! @brief Read current value of the DAC_C0_DACBBIEN field. */
3418 #define DAC_RD_C0_DACBBIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBBIEN_MASK) >> DAC_C0_DACBBIEN_SHIFT)
3419 #define DAC_BRD_C0_DACBBIEN(base) (BME_UBFX8(&DAC_C0_REG(base), DAC_C0_DACBBIEN_SHIFT, DAC_C0_DACBBIEN_WIDTH))
3420 
3421 /*! @brief Set the DACBBIEN field to a new value. */
3422 #define DAC_WR_C0_DACBBIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBBIEN_MASK, DAC_C0_DACBBIEN(value)))
3423 #define DAC_BWR_C0_DACBBIEN(base, value) (BME_BFI8(&DAC_C0_REG(base), ((uint8_t)(value) << DAC_C0_DACBBIEN_SHIFT), DAC_C0_DACBBIEN_SHIFT, DAC_C0_DACBBIEN_WIDTH))
3424 /*@}*/
3425 
3426 /*!
3427  * @name Register DAC_C0, field DACBTIEN[1] (RW)
3428  *
3429  * Values:
3430  * - 0b0 - The DAC buffer read pointer top flag interrupt is disabled.
3431  * - 0b1 - The DAC buffer read pointer top flag interrupt is enabled.
3432  */
3433 /*@{*/
3434 /*! @brief Read current value of the DAC_C0_DACBTIEN field. */
3435 #define DAC_RD_C0_DACBTIEN(base) ((DAC_C0_REG(base) & DAC_C0_DACBTIEN_MASK) >> DAC_C0_DACBTIEN_SHIFT)
3436 #define DAC_BRD_C0_DACBTIEN(base) (BME_UBFX8(&DAC_C0_REG(base), DAC_C0_DACBTIEN_SHIFT, DAC_C0_DACBTIEN_WIDTH))
3437 
3438 /*! @brief Set the DACBTIEN field to a new value. */
3439 #define DAC_WR_C0_DACBTIEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACBTIEN_MASK, DAC_C0_DACBTIEN(value)))
3440 #define DAC_BWR_C0_DACBTIEN(base, value) (BME_BFI8(&DAC_C0_REG(base), ((uint8_t)(value) << DAC_C0_DACBTIEN_SHIFT), DAC_C0_DACBTIEN_SHIFT, DAC_C0_DACBTIEN_WIDTH))
3441 /*@}*/
3442 
3443 /*!
3444  * @name Register DAC_C0, field LPEN[3] (RW)
3445  *
3446  * See the 12-bit DAC electrical characteristics of the device data sheet for
3447  * details on the impact of the modes below.
3448  *
3449  * Values:
3450  * - 0b0 - High-Power mode
3451  * - 0b1 - Low-Power mode
3452  */
3453 /*@{*/
3454 /*! @brief Read current value of the DAC_C0_LPEN field. */
3455 #define DAC_RD_C0_LPEN(base) ((DAC_C0_REG(base) & DAC_C0_LPEN_MASK) >> DAC_C0_LPEN_SHIFT)
3456 #define DAC_BRD_C0_LPEN(base) (BME_UBFX8(&DAC_C0_REG(base), DAC_C0_LPEN_SHIFT, DAC_C0_LPEN_WIDTH))
3457 
3458 /*! @brief Set the LPEN field to a new value. */
3459 #define DAC_WR_C0_LPEN(base, value) (DAC_RMW_C0(base, DAC_C0_LPEN_MASK, DAC_C0_LPEN(value)))
3460 #define DAC_BWR_C0_LPEN(base, value) (BME_BFI8(&DAC_C0_REG(base), ((uint8_t)(value) << DAC_C0_LPEN_SHIFT), DAC_C0_LPEN_SHIFT, DAC_C0_LPEN_WIDTH))
3461 /*@}*/
3462 
3463 /*!
3464  * @name Register DAC_C0, field DACSWTRG[4] (WORZ)
3465  *
3466  * Active high. This is a write-only field, which always reads 0. If DAC
3467  * software trigger is selected and buffer is enabled, writing 1 to this field will
3468  * advance the buffer read pointer once.
3469  *
3470  * Values:
3471  * - 0b0 - The DAC soft trigger is not valid.
3472  * - 0b1 - The DAC soft trigger is valid.
3473  */
3474 /*@{*/
3475 /*! @brief Set the DACSWTRG field to a new value. */
3476 #define DAC_WR_C0_DACSWTRG(base, value) (DAC_RMW_C0(base, DAC_C0_DACSWTRG_MASK, DAC_C0_DACSWTRG(value)))
3477 #define DAC_BWR_C0_DACSWTRG(base, value) (BME_BFI8(&DAC_C0_REG(base), ((uint8_t)(value) << DAC_C0_DACSWTRG_SHIFT), DAC_C0_DACSWTRG_SHIFT, DAC_C0_DACSWTRG_WIDTH))
3478 /*@}*/
3479 
3480 /*!
3481  * @name Register DAC_C0, field DACTRGSEL[5] (RW)
3482  *
3483  * Values:
3484  * - 0b0 - The DAC hardware trigger is selected.
3485  * - 0b1 - The DAC software trigger is selected.
3486  */
3487 /*@{*/
3488 /*! @brief Read current value of the DAC_C0_DACTRGSEL field. */
3489 #define DAC_RD_C0_DACTRGSEL(base) ((DAC_C0_REG(base) & DAC_C0_DACTRGSEL_MASK) >> DAC_C0_DACTRGSEL_SHIFT)
3490 #define DAC_BRD_C0_DACTRGSEL(base) (BME_UBFX8(&DAC_C0_REG(base), DAC_C0_DACTRGSEL_SHIFT, DAC_C0_DACTRGSEL_WIDTH))
3491 
3492 /*! @brief Set the DACTRGSEL field to a new value. */
3493 #define DAC_WR_C0_DACTRGSEL(base, value) (DAC_RMW_C0(base, DAC_C0_DACTRGSEL_MASK, DAC_C0_DACTRGSEL(value)))
3494 #define DAC_BWR_C0_DACTRGSEL(base, value) (BME_BFI8(&DAC_C0_REG(base), ((uint8_t)(value) << DAC_C0_DACTRGSEL_SHIFT), DAC_C0_DACTRGSEL_SHIFT, DAC_C0_DACTRGSEL_WIDTH))
3495 /*@}*/
3496 
3497 /*!
3498  * @name Register DAC_C0, field DACRFS[6] (RW)
3499  *
3500  * Values:
3501  * - 0b0 - The DAC selects DACREF_1 as the reference voltage.
3502  * - 0b1 - The DAC selects DACREF_2 as the reference voltage.
3503  */
3504 /*@{*/
3505 /*! @brief Read current value of the DAC_C0_DACRFS field. */
3506 #define DAC_RD_C0_DACRFS(base) ((DAC_C0_REG(base) & DAC_C0_DACRFS_MASK) >> DAC_C0_DACRFS_SHIFT)
3507 #define DAC_BRD_C0_DACRFS(base) (BME_UBFX8(&DAC_C0_REG(base), DAC_C0_DACRFS_SHIFT, DAC_C0_DACRFS_WIDTH))
3508 
3509 /*! @brief Set the DACRFS field to a new value. */
3510 #define DAC_WR_C0_DACRFS(base, value) (DAC_RMW_C0(base, DAC_C0_DACRFS_MASK, DAC_C0_DACRFS(value)))
3511 #define DAC_BWR_C0_DACRFS(base, value) (BME_BFI8(&DAC_C0_REG(base), ((uint8_t)(value) << DAC_C0_DACRFS_SHIFT), DAC_C0_DACRFS_SHIFT, DAC_C0_DACRFS_WIDTH))
3512 /*@}*/
3513 
3514 /*!
3515  * @name Register DAC_C0, field DACEN[7] (RW)
3516  *
3517  * Starts the Programmable Reference Generator operation.
3518  *
3519  * Values:
3520  * - 0b0 - The DAC system is disabled.
3521  * - 0b1 - The DAC system is enabled.
3522  */
3523 /*@{*/
3524 /*! @brief Read current value of the DAC_C0_DACEN field. */
3525 #define DAC_RD_C0_DACEN(base) ((DAC_C0_REG(base) & DAC_C0_DACEN_MASK) >> DAC_C0_DACEN_SHIFT)
3526 #define DAC_BRD_C0_DACEN(base) (BME_UBFX8(&DAC_C0_REG(base), DAC_C0_DACEN_SHIFT, DAC_C0_DACEN_WIDTH))
3527 
3528 /*! @brief Set the DACEN field to a new value. */
3529 #define DAC_WR_C0_DACEN(base, value) (DAC_RMW_C0(base, DAC_C0_DACEN_MASK, DAC_C0_DACEN(value)))
3530 #define DAC_BWR_C0_DACEN(base, value) (BME_BFI8(&DAC_C0_REG(base), ((uint8_t)(value) << DAC_C0_DACEN_SHIFT), DAC_C0_DACEN_SHIFT, DAC_C0_DACEN_WIDTH))
3531 /*@}*/
3532 
3533 /*******************************************************************************
3534  * DAC_C1 - DAC Control Register 1
3535  ******************************************************************************/
3536 
3537 /*!
3538  * @brief DAC_C1 - DAC Control Register 1 (RW)
3539  *
3540  * Reset value: 0x00U
3541  *
3542  * Do not use 32- or 16-bit accesses to this register.
3543  */
3544 /*!
3545  * @name Constants and macros for entire DAC_C1 register
3546  */
3547 /*@{*/
3548 #define DAC_RD_C1(base)          (DAC_C1_REG(base))
3549 #define DAC_WR_C1(base, value)   (DAC_C1_REG(base) = (value))
3550 #define DAC_RMW_C1(base, mask, value) (DAC_WR_C1(base, (DAC_RD_C1(base) & ~(mask)) | (value)))
3551 #define DAC_SET_C1(base, value)  (BME_OR8(&DAC_C1_REG(base), (uint8_t)(value)))
3552 #define DAC_CLR_C1(base, value)  (BME_AND8(&DAC_C1_REG(base), (uint8_t)(~(value))))
3553 #define DAC_TOG_C1(base, value)  (BME_XOR8(&DAC_C1_REG(base), (uint8_t)(value)))
3554 /*@}*/
3555 
3556 /*
3557  * Constants & macros for individual DAC_C1 bitfields
3558  */
3559 
3560 /*!
3561  * @name Register DAC_C1, field DACBFEN[0] (RW)
3562  *
3563  * Values:
3564  * - 0b0 - Buffer read pointer is disabled. The converted data is always the
3565  *     first word of the buffer.
3566  * - 0b1 - Buffer read pointer is enabled. The converted data is the word that
3567  *     the read pointer points to. It means converted data can be from any word of
3568  *     the buffer.
3569  */
3570 /*@{*/
3571 /*! @brief Read current value of the DAC_C1_DACBFEN field. */
3572 #define DAC_RD_C1_DACBFEN(base) ((DAC_C1_REG(base) & DAC_C1_DACBFEN_MASK) >> DAC_C1_DACBFEN_SHIFT)
3573 #define DAC_BRD_C1_DACBFEN(base) (BME_UBFX8(&DAC_C1_REG(base), DAC_C1_DACBFEN_SHIFT, DAC_C1_DACBFEN_WIDTH))
3574 
3575 /*! @brief Set the DACBFEN field to a new value. */
3576 #define DAC_WR_C1_DACBFEN(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFEN_MASK, DAC_C1_DACBFEN(value)))
3577 #define DAC_BWR_C1_DACBFEN(base, value) (BME_BFI8(&DAC_C1_REG(base), ((uint8_t)(value) << DAC_C1_DACBFEN_SHIFT), DAC_C1_DACBFEN_SHIFT, DAC_C1_DACBFEN_WIDTH))
3578 /*@}*/
3579 
3580 /*!
3581  * @name Register DAC_C1, field DACBFMD[2] (RW)
3582  *
3583  * Values:
3584  * - 0b0 - Normal mode
3585  * - 0b1 - One-Time Scan mode
3586  */
3587 /*@{*/
3588 /*! @brief Read current value of the DAC_C1_DACBFMD field. */
3589 #define DAC_RD_C1_DACBFMD(base) ((DAC_C1_REG(base) & DAC_C1_DACBFMD_MASK) >> DAC_C1_DACBFMD_SHIFT)
3590 #define DAC_BRD_C1_DACBFMD(base) (BME_UBFX8(&DAC_C1_REG(base), DAC_C1_DACBFMD_SHIFT, DAC_C1_DACBFMD_WIDTH))
3591 
3592 /*! @brief Set the DACBFMD field to a new value. */
3593 #define DAC_WR_C1_DACBFMD(base, value) (DAC_RMW_C1(base, DAC_C1_DACBFMD_MASK, DAC_C1_DACBFMD(value)))
3594 #define DAC_BWR_C1_DACBFMD(base, value) (BME_BFI8(&DAC_C1_REG(base), ((uint8_t)(value) << DAC_C1_DACBFMD_SHIFT), DAC_C1_DACBFMD_SHIFT, DAC_C1_DACBFMD_WIDTH))
3595 /*@}*/
3596 
3597 /*!
3598  * @name Register DAC_C1, field DMAEN[7] (RW)
3599  *
3600  * Values:
3601  * - 0b0 - DMA is disabled.
3602  * - 0b1 - DMA is enabled. When DMA is enabled, the DMA request will be
3603  *     generated by original interrupts. The interrupts will not be presented on this
3604  *     module at the same time.
3605  */
3606 /*@{*/
3607 /*! @brief Read current value of the DAC_C1_DMAEN field. */
3608 #define DAC_RD_C1_DMAEN(base) ((DAC_C1_REG(base) & DAC_C1_DMAEN_MASK) >> DAC_C1_DMAEN_SHIFT)
3609 #define DAC_BRD_C1_DMAEN(base) (BME_UBFX8(&DAC_C1_REG(base), DAC_C1_DMAEN_SHIFT, DAC_C1_DMAEN_WIDTH))
3610 
3611 /*! @brief Set the DMAEN field to a new value. */
3612 #define DAC_WR_C1_DMAEN(base, value) (DAC_RMW_C1(base, DAC_C1_DMAEN_MASK, DAC_C1_DMAEN(value)))
3613 #define DAC_BWR_C1_DMAEN(base, value) (BME_BFI8(&DAC_C1_REG(base), ((uint8_t)(value) << DAC_C1_DMAEN_SHIFT), DAC_C1_DMAEN_SHIFT, DAC_C1_DMAEN_WIDTH))
3614 /*@}*/
3615 
3616 /*******************************************************************************
3617  * DAC_C2 - DAC Control Register 2
3618  ******************************************************************************/
3619 
3620 /*!
3621  * @brief DAC_C2 - DAC Control Register 2 (RW)
3622  *
3623  * Reset value: 0x01U
3624  */
3625 /*!
3626  * @name Constants and macros for entire DAC_C2 register
3627  */
3628 /*@{*/
3629 #define DAC_RD_C2(base)          (DAC_C2_REG(base))
3630 #define DAC_WR_C2(base, value)   (DAC_C2_REG(base) = (value))
3631 #define DAC_RMW_C2(base, mask, value) (DAC_WR_C2(base, (DAC_RD_C2(base) & ~(mask)) | (value)))
3632 #define DAC_SET_C2(base, value)  (BME_OR8(&DAC_C2_REG(base), (uint8_t)(value)))
3633 #define DAC_CLR_C2(base, value)  (BME_AND8(&DAC_C2_REG(base), (uint8_t)(~(value))))
3634 #define DAC_TOG_C2(base, value)  (BME_XOR8(&DAC_C2_REG(base), (uint8_t)(value)))
3635 /*@}*/
3636 
3637 /*
3638  * Constants & macros for individual DAC_C2 bitfields
3639  */
3640 
3641 /*!
3642  * @name Register DAC_C2, field DACBFUP[0] (RW)
3643  *
3644  * Selects the upper limit of the DAC buffer. The buffer read pointer cannot
3645  * exceed it.
3646  */
3647 /*@{*/
3648 /*! @brief Read current value of the DAC_C2_DACBFUP field. */
3649 #define DAC_RD_C2_DACBFUP(base) ((DAC_C2_REG(base) & DAC_C2_DACBFUP_MASK) >> DAC_C2_DACBFUP_SHIFT)
3650 #define DAC_BRD_C2_DACBFUP(base) (BME_UBFX8(&DAC_C2_REG(base), DAC_C2_DACBFUP_SHIFT, DAC_C2_DACBFUP_WIDTH))
3651 
3652 /*! @brief Set the DACBFUP field to a new value. */
3653 #define DAC_WR_C2_DACBFUP(base, value) (DAC_RMW_C2(base, DAC_C2_DACBFUP_MASK, DAC_C2_DACBFUP(value)))
3654 #define DAC_BWR_C2_DACBFUP(base, value) (BME_BFI8(&DAC_C2_REG(base), ((uint8_t)(value) << DAC_C2_DACBFUP_SHIFT), DAC_C2_DACBFUP_SHIFT, DAC_C2_DACBFUP_WIDTH))
3655 /*@}*/
3656 
3657 /*!
3658  * @name Register DAC_C2, field DACBFRP[4] (RW)
3659  *
3660  * Keeps the current value of the buffer read pointer.
3661  */
3662 /*@{*/
3663 /*! @brief Read current value of the DAC_C2_DACBFRP field. */
3664 #define DAC_RD_C2_DACBFRP(base) ((DAC_C2_REG(base) & DAC_C2_DACBFRP_MASK) >> DAC_C2_DACBFRP_SHIFT)
3665 #define DAC_BRD_C2_DACBFRP(base) (BME_UBFX8(&DAC_C2_REG(base), DAC_C2_DACBFRP_SHIFT, DAC_C2_DACBFRP_WIDTH))
3666 
3667 /*! @brief Set the DACBFRP field to a new value. */
3668 #define DAC_WR_C2_DACBFRP(base, value) (DAC_RMW_C2(base, DAC_C2_DACBFRP_MASK, DAC_C2_DACBFRP(value)))
3669 #define DAC_BWR_C2_DACBFRP(base, value) (BME_BFI8(&DAC_C2_REG(base), ((uint8_t)(value) << DAC_C2_DACBFRP_SHIFT), DAC_C2_DACBFRP_SHIFT, DAC_C2_DACBFRP_WIDTH))
3670 /*@}*/
3671 
3672 /*
3673  * MKW40Z4 DCDC
3674  *
3675  * DC to DC Converter
3676  *
3677  * Registers defined in this header file:
3678  * - DCDC_REG0 - DCDC REGISTER 0
3679  * - DCDC_REG1 - DCDC REGISTER 1
3680  * - DCDC_REG2 - DCDC REGISTER 2
3681  * - DCDC_REG3 - DCDC REGISTER 3
3682  * - DCDC_REG4 - DCDC REGISTER 4
3683  * - DCDC_REG6 - DCDC REGISTER 6
3684  * - DCDC_REG7 - DCDC REGISTER 7
3685  */
3686 
3687 #define DCDC_INSTANCE_COUNT (1U) /*!< Number of instances of the DCDC module. */
3688 #define DCDC_IDX (0U) /*!< Instance number for DCDC. */
3689 
3690 /*******************************************************************************
3691  * DCDC_REG0 - DCDC REGISTER 0
3692  ******************************************************************************/
3693 
3694 /*!
3695  * @brief DCDC_REG0 - DCDC REGISTER 0 (RW)
3696  *
3697  * Reset value: 0x04180000U
3698  */
3699 /*!
3700  * @name Constants and macros for entire DCDC_REG0 register
3701  */
3702 /*@{*/
3703 #define DCDC_RD_REG0(base)       (DCDC_REG0_REG(base))
3704 #define DCDC_WR_REG0(base, value) (DCDC_REG0_REG(base) = (value))
3705 #define DCDC_RMW_REG0(base, mask, value) (DCDC_WR_REG0(base, (DCDC_RD_REG0(base) & ~(mask)) | (value)))
3706 #define DCDC_SET_REG0(base, value) (BME_OR32(&DCDC_REG0_REG(base), (uint32_t)(value)))
3707 #define DCDC_CLR_REG0(base, value) (BME_AND32(&DCDC_REG0_REG(base), (uint32_t)(~(value))))
3708 #define DCDC_TOG_REG0(base, value) (BME_XOR32(&DCDC_REG0_REG(base), (uint32_t)(value)))
3709 /*@}*/
3710 
3711 /*
3712  * Constants & macros for individual DCDC_REG0 bitfields
3713  */
3714 
3715 /*!
3716  * @name Register DCDC_REG0, field DCDC_DISABLE_AUTO_CLK_SWITCH[1] (RW)
3717  *
3718  * Disable automatic clock switch from internal oscillator to external clock.
3719  */
3720 /*@{*/
3721 /*! @brief Read current value of the DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH field. */
3722 #define DCDC_RD_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH(base) ((DCDC_REG0_REG(base) & DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_MASK) >> DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_SHIFT)
3723 #define DCDC_BRD_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_SHIFT, DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_WIDTH))
3724 
3725 /*! @brief Set the DCDC_DISABLE_AUTO_CLK_SWITCH field to a new value. */
3726 #define DCDC_WR_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_MASK, DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH(value)))
3727 #define DCDC_BWR_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(value) << DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_SHIFT), DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_SHIFT, DCDC_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH_WIDTH))
3728 /*@}*/
3729 
3730 /*!
3731  * @name Register DCDC_REG0, field DCDC_SEL_CLK[2] (RW)
3732  *
3733  * Select external clock for DCDC when DCDC_DISABLE_AUTO_CLK_SWITCH is set.
3734  */
3735 /*@{*/
3736 /*! @brief Read current value of the DCDC_REG0_DCDC_SEL_CLK field. */
3737 #define DCDC_RD_REG0_DCDC_SEL_CLK(base) ((DCDC_REG0_REG(base) & DCDC_REG0_DCDC_SEL_CLK_MASK) >> DCDC_REG0_DCDC_SEL_CLK_SHIFT)
3738 #define DCDC_BRD_REG0_DCDC_SEL_CLK(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_SEL_CLK_SHIFT, DCDC_REG0_DCDC_SEL_CLK_WIDTH))
3739 
3740 /*! @brief Set the DCDC_SEL_CLK field to a new value. */
3741 #define DCDC_WR_REG0_DCDC_SEL_CLK(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_SEL_CLK_MASK, DCDC_REG0_DCDC_SEL_CLK(value)))
3742 #define DCDC_BWR_REG0_DCDC_SEL_CLK(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(value) << DCDC_REG0_DCDC_SEL_CLK_SHIFT), DCDC_REG0_DCDC_SEL_CLK_SHIFT, DCDC_REG0_DCDC_SEL_CLK_WIDTH))
3743 /*@}*/
3744 
3745 /*!
3746  * @name Register DCDC_REG0, field DCDC_PWD_OSC_INT[3] (RW)
3747  *
3748  * Power down internal oscillator. Only set this bit when 32M crystal oscillator
3749  * is available.
3750  */
3751 /*@{*/
3752 /*! @brief Read current value of the DCDC_REG0_DCDC_PWD_OSC_INT field. */
3753 #define DCDC_RD_REG0_DCDC_PWD_OSC_INT(base) ((DCDC_REG0_REG(base) & DCDC_REG0_DCDC_PWD_OSC_INT_MASK) >> DCDC_REG0_DCDC_PWD_OSC_INT_SHIFT)
3754 #define DCDC_BRD_REG0_DCDC_PWD_OSC_INT(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_PWD_OSC_INT_SHIFT, DCDC_REG0_DCDC_PWD_OSC_INT_WIDTH))
3755 
3756 /*! @brief Set the DCDC_PWD_OSC_INT field to a new value. */
3757 #define DCDC_WR_REG0_DCDC_PWD_OSC_INT(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_PWD_OSC_INT_MASK, DCDC_REG0_DCDC_PWD_OSC_INT(value)))
3758 #define DCDC_BWR_REG0_DCDC_PWD_OSC_INT(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(value) << DCDC_REG0_DCDC_PWD_OSC_INT_SHIFT), DCDC_REG0_DCDC_PWD_OSC_INT_SHIFT, DCDC_REG0_DCDC_PWD_OSC_INT_WIDTH))
3759 /*@}*/
3760 
3761 /*!
3762  * @name Register DCDC_REG0, field DCDC_LP_DF_CMP_ENABLE[9] (RW)
3763  *
3764  * Enable low power differential comparators, to sense lower supply in pulsed
3765  * mode. This can reduce the ripple in pulsed mode.
3766  */
3767 /*@{*/
3768 /*! @brief Read current value of the DCDC_REG0_DCDC_LP_DF_CMP_ENABLE field. */
3769 #define DCDC_RD_REG0_DCDC_LP_DF_CMP_ENABLE(base) ((DCDC_REG0_REG(base) & DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_MASK) >> DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_SHIFT)
3770 #define DCDC_BRD_REG0_DCDC_LP_DF_CMP_ENABLE(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_SHIFT, DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_WIDTH))
3771 
3772 /*! @brief Set the DCDC_LP_DF_CMP_ENABLE field to a new value. */
3773 #define DCDC_WR_REG0_DCDC_LP_DF_CMP_ENABLE(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_MASK, DCDC_REG0_DCDC_LP_DF_CMP_ENABLE(value)))
3774 #define DCDC_BWR_REG0_DCDC_LP_DF_CMP_ENABLE(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(value) << DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_SHIFT), DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_SHIFT, DCDC_REG0_DCDC_LP_DF_CMP_ENABLE_WIDTH))
3775 /*@}*/
3776 
3777 /*!
3778  * @name Register DCDC_REG0, field DCDC_VBAT_DIV_CTRL[11:10] (RW)
3779  *
3780  * Controls VBAT voltage divider. The divided VBAT output is input to an ADC
3781  * channel which allows the battery voltage to be measured.
3782  */
3783 /*@{*/
3784 /*! @brief Read current value of the DCDC_REG0_DCDC_VBAT_DIV_CTRL field. */
3785 #define DCDC_RD_REG0_DCDC_VBAT_DIV_CTRL(base) ((DCDC_REG0_REG(base) & DCDC_REG0_DCDC_VBAT_DIV_CTRL_MASK) >> DCDC_REG0_DCDC_VBAT_DIV_CTRL_SHIFT)
3786 #define DCDC_BRD_REG0_DCDC_VBAT_DIV_CTRL(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_VBAT_DIV_CTRL_SHIFT, DCDC_REG0_DCDC_VBAT_DIV_CTRL_WIDTH))
3787 
3788 /*! @brief Set the DCDC_VBAT_DIV_CTRL field to a new value. */
3789 #define DCDC_WR_REG0_DCDC_VBAT_DIV_CTRL(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_VBAT_DIV_CTRL_MASK, DCDC_REG0_DCDC_VBAT_DIV_CTRL(value)))
3790 #define DCDC_BWR_REG0_DCDC_VBAT_DIV_CTRL(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(value) << DCDC_REG0_DCDC_VBAT_DIV_CTRL_SHIFT), DCDC_REG0_DCDC_VBAT_DIV_CTRL_SHIFT, DCDC_REG0_DCDC_VBAT_DIV_CTRL_WIDTH))
3791 /*@}*/
3792 
3793 /*!
3794  * @name Register DCDC_REG0, field DCDC_LP_STATE_HYS_L[18:17] (RW)
3795  *
3796  * Configure the hysteretic lower threshold value in low power mode. It
3797  * determines the hysteretic value of the output voltage in pulsed mode.
3798  *
3799  * Values:
3800  * - 0b00 - Target voltage value - 0 mV
3801  * - 0b01 - Target voltage value - 25 mV
3802  * - 0b10 - Target voltage value - 50 mV
3803  * - 0b11 - Target voltage value - 75 mV
3804  */
3805 /*@{*/
3806 /*! @brief Read current value of the DCDC_REG0_DCDC_LP_STATE_HYS_L field. */
3807 #define DCDC_RD_REG0_DCDC_LP_STATE_HYS_L(base) ((DCDC_REG0_REG(base) & DCDC_REG0_DCDC_LP_STATE_HYS_L_MASK) >> DCDC_REG0_DCDC_LP_STATE_HYS_L_SHIFT)
3808 #define DCDC_BRD_REG0_DCDC_LP_STATE_HYS_L(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_LP_STATE_HYS_L_SHIFT, DCDC_REG0_DCDC_LP_STATE_HYS_L_WIDTH))
3809 
3810 /*! @brief Set the DCDC_LP_STATE_HYS_L field to a new value. */
3811 #define DCDC_WR_REG0_DCDC_LP_STATE_HYS_L(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_LP_STATE_HYS_L_MASK, DCDC_REG0_DCDC_LP_STATE_HYS_L(value)))
3812 #define DCDC_BWR_REG0_DCDC_LP_STATE_HYS_L(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(value) << DCDC_REG0_DCDC_LP_STATE_HYS_L_SHIFT), DCDC_REG0_DCDC_LP_STATE_HYS_L_SHIFT, DCDC_REG0_DCDC_LP_STATE_HYS_L_WIDTH))
3813 /*@}*/
3814 
3815 /*!
3816  * @name Register DCDC_REG0, field DCDC_LP_STATE_HYS_H[20:19] (RW)
3817  *
3818  * Configure the hysteretic upper threshold value in low power mode. It
3819  * determines the hysteretic value of the output voltage in pulsed mode.
3820  *
3821  * Values:
3822  * - 0b00 - Target voltage value + 0 mV
3823  * - 0b01 - Target voltage value + 25 mV
3824  * - 0b10 - Target voltage value + 50 mV
3825  * - 0b11 - Target voltage value + 75 mV
3826  */
3827 /*@{*/
3828 /*! @brief Read current value of the DCDC_REG0_DCDC_LP_STATE_HYS_H field. */
3829 #define DCDC_RD_REG0_DCDC_LP_STATE_HYS_H(base) ((DCDC_REG0_REG(base) & DCDC_REG0_DCDC_LP_STATE_HYS_H_MASK) >> DCDC_REG0_DCDC_LP_STATE_HYS_H_SHIFT)
3830 #define DCDC_BRD_REG0_DCDC_LP_STATE_HYS_H(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_LP_STATE_HYS_H_SHIFT, DCDC_REG0_DCDC_LP_STATE_HYS_H_WIDTH))
3831 
3832 /*! @brief Set the DCDC_LP_STATE_HYS_H field to a new value. */
3833 #define DCDC_WR_REG0_DCDC_LP_STATE_HYS_H(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_LP_STATE_HYS_H_MASK, DCDC_REG0_DCDC_LP_STATE_HYS_H(value)))
3834 #define DCDC_BWR_REG0_DCDC_LP_STATE_HYS_H(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(value) << DCDC_REG0_DCDC_LP_STATE_HYS_H_SHIFT), DCDC_REG0_DCDC_LP_STATE_HYS_H_SHIFT, DCDC_REG0_DCDC_LP_STATE_HYS_H_WIDTH))
3835 /*@}*/
3836 
3837 /*!
3838  * @name Register DCDC_REG0, field HYST_LP_COMP_ADJ[21] (RW)
3839  *
3840  * Adjust hysteretic value in low power comparator.
3841  */
3842 /*@{*/
3843 /*! @brief Read current value of the DCDC_REG0_HYST_LP_COMP_ADJ field. */
3844 #define DCDC_RD_REG0_HYST_LP_COMP_ADJ(base) ((DCDC_REG0_REG(base) & DCDC_REG0_HYST_LP_COMP_ADJ_MASK) >> DCDC_REG0_HYST_LP_COMP_ADJ_SHIFT)
3845 #define DCDC_BRD_REG0_HYST_LP_COMP_ADJ(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_HYST_LP_COMP_ADJ_SHIFT, DCDC_REG0_HYST_LP_COMP_ADJ_WIDTH))
3846 
3847 /*! @brief Set the HYST_LP_COMP_ADJ field to a new value. */
3848 #define DCDC_WR_REG0_HYST_LP_COMP_ADJ(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_HYST_LP_COMP_ADJ_MASK, DCDC_REG0_HYST_LP_COMP_ADJ(value)))
3849 #define DCDC_BWR_REG0_HYST_LP_COMP_ADJ(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(value) << DCDC_REG0_HYST_LP_COMP_ADJ_SHIFT), DCDC_REG0_HYST_LP_COMP_ADJ_SHIFT, DCDC_REG0_HYST_LP_COMP_ADJ_WIDTH))
3850 /*@}*/
3851 
3852 /*!
3853  * @name Register DCDC_REG0, field HYST_LP_CMP_DISABLE[22] (RW)
3854  *
3855  * Disable hysteresis in low power comparator.
3856  */
3857 /*@{*/
3858 /*! @brief Read current value of the DCDC_REG0_HYST_LP_CMP_DISABLE field. */
3859 #define DCDC_RD_REG0_HYST_LP_CMP_DISABLE(base) ((DCDC_REG0_REG(base) & DCDC_REG0_HYST_LP_CMP_DISABLE_MASK) >> DCDC_REG0_HYST_LP_CMP_DISABLE_SHIFT)
3860 #define DCDC_BRD_REG0_HYST_LP_CMP_DISABLE(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_HYST_LP_CMP_DISABLE_SHIFT, DCDC_REG0_HYST_LP_CMP_DISABLE_WIDTH))
3861 
3862 /*! @brief Set the HYST_LP_CMP_DISABLE field to a new value. */
3863 #define DCDC_WR_REG0_HYST_LP_CMP_DISABLE(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_HYST_LP_CMP_DISABLE_MASK, DCDC_REG0_HYST_LP_CMP_DISABLE(value)))
3864 #define DCDC_BWR_REG0_HYST_LP_CMP_DISABLE(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(value) << DCDC_REG0_HYST_LP_CMP_DISABLE_SHIFT), DCDC_REG0_HYST_LP_CMP_DISABLE_SHIFT, DCDC_REG0_HYST_LP_CMP_DISABLE_WIDTH))
3865 /*@}*/
3866 
3867 /*!
3868  * @name Register DCDC_REG0, field OFFSET_RSNS_LP_ADJ[23] (RW)
3869  *
3870  * Adjust hysteretic value in low power voltage sense.
3871  */
3872 /*@{*/
3873 /*! @brief Read current value of the DCDC_REG0_OFFSET_RSNS_LP_ADJ field. */
3874 #define DCDC_RD_REG0_OFFSET_RSNS_LP_ADJ(base) ((DCDC_REG0_REG(base) & DCDC_REG0_OFFSET_RSNS_LP_ADJ_MASK) >> DCDC_REG0_OFFSET_RSNS_LP_ADJ_SHIFT)
3875 #define DCDC_BRD_REG0_OFFSET_RSNS_LP_ADJ(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_OFFSET_RSNS_LP_ADJ_SHIFT, DCDC_REG0_OFFSET_RSNS_LP_ADJ_WIDTH))
3876 
3877 /*! @brief Set the OFFSET_RSNS_LP_ADJ field to a new value. */
3878 #define DCDC_WR_REG0_OFFSET_RSNS_LP_ADJ(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_OFFSET_RSNS_LP_ADJ_MASK, DCDC_REG0_OFFSET_RSNS_LP_ADJ(value)))
3879 #define DCDC_BWR_REG0_OFFSET_RSNS_LP_ADJ(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(value) << DCDC_REG0_OFFSET_RSNS_LP_ADJ_SHIFT), DCDC_REG0_OFFSET_RSNS_LP_ADJ_SHIFT, DCDC_REG0_OFFSET_RSNS_LP_ADJ_WIDTH))
3880 /*@}*/
3881 
3882 /*!
3883  * @name Register DCDC_REG0, field OFFSET_RSNS_LP_DISABLE[24] (RW)
3884  *
3885  * Disable hysteresis in low power voltage sense.
3886  */
3887 /*@{*/
3888 /*! @brief Read current value of the DCDC_REG0_OFFSET_RSNS_LP_DISABLE field. */
3889 #define DCDC_RD_REG0_OFFSET_RSNS_LP_DISABLE(base) ((DCDC_REG0_REG(base) & DCDC_REG0_OFFSET_RSNS_LP_DISABLE_MASK) >> DCDC_REG0_OFFSET_RSNS_LP_DISABLE_SHIFT)
3890 #define DCDC_BRD_REG0_OFFSET_RSNS_LP_DISABLE(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_OFFSET_RSNS_LP_DISABLE_SHIFT, DCDC_REG0_OFFSET_RSNS_LP_DISABLE_WIDTH))
3891 
3892 /*! @brief Set the OFFSET_RSNS_LP_DISABLE field to a new value. */
3893 #define DCDC_WR_REG0_OFFSET_RSNS_LP_DISABLE(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_OFFSET_RSNS_LP_DISABLE_MASK, DCDC_REG0_OFFSET_RSNS_LP_DISABLE(value)))
3894 #define DCDC_BWR_REG0_OFFSET_RSNS_LP_DISABLE(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(value) << DCDC_REG0_OFFSET_RSNS_LP_DISABLE_SHIFT), DCDC_REG0_OFFSET_RSNS_LP_DISABLE_SHIFT, DCDC_REG0_OFFSET_RSNS_LP_DISABLE_WIDTH))
3895 /*@}*/
3896 
3897 /*!
3898  * @name Register DCDC_REG0, field DCDC_LESS_I[25] (RW)
3899  *
3900  * Reduce DCDC current. It will save approximately 20uA in RUN.
3901  */
3902 /*@{*/
3903 /*! @brief Read current value of the DCDC_REG0_DCDC_LESS_I field. */
3904 #define DCDC_RD_REG0_DCDC_LESS_I(base) ((DCDC_REG0_REG(base) & DCDC_REG0_DCDC_LESS_I_MASK) >> DCDC_REG0_DCDC_LESS_I_SHIFT)
3905 #define DCDC_BRD_REG0_DCDC_LESS_I(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_LESS_I_SHIFT, DCDC_REG0_DCDC_LESS_I_WIDTH))
3906 
3907 /*! @brief Set the DCDC_LESS_I field to a new value. */
3908 #define DCDC_WR_REG0_DCDC_LESS_I(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_LESS_I_MASK, DCDC_REG0_DCDC_LESS_I(value)))
3909 #define DCDC_BWR_REG0_DCDC_LESS_I(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(value) << DCDC_REG0_DCDC_LESS_I_SHIFT), DCDC_REG0_DCDC_LESS_I_SHIFT, DCDC_REG0_DCDC_LESS_I_WIDTH))
3910 /*@}*/
3911 
3912 /*!
3913  * @name Register DCDC_REG0, field PWD_CMP_OFFSET[26] (RW)
3914  *
3915  * Power down output range comparator
3916  */
3917 /*@{*/
3918 /*! @brief Read current value of the DCDC_REG0_PWD_CMP_OFFSET field. */
3919 #define DCDC_RD_REG0_PWD_CMP_OFFSET(base) ((DCDC_REG0_REG(base) & DCDC_REG0_PWD_CMP_OFFSET_MASK) >> DCDC_REG0_PWD_CMP_OFFSET_SHIFT)
3920 #define DCDC_BRD_REG0_PWD_CMP_OFFSET(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_PWD_CMP_OFFSET_SHIFT, DCDC_REG0_PWD_CMP_OFFSET_WIDTH))
3921 
3922 /*! @brief Set the PWD_CMP_OFFSET field to a new value. */
3923 #define DCDC_WR_REG0_PWD_CMP_OFFSET(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_PWD_CMP_OFFSET_MASK, DCDC_REG0_PWD_CMP_OFFSET(value)))
3924 #define DCDC_BWR_REG0_PWD_CMP_OFFSET(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(value) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT), DCDC_REG0_PWD_CMP_OFFSET_SHIFT, DCDC_REG0_PWD_CMP_OFFSET_WIDTH))
3925 /*@}*/
3926 
3927 /*!
3928  * @name Register DCDC_REG0, field DCDC_XTALOK_DISABLE[27] (RW)
3929  *
3930  * Disable xtalok detection circuit.
3931  */
3932 /*@{*/
3933 /*! @brief Read current value of the DCDC_REG0_DCDC_XTALOK_DISABLE field. */
3934 #define DCDC_RD_REG0_DCDC_XTALOK_DISABLE(base) ((DCDC_REG0_REG(base) & DCDC_REG0_DCDC_XTALOK_DISABLE_MASK) >> DCDC_REG0_DCDC_XTALOK_DISABLE_SHIFT)
3935 #define DCDC_BRD_REG0_DCDC_XTALOK_DISABLE(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_XTALOK_DISABLE_SHIFT, DCDC_REG0_DCDC_XTALOK_DISABLE_WIDTH))
3936 
3937 /*! @brief Set the DCDC_XTALOK_DISABLE field to a new value. */
3938 #define DCDC_WR_REG0_DCDC_XTALOK_DISABLE(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_XTALOK_DISABLE_MASK, DCDC_REG0_DCDC_XTALOK_DISABLE(value)))
3939 #define DCDC_BWR_REG0_DCDC_XTALOK_DISABLE(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(value) << DCDC_REG0_DCDC_XTALOK_DISABLE_SHIFT), DCDC_REG0_DCDC_XTALOK_DISABLE_SHIFT, DCDC_REG0_DCDC_XTALOK_DISABLE_WIDTH))
3940 /*@}*/
3941 
3942 /*!
3943  * @name Register DCDC_REG0, field PSWITCH_STATUS[28] (RO)
3944  *
3945  * Status register to indicate PSWITCH status
3946  */
3947 /*@{*/
3948 /*! @brief Read current value of the DCDC_REG0_PSWITCH_STATUS field. */
3949 #define DCDC_RD_REG0_PSWITCH_STATUS(base) ((DCDC_REG0_REG(base) & DCDC_REG0_PSWITCH_STATUS_MASK) >> DCDC_REG0_PSWITCH_STATUS_SHIFT)
3950 #define DCDC_BRD_REG0_PSWITCH_STATUS(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_PSWITCH_STATUS_SHIFT, DCDC_REG0_PSWITCH_STATUS_WIDTH))
3951 /*@}*/
3952 
3953 /*!
3954  * @name Register DCDC_REG0, field VLPS_CONFIG_DCDC_HP[29] (RW)
3955  *
3956  * Selects behavior of DCDC in device VLPS low power mode. Pulsed mode is a
3957  * lower power mode. It can be used if the loads are small (<=0.5mA) in VLPx modes.
3958  */
3959 /*@{*/
3960 /*! @brief Read current value of the DCDC_REG0_VLPS_CONFIG_DCDC_HP field. */
3961 #define DCDC_RD_REG0_VLPS_CONFIG_DCDC_HP(base) ((DCDC_REG0_REG(base) & DCDC_REG0_VLPS_CONFIG_DCDC_HP_MASK) >> DCDC_REG0_VLPS_CONFIG_DCDC_HP_SHIFT)
3962 #define DCDC_BRD_REG0_VLPS_CONFIG_DCDC_HP(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_VLPS_CONFIG_DCDC_HP_SHIFT, DCDC_REG0_VLPS_CONFIG_DCDC_HP_WIDTH))
3963 
3964 /*! @brief Set the VLPS_CONFIG_DCDC_HP field to a new value. */
3965 #define DCDC_WR_REG0_VLPS_CONFIG_DCDC_HP(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_VLPS_CONFIG_DCDC_HP_MASK, DCDC_REG0_VLPS_CONFIG_DCDC_HP(value)))
3966 #define DCDC_BWR_REG0_VLPS_CONFIG_DCDC_HP(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(value) << DCDC_REG0_VLPS_CONFIG_DCDC_HP_SHIFT), DCDC_REG0_VLPS_CONFIG_DCDC_HP_SHIFT, DCDC_REG0_VLPS_CONFIG_DCDC_HP_WIDTH))
3967 /*@}*/
3968 
3969 /*!
3970  * @name Register DCDC_REG0, field VLPR_VLPW_CONFIG_DCDC_HP[30] (RW)
3971  *
3972  * Selects behavior of DCDC in device VLPR and VLPW low power modes. Pulsed mode
3973  * is a lower power mode. It can be used if the loads are small (<=0.5mA) in
3974  * VLPx modes.
3975  */
3976 /*@{*/
3977 /*! @brief Read current value of the DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP field. */
3978 #define DCDC_RD_REG0_VLPR_VLPW_CONFIG_DCDC_HP(base) ((DCDC_REG0_REG(base) & DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_MASK) >> DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_SHIFT)
3979 #define DCDC_BRD_REG0_VLPR_VLPW_CONFIG_DCDC_HP(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_SHIFT, DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_WIDTH))
3980 
3981 /*! @brief Set the VLPR_VLPW_CONFIG_DCDC_HP field to a new value. */
3982 #define DCDC_WR_REG0_VLPR_VLPW_CONFIG_DCDC_HP(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_MASK, DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP(value)))
3983 #define DCDC_BWR_REG0_VLPR_VLPW_CONFIG_DCDC_HP(base, value) (BME_BFI32(&DCDC_REG0_REG(base), ((uint32_t)(value) << DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_SHIFT), DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_SHIFT, DCDC_REG0_VLPR_VLPW_CONFIG_DCDC_HP_WIDTH))
3984 /*@}*/
3985 
3986 /*!
3987  * @name Register DCDC_REG0, field DCDC_STS_DC_OK[31] (RO)
3988  *
3989  * Status register to indicate DCDC lock. The lock time depends on the loading
3990  * and the DCDC mode. When changing output voltage target, it will take
3991  * approximately (0.5ms* target change steps). In pulsed mode, it will take approximately
3992  * 5ms. In startup, it will take approximately 50ms.
3993  */
3994 /*@{*/
3995 /*! @brief Read current value of the DCDC_REG0_DCDC_STS_DC_OK field. */
3996 #define DCDC_RD_REG0_DCDC_STS_DC_OK(base) ((DCDC_REG0_REG(base) & DCDC_REG0_DCDC_STS_DC_OK_MASK) >> DCDC_REG0_DCDC_STS_DC_OK_SHIFT)
3997 #define DCDC_BRD_REG0_DCDC_STS_DC_OK(base) (BME_UBFX32(&DCDC_REG0_REG(base), DCDC_REG0_DCDC_STS_DC_OK_SHIFT, DCDC_REG0_DCDC_STS_DC_OK_WIDTH))
3998 /*@}*/
3999 
4000 /*******************************************************************************
4001  * DCDC_REG1 - DCDC REGISTER 1
4002  ******************************************************************************/
4003 
4004 /*!
4005  * @brief DCDC_REG1 - DCDC REGISTER 1 (RW)
4006  *
4007  * Reset value: 0x0017C21CU
4008  */
4009 /*!
4010  * @name Constants and macros for entire DCDC_REG1 register
4011  */
4012 /*@{*/
4013 #define DCDC_RD_REG1(base)       (DCDC_REG1_REG(base))
4014 #define DCDC_WR_REG1(base, value) (DCDC_REG1_REG(base) = (value))
4015 #define DCDC_RMW_REG1(base, mask, value) (DCDC_WR_REG1(base, (DCDC_RD_REG1(base) & ~(mask)) | (value)))
4016 #define DCDC_SET_REG1(base, value) (BME_OR32(&DCDC_REG1_REG(base), (uint32_t)(value)))
4017 #define DCDC_CLR_REG1(base, value) (BME_AND32(&DCDC_REG1_REG(base), (uint32_t)(~(value))))
4018 #define DCDC_TOG_REG1(base, value) (BME_XOR32(&DCDC_REG1_REG(base), (uint32_t)(value)))
4019 /*@}*/
4020 
4021 /*
4022  * Constants & macros for individual DCDC_REG1 bitfields
4023  */
4024 
4025 /*!
4026  * @name Register DCDC_REG1, field POSLIMIT_BUCK_IN[6:0] (RW)
4027  *
4028  * Upper limit duty cycle limit in DC-DC converter. This field limits the
4029  * maximum VDDIO achievable for a given battery voltage, and its value may be increased
4030  * if very low battery operation is met.
4031  */
4032 /*@{*/
4033 /*! @brief Read current value of the DCDC_REG1_POSLIMIT_BUCK_IN field. */
4034 #define DCDC_RD_REG1_POSLIMIT_BUCK_IN(base) ((DCDC_REG1_REG(base) & DCDC_REG1_POSLIMIT_BUCK_IN_MASK) >> DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT)
4035 #define DCDC_BRD_REG1_POSLIMIT_BUCK_IN(base) (BME_UBFX32(&DCDC_REG1_REG(base), DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT, DCDC_REG1_POSLIMIT_BUCK_IN_WIDTH))
4036 
4037 /*! @brief Set the POSLIMIT_BUCK_IN field to a new value. */
4038 #define DCDC_WR_REG1_POSLIMIT_BUCK_IN(base, value) (DCDC_RMW_REG1(base, DCDC_REG1_POSLIMIT_BUCK_IN_MASK, DCDC_REG1_POSLIMIT_BUCK_IN(value)))
4039 #define DCDC_BWR_REG1_POSLIMIT_BUCK_IN(base, value) (BME_BFI32(&DCDC_REG1_REG(base), ((uint32_t)(value) << DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT), DCDC_REG1_POSLIMIT_BUCK_IN_SHIFT, DCDC_REG1_POSLIMIT_BUCK_IN_WIDTH))
4040 /*@}*/
4041 
4042 /*!
4043  * @name Register DCDC_REG1, field POSLIMIT_BOOST_IN[13:7] (RW)
4044  *
4045  * Upper limit duty cycle limit in DC-DC converter. This field limits the
4046  * maximum VDDIO achievable for a given battery voltage, and its value may be increased
4047  * if very low battery operation is met.
4048  */
4049 /*@{*/
4050 /*! @brief Read current value of the DCDC_REG1_POSLIMIT_BOOST_IN field. */
4051 #define DCDC_RD_REG1_POSLIMIT_BOOST_IN(base) ((DCDC_REG1_REG(base) & DCDC_REG1_POSLIMIT_BOOST_IN_MASK) >> DCDC_REG1_POSLIMIT_BOOST_IN_SHIFT)
4052 #define DCDC_BRD_REG1_POSLIMIT_BOOST_IN(base) (BME_UBFX32(&DCDC_REG1_REG(base), DCDC_REG1_POSLIMIT_BOOST_IN_SHIFT, DCDC_REG1_POSLIMIT_BOOST_IN_WIDTH))
4053 
4054 /*! @brief Set the POSLIMIT_BOOST_IN field to a new value. */
4055 #define DCDC_WR_REG1_POSLIMIT_BOOST_IN(base, value) (DCDC_RMW_REG1(base, DCDC_REG1_POSLIMIT_BOOST_IN_MASK, DCDC_REG1_POSLIMIT_BOOST_IN(value)))
4056 #define DCDC_BWR_REG1_POSLIMIT_BOOST_IN(base, value) (BME_BFI32(&DCDC_REG1_REG(base), ((uint32_t)(value) << DCDC_REG1_POSLIMIT_BOOST_IN_SHIFT), DCDC_REG1_POSLIMIT_BOOST_IN_SHIFT, DCDC_REG1_POSLIMIT_BOOST_IN_WIDTH))
4057 /*@}*/
4058 
4059 /*!
4060  * @name Register DCDC_REG1, field DCDC_LOOPCTRL_CM_HST_THRESH[21] (RW)
4061  *
4062  * Enable hysteresis in switching converter common mode analog comparators. This
4063  * feature improves transient supply ripple and efficiency.
4064  */
4065 /*@{*/
4066 /*! @brief Read current value of the DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH field. */
4067 #define DCDC_RD_REG1_DCDC_LOOPCTRL_CM_HST_THRESH(base) ((DCDC_REG1_REG(base) & DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH_MASK) >> DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH_SHIFT)
4068 #define DCDC_BRD_REG1_DCDC_LOOPCTRL_CM_HST_THRESH(base) (BME_UBFX32(&DCDC_REG1_REG(base), DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH_SHIFT, DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH_WIDTH))
4069 
4070 /*! @brief Set the DCDC_LOOPCTRL_CM_HST_THRESH field to a new value. */
4071 #define DCDC_WR_REG1_DCDC_LOOPCTRL_CM_HST_THRESH(base, value) (DCDC_RMW_REG1(base, DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH_MASK, DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH(value)))
4072 #define DCDC_BWR_REG1_DCDC_LOOPCTRL_CM_HST_THRESH(base, value) (BME_BFI32(&DCDC_REG1_REG(base), ((uint32_t)(value) << DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH_SHIFT), DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH_SHIFT, DCDC_REG1_DCDC_LOOPCTRL_CM_HST_THRESH_WIDTH))
4073 /*@}*/
4074 
4075 /*!
4076  * @name Register DCDC_REG1, field DCDC_LOOPCTRL_DF_HST_THRESH[22] (RW)
4077  *
4078  * Enable hysteresis in switching converter differential mode analog
4079  * comparators. This feature improves transient supply ripple and efficiency.
4080  */
4081 /*@{*/
4082 /*! @brief Read current value of the DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH field. */
4083 #define DCDC_RD_REG1_DCDC_LOOPCTRL_DF_HST_THRESH(base) ((DCDC_REG1_REG(base) & DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH_MASK) >> DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH_SHIFT)
4084 #define DCDC_BRD_REG1_DCDC_LOOPCTRL_DF_HST_THRESH(base) (BME_UBFX32(&DCDC_REG1_REG(base), DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH_SHIFT, DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH_WIDTH))
4085 
4086 /*! @brief Set the DCDC_LOOPCTRL_DF_HST_THRESH field to a new value. */
4087 #define DCDC_WR_REG1_DCDC_LOOPCTRL_DF_HST_THRESH(base, value) (DCDC_RMW_REG1(base, DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH_MASK, DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH(value)))
4088 #define DCDC_BWR_REG1_DCDC_LOOPCTRL_DF_HST_THRESH(base, value) (BME_BFI32(&DCDC_REG1_REG(base), ((uint32_t)(value) << DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH_SHIFT), DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH_SHIFT, DCDC_REG1_DCDC_LOOPCTRL_DF_HST_THRESH_WIDTH))
4089 /*@}*/
4090 
4091 /*!
4092  * @name Register DCDC_REG1, field DCDC_LOOPCTRL_EN_CM_HYST[23] (RW)
4093  *
4094  * Enable hysteresis in switching converter common mode analog comparators. This
4095  * feature improves transient supply ripple and efficiency.
4096  */
4097 /*@{*/
4098 /*! @brief Read current value of the DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST field. */
4099 #define DCDC_RD_REG1_DCDC_LOOPCTRL_EN_CM_HYST(base) ((DCDC_REG1_REG(base) & DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST_MASK) >> DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST_SHIFT)
4100 #define DCDC_BRD_REG1_DCDC_LOOPCTRL_EN_CM_HYST(base) (BME_UBFX32(&DCDC_REG1_REG(base), DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST_SHIFT, DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST_WIDTH))
4101 
4102 /*! @brief Set the DCDC_LOOPCTRL_EN_CM_HYST field to a new value. */
4103 #define DCDC_WR_REG1_DCDC_LOOPCTRL_EN_CM_HYST(base, value) (DCDC_RMW_REG1(base, DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST_MASK, DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST(value)))
4104 #define DCDC_BWR_REG1_DCDC_LOOPCTRL_EN_CM_HYST(base, value) (BME_BFI32(&DCDC_REG1_REG(base), ((uint32_t)(value) << DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST_SHIFT), DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST_SHIFT, DCDC_REG1_DCDC_LOOPCTRL_EN_CM_HYST_WIDTH))
4105 /*@}*/
4106 
4107 /*!
4108  * @name Register DCDC_REG1, field DCDC_LOOPCTRL_EN_DF_HYST[24] (RW)
4109  *
4110  * Enable hysteresis in switching converter differential mode analog
4111  * comparators. This feature improves transient supply ripple and efficiency.
4112  */
4113 /*@{*/
4114 /*! @brief Read current value of the DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST field. */
4115 #define DCDC_RD_REG1_DCDC_LOOPCTRL_EN_DF_HYST(base) ((DCDC_REG1_REG(base) & DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST_MASK) >> DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST_SHIFT)
4116 #define DCDC_BRD_REG1_DCDC_LOOPCTRL_EN_DF_HYST(base) (BME_UBFX32(&DCDC_REG1_REG(base), DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST_SHIFT, DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST_WIDTH))
4117 
4118 /*! @brief Set the DCDC_LOOPCTRL_EN_DF_HYST field to a new value. */
4119 #define DCDC_WR_REG1_DCDC_LOOPCTRL_EN_DF_HYST(base, value) (DCDC_RMW_REG1(base, DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST_MASK, DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST(value)))
4120 #define DCDC_BWR_REG1_DCDC_LOOPCTRL_EN_DF_HYST(base, value) (BME_BFI32(&DCDC_REG1_REG(base), ((uint32_t)(value) << DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST_SHIFT), DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST_SHIFT, DCDC_REG1_DCDC_LOOPCTRL_EN_DF_HYST_WIDTH))
4121 /*@}*/
4122 
4123 /*******************************************************************************
4124  * DCDC_REG2 - DCDC REGISTER 2
4125  ******************************************************************************/
4126 
4127 /*!
4128  * @brief DCDC_REG2 - DCDC REGISTER 2 (RW)
4129  *
4130  * Reset value: 0x00004009U
4131  */
4132 /*!
4133  * @name Constants and macros for entire DCDC_REG2 register
4134  */
4135 /*@{*/
4136 #define DCDC_RD_REG2(base)       (DCDC_REG2_REG(base))
4137 #define DCDC_WR_REG2(base, value) (DCDC_REG2_REG(base) = (value))
4138 #define DCDC_RMW_REG2(base, mask, value) (DCDC_WR_REG2(base, (DCDC_RD_REG2(base) & ~(mask)) | (value)))
4139 #define DCDC_SET_REG2(base, value) (BME_OR32(&DCDC_REG2_REG(base), (uint32_t)(value)))
4140 #define DCDC_CLR_REG2(base, value) (BME_AND32(&DCDC_REG2_REG(base), (uint32_t)(~(value))))
4141 #define DCDC_TOG_REG2(base, value) (BME_XOR32(&DCDC_REG2_REG(base), (uint32_t)(value)))
4142 /*@}*/
4143 
4144 /*
4145  * Constants & macros for individual DCDC_REG2 bitfields
4146  */
4147 
4148 /*!
4149  * @name Register DCDC_REG2, field DCDC_LOOPCTRL_DC_C[1:0] (RW)
4150  *
4151  * Ratio of integral control parameter to proportional control parameter in the
4152  * switching DC-DC converter, it can be used to optimize efficiency and loop
4153  * response.
4154  */
4155 /*@{*/
4156 /*! @brief Read current value of the DCDC_REG2_DCDC_LOOPCTRL_DC_C field. */
4157 #define DCDC_RD_REG2_DCDC_LOOPCTRL_DC_C(base) ((DCDC_REG2_REG(base) & DCDC_REG2_DCDC_LOOPCTRL_DC_C_MASK) >> DCDC_REG2_DCDC_LOOPCTRL_DC_C_SHIFT)
4158 #define DCDC_BRD_REG2_DCDC_LOOPCTRL_DC_C(base) (BME_UBFX32(&DCDC_REG2_REG(base), DCDC_REG2_DCDC_LOOPCTRL_DC_C_SHIFT, DCDC_REG2_DCDC_LOOPCTRL_DC_C_WIDTH))
4159 
4160 /*! @brief Set the DCDC_LOOPCTRL_DC_C field to a new value. */
4161 #define DCDC_WR_REG2_DCDC_LOOPCTRL_DC_C(base, value) (DCDC_RMW_REG2(base, DCDC_REG2_DCDC_LOOPCTRL_DC_C_MASK, DCDC_REG2_DCDC_LOOPCTRL_DC_C(value)))
4162 #define DCDC_BWR_REG2_DCDC_LOOPCTRL_DC_C(base, value) (BME_BFI32(&DCDC_REG2_REG(base), ((uint32_t)(value) << DCDC_REG2_DCDC_LOOPCTRL_DC_C_SHIFT), DCDC_REG2_DCDC_LOOPCTRL_DC_C_SHIFT, DCDC_REG2_DCDC_LOOPCTRL_DC_C_WIDTH))
4163 /*@}*/
4164 
4165 /*!
4166  * @name Register DCDC_REG2, field DCDC_LOOPCTRL_DC_FF[8:6] (RW)
4167  *
4168  * Two complement feed forward step in duty cycle in the switching DC-DC
4169  * converter. Each time this bit makes a transition from 0x0, the loop filter of the
4170  * DC-DC converter is stepped once by a value proportional to the change. This can
4171  * be used to force a certain control loop behavior, such as improving response
4172  * under known heavy load transients.
4173  */
4174 /*@{*/
4175 /*! @brief Read current value of the DCDC_REG2_DCDC_LOOPCTRL_DC_FF field. */
4176 #define DCDC_RD_REG2_DCDC_LOOPCTRL_DC_FF(base) ((DCDC_REG2_REG(base) & DCDC_REG2_DCDC_LOOPCTRL_DC_FF_MASK) >> DCDC_REG2_DCDC_LOOPCTRL_DC_FF_SHIFT)
4177 #define DCDC_BRD_REG2_DCDC_LOOPCTRL_DC_FF(base) (BME_UBFX32(&DCDC_REG2_REG(base), DCDC_REG2_DCDC_LOOPCTRL_DC_FF_SHIFT, DCDC_REG2_DCDC_LOOPCTRL_DC_FF_WIDTH))
4178 
4179 /*! @brief Set the DCDC_LOOPCTRL_DC_FF field to a new value. */
4180 #define DCDC_WR_REG2_DCDC_LOOPCTRL_DC_FF(base, value) (DCDC_RMW_REG2(base, DCDC_REG2_DCDC_LOOPCTRL_DC_FF_MASK, DCDC_REG2_DCDC_LOOPCTRL_DC_FF(value)))
4181 #define DCDC_BWR_REG2_DCDC_LOOPCTRL_DC_FF(base, value) (BME_BFI32(&DCDC_REG2_REG(base), ((uint32_t)(value) << DCDC_REG2_DCDC_LOOPCTRL_DC_FF_SHIFT), DCDC_REG2_DCDC_LOOPCTRL_DC_FF_SHIFT, DCDC_REG2_DCDC_LOOPCTRL_DC_FF_WIDTH))
4182 /*@}*/
4183 
4184 /*!
4185  * @name Register DCDC_REG2, field DCDC_LOOPCTRL_HYST_SIGN[13] (RW)
4186  *
4187  * Invert the sign of the hysteresis in DC-DC analog comparators. This bit is
4188  * set when in limp mode.
4189  */
4190 /*@{*/
4191 /*! @brief Read current value of the DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN field. */
4192 #define DCDC_RD_REG2_DCDC_LOOPCTRL_HYST_SIGN(base) ((DCDC_REG2_REG(base) & DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN_MASK) >> DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN_SHIFT)
4193 #define DCDC_BRD_REG2_DCDC_LOOPCTRL_HYST_SIGN(base) (BME_UBFX32(&DCDC_REG2_REG(base), DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN_SHIFT, DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN_WIDTH))
4194 
4195 /*! @brief Set the DCDC_LOOPCTRL_HYST_SIGN field to a new value. */
4196 #define DCDC_WR_REG2_DCDC_LOOPCTRL_HYST_SIGN(base, value) (DCDC_RMW_REG2(base, DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN_MASK, DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN(value)))
4197 #define DCDC_BWR_REG2_DCDC_LOOPCTRL_HYST_SIGN(base, value) (BME_BFI32(&DCDC_REG2_REG(base), ((uint32_t)(value) << DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN_SHIFT), DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN_SHIFT, DCDC_REG2_DCDC_LOOPCTRL_HYST_SIGN_WIDTH))
4198 /*@}*/
4199 
4200 /*!
4201  * @name Register DCDC_REG2, field DCDC_LOOPCTRL_TOGGLE_DIF[14] (RW)
4202  *
4203  * Set high to enable supply stepping to change, only after the differential
4204  * control loop has toggled. This bit eliminates any chance of large transients when
4205  * supply voltage changes are made.
4206  */
4207 /*@{*/
4208 /*! @brief Read current value of the DCDC_REG2_DCDC_LOOPCTRL_TOGGLE_DIF field. */
4209 #define DCDC_RD_REG2_DCDC_LOOPCTRL_TOGGLE_DIF(base) ((DCDC_REG2_REG(base) & DCDC_REG2_DCDC_LOOPCTRL_TOGGLE_DIF_MASK) >> DCDC_REG2_DCDC_LOOPCTRL_TOGGLE_DIF_SHIFT)
4210 #define DCDC_BRD_REG2_DCDC_LOOPCTRL_TOGGLE_DIF(base) (BME_UBFX32(&DCDC_REG2_REG(base), DCDC_REG2_DCDC_LOOPCTRL_TOGGLE_DIF_SHIFT, DCDC_REG2_DCDC_LOOPCTRL_TOGGLE_DIF_WIDTH))
4211 
4212 /*! @brief Set the DCDC_LOOPCTRL_TOGGLE_DIF field to a new value. */
4213 #define DCDC_WR_REG2_DCDC_LOOPCTRL_TOGGLE_DIF(base, value) (DCDC_RMW_REG2(base, DCDC_REG2_DCDC_LOOPCTRL_TOGGLE_DIF_MASK, DCDC_REG2_DCDC_LOOPCTRL_TOGGLE_DIF(value)))
4214 #define DCDC_BWR_REG2_DCDC_LOOPCTRL_TOGGLE_DIF(base, value) (BME_BFI32(&DCDC_REG2_REG(base), ((uint32_t)(value) << DCDC_REG2_DCDC_LOOPCTRL_TOGGLE_DIF_SHIFT), DCDC_REG2_DCDC_LOOPCTRL_TOGGLE_DIF_SHIFT, DCDC_REG2_DCDC_LOOPCTRL_TOGGLE_DIF_WIDTH))
4215 /*@}*/
4216 
4217 /*!
4218  * @name Register DCDC_REG2, field DCDC_BATTMONITOR_EN_BATADJ[15] (RW)
4219  *
4220  * This bit enables the DC-DC to improve efficiency and minimize ripple using
4221  * the information from the BATT_VAL field. The BATT_VAL contains accurate
4222  * information before setting EN_BATADJ.
4223  */
4224 /*@{*/
4225 /*! @brief Read current value of the DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ field. */
4226 #define DCDC_RD_REG2_DCDC_BATTMONITOR_EN_BATADJ(base) ((DCDC_REG2_REG(base) & DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ_MASK) >> DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ_SHIFT)
4227 #define DCDC_BRD_REG2_DCDC_BATTMONITOR_EN_BATADJ(base) (BME_UBFX32(&DCDC_REG2_REG(base), DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ_SHIFT, DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ_WIDTH))
4228 
4229 /*! @brief Set the DCDC_BATTMONITOR_EN_BATADJ field to a new value. */
4230 #define DCDC_WR_REG2_DCDC_BATTMONITOR_EN_BATADJ(base, value) (DCDC_RMW_REG2(base, DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ_MASK, DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ(value)))
4231 #define DCDC_BWR_REG2_DCDC_BATTMONITOR_EN_BATADJ(base, value) (BME_BFI32(&DCDC_REG2_REG(base), ((uint32_t)(value) << DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ_SHIFT), DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ_SHIFT, DCDC_REG2_DCDC_BATTMONITOR_EN_BATADJ_WIDTH))
4232 /*@}*/
4233 
4234 /*!
4235  * @name Register DCDC_REG2, field DCDC_BATTMONITOR_BATT_VAL[25:16] (RW)
4236  *
4237  * Software should be configured to place the battery voltage in this register
4238  * measured with an 8 mV LSB resolution through the ADC. This value is used by the
4239  * DC-DC converter and must be proper configured before setting EN_BATADJ.
4240  */
4241 /*@{*/
4242 /*! @brief Read current value of the DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL field. */
4243 #define DCDC_RD_REG2_DCDC_BATTMONITOR_BATT_VAL(base) ((DCDC_REG2_REG(base) & DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL_MASK) >> DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL_SHIFT)
4244 #define DCDC_BRD_REG2_DCDC_BATTMONITOR_BATT_VAL(base) (BME_UBFX32(&DCDC_REG2_REG(base), DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL_SHIFT, DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL_WIDTH))
4245 
4246 /*! @brief Set the DCDC_BATTMONITOR_BATT_VAL field to a new value. */
4247 #define DCDC_WR_REG2_DCDC_BATTMONITOR_BATT_VAL(base, value) (DCDC_RMW_REG2(base, DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL_MASK, DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL(value)))
4248 #define DCDC_BWR_REG2_DCDC_BATTMONITOR_BATT_VAL(base, value) (BME_BFI32(&DCDC_REG2_REG(base), ((uint32_t)(value) << DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL_SHIFT), DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL_SHIFT, DCDC_REG2_DCDC_BATTMONITOR_BATT_VAL_WIDTH))
4249 /*@}*/
4250 
4251 /*******************************************************************************
4252  * DCDC_REG3 - DCDC REGISTER 3
4253  ******************************************************************************/
4254 
4255 /*!
4256  * @brief DCDC_REG3 - DCDC REGISTER 3 (RW)
4257  *
4258  * Reset value: 0x0000A9C6U
4259  */
4260 /*!
4261  * @name Constants and macros for entire DCDC_REG3 register
4262  */
4263 /*@{*/
4264 #define DCDC_RD_REG3(base)       (DCDC_REG3_REG(base))
4265 #define DCDC_WR_REG3(base, value) (DCDC_REG3_REG(base) = (value))
4266 #define DCDC_RMW_REG3(base, mask, value) (DCDC_WR_REG3(base, (DCDC_RD_REG3(base) & ~(mask)) | (value)))
4267 #define DCDC_SET_REG3(base, value) (BME_OR32(&DCDC_REG3_REG(base), (uint32_t)(value)))
4268 #define DCDC_CLR_REG3(base, value) (BME_AND32(&DCDC_REG3_REG(base), (uint32_t)(~(value))))
4269 #define DCDC_TOG_REG3(base, value) (BME_XOR32(&DCDC_REG3_REG(base), (uint32_t)(value)))
4270 /*@}*/
4271 
4272 /*
4273  * Constants & macros for individual DCDC_REG3 bitfields
4274  */
4275 
4276 /*!
4277  * @name Register DCDC_REG3, field DCDC_VDD1P8CTRL_TRG[5:0] (RW)
4278  *
4279  * Target value of VDD1P8, 25 mV each step in two ranges, from 0x00 to 0x11 and
4280  * 0x20 to 0x3F.
4281  *
4282  * Values:
4283  * - 0b000000 - 1.65 V
4284  * - 0b000110 - 1.8 V
4285  * - 0b010001 - 2.075 V
4286  * - 0b100000 - 2.8 V
4287  * - 0b110100 - 3.3 V
4288  * - 0b111111 - 3.575 V
4289  */
4290 /*@{*/
4291 /*! @brief Read current value of the DCDC_REG3_DCDC_VDD1P8CTRL_TRG field. */
4292 #define DCDC_RD_REG3_DCDC_VDD1P8CTRL_TRG(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_VDD1P8CTRL_TRG_MASK) >> DCDC_REG3_DCDC_VDD1P8CTRL_TRG_SHIFT)
4293 #define DCDC_BRD_REG3_DCDC_VDD1P8CTRL_TRG(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCDC_VDD1P8CTRL_TRG_SHIFT, DCDC_REG3_DCDC_VDD1P8CTRL_TRG_WIDTH))
4294 
4295 /*! @brief Set the DCDC_VDD1P8CTRL_TRG field to a new value. */
4296 #define DCDC_WR_REG3_DCDC_VDD1P8CTRL_TRG(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_VDD1P8CTRL_TRG_MASK, DCDC_REG3_DCDC_VDD1P8CTRL_TRG(value)))
4297 #define DCDC_BWR_REG3_DCDC_VDD1P8CTRL_TRG(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint32_t)(value) << DCDC_REG3_DCDC_VDD1P8CTRL_TRG_SHIFT), DCDC_REG3_DCDC_VDD1P8CTRL_TRG_SHIFT, DCDC_REG3_DCDC_VDD1P8CTRL_TRG_WIDTH))
4298 /*@}*/
4299 
4300 /*!
4301  * @name Register DCDC_REG3, field DCDC_VDD1P45CTRL_TRG_BUCK[10:6] (RW)
4302  *
4303  * Target value of VDD1p45 in buck mode, 25 mV each step from 0x00 to 0x0F
4304  *
4305  * Values:
4306  * - 0b01111 - 1.65 V
4307  * - 0b00111 - 1.45 V
4308  * - 0b00000 - 1.275 V
4309  */
4310 /*@{*/
4311 /*! @brief Read current value of the DCDC_REG3_DCDC_VDD1P45CTRL_TRG_BUCK field. */
4312 #define DCDC_RD_REG3_DCDC_VDD1P45CTRL_TRG_BUCK(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_VDD1P45CTRL_TRG_BUCK_MASK) >> DCDC_REG3_DCDC_VDD1P45CTRL_TRG_BUCK_SHIFT)
4313 #define DCDC_BRD_REG3_DCDC_VDD1P45CTRL_TRG_BUCK(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCDC_VDD1P45CTRL_TRG_BUCK_SHIFT, DCDC_REG3_DCDC_VDD1P45CTRL_TRG_BUCK_WIDTH))
4314 
4315 /*! @brief Set the DCDC_VDD1P45CTRL_TRG_BUCK field to a new value. */
4316 #define DCDC_WR_REG3_DCDC_VDD1P45CTRL_TRG_BUCK(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_VDD1P45CTRL_TRG_BUCK_MASK, DCDC_REG3_DCDC_VDD1P45CTRL_TRG_BUCK(value)))
4317 #define DCDC_BWR_REG3_DCDC_VDD1P45CTRL_TRG_BUCK(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint32_t)(value) << DCDC_REG3_DCDC_VDD1P45CTRL_TRG_BUCK_SHIFT), DCDC_REG3_DCDC_VDD1P45CTRL_TRG_BUCK_SHIFT, DCDC_REG3_DCDC_VDD1P45CTRL_TRG_BUCK_WIDTH))
4318 /*@}*/
4319 
4320 /*!
4321  * @name Register DCDC_REG3, field DCDC_VDD1P45CTRL_TRG_BOOST[15:11] (RW)
4322  *
4323  * Target value of VDD1P45 in bost mode, 25 mV each step from 0x00 to 0x0F. In
4324  * boost mode, DCDC boosts VDD1P45 to 1.8 V by default, software need to measure
4325  * battery voltage in light load, then adjust the target value accordingly. If the
4326  * total load current < 10mA, it is considered to be light load. It depends on
4327  * the internal resistance of the battery type.
4328  *
4329  * Values:
4330  * - 0b10101 - 1.8 V
4331  * - 0b01111 - 1.65 V
4332  * - 0b00111 - 1.45 V
4333  * - 0b00000 - 1.275 V
4334  */
4335 /*@{*/
4336 /*! @brief Read current value of the DCDC_REG3_DCDC_VDD1P45CTRL_TRG_BOOST field. */
4337 #define DCDC_RD_REG3_DCDC_VDD1P45CTRL_TRG_BOOST(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_VDD1P45CTRL_TRG_BOOST_MASK) >> DCDC_REG3_DCDC_VDD1P45CTRL_TRG_BOOST_SHIFT)
4338 #define DCDC_BRD_REG3_DCDC_VDD1P45CTRL_TRG_BOOST(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCDC_VDD1P45CTRL_TRG_BOOST_SHIFT, DCDC_REG3_DCDC_VDD1P45CTRL_TRG_BOOST_WIDTH))
4339 
4340 /*! @brief Set the DCDC_VDD1P45CTRL_TRG_BOOST field to a new value. */
4341 #define DCDC_WR_REG3_DCDC_VDD1P45CTRL_TRG_BOOST(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_VDD1P45CTRL_TRG_BOOST_MASK, DCDC_REG3_DCDC_VDD1P45CTRL_TRG_BOOST(value)))
4342 #define DCDC_BWR_REG3_DCDC_VDD1P45CTRL_TRG_BOOST(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint32_t)(value) << DCDC_REG3_DCDC_VDD1P45CTRL_TRG_BOOST_SHIFT), DCDC_REG3_DCDC_VDD1P45CTRL_TRG_BOOST_SHIFT, DCDC_REG3_DCDC_VDD1P45CTRL_TRG_BOOST_WIDTH))
4343 /*@}*/
4344 
4345 /*!
4346  * @name Register DCDC_REG3, field DCDC_VDD1P45CTRL_ADJTN[20:17] (RW)
4347  *
4348  * Adjust value of duty cycle when switching between VDD1P45 and VDD1P8. The
4349  * unit is 1/32 or 3.125%.
4350  */
4351 /*@{*/
4352 /*! @brief Read current value of the DCDC_REG3_DCDC_VDD1P45CTRL_ADJTN field. */
4353 #define DCDC_RD_REG3_DCDC_VDD1P45CTRL_ADJTN(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_VDD1P45CTRL_ADJTN_MASK) >> DCDC_REG3_DCDC_VDD1P45CTRL_ADJTN_SHIFT)
4354 #define DCDC_BRD_REG3_DCDC_VDD1P45CTRL_ADJTN(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCDC_VDD1P45CTRL_ADJTN_SHIFT, DCDC_REG3_DCDC_VDD1P45CTRL_ADJTN_WIDTH))
4355 
4356 /*! @brief Set the DCDC_VDD1P45CTRL_ADJTN field to a new value. */
4357 #define DCDC_WR_REG3_DCDC_VDD1P45CTRL_ADJTN(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_VDD1P45CTRL_ADJTN_MASK, DCDC_REG3_DCDC_VDD1P45CTRL_ADJTN(value)))
4358 #define DCDC_BWR_REG3_DCDC_VDD1P45CTRL_ADJTN(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint32_t)(value) << DCDC_REG3_DCDC_VDD1P45CTRL_ADJTN_SHIFT), DCDC_REG3_DCDC_VDD1P45CTRL_ADJTN_SHIFT, DCDC_REG3_DCDC_VDD1P45CTRL_ADJTN_WIDTH))
4359 /*@}*/
4360 
4361 /*!
4362  * @name Register DCDC_REG3, field DCDC_MINPWR_DC_HALFCLK_LIMP[21] (RW)
4363  *
4364  * Set DCDC clock to half frequency for the limp mode.
4365  */
4366 /*@{*/
4367 /*! @brief Read current value of the DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_LIMP field. */
4368 #define DCDC_RD_REG3_DCDC_MINPWR_DC_HALFCLK_LIMP(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_LIMP_MASK) >> DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_LIMP_SHIFT)
4369 #define DCDC_BRD_REG3_DCDC_MINPWR_DC_HALFCLK_LIMP(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_LIMP_SHIFT, DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_LIMP_WIDTH))
4370 
4371 /*! @brief Set the DCDC_MINPWR_DC_HALFCLK_LIMP field to a new value. */
4372 #define DCDC_WR_REG3_DCDC_MINPWR_DC_HALFCLK_LIMP(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_LIMP_MASK, DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_LIMP(value)))
4373 #define DCDC_BWR_REG3_DCDC_MINPWR_DC_HALFCLK_LIMP(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint32_t)(value) << DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_LIMP_SHIFT), DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_LIMP_SHIFT, DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_LIMP_WIDTH))
4374 /*@}*/
4375 
4376 /*!
4377  * @name Register DCDC_REG3, field DCDC_MINPWR_DOUBLE_FETS_LIMP[22] (RW)
4378  *
4379  * Use double switch FET for the limp mode.
4380  */
4381 /*@{*/
4382 /*! @brief Read current value of the DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_LIMP field. */
4383 #define DCDC_RD_REG3_DCDC_MINPWR_DOUBLE_FETS_LIMP(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_LIMP_MASK) >> DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_LIMP_SHIFT)
4384 #define DCDC_BRD_REG3_DCDC_MINPWR_DOUBLE_FETS_LIMP(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_LIMP_SHIFT, DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_LIMP_WIDTH))
4385 
4386 /*! @brief Set the DCDC_MINPWR_DOUBLE_FETS_LIMP field to a new value. */
4387 #define DCDC_WR_REG3_DCDC_MINPWR_DOUBLE_FETS_LIMP(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_LIMP_MASK, DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_LIMP(value)))
4388 #define DCDC_BWR_REG3_DCDC_MINPWR_DOUBLE_FETS_LIMP(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint32_t)(value) << DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_LIMP_SHIFT), DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_LIMP_SHIFT, DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_LIMP_WIDTH))
4389 /*@}*/
4390 
4391 /*!
4392  * @name Register DCDC_REG3, field DCDC_MINPWR_HALF_FETS_LIMP[23] (RW)
4393  *
4394  * Use half switch FET for the limp mode.
4395  */
4396 /*@{*/
4397 /*! @brief Read current value of the DCDC_REG3_DCDC_MINPWR_HALF_FETS_LIMP field. */
4398 #define DCDC_RD_REG3_DCDC_MINPWR_HALF_FETS_LIMP(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_MINPWR_HALF_FETS_LIMP_MASK) >> DCDC_REG3_DCDC_MINPWR_HALF_FETS_LIMP_SHIFT)
4399 #define DCDC_BRD_REG3_DCDC_MINPWR_HALF_FETS_LIMP(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCDC_MINPWR_HALF_FETS_LIMP_SHIFT, DCDC_REG3_DCDC_MINPWR_HALF_FETS_LIMP_WIDTH))
4400 
4401 /*! @brief Set the DCDC_MINPWR_HALF_FETS_LIMP field to a new value. */
4402 #define DCDC_WR_REG3_DCDC_MINPWR_HALF_FETS_LIMP(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_MINPWR_HALF_FETS_LIMP_MASK, DCDC_REG3_DCDC_MINPWR_HALF_FETS_LIMP(value)))
4403 #define DCDC_BWR_REG3_DCDC_MINPWR_HALF_FETS_LIMP(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint32_t)(value) << DCDC_REG3_DCDC_MINPWR_HALF_FETS_LIMP_SHIFT), DCDC_REG3_DCDC_MINPWR_HALF_FETS_LIMP_SHIFT, DCDC_REG3_DCDC_MINPWR_HALF_FETS_LIMP_WIDTH))
4404 /*@}*/
4405 
4406 /*!
4407  * @name Register DCDC_REG3, field DCDC_MINPWR_DC_HALFCLK[24] (RW)
4408  *
4409  * Set DCDC clock to half frequency for the continuous mode.
4410  */
4411 /*@{*/
4412 /*! @brief Read current value of the DCDC_REG3_DCDC_MINPWR_DC_HALFCLK field. */
4413 #define DCDC_RD_REG3_DCDC_MINPWR_DC_HALFCLK(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_MASK) >> DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_SHIFT)
4414 #define DCDC_BRD_REG3_DCDC_MINPWR_DC_HALFCLK(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_SHIFT, DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_WIDTH))
4415 
4416 /*! @brief Set the DCDC_MINPWR_DC_HALFCLK field to a new value. */
4417 #define DCDC_WR_REG3_DCDC_MINPWR_DC_HALFCLK(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_MASK, DCDC_REG3_DCDC_MINPWR_DC_HALFCLK(value)))
4418 #define DCDC_BWR_REG3_DCDC_MINPWR_DC_HALFCLK(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint32_t)(value) << DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_SHIFT), DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_SHIFT, DCDC_REG3_DCDC_MINPWR_DC_HALFCLK_WIDTH))
4419 /*@}*/
4420 
4421 /*!
4422  * @name Register DCDC_REG3, field DCDC_MINPWR_DOUBLE_FETS[25] (RW)
4423  *
4424  * Use double switch FET for the continuous mode.
4425  */
4426 /*@{*/
4427 /*! @brief Read current value of the DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS field. */
4428 #define DCDC_RD_REG3_DCDC_MINPWR_DOUBLE_FETS(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_MASK) >> DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_SHIFT)
4429 #define DCDC_BRD_REG3_DCDC_MINPWR_DOUBLE_FETS(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_SHIFT, DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_WIDTH))
4430 
4431 /*! @brief Set the DCDC_MINPWR_DOUBLE_FETS field to a new value. */
4432 #define DCDC_WR_REG3_DCDC_MINPWR_DOUBLE_FETS(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_MASK, DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS(value)))
4433 #define DCDC_BWR_REG3_DCDC_MINPWR_DOUBLE_FETS(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint32_t)(value) << DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_SHIFT), DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_SHIFT, DCDC_REG3_DCDC_MINPWR_DOUBLE_FETS_WIDTH))
4434 /*@}*/
4435 
4436 /*!
4437  * @name Register DCDC_REG3, field DCDC_MINPWR_HALF_FETS[26] (RW)
4438  *
4439  * Use half switch FET for the continuous mode.
4440  */
4441 /*@{*/
4442 /*! @brief Read current value of the DCDC_REG3_DCDC_MINPWR_HALF_FETS field. */
4443 #define DCDC_RD_REG3_DCDC_MINPWR_HALF_FETS(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_MINPWR_HALF_FETS_MASK) >> DCDC_REG3_DCDC_MINPWR_HALF_FETS_SHIFT)
4444 #define DCDC_BRD_REG3_DCDC_MINPWR_HALF_FETS(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCDC_MINPWR_HALF_FETS_SHIFT, DCDC_REG3_DCDC_MINPWR_HALF_FETS_WIDTH))
4445 
4446 /*! @brief Set the DCDC_MINPWR_HALF_FETS field to a new value. */
4447 #define DCDC_WR_REG3_DCDC_MINPWR_HALF_FETS(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_MINPWR_HALF_FETS_MASK, DCDC_REG3_DCDC_MINPWR_HALF_FETS(value)))
4448 #define DCDC_BWR_REG3_DCDC_MINPWR_HALF_FETS(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint32_t)(value) << DCDC_REG3_DCDC_MINPWR_HALF_FETS_SHIFT), DCDC_REG3_DCDC_MINPWR_HALF_FETS_SHIFT, DCDC_REG3_DCDC_MINPWR_HALF_FETS_WIDTH))
4449 /*@}*/
4450 
4451 /*!
4452  * @name Register DCDC_REG3, field DCDC_VDD1P45CTRL_DISABLE_STEP[29] (RW)
4453  *
4454  * Disable stepping for VDD1P45. Must set this bit before enter low power modes.
4455  */
4456 /*@{*/
4457 /*! @brief Read current value of the DCDC_REG3_DCDC_VDD1P45CTRL_DISABLE_STEP field. */
4458 #define DCDC_RD_REG3_DCDC_VDD1P45CTRL_DISABLE_STEP(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_VDD1P45CTRL_DISABLE_STEP_MASK) >> DCDC_REG3_DCDC_VDD1P45CTRL_DISABLE_STEP_SHIFT)
4459 #define DCDC_BRD_REG3_DCDC_VDD1P45CTRL_DISABLE_STEP(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCDC_VDD1P45CTRL_DISABLE_STEP_SHIFT, DCDC_REG3_DCDC_VDD1P45CTRL_DISABLE_STEP_WIDTH))
4460 
4461 /*! @brief Set the DCDC_VDD1P45CTRL_DISABLE_STEP field to a new value. */
4462 #define DCDC_WR_REG3_DCDC_VDD1P45CTRL_DISABLE_STEP(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_VDD1P45CTRL_DISABLE_STEP_MASK, DCDC_REG3_DCDC_VDD1P45CTRL_DISABLE_STEP(value)))
4463 #define DCDC_BWR_REG3_DCDC_VDD1P45CTRL_DISABLE_STEP(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint32_t)(value) << DCDC_REG3_DCDC_VDD1P45CTRL_DISABLE_STEP_SHIFT), DCDC_REG3_DCDC_VDD1P45CTRL_DISABLE_STEP_SHIFT, DCDC_REG3_DCDC_VDD1P45CTRL_DISABLE_STEP_WIDTH))
4464 /*@}*/
4465 
4466 /*!
4467  * @name Register DCDC_REG3, field DCDC_VDD1P8CTRL_DISABLE_STEP[30] (RW)
4468  *
4469  * Disable stepping for VDD1P8. Must set this bit before enter low power modes.
4470  */
4471 /*@{*/
4472 /*! @brief Read current value of the DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP field. */
4473 #define DCDC_RD_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP(base) ((DCDC_REG3_REG(base) & DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK) >> DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_SHIFT)
4474 #define DCDC_BRD_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP(base) (BME_UBFX32(&DCDC_REG3_REG(base), DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_SHIFT, DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_WIDTH))
4475 
4476 /*! @brief Set the DCDC_VDD1P8CTRL_DISABLE_STEP field to a new value. */
4477 #define DCDC_WR_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP(base, value) (DCDC_RMW_REG3(base, DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK, DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP(value)))
4478 #define DCDC_BWR_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP(base, value) (BME_BFI32(&DCDC_REG3_REG(base), ((uint32_t)(value) << DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_SHIFT), DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_SHIFT, DCDC_REG3_DCDC_VDD1P8CTRL_DISABLE_STEP_WIDTH))
4479 /*@}*/
4480 
4481 /*******************************************************************************
4482  * DCDC_REG4 - DCDC REGISTER 4
4483  ******************************************************************************/
4484 
4485 /*!
4486  * @brief DCDC_REG4 - DCDC REGISTER 4 (RW)
4487  *
4488  * Reset value: 0x00000000U
4489  */
4490 /*!
4491  * @name Constants and macros for entire DCDC_REG4 register
4492  */
4493 /*@{*/
4494 #define DCDC_RD_REG4(base)       (DCDC_REG4_REG(base))
4495 #define DCDC_WR_REG4(base, value) (DCDC_REG4_REG(base) = (value))
4496 #define DCDC_RMW_REG4(base, mask, value) (DCDC_WR_REG4(base, (DCDC_RD_REG4(base) & ~(mask)) | (value)))
4497 #define DCDC_SET_REG4(base, value) (BME_OR32(&DCDC_REG4_REG(base), (uint32_t)(value)))
4498 #define DCDC_CLR_REG4(base, value) (BME_AND32(&DCDC_REG4_REG(base), (uint32_t)(~(value))))
4499 #define DCDC_TOG_REG4(base, value) (BME_XOR32(&DCDC_REG4_REG(base), (uint32_t)(value)))
4500 /*@}*/
4501 
4502 /*
4503  * Constants & macros for individual DCDC_REG4 bitfields
4504  */
4505 
4506 /*!
4507  * @name Register DCDC_REG4, field DCDC_SW_SHUTDOWN[0] (RW)
4508  */
4509 /*@{*/
4510 /*! @brief Read current value of the DCDC_REG4_DCDC_SW_SHUTDOWN field. */
4511 #define DCDC_RD_REG4_DCDC_SW_SHUTDOWN(base) ((DCDC_REG4_REG(base) & DCDC_REG4_DCDC_SW_SHUTDOWN_MASK) >> DCDC_REG4_DCDC_SW_SHUTDOWN_SHIFT)
4512 #define DCDC_BRD_REG4_DCDC_SW_SHUTDOWN(base) (BME_UBFX32(&DCDC_REG4_REG(base), DCDC_REG4_DCDC_SW_SHUTDOWN_SHIFT, DCDC_REG4_DCDC_SW_SHUTDOWN_WIDTH))
4513 
4514 /*! @brief Set the DCDC_SW_SHUTDOWN field to a new value. */
4515 #define DCDC_WR_REG4_DCDC_SW_SHUTDOWN(base, value) (DCDC_RMW_REG4(base, DCDC_REG4_DCDC_SW_SHUTDOWN_MASK, DCDC_REG4_DCDC_SW_SHUTDOWN(value)))
4516 #define DCDC_BWR_REG4_DCDC_SW_SHUTDOWN(base, value) (BME_BFI32(&DCDC_REG4_REG(base), ((uint32_t)(value) << DCDC_REG4_DCDC_SW_SHUTDOWN_SHIFT), DCDC_REG4_DCDC_SW_SHUTDOWN_SHIFT, DCDC_REG4_DCDC_SW_SHUTDOWN_WIDTH))
4517 /*@}*/
4518 
4519 /*!
4520  * @name Register DCDC_REG4, field UNLOCK[31:16] (RW)
4521  *
4522  * 0x3E77 KEY-Key needed to unlock HW_POWER_RESET register. Write 0x3E77 to
4523  * unlock this register and allow other bits to be changed. This register must be
4524  * unlocked on a write-by-write basis, so the UNLOCK bit can contain the correct key
4525  * value during all writes to this register in order to update any other bit
4526  * values in the register.
4527  */
4528 /*@{*/
4529 /*! @brief Read current value of the DCDC_REG4_UNLOCK field. */
4530 #define DCDC_RD_REG4_UNLOCK(base) ((DCDC_REG4_REG(base) & DCDC_REG4_UNLOCK_MASK) >> DCDC_REG4_UNLOCK_SHIFT)
4531 #define DCDC_BRD_REG4_UNLOCK(base) (BME_UBFX32(&DCDC_REG4_REG(base), DCDC_REG4_UNLOCK_SHIFT, DCDC_REG4_UNLOCK_WIDTH))
4532 
4533 /*! @brief Set the UNLOCK field to a new value. */
4534 #define DCDC_WR_REG4_UNLOCK(base, value) (DCDC_RMW_REG4(base, DCDC_REG4_UNLOCK_MASK, DCDC_REG4_UNLOCK(value)))
4535 #define DCDC_BWR_REG4_UNLOCK(base, value) (BME_BFI32(&DCDC_REG4_REG(base), ((uint32_t)(value) << DCDC_REG4_UNLOCK_SHIFT), DCDC_REG4_UNLOCK_SHIFT, DCDC_REG4_UNLOCK_WIDTH))
4536 /*@}*/
4537 
4538 /*******************************************************************************
4539  * DCDC_REG6 - DCDC REGISTER 6
4540  ******************************************************************************/
4541 
4542 /*!
4543  * @brief DCDC_REG6 - DCDC REGISTER 6 (RW)
4544  *
4545  * Reset value: 0x00000000U
4546  */
4547 /*!
4548  * @name Constants and macros for entire DCDC_REG6 register
4549  */
4550 /*@{*/
4551 #define DCDC_RD_REG6(base)       (DCDC_REG6_REG(base))
4552 #define DCDC_WR_REG6(base, value) (DCDC_REG6_REG(base) = (value))
4553 #define DCDC_RMW_REG6(base, mask, value) (DCDC_WR_REG6(base, (DCDC_RD_REG6(base) & ~(mask)) | (value)))
4554 #define DCDC_SET_REG6(base, value) (BME_OR32(&DCDC_REG6_REG(base), (uint32_t)(value)))
4555 #define DCDC_CLR_REG6(base, value) (BME_AND32(&DCDC_REG6_REG(base), (uint32_t)(~(value))))
4556 #define DCDC_TOG_REG6(base, value) (BME_XOR32(&DCDC_REG6_REG(base), (uint32_t)(value)))
4557 /*@}*/
4558 
4559 /*
4560  * Constants & macros for individual DCDC_REG6 bitfields
4561  */
4562 
4563 /*!
4564  * @name Register DCDC_REG6, field PSWITCH_INT_RISE_EN[0] (RW)
4565  *
4566  * Enable rising edge detect for interrupt.
4567  */
4568 /*@{*/
4569 /*! @brief Read current value of the DCDC_REG6_PSWITCH_INT_RISE_EN field. */
4570 #define DCDC_RD_REG6_PSWITCH_INT_RISE_EN(base) ((DCDC_REG6_REG(base) & DCDC_REG6_PSWITCH_INT_RISE_EN_MASK) >> DCDC_REG6_PSWITCH_INT_RISE_EN_SHIFT)
4571 #define DCDC_BRD_REG6_PSWITCH_INT_RISE_EN(base) (BME_UBFX32(&DCDC_REG6_REG(base), DCDC_REG6_PSWITCH_INT_RISE_EN_SHIFT, DCDC_REG6_PSWITCH_INT_RISE_EN_WIDTH))
4572 
4573 /*! @brief Set the PSWITCH_INT_RISE_EN field to a new value. */
4574 #define DCDC_WR_REG6_PSWITCH_INT_RISE_EN(base, value) (DCDC_RMW_REG6(base, DCDC_REG6_PSWITCH_INT_RISE_EN_MASK, DCDC_REG6_PSWITCH_INT_RISE_EN(value)))
4575 #define DCDC_BWR_REG6_PSWITCH_INT_RISE_EN(base, value) (BME_BFI32(&DCDC_REG6_REG(base), ((uint32_t)(value) << DCDC_REG6_PSWITCH_INT_RISE_EN_SHIFT), DCDC_REG6_PSWITCH_INT_RISE_EN_SHIFT, DCDC_REG6_PSWITCH_INT_RISE_EN_WIDTH))
4576 /*@}*/
4577 
4578 /*!
4579  * @name Register DCDC_REG6, field PSWITCH_INT_FALL_EN[1] (RW)
4580  *
4581  * Enable falling edge detect for interrupt.
4582  */
4583 /*@{*/
4584 /*! @brief Read current value of the DCDC_REG6_PSWITCH_INT_FALL_EN field. */
4585 #define DCDC_RD_REG6_PSWITCH_INT_FALL_EN(base) ((DCDC_REG6_REG(base) & DCDC_REG6_PSWITCH_INT_FALL_EN_MASK) >> DCDC_REG6_PSWITCH_INT_FALL_EN_SHIFT)
4586 #define DCDC_BRD_REG6_PSWITCH_INT_FALL_EN(base) (BME_UBFX32(&DCDC_REG6_REG(base), DCDC_REG6_PSWITCH_INT_FALL_EN_SHIFT, DCDC_REG6_PSWITCH_INT_FALL_EN_WIDTH))
4587 
4588 /*! @brief Set the PSWITCH_INT_FALL_EN field to a new value. */
4589 #define DCDC_WR_REG6_PSWITCH_INT_FALL_EN(base, value) (DCDC_RMW_REG6(base, DCDC_REG6_PSWITCH_INT_FALL_EN_MASK, DCDC_REG6_PSWITCH_INT_FALL_EN(value)))
4590 #define DCDC_BWR_REG6_PSWITCH_INT_FALL_EN(base, value) (BME_BFI32(&DCDC_REG6_REG(base), ((uint32_t)(value) << DCDC_REG6_PSWITCH_INT_FALL_EN_SHIFT), DCDC_REG6_PSWITCH_INT_FALL_EN_SHIFT, DCDC_REG6_PSWITCH_INT_FALL_EN_WIDTH))
4591 /*@}*/
4592 
4593 /*!
4594  * @name Register DCDC_REG6, field PSWITCH_INT_CLEAR[2] (RW)
4595  *
4596  * Write 1 to clear interrupt. Set to 0 after clear.
4597  */
4598 /*@{*/
4599 /*! @brief Read current value of the DCDC_REG6_PSWITCH_INT_CLEAR field. */
4600 #define DCDC_RD_REG6_PSWITCH_INT_CLEAR(base) ((DCDC_REG6_REG(base) & DCDC_REG6_PSWITCH_INT_CLEAR_MASK) >> DCDC_REG6_PSWITCH_INT_CLEAR_SHIFT)
4601 #define DCDC_BRD_REG6_PSWITCH_INT_CLEAR(base) (BME_UBFX32(&DCDC_REG6_REG(base), DCDC_REG6_PSWITCH_INT_CLEAR_SHIFT, DCDC_REG6_PSWITCH_INT_CLEAR_WIDTH))
4602 
4603 /*! @brief Set the PSWITCH_INT_CLEAR field to a new value. */
4604 #define DCDC_WR_REG6_PSWITCH_INT_CLEAR(base, value) (DCDC_RMW_REG6(base, DCDC_REG6_PSWITCH_INT_CLEAR_MASK, DCDC_REG6_PSWITCH_INT_CLEAR(value)))
4605 #define DCDC_BWR_REG6_PSWITCH_INT_CLEAR(base, value) (BME_BFI32(&DCDC_REG6_REG(base), ((uint32_t)(value) << DCDC_REG6_PSWITCH_INT_CLEAR_SHIFT), DCDC_REG6_PSWITCH_INT_CLEAR_SHIFT, DCDC_REG6_PSWITCH_INT_CLEAR_WIDTH))
4606 /*@}*/
4607 
4608 /*!
4609  * @name Register DCDC_REG6, field PSWITCH_INT_MUTE[3] (RW)
4610  *
4611  * Mask interrupt to SoC, edge detection result can be read from PSIWTCH_INT_STS.
4612  */
4613 /*@{*/
4614 /*! @brief Read current value of the DCDC_REG6_PSWITCH_INT_MUTE field. */
4615 #define DCDC_RD_REG6_PSWITCH_INT_MUTE(base) ((DCDC_REG6_REG(base) & DCDC_REG6_PSWITCH_INT_MUTE_MASK) >> DCDC_REG6_PSWITCH_INT_MUTE_SHIFT)
4616 #define DCDC_BRD_REG6_PSWITCH_INT_MUTE(base) (BME_UBFX32(&DCDC_REG6_REG(base), DCDC_REG6_PSWITCH_INT_MUTE_SHIFT, DCDC_REG6_PSWITCH_INT_MUTE_WIDTH))
4617 
4618 /*! @brief Set the PSWITCH_INT_MUTE field to a new value. */
4619 #define DCDC_WR_REG6_PSWITCH_INT_MUTE(base, value) (DCDC_RMW_REG6(base, DCDC_REG6_PSWITCH_INT_MUTE_MASK, DCDC_REG6_PSWITCH_INT_MUTE(value)))
4620 #define DCDC_BWR_REG6_PSWITCH_INT_MUTE(base, value) (BME_BFI32(&DCDC_REG6_REG(base), ((uint32_t)(value) << DCDC_REG6_PSWITCH_INT_MUTE_SHIFT), DCDC_REG6_PSWITCH_INT_MUTE_SHIFT, DCDC_REG6_PSWITCH_INT_MUTE_WIDTH))
4621 /*@}*/
4622 
4623 /*!
4624  * @name Register DCDC_REG6, field PSWITCH_INT_STS[31] (RO)
4625  *
4626  * PSWITCH edge detection interrupt status
4627  */
4628 /*@{*/
4629 /*! @brief Read current value of the DCDC_REG6_PSWITCH_INT_STS field. */
4630 #define DCDC_RD_REG6_PSWITCH_INT_STS(base) ((DCDC_REG6_REG(base) & DCDC_REG6_PSWITCH_INT_STS_MASK) >> DCDC_REG6_PSWITCH_INT_STS_SHIFT)
4631 #define DCDC_BRD_REG6_PSWITCH_INT_STS(base) (BME_UBFX32(&DCDC_REG6_REG(base), DCDC_REG6_PSWITCH_INT_STS_SHIFT, DCDC_REG6_PSWITCH_INT_STS_WIDTH))
4632 /*@}*/
4633 
4634 /*******************************************************************************
4635  * DCDC_REG7 - DCDC REGISTER 7
4636  ******************************************************************************/
4637 
4638 /*!
4639  * @brief DCDC_REG7 - DCDC REGISTER 7 (RW)
4640  *
4641  * Reset value: 0x00000000U
4642  */
4643 /*!
4644  * @name Constants and macros for entire DCDC_REG7 register
4645  */
4646 /*@{*/
4647 #define DCDC_RD_REG7(base)       (DCDC_REG7_REG(base))
4648 #define DCDC_WR_REG7(base, value) (DCDC_REG7_REG(base) = (value))
4649 #define DCDC_RMW_REG7(base, mask, value) (DCDC_WR_REG7(base, (DCDC_RD_REG7(base) & ~(mask)) | (value)))
4650 #define DCDC_SET_REG7(base, value) (BME_OR32(&DCDC_REG7_REG(base), (uint32_t)(value)))
4651 #define DCDC_CLR_REG7(base, value) (BME_AND32(&DCDC_REG7_REG(base), (uint32_t)(~(value))))
4652 #define DCDC_TOG_REG7(base, value) (BME_XOR32(&DCDC_REG7_REG(base), (uint32_t)(value)))
4653 /*@}*/
4654 
4655 /*
4656  * Constants & macros for individual DCDC_REG7 bitfields
4657  */
4658 
4659 /*!
4660  * @name Register DCDC_REG7, field INTEGRATOR_VALUE[18:0] (RW)
4661  *
4662  * Integrator value which can be loaded in pulsed mode. Software can program
4663  * this value according to battery voltage and VDD1P45 output target value before
4664  * goes to the pulsed mode. It is signed number. The register value = (Dutycycle *
4665  * 32 - 16) * 2 ^ 13 For buck mode, dutycycle = VDD1P45 / Vbat.For boost mode,
4666  * dutycycle = (VDD1P45 - Vbat) / VDD1P45.
4667  */
4668 /*@{*/
4669 /*! @brief Read current value of the DCDC_REG7_INTEGRATOR_VALUE field. */
4670 #define DCDC_RD_REG7_INTEGRATOR_VALUE(base) ((DCDC_REG7_REG(base) & DCDC_REG7_INTEGRATOR_VALUE_MASK) >> DCDC_REG7_INTEGRATOR_VALUE_SHIFT)
4671 #define DCDC_BRD_REG7_INTEGRATOR_VALUE(base) (DCDC_RD_REG7_INTEGRATOR_VALUE(base))
4672 
4673 /*! @brief Set the INTEGRATOR_VALUE field to a new value. */
4674 #define DCDC_WR_REG7_INTEGRATOR_VALUE(base, value) (DCDC_RMW_REG7(base, DCDC_REG7_INTEGRATOR_VALUE_MASK, DCDC_REG7_INTEGRATOR_VALUE(value)))
4675 #define DCDC_BWR_REG7_INTEGRATOR_VALUE(base, value) (DCDC_WR_REG7_INTEGRATOR_VALUE(base, value))
4676 /*@}*/
4677 
4678 /*!
4679  * @name Register DCDC_REG7, field INTEGRATOR_VALUE_SEL[19] (RW)
4680  *
4681  * Select the integrator value from above register or saved value in hardware.
4682  */
4683 /*@{*/
4684 /*! @brief Read current value of the DCDC_REG7_INTEGRATOR_VALUE_SEL field. */
4685 #define DCDC_RD_REG7_INTEGRATOR_VALUE_SEL(base) ((DCDC_REG7_REG(base) & DCDC_REG7_INTEGRATOR_VALUE_SEL_MASK) >> DCDC_REG7_INTEGRATOR_VALUE_SEL_SHIFT)
4686 #define DCDC_BRD_REG7_INTEGRATOR_VALUE_SEL(base) (BME_UBFX32(&DCDC_REG7_REG(base), DCDC_REG7_INTEGRATOR_VALUE_SEL_SHIFT, DCDC_REG7_INTEGRATOR_VALUE_SEL_WIDTH))
4687 
4688 /*! @brief Set the INTEGRATOR_VALUE_SEL field to a new value. */
4689 #define DCDC_WR_REG7_INTEGRATOR_VALUE_SEL(base, value) (DCDC_RMW_REG7(base, DCDC_REG7_INTEGRATOR_VALUE_SEL_MASK, DCDC_REG7_INTEGRATOR_VALUE_SEL(value)))
4690 #define DCDC_BWR_REG7_INTEGRATOR_VALUE_SEL(base, value) (BME_BFI32(&DCDC_REG7_REG(base), ((uint32_t)(value) << DCDC_REG7_INTEGRATOR_VALUE_SEL_SHIFT), DCDC_REG7_INTEGRATOR_VALUE_SEL_SHIFT, DCDC_REG7_INTEGRATOR_VALUE_SEL_WIDTH))
4691 /*@}*/
4692 
4693 /*!
4694  * @name Register DCDC_REG7, field PULSE_RUN_SPEEDUP[20] (RW)
4695  *
4696  * Enable pulse run speedup. Before setting this bit, INTEGRATOR_VALUE_SEL must
4697  * be set to 1'b1 and integrator value must be programmed.
4698  */
4699 /*@{*/
4700 /*! @brief Read current value of the DCDC_REG7_PULSE_RUN_SPEEDUP field. */
4701 #define DCDC_RD_REG7_PULSE_RUN_SPEEDUP(base) ((DCDC_REG7_REG(base) & DCDC_REG7_PULSE_RUN_SPEEDUP_MASK) >> DCDC_REG7_PULSE_RUN_SPEEDUP_SHIFT)
4702 #define DCDC_BRD_REG7_PULSE_RUN_SPEEDUP(base) (BME_UBFX32(&DCDC_REG7_REG(base), DCDC_REG7_PULSE_RUN_SPEEDUP_SHIFT, DCDC_REG7_PULSE_RUN_SPEEDUP_WIDTH))
4703 
4704 /*! @brief Set the PULSE_RUN_SPEEDUP field to a new value. */
4705 #define DCDC_WR_REG7_PULSE_RUN_SPEEDUP(base, value) (DCDC_RMW_REG7(base, DCDC_REG7_PULSE_RUN_SPEEDUP_MASK, DCDC_REG7_PULSE_RUN_SPEEDUP(value)))
4706 #define DCDC_BWR_REG7_PULSE_RUN_SPEEDUP(base, value) (BME_BFI32(&DCDC_REG7_REG(base), ((uint32_t)(value) << DCDC_REG7_PULSE_RUN_SPEEDUP_SHIFT), DCDC_REG7_PULSE_RUN_SPEEDUP_SHIFT, DCDC_REG7_PULSE_RUN_SPEEDUP_WIDTH))
4707 /*@}*/
4708 
4709 /*
4710  * MKW40Z4 DMA
4711  *
4712  * DMA Controller
4713  *
4714  * Registers defined in this header file:
4715  * - DMA_SAR - Source Address Register
4716  * - DMA_DAR - Destination Address Register
4717  * - DMA_DSR - DMA_DSR0 register.
4718  * - DMA_DSR_BCR - DMA Status Register / Byte Count Register
4719  * - DMA_DCR - DMA Control Register
4720  */
4721 
4722 #define DMA_INSTANCE_COUNT (1U) /*!< Number of instances of the DMA module. */
4723 #define DMA_IDX (0U) /*!< Instance number for DMA. */
4724 
4725 /*******************************************************************************
4726  * DMA_SAR - Source Address Register
4727  ******************************************************************************/
4728 
4729 /*!
4730  * @brief DMA_SAR - Source Address Register (RW)
4731  *
4732  * Reset value: 0x00000000U
4733  *
4734  * For this register: Only 32-bit writes are allowed. 16-bit and 8-bit writes
4735  * result in a bus error. Only several values are allowed to be written to bits
4736  * 31-20 of this register, see the value list in the field description. A write of
4737  * any other value to these bits causes a configuration error when the channel
4738  * starts to execute. For more information about the configuration error, see the
4739  * description of the CEConfiguration Error field of DSR.
4740  */
4741 /*!
4742  * @name Constants and macros for entire DMA_SAR register
4743  */
4744 /*@{*/
4745 #define DMA_RD_SAR(base, index)  (DMA_SAR_REG(base, index))
4746 #define DMA_WR_SAR(base, index, value) (DMA_SAR_REG(base, index) = (value))
4747 #define DMA_RMW_SAR(base, index, mask, value) (DMA_WR_SAR(base, index, (DMA_RD_SAR(base, index) & ~(mask)) | (value)))
4748 #define DMA_SET_SAR(base, index, value) (BME_OR32(&DMA_SAR_REG(base, index), (uint32_t)(value)))
4749 #define DMA_CLR_SAR(base, index, value) (BME_AND32(&DMA_SAR_REG(base, index), (uint32_t)(~(value))))
4750 #define DMA_TOG_SAR(base, index, value) (BME_XOR32(&DMA_SAR_REG(base, index), (uint32_t)(value)))
4751 /*@}*/
4752 
4753 /*******************************************************************************
4754  * DMA_DAR - Destination Address Register
4755  ******************************************************************************/
4756 
4757 /*!
4758  * @brief DMA_DAR - Destination Address Register (RW)
4759  *
4760  * Reset value: 0x00000000U
4761  *
4762  * For this register: Only 32-bit writes are allowed. 16-bit and 8-bit writes
4763  * result in a bus error. Only several values are allowed to be written to bits
4764  * 31-20 of this register, see the value list in the field description. A write of
4765  * any other value to these bits causes a configuration error when the channel
4766  * starts to execute. For more information about the configuration error, see the
4767  * description of the CEConfiguration Error field of DSR.
4768  */
4769 /*!
4770  * @name Constants and macros for entire DMA_DAR register
4771  */
4772 /*@{*/
4773 #define DMA_RD_DAR(base, index)  (DMA_DAR_REG(base, index))
4774 #define DMA_WR_DAR(base, index, value) (DMA_DAR_REG(base, index) = (value))
4775 #define DMA_RMW_DAR(base, index, mask, value) (DMA_WR_DAR(base, index, (DMA_RD_DAR(base, index) & ~(mask)) | (value)))
4776 #define DMA_SET_DAR(base, index, value) (BME_OR32(&DMA_DAR_REG(base, index), (uint32_t)(value)))
4777 #define DMA_CLR_DAR(base, index, value) (BME_AND32(&DMA_DAR_REG(base, index), (uint32_t)(~(value))))
4778 #define DMA_TOG_DAR(base, index, value) (BME_XOR32(&DMA_DAR_REG(base, index), (uint32_t)(value)))
4779 /*@}*/
4780 
4781 /*******************************************************************************
4782  * DMA_DSR_BCR - DMA Status Register / Byte Count Register
4783  ******************************************************************************/
4784 
4785 /*!
4786  * @brief DMA_DSR_BCR - DMA Status Register / Byte Count Register (RW)
4787  *
4788  * Reset value: 0x00000000U
4789  *
4790  * DSR and BCR are two logical registers that occupy one 32-bit address. DSRn
4791  * occupies bits 31-24, and BCRn occupies bits 23-0. DSRn contains flags indicating
4792  * the channel status, and BCRn contains the number of bytes yet to be
4793  * transferred for a given block. On the successful completion of the write transfer, BCRn
4794  * decrements by 1, 2, or 4 for 8-bit, 16-bit, or 32-bit accesses, respectively.
4795  * BCRn is cleared if a 1 is written to DSR[DONE]. In response to an event, the
4796  * DMA controller writes to the appropriate DSRn bit. Only a write to DSRn[DONE]
4797  * results in action. DSRn[DONE] is set when the block transfer is complete. When
4798  * a transfer sequence is initiated and BCRn[BCR] is not a multiple of 4 or 2
4799  * when the DMA is configured for 32-bit or 16-bit transfers, respectively,
4800  * DSRn[CE] is set and no transfer occurs.
4801  */
4802 /*!
4803  * @name Constants and macros for entire DMA_DSR_BCR register
4804  */
4805 /*@{*/
4806 #define DMA_RD_DSR_BCR(base, index) (DMA_DSR_BCR_REG(base, index))
4807 #define DMA_WR_DSR_BCR(base, index, value) (DMA_DSR_BCR_REG(base, index) = (value))
4808 #define DMA_RMW_DSR_BCR(base, index, mask, value) (DMA_WR_DSR_BCR(base, index, (DMA_RD_DSR_BCR(base, index) & ~(mask)) | (value)))
4809 #define DMA_SET_DSR_BCR(base, index, value) (BME_OR32(&DMA_DSR_BCR_REG(base, index), (uint32_t)(value)))
4810 #define DMA_CLR_DSR_BCR(base, index, value) (BME_AND32(&DMA_DSR_BCR_REG(base, index), (uint32_t)(~(value))))
4811 #define DMA_TOG_DSR_BCR(base, index, value) (BME_XOR32(&DMA_DSR_BCR_REG(base, index), (uint32_t)(value)))
4812 /*@}*/
4813 
4814 /*
4815  * Constants & macros for individual DMA_DSR_BCR bitfields
4816  */
4817 
4818 /*!
4819  * @name Register DMA_DSR_BCR, field BCR[23:0] (RW)
4820  *
4821  * This field contains the number of bytes yet to be transferred for a given
4822  * block. BCR must be written with a value equal to or less than 0F_FFFFh. After
4823  * being written with a value in this range, bits 23-20 of BCR read back as 0000b. A
4824  * write to BCR of a value greater than 0F_FFFFh causes a configuration error
4825  * when the channel starts to execute. After being written with a value in this
4826  * range, bits 23-20 of BCR read back as 0001b.
4827  */
4828 /*@{*/
4829 /*! @brief Read current value of the DMA_DSR_BCR_BCR field. */
4830 #define DMA_RD_DSR_BCR_BCR(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_BCR_MASK) >> DMA_DSR_BCR_BCR_SHIFT)
4831 #define DMA_BRD_DSR_BCR_BCR(base, index) (DMA_RD_DSR_BCR_BCR(base, index))
4832 
4833 /*! @brief Set the BCR field to a new value. */
4834 #define DMA_WR_DSR_BCR_BCR(base, index, value) (DMA_RMW_DSR_BCR(base, index, (DMA_DSR_BCR_BCR_MASK | DMA_DSR_BCR_DONE_MASK), DMA_DSR_BCR_BCR(value)))
4835 #define DMA_BWR_DSR_BCR_BCR(base, index, value) (DMA_WR_DSR_BCR_BCR(base, index, value))
4836 /*@}*/
4837 
4838 /*!
4839  * @name Register DMA_DSR_BCR, field DONE[24] (W1C)
4840  *
4841  * Set when all DMA controller transactions complete as determined by transfer
4842  * count, or based on error conditions. When BCR reaches 0, DONE is set when the
4843  * final transfer completes successfully. DONE can also be used to abort a
4844  * transfer by resetting the status bits. When a transfer completes, software must clear
4845  * DONE before reprogramming the DMA.
4846  *
4847  * Values:
4848  * - 0b0 - DMA transfer is not yet complete. Writing a 0 has no effect.
4849  * - 0b1 - DMA transfer completed. Writing a 1 to this bit clears all DMA status
4850  *     bits and should be used in an interrupt service routine to clear the DMA
4851  *     interrupt and error bits.
4852  */
4853 /*@{*/
4854 /*! @brief Read current value of the DMA_DSR_BCR_DONE field. */
4855 #define DMA_RD_DSR_BCR_DONE(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_DONE_MASK) >> DMA_DSR_BCR_DONE_SHIFT)
4856 #define DMA_BRD_DSR_BCR_DONE(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_DONE_SHIFT, DMA_DSR_BCR_DONE_WIDTH))
4857 
4858 /*! @brief Set the DONE field to a new value. */
4859 #define DMA_WR_DSR_BCR_DONE(base, index, value) (DMA_RMW_DSR_BCR(base, index, DMA_DSR_BCR_DONE_MASK, DMA_DSR_BCR_DONE(value)))
4860 #define DMA_BWR_DSR_BCR_DONE(base, index, value) (BME_BFI32(&DMA_DSR_BCR_REG(base, index), ((uint32_t)(value) << DMA_DSR_BCR_DONE_SHIFT), DMA_DSR_BCR_DONE_SHIFT, DMA_DSR_BCR_DONE_WIDTH))
4861 /*@}*/
4862 
4863 /*!
4864  * @name Register DMA_DSR_BCR, field BSY[25] (RO)
4865  *
4866  * Values:
4867  * - 0b0 - DMA channel is inactive. Cleared when the DMA has finished the last
4868  *     transaction.
4869  * - 0b1 - BSY is set the first time the channel is enabled after a transfer is
4870  *     initiated.
4871  */
4872 /*@{*/
4873 /*! @brief Read current value of the DMA_DSR_BCR_BSY field. */
4874 #define DMA_RD_DSR_BCR_BSY(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_BSY_MASK) >> DMA_DSR_BCR_BSY_SHIFT)
4875 #define DMA_BRD_DSR_BCR_BSY(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_BSY_SHIFT, DMA_DSR_BCR_BSY_WIDTH))
4876 /*@}*/
4877 
4878 /*!
4879  * @name Register DMA_DSR_BCR, field REQ[26] (RO)
4880  *
4881  * Values:
4882  * - 0b0 - No request is pending or the channel is currently active. Cleared
4883  *     when the channel is selected.
4884  * - 0b1 - The DMA channel has a transfer remaining and the channel is not
4885  *     selected.
4886  */
4887 /*@{*/
4888 /*! @brief Read current value of the DMA_DSR_BCR_REQ field. */
4889 #define DMA_RD_DSR_BCR_REQ(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_REQ_MASK) >> DMA_DSR_BCR_REQ_SHIFT)
4890 #define DMA_BRD_DSR_BCR_REQ(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_REQ_SHIFT, DMA_DSR_BCR_REQ_WIDTH))
4891 /*@}*/
4892 
4893 /*!
4894  * @name Register DMA_DSR_BCR, field BED[28] (RO)
4895  *
4896  * BED is cleared at hardware reset or by writing a 1 to DONE.
4897  *
4898  * Values:
4899  * - 0b0 - No bus error occurred.
4900  * - 0b1 - The DMA channel terminated with a bus error during the write portion
4901  *     of a transfer.
4902  */
4903 /*@{*/
4904 /*! @brief Read current value of the DMA_DSR_BCR_BED field. */
4905 #define DMA_RD_DSR_BCR_BED(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_BED_MASK) >> DMA_DSR_BCR_BED_SHIFT)
4906 #define DMA_BRD_DSR_BCR_BED(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_BED_SHIFT, DMA_DSR_BCR_BED_WIDTH))
4907 /*@}*/
4908 
4909 /*!
4910  * @name Register DMA_DSR_BCR, field BES[29] (RO)
4911  *
4912  * BES is cleared at hardware reset or by writing a 1 to DONE.
4913  *
4914  * Values:
4915  * - 0b0 - No bus error occurred.
4916  * - 0b1 - The DMA channel terminated with a bus error during the read portion
4917  *     of a transfer.
4918  */
4919 /*@{*/
4920 /*! @brief Read current value of the DMA_DSR_BCR_BES field. */
4921 #define DMA_RD_DSR_BCR_BES(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_BES_MASK) >> DMA_DSR_BCR_BES_SHIFT)
4922 #define DMA_BRD_DSR_BCR_BES(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_BES_SHIFT, DMA_DSR_BCR_BES_WIDTH))
4923 /*@}*/
4924 
4925 /*!
4926  * @name Register DMA_DSR_BCR, field CE[30] (RO)
4927  *
4928  * Any of the following conditions causes a configuration error: BCR, SAR, or
4929  * DAR does not match the requested transfer size. A value greater than 0F_FFFFh is
4930  * written to BCR. Bits 31-20 of SAR or DAR are written with a value other than
4931  * one of the allowed values. See SARSAR and DARDAR . SSIZE or DSIZE is set to an
4932  * unsupported value. BCR equals 0 when the DMA receives a start condition. CE
4933  * is cleared at hardware reset or by writing a 1 to DONE.
4934  *
4935  * Values:
4936  * - 0b0 - No configuration error exists.
4937  * - 0b1 - A configuration error has occurred.
4938  */
4939 /*@{*/
4940 /*! @brief Read current value of the DMA_DSR_BCR_CE field. */
4941 #define DMA_RD_DSR_BCR_CE(base, index) ((DMA_DSR_BCR_REG(base, index) & DMA_DSR_BCR_CE_MASK) >> DMA_DSR_BCR_CE_SHIFT)
4942 #define DMA_BRD_DSR_BCR_CE(base, index) (BME_UBFX32(&DMA_DSR_BCR_REG(base, index), DMA_DSR_BCR_CE_SHIFT, DMA_DSR_BCR_CE_WIDTH))
4943 /*@}*/
4944 
4945 /*******************************************************************************
4946  * DMA_DSR - DMA_DSR0 register.
4947  ******************************************************************************/
4948 
4949 /*!
4950  * @brief DMA_DSR - DMA_DSR0 register. (RW)
4951  *
4952  * Reset value: 0x00U
4953  */
4954 /*!
4955  * @name Constants and macros for entire DMA_DSR register
4956  */
4957 /*@{*/
4958 #define DMA_RD_DSR(base, index)  (DMA_DSR_REG(base, index))
4959 #define DMA_WR_DSR(base, index, value) (DMA_DSR_REG(base, index) = (value))
4960 #define DMA_RMW_DSR(base, index, mask, value) (DMA_WR_DSR(base, index, (DMA_RD_DSR(base, index) & ~(mask)) | (value)))
4961 #define DMA_SET_DSR(base, index, value) (BME_OR8(&DMA_DSR_REG(base, index), (uint8_t)(value)))
4962 #define DMA_CLR_DSR(base, index, value) (BME_AND8(&DMA_DSR_REG(base, index), (uint8_t)(~(value))))
4963 #define DMA_TOG_DSR(base, index, value) (BME_XOR8(&DMA_DSR_REG(base, index), (uint8_t)(value)))
4964 /*@}*/
4965 
4966 /*******************************************************************************
4967  * DMA_DCR - DMA Control Register
4968  ******************************************************************************/
4969 
4970 /*!
4971  * @brief DMA_DCR - DMA Control Register (RW)
4972  *
4973  * Reset value: 0x00000000U
4974  */
4975 /*!
4976  * @name Constants and macros for entire DMA_DCR register
4977  */
4978 /*@{*/
4979 #define DMA_RD_DCR(base, index)  (DMA_DCR_REG(base, index))
4980 #define DMA_WR_DCR(base, index, value) (DMA_DCR_REG(base, index) = (value))
4981 #define DMA_RMW_DCR(base, index, mask, value) (DMA_WR_DCR(base, index, (DMA_RD_DCR(base, index) & ~(mask)) | (value)))
4982 #define DMA_SET_DCR(base, index, value) (BME_OR32(&DMA_DCR_REG(base, index), (uint32_t)(value)))
4983 #define DMA_CLR_DCR(base, index, value) (BME_AND32(&DMA_DCR_REG(base, index), (uint32_t)(~(value))))
4984 #define DMA_TOG_DCR(base, index, value) (BME_XOR32(&DMA_DCR_REG(base, index), (uint32_t)(value)))
4985 /*@}*/
4986 
4987 /*
4988  * Constants & macros for individual DMA_DCR bitfields
4989  */
4990 
4991 /*!
4992  * @name Register DMA_DCR, field LCH2[1:0] (RW)
4993  *
4994  * The 2-bit link channel number under control of the encoded link control
4995  * field, LINKCC.
4996  *
4997  * Values:
4998  * - 0b00 - DMA Channel 0
4999  * - 0b01 - DMA Channel 1
5000  * - 0b10 - DMA Channel 2
5001  * - 0b11 - DMA Channel 3
5002  */
5003 /*@{*/
5004 /*! @brief Read current value of the DMA_DCR_LCH2 field. */
5005 #define DMA_RD_DCR_LCH2(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_LCH2_MASK) >> DMA_DCR_LCH2_SHIFT)
5006 #define DMA_BRD_DCR_LCH2(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_LCH2_SHIFT, DMA_DCR_LCH2_WIDTH))
5007 
5008 /*! @brief Set the LCH2 field to a new value. */
5009 #define DMA_WR_DCR_LCH2(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_LCH2_MASK, DMA_DCR_LCH2(value)))
5010 #define DMA_BWR_DCR_LCH2(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_LCH2_SHIFT), DMA_DCR_LCH2_SHIFT, DMA_DCR_LCH2_WIDTH))
5011 /*@}*/
5012 
5013 /*!
5014  * @name Register DMA_DCR, field LCH1[3:2] (RW)
5015  *
5016  * The 2-bit link channel number under control of the encoded link control
5017  * field, LINKCC.
5018  *
5019  * Values:
5020  * - 0b00 - DMA Channel 0
5021  * - 0b01 - DMA Channel 1
5022  * - 0b10 - DMA Channel 2
5023  * - 0b11 - DMA Channel 3
5024  */
5025 /*@{*/
5026 /*! @brief Read current value of the DMA_DCR_LCH1 field. */
5027 #define DMA_RD_DCR_LCH1(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_LCH1_MASK) >> DMA_DCR_LCH1_SHIFT)
5028 #define DMA_BRD_DCR_LCH1(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_LCH1_SHIFT, DMA_DCR_LCH1_WIDTH))
5029 
5030 /*! @brief Set the LCH1 field to a new value. */
5031 #define DMA_WR_DCR_LCH1(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_LCH1_MASK, DMA_DCR_LCH1(value)))
5032 #define DMA_BWR_DCR_LCH1(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_LCH1_SHIFT), DMA_DCR_LCH1_SHIFT, DMA_DCR_LCH1_WIDTH))
5033 /*@}*/
5034 
5035 /*!
5036  * @name Register DMA_DCR, field LINKCC[5:4] (RW)
5037  *
5038  * The LINKCC field provides a 2-bit encoded value defining the applicable
5039  * channel-to-channel linking. If not in cycle steal mode (DCRn[CS]=0) and LINKCC
5040  * equals 01 or 10, no link to LCH1 occurs. The link channel (LCH1, LCH2) number
5041  * cannot be the same as the currently executing channel, and generates a
5042  * configuration error if this is attempted (DSRn[CE] is set). This type of configuration
5043  * error sets both DSRn[7:6]. The DSRn[CE] bit is set the standard configuration
5044  * error flag, while DSRn[7] is a new flag to explicitly signal an linking
5045  * configuration error. If LINKCC equals 01, a link to LCH1 is created after each
5046  * cycle-steal transfer except the last one is completed. As the last cycle-steal is
5047  * performed and the BCR is done, then the link to LCH1 is closed and a link to LCH2
5048  * is created.
5049  *
5050  * Values:
5051  * - 0b00 - No channel-to-channel linking
5052  * - 0b01 - Perform a link to channel LCH1 after each cycle-steal transfer
5053  *     followed by a link to LCH2 after the BCR decrements to 0.
5054  * - 0b10 - Perform a link to channel LCH1 after each cycle-steal transfer
5055  * - 0b11 - Perform a link to channel LCH1 after the BCR decrements to 0.
5056  */
5057 /*@{*/
5058 /*! @brief Read current value of the DMA_DCR_LINKCC field. */
5059 #define DMA_RD_DCR_LINKCC(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_LINKCC_MASK) >> DMA_DCR_LINKCC_SHIFT)
5060 #define DMA_BRD_DCR_LINKCC(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_LINKCC_SHIFT, DMA_DCR_LINKCC_WIDTH))
5061 
5062 /*! @brief Set the LINKCC field to a new value. */
5063 #define DMA_WR_DCR_LINKCC(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_LINKCC_MASK, DMA_DCR_LINKCC(value)))
5064 #define DMA_BWR_DCR_LINKCC(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_LINKCC_SHIFT), DMA_DCR_LINKCC_SHIFT, DMA_DCR_LINKCC_WIDTH))
5065 /*@}*/
5066 
5067 /*!
5068  * @name Register DMA_DCR, field D_REQ[7] (RW)
5069  *
5070  * If this flag is set, the DMA hardware automatically clears the corresponding
5071  * DCRn[ERQ] bit when the byte count register reaches 0.
5072  *
5073  * Values:
5074  * - 0b0 - The channel's ERQ bit is not affected.
5075  * - 0b1 - The channel's ERQ bit is cleared when the BCR is exhausted.
5076  */
5077 /*@{*/
5078 /*! @brief Read current value of the DMA_DCR_D_REQ field. */
5079 #define DMA_RD_DCR_D_REQ(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_D_REQ_MASK) >> DMA_DCR_D_REQ_SHIFT)
5080 #define DMA_BRD_DCR_D_REQ(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_D_REQ_SHIFT, DMA_DCR_D_REQ_WIDTH))
5081 
5082 /*! @brief Set the D_REQ field to a new value. */
5083 #define DMA_WR_DCR_D_REQ(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_D_REQ_MASK, DMA_DCR_D_REQ(value)))
5084 #define DMA_BWR_DCR_D_REQ(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_D_REQ_SHIFT), DMA_DCR_D_REQ_SHIFT, DMA_DCR_D_REQ_WIDTH))
5085 /*@}*/
5086 
5087 /*!
5088  * @name Register DMA_DCR, field DMOD[11:8] (RW)
5089  *
5090  * Defines the size of the destination data circular buffer used by the DMA
5091  * Controller. If enabled (DMOD value is non-zero), the buffer base address is
5092  * located on a boundary of the buffer size. The value of this boundary depends on the
5093  * initial destination address (DAR). The base address should be aligned to a
5094  * 0-modulo-(circular buffer size) boundary. Misaligned buffers are not possible.
5095  * The boundary is forced to the value determined by the upper address bits in the
5096  * field selection. Same functionality as SMOD, except it is applied to the
5097  * destination address generation.
5098  *
5099  * Values:
5100  * - 0b0000 - Buffer disabled
5101  * - 0b0001 - Circular buffer size is 16 bytes
5102  * - 0b0010 - Circular buffer size is 32 bytes
5103  * - 0b0011 - Circular buffer size is 64 bytes
5104  * - 0b0100 - Circular buffer size is 128 bytes
5105  * - 0b0101 - Circular buffer size is 256 bytes
5106  * - 0b0110 - Circular buffer size is 512 bytes
5107  * - 0b0111 - Circular buffer size is 1 KB
5108  * - 0b1000 - Circular buffer size is 2 KB
5109  * - 0b1001 - Circular buffer size is 4 KB
5110  * - 0b1010 - Circular buffer size is 8 KB
5111  * - 0b1011 - Circular buffer size is 16 KB
5112  * - 0b1100 - Circular buffer size is 32 KB
5113  * - 0b1101 - Circular buffer size is 64 KB
5114  * - 0b1110 - Circular buffer size is 128 KB
5115  * - 0b1111 - Circular buffer size is 256 KB
5116  */
5117 /*@{*/
5118 /*! @brief Read current value of the DMA_DCR_DMOD field. */
5119 #define DMA_RD_DCR_DMOD(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_DMOD_MASK) >> DMA_DCR_DMOD_SHIFT)
5120 #define DMA_BRD_DCR_DMOD(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_DMOD_SHIFT, DMA_DCR_DMOD_WIDTH))
5121 
5122 /*! @brief Set the DMOD field to a new value. */
5123 #define DMA_WR_DCR_DMOD(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_DMOD_MASK, DMA_DCR_DMOD(value)))
5124 #define DMA_BWR_DCR_DMOD(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_DMOD_SHIFT), DMA_DCR_DMOD_SHIFT, DMA_DCR_DMOD_WIDTH))
5125 /*@}*/
5126 
5127 /*!
5128  * @name Register DMA_DCR, field SMOD[15:12] (RW)
5129  *
5130  * Defines the size of the source data circular buffer used by the DMA
5131  * Controller. If enabled (SMOD is non-zero), the buffer base address is located on a
5132  * boundary of the buffer size. The value of this boundary is based upon the initial
5133  * source address (SAR). The base address should be aligned to a
5134  * 0-modulo-(circular buffer size) boundary. Misaligned buffers are not possible. The boundary is
5135  * forced to the value determined by the upper address bits in the field
5136  * selection. 0 Source address modulo feature is disabled. non-0: The value defines each
5137  * address bit which is selected to be either the value after next-state SAR
5138  * calculation is performed or the current SAR register value. This feature provides
5139  * the ability to easily implement circular data queues. For data queues
5140  * requiring power-of-2 "size" bytes, the queue should be based at a 0-modulo-size
5141  * address and the SMOD field set to the appropriate value to effectively freeze the
5142  * upper address bits. The bit select is defined as ((1 << SMOD+3) - 1) where a
5143  * resulting 1 in a bit location selects the next state address for the
5144  * corresponding address bit location and a 0 selects the original register value for the
5145  * corresponding address bit location. The modulo implementation includes 32
5146  * one-bit 2-to-1 muxes connected to the source address register and the output of an
5147  * adder used to generate the next-state address. The adder sums the source
5148  * address register with an offset calculated based on the transfer size and increment
5149  * control (DCRn[SSIZE, SINC]). The 32-bit wide select vector is formed using the
5150  * expression noted above and is then used to select either the source address
5151  * register bit (select = 0) or the corresponding bit position from the adder
5152  * output (select = 1) for each bit of the next-state source address. This
5153  * functionality supports circular queues ranging in size from 16 bytes (SMOD = 1) to 256
5154  * KB (SMOD = 15).
5155  *
5156  * Values:
5157  * - 0b0000 - Buffer disabled
5158  * - 0b0001 - Circular buffer size is 16 bytes.
5159  * - 0b0010 - Circular buffer size is 32 bytes.
5160  * - 0b0011 - Circular buffer size is 64 bytes.
5161  * - 0b0100 - Circular buffer size is 128 bytes.
5162  * - 0b0101 - Circular buffer size is 256 bytes.
5163  * - 0b0110 - Circular buffer size is 512 bytes.
5164  * - 0b0111 - Circular buffer size is 1 KB.
5165  * - 0b1000 - Circular buffer size is 2 KB.
5166  * - 0b1001 - Circular buffer size is 4 KB.
5167  * - 0b1010 - Circular buffer size is 8 KB.
5168  * - 0b1011 - Circular buffer size is 16 KB.
5169  * - 0b1100 - Circular buffer size is 32 KB.
5170  * - 0b1101 - Circular buffer size is 64 KB.
5171  * - 0b1110 - Circular buffer size is 128 KB.
5172  * - 0b1111 - Circular buffer size is 256 KB.
5173  */
5174 /*@{*/
5175 /*! @brief Read current value of the DMA_DCR_SMOD field. */
5176 #define DMA_RD_DCR_SMOD(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_SMOD_MASK) >> DMA_DCR_SMOD_SHIFT)
5177 #define DMA_BRD_DCR_SMOD(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_SMOD_SHIFT, DMA_DCR_SMOD_WIDTH))
5178 
5179 /*! @brief Set the SMOD field to a new value. */
5180 #define DMA_WR_DCR_SMOD(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_SMOD_MASK, DMA_DCR_SMOD(value)))
5181 #define DMA_BWR_DCR_SMOD(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_SMOD_SHIFT), DMA_DCR_SMOD_SHIFT, DMA_DCR_SMOD_WIDTH))
5182 /*@}*/
5183 
5184 /*!
5185  * @name Register DMA_DCR, field START[16] (WORZ)
5186  *
5187  * Values:
5188  * - 0b0 - DMA inactive
5189  * - 0b1 - The DMA begins the transfer in accordance to the values in the TCDn.
5190  *     START is cleared automatically after one module clock and always reads as
5191  *     logic 0.
5192  */
5193 /*@{*/
5194 /*! @brief Set the START field to a new value. */
5195 #define DMA_WR_DCR_START(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_START_MASK, DMA_DCR_START(value)))
5196 #define DMA_BWR_DCR_START(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_START_SHIFT), DMA_DCR_START_SHIFT, DMA_DCR_START_WIDTH))
5197 /*@}*/
5198 
5199 /*!
5200  * @name Register DMA_DCR, field DSIZE[18:17] (RW)
5201  *
5202  * Determines the data size of the destination bus cycle for the DMA controller.
5203  *
5204  * Values:
5205  * - 0b00 - 32-bit
5206  * - 0b01 - 8-bit
5207  * - 0b10 - 16-bit
5208  * - 0b11 - Reserved (generates a configuration error (DSRn[CE]) if incorrectly
5209  *     specified at time of channel activation)
5210  */
5211 /*@{*/
5212 /*! @brief Read current value of the DMA_DCR_DSIZE field. */
5213 #define DMA_RD_DCR_DSIZE(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_DSIZE_MASK) >> DMA_DCR_DSIZE_SHIFT)
5214 #define DMA_BRD_DCR_DSIZE(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_DSIZE_SHIFT, DMA_DCR_DSIZE_WIDTH))
5215 
5216 /*! @brief Set the DSIZE field to a new value. */
5217 #define DMA_WR_DCR_DSIZE(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_DSIZE_MASK, DMA_DCR_DSIZE(value)))
5218 #define DMA_BWR_DCR_DSIZE(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_DSIZE_SHIFT), DMA_DCR_DSIZE_SHIFT, DMA_DCR_DSIZE_WIDTH))
5219 /*@}*/
5220 
5221 /*!
5222  * @name Register DMA_DCR, field DINC[19] (RW)
5223  *
5224  * Controls whether the destination address increments after each successful
5225  * transfer.
5226  *
5227  * Values:
5228  * - 0b0 - No change to the DAR after a successful transfer.
5229  * - 0b1 - The DAR increments by 1, 2, 4 depending upon the size of the transfer.
5230  */
5231 /*@{*/
5232 /*! @brief Read current value of the DMA_DCR_DINC field. */
5233 #define DMA_RD_DCR_DINC(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_DINC_MASK) >> DMA_DCR_DINC_SHIFT)
5234 #define DMA_BRD_DCR_DINC(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_DINC_SHIFT, DMA_DCR_DINC_WIDTH))
5235 
5236 /*! @brief Set the DINC field to a new value. */
5237 #define DMA_WR_DCR_DINC(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_DINC_MASK, DMA_DCR_DINC(value)))
5238 #define DMA_BWR_DCR_DINC(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_DINC_SHIFT), DMA_DCR_DINC_SHIFT, DMA_DCR_DINC_WIDTH))
5239 /*@}*/
5240 
5241 /*!
5242  * @name Register DMA_DCR, field SSIZE[21:20] (RW)
5243  *
5244  * Determines the data size of the source bus cycle for the DMA controller.
5245  *
5246  * Values:
5247  * - 0b00 - 32-bit
5248  * - 0b01 - 8-bit
5249  * - 0b10 - 16-bit
5250  * - 0b11 - Reserved (generates a configuration error (DSRn[CE]) if incorrectly
5251  *     specified at time of channel activation)
5252  */
5253 /*@{*/
5254 /*! @brief Read current value of the DMA_DCR_SSIZE field. */
5255 #define DMA_RD_DCR_SSIZE(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_SSIZE_MASK) >> DMA_DCR_SSIZE_SHIFT)
5256 #define DMA_BRD_DCR_SSIZE(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_SSIZE_SHIFT, DMA_DCR_SSIZE_WIDTH))
5257 
5258 /*! @brief Set the SSIZE field to a new value. */
5259 #define DMA_WR_DCR_SSIZE(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_SSIZE_MASK, DMA_DCR_SSIZE(value)))
5260 #define DMA_BWR_DCR_SSIZE(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_SSIZE_SHIFT), DMA_DCR_SSIZE_SHIFT, DMA_DCR_SSIZE_WIDTH))
5261 /*@}*/
5262 
5263 /*!
5264  * @name Register DMA_DCR, field SINC[22] (RW)
5265  *
5266  * Controls whether the source address increments after each successful transfer.
5267  *
5268  * Values:
5269  * - 0b0 - No change to SAR after a successful transfer.
5270  * - 0b1 - The SAR increments by 1, 2, 4 as determined by the transfer size.
5271  */
5272 /*@{*/
5273 /*! @brief Read current value of the DMA_DCR_SINC field. */
5274 #define DMA_RD_DCR_SINC(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_SINC_MASK) >> DMA_DCR_SINC_SHIFT)
5275 #define DMA_BRD_DCR_SINC(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_SINC_SHIFT, DMA_DCR_SINC_WIDTH))
5276 
5277 /*! @brief Set the SINC field to a new value. */
5278 #define DMA_WR_DCR_SINC(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_SINC_MASK, DMA_DCR_SINC(value)))
5279 #define DMA_BWR_DCR_SINC(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_SINC_SHIFT), DMA_DCR_SINC_SHIFT, DMA_DCR_SINC_WIDTH))
5280 /*@}*/
5281 
5282 /*!
5283  * @name Register DMA_DCR, field EADREQ[23] (RW)
5284  *
5285  * Enables the channel to support asynchronous DREQs while the MCU is in Stop
5286  * mode.
5287  *
5288  * Values:
5289  * - 0b0 - Disabled
5290  * - 0b1 - Enabled
5291  */
5292 /*@{*/
5293 /*! @brief Read current value of the DMA_DCR_EADREQ field. */
5294 #define DMA_RD_DCR_EADREQ(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_EADREQ_MASK) >> DMA_DCR_EADREQ_SHIFT)
5295 #define DMA_BRD_DCR_EADREQ(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_EADREQ_SHIFT, DMA_DCR_EADREQ_WIDTH))
5296 
5297 /*! @brief Set the EADREQ field to a new value. */
5298 #define DMA_WR_DCR_EADREQ(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_EADREQ_MASK, DMA_DCR_EADREQ(value)))
5299 #define DMA_BWR_DCR_EADREQ(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_EADREQ_SHIFT), DMA_DCR_EADREQ_SHIFT, DMA_DCR_EADREQ_WIDTH))
5300 /*@}*/
5301 
5302 /*!
5303  * @name Register DMA_DCR, field AA[28] (RW)
5304  *
5305  * AA and SIZE bits determine whether the source or destination is auto-aligned;
5306  * that is, transfers are optimized based on the address and size.
5307  *
5308  * Values:
5309  * - 0b0 - Auto-align disabled
5310  * - 0b1 - If SSIZE indicates a transfer no smaller than DSIZE, source accesses
5311  *     are auto-aligned; otherwise, destination accesses are auto-aligned. Source
5312  *     alignment takes precedence over destination alignment. If auto-alignment
5313  *     is enabled, the appropriate address register increments, regardless of
5314  *     DINC or SINC.
5315  */
5316 /*@{*/
5317 /*! @brief Read current value of the DMA_DCR_AA field. */
5318 #define DMA_RD_DCR_AA(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_AA_MASK) >> DMA_DCR_AA_SHIFT)
5319 #define DMA_BRD_DCR_AA(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_AA_SHIFT, DMA_DCR_AA_WIDTH))
5320 
5321 /*! @brief Set the AA field to a new value. */
5322 #define DMA_WR_DCR_AA(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_AA_MASK, DMA_DCR_AA(value)))
5323 #define DMA_BWR_DCR_AA(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_AA_SHIFT), DMA_DCR_AA_SHIFT, DMA_DCR_AA_WIDTH))
5324 /*@}*/
5325 
5326 /*!
5327  * @name Register DMA_DCR, field CS[29] (RW)
5328  *
5329  * Values:
5330  * - 0b0 - DMA continuously makes read/write transfers until the BCR decrements
5331  *     to 0.
5332  * - 0b1 - Forces a single read/write transfer per request.
5333  */
5334 /*@{*/
5335 /*! @brief Read current value of the DMA_DCR_CS field. */
5336 #define DMA_RD_DCR_CS(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_CS_MASK) >> DMA_DCR_CS_SHIFT)
5337 #define DMA_BRD_DCR_CS(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_CS_SHIFT, DMA_DCR_CS_WIDTH))
5338 
5339 /*! @brief Set the CS field to a new value. */
5340 #define DMA_WR_DCR_CS(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_CS_MASK, DMA_DCR_CS(value)))
5341 #define DMA_BWR_DCR_CS(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_CS_SHIFT), DMA_DCR_CS_SHIFT, DMA_DCR_CS_WIDTH))
5342 /*@}*/
5343 
5344 /*!
5345  * @name Register DMA_DCR, field ERQ[30] (RW)
5346  *
5347  * Be careful: a collision can occur between START and D_REQ when ERQ is 1.
5348  *
5349  * Values:
5350  * - 0b0 - Peripheral request is ignored.
5351  * - 0b1 - Enables peripheral request to initiate transfer. A software-initiated
5352  *     request (setting START) is always enabled.
5353  */
5354 /*@{*/
5355 /*! @brief Read current value of the DMA_DCR_ERQ field. */
5356 #define DMA_RD_DCR_ERQ(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_ERQ_MASK) >> DMA_DCR_ERQ_SHIFT)
5357 #define DMA_BRD_DCR_ERQ(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_ERQ_SHIFT, DMA_DCR_ERQ_WIDTH))
5358 
5359 /*! @brief Set the ERQ field to a new value. */
5360 #define DMA_WR_DCR_ERQ(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_ERQ_MASK, DMA_DCR_ERQ(value)))
5361 #define DMA_BWR_DCR_ERQ(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_ERQ_SHIFT), DMA_DCR_ERQ_SHIFT, DMA_DCR_ERQ_WIDTH))
5362 /*@}*/
5363 
5364 /*!
5365  * @name Register DMA_DCR, field EINT[31] (RW)
5366  *
5367  * Determines whether an interrupt is generated by completing a transfer or by
5368  * the occurrence of an error condition.
5369  *
5370  * Values:
5371  * - 0b0 - No interrupt is generated.
5372  * - 0b1 - SINT asserts. Interrupt signal is enabled.
5373  */
5374 /*@{*/
5375 /*! @brief Read current value of the DMA_DCR_EINT field. */
5376 #define DMA_RD_DCR_EINT(base, index) ((DMA_DCR_REG(base, index) & DMA_DCR_EINT_MASK) >> DMA_DCR_EINT_SHIFT)
5377 #define DMA_BRD_DCR_EINT(base, index) (BME_UBFX32(&DMA_DCR_REG(base, index), DMA_DCR_EINT_SHIFT, DMA_DCR_EINT_WIDTH))
5378 
5379 /*! @brief Set the EINT field to a new value. */
5380 #define DMA_WR_DCR_EINT(base, index, value) (DMA_RMW_DCR(base, index, DMA_DCR_EINT_MASK, DMA_DCR_EINT(value)))
5381 #define DMA_BWR_DCR_EINT(base, index, value) (BME_BFI32(&DMA_DCR_REG(base, index), ((uint32_t)(value) << DMA_DCR_EINT_SHIFT), DMA_DCR_EINT_SHIFT, DMA_DCR_EINT_WIDTH))
5382 /*@}*/
5383 
5384 /*
5385  * MKW40Z4 DMAMUX
5386  *
5387  * DMA channel multiplexor
5388  *
5389  * Registers defined in this header file:
5390  * - DMAMUX_CHCFG - Channel Configuration register
5391  */
5392 
5393 #define DMAMUX_INSTANCE_COUNT (1U) /*!< Number of instances of the DMAMUX module. */
5394 #define DMAMUX0_IDX (0U) /*!< Instance number for DMAMUX0. */
5395 
5396 /*******************************************************************************
5397  * DMAMUX_CHCFG - Channel Configuration register
5398  ******************************************************************************/
5399 
5400 /*!
5401  * @brief DMAMUX_CHCFG - Channel Configuration register (RW)
5402  *
5403  * Reset value: 0x00U
5404  *
5405  * Each of the DMA channels can be independently enabled/disabled and associated
5406  * with one of the DMA slots (peripheral slots or always-on slots) in the
5407  * system. Setting multiple CHCFG registers with the same source value will result in
5408  * unpredictable behavior. This is true, even if a channel is disabled (ENBL==0).
5409  * Before changing the trigger or source settings, a DMA channel must be disabled
5410  * via CHCFGn[ENBL].
5411  */
5412 /*!
5413  * @name Constants and macros for entire DMAMUX_CHCFG register
5414  */
5415 /*@{*/
5416 #define DMAMUX_RD_CHCFG(base, index) (DMAMUX_CHCFG_REG(base, index))
5417 #define DMAMUX_WR_CHCFG(base, index, value) (DMAMUX_CHCFG_REG(base, index) = (value))
5418 #define DMAMUX_RMW_CHCFG(base, index, mask, value) (DMAMUX_WR_CHCFG(base, index, (DMAMUX_RD_CHCFG(base, index) & ~(mask)) | (value)))
5419 #define DMAMUX_SET_CHCFG(base, index, value) (BME_OR8(&DMAMUX_CHCFG_REG(base, index), (uint8_t)(value)))
5420 #define DMAMUX_CLR_CHCFG(base, index, value) (BME_AND8(&DMAMUX_CHCFG_REG(base, index), (uint8_t)(~(value))))
5421 #define DMAMUX_TOG_CHCFG(base, index, value) (BME_XOR8(&DMAMUX_CHCFG_REG(base, index), (uint8_t)(value)))
5422 /*@}*/
5423 
5424 /*
5425  * Constants & macros for individual DMAMUX_CHCFG bitfields
5426  */
5427 
5428 /*!
5429  * @name Register DMAMUX_CHCFG, field SOURCE[5:0] (RW)
5430  *
5431  * Specifies which DMA source, if any, is routed to a particular DMA channel.
5432  * See the chip-specific DMAMUX information for details about the peripherals and
5433  * their slot numbers.
5434  */
5435 /*@{*/
5436 /*! @brief Read current value of the DMAMUX_CHCFG_SOURCE field. */
5437 #define DMAMUX_RD_CHCFG_SOURCE(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_SOURCE_MASK) >> DMAMUX_CHCFG_SOURCE_SHIFT)
5438 #define DMAMUX_BRD_CHCFG_SOURCE(base, index) (BME_UBFX8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_SOURCE_SHIFT, DMAMUX_CHCFG_SOURCE_WIDTH))
5439 
5440 /*! @brief Set the SOURCE field to a new value. */
5441 #define DMAMUX_WR_CHCFG_SOURCE(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_SOURCE_MASK, DMAMUX_CHCFG_SOURCE(value)))
5442 #define DMAMUX_BWR_CHCFG_SOURCE(base, index, value) (BME_BFI8(&DMAMUX_CHCFG_REG(base, index), ((uint8_t)(value) << DMAMUX_CHCFG_SOURCE_SHIFT), DMAMUX_CHCFG_SOURCE_SHIFT, DMAMUX_CHCFG_SOURCE_WIDTH))
5443 /*@}*/
5444 
5445 /*!
5446  * @name Register DMAMUX_CHCFG, field TRIG[6] (RW)
5447  *
5448  * Enables the periodic trigger capability for the triggered DMA channel.
5449  *
5450  * Values:
5451  * - 0b0 - Triggering is disabled. If triggering is disabled and ENBL is set,
5452  *     the DMA Channel will simply route the specified source to the DMA channel.
5453  *     (Normal mode)
5454  * - 0b1 - Triggering is enabled. If triggering is enabled and ENBL is set, the
5455  *     DMAMUX is in Periodic Trigger mode.
5456  */
5457 /*@{*/
5458 /*! @brief Read current value of the DMAMUX_CHCFG_TRIG field. */
5459 #define DMAMUX_RD_CHCFG_TRIG(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_TRIG_MASK) >> DMAMUX_CHCFG_TRIG_SHIFT)
5460 #define DMAMUX_BRD_CHCFG_TRIG(base, index) (BME_UBFX8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_TRIG_SHIFT, DMAMUX_CHCFG_TRIG_WIDTH))
5461 
5462 /*! @brief Set the TRIG field to a new value. */
5463 #define DMAMUX_WR_CHCFG_TRIG(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_TRIG_MASK, DMAMUX_CHCFG_TRIG(value)))
5464 #define DMAMUX_BWR_CHCFG_TRIG(base, index, value) (BME_BFI8(&DMAMUX_CHCFG_REG(base, index), ((uint8_t)(value) << DMAMUX_CHCFG_TRIG_SHIFT), DMAMUX_CHCFG_TRIG_SHIFT, DMAMUX_CHCFG_TRIG_WIDTH))
5465 /*@}*/
5466 
5467 /*!
5468  * @name Register DMAMUX_CHCFG, field ENBL[7] (RW)
5469  *
5470  * Enables the DMA channel.
5471  *
5472  * Values:
5473  * - 0b0 - DMA channel is disabled. This mode is primarily used during
5474  *     configuration of the DMAMux. The DMA has separate channel enables/disables, which
5475  *     should be used to disable or reconfigure a DMA channel.
5476  * - 0b1 - DMA channel is enabled
5477  */
5478 /*@{*/
5479 /*! @brief Read current value of the DMAMUX_CHCFG_ENBL field. */
5480 #define DMAMUX_RD_CHCFG_ENBL(base, index) ((DMAMUX_CHCFG_REG(base, index) & DMAMUX_CHCFG_ENBL_MASK) >> DMAMUX_CHCFG_ENBL_SHIFT)
5481 #define DMAMUX_BRD_CHCFG_ENBL(base, index) (BME_UBFX8(&DMAMUX_CHCFG_REG(base, index), DMAMUX_CHCFG_ENBL_SHIFT, DMAMUX_CHCFG_ENBL_WIDTH))
5482 
5483 /*! @brief Set the ENBL field to a new value. */
5484 #define DMAMUX_WR_CHCFG_ENBL(base, index, value) (DMAMUX_RMW_CHCFG(base, index, DMAMUX_CHCFG_ENBL_MASK, DMAMUX_CHCFG_ENBL(value)))
5485 #define DMAMUX_BWR_CHCFG_ENBL(base, index, value) (BME_BFI8(&DMAMUX_CHCFG_REG(base, index), ((uint8_t)(value) << DMAMUX_CHCFG_ENBL_SHIFT), DMAMUX_CHCFG_ENBL_SHIFT, DMAMUX_CHCFG_ENBL_WIDTH))
5486 /*@}*/
5487 
5488 /*
5489  * MKW40Z4 FGPIO
5490  *
5491  * General Purpose Input/Output
5492  *
5493  * Registers defined in this header file:
5494  * - FGPIO_PDOR - Port Data Output Register
5495  * - FGPIO_PSOR - Port Set Output Register
5496  * - FGPIO_PCOR - Port Clear Output Register
5497  * - FGPIO_PTOR - Port Toggle Output Register
5498  * - FGPIO_PDIR - Port Data Input Register
5499  * - FGPIO_PDDR - Port Data Direction Register
5500  */
5501 
5502 #define FGPIO_INSTANCE_COUNT (3U) /*!< Number of instances of the FGPIO module. */
5503 #define FGPIOA_IDX (0U) /*!< Instance number for FGPIOA. */
5504 #define FGPIOB_IDX (1U) /*!< Instance number for FGPIOB. */
5505 #define FGPIOC_IDX (2U) /*!< Instance number for FGPIOC. */
5506 
5507 /*******************************************************************************
5508  * FGPIO_PDOR - Port Data Output Register
5509  ******************************************************************************/
5510 
5511 /*!
5512  * @brief FGPIO_PDOR - Port Data Output Register (RW)
5513  *
5514  * Reset value: 0x00000000U
5515  *
5516  * This register configures the logic levels that are driven on each
5517  * general-purpose output pins.
5518  */
5519 /*!
5520  * @name Constants and macros for entire FGPIO_PDOR register
5521  */
5522 /*@{*/
5523 #define FGPIO_RD_PDOR(base)      (FGPIO_PDOR_REG(base))
5524 #define FGPIO_WR_PDOR(base, value) (FGPIO_PDOR_REG(base) = (value))
5525 #define FGPIO_RMW_PDOR(base, mask, value) (FGPIO_WR_PDOR(base, (FGPIO_RD_PDOR(base) & ~(mask)) | (value)))
5526 #define FGPIO_SET_PDOR(base, value) (FGPIO_WR_PDOR(base, FGPIO_RD_PDOR(base) |  (value)))
5527 #define FGPIO_CLR_PDOR(base, value) (FGPIO_WR_PDOR(base, FGPIO_RD_PDOR(base) & ~(value)))
5528 #define FGPIO_TOG_PDOR(base, value) (FGPIO_WR_PDOR(base, FGPIO_RD_PDOR(base) ^  (value)))
5529 /*@}*/
5530 
5531 /*******************************************************************************
5532  * FGPIO_PSOR - Port Set Output Register
5533  ******************************************************************************/
5534 
5535 /*!
5536  * @brief FGPIO_PSOR - Port Set Output Register (WORZ)
5537  *
5538  * Reset value: 0x00000000U
5539  *
5540  * This register configures whether to set the fields of the PDOR.
5541  */
5542 /*!
5543  * @name Constants and macros for entire FGPIO_PSOR register
5544  */
5545 /*@{*/
5546 #define FGPIO_RD_PSOR(base)      (FGPIO_PSOR_REG(base))
5547 #define FGPIO_WR_PSOR(base, value) (FGPIO_PSOR_REG(base) = (value))
5548 #define FGPIO_RMW_PSOR(base, mask, value) (FGPIO_WR_PSOR(base, (FGPIO_RD_PSOR(base) & ~(mask)) | (value)))
5549 /*@}*/
5550 
5551 /*******************************************************************************
5552  * FGPIO_PCOR - Port Clear Output Register
5553  ******************************************************************************/
5554 
5555 /*!
5556  * @brief FGPIO_PCOR - Port Clear Output Register (WORZ)
5557  *
5558  * Reset value: 0x00000000U
5559  *
5560  * This register configures whether to clear the fields of PDOR.
5561  */
5562 /*!
5563  * @name Constants and macros for entire FGPIO_PCOR register
5564  */
5565 /*@{*/
5566 #define FGPIO_RD_PCOR(base)      (FGPIO_PCOR_REG(base))
5567 #define FGPIO_WR_PCOR(base, value) (FGPIO_PCOR_REG(base) = (value))
5568 #define FGPIO_RMW_PCOR(base, mask, value) (FGPIO_WR_PCOR(base, (FGPIO_RD_PCOR(base) & ~(mask)) | (value)))
5569 /*@}*/
5570 
5571 /*******************************************************************************
5572  * FGPIO_PTOR - Port Toggle Output Register
5573  ******************************************************************************/
5574 
5575 /*!
5576  * @brief FGPIO_PTOR - Port Toggle Output Register (WORZ)
5577  *
5578  * Reset value: 0x00000000U
5579  */
5580 /*!
5581  * @name Constants and macros for entire FGPIO_PTOR register
5582  */
5583 /*@{*/
5584 #define FGPIO_RD_PTOR(base)      (FGPIO_PTOR_REG(base))
5585 #define FGPIO_WR_PTOR(base, value) (FGPIO_PTOR_REG(base) = (value))
5586 #define FGPIO_RMW_PTOR(base, mask, value) (FGPIO_WR_PTOR(base, (FGPIO_RD_PTOR(base) & ~(mask)) | (value)))
5587 /*@}*/
5588 
5589 /*******************************************************************************
5590  * FGPIO_PDIR - Port Data Input Register
5591  ******************************************************************************/
5592 
5593 /*!
5594  * @brief FGPIO_PDIR - Port Data Input Register (RO)
5595  *
5596  * Reset value: 0x00000000U
5597  */
5598 /*!
5599  * @name Constants and macros for entire FGPIO_PDIR register
5600  */
5601 /*@{*/
5602 #define FGPIO_RD_PDIR(base)      (FGPIO_PDIR_REG(base))
5603 /*@}*/
5604 
5605 /*******************************************************************************
5606  * FGPIO_PDDR - Port Data Direction Register
5607  ******************************************************************************/
5608 
5609 /*!
5610  * @brief FGPIO_PDDR - Port Data Direction Register (RW)
5611  *
5612  * Reset value: 0x00000000U
5613  *
5614  * The PDDR configures the individual port pins for input or output.
5615  */
5616 /*!
5617  * @name Constants and macros for entire FGPIO_PDDR register
5618  */
5619 /*@{*/
5620 #define FGPIO_RD_PDDR(base)      (FGPIO_PDDR_REG(base))
5621 #define FGPIO_WR_PDDR(base, value) (FGPIO_PDDR_REG(base) = (value))
5622 #define FGPIO_RMW_PDDR(base, mask, value) (FGPIO_WR_PDDR(base, (FGPIO_RD_PDDR(base) & ~(mask)) | (value)))
5623 #define FGPIO_SET_PDDR(base, value) (FGPIO_WR_PDDR(base, FGPIO_RD_PDDR(base) |  (value)))
5624 #define FGPIO_CLR_PDDR(base, value) (FGPIO_WR_PDDR(base, FGPIO_RD_PDDR(base) & ~(value)))
5625 #define FGPIO_TOG_PDDR(base, value) (FGPIO_WR_PDDR(base, FGPIO_RD_PDDR(base) ^  (value)))
5626 /*@}*/
5627 
5628 /*
5629  * MKW40Z4 FTFA
5630  *
5631  * Flash Memory Interface
5632  *
5633  * Registers defined in this header file:
5634  * - FTFA_FSTAT - Flash Status Register
5635  * - FTFA_FCNFG - Flash Configuration Register
5636  * - FTFA_FSEC - Flash Security Register
5637  * - FTFA_FOPT - Flash Option Register
5638  * - FTFA_FCCOB3 - Flash Common Command Object Registers
5639  * - FTFA_FCCOB2 - Flash Common Command Object Registers
5640  * - FTFA_FCCOB1 - Flash Common Command Object Registers
5641  * - FTFA_FCCOB0 - Flash Common Command Object Registers
5642  * - FTFA_FCCOB7 - Flash Common Command Object Registers
5643  * - FTFA_FCCOB6 - Flash Common Command Object Registers
5644  * - FTFA_FCCOB5 - Flash Common Command Object Registers
5645  * - FTFA_FCCOB4 - Flash Common Command Object Registers
5646  * - FTFA_FCCOBB - Flash Common Command Object Registers
5647  * - FTFA_FCCOBA - Flash Common Command Object Registers
5648  * - FTFA_FCCOB9 - Flash Common Command Object Registers
5649  * - FTFA_FCCOB8 - Flash Common Command Object Registers
5650  * - FTFA_FPROT3 - Program Flash Protection Registers
5651  * - FTFA_FPROT2 - Program Flash Protection Registers
5652  * - FTFA_FPROT1 - Program Flash Protection Registers
5653  * - FTFA_FPROT0 - Program Flash Protection Registers
5654  * - FTFA_XACCH3 - Execute-only Access Registers
5655  * - FTFA_XACCH2 - Execute-only Access Registers
5656  * - FTFA_XACCH1 - Execute-only Access Registers
5657  * - FTFA_XACCH0 - Execute-only Access Registers
5658  * - FTFA_XACCL3 - Execute-only Access Registers
5659  * - FTFA_XACCL2 - Execute-only Access Registers
5660  * - FTFA_XACCL1 - Execute-only Access Registers
5661  * - FTFA_XACCL0 - Execute-only Access Registers
5662  * - FTFA_SACCH3 - Supervisor-only Access Registers
5663  * - FTFA_SACCH2 - Supervisor-only Access Registers
5664  * - FTFA_SACCH1 - Supervisor-only Access Registers
5665  * - FTFA_SACCH0 - Supervisor-only Access Registers
5666  * - FTFA_SACCL3 - Supervisor-only Access Registers
5667  * - FTFA_SACCL2 - Supervisor-only Access Registers
5668  * - FTFA_SACCL1 - Supervisor-only Access Registers
5669  * - FTFA_SACCL0 - Supervisor-only Access Registers
5670  * - FTFA_FACSS - Flash Access Segment Size Register
5671  * - FTFA_FACSN - Flash Access Segment Number Register
5672  */
5673 
5674 #define FTFA_INSTANCE_COUNT (1U) /*!< Number of instances of the FTFA module. */
5675 #define FTFA_IDX (0U) /*!< Instance number for FTFA. */
5676 
5677 /*******************************************************************************
5678  * FTFA_FSTAT - Flash Status Register
5679  ******************************************************************************/
5680 
5681 /*!
5682  * @brief FTFA_FSTAT - Flash Status Register (RW)
5683  *
5684  * Reset value: 0x00U
5685  *
5686  * The FSTAT register reports the operational status of the flash memory module.
5687  * The CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The
5688  * MGSTAT0 bit is read only. The unassigned bits read 0 and are not writable. When
5689  * set, the Access Error (ACCERR) and Flash Protection Violation (FPVIOL) bits in
5690  * this register prevent the launch of any more commands until the flag is
5691  * cleared (by writing a one to it).
5692  */
5693 /*!
5694  * @name Constants and macros for entire FTFA_FSTAT register
5695  */
5696 /*@{*/
5697 #define FTFA_RD_FSTAT(base)      (FTFA_FSTAT_REG(base))
5698 #define FTFA_WR_FSTAT(base, value) (FTFA_FSTAT_REG(base) = (value))
5699 #define FTFA_RMW_FSTAT(base, mask, value) (FTFA_WR_FSTAT(base, (FTFA_RD_FSTAT(base) & ~(mask)) | (value)))
5700 #define FTFA_SET_FSTAT(base, value) (BME_OR8(&FTFA_FSTAT_REG(base), (uint8_t)(value)))
5701 #define FTFA_CLR_FSTAT(base, value) (BME_AND8(&FTFA_FSTAT_REG(base), (uint8_t)(~(value))))
5702 #define FTFA_TOG_FSTAT(base, value) (BME_XOR8(&FTFA_FSTAT_REG(base), (uint8_t)(value)))
5703 /*@}*/
5704 
5705 /*
5706  * Constants & macros for individual FTFA_FSTAT bitfields
5707  */
5708 
5709 /*!
5710  * @name Register FTFA_FSTAT, field MGSTAT0[0] (RO)
5711  *
5712  * The MGSTAT0 status flag is set if an error is detected during execution of a
5713  * flash command or during the flash reset sequence. As a status flag, this field
5714  * cannot (and need not) be cleared by the user like the other error flags in
5715  * this register. The value of the MGSTAT0 bit for "command-N" is valid only at the
5716  * end of the "command-N" execution when CCIF=1 and before the next command has
5717  * been launched. At some point during the execution of "command-N+1," the
5718  * previous result is discarded and any previous error is cleared.
5719  */
5720 /*@{*/
5721 /*! @brief Read current value of the FTFA_FSTAT_MGSTAT0 field. */
5722 #define FTFA_RD_FSTAT_MGSTAT0(base) ((FTFA_FSTAT_REG(base) & FTFA_FSTAT_MGSTAT0_MASK) >> FTFA_FSTAT_MGSTAT0_SHIFT)
5723 #define FTFA_BRD_FSTAT_MGSTAT0(base) (BME_UBFX8(&FTFA_FSTAT_REG(base), FTFA_FSTAT_MGSTAT0_SHIFT, FTFA_FSTAT_MGSTAT0_WIDTH))
5724 /*@}*/
5725 
5726 /*!
5727  * @name Register FTFA_FSTAT, field FPVIOL[4] (W1C)
5728  *
5729  * Indicates an attempt was made to program or erase an address in a protected
5730  * area of program flash memory during a command write sequence . While FPVIOL is
5731  * set, the CCIF flag cannot be cleared to launch a command. The FPVIOL bit is
5732  * cleared by writing a 1 to FPVIOL while CCIF is set. Writing a 0 to the FPVIOL
5733  * bit has no effect.
5734  *
5735  * Values:
5736  * - 0b0 - No protection violation detected
5737  * - 0b1 - Protection violation detected
5738  */
5739 /*@{*/
5740 /*! @brief Read current value of the FTFA_FSTAT_FPVIOL field. */
5741 #define FTFA_RD_FSTAT_FPVIOL(base) ((FTFA_FSTAT_REG(base) & FTFA_FSTAT_FPVIOL_MASK) >> FTFA_FSTAT_FPVIOL_SHIFT)
5742 #define FTFA_BRD_FSTAT_FPVIOL(base) (BME_UBFX8(&FTFA_FSTAT_REG(base), FTFA_FSTAT_FPVIOL_SHIFT, FTFA_FSTAT_FPVIOL_WIDTH))
5743 
5744 /*! @brief Set the FPVIOL field to a new value. */
5745 #define FTFA_WR_FSTAT_FPVIOL(base, value) (FTFA_RMW_FSTAT(base, (FTFA_FSTAT_FPVIOL_MASK | FTFA_FSTAT_ACCERR_MASK | FTFA_FSTAT_RDCOLERR_MASK | FTFA_FSTAT_CCIF_MASK), FTFA_FSTAT_FPVIOL(value)))
5746 #define FTFA_BWR_FSTAT_FPVIOL(base, value) (BME_BFI8(&FTFA_FSTAT_REG(base), ((uint8_t)(value) << FTFA_FSTAT_FPVIOL_SHIFT), FTFA_FSTAT_FPVIOL_SHIFT, FTFA_FSTAT_FPVIOL_WIDTH))
5747 /*@}*/
5748 
5749 /*!
5750  * @name Register FTFA_FSTAT, field ACCERR[5] (W1C)
5751  *
5752  * Indicates an illegal access has occurred to a flash memory resource caused by
5753  * a violation of the command write sequence or issuing an illegal flash
5754  * command. While ACCERR is set, the CCIF flag cannot be cleared to launch a command.
5755  * The ACCERR bit is cleared by writing a 1 to ACCERR while CCIF is set. Writing a
5756  * 0 to the ACCERR bit has no effect.
5757  *
5758  * Values:
5759  * - 0b0 - No access error detected
5760  * - 0b1 - Access error detected
5761  */
5762 /*@{*/
5763 /*! @brief Read current value of the FTFA_FSTAT_ACCERR field. */
5764 #define FTFA_RD_FSTAT_ACCERR(base) ((FTFA_FSTAT_REG(base) & FTFA_FSTAT_ACCERR_MASK) >> FTFA_FSTAT_ACCERR_SHIFT)
5765 #define FTFA_BRD_FSTAT_ACCERR(base) (BME_UBFX8(&FTFA_FSTAT_REG(base), FTFA_FSTAT_ACCERR_SHIFT, FTFA_FSTAT_ACCERR_WIDTH))
5766 
5767 /*! @brief Set the ACCERR field to a new value. */
5768 #define FTFA_WR_FSTAT_ACCERR(base, value) (FTFA_RMW_FSTAT(base, (FTFA_FSTAT_ACCERR_MASK | FTFA_FSTAT_FPVIOL_MASK | FTFA_FSTAT_RDCOLERR_MASK | FTFA_FSTAT_CCIF_MASK), FTFA_FSTAT_ACCERR(value)))
5769 #define FTFA_BWR_FSTAT_ACCERR(base, value) (BME_BFI8(&FTFA_FSTAT_REG(base), ((uint8_t)(value) << FTFA_FSTAT_ACCERR_SHIFT), FTFA_FSTAT_ACCERR_SHIFT, FTFA_FSTAT_ACCERR_WIDTH))
5770 /*@}*/
5771 
5772 /*!
5773  * @name Register FTFA_FSTAT, field RDCOLERR[6] (W1C)
5774  *
5775  * Indicates that the MCU attempted a read from a flash memory resource that was
5776  * being manipulated by a flash command (CCIF=0). Any simultaneous access is
5777  * detected as a collision error by the block arbitration logic. The read data in
5778  * this case cannot be guaranteed. The RDCOLERR bit is cleared by writing a 1 to
5779  * it. Writing a 0 to RDCOLERR has no effect.
5780  *
5781  * Values:
5782  * - 0b0 - No collision error detected
5783  * - 0b1 - Collision error detected
5784  */
5785 /*@{*/
5786 /*! @brief Read current value of the FTFA_FSTAT_RDCOLERR field. */
5787 #define FTFA_RD_FSTAT_RDCOLERR(base) ((FTFA_FSTAT_REG(base) & FTFA_FSTAT_RDCOLERR_MASK) >> FTFA_FSTAT_RDCOLERR_SHIFT)
5788 #define FTFA_BRD_FSTAT_RDCOLERR(base) (BME_UBFX8(&FTFA_FSTAT_REG(base), FTFA_FSTAT_RDCOLERR_SHIFT, FTFA_FSTAT_RDCOLERR_WIDTH))
5789 
5790 /*! @brief Set the RDCOLERR field to a new value. */
5791 #define FTFA_WR_FSTAT_RDCOLERR(base, value) (FTFA_RMW_FSTAT(base, (FTFA_FSTAT_RDCOLERR_MASK | FTFA_FSTAT_FPVIOL_MASK | FTFA_FSTAT_ACCERR_MASK | FTFA_FSTAT_CCIF_MASK), FTFA_FSTAT_RDCOLERR(value)))
5792 #define FTFA_BWR_FSTAT_RDCOLERR(base, value) (BME_BFI8(&FTFA_FSTAT_REG(base), ((uint8_t)(value) << FTFA_FSTAT_RDCOLERR_SHIFT), FTFA_FSTAT_RDCOLERR_SHIFT, FTFA_FSTAT_RDCOLERR_WIDTH))
5793 /*@}*/
5794 
5795 /*!
5796  * @name Register FTFA_FSTAT, field CCIF[7] (W1C)
5797  *
5798  * Indicates that a flash command has completed. The CCIF flag is cleared by
5799  * writing a 1 to CCIF to launch a command, and CCIF stays low until command
5800  * completion or command violation. CCIF is reset to 0 but is set to 1 by the memory
5801  * controller at the end of the reset initialization sequence. Depending on how
5802  * quickly the read occurs after reset release, the user may or may not see the 0
5803  * hardware reset value.
5804  *
5805  * Values:
5806  * - 0b0 - Flash command in progress
5807  * - 0b1 - Flash command has completed
5808  */
5809 /*@{*/
5810 /*! @brief Read current value of the FTFA_FSTAT_CCIF field. */
5811 #define FTFA_RD_FSTAT_CCIF(base) ((FTFA_FSTAT_REG(base) & FTFA_FSTAT_CCIF_MASK) >> FTFA_FSTAT_CCIF_SHIFT)
5812 #define FTFA_BRD_FSTAT_CCIF(base) (BME_UBFX8(&FTFA_FSTAT_REG(base), FTFA_FSTAT_CCIF_SHIFT, FTFA_FSTAT_CCIF_WIDTH))
5813 
5814 /*! @brief Set the CCIF field to a new value. */
5815 #define FTFA_WR_FSTAT_CCIF(base, value) (FTFA_RMW_FSTAT(base, (FTFA_FSTAT_CCIF_MASK | FTFA_FSTAT_FPVIOL_MASK | FTFA_FSTAT_ACCERR_MASK | FTFA_FSTAT_RDCOLERR_MASK), FTFA_FSTAT_CCIF(value)))
5816 #define FTFA_BWR_FSTAT_CCIF(base, value) (BME_BFI8(&FTFA_FSTAT_REG(base), ((uint8_t)(value) << FTFA_FSTAT_CCIF_SHIFT), FTFA_FSTAT_CCIF_SHIFT, FTFA_FSTAT_CCIF_WIDTH))
5817 /*@}*/
5818 
5819 /*******************************************************************************
5820  * FTFA_FCNFG - Flash Configuration Register
5821  ******************************************************************************/
5822 
5823 /*!
5824  * @brief FTFA_FCNFG - Flash Configuration Register (RW)
5825  *
5826  * Reset value: 0x00U
5827  *
5828  * This register provides information on the current functional state of the
5829  * flash memory module. The erase control bits (ERSAREQ and ERSSUSP) have write
5830  * restrictions. The unassigned bits read as noted and are not writable.
5831  */
5832 /*!
5833  * @name Constants and macros for entire FTFA_FCNFG register
5834  */
5835 /*@{*/
5836 #define FTFA_RD_FCNFG(base)      (FTFA_FCNFG_REG(base))
5837 #define FTFA_WR_FCNFG(base, value) (FTFA_FCNFG_REG(base) = (value))
5838 #define FTFA_RMW_FCNFG(base, mask, value) (FTFA_WR_FCNFG(base, (FTFA_RD_FCNFG(base) & ~(mask)) | (value)))
5839 #define FTFA_SET_FCNFG(base, value) (BME_OR8(&FTFA_FCNFG_REG(base), (uint8_t)(value)))
5840 #define FTFA_CLR_FCNFG(base, value) (BME_AND8(&FTFA_FCNFG_REG(base), (uint8_t)(~(value))))
5841 #define FTFA_TOG_FCNFG(base, value) (BME_XOR8(&FTFA_FCNFG_REG(base), (uint8_t)(value)))
5842 /*@}*/
5843 
5844 /*
5845  * Constants & macros for individual FTFA_FCNFG bitfields
5846  */
5847 
5848 /*!
5849  * @name Register FTFA_FCNFG, field ERSSUSP[4] (RW)
5850  *
5851  * Allows the user to suspend (interrupt) the Erase Flash Sector command while
5852  * it is executing.
5853  *
5854  * Values:
5855  * - 0b0 - No suspend requested
5856  * - 0b1 - Suspend the current Erase Flash Sector command execution.
5857  */
5858 /*@{*/
5859 /*! @brief Read current value of the FTFA_FCNFG_ERSSUSP field. */
5860 #define FTFA_RD_FCNFG_ERSSUSP(base) ((FTFA_FCNFG_REG(base) & FTFA_FCNFG_ERSSUSP_MASK) >> FTFA_FCNFG_ERSSUSP_SHIFT)
5861 #define FTFA_BRD_FCNFG_ERSSUSP(base) (BME_UBFX8(&FTFA_FCNFG_REG(base), FTFA_FCNFG_ERSSUSP_SHIFT, FTFA_FCNFG_ERSSUSP_WIDTH))
5862 
5863 /*! @brief Set the ERSSUSP field to a new value. */
5864 #define FTFA_WR_FCNFG_ERSSUSP(base, value) (FTFA_RMW_FCNFG(base, FTFA_FCNFG_ERSSUSP_MASK, FTFA_FCNFG_ERSSUSP(value)))
5865 #define FTFA_BWR_FCNFG_ERSSUSP(base, value) (BME_BFI8(&FTFA_FCNFG_REG(base), ((uint8_t)(value) << FTFA_FCNFG_ERSSUSP_SHIFT), FTFA_FCNFG_ERSSUSP_SHIFT, FTFA_FCNFG_ERSSUSP_WIDTH))
5866 /*@}*/
5867 
5868 /*!
5869  * @name Register FTFA_FCNFG, field ERSAREQ[5] (RO)
5870  *
5871  * Issues a request to the memory controller to execute the Erase All Blocks
5872  * command and release security. ERSAREQ is not directly writable but is under
5873  * indirect user control. Refer to the device's Chip Configuration details on how to
5874  * request this command. ERSAREQ sets when and CCIF is set (no command is
5875  * currently being executed). ERSAREQ is cleared by the flash memory module when the
5876  * operation completes.
5877  *
5878  * Values:
5879  * - 0b0 - No request or request complete
5880  * - 0b1 - Request to: run the Erase All Blocks command, verify the erased
5881  *     state, program the security byte in the Flash Configuration Field to the
5882  *     unsecure state, and release MCU security by setting the FSEC[SEC] field to the
5883  *     unsecure state.
5884  */
5885 /*@{*/
5886 /*! @brief Read current value of the FTFA_FCNFG_ERSAREQ field. */
5887 #define FTFA_RD_FCNFG_ERSAREQ(base) ((FTFA_FCNFG_REG(base) & FTFA_FCNFG_ERSAREQ_MASK) >> FTFA_FCNFG_ERSAREQ_SHIFT)
5888 #define FTFA_BRD_FCNFG_ERSAREQ(base) (BME_UBFX8(&FTFA_FCNFG_REG(base), FTFA_FCNFG_ERSAREQ_SHIFT, FTFA_FCNFG_ERSAREQ_WIDTH))
5889 /*@}*/
5890 
5891 /*!
5892  * @name Register FTFA_FCNFG, field RDCOLLIE[6] (RW)
5893  *
5894  * Controls interrupt generation when a flash memory read collision error occurs.
5895  *
5896  * Values:
5897  * - 0b0 - Read collision error interrupt disabled
5898  * - 0b1 - Read collision error interrupt enabled. An interrupt request is
5899  *     generated whenever a flash memory read collision error is detected (see the
5900  *     description of FSTAT[RDCOLERR]).
5901  */
5902 /*@{*/
5903 /*! @brief Read current value of the FTFA_FCNFG_RDCOLLIE field. */
5904 #define FTFA_RD_FCNFG_RDCOLLIE(base) ((FTFA_FCNFG_REG(base) & FTFA_FCNFG_RDCOLLIE_MASK) >> FTFA_FCNFG_RDCOLLIE_SHIFT)
5905 #define FTFA_BRD_FCNFG_RDCOLLIE(base) (BME_UBFX8(&FTFA_FCNFG_REG(base), FTFA_FCNFG_RDCOLLIE_SHIFT, FTFA_FCNFG_RDCOLLIE_WIDTH))
5906 
5907 /*! @brief Set the RDCOLLIE field to a new value. */
5908 #define FTFA_WR_FCNFG_RDCOLLIE(base, value) (FTFA_RMW_FCNFG(base, FTFA_FCNFG_RDCOLLIE_MASK, FTFA_FCNFG_RDCOLLIE(value)))
5909 #define FTFA_BWR_FCNFG_RDCOLLIE(base, value) (BME_BFI8(&FTFA_FCNFG_REG(base), ((uint8_t)(value) << FTFA_FCNFG_RDCOLLIE_SHIFT), FTFA_FCNFG_RDCOLLIE_SHIFT, FTFA_FCNFG_RDCOLLIE_WIDTH))
5910 /*@}*/
5911 
5912 /*!
5913  * @name Register FTFA_FCNFG, field CCIE[7] (RW)
5914  *
5915  * Controls interrupt generation when a flash command completes.
5916  *
5917  * Values:
5918  * - 0b0 - Command complete interrupt disabled
5919  * - 0b1 - Command complete interrupt enabled. An interrupt request is generated
5920  *     whenever the FSTAT[CCIF] flag is set.
5921  */
5922 /*@{*/
5923 /*! @brief Read current value of the FTFA_FCNFG_CCIE field. */
5924 #define FTFA_RD_FCNFG_CCIE(base) ((FTFA_FCNFG_REG(base) & FTFA_FCNFG_CCIE_MASK) >> FTFA_FCNFG_CCIE_SHIFT)
5925 #define FTFA_BRD_FCNFG_CCIE(base) (BME_UBFX8(&FTFA_FCNFG_REG(base), FTFA_FCNFG_CCIE_SHIFT, FTFA_FCNFG_CCIE_WIDTH))
5926 
5927 /*! @brief Set the CCIE field to a new value. */
5928 #define FTFA_WR_FCNFG_CCIE(base, value) (FTFA_RMW_FCNFG(base, FTFA_FCNFG_CCIE_MASK, FTFA_FCNFG_CCIE(value)))
5929 #define FTFA_BWR_FCNFG_CCIE(base, value) (BME_BFI8(&FTFA_FCNFG_REG(base), ((uint8_t)(value) << FTFA_FCNFG_CCIE_SHIFT), FTFA_FCNFG_CCIE_SHIFT, FTFA_FCNFG_CCIE_WIDTH))
5930 /*@}*/
5931 
5932 /*******************************************************************************
5933  * FTFA_FSEC - Flash Security Register
5934  ******************************************************************************/
5935 
5936 /*!
5937  * @brief FTFA_FSEC - Flash Security Register (RO)
5938  *
5939  * Reset value: 0x00U
5940  *
5941  * This read-only register holds all bits associated with the security of the
5942  * MCU and flash memory module. During the reset sequence, the register is loaded
5943  * with the contents of the flash security byte in the Flash Configuration Field
5944  * located in program flash memory. The flash basis for the values is signified by
5945  * X in the reset value.
5946  */
5947 /*!
5948  * @name Constants and macros for entire FTFA_FSEC register
5949  */
5950 /*@{*/
5951 #define FTFA_RD_FSEC(base)       (FTFA_FSEC_REG(base))
5952 /*@}*/
5953 
5954 /*
5955  * Constants & macros for individual FTFA_FSEC bitfields
5956  */
5957 
5958 /*!
5959  * @name Register FTFA_FSEC, field SEC[1:0] (RO)
5960  *
5961  * Defines the security state of the MCU. In the secure state, the MCU limits
5962  * access to flash memory module resources. The limitations are defined per device
5963  * and are detailed in the Chip Configuration details. If the flash memory module
5964  * is unsecured using backdoor key access, SEC is forced to 10b.
5965  *
5966  * Values:
5967  * - 0b00 - MCU security status is secure.
5968  * - 0b01 - MCU security status is secure.
5969  * - 0b10 - MCU security status is unsecure. (The standard shipping condition of
5970  *     the flash memory module is unsecure.)
5971  * - 0b11 - MCU security status is secure.
5972  */
5973 /*@{*/
5974 /*! @brief Read current value of the FTFA_FSEC_SEC field. */
5975 #define FTFA_RD_FSEC_SEC(base) ((FTFA_FSEC_REG(base) & FTFA_FSEC_SEC_MASK) >> FTFA_FSEC_SEC_SHIFT)
5976 #define FTFA_BRD_FSEC_SEC(base) (BME_UBFX8(&FTFA_FSEC_REG(base), FTFA_FSEC_SEC_SHIFT, FTFA_FSEC_SEC_WIDTH))
5977 /*@}*/
5978 
5979 /*!
5980  * @name Register FTFA_FSEC, field FSLACC[3:2] (RO)
5981  *
5982  * Enables or disables access to the flash memory contents during returned part
5983  * failure analysis at Freescale. When SEC is secure and FSLACC is denied, access
5984  * to the program flash contents is denied and any failure analysis performed by
5985  * Freescale factory test must begin with a full erase to unsecure the part.
5986  * When access is granted (SEC is unsecure, or SEC is secure and FSLACC is granted),
5987  * Freescale factory testing has visibility of the current flash contents. The
5988  * state of the FSLACC bits is only relevant when SEC is set to secure. When SEC
5989  * is set to unsecure, the FSLACC setting does not matter.
5990  *
5991  * Values:
5992  * - 0b00 - Freescale factory access granted
5993  * - 0b01 - Freescale factory access denied
5994  * - 0b10 - Freescale factory access denied
5995  * - 0b11 - Freescale factory access granted
5996  */
5997 /*@{*/
5998 /*! @brief Read current value of the FTFA_FSEC_FSLACC field. */
5999 #define FTFA_RD_FSEC_FSLACC(base) ((FTFA_FSEC_REG(base) & FTFA_FSEC_FSLACC_MASK) >> FTFA_FSEC_FSLACC_SHIFT)
6000 #define FTFA_BRD_FSEC_FSLACC(base) (BME_UBFX8(&FTFA_FSEC_REG(base), FTFA_FSEC_FSLACC_SHIFT, FTFA_FSEC_FSLACC_WIDTH))
6001 /*@}*/
6002 
6003 /*!
6004  * @name Register FTFA_FSEC, field MEEN[5:4] (RO)
6005  *
6006  * Enables and disables mass erase capability of the flash memory module. When
6007  * SEC is set to unsecure, the MEEN setting does not matter.
6008  *
6009  * Values:
6010  * - 0b00 - Mass erase is enabled
6011  * - 0b01 - Mass erase is enabled
6012  * - 0b10 - Mass erase is disabled
6013  * - 0b11 - Mass erase is enabled
6014  */
6015 /*@{*/
6016 /*! @brief Read current value of the FTFA_FSEC_MEEN field. */
6017 #define FTFA_RD_FSEC_MEEN(base) ((FTFA_FSEC_REG(base) & FTFA_FSEC_MEEN_MASK) >> FTFA_FSEC_MEEN_SHIFT)
6018 #define FTFA_BRD_FSEC_MEEN(base) (BME_UBFX8(&FTFA_FSEC_REG(base), FTFA_FSEC_MEEN_SHIFT, FTFA_FSEC_MEEN_WIDTH))
6019 /*@}*/
6020 
6021 /*!
6022  * @name Register FTFA_FSEC, field KEYEN[7:6] (RO)
6023  *
6024  * Enables or disables backdoor key access to the flash memory module.
6025  *
6026  * Values:
6027  * - 0b00 - Backdoor key access disabled
6028  * - 0b01 - Backdoor key access disabled (preferred KEYEN state to disable
6029  *     backdoor key access)
6030  * - 0b10 - Backdoor key access enabled
6031  * - 0b11 - Backdoor key access disabled
6032  */
6033 /*@{*/
6034 /*! @brief Read current value of the FTFA_FSEC_KEYEN field. */
6035 #define FTFA_RD_FSEC_KEYEN(base) ((FTFA_FSEC_REG(base) & FTFA_FSEC_KEYEN_MASK) >> FTFA_FSEC_KEYEN_SHIFT)
6036 #define FTFA_BRD_FSEC_KEYEN(base) (BME_UBFX8(&FTFA_FSEC_REG(base), FTFA_FSEC_KEYEN_SHIFT, FTFA_FSEC_KEYEN_WIDTH))
6037 /*@}*/
6038 
6039 /*******************************************************************************
6040  * FTFA_FOPT - Flash Option Register
6041  ******************************************************************************/
6042 
6043 /*!
6044  * @brief FTFA_FOPT - Flash Option Register (RO)
6045  *
6046  * Reset value: 0x00U
6047  *
6048  * The flash option register allows the MCU to customize its operations by
6049  * examining the state of these read-only bits, which are loaded from NVM at reset.
6050  * The function of the bits is defined in the device's Chip Configuration details.
6051  * All bits in the register are read-only . During the reset sequence, the
6052  * register is loaded from the flash nonvolatile option byte in the Flash Configuration
6053  * Field located in program flash memory. The flash basis for the values is
6054  * signified by X in the reset value.
6055  */
6056 /*!
6057  * @name Constants and macros for entire FTFA_FOPT register
6058  */
6059 /*@{*/
6060 #define FTFA_RD_FOPT(base)       (FTFA_FOPT_REG(base))
6061 /*@}*/
6062 
6063 /*******************************************************************************
6064  * FTFA_FCCOB3 - Flash Common Command Object Registers
6065  ******************************************************************************/
6066 
6067 /*!
6068  * @brief FTFA_FCCOB3 - Flash Common Command Object Registers (RW)
6069  *
6070  * Reset value: 0x00U
6071  *
6072  * The FCCOB register group provides 12 bytes for command codes and parameters.
6073  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
6074  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
6075  */
6076 /*!
6077  * @name Constants and macros for entire FTFA_FCCOB3 register
6078  */
6079 /*@{*/
6080 #define FTFA_RD_FCCOB3(base)     (FTFA_FCCOB3_REG(base))
6081 #define FTFA_WR_FCCOB3(base, value) (FTFA_FCCOB3_REG(base) = (value))
6082 #define FTFA_RMW_FCCOB3(base, mask, value) (FTFA_WR_FCCOB3(base, (FTFA_RD_FCCOB3(base) & ~(mask)) | (value)))
6083 #define FTFA_SET_FCCOB3(base, value) (BME_OR8(&FTFA_FCCOB3_REG(base), (uint8_t)(value)))
6084 #define FTFA_CLR_FCCOB3(base, value) (BME_AND8(&FTFA_FCCOB3_REG(base), (uint8_t)(~(value))))
6085 #define FTFA_TOG_FCCOB3(base, value) (BME_XOR8(&FTFA_FCCOB3_REG(base), (uint8_t)(value)))
6086 /*@}*/
6087 
6088 /*******************************************************************************
6089  * FTFA_FCCOB2 - Flash Common Command Object Registers
6090  ******************************************************************************/
6091 
6092 /*!
6093  * @brief FTFA_FCCOB2 - Flash Common Command Object Registers (RW)
6094  *
6095  * Reset value: 0x00U
6096  *
6097  * The FCCOB register group provides 12 bytes for command codes and parameters.
6098  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
6099  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
6100  */
6101 /*!
6102  * @name Constants and macros for entire FTFA_FCCOB2 register
6103  */
6104 /*@{*/
6105 #define FTFA_RD_FCCOB2(base)     (FTFA_FCCOB2_REG(base))
6106 #define FTFA_WR_FCCOB2(base, value) (FTFA_FCCOB2_REG(base) = (value))
6107 #define FTFA_RMW_FCCOB2(base, mask, value) (FTFA_WR_FCCOB2(base, (FTFA_RD_FCCOB2(base) & ~(mask)) | (value)))
6108 #define FTFA_SET_FCCOB2(base, value) (BME_OR8(&FTFA_FCCOB2_REG(base), (uint8_t)(value)))
6109 #define FTFA_CLR_FCCOB2(base, value) (BME_AND8(&FTFA_FCCOB2_REG(base), (uint8_t)(~(value))))
6110 #define FTFA_TOG_FCCOB2(base, value) (BME_XOR8(&FTFA_FCCOB2_REG(base), (uint8_t)(value)))
6111 /*@}*/
6112 
6113 /*******************************************************************************
6114  * FTFA_FCCOB1 - Flash Common Command Object Registers
6115  ******************************************************************************/
6116 
6117 /*!
6118  * @brief FTFA_FCCOB1 - Flash Common Command Object Registers (RW)
6119  *
6120  * Reset value: 0x00U
6121  *
6122  * The FCCOB register group provides 12 bytes for command codes and parameters.
6123  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
6124  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
6125  */
6126 /*!
6127  * @name Constants and macros for entire FTFA_FCCOB1 register
6128  */
6129 /*@{*/
6130 #define FTFA_RD_FCCOB1(base)     (FTFA_FCCOB1_REG(base))
6131 #define FTFA_WR_FCCOB1(base, value) (FTFA_FCCOB1_REG(base) = (value))
6132 #define FTFA_RMW_FCCOB1(base, mask, value) (FTFA_WR_FCCOB1(base, (FTFA_RD_FCCOB1(base) & ~(mask)) | (value)))
6133 #define FTFA_SET_FCCOB1(base, value) (BME_OR8(&FTFA_FCCOB1_REG(base), (uint8_t)(value)))
6134 #define FTFA_CLR_FCCOB1(base, value) (BME_AND8(&FTFA_FCCOB1_REG(base), (uint8_t)(~(value))))
6135 #define FTFA_TOG_FCCOB1(base, value) (BME_XOR8(&FTFA_FCCOB1_REG(base), (uint8_t)(value)))
6136 /*@}*/
6137 
6138 /*******************************************************************************
6139  * FTFA_FCCOB0 - Flash Common Command Object Registers
6140  ******************************************************************************/
6141 
6142 /*!
6143  * @brief FTFA_FCCOB0 - Flash Common Command Object Registers (RW)
6144  *
6145  * Reset value: 0x00U
6146  *
6147  * The FCCOB register group provides 12 bytes for command codes and parameters.
6148  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
6149  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
6150  */
6151 /*!
6152  * @name Constants and macros for entire FTFA_FCCOB0 register
6153  */
6154 /*@{*/
6155 #define FTFA_RD_FCCOB0(base)     (FTFA_FCCOB0_REG(base))
6156 #define FTFA_WR_FCCOB0(base, value) (FTFA_FCCOB0_REG(base) = (value))
6157 #define FTFA_RMW_FCCOB0(base, mask, value) (FTFA_WR_FCCOB0(base, (FTFA_RD_FCCOB0(base) & ~(mask)) | (value)))
6158 #define FTFA_SET_FCCOB0(base, value) (BME_OR8(&FTFA_FCCOB0_REG(base), (uint8_t)(value)))
6159 #define FTFA_CLR_FCCOB0(base, value) (BME_AND8(&FTFA_FCCOB0_REG(base), (uint8_t)(~(value))))
6160 #define FTFA_TOG_FCCOB0(base, value) (BME_XOR8(&FTFA_FCCOB0_REG(base), (uint8_t)(value)))
6161 /*@}*/
6162 
6163 /*******************************************************************************
6164  * FTFA_FCCOB7 - Flash Common Command Object Registers
6165  ******************************************************************************/
6166 
6167 /*!
6168  * @brief FTFA_FCCOB7 - Flash Common Command Object Registers (RW)
6169  *
6170  * Reset value: 0x00U
6171  *
6172  * The FCCOB register group provides 12 bytes for command codes and parameters.
6173  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
6174  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
6175  */
6176 /*!
6177  * @name Constants and macros for entire FTFA_FCCOB7 register
6178  */
6179 /*@{*/
6180 #define FTFA_RD_FCCOB7(base)     (FTFA_FCCOB7_REG(base))
6181 #define FTFA_WR_FCCOB7(base, value) (FTFA_FCCOB7_REG(base) = (value))
6182 #define FTFA_RMW_FCCOB7(base, mask, value) (FTFA_WR_FCCOB7(base, (FTFA_RD_FCCOB7(base) & ~(mask)) | (value)))
6183 #define FTFA_SET_FCCOB7(base, value) (BME_OR8(&FTFA_FCCOB7_REG(base), (uint8_t)(value)))
6184 #define FTFA_CLR_FCCOB7(base, value) (BME_AND8(&FTFA_FCCOB7_REG(base), (uint8_t)(~(value))))
6185 #define FTFA_TOG_FCCOB7(base, value) (BME_XOR8(&FTFA_FCCOB7_REG(base), (uint8_t)(value)))
6186 /*@}*/
6187 
6188 /*******************************************************************************
6189  * FTFA_FCCOB6 - Flash Common Command Object Registers
6190  ******************************************************************************/
6191 
6192 /*!
6193  * @brief FTFA_FCCOB6 - Flash Common Command Object Registers (RW)
6194  *
6195  * Reset value: 0x00U
6196  *
6197  * The FCCOB register group provides 12 bytes for command codes and parameters.
6198  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
6199  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
6200  */
6201 /*!
6202  * @name Constants and macros for entire FTFA_FCCOB6 register
6203  */
6204 /*@{*/
6205 #define FTFA_RD_FCCOB6(base)     (FTFA_FCCOB6_REG(base))
6206 #define FTFA_WR_FCCOB6(base, value) (FTFA_FCCOB6_REG(base) = (value))
6207 #define FTFA_RMW_FCCOB6(base, mask, value) (FTFA_WR_FCCOB6(base, (FTFA_RD_FCCOB6(base) & ~(mask)) | (value)))
6208 #define FTFA_SET_FCCOB6(base, value) (BME_OR8(&FTFA_FCCOB6_REG(base), (uint8_t)(value)))
6209 #define FTFA_CLR_FCCOB6(base, value) (BME_AND8(&FTFA_FCCOB6_REG(base), (uint8_t)(~(value))))
6210 #define FTFA_TOG_FCCOB6(base, value) (BME_XOR8(&FTFA_FCCOB6_REG(base), (uint8_t)(value)))
6211 /*@}*/
6212 
6213 /*******************************************************************************
6214  * FTFA_FCCOB5 - Flash Common Command Object Registers
6215  ******************************************************************************/
6216 
6217 /*!
6218  * @brief FTFA_FCCOB5 - Flash Common Command Object Registers (RW)
6219  *
6220  * Reset value: 0x00U
6221  *
6222  * The FCCOB register group provides 12 bytes for command codes and parameters.
6223  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
6224  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
6225  */
6226 /*!
6227  * @name Constants and macros for entire FTFA_FCCOB5 register
6228  */
6229 /*@{*/
6230 #define FTFA_RD_FCCOB5(base)     (FTFA_FCCOB5_REG(base))
6231 #define FTFA_WR_FCCOB5(base, value) (FTFA_FCCOB5_REG(base) = (value))
6232 #define FTFA_RMW_FCCOB5(base, mask, value) (FTFA_WR_FCCOB5(base, (FTFA_RD_FCCOB5(base) & ~(mask)) | (value)))
6233 #define FTFA_SET_FCCOB5(base, value) (BME_OR8(&FTFA_FCCOB5_REG(base), (uint8_t)(value)))
6234 #define FTFA_CLR_FCCOB5(base, value) (BME_AND8(&FTFA_FCCOB5_REG(base), (uint8_t)(~(value))))
6235 #define FTFA_TOG_FCCOB5(base, value) (BME_XOR8(&FTFA_FCCOB5_REG(base), (uint8_t)(value)))
6236 /*@}*/
6237 
6238 /*******************************************************************************
6239  * FTFA_FCCOB4 - Flash Common Command Object Registers
6240  ******************************************************************************/
6241 
6242 /*!
6243  * @brief FTFA_FCCOB4 - Flash Common Command Object Registers (RW)
6244  *
6245  * Reset value: 0x00U
6246  *
6247  * The FCCOB register group provides 12 bytes for command codes and parameters.
6248  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
6249  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
6250  */
6251 /*!
6252  * @name Constants and macros for entire FTFA_FCCOB4 register
6253  */
6254 /*@{*/
6255 #define FTFA_RD_FCCOB4(base)     (FTFA_FCCOB4_REG(base))
6256 #define FTFA_WR_FCCOB4(base, value) (FTFA_FCCOB4_REG(base) = (value))
6257 #define FTFA_RMW_FCCOB4(base, mask, value) (FTFA_WR_FCCOB4(base, (FTFA_RD_FCCOB4(base) & ~(mask)) | (value)))
6258 #define FTFA_SET_FCCOB4(base, value) (BME_OR8(&FTFA_FCCOB4_REG(base), (uint8_t)(value)))
6259 #define FTFA_CLR_FCCOB4(base, value) (BME_AND8(&FTFA_FCCOB4_REG(base), (uint8_t)(~(value))))
6260 #define FTFA_TOG_FCCOB4(base, value) (BME_XOR8(&FTFA_FCCOB4_REG(base), (uint8_t)(value)))
6261 /*@}*/
6262 
6263 /*******************************************************************************
6264  * FTFA_FCCOBB - Flash Common Command Object Registers
6265  ******************************************************************************/
6266 
6267 /*!
6268  * @brief FTFA_FCCOBB - Flash Common Command Object Registers (RW)
6269  *
6270  * Reset value: 0x00U
6271  *
6272  * The FCCOB register group provides 12 bytes for command codes and parameters.
6273  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
6274  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
6275  */
6276 /*!
6277  * @name Constants and macros for entire FTFA_FCCOBB register
6278  */
6279 /*@{*/
6280 #define FTFA_RD_FCCOBB(base)     (FTFA_FCCOBB_REG(base))
6281 #define FTFA_WR_FCCOBB(base, value) (FTFA_FCCOBB_REG(base) = (value))
6282 #define FTFA_RMW_FCCOBB(base, mask, value) (FTFA_WR_FCCOBB(base, (FTFA_RD_FCCOBB(base) & ~(mask)) | (value)))
6283 #define FTFA_SET_FCCOBB(base, value) (BME_OR8(&FTFA_FCCOBB_REG(base), (uint8_t)(value)))
6284 #define FTFA_CLR_FCCOBB(base, value) (BME_AND8(&FTFA_FCCOBB_REG(base), (uint8_t)(~(value))))
6285 #define FTFA_TOG_FCCOBB(base, value) (BME_XOR8(&FTFA_FCCOBB_REG(base), (uint8_t)(value)))
6286 /*@}*/
6287 
6288 /*******************************************************************************
6289  * FTFA_FCCOBA - Flash Common Command Object Registers
6290  ******************************************************************************/
6291 
6292 /*!
6293  * @brief FTFA_FCCOBA - Flash Common Command Object Registers (RW)
6294  *
6295  * Reset value: 0x00U
6296  *
6297  * The FCCOB register group provides 12 bytes for command codes and parameters.
6298  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
6299  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
6300  */
6301 /*!
6302  * @name Constants and macros for entire FTFA_FCCOBA register
6303  */
6304 /*@{*/
6305 #define FTFA_RD_FCCOBA(base)     (FTFA_FCCOBA_REG(base))
6306 #define FTFA_WR_FCCOBA(base, value) (FTFA_FCCOBA_REG(base) = (value))
6307 #define FTFA_RMW_FCCOBA(base, mask, value) (FTFA_WR_FCCOBA(base, (FTFA_RD_FCCOBA(base) & ~(mask)) | (value)))
6308 #define FTFA_SET_FCCOBA(base, value) (BME_OR8(&FTFA_FCCOBA_REG(base), (uint8_t)(value)))
6309 #define FTFA_CLR_FCCOBA(base, value) (BME_AND8(&FTFA_FCCOBA_REG(base), (uint8_t)(~(value))))
6310 #define FTFA_TOG_FCCOBA(base, value) (BME_XOR8(&FTFA_FCCOBA_REG(base), (uint8_t)(value)))
6311 /*@}*/
6312 
6313 /*******************************************************************************
6314  * FTFA_FCCOB9 - Flash Common Command Object Registers
6315  ******************************************************************************/
6316 
6317 /*!
6318  * @brief FTFA_FCCOB9 - Flash Common Command Object Registers (RW)
6319  *
6320  * Reset value: 0x00U
6321  *
6322  * The FCCOB register group provides 12 bytes for command codes and parameters.
6323  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
6324  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
6325  */
6326 /*!
6327  * @name Constants and macros for entire FTFA_FCCOB9 register
6328  */
6329 /*@{*/
6330 #define FTFA_RD_FCCOB9(base)     (FTFA_FCCOB9_REG(base))
6331 #define FTFA_WR_FCCOB9(base, value) (FTFA_FCCOB9_REG(base) = (value))
6332 #define FTFA_RMW_FCCOB9(base, mask, value) (FTFA_WR_FCCOB9(base, (FTFA_RD_FCCOB9(base) & ~(mask)) | (value)))
6333 #define FTFA_SET_FCCOB9(base, value) (BME_OR8(&FTFA_FCCOB9_REG(base), (uint8_t)(value)))
6334 #define FTFA_CLR_FCCOB9(base, value) (BME_AND8(&FTFA_FCCOB9_REG(base), (uint8_t)(~(value))))
6335 #define FTFA_TOG_FCCOB9(base, value) (BME_XOR8(&FTFA_FCCOB9_REG(base), (uint8_t)(value)))
6336 /*@}*/
6337 
6338 /*******************************************************************************
6339  * FTFA_FCCOB8 - Flash Common Command Object Registers
6340  ******************************************************************************/
6341 
6342 /*!
6343  * @brief FTFA_FCCOB8 - Flash Common Command Object Registers (RW)
6344  *
6345  * Reset value: 0x00U
6346  *
6347  * The FCCOB register group provides 12 bytes for command codes and parameters.
6348  * The individual bytes within the set append a 0-B hex identifier to the FCCOB
6349  * register name: FCCOB0, FCCOB1, ..., FCCOBB.
6350  */
6351 /*!
6352  * @name Constants and macros for entire FTFA_FCCOB8 register
6353  */
6354 /*@{*/
6355 #define FTFA_RD_FCCOB8(base)     (FTFA_FCCOB8_REG(base))
6356 #define FTFA_WR_FCCOB8(base, value) (FTFA_FCCOB8_REG(base) = (value))
6357 #define FTFA_RMW_FCCOB8(base, mask, value) (FTFA_WR_FCCOB8(base, (FTFA_RD_FCCOB8(base) & ~(mask)) | (value)))
6358 #define FTFA_SET_FCCOB8(base, value) (BME_OR8(&FTFA_FCCOB8_REG(base), (uint8_t)(value)))
6359 #define FTFA_CLR_FCCOB8(base, value) (BME_AND8(&FTFA_FCCOB8_REG(base), (uint8_t)(~(value))))
6360 #define FTFA_TOG_FCCOB8(base, value) (BME_XOR8(&FTFA_FCCOB8_REG(base), (uint8_t)(value)))
6361 /*@}*/
6362 
6363 /*******************************************************************************
6364  * FTFA_FPROT3 - Program Flash Protection Registers
6365  ******************************************************************************/
6366 
6367 /*!
6368  * @brief FTFA_FPROT3 - Program Flash Protection Registers (RW)
6369  *
6370  * Reset value: 0x00U
6371  *
6372  * The FPROT registers define which program flash regions are protected from
6373  * program and erase operations. Protected flash regions cannot have their content
6374  * changed; that is, these regions cannot be programmed and cannot be erased by
6375  * any flash command. Unprotected regions can be changed by program and erase
6376  * operations. The four FPROT registers allow up to 32 protectable regions. Each bit
6377  * protects a 1/32 region of the program flash memory except for memory
6378  * configurations with less than 32 KB of program flash where each assigned bit protects 1
6379  * KB . For configurations with 24 KB of program flash memory or less, FPROT0 is
6380  * not used. For configurations with 16 KB of program flash memory or less,
6381  * FPROT1 is not used. For configurations with 8 KB of program flash memory, FPROT2 is
6382  * not used. For configurations with 24 KB of program flash memory or less,
6383  * FPROT0 is not used. For configurations with 16 KB of program flash memory or less,
6384  * FPROT1 is not used. For configurations with 8 KB of program flash memory,
6385  * FPROT2 is not used. The bitfields are defined in each register as follows:
6386  * Program flash protection register Program flash protection bits FPROT0 PROT[31:24]
6387  * FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset
6388  * sequence, the FPROT registers are loaded with the contents of the program flash
6389  * protection bytes in the Flash Configuration Field as indicated in the following
6390  * table. Program flash protection register Flash Configuration Field offset address
6391  * FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the program
6392  * flash protection that is loaded during the reset sequence, unprotect the
6393  * sector of program flash memory that contains the Flash Configuration Field. Then,
6394  * reprogram the program flash protection byte.
6395  */
6396 /*!
6397  * @name Constants and macros for entire FTFA_FPROT3 register
6398  */
6399 /*@{*/
6400 #define FTFA_RD_FPROT3(base)     (FTFA_FPROT3_REG(base))
6401 #define FTFA_WR_FPROT3(base, value) (FTFA_FPROT3_REG(base) = (value))
6402 #define FTFA_RMW_FPROT3(base, mask, value) (FTFA_WR_FPROT3(base, (FTFA_RD_FPROT3(base) & ~(mask)) | (value)))
6403 #define FTFA_SET_FPROT3(base, value) (BME_OR8(&FTFA_FPROT3_REG(base), (uint8_t)(value)))
6404 #define FTFA_CLR_FPROT3(base, value) (BME_AND8(&FTFA_FPROT3_REG(base), (uint8_t)(~(value))))
6405 #define FTFA_TOG_FPROT3(base, value) (BME_XOR8(&FTFA_FPROT3_REG(base), (uint8_t)(value)))
6406 /*@}*/
6407 
6408 /*******************************************************************************
6409  * FTFA_FPROT2 - Program Flash Protection Registers
6410  ******************************************************************************/
6411 
6412 /*!
6413  * @brief FTFA_FPROT2 - Program Flash Protection Registers (RW)
6414  *
6415  * Reset value: 0x00U
6416  *
6417  * The FPROT registers define which program flash regions are protected from
6418  * program and erase operations. Protected flash regions cannot have their content
6419  * changed; that is, these regions cannot be programmed and cannot be erased by
6420  * any flash command. Unprotected regions can be changed by program and erase
6421  * operations. The four FPROT registers allow up to 32 protectable regions. Each bit
6422  * protects a 1/32 region of the program flash memory except for memory
6423  * configurations with less than 32 KB of program flash where each assigned bit protects 1
6424  * KB . For configurations with 24 KB of program flash memory or less, FPROT0 is
6425  * not used. For configurations with 16 KB of program flash memory or less,
6426  * FPROT1 is not used. For configurations with 8 KB of program flash memory, FPROT2 is
6427  * not used. For configurations with 24 KB of program flash memory or less,
6428  * FPROT0 is not used. For configurations with 16 KB of program flash memory or less,
6429  * FPROT1 is not used. For configurations with 8 KB of program flash memory,
6430  * FPROT2 is not used. The bitfields are defined in each register as follows:
6431  * Program flash protection register Program flash protection bits FPROT0 PROT[31:24]
6432  * FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset
6433  * sequence, the FPROT registers are loaded with the contents of the program flash
6434  * protection bytes in the Flash Configuration Field as indicated in the following
6435  * table. Program flash protection register Flash Configuration Field offset address
6436  * FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the program
6437  * flash protection that is loaded during the reset sequence, unprotect the
6438  * sector of program flash memory that contains the Flash Configuration Field. Then,
6439  * reprogram the program flash protection byte.
6440  */
6441 /*!
6442  * @name Constants and macros for entire FTFA_FPROT2 register
6443  */
6444 /*@{*/
6445 #define FTFA_RD_FPROT2(base)     (FTFA_FPROT2_REG(base))
6446 #define FTFA_WR_FPROT2(base, value) (FTFA_FPROT2_REG(base) = (value))
6447 #define FTFA_RMW_FPROT2(base, mask, value) (FTFA_WR_FPROT2(base, (FTFA_RD_FPROT2(base) & ~(mask)) | (value)))
6448 #define FTFA_SET_FPROT2(base, value) (BME_OR8(&FTFA_FPROT2_REG(base), (uint8_t)(value)))
6449 #define FTFA_CLR_FPROT2(base, value) (BME_AND8(&FTFA_FPROT2_REG(base), (uint8_t)(~(value))))
6450 #define FTFA_TOG_FPROT2(base, value) (BME_XOR8(&FTFA_FPROT2_REG(base), (uint8_t)(value)))
6451 /*@}*/
6452 
6453 /*******************************************************************************
6454  * FTFA_FPROT1 - Program Flash Protection Registers
6455  ******************************************************************************/
6456 
6457 /*!
6458  * @brief FTFA_FPROT1 - Program Flash Protection Registers (RW)
6459  *
6460  * Reset value: 0x00U
6461  *
6462  * The FPROT registers define which program flash regions are protected from
6463  * program and erase operations. Protected flash regions cannot have their content
6464  * changed; that is, these regions cannot be programmed and cannot be erased by
6465  * any flash command. Unprotected regions can be changed by program and erase
6466  * operations. The four FPROT registers allow up to 32 protectable regions. Each bit
6467  * protects a 1/32 region of the program flash memory except for memory
6468  * configurations with less than 32 KB of program flash where each assigned bit protects 1
6469  * KB . For configurations with 24 KB of program flash memory or less, FPROT0 is
6470  * not used. For configurations with 16 KB of program flash memory or less,
6471  * FPROT1 is not used. For configurations with 8 KB of program flash memory, FPROT2 is
6472  * not used. For configurations with 24 KB of program flash memory or less,
6473  * FPROT0 is not used. For configurations with 16 KB of program flash memory or less,
6474  * FPROT1 is not used. For configurations with 8 KB of program flash memory,
6475  * FPROT2 is not used. The bitfields are defined in each register as follows:
6476  * Program flash protection register Program flash protection bits FPROT0 PROT[31:24]
6477  * FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset
6478  * sequence, the FPROT registers are loaded with the contents of the program flash
6479  * protection bytes in the Flash Configuration Field as indicated in the following
6480  * table. Program flash protection register Flash Configuration Field offset address
6481  * FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the program
6482  * flash protection that is loaded during the reset sequence, unprotect the
6483  * sector of program flash memory that contains the Flash Configuration Field. Then,
6484  * reprogram the program flash protection byte.
6485  */
6486 /*!
6487  * @name Constants and macros for entire FTFA_FPROT1 register
6488  */
6489 /*@{*/
6490 #define FTFA_RD_FPROT1(base)     (FTFA_FPROT1_REG(base))
6491 #define FTFA_WR_FPROT1(base, value) (FTFA_FPROT1_REG(base) = (value))
6492 #define FTFA_RMW_FPROT1(base, mask, value) (FTFA_WR_FPROT1(base, (FTFA_RD_FPROT1(base) & ~(mask)) | (value)))
6493 #define FTFA_SET_FPROT1(base, value) (BME_OR8(&FTFA_FPROT1_REG(base), (uint8_t)(value)))
6494 #define FTFA_CLR_FPROT1(base, value) (BME_AND8(&FTFA_FPROT1_REG(base), (uint8_t)(~(value))))
6495 #define FTFA_TOG_FPROT1(base, value) (BME_XOR8(&FTFA_FPROT1_REG(base), (uint8_t)(value)))
6496 /*@}*/
6497 
6498 /*******************************************************************************
6499  * FTFA_FPROT0 - Program Flash Protection Registers
6500  ******************************************************************************/
6501 
6502 /*!
6503  * @brief FTFA_FPROT0 - Program Flash Protection Registers (RW)
6504  *
6505  * Reset value: 0x00U
6506  *
6507  * The FPROT registers define which program flash regions are protected from
6508  * program and erase operations. Protected flash regions cannot have their content
6509  * changed; that is, these regions cannot be programmed and cannot be erased by
6510  * any flash command. Unprotected regions can be changed by program and erase
6511  * operations. The four FPROT registers allow up to 32 protectable regions. Each bit
6512  * protects a 1/32 region of the program flash memory except for memory
6513  * configurations with less than 32 KB of program flash where each assigned bit protects 1
6514  * KB . For configurations with 24 KB of program flash memory or less, FPROT0 is
6515  * not used. For configurations with 16 KB of program flash memory or less,
6516  * FPROT1 is not used. For configurations with 8 KB of program flash memory, FPROT2 is
6517  * not used. For configurations with 24 KB of program flash memory or less,
6518  * FPROT0 is not used. For configurations with 16 KB of program flash memory or less,
6519  * FPROT1 is not used. For configurations with 8 KB of program flash memory,
6520  * FPROT2 is not used. The bitfields are defined in each register as follows:
6521  * Program flash protection register Program flash protection bits FPROT0 PROT[31:24]
6522  * FPROT1 PROT[23:16] FPROT2 PROT[15:8] FPROT3 PROT[7:0] During the reset
6523  * sequence, the FPROT registers are loaded with the contents of the program flash
6524  * protection bytes in the Flash Configuration Field as indicated in the following
6525  * table. Program flash protection register Flash Configuration Field offset address
6526  * FPROT0 0x000B FPROT1 0x000A FPROT2 0x0009 FPROT3 0x0008 To change the program
6527  * flash protection that is loaded during the reset sequence, unprotect the
6528  * sector of program flash memory that contains the Flash Configuration Field. Then,
6529  * reprogram the program flash protection byte.
6530  */
6531 /*!
6532  * @name Constants and macros for entire FTFA_FPROT0 register
6533  */
6534 /*@{*/
6535 #define FTFA_RD_FPROT0(base)     (FTFA_FPROT0_REG(base))
6536 #define FTFA_WR_FPROT0(base, value) (FTFA_FPROT0_REG(base) = (value))
6537 #define FTFA_RMW_FPROT0(base, mask, value) (FTFA_WR_FPROT0(base, (FTFA_RD_FPROT0(base) & ~(mask)) | (value)))
6538 #define FTFA_SET_FPROT0(base, value) (BME_OR8(&FTFA_FPROT0_REG(base), (uint8_t)(value)))
6539 #define FTFA_CLR_FPROT0(base, value) (BME_AND8(&FTFA_FPROT0_REG(base), (uint8_t)(~(value))))
6540 #define FTFA_TOG_FPROT0(base, value) (BME_XOR8(&FTFA_FPROT0_REG(base), (uint8_t)(value)))
6541 /*@}*/
6542 
6543 /*******************************************************************************
6544  * FTFA_XACCH3 - Execute-only Access Registers
6545  ******************************************************************************/
6546 
6547 /*!
6548  * @brief FTFA_XACCH3 - Execute-only Access Registers (RO)
6549  *
6550  * Reset value: 0x00U
6551  *
6552  * The XACC registers define which program flash segments are restricted to data
6553  * read or execute only or both data and instruction fetches. The eight XACC
6554  * registers allow up to 64 restricted segments of equal memory size. Execute-only
6555  * access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1
6556  * XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16]
6557  * XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers
6558  * are loaded with the logical AND of Program Flash IFR addresses A and B as
6559  * indicated in the following table. Execute-only access register Program Flash IFR
6560  * address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2
6561  * 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD
6562  * XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only
6563  * access control fields that are loaded during the reset sequence.
6564  */
6565 /*!
6566  * @name Constants and macros for entire FTFA_XACCH3 register
6567  */
6568 /*@{*/
6569 #define FTFA_RD_XACCH3(base)     (FTFA_XACCH3_REG(base))
6570 /*@}*/
6571 
6572 /*******************************************************************************
6573  * FTFA_XACCH2 - Execute-only Access Registers
6574  ******************************************************************************/
6575 
6576 /*!
6577  * @brief FTFA_XACCH2 - Execute-only Access Registers (RO)
6578  *
6579  * Reset value: 0x00U
6580  *
6581  * The XACC registers define which program flash segments are restricted to data
6582  * read or execute only or both data and instruction fetches. The eight XACC
6583  * registers allow up to 64 restricted segments of equal memory size. Execute-only
6584  * access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1
6585  * XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16]
6586  * XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers
6587  * are loaded with the logical AND of Program Flash IFR addresses A and B as
6588  * indicated in the following table. Execute-only access register Program Flash IFR
6589  * address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2
6590  * 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD
6591  * XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only
6592  * access control fields that are loaded during the reset sequence.
6593  */
6594 /*!
6595  * @name Constants and macros for entire FTFA_XACCH2 register
6596  */
6597 /*@{*/
6598 #define FTFA_RD_XACCH2(base)     (FTFA_XACCH2_REG(base))
6599 /*@}*/
6600 
6601 /*******************************************************************************
6602  * FTFA_XACCH1 - Execute-only Access Registers
6603  ******************************************************************************/
6604 
6605 /*!
6606  * @brief FTFA_XACCH1 - Execute-only Access Registers (RO)
6607  *
6608  * Reset value: 0x00U
6609  *
6610  * The XACC registers define which program flash segments are restricted to data
6611  * read or execute only or both data and instruction fetches. The eight XACC
6612  * registers allow up to 64 restricted segments of equal memory size. Execute-only
6613  * access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1
6614  * XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16]
6615  * XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers
6616  * are loaded with the logical AND of Program Flash IFR addresses A and B as
6617  * indicated in the following table. Execute-only access register Program Flash IFR
6618  * address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2
6619  * 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD
6620  * XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only
6621  * access control fields that are loaded during the reset sequence.
6622  */
6623 /*!
6624  * @name Constants and macros for entire FTFA_XACCH1 register
6625  */
6626 /*@{*/
6627 #define FTFA_RD_XACCH1(base)     (FTFA_XACCH1_REG(base))
6628 /*@}*/
6629 
6630 /*******************************************************************************
6631  * FTFA_XACCH0 - Execute-only Access Registers
6632  ******************************************************************************/
6633 
6634 /*!
6635  * @brief FTFA_XACCH0 - Execute-only Access Registers (RO)
6636  *
6637  * Reset value: 0x00U
6638  *
6639  * The XACC registers define which program flash segments are restricted to data
6640  * read or execute only or both data and instruction fetches. The eight XACC
6641  * registers allow up to 64 restricted segments of equal memory size. Execute-only
6642  * access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1
6643  * XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16]
6644  * XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers
6645  * are loaded with the logical AND of Program Flash IFR addresses A and B as
6646  * indicated in the following table. Execute-only access register Program Flash IFR
6647  * address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2
6648  * 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD
6649  * XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only
6650  * access control fields that are loaded during the reset sequence.
6651  */
6652 /*!
6653  * @name Constants and macros for entire FTFA_XACCH0 register
6654  */
6655 /*@{*/
6656 #define FTFA_RD_XACCH0(base)     (FTFA_XACCH0_REG(base))
6657 /*@}*/
6658 
6659 /*******************************************************************************
6660  * FTFA_XACCL3 - Execute-only Access Registers
6661  ******************************************************************************/
6662 
6663 /*!
6664  * @brief FTFA_XACCL3 - Execute-only Access Registers (RO)
6665  *
6666  * Reset value: 0x00U
6667  *
6668  * The XACC registers define which program flash segments are restricted to data
6669  * read or execute only or both data and instruction fetches. The eight XACC
6670  * registers allow up to 64 restricted segments of equal memory size. Execute-only
6671  * access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1
6672  * XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16]
6673  * XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers
6674  * are loaded with the logical AND of Program Flash IFR addresses A and B as
6675  * indicated in the following table. Execute-only access register Program Flash IFR
6676  * address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2
6677  * 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD
6678  * XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only
6679  * access control fields that are loaded during the reset sequence.
6680  */
6681 /*!
6682  * @name Constants and macros for entire FTFA_XACCL3 register
6683  */
6684 /*@{*/
6685 #define FTFA_RD_XACCL3(base)     (FTFA_XACCL3_REG(base))
6686 /*@}*/
6687 
6688 /*******************************************************************************
6689  * FTFA_XACCL2 - Execute-only Access Registers
6690  ******************************************************************************/
6691 
6692 /*!
6693  * @brief FTFA_XACCL2 - Execute-only Access Registers (RO)
6694  *
6695  * Reset value: 0x00U
6696  *
6697  * The XACC registers define which program flash segments are restricted to data
6698  * read or execute only or both data and instruction fetches. The eight XACC
6699  * registers allow up to 64 restricted segments of equal memory size. Execute-only
6700  * access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1
6701  * XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16]
6702  * XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers
6703  * are loaded with the logical AND of Program Flash IFR addresses A and B as
6704  * indicated in the following table. Execute-only access register Program Flash IFR
6705  * address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2
6706  * 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD
6707  * XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only
6708  * access control fields that are loaded during the reset sequence.
6709  */
6710 /*!
6711  * @name Constants and macros for entire FTFA_XACCL2 register
6712  */
6713 /*@{*/
6714 #define FTFA_RD_XACCL2(base)     (FTFA_XACCL2_REG(base))
6715 /*@}*/
6716 
6717 /*******************************************************************************
6718  * FTFA_XACCL1 - Execute-only Access Registers
6719  ******************************************************************************/
6720 
6721 /*!
6722  * @brief FTFA_XACCL1 - Execute-only Access Registers (RO)
6723  *
6724  * Reset value: 0x00U
6725  *
6726  * The XACC registers define which program flash segments are restricted to data
6727  * read or execute only or both data and instruction fetches. The eight XACC
6728  * registers allow up to 64 restricted segments of equal memory size. Execute-only
6729  * access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1
6730  * XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16]
6731  * XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers
6732  * are loaded with the logical AND of Program Flash IFR addresses A and B as
6733  * indicated in the following table. Execute-only access register Program Flash IFR
6734  * address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2
6735  * 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD
6736  * XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only
6737  * access control fields that are loaded during the reset sequence.
6738  */
6739 /*!
6740  * @name Constants and macros for entire FTFA_XACCL1 register
6741  */
6742 /*@{*/
6743 #define FTFA_RD_XACCL1(base)     (FTFA_XACCL1_REG(base))
6744 /*@}*/
6745 
6746 /*******************************************************************************
6747  * FTFA_XACCL0 - Execute-only Access Registers
6748  ******************************************************************************/
6749 
6750 /*!
6751  * @brief FTFA_XACCL0 - Execute-only Access Registers (RO)
6752  *
6753  * Reset value: 0x00U
6754  *
6755  * The XACC registers define which program flash segments are restricted to data
6756  * read or execute only or both data and instruction fetches. The eight XACC
6757  * registers allow up to 64 restricted segments of equal memory size. Execute-only
6758  * access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1
6759  * XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16]
6760  * XACCL2 XA[15:8] XACCL3 XA[7:0] During the reset sequence, the XACC registers
6761  * are loaded with the logical AND of Program Flash IFR addresses A and B as
6762  * indicated in the following table. Execute-only access register Program Flash IFR
6763  * address A Program Flash IFR address B XACCH0 0xA3 0xAB XACCH1 0xA2 0xAA XACCH2
6764  * 0xA1 0xA9 XACCH3 0xA0 0xA8 XACCL0 0xA7 0xAF XACCL1 0xA6 0xAE XACCL2 0xA5 0xAD
6765  * XACCL3 0xA4 0xAC Use the Program Once command to program the execute-only
6766  * access control fields that are loaded during the reset sequence.
6767  */
6768 /*!
6769  * @name Constants and macros for entire FTFA_XACCL0 register
6770  */
6771 /*@{*/
6772 #define FTFA_RD_XACCL0(base)     (FTFA_XACCL0_REG(base))
6773 /*@}*/
6774 
6775 /*******************************************************************************
6776  * FTFA_SACCH3 - Supervisor-only Access Registers
6777  ******************************************************************************/
6778 
6779 /*!
6780  * @brief FTFA_SACCH3 - Supervisor-only Access Registers (RO)
6781  *
6782  * Reset value: 0x00U
6783  *
6784  * The SACC registers define which program flash segments are restricted to
6785  * supervisor only or user and supervisor access. The eight SACC registers allow up
6786  * to 64 restricted segments of equal memory size. Supervisor-only access register
6787  * Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48]
6788  * SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2
6789  * SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded
6790  * with the logical AND of Program Flash IFR addresses A and B as indicated in the
6791  * following table. Supervisor-only access register Program Flash IFR address A
6792  * Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9
6793  * SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3
6794  * 0xB4 0xBC Use the Program Once command to program the supervisor-only access
6795  * control fields that are loaded during the reset sequence.
6796  */
6797 /*!
6798  * @name Constants and macros for entire FTFA_SACCH3 register
6799  */
6800 /*@{*/
6801 #define FTFA_RD_SACCH3(base)     (FTFA_SACCH3_REG(base))
6802 /*@}*/
6803 
6804 /*******************************************************************************
6805  * FTFA_SACCH2 - Supervisor-only Access Registers
6806  ******************************************************************************/
6807 
6808 /*!
6809  * @brief FTFA_SACCH2 - Supervisor-only Access Registers (RO)
6810  *
6811  * Reset value: 0x00U
6812  *
6813  * The SACC registers define which program flash segments are restricted to
6814  * supervisor only or user and supervisor access. The eight SACC registers allow up
6815  * to 64 restricted segments of equal memory size. Supervisor-only access register
6816  * Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48]
6817  * SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2
6818  * SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded
6819  * with the logical AND of Program Flash IFR addresses A and B as indicated in the
6820  * following table. Supervisor-only access register Program Flash IFR address A
6821  * Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9
6822  * SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3
6823  * 0xB4 0xBC Use the Program Once command to program the supervisor-only access
6824  * control fields that are loaded during the reset sequence.
6825  */
6826 /*!
6827  * @name Constants and macros for entire FTFA_SACCH2 register
6828  */
6829 /*@{*/
6830 #define FTFA_RD_SACCH2(base)     (FTFA_SACCH2_REG(base))
6831 /*@}*/
6832 
6833 /*******************************************************************************
6834  * FTFA_SACCH1 - Supervisor-only Access Registers
6835  ******************************************************************************/
6836 
6837 /*!
6838  * @brief FTFA_SACCH1 - Supervisor-only Access Registers (RO)
6839  *
6840  * Reset value: 0x00U
6841  *
6842  * The SACC registers define which program flash segments are restricted to
6843  * supervisor only or user and supervisor access. The eight SACC registers allow up
6844  * to 64 restricted segments of equal memory size. Supervisor-only access register
6845  * Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48]
6846  * SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2
6847  * SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded
6848  * with the logical AND of Program Flash IFR addresses A and B as indicated in the
6849  * following table. Supervisor-only access register Program Flash IFR address A
6850  * Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9
6851  * SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3
6852  * 0xB4 0xBC Use the Program Once command to program the supervisor-only access
6853  * control fields that are loaded during the reset sequence.
6854  */
6855 /*!
6856  * @name Constants and macros for entire FTFA_SACCH1 register
6857  */
6858 /*@{*/
6859 #define FTFA_RD_SACCH1(base)     (FTFA_SACCH1_REG(base))
6860 /*@}*/
6861 
6862 /*******************************************************************************
6863  * FTFA_SACCH0 - Supervisor-only Access Registers
6864  ******************************************************************************/
6865 
6866 /*!
6867  * @brief FTFA_SACCH0 - Supervisor-only Access Registers (RO)
6868  *
6869  * Reset value: 0x00U
6870  *
6871  * The SACC registers define which program flash segments are restricted to
6872  * supervisor only or user and supervisor access. The eight SACC registers allow up
6873  * to 64 restricted segments of equal memory size. Supervisor-only access register
6874  * Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48]
6875  * SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2
6876  * SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded
6877  * with the logical AND of Program Flash IFR addresses A and B as indicated in the
6878  * following table. Supervisor-only access register Program Flash IFR address A
6879  * Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9
6880  * SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3
6881  * 0xB4 0xBC Use the Program Once command to program the supervisor-only access
6882  * control fields that are loaded during the reset sequence.
6883  */
6884 /*!
6885  * @name Constants and macros for entire FTFA_SACCH0 register
6886  */
6887 /*@{*/
6888 #define FTFA_RD_SACCH0(base)     (FTFA_SACCH0_REG(base))
6889 /*@}*/
6890 
6891 /*******************************************************************************
6892  * FTFA_SACCL3 - Supervisor-only Access Registers
6893  ******************************************************************************/
6894 
6895 /*!
6896  * @brief FTFA_SACCL3 - Supervisor-only Access Registers (RO)
6897  *
6898  * Reset value: 0x00U
6899  *
6900  * The SACC registers define which program flash segments are restricted to
6901  * supervisor only or user and supervisor access. The eight SACC registers allow up
6902  * to 64 restricted segments of equal memory size. Supervisor-only access register
6903  * Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48]
6904  * SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2
6905  * SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded
6906  * with the logical AND of Program Flash IFR addresses A and B as indicated in the
6907  * following table. Supervisor-only access register Program Flash IFR address A
6908  * Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9
6909  * SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3
6910  * 0xB4 0xBC Use the Program Once command to program the supervisor-only access
6911  * control fields that are loaded during the reset sequence.
6912  */
6913 /*!
6914  * @name Constants and macros for entire FTFA_SACCL3 register
6915  */
6916 /*@{*/
6917 #define FTFA_RD_SACCL3(base)     (FTFA_SACCL3_REG(base))
6918 /*@}*/
6919 
6920 /*******************************************************************************
6921  * FTFA_SACCL2 - Supervisor-only Access Registers
6922  ******************************************************************************/
6923 
6924 /*!
6925  * @brief FTFA_SACCL2 - Supervisor-only Access Registers (RO)
6926  *
6927  * Reset value: 0x00U
6928  *
6929  * The SACC registers define which program flash segments are restricted to
6930  * supervisor only or user and supervisor access. The eight SACC registers allow up
6931  * to 64 restricted segments of equal memory size. Supervisor-only access register
6932  * Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48]
6933  * SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2
6934  * SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded
6935  * with the logical AND of Program Flash IFR addresses A and B as indicated in the
6936  * following table. Supervisor-only access register Program Flash IFR address A
6937  * Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9
6938  * SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3
6939  * 0xB4 0xBC Use the Program Once command to program the supervisor-only access
6940  * control fields that are loaded during the reset sequence.
6941  */
6942 /*!
6943  * @name Constants and macros for entire FTFA_SACCL2 register
6944  */
6945 /*@{*/
6946 #define FTFA_RD_SACCL2(base)     (FTFA_SACCL2_REG(base))
6947 /*@}*/
6948 
6949 /*******************************************************************************
6950  * FTFA_SACCL1 - Supervisor-only Access Registers
6951  ******************************************************************************/
6952 
6953 /*!
6954  * @brief FTFA_SACCL1 - Supervisor-only Access Registers (RO)
6955  *
6956  * Reset value: 0x00U
6957  *
6958  * The SACC registers define which program flash segments are restricted to
6959  * supervisor only or user and supervisor access. The eight SACC registers allow up
6960  * to 64 restricted segments of equal memory size. Supervisor-only access register
6961  * Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48]
6962  * SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2
6963  * SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded
6964  * with the logical AND of Program Flash IFR addresses A and B as indicated in the
6965  * following table. Supervisor-only access register Program Flash IFR address A
6966  * Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9
6967  * SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3
6968  * 0xB4 0xBC Use the Program Once command to program the supervisor-only access
6969  * control fields that are loaded during the reset sequence.
6970  */
6971 /*!
6972  * @name Constants and macros for entire FTFA_SACCL1 register
6973  */
6974 /*@{*/
6975 #define FTFA_RD_SACCL1(base)     (FTFA_SACCL1_REG(base))
6976 /*@}*/
6977 
6978 /*******************************************************************************
6979  * FTFA_SACCL0 - Supervisor-only Access Registers
6980  ******************************************************************************/
6981 
6982 /*!
6983  * @brief FTFA_SACCL0 - Supervisor-only Access Registers (RO)
6984  *
6985  * Reset value: 0x00U
6986  *
6987  * The SACC registers define which program flash segments are restricted to
6988  * supervisor only or user and supervisor access. The eight SACC registers allow up
6989  * to 64 restricted segments of equal memory size. Supervisor-only access register
6990  * Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48]
6991  * SACCH2 SA[47:40] SACCH3 SA[39:32] SACCL0 SA[31:24] SACCL1 SA[23:16] SACCL2
6992  * SA[15:8] SACCL3 SA[7:0] During the reset sequence, the SACC registers are loaded
6993  * with the logical AND of Program Flash IFR addresses A and B as indicated in the
6994  * following table. Supervisor-only access register Program Flash IFR address A
6995  * Program Flash IFR address B SACCH0 0xB3 0xBB SACCH1 0xB2 0xBA SACCH2 0xB1 0xB9
6996  * SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3
6997  * 0xB4 0xBC Use the Program Once command to program the supervisor-only access
6998  * control fields that are loaded during the reset sequence.
6999  */
7000 /*!
7001  * @name Constants and macros for entire FTFA_SACCL0 register
7002  */
7003 /*@{*/
7004 #define FTFA_RD_SACCL0(base)     (FTFA_SACCL0_REG(base))
7005 /*@}*/
7006 
7007 /*******************************************************************************
7008  * FTFA_FACSS - Flash Access Segment Size Register
7009  ******************************************************************************/
7010 
7011 /*!
7012  * @brief FTFA_FACSS - Flash Access Segment Size Register (RO)
7013  *
7014  * Reset value: 0x00U
7015  *
7016  * The flash access segment size register determines which bits in the address
7017  * are used to index into the SACC and XACC bitmaps to get the appropriate
7018  * permission flags. All bits in the register are read-only. The contents of this
7019  * register are loaded during the reset sequence.
7020  */
7021 /*!
7022  * @name Constants and macros for entire FTFA_FACSS register
7023  */
7024 /*@{*/
7025 #define FTFA_RD_FACSS(base)      (FTFA_FACSS_REG(base))
7026 /*@}*/
7027 
7028 /*******************************************************************************
7029  * FTFA_FACSN - Flash Access Segment Number Register
7030  ******************************************************************************/
7031 
7032 /*!
7033  * @brief FTFA_FACSN - Flash Access Segment Number Register (RO)
7034  *
7035  * Reset value: 0x00U
7036  *
7037  * The flash access segment number register provides the number of program flash
7038  * segments that are available for XACC and SACC permissions. All bits in the
7039  * register are read-only. The contents of this register are loaded during the
7040  * reset sequence.
7041  */
7042 /*!
7043  * @name Constants and macros for entire FTFA_FACSN register
7044  */
7045 /*@{*/
7046 #define FTFA_RD_FACSN(base)      (FTFA_FACSN_REG(base))
7047 /*@}*/
7048 
7049 /*
7050  * MKW40Z4 GPIO
7051  *
7052  * General Purpose Input/Output
7053  *
7054  * Registers defined in this header file:
7055  * - GPIO_PDOR - Port Data Output Register
7056  * - GPIO_PSOR - Port Set Output Register
7057  * - GPIO_PCOR - Port Clear Output Register
7058  * - GPIO_PTOR - Port Toggle Output Register
7059  * - GPIO_PDIR - Port Data Input Register
7060  * - GPIO_PDDR - Port Data Direction Register
7061  */
7062 
7063 #define GPIO_INSTANCE_COUNT (3U) /*!< Number of instances of the GPIO module. */
7064 #define GPIOA_IDX (0U) /*!< Instance number for GPIOA. */
7065 #define GPIOB_IDX (1U) /*!< Instance number for GPIOB. */
7066 #define GPIOC_IDX (2U) /*!< Instance number for GPIOC. */
7067 
7068 /*******************************************************************************
7069  * GPIO_PDOR - Port Data Output Register
7070  ******************************************************************************/
7071 
7072 /*!
7073  * @brief GPIO_PDOR - Port Data Output Register (RW)
7074  *
7075  * Reset value: 0x00000000U
7076  *
7077  * This register configures the logic levels that are driven on each
7078  * general-purpose output pins. Do not modify pin configuration registers associated with
7079  * pins not available in your selected package. All unbonded pins not available in
7080  * your package will default to DISABLE state for lowest power consumption.
7081  */
7082 /*!
7083  * @name Constants and macros for entire GPIO_PDOR register
7084  */
7085 /*@{*/
7086 #define GPIO_RD_PDOR(base)       (GPIO_PDOR_REG(base))
7087 #define GPIO_WR_PDOR(base, value) (GPIO_PDOR_REG(base) = (value))
7088 #define GPIO_RMW_PDOR(base, mask, value) (GPIO_WR_PDOR(base, (GPIO_RD_PDOR(base) & ~(mask)) | (value)))
7089 #define GPIO_SET_PDOR(base, value) (BME_OR32(&GPIO_PDOR_REG(base), (uint32_t)(value)))
7090 #define GPIO_CLR_PDOR(base, value) (BME_AND32(&GPIO_PDOR_REG(base), (uint32_t)(~(value))))
7091 #define GPIO_TOG_PDOR(base, value) (BME_XOR32(&GPIO_PDOR_REG(base), (uint32_t)(value)))
7092 /*@}*/
7093 
7094 /*******************************************************************************
7095  * GPIO_PSOR - Port Set Output Register
7096  ******************************************************************************/
7097 
7098 /*!
7099  * @brief GPIO_PSOR - Port Set Output Register (WORZ)
7100  *
7101  * Reset value: 0x00000000U
7102  *
7103  * This register configures whether to set the fields of the PDOR.
7104  */
7105 /*!
7106  * @name Constants and macros for entire GPIO_PSOR register
7107  */
7108 /*@{*/
7109 #define GPIO_RD_PSOR(base)       (GPIO_PSOR_REG(base))
7110 #define GPIO_WR_PSOR(base, value) (GPIO_PSOR_REG(base) = (value))
7111 #define GPIO_RMW_PSOR(base, mask, value) (GPIO_WR_PSOR(base, (GPIO_RD_PSOR(base) & ~(mask)) | (value)))
7112 /*@}*/
7113 
7114 /*******************************************************************************
7115  * GPIO_PCOR - Port Clear Output Register
7116  ******************************************************************************/
7117 
7118 /*!
7119  * @brief GPIO_PCOR - Port Clear Output Register (WORZ)
7120  *
7121  * Reset value: 0x00000000U
7122  *
7123  * This register configures whether to clear the fields of PDOR.
7124  */
7125 /*!
7126  * @name Constants and macros for entire GPIO_PCOR register
7127  */
7128 /*@{*/
7129 #define GPIO_RD_PCOR(base)       (GPIO_PCOR_REG(base))
7130 #define GPIO_WR_PCOR(base, value) (GPIO_PCOR_REG(base) = (value))
7131 #define GPIO_RMW_PCOR(base, mask, value) (GPIO_WR_PCOR(base, (GPIO_RD_PCOR(base) & ~(mask)) | (value)))
7132 /*@}*/
7133 
7134 /*******************************************************************************
7135  * GPIO_PTOR - Port Toggle Output Register
7136  ******************************************************************************/
7137 
7138 /*!
7139  * @brief GPIO_PTOR - Port Toggle Output Register (WORZ)
7140  *
7141  * Reset value: 0x00000000U
7142  */
7143 /*!
7144  * @name Constants and macros for entire GPIO_PTOR register
7145  */
7146 /*@{*/
7147 #define GPIO_RD_PTOR(base)       (GPIO_PTOR_REG(base))
7148 #define GPIO_WR_PTOR(base, value) (GPIO_PTOR_REG(base) = (value))
7149 #define GPIO_RMW_PTOR(base, mask, value) (GPIO_WR_PTOR(base, (GPIO_RD_PTOR(base) & ~(mask)) | (value)))
7150 /*@}*/
7151 
7152 /*******************************************************************************
7153  * GPIO_PDIR - Port Data Input Register
7154  ******************************************************************************/
7155 
7156 /*!
7157  * @brief GPIO_PDIR - Port Data Input Register (RO)
7158  *
7159  * Reset value: 0x00000000U
7160  *
7161  * Do not modify pin configuration registers associated with pins not available
7162  * in your selected package. All unbonded pins not available in your package will
7163  * default to DISABLE state for lowest power consumption.
7164  */
7165 /*!
7166  * @name Constants and macros for entire GPIO_PDIR register
7167  */
7168 /*@{*/
7169 #define GPIO_RD_PDIR(base)       (GPIO_PDIR_REG(base))
7170 /*@}*/
7171 
7172 /*******************************************************************************
7173  * GPIO_PDDR - Port Data Direction Register
7174  ******************************************************************************/
7175 
7176 /*!
7177  * @brief GPIO_PDDR - Port Data Direction Register (RW)
7178  *
7179  * Reset value: 0x00000000U
7180  *
7181  * The PDDR configures the individual port pins for input or output.
7182  */
7183 /*!
7184  * @name Constants and macros for entire GPIO_PDDR register
7185  */
7186 /*@{*/
7187 #define GPIO_RD_PDDR(base)       (GPIO_PDDR_REG(base))
7188 #define GPIO_WR_PDDR(base, value) (GPIO_PDDR_REG(base) = (value))
7189 #define GPIO_RMW_PDDR(base, mask, value) (GPIO_WR_PDDR(base, (GPIO_RD_PDDR(base) & ~(mask)) | (value)))
7190 #define GPIO_SET_PDDR(base, value) (BME_OR32(&GPIO_PDDR_REG(base), (uint32_t)(value)))
7191 #define GPIO_CLR_PDDR(base, value) (BME_AND32(&GPIO_PDDR_REG(base), (uint32_t)(~(value))))
7192 #define GPIO_TOG_PDDR(base, value) (BME_XOR32(&GPIO_PDDR_REG(base), (uint32_t)(value)))
7193 /*@}*/
7194 
7195 /*
7196  * MKW40Z4 I2C
7197  *
7198  * Inter-Integrated Circuit
7199  *
7200  * Registers defined in this header file:
7201  * - I2C_A1 - I2C Address Register 1
7202  * - I2C_F - I2C Frequency Divider register
7203  * - I2C_C1 - I2C Control Register 1
7204  * - I2C_S - I2C Status register
7205  * - I2C_D - I2C Data I/O register
7206  * - I2C_C2 - I2C Control Register 2
7207  * - I2C_FLT - I2C Programmable Input Glitch Filter Register
7208  * - I2C_RA - I2C Range Address register
7209  * - I2C_SMB - I2C SMBus Control and Status register
7210  * - I2C_A2 - I2C Address Register 2
7211  * - I2C_SLTH - I2C SCL Low Timeout Register High
7212  * - I2C_SLTL - I2C SCL Low Timeout Register Low
7213  * - I2C_S2 - I2C Status register 2
7214  */
7215 
7216 #define I2C_INSTANCE_COUNT (2U) /*!< Number of instances of the I2C module. */
7217 #define I2C0_IDX (0U) /*!< Instance number for I2C0. */
7218 #define I2C1_IDX (1U) /*!< Instance number for I2C1. */
7219 
7220 /*******************************************************************************
7221  * I2C_A1 - I2C Address Register 1
7222  ******************************************************************************/
7223 
7224 /*!
7225  * @brief I2C_A1 - I2C Address Register 1 (RW)
7226  *
7227  * Reset value: 0x00U
7228  *
7229  * This register contains the slave address to be used by the I2C module.
7230  */
7231 /*!
7232  * @name Constants and macros for entire I2C_A1 register
7233  */
7234 /*@{*/
7235 #define I2C_RD_A1(base)          (I2C_A1_REG(base))
7236 #define I2C_WR_A1(base, value)   (I2C_A1_REG(base) = (value))
7237 #define I2C_RMW_A1(base, mask, value) (I2C_WR_A1(base, (I2C_RD_A1(base) & ~(mask)) | (value)))
7238 #define I2C_SET_A1(base, value)  (BME_OR8(&I2C_A1_REG(base), (uint8_t)(value)))
7239 #define I2C_CLR_A1(base, value)  (BME_AND8(&I2C_A1_REG(base), (uint8_t)(~(value))))
7240 #define I2C_TOG_A1(base, value)  (BME_XOR8(&I2C_A1_REG(base), (uint8_t)(value)))
7241 /*@}*/
7242 
7243 /*
7244  * Constants & macros for individual I2C_A1 bitfields
7245  */
7246 
7247 /*!
7248  * @name Register I2C_A1, field AD[7:1] (RW)
7249  *
7250  * Contains the primary slave address used by the I2C module when it is
7251  * addressed as a slave. This field is used in the 7-bit address scheme and the lower
7252  * seven bits in the 10-bit address scheme.
7253  */
7254 /*@{*/
7255 /*! @brief Read current value of the I2C_A1_AD field. */
7256 #define I2C_RD_A1_AD(base)   ((I2C_A1_REG(base) & I2C_A1_AD_MASK) >> I2C_A1_AD_SHIFT)
7257 #define I2C_BRD_A1_AD(base)  (BME_UBFX8(&I2C_A1_REG(base), I2C_A1_AD_SHIFT, I2C_A1_AD_WIDTH))
7258 
7259 /*! @brief Set the AD field to a new value. */
7260 #define I2C_WR_A1_AD(base, value) (I2C_RMW_A1(base, I2C_A1_AD_MASK, I2C_A1_AD(value)))
7261 #define I2C_BWR_A1_AD(base, value) (BME_BFI8(&I2C_A1_REG(base), ((uint8_t)(value) << I2C_A1_AD_SHIFT), I2C_A1_AD_SHIFT, I2C_A1_AD_WIDTH))
7262 /*@}*/
7263 
7264 /*******************************************************************************
7265  * I2C_F - I2C Frequency Divider register
7266  ******************************************************************************/
7267 
7268 /*!
7269  * @brief I2C_F - I2C Frequency Divider register (RW)
7270  *
7271  * Reset value: 0x00U
7272  */
7273 /*!
7274  * @name Constants and macros for entire I2C_F register
7275  */
7276 /*@{*/
7277 #define I2C_RD_F(base)           (I2C_F_REG(base))
7278 #define I2C_WR_F(base, value)    (I2C_F_REG(base) = (value))
7279 #define I2C_RMW_F(base, mask, value) (I2C_WR_F(base, (I2C_RD_F(base) & ~(mask)) | (value)))
7280 #define I2C_SET_F(base, value)   (BME_OR8(&I2C_F_REG(base), (uint8_t)(value)))
7281 #define I2C_CLR_F(base, value)   (BME_AND8(&I2C_F_REG(base), (uint8_t)(~(value))))
7282 #define I2C_TOG_F(base, value)   (BME_XOR8(&I2C_F_REG(base), (uint8_t)(value)))
7283 /*@}*/
7284 
7285 /*
7286  * Constants & macros for individual I2C_F bitfields
7287  */
7288 
7289 /*!
7290  * @name Register I2C_F, field ICR[5:0] (RW)
7291  *
7292  * Prescales the I2C module clock for bit rate selection. This field and the
7293  * MULT field determine the I2C baud rate, the SDA hold time, the SCL start hold
7294  * time, and the SCL stop hold time. For a list of values corresponding to each ICR
7295  * setting, see I2C divider and hold values. The SCL divider multiplied by
7296  * multiplier factor (mul) determines the I2C baud rate. I2C baud rate = I2C module
7297  * clock speed (Hz)/(mul * SCL divider) The SDA hold time is the delay from the
7298  * falling edge of SCL (I2C clock) to the changing of SDA (I2C data). SDA hold time =
7299  * I2C module clock period (s) * mul * SDA hold value The SCL start hold time is
7300  * the delay from the falling edge of SDA (I2C data) while SCL is high (start
7301  * condition) to the falling edge of SCL (I2C clock). SCL start hold time = I2C
7302  * module clock period (s) * mul * SCL start hold value The SCL stop hold time is
7303  * the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
7304  * data) while SCL is high (stop condition). SCL stop hold time = I2C module
7305  * clock period (s) * mul * SCL stop hold value For example, if the I2C module clock
7306  * speed is 8 MHz, the following table shows the possible hold time values with
7307  * different ICR and MULT selections to achieve an I2C baud rate of 100 kbit/s.
7308  * MULT ICR Hold times (us) SDA SCL Start SCL Stop 2h 00h 3.500 3.000 5.500 1h 07h
7309  * 2.500 4.000 5.250 1h 0Bh 2.250 4.000 5.250 0h 14h 2.125 4.250 5.125 0h 18h
7310  * 1.125 4.750 5.125
7311  */
7312 /*@{*/
7313 /*! @brief Read current value of the I2C_F_ICR field. */
7314 #define I2C_RD_F_ICR(base)   ((I2C_F_REG(base) & I2C_F_ICR_MASK) >> I2C_F_ICR_SHIFT)
7315 #define I2C_BRD_F_ICR(base)  (BME_UBFX8(&I2C_F_REG(base), I2C_F_ICR_SHIFT, I2C_F_ICR_WIDTH))
7316 
7317 /*! @brief Set the ICR field to a new value. */
7318 #define I2C_WR_F_ICR(base, value) (I2C_RMW_F(base, I2C_F_ICR_MASK, I2C_F_ICR(value)))
7319 #define I2C_BWR_F_ICR(base, value) (BME_BFI8(&I2C_F_REG(base), ((uint8_t)(value) << I2C_F_ICR_SHIFT), I2C_F_ICR_SHIFT, I2C_F_ICR_WIDTH))
7320 /*@}*/
7321 
7322 /*!
7323  * @name Register I2C_F, field MULT[7:6] (RW)
7324  *
7325  * Defines the multiplier factor (mul). This factor is used along with the SCL
7326  * divider to generate the I2C baud rate.
7327  *
7328  * Values:
7329  * - 0b00 - mul = 1
7330  * - 0b01 - mul = 2
7331  * - 0b10 - mul = 4
7332  * - 0b11 - Reserved
7333  */
7334 /*@{*/
7335 /*! @brief Read current value of the I2C_F_MULT field. */
7336 #define I2C_RD_F_MULT(base)  ((I2C_F_REG(base) & I2C_F_MULT_MASK) >> I2C_F_MULT_SHIFT)
7337 #define I2C_BRD_F_MULT(base) (BME_UBFX8(&I2C_F_REG(base), I2C_F_MULT_SHIFT, I2C_F_MULT_WIDTH))
7338 
7339 /*! @brief Set the MULT field to a new value. */
7340 #define I2C_WR_F_MULT(base, value) (I2C_RMW_F(base, I2C_F_MULT_MASK, I2C_F_MULT(value)))
7341 #define I2C_BWR_F_MULT(base, value) (BME_BFI8(&I2C_F_REG(base), ((uint8_t)(value) << I2C_F_MULT_SHIFT), I2C_F_MULT_SHIFT, I2C_F_MULT_WIDTH))
7342 /*@}*/
7343 
7344 /*******************************************************************************
7345  * I2C_C1 - I2C Control Register 1
7346  ******************************************************************************/
7347 
7348 /*!
7349  * @brief I2C_C1 - I2C Control Register 1 (RW)
7350  *
7351  * Reset value: 0x00U
7352  */
7353 /*!
7354  * @name Constants and macros for entire I2C_C1 register
7355  */
7356 /*@{*/
7357 #define I2C_RD_C1(base)          (I2C_C1_REG(base))
7358 #define I2C_WR_C1(base, value)   (I2C_C1_REG(base) = (value))
7359 #define I2C_RMW_C1(base, mask, value) (I2C_WR_C1(base, (I2C_RD_C1(base) & ~(mask)) | (value)))
7360 #define I2C_SET_C1(base, value)  (BME_OR8(&I2C_C1_REG(base), (uint8_t)(value)))
7361 #define I2C_CLR_C1(base, value)  (BME_AND8(&I2C_C1_REG(base), (uint8_t)(~(value))))
7362 #define I2C_TOG_C1(base, value)  (BME_XOR8(&I2C_C1_REG(base), (uint8_t)(value)))
7363 /*@}*/
7364 
7365 /*
7366  * Constants & macros for individual I2C_C1 bitfields
7367  */
7368 
7369 /*!
7370  * @name Register I2C_C1, field DMAEN[0] (RW)
7371  *
7372  * Enables or disables the DMA function.
7373  *
7374  * Values:
7375  * - 0b0 - All DMA signalling disabled.
7376  * - 0b1 - DMA transfer is enabled. While SMB[FACK] = 0, the following
7377  *     conditions trigger the DMA request: a data byte is received, and either address or
7378  *     data is transmitted. (ACK/NACK is automatic) the first byte received
7379  *     matches the A1 register or is a general call address. If any address matching
7380  *     occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known
7381  *     from master to slave, then it is not required to check S[SRW]. With this
7382  *     assumption, DMA can also be used in this case. In other cases, if the master
7383  *     reads data from the slave, then it is required to rewrite the C1 register
7384  *     operation. With this assumption, DMA cannot be used. When FACK = 1, an
7385  *     address or a data byte is transmitted.
7386  */
7387 /*@{*/
7388 /*! @brief Read current value of the I2C_C1_DMAEN field. */
7389 #define I2C_RD_C1_DMAEN(base) ((I2C_C1_REG(base) & I2C_C1_DMAEN_MASK) >> I2C_C1_DMAEN_SHIFT)
7390 #define I2C_BRD_C1_DMAEN(base) (BME_UBFX8(&I2C_C1_REG(base), I2C_C1_DMAEN_SHIFT, I2C_C1_DMAEN_WIDTH))
7391 
7392 /*! @brief Set the DMAEN field to a new value. */
7393 #define I2C_WR_C1_DMAEN(base, value) (I2C_RMW_C1(base, I2C_C1_DMAEN_MASK, I2C_C1_DMAEN(value)))
7394 #define I2C_BWR_C1_DMAEN(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_DMAEN_SHIFT), I2C_C1_DMAEN_SHIFT, I2C_C1_DMAEN_WIDTH))
7395 /*@}*/
7396 
7397 /*!
7398  * @name Register I2C_C1, field WUEN[1] (RW)
7399  *
7400  * The I2C module can wake the MCU from low power mode with no peripheral bus
7401  * running when slave address matching occurs.
7402  *
7403  * Values:
7404  * - 0b0 - Normal operation. No interrupt generated when address matching in low
7405  *     power mode.
7406  * - 0b1 - Enables the wakeup function in low power mode.
7407  */
7408 /*@{*/
7409 /*! @brief Read current value of the I2C_C1_WUEN field. */
7410 #define I2C_RD_C1_WUEN(base) ((I2C_C1_REG(base) & I2C_C1_WUEN_MASK) >> I2C_C1_WUEN_SHIFT)
7411 #define I2C_BRD_C1_WUEN(base) (BME_UBFX8(&I2C_C1_REG(base), I2C_C1_WUEN_SHIFT, I2C_C1_WUEN_WIDTH))
7412 
7413 /*! @brief Set the WUEN field to a new value. */
7414 #define I2C_WR_C1_WUEN(base, value) (I2C_RMW_C1(base, I2C_C1_WUEN_MASK, I2C_C1_WUEN(value)))
7415 #define I2C_BWR_C1_WUEN(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_WUEN_SHIFT), I2C_C1_WUEN_SHIFT, I2C_C1_WUEN_WIDTH))
7416 /*@}*/
7417 
7418 /*!
7419  * @name Register I2C_C1, field RSTA[2] (WORZ)
7420  *
7421  * Writing 1 to this bit generates a repeated START condition provided it is the
7422  * current master. This bit will always be read as 0. Attempting a repeat at the
7423  * wrong time results in loss of arbitration.
7424  */
7425 /*@{*/
7426 /*! @brief Set the RSTA field to a new value. */
7427 #define I2C_WR_C1_RSTA(base, value) (I2C_RMW_C1(base, I2C_C1_RSTA_MASK, I2C_C1_RSTA(value)))
7428 #define I2C_BWR_C1_RSTA(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_RSTA_SHIFT), I2C_C1_RSTA_SHIFT, I2C_C1_RSTA_WIDTH))
7429 /*@}*/
7430 
7431 /*!
7432  * @name Register I2C_C1, field TXAK[3] (RW)
7433  *
7434  * Specifies the value driven onto the SDA during data acknowledge cycles for
7435  * both master and slave receivers. The value of SMB[FACK] affects NACK/ACK
7436  * generation. SCL is held low until TXAK is written.
7437  *
7438  * Values:
7439  * - 0b0 - An acknowledge signal is sent to the bus on the following receiving
7440  *     byte (if FACK is cleared) or the current receiving byte (if FACK is set).
7441  * - 0b1 - No acknowledge signal is sent to the bus on the following receiving
7442  *     data byte (if FACK is cleared) or the current receiving data byte (if FACK
7443  *     is set).
7444  */
7445 /*@{*/
7446 /*! @brief Read current value of the I2C_C1_TXAK field. */
7447 #define I2C_RD_C1_TXAK(base) ((I2C_C1_REG(base) & I2C_C1_TXAK_MASK) >> I2C_C1_TXAK_SHIFT)
7448 #define I2C_BRD_C1_TXAK(base) (BME_UBFX8(&I2C_C1_REG(base), I2C_C1_TXAK_SHIFT, I2C_C1_TXAK_WIDTH))
7449 
7450 /*! @brief Set the TXAK field to a new value. */
7451 #define I2C_WR_C1_TXAK(base, value) (I2C_RMW_C1(base, I2C_C1_TXAK_MASK, I2C_C1_TXAK(value)))
7452 #define I2C_BWR_C1_TXAK(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_TXAK_SHIFT), I2C_C1_TXAK_SHIFT, I2C_C1_TXAK_WIDTH))
7453 /*@}*/
7454 
7455 /*!
7456  * @name Register I2C_C1, field TX[4] (RW)
7457  *
7458  * Selects the direction of master and slave transfers. In master mode this bit
7459  * must be set according to the type of transfer required. Therefore, for address
7460  * cycles, this bit is always set. When addressed as a slave this bit must be
7461  * set by software according to the SRW bit in the status register.
7462  *
7463  * Values:
7464  * - 0b0 - Receive
7465  * - 0b1 - Transmit
7466  */
7467 /*@{*/
7468 /*! @brief Read current value of the I2C_C1_TX field. */
7469 #define I2C_RD_C1_TX(base)   ((I2C_C1_REG(base) & I2C_C1_TX_MASK) >> I2C_C1_TX_SHIFT)
7470 #define I2C_BRD_C1_TX(base)  (BME_UBFX8(&I2C_C1_REG(base), I2C_C1_TX_SHIFT, I2C_C1_TX_WIDTH))
7471 
7472 /*! @brief Set the TX field to a new value. */
7473 #define I2C_WR_C1_TX(base, value) (I2C_RMW_C1(base, I2C_C1_TX_MASK, I2C_C1_TX(value)))
7474 #define I2C_BWR_C1_TX(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_TX_SHIFT), I2C_C1_TX_SHIFT, I2C_C1_TX_WIDTH))
7475 /*@}*/
7476 
7477 /*!
7478  * @name Register I2C_C1, field MST[5] (RW)
7479  *
7480  * When MST is changed from 0 to 1, a START signal is generated on the bus and
7481  * master mode is selected. When this bit changes from 1 to 0, a STOP signal is
7482  * generated and the mode of operation changes from master to slave.
7483  *
7484  * Values:
7485  * - 0b0 - Slave mode
7486  * - 0b1 - Master mode
7487  */
7488 /*@{*/
7489 /*! @brief Read current value of the I2C_C1_MST field. */
7490 #define I2C_RD_C1_MST(base)  ((I2C_C1_REG(base) & I2C_C1_MST_MASK) >> I2C_C1_MST_SHIFT)
7491 #define I2C_BRD_C1_MST(base) (BME_UBFX8(&I2C_C1_REG(base), I2C_C1_MST_SHIFT, I2C_C1_MST_WIDTH))
7492 
7493 /*! @brief Set the MST field to a new value. */
7494 #define I2C_WR_C1_MST(base, value) (I2C_RMW_C1(base, I2C_C1_MST_MASK, I2C_C1_MST(value)))
7495 #define I2C_BWR_C1_MST(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_MST_SHIFT), I2C_C1_MST_SHIFT, I2C_C1_MST_WIDTH))
7496 /*@}*/
7497 
7498 /*!
7499  * @name Register I2C_C1, field IICIE[6] (RW)
7500  *
7501  * Enables I2C interrupt requests.
7502  *
7503  * Values:
7504  * - 0b0 - Disabled
7505  * - 0b1 - Enabled
7506  */
7507 /*@{*/
7508 /*! @brief Read current value of the I2C_C1_IICIE field. */
7509 #define I2C_RD_C1_IICIE(base) ((I2C_C1_REG(base) & I2C_C1_IICIE_MASK) >> I2C_C1_IICIE_SHIFT)
7510 #define I2C_BRD_C1_IICIE(base) (BME_UBFX8(&I2C_C1_REG(base), I2C_C1_IICIE_SHIFT, I2C_C1_IICIE_WIDTH))
7511 
7512 /*! @brief Set the IICIE field to a new value. */
7513 #define I2C_WR_C1_IICIE(base, value) (I2C_RMW_C1(base, I2C_C1_IICIE_MASK, I2C_C1_IICIE(value)))
7514 #define I2C_BWR_C1_IICIE(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_IICIE_SHIFT), I2C_C1_IICIE_SHIFT, I2C_C1_IICIE_WIDTH))
7515 /*@}*/
7516 
7517 /*!
7518  * @name Register I2C_C1, field IICEN[7] (RW)
7519  *
7520  * Enables I2C module operation.
7521  *
7522  * Values:
7523  * - 0b0 - Disabled
7524  * - 0b1 - Enabled
7525  */
7526 /*@{*/
7527 /*! @brief Read current value of the I2C_C1_IICEN field. */
7528 #define I2C_RD_C1_IICEN(base) ((I2C_C1_REG(base) & I2C_C1_IICEN_MASK) >> I2C_C1_IICEN_SHIFT)
7529 #define I2C_BRD_C1_IICEN(base) (BME_UBFX8(&I2C_C1_REG(base), I2C_C1_IICEN_SHIFT, I2C_C1_IICEN_WIDTH))
7530 
7531 /*! @brief Set the IICEN field to a new value. */
7532 #define I2C_WR_C1_IICEN(base, value) (I2C_RMW_C1(base, I2C_C1_IICEN_MASK, I2C_C1_IICEN(value)))
7533 #define I2C_BWR_C1_IICEN(base, value) (BME_BFI8(&I2C_C1_REG(base), ((uint8_t)(value) << I2C_C1_IICEN_SHIFT), I2C_C1_IICEN_SHIFT, I2C_C1_IICEN_WIDTH))
7534 /*@}*/
7535 
7536 /*******************************************************************************
7537  * I2C_S - I2C Status register
7538  ******************************************************************************/
7539 
7540 /*!
7541  * @brief I2C_S - I2C Status register (RW)
7542  *
7543  * Reset value: 0x80U
7544  */
7545 /*!
7546  * @name Constants and macros for entire I2C_S register
7547  */
7548 /*@{*/
7549 #define I2C_RD_S(base)           (I2C_S_REG(base))
7550 #define I2C_WR_S(base, value)    (I2C_S_REG(base) = (value))
7551 #define I2C_RMW_S(base, mask, value) (I2C_WR_S(base, (I2C_RD_S(base) & ~(mask)) | (value)))
7552 #define I2C_SET_S(base, value)   (BME_OR8(&I2C_S_REG(base), (uint8_t)(value)))
7553 #define I2C_CLR_S(base, value)   (BME_AND8(&I2C_S_REG(base), (uint8_t)(~(value))))
7554 #define I2C_TOG_S(base, value)   (BME_XOR8(&I2C_S_REG(base), (uint8_t)(value)))
7555 /*@}*/
7556 
7557 /*
7558  * Constants & macros for individual I2C_S bitfields
7559  */
7560 
7561 /*!
7562  * @name Register I2C_S, field RXAK[0] (RO)
7563  *
7564  * Values:
7565  * - 0b0 - Acknowledge signal was received after the completion of one byte of
7566  *     data transmission on the bus
7567  * - 0b1 - No acknowledge signal detected
7568  */
7569 /*@{*/
7570 /*! @brief Read current value of the I2C_S_RXAK field. */
7571 #define I2C_RD_S_RXAK(base)  ((I2C_S_REG(base) & I2C_S_RXAK_MASK) >> I2C_S_RXAK_SHIFT)
7572 #define I2C_BRD_S_RXAK(base) (BME_UBFX8(&I2C_S_REG(base), I2C_S_RXAK_SHIFT, I2C_S_RXAK_WIDTH))
7573 /*@}*/
7574 
7575 /*!
7576  * @name Register I2C_S, field IICIF[1] (W1C)
7577  *
7578  * This bit sets when an interrupt is pending. This bit must be cleared by
7579  * software by writing 1 to it, such as in the interrupt routine. One of the following
7580  * events can set this bit: One byte transfer, including ACK/NACK bit, completes
7581  * if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK
7582  * after this bit is set in receive mode. One byte transfer, excluding ACK/NACK bit,
7583  * completes if FACK is 1. Match of slave address to calling address including
7584  * primary slave address, range slave address , alert response address, second
7585  * slave address, or general call address. Arbitration lost In SMBus mode, any
7586  * timeouts except SCL and SDA high timeouts I2C bus stop or start detection if the
7587  * STOPIE SSIE bit in the Input Glitch Filter register is 1 To clear the I2C bus
7588  * stop or start detection interrupt: In the interrupt service routine, first clear
7589  * the STOPF or STARTF bit in the Input Glitch Filter register by writing 1 to
7590  * it, and then clear the IICIF bit. If this sequence is reversed, the IICIF bit
7591  * is asserted again.
7592  *
7593  * Values:
7594  * - 0b0 - No interrupt pending
7595  * - 0b1 - Interrupt pending
7596  */
7597 /*@{*/
7598 /*! @brief Read current value of the I2C_S_IICIF field. */
7599 #define I2C_RD_S_IICIF(base) ((I2C_S_REG(base) & I2C_S_IICIF_MASK) >> I2C_S_IICIF_SHIFT)
7600 #define I2C_BRD_S_IICIF(base) (BME_UBFX8(&I2C_S_REG(base), I2C_S_IICIF_SHIFT, I2C_S_IICIF_WIDTH))
7601 
7602 /*! @brief Set the IICIF field to a new value. */
7603 #define I2C_WR_S_IICIF(base, value) (I2C_RMW_S(base, (I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_IICIF(value)))
7604 #define I2C_BWR_S_IICIF(base, value) (BME_BFI8(&I2C_S_REG(base), ((uint8_t)(value) << I2C_S_IICIF_SHIFT), I2C_S_IICIF_SHIFT, I2C_S_IICIF_WIDTH))
7605 /*@}*/
7606 
7607 /*!
7608  * @name Register I2C_S, field SRW[2] (RO)
7609  *
7610  * When addressed as a slave, SRW indicates the value of the R/W command bit of
7611  * the calling address sent to the master.
7612  *
7613  * Values:
7614  * - 0b0 - Slave receive, master writing to slave
7615  * - 0b1 - Slave transmit, master reading from slave
7616  */
7617 /*@{*/
7618 /*! @brief Read current value of the I2C_S_SRW field. */
7619 #define I2C_RD_S_SRW(base)   ((I2C_S_REG(base) & I2C_S_SRW_MASK) >> I2C_S_SRW_SHIFT)
7620 #define I2C_BRD_S_SRW(base)  (BME_UBFX8(&I2C_S_REG(base), I2C_S_SRW_SHIFT, I2C_S_SRW_WIDTH))
7621 /*@}*/
7622 
7623 /*!
7624  * @name Register I2C_S, field RAM[3] (RW)
7625  *
7626  * This bit is set to 1 by any of the following conditions, if I2C_C2[RMEN] = 1:
7627  * Any nonzero calling address is received that matches the address in the RA
7628  * register. The calling address is within the range of values of the A1 and RA
7629  * registers. For the RAM bit to be set to 1 correctly, C1[IICIE] must be set to 1.
7630  * Writing the C1 register with any value clears this bit to 0.
7631  *
7632  * Values:
7633  * - 0b0 - Not addressed
7634  * - 0b1 - Addressed as a slave
7635  */
7636 /*@{*/
7637 /*! @brief Read current value of the I2C_S_RAM field. */
7638 #define I2C_RD_S_RAM(base)   ((I2C_S_REG(base) & I2C_S_RAM_MASK) >> I2C_S_RAM_SHIFT)
7639 #define I2C_BRD_S_RAM(base)  (BME_UBFX8(&I2C_S_REG(base), I2C_S_RAM_SHIFT, I2C_S_RAM_WIDTH))
7640 
7641 /*! @brief Set the RAM field to a new value. */
7642 #define I2C_WR_S_RAM(base, value) (I2C_RMW_S(base, (I2C_S_RAM_MASK | I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_RAM(value)))
7643 #define I2C_BWR_S_RAM(base, value) (BME_BFI8(&I2C_S_REG(base), ((uint8_t)(value) << I2C_S_RAM_SHIFT), I2C_S_RAM_SHIFT, I2C_S_RAM_WIDTH))
7644 /*@}*/
7645 
7646 /*!
7647  * @name Register I2C_S, field ARBL[4] (W1C)
7648  *
7649  * This bit is set by hardware when the arbitration procedure is lost. The ARBL
7650  * bit must be cleared by software, by writing 1 to it.
7651  *
7652  * Values:
7653  * - 0b0 - Standard bus operation.
7654  * - 0b1 - Loss of arbitration.
7655  */
7656 /*@{*/
7657 /*! @brief Read current value of the I2C_S_ARBL field. */
7658 #define I2C_RD_S_ARBL(base)  ((I2C_S_REG(base) & I2C_S_ARBL_MASK) >> I2C_S_ARBL_SHIFT)
7659 #define I2C_BRD_S_ARBL(base) (BME_UBFX8(&I2C_S_REG(base), I2C_S_ARBL_SHIFT, I2C_S_ARBL_WIDTH))
7660 
7661 /*! @brief Set the ARBL field to a new value. */
7662 #define I2C_WR_S_ARBL(base, value) (I2C_RMW_S(base, (I2C_S_ARBL_MASK | I2C_S_IICIF_MASK), I2C_S_ARBL(value)))
7663 #define I2C_BWR_S_ARBL(base, value) (BME_BFI8(&I2C_S_REG(base), ((uint8_t)(value) << I2C_S_ARBL_SHIFT), I2C_S_ARBL_SHIFT, I2C_S_ARBL_WIDTH))
7664 /*@}*/
7665 
7666 /*!
7667  * @name Register I2C_S, field BUSY[5] (RO)
7668  *
7669  * Indicates the status of the bus regardless of slave or master mode. This bit
7670  * is set when a START signal is detected and cleared when a STOP signal is
7671  * detected.
7672  *
7673  * Values:
7674  * - 0b0 - Bus is idle
7675  * - 0b1 - Bus is busy
7676  */
7677 /*@{*/
7678 /*! @brief Read current value of the I2C_S_BUSY field. */
7679 #define I2C_RD_S_BUSY(base)  ((I2C_S_REG(base) & I2C_S_BUSY_MASK) >> I2C_S_BUSY_SHIFT)
7680 #define I2C_BRD_S_BUSY(base) (BME_UBFX8(&I2C_S_REG(base), I2C_S_BUSY_SHIFT, I2C_S_BUSY_WIDTH))
7681 /*@}*/
7682 
7683 /*!
7684  * @name Register I2C_S, field IAAS[6] (RW)
7685  *
7686  * This bit is set by one of the following conditions: The calling address
7687  * matches the programmed primary slave address in the A1 register, or matches the
7688  * range address in the RA register (which must be set to a nonzero value and under
7689  * the condition I2C_C2[RMEN] = 1). C2[GCAEN] is set and a general call is
7690  * received. SMB[SIICAEN] is set and the calling address matches the second programmed
7691  * slave address. ALERTEN is set and an SMBus alert response address is received
7692  * RMEN is set and an address is received that is within the range between the
7693  * values of the A1 and RA registers. IAAS sets before the ACK bit. The CPU must
7694  * check the SRW bit and set TX/RX accordingly. Writing the C1 register with any
7695  * value clears this bit.
7696  *
7697  * Values:
7698  * - 0b0 - Not addressed
7699  * - 0b1 - Addressed as a slave
7700  */
7701 /*@{*/
7702 /*! @brief Read current value of the I2C_S_IAAS field. */
7703 #define I2C_RD_S_IAAS(base)  ((I2C_S_REG(base) & I2C_S_IAAS_MASK) >> I2C_S_IAAS_SHIFT)
7704 #define I2C_BRD_S_IAAS(base) (BME_UBFX8(&I2C_S_REG(base), I2C_S_IAAS_SHIFT, I2C_S_IAAS_WIDTH))
7705 
7706 /*! @brief Set the IAAS field to a new value. */
7707 #define I2C_WR_S_IAAS(base, value) (I2C_RMW_S(base, (I2C_S_IAAS_MASK | I2C_S_IICIF_MASK | I2C_S_ARBL_MASK), I2C_S_IAAS(value)))
7708 #define I2C_BWR_S_IAAS(base, value) (BME_BFI8(&I2C_S_REG(base), ((uint8_t)(value) << I2C_S_IAAS_SHIFT), I2C_S_IAAS_SHIFT, I2C_S_IAAS_WIDTH))
7709 /*@}*/
7710 
7711 /*!
7712  * @name Register I2C_S, field TCF[7] (RO)
7713  *
7714  * Acknowledges a byte transfer; TCF is set on the completion of a byte
7715  * transfer. This bit is valid only during or immediately following a transfer to or from
7716  * the I2C module. TCF is cleared by reading the I2C data register in receive
7717  * mode or by writing to the I2C data register in transmit mode.In the buffer mode,
7718  * TCF is cleared automatically by internal reading or writing the data register
7719  * I2C_D, with no need waiting for manually reading/writing the I2C data
7720  * register in Rx/Tx mode.
7721  *
7722  * Values:
7723  * - 0b0 - Transfer in progress
7724  * - 0b1 - Transfer complete
7725  */
7726 /*@{*/
7727 /*! @brief Read current value of the I2C_S_TCF field. */
7728 #define I2C_RD_S_TCF(base)   ((I2C_S_REG(base) & I2C_S_TCF_MASK) >> I2C_S_TCF_SHIFT)
7729 #define I2C_BRD_S_TCF(base)  (BME_UBFX8(&I2C_S_REG(base), I2C_S_TCF_SHIFT, I2C_S_TCF_WIDTH))
7730 /*@}*/
7731 
7732 /*******************************************************************************
7733  * I2C_D - I2C Data I/O register
7734  ******************************************************************************/
7735 
7736 /*!
7737  * @brief I2C_D - I2C Data I/O register (RW)
7738  *
7739  * Reset value: 0x00U
7740  */
7741 /*!
7742  * @name Constants and macros for entire I2C_D register
7743  */
7744 /*@{*/
7745 #define I2C_RD_D(base)           (I2C_D_REG(base))
7746 #define I2C_WR_D(base, value)    (I2C_D_REG(base) = (value))
7747 #define I2C_RMW_D(base, mask, value) (I2C_WR_D(base, (I2C_RD_D(base) & ~(mask)) | (value)))
7748 #define I2C_SET_D(base, value)   (BME_OR8(&I2C_D_REG(base), (uint8_t)(value)))
7749 #define I2C_CLR_D(base, value)   (BME_AND8(&I2C_D_REG(base), (uint8_t)(~(value))))
7750 #define I2C_TOG_D(base, value)   (BME_XOR8(&I2C_D_REG(base), (uint8_t)(value)))
7751 /*@}*/
7752 
7753 /*******************************************************************************
7754  * I2C_C2 - I2C Control Register 2
7755  ******************************************************************************/
7756 
7757 /*!
7758  * @brief I2C_C2 - I2C Control Register 2 (RW)
7759  *
7760  * Reset value: 0x00U
7761  */
7762 /*!
7763  * @name Constants and macros for entire I2C_C2 register
7764  */
7765 /*@{*/
7766 #define I2C_RD_C2(base)          (I2C_C2_REG(base))
7767 #define I2C_WR_C2(base, value)   (I2C_C2_REG(base) = (value))
7768 #define I2C_RMW_C2(base, mask, value) (I2C_WR_C2(base, (I2C_RD_C2(base) & ~(mask)) | (value)))
7769 #define I2C_SET_C2(base, value)  (BME_OR8(&I2C_C2_REG(base), (uint8_t)(value)))
7770 #define I2C_CLR_C2(base, value)  (BME_AND8(&I2C_C2_REG(base), (uint8_t)(~(value))))
7771 #define I2C_TOG_C2(base, value)  (BME_XOR8(&I2C_C2_REG(base), (uint8_t)(value)))
7772 /*@}*/
7773 
7774 /*
7775  * Constants & macros for individual I2C_C2 bitfields
7776  */
7777 
7778 /*!
7779  * @name Register I2C_C2, field AD[2:0] (RW)
7780  *
7781  * Contains the upper three bits of the slave address in the 10-bit address
7782  * scheme. This field is valid only while the ADEXT bit is set.
7783  */
7784 /*@{*/
7785 /*! @brief Read current value of the I2C_C2_AD field. */
7786 #define I2C_RD_C2_AD(base)   ((I2C_C2_REG(base) & I2C_C2_AD_MASK) >> I2C_C2_AD_SHIFT)
7787 #define I2C_BRD_C2_AD(base)  (BME_UBFX8(&I2C_C2_REG(base), I2C_C2_AD_SHIFT, I2C_C2_AD_WIDTH))
7788 
7789 /*! @brief Set the AD field to a new value. */
7790 #define I2C_WR_C2_AD(base, value) (I2C_RMW_C2(base, I2C_C2_AD_MASK, I2C_C2_AD(value)))
7791 #define I2C_BWR_C2_AD(base, value) (BME_BFI8(&I2C_C2_REG(base), ((uint8_t)(value) << I2C_C2_AD_SHIFT), I2C_C2_AD_SHIFT, I2C_C2_AD_WIDTH))
7792 /*@}*/
7793 
7794 /*!
7795  * @name Register I2C_C2, field RMEN[3] (RW)
7796  *
7797  * This bit controls the slave address matching for addresses between the values
7798  * of the A1 and RA registers. When this bit is set, a slave address matching
7799  * occurs for any address greater than the value of the A1 register and less than
7800  * or equal to the value of the RA register.
7801  *
7802  * Values:
7803  * - 0b0 - Range mode disabled. No address matching occurs for an address within
7804  *     the range of values of the A1 and RA registers.
7805  * - 0b1 - Range mode enabled. Address matching occurs when a slave receives an
7806  *     address within the range of values of the A1 and RA registers.
7807  */
7808 /*@{*/
7809 /*! @brief Read current value of the I2C_C2_RMEN field. */
7810 #define I2C_RD_C2_RMEN(base) ((I2C_C2_REG(base) & I2C_C2_RMEN_MASK) >> I2C_C2_RMEN_SHIFT)
7811 #define I2C_BRD_C2_RMEN(base) (BME_UBFX8(&I2C_C2_REG(base), I2C_C2_RMEN_SHIFT, I2C_C2_RMEN_WIDTH))
7812 
7813 /*! @brief Set the RMEN field to a new value. */
7814 #define I2C_WR_C2_RMEN(base, value) (I2C_RMW_C2(base, I2C_C2_RMEN_MASK, I2C_C2_RMEN(value)))
7815 #define I2C_BWR_C2_RMEN(base, value) (BME_BFI8(&I2C_C2_REG(base), ((uint8_t)(value) << I2C_C2_RMEN_SHIFT), I2C_C2_RMEN_SHIFT, I2C_C2_RMEN_WIDTH))
7816 /*@}*/
7817 
7818 /*!
7819  * @name Register I2C_C2, field SBRC[4] (RW)
7820  *
7821  * Enables independent slave mode baud rate at maximum frequency, which forces
7822  * clock stretching on SCL in very fast I2C modes. To a slave, an example of a
7823  * "very fast" mode is when the master transfers at 40 kbit/s but the slave can
7824  * capture the master's data at only 10 kbit/s.
7825  *
7826  * Values:
7827  * - 0b0 - The slave baud rate follows the master baud rate and clock stretching
7828  *     may occur
7829  * - 0b1 - Slave baud rate is independent of the master baud rate
7830  */
7831 /*@{*/
7832 /*! @brief Read current value of the I2C_C2_SBRC field. */
7833 #define I2C_RD_C2_SBRC(base) ((I2C_C2_REG(base) & I2C_C2_SBRC_MASK) >> I2C_C2_SBRC_SHIFT)
7834 #define I2C_BRD_C2_SBRC(base) (BME_UBFX8(&I2C_C2_REG(base), I2C_C2_SBRC_SHIFT, I2C_C2_SBRC_WIDTH))
7835 
7836 /*! @brief Set the SBRC field to a new value. */
7837 #define I2C_WR_C2_SBRC(base, value) (I2C_RMW_C2(base, I2C_C2_SBRC_MASK, I2C_C2_SBRC(value)))
7838 #define I2C_BWR_C2_SBRC(base, value) (BME_BFI8(&I2C_C2_REG(base), ((uint8_t)(value) << I2C_C2_SBRC_SHIFT), I2C_C2_SBRC_SHIFT, I2C_C2_SBRC_WIDTH))
7839 /*@}*/
7840 
7841 /*!
7842  * @name Register I2C_C2, field HDRS[5] (RW)
7843  *
7844  * Controls the drive capability of the I2C pads.
7845  *
7846  * Values:
7847  * - 0b0 - Normal drive mode
7848  * - 0b1 - High drive mode
7849  */
7850 /*@{*/
7851 /*! @brief Read current value of the I2C_C2_HDRS field. */
7852 #define I2C_RD_C2_HDRS(base) ((I2C_C2_REG(base) & I2C_C2_HDRS_MASK) >> I2C_C2_HDRS_SHIFT)
7853 #define I2C_BRD_C2_HDRS(base) (BME_UBFX8(&I2C_C2_REG(base), I2C_C2_HDRS_SHIFT, I2C_C2_HDRS_WIDTH))
7854 
7855 /*! @brief Set the HDRS field to a new value. */
7856 #define I2C_WR_C2_HDRS(base, value) (I2C_RMW_C2(base, I2C_C2_HDRS_MASK, I2C_C2_HDRS(value)))
7857 #define I2C_BWR_C2_HDRS(base, value) (BME_BFI8(&I2C_C2_REG(base), ((uint8_t)(value) << I2C_C2_HDRS_SHIFT), I2C_C2_HDRS_SHIFT, I2C_C2_HDRS_WIDTH))
7858 /*@}*/
7859 
7860 /*!
7861  * @name Register I2C_C2, field ADEXT[6] (RW)
7862  *
7863  * Controls the number of bits used for the slave address.
7864  *
7865  * Values:
7866  * - 0b0 - 7-bit address scheme
7867  * - 0b1 - 10-bit address scheme
7868  */
7869 /*@{*/
7870 /*! @brief Read current value of the I2C_C2_ADEXT field. */
7871 #define I2C_RD_C2_ADEXT(base) ((I2C_C2_REG(base) & I2C_C2_ADEXT_MASK) >> I2C_C2_ADEXT_SHIFT)
7872 #define I2C_BRD_C2_ADEXT(base) (BME_UBFX8(&I2C_C2_REG(base), I2C_C2_ADEXT_SHIFT, I2C_C2_ADEXT_WIDTH))
7873 
7874 /*! @brief Set the ADEXT field to a new value. */
7875 #define I2C_WR_C2_ADEXT(base, value) (I2C_RMW_C2(base, I2C_C2_ADEXT_MASK, I2C_C2_ADEXT(value)))
7876 #define I2C_BWR_C2_ADEXT(base, value) (BME_BFI8(&I2C_C2_REG(base), ((uint8_t)(value) << I2C_C2_ADEXT_SHIFT), I2C_C2_ADEXT_SHIFT, I2C_C2_ADEXT_WIDTH))
7877 /*@}*/
7878 
7879 /*!
7880  * @name Register I2C_C2, field GCAEN[7] (RW)
7881  *
7882  * Enables general call address.
7883  *
7884  * Values:
7885  * - 0b0 - Disabled
7886  * - 0b1 - Enabled
7887  */
7888 /*@{*/
7889 /*! @brief Read current value of the I2C_C2_GCAEN field. */
7890 #define I2C_RD_C2_GCAEN(base) ((I2C_C2_REG(base) & I2C_C2_GCAEN_MASK) >> I2C_C2_GCAEN_SHIFT)
7891 #define I2C_BRD_C2_GCAEN(base) (BME_UBFX8(&I2C_C2_REG(base), I2C_C2_GCAEN_SHIFT, I2C_C2_GCAEN_WIDTH))
7892 
7893 /*! @brief Set the GCAEN field to a new value. */
7894 #define I2C_WR_C2_GCAEN(base, value) (I2C_RMW_C2(base, I2C_C2_GCAEN_MASK, I2C_C2_GCAEN(value)))
7895 #define I2C_BWR_C2_GCAEN(base, value) (BME_BFI8(&I2C_C2_REG(base), ((uint8_t)(value) << I2C_C2_GCAEN_SHIFT), I2C_C2_GCAEN_SHIFT, I2C_C2_GCAEN_WIDTH))
7896 /*@}*/
7897 
7898 /*******************************************************************************
7899  * I2C_FLT - I2C Programmable Input Glitch Filter Register
7900  ******************************************************************************/
7901 
7902 /*!
7903  * @brief I2C_FLT - I2C Programmable Input Glitch Filter Register (RW)
7904  *
7905  * Reset value: 0x00U
7906  */
7907 /*!
7908  * @name Constants and macros for entire I2C_FLT register
7909  */
7910 /*@{*/
7911 #define I2C_RD_FLT(base)         (I2C_FLT_REG(base))
7912 #define I2C_WR_FLT(base, value)  (I2C_FLT_REG(base) = (value))
7913 #define I2C_RMW_FLT(base, mask, value) (I2C_WR_FLT(base, (I2C_RD_FLT(base) & ~(mask)) | (value)))
7914 #define I2C_SET_FLT(base, value) (BME_OR8(&I2C_FLT_REG(base), (uint8_t)(value)))
7915 #define I2C_CLR_FLT(base, value) (BME_AND8(&I2C_FLT_REG(base), (uint8_t)(~(value))))
7916 #define I2C_TOG_FLT(base, value) (BME_XOR8(&I2C_FLT_REG(base), (uint8_t)(value)))
7917 /*@}*/
7918 
7919 /*
7920  * Constants & macros for individual I2C_FLT bitfields
7921  */
7922 
7923 /*!
7924  * @name Register I2C_FLT, field FLT[3:0] (RW)
7925  *
7926  * Controls the width of the glitch, in terms of I2C module clock cycles, that
7927  * the filter must absorb. For any glitch whose size is less than or equal to this
7928  * width setting, the filter does not allow the glitch to pass. The width of the
7929  * FLT is an integration option that can be changed in different SoCs. Also the
7930  * clock source used is an integration/configuration option: it could be the 2*
7931  * IPBus clock or the IPBus clock -- which must be identified at architectural
7932  * definition. For the sample 4-bit definitions, the description of "half" IPBUS
7933  * clock cycles does not apply when the IPBUS clock is used for filtering logic.
7934  *
7935  * Values:
7936  * - 0b0000 - No filter/bypass
7937  */
7938 /*@{*/
7939 /*! @brief Read current value of the I2C_FLT_FLT field. */
7940 #define I2C_RD_FLT_FLT(base) ((I2C_FLT_REG(base) & I2C_FLT_FLT_MASK) >> I2C_FLT_FLT_SHIFT)
7941 #define I2C_BRD_FLT_FLT(base) (BME_UBFX8(&I2C_FLT_REG(base), I2C_FLT_FLT_SHIFT, I2C_FLT_FLT_WIDTH))
7942 
7943 /*! @brief Set the FLT field to a new value. */
7944 #define I2C_WR_FLT_FLT(base, value) (I2C_RMW_FLT(base, (I2C_FLT_FLT_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_FLT(value)))
7945 #define I2C_BWR_FLT_FLT(base, value) (BME_BFI8(&I2C_FLT_REG(base), ((uint8_t)(value) << I2C_FLT_FLT_SHIFT), I2C_FLT_FLT_SHIFT, I2C_FLT_FLT_WIDTH))
7946 /*@}*/
7947 
7948 /*!
7949  * @name Register I2C_FLT, field STARTF[4] (W1C)
7950  *
7951  * Hardware sets this bit when the I2C bus's start status is detected. The
7952  * STARTF bit must be cleared by writing 1 to it.
7953  *
7954  * Values:
7955  * - 0b0 - No start happens on I2C bus
7956  * - 0b1 - Start detected on I2C bus
7957  */
7958 /*@{*/
7959 /*! @brief Read current value of the I2C_FLT_STARTF field. */
7960 #define I2C_RD_FLT_STARTF(base) ((I2C_FLT_REG(base) & I2C_FLT_STARTF_MASK) >> I2C_FLT_STARTF_SHIFT)
7961 #define I2C_BRD_FLT_STARTF(base) (BME_UBFX8(&I2C_FLT_REG(base), I2C_FLT_STARTF_SHIFT, I2C_FLT_STARTF_WIDTH))
7962 
7963 /*! @brief Set the STARTF field to a new value. */
7964 #define I2C_WR_FLT_STARTF(base, value) (I2C_RMW_FLT(base, (I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_STARTF(value)))
7965 #define I2C_BWR_FLT_STARTF(base, value) (BME_BFI8(&I2C_FLT_REG(base), ((uint8_t)(value) << I2C_FLT_STARTF_SHIFT), I2C_FLT_STARTF_SHIFT, I2C_FLT_STARTF_WIDTH))
7966 /*@}*/
7967 
7968 /*!
7969  * @name Register I2C_FLT, field SSIE[5] (RW)
7970  *
7971  * This bit enables the interrupt for I2C bus stop or start detection. To clear
7972  * the I2C bus stop or start detection interrupt: In the interrupt service
7973  * routine, first clear the STOPF or STARTF bit by writing 1 to it, and then clear the
7974  * IICIF bit in the status register. If this sequence is reversed, the IICIF bit
7975  * is asserted again.
7976  *
7977  * Values:
7978  * - 0b0 - Stop or start detection interrupt is disabled
7979  * - 0b1 - Stop or start detection interrupt is enabled
7980  */
7981 /*@{*/
7982 /*! @brief Read current value of the I2C_FLT_SSIE field. */
7983 #define I2C_RD_FLT_SSIE(base) ((I2C_FLT_REG(base) & I2C_FLT_SSIE_MASK) >> I2C_FLT_SSIE_SHIFT)
7984 #define I2C_BRD_FLT_SSIE(base) (BME_UBFX8(&I2C_FLT_REG(base), I2C_FLT_SSIE_SHIFT, I2C_FLT_SSIE_WIDTH))
7985 
7986 /*! @brief Set the SSIE field to a new value. */
7987 #define I2C_WR_FLT_SSIE(base, value) (I2C_RMW_FLT(base, (I2C_FLT_SSIE_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_SSIE(value)))
7988 #define I2C_BWR_FLT_SSIE(base, value) (BME_BFI8(&I2C_FLT_REG(base), ((uint8_t)(value) << I2C_FLT_SSIE_SHIFT), I2C_FLT_SSIE_SHIFT, I2C_FLT_SSIE_WIDTH))
7989 /*@}*/
7990 
7991 /*!
7992  * @name Register I2C_FLT, field STOPF[6] (W1C)
7993  *
7994  * Hardware sets this bit when the I2C bus's stop status is detected. The STOPF
7995  * bit must be cleared by writing 1 to it.
7996  *
7997  * Values:
7998  * - 0b0 - No stop happens on I2C bus
7999  * - 0b1 - Stop detected on I2C bus
8000  */
8001 /*@{*/
8002 /*! @brief Read current value of the I2C_FLT_STOPF field. */
8003 #define I2C_RD_FLT_STOPF(base) ((I2C_FLT_REG(base) & I2C_FLT_STOPF_MASK) >> I2C_FLT_STOPF_SHIFT)
8004 #define I2C_BRD_FLT_STOPF(base) (BME_UBFX8(&I2C_FLT_REG(base), I2C_FLT_STOPF_SHIFT, I2C_FLT_STOPF_WIDTH))
8005 
8006 /*! @brief Set the STOPF field to a new value. */
8007 #define I2C_WR_FLT_STOPF(base, value) (I2C_RMW_FLT(base, (I2C_FLT_STOPF_MASK | I2C_FLT_STARTF_MASK), I2C_FLT_STOPF(value)))
8008 #define I2C_BWR_FLT_STOPF(base, value) (BME_BFI8(&I2C_FLT_REG(base), ((uint8_t)(value) << I2C_FLT_STOPF_SHIFT), I2C_FLT_STOPF_SHIFT, I2C_FLT_STOPF_WIDTH))
8009 /*@}*/
8010 
8011 /*!
8012  * @name Register I2C_FLT, field SHEN[7] (RW)
8013  *
8014  * Set this bit to hold off entry to stop mode when any data transmission or
8015  * reception is occurring. The following scenario explains the holdoff
8016  * functionality: The I2C module is configured for a basic transfer, and the SHEN bit is set
8017  * to 1. A transfer begins. The MCU signals the I2C module to enter stop mode. The
8018  * byte currently being transferred, including both address and data, completes
8019  * its transfer. The I2C slave or master acknowledges that the in-transfer byte
8020  * completed its transfer and acknowledges the request to enter stop mode. After
8021  * receiving the I2C module's acknowledgment of the request to enter stop mode,
8022  * the MCU determines whether to shut off the I2C module's clock. If the SHEN bit
8023  * is set to 1 and the I2C module is in an idle or disabled state when the MCU
8024  * signals to enter stop mode, the module immediately acknowledges the request to
8025  * enter stop mode. If SHEN is cleared to 0 and the overall data transmission or
8026  * reception that was suspended by stop mode entry was incomplete: To resume the
8027  * overall transmission or reception after the MCU exits stop mode, software must
8028  * reinitialize the transfer by resending the address of the slave. If the I2C
8029  * Control Register 1's IICIE bit was set to 1 before the MCU entered stop mode,
8030  * system software will receive the interrupt triggered by the I2C Status Register's
8031  * TCF bit after the MCU wakes from the stop mode.
8032  *
8033  * Values:
8034  * - 0b0 - Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
8035  *     Clocks to peripherals are gated when the core stop occurs.
8036  * - 0b1 - Stop holdoff is enabled. Stop mode entry is gated until the current
8037  *     transaction phase is complete, and the IP enters stop mode (clocks are
8038  *     gated) after the current phase's completion. That is to say: If the system
8039  *     stop request occurs between the address or data phase, the stop acknowledge
8040  *     is asserted after the current byte and IIC ack completion (after the
8041  *     acknowledge in the ninth cycle).
8042  */
8043 /*@{*/
8044 /*! @brief Read current value of the I2C_FLT_SHEN field. */
8045 #define I2C_RD_FLT_SHEN(base) ((I2C_FLT_REG(base) & I2C_FLT_SHEN_MASK) >> I2C_FLT_SHEN_SHIFT)
8046 #define I2C_BRD_FLT_SHEN(base) (BME_UBFX8(&I2C_FLT_REG(base), I2C_FLT_SHEN_SHIFT, I2C_FLT_SHEN_WIDTH))
8047 
8048 /*! @brief Set the SHEN field to a new value. */
8049 #define I2C_WR_FLT_SHEN(base, value) (I2C_RMW_FLT(base, (I2C_FLT_SHEN_MASK | I2C_FLT_STARTF_MASK | I2C_FLT_STOPF_MASK), I2C_FLT_SHEN(value)))
8050 #define I2C_BWR_FLT_SHEN(base, value) (BME_BFI8(&I2C_FLT_REG(base), ((uint8_t)(value) << I2C_FLT_SHEN_SHIFT), I2C_FLT_SHEN_SHIFT, I2C_FLT_SHEN_WIDTH))
8051 /*@}*/
8052 
8053 /*******************************************************************************
8054  * I2C_RA - I2C Range Address register
8055  ******************************************************************************/
8056 
8057 /*!
8058  * @brief I2C_RA - I2C Range Address register (RW)
8059  *
8060  * Reset value: 0x00U
8061  */
8062 /*!
8063  * @name Constants and macros for entire I2C_RA register
8064  */
8065 /*@{*/
8066 #define I2C_RD_RA(base)          (I2C_RA_REG(base))
8067 #define I2C_WR_RA(base, value)   (I2C_RA_REG(base) = (value))
8068 #define I2C_RMW_RA(base, mask, value) (I2C_WR_RA(base, (I2C_RD_RA(base) & ~(mask)) | (value)))
8069 #define I2C_SET_RA(base, value)  (BME_OR8(&I2C_RA_REG(base), (uint8_t)(value)))
8070 #define I2C_CLR_RA(base, value)  (BME_AND8(&I2C_RA_REG(base), (uint8_t)(~(value))))
8071 #define I2C_TOG_RA(base, value)  (BME_XOR8(&I2C_RA_REG(base), (uint8_t)(value)))
8072 /*@}*/
8073 
8074 /*
8075  * Constants & macros for individual I2C_RA bitfields
8076  */
8077 
8078 /*!
8079  * @name Register I2C_RA, field RAD[7:1] (RW)
8080  *
8081  * This field contains the slave address to be used by the I2C module. The field
8082  * is used in the 7-bit address scheme. If I2C_C2[RMEN] is set to 1, any nonzero
8083  * value write enables this register. This register value can be considered as a
8084  * maximum boundary in the range matching mode.
8085  */
8086 /*@{*/
8087 /*! @brief Read current value of the I2C_RA_RAD field. */
8088 #define I2C_RD_RA_RAD(base)  ((I2C_RA_REG(base) & I2C_RA_RAD_MASK) >> I2C_RA_RAD_SHIFT)
8089 #define I2C_BRD_RA_RAD(base) (BME_UBFX8(&I2C_RA_REG(base), I2C_RA_RAD_SHIFT, I2C_RA_RAD_WIDTH))
8090 
8091 /*! @brief Set the RAD field to a new value. */
8092 #define I2C_WR_RA_RAD(base, value) (I2C_RMW_RA(base, I2C_RA_RAD_MASK, I2C_RA_RAD(value)))
8093 #define I2C_BWR_RA_RAD(base, value) (BME_BFI8(&I2C_RA_REG(base), ((uint8_t)(value) << I2C_RA_RAD_SHIFT), I2C_RA_RAD_SHIFT, I2C_RA_RAD_WIDTH))
8094 /*@}*/
8095 
8096 /*******************************************************************************
8097  * I2C_SMB - I2C SMBus Control and Status register
8098  ******************************************************************************/
8099 
8100 /*!
8101  * @brief I2C_SMB - I2C SMBus Control and Status register (RW)
8102  *
8103  * Reset value: 0x00U
8104  *
8105  * When the SCL and SDA signals are held high for a length of time greater than
8106  * the high timeout period, the SHTF1 flag sets. Before reaching this threshold,
8107  * while the system is detecting how long these signals are being held high, a
8108  * master assumes that the bus is free. However, the SHTF1 bit is set to 1 in the
8109  * bus transmission process with the idle bus state. When the TCKSEL bit is set,
8110  * there is no need to monitor the SHTF1 bit because the bus speed is too high to
8111  * match the protocol of SMBus.
8112  */
8113 /*!
8114  * @name Constants and macros for entire I2C_SMB register
8115  */
8116 /*@{*/
8117 #define I2C_RD_SMB(base)         (I2C_SMB_REG(base))
8118 #define I2C_WR_SMB(base, value)  (I2C_SMB_REG(base) = (value))
8119 #define I2C_RMW_SMB(base, mask, value) (I2C_WR_SMB(base, (I2C_RD_SMB(base) & ~(mask)) | (value)))
8120 #define I2C_SET_SMB(base, value) (BME_OR8(&I2C_SMB_REG(base), (uint8_t)(value)))
8121 #define I2C_CLR_SMB(base, value) (BME_AND8(&I2C_SMB_REG(base), (uint8_t)(~(value))))
8122 #define I2C_TOG_SMB(base, value) (BME_XOR8(&I2C_SMB_REG(base), (uint8_t)(value)))
8123 /*@}*/
8124 
8125 /*
8126  * Constants & macros for individual I2C_SMB bitfields
8127  */
8128 
8129 /*!
8130  * @name Register I2C_SMB, field SHTF2IE[0] (RW)
8131  *
8132  * Enables SCL high and SDA low timeout interrupt.
8133  *
8134  * Values:
8135  * - 0b0 - SHTF2 interrupt is disabled
8136  * - 0b1 - SHTF2 interrupt is enabled
8137  */
8138 /*@{*/
8139 /*! @brief Read current value of the I2C_SMB_SHTF2IE field. */
8140 #define I2C_RD_SMB_SHTF2IE(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF2IE_MASK) >> I2C_SMB_SHTF2IE_SHIFT)
8141 #define I2C_BRD_SMB_SHTF2IE(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_SHTF2IE_SHIFT, I2C_SMB_SHTF2IE_WIDTH))
8142 
8143 /*! @brief Set the SHTF2IE field to a new value. */
8144 #define I2C_WR_SMB_SHTF2IE(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SHTF2IE_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SHTF2IE(value)))
8145 #define I2C_BWR_SMB_SHTF2IE(base, value) (BME_BFI8(&I2C_SMB_REG(base), ((uint8_t)(value) << I2C_SMB_SHTF2IE_SHIFT), I2C_SMB_SHTF2IE_SHIFT, I2C_SMB_SHTF2IE_WIDTH))
8146 /*@}*/
8147 
8148 /*!
8149  * @name Register I2C_SMB, field SHTF2[1] (W1C)
8150  *
8151  * This bit sets when SCL is held high and SDA is held low more than clock *
8152  * LoValue / 512. Software clears this bit by writing 1 to it.
8153  *
8154  * Values:
8155  * - 0b0 - No SCL high and SDA low timeout occurs
8156  * - 0b1 - SCL high and SDA low timeout occurs
8157  */
8158 /*@{*/
8159 /*! @brief Read current value of the I2C_SMB_SHTF2 field. */
8160 #define I2C_RD_SMB_SHTF2(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF2_MASK) >> I2C_SMB_SHTF2_SHIFT)
8161 #define I2C_BRD_SMB_SHTF2(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_SHTF2_SHIFT, I2C_SMB_SHTF2_WIDTH))
8162 
8163 /*! @brief Set the SHTF2 field to a new value. */
8164 #define I2C_WR_SMB_SHTF2(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SHTF2(value)))
8165 #define I2C_BWR_SMB_SHTF2(base, value) (BME_BFI8(&I2C_SMB_REG(base), ((uint8_t)(value) << I2C_SMB_SHTF2_SHIFT), I2C_SMB_SHTF2_SHIFT, I2C_SMB_SHTF2_WIDTH))
8166 /*@}*/
8167 
8168 /*!
8169  * @name Register I2C_SMB, field SHTF1[2] (RO)
8170  *
8171  * This read-only bit sets when SCL and SDA are held high more than clock *
8172  * LoValue / 512, which indicates the bus is free. This bit is cleared automatically.
8173  *
8174  * Values:
8175  * - 0b0 - No SCL high and SDA high timeout occurs
8176  * - 0b1 - SCL high and SDA high timeout occurs
8177  */
8178 /*@{*/
8179 /*! @brief Read current value of the I2C_SMB_SHTF1 field. */
8180 #define I2C_RD_SMB_SHTF1(base) ((I2C_SMB_REG(base) & I2C_SMB_SHTF1_MASK) >> I2C_SMB_SHTF1_SHIFT)
8181 #define I2C_BRD_SMB_SHTF1(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_SHTF1_SHIFT, I2C_SMB_SHTF1_WIDTH))
8182 /*@}*/
8183 
8184 /*!
8185  * @name Register I2C_SMB, field SLTF[3] (W1C)
8186  *
8187  * This bit is set when the SLT register (consisting of the SLTH and SLTL
8188  * registers) is loaded with a non-zero value (LoValue) and an SCL low timeout occurs.
8189  * Software clears this bit by writing a logic 1 to it. The low timeout function
8190  * is disabled when the SLT register's value is 0.
8191  *
8192  * Values:
8193  * - 0b0 - No low timeout occurs
8194  * - 0b1 - Low timeout occurs
8195  */
8196 /*@{*/
8197 /*! @brief Read current value of the I2C_SMB_SLTF field. */
8198 #define I2C_RD_SMB_SLTF(base) ((I2C_SMB_REG(base) & I2C_SMB_SLTF_MASK) >> I2C_SMB_SLTF_SHIFT)
8199 #define I2C_BRD_SMB_SLTF(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_SLTF_SHIFT, I2C_SMB_SLTF_WIDTH))
8200 
8201 /*! @brief Set the SLTF field to a new value. */
8202 #define I2C_WR_SMB_SLTF(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SLTF_MASK | I2C_SMB_SHTF2_MASK), I2C_SMB_SLTF(value)))
8203 #define I2C_BWR_SMB_SLTF(base, value) (BME_BFI8(&I2C_SMB_REG(base), ((uint8_t)(value) << I2C_SMB_SLTF_SHIFT), I2C_SMB_SLTF_SHIFT, I2C_SMB_SLTF_WIDTH))
8204 /*@}*/
8205 
8206 /*!
8207  * @name Register I2C_SMB, field TCKSEL[4] (RW)
8208  *
8209  * Selects the clock source of the timeout counter.
8210  *
8211  * Values:
8212  * - 0b0 - Timeout counter counts at the frequency of the I2C module clock / 64
8213  * - 0b1 - Timeout counter counts at the frequency of the I2C module clock
8214  */
8215 /*@{*/
8216 /*! @brief Read current value of the I2C_SMB_TCKSEL field. */
8217 #define I2C_RD_SMB_TCKSEL(base) ((I2C_SMB_REG(base) & I2C_SMB_TCKSEL_MASK) >> I2C_SMB_TCKSEL_SHIFT)
8218 #define I2C_BRD_SMB_TCKSEL(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_TCKSEL_SHIFT, I2C_SMB_TCKSEL_WIDTH))
8219 
8220 /*! @brief Set the TCKSEL field to a new value. */
8221 #define I2C_WR_SMB_TCKSEL(base, value) (I2C_RMW_SMB(base, (I2C_SMB_TCKSEL_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_TCKSEL(value)))
8222 #define I2C_BWR_SMB_TCKSEL(base, value) (BME_BFI8(&I2C_SMB_REG(base), ((uint8_t)(value) << I2C_SMB_TCKSEL_SHIFT), I2C_SMB_TCKSEL_SHIFT, I2C_SMB_TCKSEL_WIDTH))
8223 /*@}*/
8224 
8225 /*!
8226  * @name Register I2C_SMB, field SIICAEN[5] (RW)
8227  *
8228  * Enables or disables SMBus device default address.
8229  *
8230  * Values:
8231  * - 0b0 - I2C address register 2 matching is disabled
8232  * - 0b1 - I2C address register 2 matching is enabled
8233  */
8234 /*@{*/
8235 /*! @brief Read current value of the I2C_SMB_SIICAEN field. */
8236 #define I2C_RD_SMB_SIICAEN(base) ((I2C_SMB_REG(base) & I2C_SMB_SIICAEN_MASK) >> I2C_SMB_SIICAEN_SHIFT)
8237 #define I2C_BRD_SMB_SIICAEN(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_SIICAEN_SHIFT, I2C_SMB_SIICAEN_WIDTH))
8238 
8239 /*! @brief Set the SIICAEN field to a new value. */
8240 #define I2C_WR_SMB_SIICAEN(base, value) (I2C_RMW_SMB(base, (I2C_SMB_SIICAEN_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_SIICAEN(value)))
8241 #define I2C_BWR_SMB_SIICAEN(base, value) (BME_BFI8(&I2C_SMB_REG(base), ((uint8_t)(value) << I2C_SMB_SIICAEN_SHIFT), I2C_SMB_SIICAEN_SHIFT, I2C_SMB_SIICAEN_WIDTH))
8242 /*@}*/
8243 
8244 /*!
8245  * @name Register I2C_SMB, field ALERTEN[6] (RW)
8246  *
8247  * Enables or disables SMBus alert response address matching. After the host
8248  * responds to a device that used the alert response address, you must use software
8249  * to put the device's address on the bus. The alert protocol is described in the
8250  * SMBus specification.
8251  *
8252  * Values:
8253  * - 0b0 - SMBus alert response address matching is disabled
8254  * - 0b1 - SMBus alert response address matching is enabled
8255  */
8256 /*@{*/
8257 /*! @brief Read current value of the I2C_SMB_ALERTEN field. */
8258 #define I2C_RD_SMB_ALERTEN(base) ((I2C_SMB_REG(base) & I2C_SMB_ALERTEN_MASK) >> I2C_SMB_ALERTEN_SHIFT)
8259 #define I2C_BRD_SMB_ALERTEN(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_ALERTEN_SHIFT, I2C_SMB_ALERTEN_WIDTH))
8260 
8261 /*! @brief Set the ALERTEN field to a new value. */
8262 #define I2C_WR_SMB_ALERTEN(base, value) (I2C_RMW_SMB(base, (I2C_SMB_ALERTEN_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_ALERTEN(value)))
8263 #define I2C_BWR_SMB_ALERTEN(base, value) (BME_BFI8(&I2C_SMB_REG(base), ((uint8_t)(value) << I2C_SMB_ALERTEN_SHIFT), I2C_SMB_ALERTEN_SHIFT, I2C_SMB_ALERTEN_WIDTH))
8264 /*@}*/
8265 
8266 /*!
8267  * @name Register I2C_SMB, field FACK[7] (RW)
8268  *
8269  * For SMBus packet error checking, the CPU must be able to issue an ACK or NACK
8270  * according to the result of receiving data byte.
8271  *
8272  * Values:
8273  * - 0b0 - An ACK or NACK is sent on the following receiving data byte
8274  * - 0b1 - Writing 0 to TXAK after receiving a data byte generates an ACK.
8275  *     Writing 1 to TXAK after receiving a data byte generates a NACK.
8276  */
8277 /*@{*/
8278 /*! @brief Read current value of the I2C_SMB_FACK field. */
8279 #define I2C_RD_SMB_FACK(base) ((I2C_SMB_REG(base) & I2C_SMB_FACK_MASK) >> I2C_SMB_FACK_SHIFT)
8280 #define I2C_BRD_SMB_FACK(base) (BME_UBFX8(&I2C_SMB_REG(base), I2C_SMB_FACK_SHIFT, I2C_SMB_FACK_WIDTH))
8281 
8282 /*! @brief Set the FACK field to a new value. */
8283 #define I2C_WR_SMB_FACK(base, value) (I2C_RMW_SMB(base, (I2C_SMB_FACK_MASK | I2C_SMB_SHTF2_MASK | I2C_SMB_SLTF_MASK), I2C_SMB_FACK(value)))
8284 #define I2C_BWR_SMB_FACK(base, value) (BME_BFI8(&I2C_SMB_REG(base), ((uint8_t)(value) << I2C_SMB_FACK_SHIFT), I2C_SMB_FACK_SHIFT, I2C_SMB_FACK_WIDTH))
8285 /*@}*/
8286 
8287 /*******************************************************************************
8288  * I2C_A2 - I2C Address Register 2
8289  ******************************************************************************/
8290 
8291 /*!
8292  * @brief I2C_A2 - I2C Address Register 2 (RW)
8293  *
8294  * Reset value: 0xC2U
8295  */
8296 /*!
8297  * @name Constants and macros for entire I2C_A2 register
8298  */
8299 /*@{*/
8300 #define I2C_RD_A2(base)          (I2C_A2_REG(base))
8301 #define I2C_WR_A2(base, value)   (I2C_A2_REG(base) = (value))
8302 #define I2C_RMW_A2(base, mask, value) (I2C_WR_A2(base, (I2C_RD_A2(base) & ~(mask)) | (value)))
8303 #define I2C_SET_A2(base, value)  (BME_OR8(&I2C_A2_REG(base), (uint8_t)(value)))
8304 #define I2C_CLR_A2(base, value)  (BME_AND8(&I2C_A2_REG(base), (uint8_t)(~(value))))
8305 #define I2C_TOG_A2(base, value)  (BME_XOR8(&I2C_A2_REG(base), (uint8_t)(value)))
8306 /*@}*/
8307 
8308 /*
8309  * Constants & macros for individual I2C_A2 bitfields
8310  */
8311 
8312 /*!
8313  * @name Register I2C_A2, field SAD[7:1] (RW)
8314  *
8315  * Contains the slave address used by the SMBus. This field is used on the
8316  * device default address or other related addresses.
8317  */
8318 /*@{*/
8319 /*! @brief Read current value of the I2C_A2_SAD field. */
8320 #define I2C_RD_A2_SAD(base)  ((I2C_A2_REG(base) & I2C_A2_SAD_MASK) >> I2C_A2_SAD_SHIFT)
8321 #define I2C_BRD_A2_SAD(base) (BME_UBFX8(&I2C_A2_REG(base), I2C_A2_SAD_SHIFT, I2C_A2_SAD_WIDTH))
8322 
8323 /*! @brief Set the SAD field to a new value. */
8324 #define I2C_WR_A2_SAD(base, value) (I2C_RMW_A2(base, I2C_A2_SAD_MASK, I2C_A2_SAD(value)))
8325 #define I2C_BWR_A2_SAD(base, value) (BME_BFI8(&I2C_A2_REG(base), ((uint8_t)(value) << I2C_A2_SAD_SHIFT), I2C_A2_SAD_SHIFT, I2C_A2_SAD_WIDTH))
8326 /*@}*/
8327 
8328 /*******************************************************************************
8329  * I2C_SLTH - I2C SCL Low Timeout Register High
8330  ******************************************************************************/
8331 
8332 /*!
8333  * @brief I2C_SLTH - I2C SCL Low Timeout Register High (RW)
8334  *
8335  * Reset value: 0x00U
8336  */
8337 /*!
8338  * @name Constants and macros for entire I2C_SLTH register
8339  */
8340 /*@{*/
8341 #define I2C_RD_SLTH(base)        (I2C_SLTH_REG(base))
8342 #define I2C_WR_SLTH(base, value) (I2C_SLTH_REG(base) = (value))
8343 #define I2C_RMW_SLTH(base, mask, value) (I2C_WR_SLTH(base, (I2C_RD_SLTH(base) & ~(mask)) | (value)))
8344 #define I2C_SET_SLTH(base, value) (BME_OR8(&I2C_SLTH_REG(base), (uint8_t)(value)))
8345 #define I2C_CLR_SLTH(base, value) (BME_AND8(&I2C_SLTH_REG(base), (uint8_t)(~(value))))
8346 #define I2C_TOG_SLTH(base, value) (BME_XOR8(&I2C_SLTH_REG(base), (uint8_t)(value)))
8347 /*@}*/
8348 
8349 /*******************************************************************************
8350  * I2C_SLTL - I2C SCL Low Timeout Register Low
8351  ******************************************************************************/
8352 
8353 /*!
8354  * @brief I2C_SLTL - I2C SCL Low Timeout Register Low (RW)
8355  *
8356  * Reset value: 0x00U
8357  */
8358 /*!
8359  * @name Constants and macros for entire I2C_SLTL register
8360  */
8361 /*@{*/
8362 #define I2C_RD_SLTL(base)        (I2C_SLTL_REG(base))
8363 #define I2C_WR_SLTL(base, value) (I2C_SLTL_REG(base) = (value))
8364 #define I2C_RMW_SLTL(base, mask, value) (I2C_WR_SLTL(base, (I2C_RD_SLTL(base) & ~(mask)) | (value)))
8365 #define I2C_SET_SLTL(base, value) (BME_OR8(&I2C_SLTL_REG(base), (uint8_t)(value)))
8366 #define I2C_CLR_SLTL(base, value) (BME_AND8(&I2C_SLTL_REG(base), (uint8_t)(~(value))))
8367 #define I2C_TOG_SLTL(base, value) (BME_XOR8(&I2C_SLTL_REG(base), (uint8_t)(value)))
8368 /*@}*/
8369 
8370 /*******************************************************************************
8371  * I2C_S2 - I2C Status register 2
8372  ******************************************************************************/
8373 
8374 /*!
8375  * @brief I2C_S2 - I2C Status register 2 (RW)
8376  *
8377  * Reset value: 0x01U
8378  */
8379 /*!
8380  * @name Constants and macros for entire I2C_S2 register
8381  */
8382 /*@{*/
8383 #define I2C_RD_S2(base)          (I2C_S2_REG(base))
8384 #define I2C_WR_S2(base, value)   (I2C_S2_REG(base) = (value))
8385 #define I2C_RMW_S2(base, mask, value) (I2C_WR_S2(base, (I2C_RD_S2(base) & ~(mask)) | (value)))
8386 #define I2C_SET_S2(base, value)  (BME_OR8(&I2C_S2_REG(base), (uint8_t)(value)))
8387 #define I2C_CLR_S2(base, value)  (BME_AND8(&I2C_S2_REG(base), (uint8_t)(~(value))))
8388 #define I2C_TOG_S2(base, value)  (BME_XOR8(&I2C_S2_REG(base), (uint8_t)(value)))
8389 /*@}*/
8390 
8391 /*
8392  * Constants & macros for individual I2C_S2 bitfields
8393  */
8394 
8395 /*!
8396  * @name Register I2C_S2, field EMPTY[0] (RO)
8397  *
8398  * Indicates if the Tx or Rx buffer is empty.
8399  *
8400  * Values:
8401  * - 0b0 - Tx or Rx buffer is not empty and cannot be written to, that is new
8402  *     data cannot be loaded into the buffer.
8403  * - 0b1 - Tx or Rx buffer is empty and can be written to, that is new data can
8404  *     be loaded into the buffer. Write 1 to reset this flag (to the default
8405  *     value 1, which means that the Tx or Rx buffer is empty).
8406  */
8407 /*@{*/
8408 /*! @brief Read current value of the I2C_S2_EMPTY field. */
8409 #define I2C_RD_S2_EMPTY(base) ((I2C_S2_REG(base) & I2C_S2_EMPTY_MASK) >> I2C_S2_EMPTY_SHIFT)
8410 #define I2C_BRD_S2_EMPTY(base) (BME_UBFX8(&I2C_S2_REG(base), I2C_S2_EMPTY_SHIFT, I2C_S2_EMPTY_WIDTH))
8411 /*@}*/
8412 
8413 /*!
8414  * @name Register I2C_S2, field ERROR[1] (W1C)
8415  *
8416  * Indicates if there are read or write errors with the Tx and Rx buffers.
8417  *
8418  * Values:
8419  * - 0b0 - The buffer is not full and all write/read operations have no errors.
8420  * - 0b1 - There are 3 or more write/read errors during the data transfer phase
8421  *     (when the Empty flag is not set and the buffer is busy).
8422  */
8423 /*@{*/
8424 /*! @brief Read current value of the I2C_S2_ERROR field. */
8425 #define I2C_RD_S2_ERROR(base) ((I2C_S2_REG(base) & I2C_S2_ERROR_MASK) >> I2C_S2_ERROR_SHIFT)
8426 #define I2C_BRD_S2_ERROR(base) (BME_UBFX8(&I2C_S2_REG(base), I2C_S2_ERROR_SHIFT, I2C_S2_ERROR_WIDTH))
8427 
8428 /*! @brief Set the ERROR field to a new value. */
8429 #define I2C_WR_S2_ERROR(base, value) (I2C_RMW_S2(base, I2C_S2_ERROR_MASK, I2C_S2_ERROR(value)))
8430 #define I2C_BWR_S2_ERROR(base, value) (BME_BFI8(&I2C_S2_REG(base), ((uint8_t)(value) << I2C_S2_ERROR_SHIFT), I2C_S2_ERROR_SHIFT, I2C_S2_ERROR_WIDTH))
8431 /*@}*/
8432 
8433 /*
8434  * MKW40Z4 LLWU
8435  *
8436  * Low leakage wakeup unit
8437  *
8438  * Registers defined in this header file:
8439  * - LLWU_PE1 - LLWU Pin Enable 1 register
8440  * - LLWU_PE2 - LLWU Pin Enable 2 register
8441  * - LLWU_PE3 - LLWU Pin Enable 3 register
8442  * - LLWU_PE4 - LLWU Pin Enable 4 register
8443  * - LLWU_ME - LLWU Module Enable register
8444  * - LLWU_F1 - LLWU Flag 1 register
8445  * - LLWU_F2 - LLWU Flag 2 register
8446  * - LLWU_F3 - LLWU Flag 3 register
8447  * - LLWU_FILT1 - LLWU Pin Filter 1 register
8448  * - LLWU_FILT2 - LLWU Pin Filter 2 register
8449  */
8450 
8451 #define LLWU_INSTANCE_COUNT (1U) /*!< Number of instances of the LLWU module. */
8452 #define LLWU_IDX (0U) /*!< Instance number for LLWU. */
8453 
8454 /*******************************************************************************
8455  * LLWU_PE1 - LLWU Pin Enable 1 register
8456  ******************************************************************************/
8457 
8458 /*!
8459  * @brief LLWU_PE1 - LLWU Pin Enable 1 register (RW)
8460  *
8461  * Reset value: 0x00U
8462  *
8463  * LLWU_PE1 contains the field to enable and select the edge detect type for the
8464  * external wakeup input pins LLWU_P3-LLWU_P0. This register is reset on Chip
8465  * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
8466  * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
8467  * IntroductionInformation found here describes the registers of the Reset Control Module
8468  * (RCM). The RCM implements many of the reset functions for the chip. See the
8469  * chip's reset chapter for more information. details for more information.
8470  */
8471 /*!
8472  * @name Constants and macros for entire LLWU_PE1 register
8473  */
8474 /*@{*/
8475 #define LLWU_RD_PE1(base)        (LLWU_PE1_REG(base))
8476 #define LLWU_WR_PE1(base, value) (LLWU_PE1_REG(base) = (value))
8477 #define LLWU_RMW_PE1(base, mask, value) (LLWU_WR_PE1(base, (LLWU_RD_PE1(base) & ~(mask)) | (value)))
8478 #define LLWU_SET_PE1(base, value) (BME_OR8(&LLWU_PE1_REG(base), (uint8_t)(value)))
8479 #define LLWU_CLR_PE1(base, value) (BME_AND8(&LLWU_PE1_REG(base), (uint8_t)(~(value))))
8480 #define LLWU_TOG_PE1(base, value) (BME_XOR8(&LLWU_PE1_REG(base), (uint8_t)(value)))
8481 /*@}*/
8482 
8483 /*
8484  * Constants & macros for individual LLWU_PE1 bitfields
8485  */
8486 
8487 /*!
8488  * @name Register LLWU_PE1, field WUPE0[1:0] (RW)
8489  *
8490  * Enables and configures the edge detection for the wakeup pin.
8491  *
8492  * Values:
8493  * - 0b00 - External input pin disabled as wakeup input
8494  * - 0b01 - External input pin enabled with rising edge detection
8495  * - 0b10 - External input pin enabled with falling edge detection
8496  * - 0b11 - External input pin enabled with any change detection
8497  */
8498 /*@{*/
8499 /*! @brief Read current value of the LLWU_PE1_WUPE0 field. */
8500 #define LLWU_RD_PE1_WUPE0(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE0_MASK) >> LLWU_PE1_WUPE0_SHIFT)
8501 #define LLWU_BRD_PE1_WUPE0(base) (BME_UBFX8(&LLWU_PE1_REG(base), LLWU_PE1_WUPE0_SHIFT, LLWU_PE1_WUPE0_WIDTH))
8502 
8503 /*! @brief Set the WUPE0 field to a new value. */
8504 #define LLWU_WR_PE1_WUPE0(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE0_MASK, LLWU_PE1_WUPE0(value)))
8505 #define LLWU_BWR_PE1_WUPE0(base, value) (BME_BFI8(&LLWU_PE1_REG(base), ((uint8_t)(value) << LLWU_PE1_WUPE0_SHIFT), LLWU_PE1_WUPE0_SHIFT, LLWU_PE1_WUPE0_WIDTH))
8506 /*@}*/
8507 
8508 /*!
8509  * @name Register LLWU_PE1, field WUPE1[3:2] (RW)
8510  *
8511  * Enables and configures the edge detection for the wakeup pin.
8512  *
8513  * Values:
8514  * - 0b00 - External input pin disabled as wakeup input
8515  * - 0b01 - External input pin enabled with rising edge detection
8516  * - 0b10 - External input pin enabled with falling edge detection
8517  * - 0b11 - External input pin enabled with any change detection
8518  */
8519 /*@{*/
8520 /*! @brief Read current value of the LLWU_PE1_WUPE1 field. */
8521 #define LLWU_RD_PE1_WUPE1(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE1_MASK) >> LLWU_PE1_WUPE1_SHIFT)
8522 #define LLWU_BRD_PE1_WUPE1(base) (BME_UBFX8(&LLWU_PE1_REG(base), LLWU_PE1_WUPE1_SHIFT, LLWU_PE1_WUPE1_WIDTH))
8523 
8524 /*! @brief Set the WUPE1 field to a new value. */
8525 #define LLWU_WR_PE1_WUPE1(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE1_MASK, LLWU_PE1_WUPE1(value)))
8526 #define LLWU_BWR_PE1_WUPE1(base, value) (BME_BFI8(&LLWU_PE1_REG(base), ((uint8_t)(value) << LLWU_PE1_WUPE1_SHIFT), LLWU_PE1_WUPE1_SHIFT, LLWU_PE1_WUPE1_WIDTH))
8527 /*@}*/
8528 
8529 /*!
8530  * @name Register LLWU_PE1, field WUPE2[5:4] (RW)
8531  *
8532  * Enables and configures the edge detection for the wakeup pin.
8533  *
8534  * Values:
8535  * - 0b00 - External input pin disabled as wakeup input
8536  * - 0b01 - External input pin enabled with rising edge detection
8537  * - 0b10 - External input pin enabled with falling edge detection
8538  * - 0b11 - External input pin enabled with any change detection
8539  */
8540 /*@{*/
8541 /*! @brief Read current value of the LLWU_PE1_WUPE2 field. */
8542 #define LLWU_RD_PE1_WUPE2(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE2_MASK) >> LLWU_PE1_WUPE2_SHIFT)
8543 #define LLWU_BRD_PE1_WUPE2(base) (BME_UBFX8(&LLWU_PE1_REG(base), LLWU_PE1_WUPE2_SHIFT, LLWU_PE1_WUPE2_WIDTH))
8544 
8545 /*! @brief Set the WUPE2 field to a new value. */
8546 #define LLWU_WR_PE1_WUPE2(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE2_MASK, LLWU_PE1_WUPE2(value)))
8547 #define LLWU_BWR_PE1_WUPE2(base, value) (BME_BFI8(&LLWU_PE1_REG(base), ((uint8_t)(value) << LLWU_PE1_WUPE2_SHIFT), LLWU_PE1_WUPE2_SHIFT, LLWU_PE1_WUPE2_WIDTH))
8548 /*@}*/
8549 
8550 /*!
8551  * @name Register LLWU_PE1, field WUPE3[7:6] (RW)
8552  *
8553  * Enables and configures the edge detection for the wakeup pin.
8554  *
8555  * Values:
8556  * - 0b00 - External input pin disabled as wakeup input
8557  * - 0b01 - External input pin enabled with rising edge detection
8558  * - 0b10 - External input pin enabled with falling edge detection
8559  * - 0b11 - External input pin enabled with any change detection
8560  */
8561 /*@{*/
8562 /*! @brief Read current value of the LLWU_PE1_WUPE3 field. */
8563 #define LLWU_RD_PE1_WUPE3(base) ((LLWU_PE1_REG(base) & LLWU_PE1_WUPE3_MASK) >> LLWU_PE1_WUPE3_SHIFT)
8564 #define LLWU_BRD_PE1_WUPE3(base) (BME_UBFX8(&LLWU_PE1_REG(base), LLWU_PE1_WUPE3_SHIFT, LLWU_PE1_WUPE3_WIDTH))
8565 
8566 /*! @brief Set the WUPE3 field to a new value. */
8567 #define LLWU_WR_PE1_WUPE3(base, value) (LLWU_RMW_PE1(base, LLWU_PE1_WUPE3_MASK, LLWU_PE1_WUPE3(value)))
8568 #define LLWU_BWR_PE1_WUPE3(base, value) (BME_BFI8(&LLWU_PE1_REG(base), ((uint8_t)(value) << LLWU_PE1_WUPE3_SHIFT), LLWU_PE1_WUPE3_SHIFT, LLWU_PE1_WUPE3_WIDTH))
8569 /*@}*/
8570 
8571 /*******************************************************************************
8572  * LLWU_PE2 - LLWU Pin Enable 2 register
8573  ******************************************************************************/
8574 
8575 /*!
8576  * @brief LLWU_PE2 - LLWU Pin Enable 2 register (RW)
8577  *
8578  * Reset value: 0x00U
8579  *
8580  * LLWU_PE2 contains the field to enable and select the edge detect type for the
8581  * external wakeup input pins LLWU_P7-LLWU_P4. This register is reset on Chip
8582  * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
8583  * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
8584  * IntroductionInformation found here describes the registers of the Reset Control Module
8585  * (RCM). The RCM implements many of the reset functions for the chip. See the
8586  * chip's reset chapter for more information. details for more information.
8587  */
8588 /*!
8589  * @name Constants and macros for entire LLWU_PE2 register
8590  */
8591 /*@{*/
8592 #define LLWU_RD_PE2(base)        (LLWU_PE2_REG(base))
8593 #define LLWU_WR_PE2(base, value) (LLWU_PE2_REG(base) = (value))
8594 #define LLWU_RMW_PE2(base, mask, value) (LLWU_WR_PE2(base, (LLWU_RD_PE2(base) & ~(mask)) | (value)))
8595 #define LLWU_SET_PE2(base, value) (BME_OR8(&LLWU_PE2_REG(base), (uint8_t)(value)))
8596 #define LLWU_CLR_PE2(base, value) (BME_AND8(&LLWU_PE2_REG(base), (uint8_t)(~(value))))
8597 #define LLWU_TOG_PE2(base, value) (BME_XOR8(&LLWU_PE2_REG(base), (uint8_t)(value)))
8598 /*@}*/
8599 
8600 /*
8601  * Constants & macros for individual LLWU_PE2 bitfields
8602  */
8603 
8604 /*!
8605  * @name Register LLWU_PE2, field WUPE4[1:0] (RW)
8606  *
8607  * Enables and configures the edge detection for the wakeup pin.
8608  *
8609  * Values:
8610  * - 0b00 - External input pin disabled as wakeup input
8611  * - 0b01 - External input pin enabled with rising edge detection
8612  * - 0b10 - External input pin enabled with falling edge detection
8613  * - 0b11 - External input pin enabled with any change detection
8614  */
8615 /*@{*/
8616 /*! @brief Read current value of the LLWU_PE2_WUPE4 field. */
8617 #define LLWU_RD_PE2_WUPE4(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE4_MASK) >> LLWU_PE2_WUPE4_SHIFT)
8618 #define LLWU_BRD_PE2_WUPE4(base) (BME_UBFX8(&LLWU_PE2_REG(base), LLWU_PE2_WUPE4_SHIFT, LLWU_PE2_WUPE4_WIDTH))
8619 
8620 /*! @brief Set the WUPE4 field to a new value. */
8621 #define LLWU_WR_PE2_WUPE4(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE4_MASK, LLWU_PE2_WUPE4(value)))
8622 #define LLWU_BWR_PE2_WUPE4(base, value) (BME_BFI8(&LLWU_PE2_REG(base), ((uint8_t)(value) << LLWU_PE2_WUPE4_SHIFT), LLWU_PE2_WUPE4_SHIFT, LLWU_PE2_WUPE4_WIDTH))
8623 /*@}*/
8624 
8625 /*!
8626  * @name Register LLWU_PE2, field WUPE5[3:2] (RW)
8627  *
8628  * Enables and configures the edge detection for the wakeup pin.
8629  *
8630  * Values:
8631  * - 0b00 - External input pin disabled as wakeup input
8632  * - 0b01 - External input pin enabled with rising edge detection
8633  * - 0b10 - External input pin enabled with falling edge detection
8634  * - 0b11 - External input pin enabled with any change detection
8635  */
8636 /*@{*/
8637 /*! @brief Read current value of the LLWU_PE2_WUPE5 field. */
8638 #define LLWU_RD_PE2_WUPE5(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE5_MASK) >> LLWU_PE2_WUPE5_SHIFT)
8639 #define LLWU_BRD_PE2_WUPE5(base) (BME_UBFX8(&LLWU_PE2_REG(base), LLWU_PE2_WUPE5_SHIFT, LLWU_PE2_WUPE5_WIDTH))
8640 
8641 /*! @brief Set the WUPE5 field to a new value. */
8642 #define LLWU_WR_PE2_WUPE5(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE5_MASK, LLWU_PE2_WUPE5(value)))
8643 #define LLWU_BWR_PE2_WUPE5(base, value) (BME_BFI8(&LLWU_PE2_REG(base), ((uint8_t)(value) << LLWU_PE2_WUPE5_SHIFT), LLWU_PE2_WUPE5_SHIFT, LLWU_PE2_WUPE5_WIDTH))
8644 /*@}*/
8645 
8646 /*!
8647  * @name Register LLWU_PE2, field WUPE6[5:4] (RW)
8648  *
8649  * Enables and configures the edge detection for the wakeup pin.
8650  *
8651  * Values:
8652  * - 0b00 - External input pin disabled as wakeup input
8653  * - 0b01 - External input pin enabled with rising edge detection
8654  * - 0b10 - External input pin enabled with falling edge detection
8655  * - 0b11 - External input pin enabled with any change detection
8656  */
8657 /*@{*/
8658 /*! @brief Read current value of the LLWU_PE2_WUPE6 field. */
8659 #define LLWU_RD_PE2_WUPE6(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE6_MASK) >> LLWU_PE2_WUPE6_SHIFT)
8660 #define LLWU_BRD_PE2_WUPE6(base) (BME_UBFX8(&LLWU_PE2_REG(base), LLWU_PE2_WUPE6_SHIFT, LLWU_PE2_WUPE6_WIDTH))
8661 
8662 /*! @brief Set the WUPE6 field to a new value. */
8663 #define LLWU_WR_PE2_WUPE6(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE6_MASK, LLWU_PE2_WUPE6(value)))
8664 #define LLWU_BWR_PE2_WUPE6(base, value) (BME_BFI8(&LLWU_PE2_REG(base), ((uint8_t)(value) << LLWU_PE2_WUPE6_SHIFT), LLWU_PE2_WUPE6_SHIFT, LLWU_PE2_WUPE6_WIDTH))
8665 /*@}*/
8666 
8667 /*!
8668  * @name Register LLWU_PE2, field WUPE7[7:6] (RW)
8669  *
8670  * Enables and configures the edge detection for the wakeup pin.
8671  *
8672  * Values:
8673  * - 0b00 - External input pin disabled as wakeup input
8674  * - 0b01 - External input pin enabled with rising edge detection
8675  * - 0b10 - External input pin enabled with falling edge detection
8676  * - 0b11 - External input pin enabled with any change detection
8677  */
8678 /*@{*/
8679 /*! @brief Read current value of the LLWU_PE2_WUPE7 field. */
8680 #define LLWU_RD_PE2_WUPE7(base) ((LLWU_PE2_REG(base) & LLWU_PE2_WUPE7_MASK) >> LLWU_PE2_WUPE7_SHIFT)
8681 #define LLWU_BRD_PE2_WUPE7(base) (BME_UBFX8(&LLWU_PE2_REG(base), LLWU_PE2_WUPE7_SHIFT, LLWU_PE2_WUPE7_WIDTH))
8682 
8683 /*! @brief Set the WUPE7 field to a new value. */
8684 #define LLWU_WR_PE2_WUPE7(base, value) (LLWU_RMW_PE2(base, LLWU_PE2_WUPE7_MASK, LLWU_PE2_WUPE7(value)))
8685 #define LLWU_BWR_PE2_WUPE7(base, value) (BME_BFI8(&LLWU_PE2_REG(base), ((uint8_t)(value) << LLWU_PE2_WUPE7_SHIFT), LLWU_PE2_WUPE7_SHIFT, LLWU_PE2_WUPE7_WIDTH))
8686 /*@}*/
8687 
8688 /*******************************************************************************
8689  * LLWU_PE3 - LLWU Pin Enable 3 register
8690  ******************************************************************************/
8691 
8692 /*!
8693  * @brief LLWU_PE3 - LLWU Pin Enable 3 register (RW)
8694  *
8695  * Reset value: 0x00U
8696  *
8697  * LLWU_PE3 contains the field to enable and select the edge detect type for the
8698  * external wakeup input pins LLWU_P11-LLWU_P8. This register is reset on Chip
8699  * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
8700  * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
8701  * IntroductionInformation found here describes the registers of the Reset Control Module
8702  * (RCM). The RCM implements many of the reset functions for the chip. See the
8703  * chip's reset chapter for more information. details for more information.
8704  */
8705 /*!
8706  * @name Constants and macros for entire LLWU_PE3 register
8707  */
8708 /*@{*/
8709 #define LLWU_RD_PE3(base)        (LLWU_PE3_REG(base))
8710 #define LLWU_WR_PE3(base, value) (LLWU_PE3_REG(base) = (value))
8711 #define LLWU_RMW_PE3(base, mask, value) (LLWU_WR_PE3(base, (LLWU_RD_PE3(base) & ~(mask)) | (value)))
8712 #define LLWU_SET_PE3(base, value) (BME_OR8(&LLWU_PE3_REG(base), (uint8_t)(value)))
8713 #define LLWU_CLR_PE3(base, value) (BME_AND8(&LLWU_PE3_REG(base), (uint8_t)(~(value))))
8714 #define LLWU_TOG_PE3(base, value) (BME_XOR8(&LLWU_PE3_REG(base), (uint8_t)(value)))
8715 /*@}*/
8716 
8717 /*
8718  * Constants & macros for individual LLWU_PE3 bitfields
8719  */
8720 
8721 /*!
8722  * @name Register LLWU_PE3, field WUPE8[1:0] (RW)
8723  *
8724  * Enables and configures the edge detection for the wakeup pin.
8725  *
8726  * Values:
8727  * - 0b00 - External input pin disabled as wakeup input
8728  * - 0b01 - External input pin enabled with rising edge detection
8729  * - 0b10 - External input pin enabled with falling edge detection
8730  * - 0b11 - External input pin enabled with any change detection
8731  */
8732 /*@{*/
8733 /*! @brief Read current value of the LLWU_PE3_WUPE8 field. */
8734 #define LLWU_RD_PE3_WUPE8(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE8_MASK) >> LLWU_PE3_WUPE8_SHIFT)
8735 #define LLWU_BRD_PE3_WUPE8(base) (BME_UBFX8(&LLWU_PE3_REG(base), LLWU_PE3_WUPE8_SHIFT, LLWU_PE3_WUPE8_WIDTH))
8736 
8737 /*! @brief Set the WUPE8 field to a new value. */
8738 #define LLWU_WR_PE3_WUPE8(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE8_MASK, LLWU_PE3_WUPE8(value)))
8739 #define LLWU_BWR_PE3_WUPE8(base, value) (BME_BFI8(&LLWU_PE3_REG(base), ((uint8_t)(value) << LLWU_PE3_WUPE8_SHIFT), LLWU_PE3_WUPE8_SHIFT, LLWU_PE3_WUPE8_WIDTH))
8740 /*@}*/
8741 
8742 /*!
8743  * @name Register LLWU_PE3, field WUPE9[3:2] (RW)
8744  *
8745  * Enables and configures the edge detection for the wakeup pin.
8746  *
8747  * Values:
8748  * - 0b00 - External input pin disabled as wakeup input
8749  * - 0b01 - External input pin enabled with rising edge detection
8750  * - 0b10 - External input pin enabled with falling edge detection
8751  * - 0b11 - External input pin enabled with any change detection
8752  */
8753 /*@{*/
8754 /*! @brief Read current value of the LLWU_PE3_WUPE9 field. */
8755 #define LLWU_RD_PE3_WUPE9(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE9_MASK) >> LLWU_PE3_WUPE9_SHIFT)
8756 #define LLWU_BRD_PE3_WUPE9(base) (BME_UBFX8(&LLWU_PE3_REG(base), LLWU_PE3_WUPE9_SHIFT, LLWU_PE3_WUPE9_WIDTH))
8757 
8758 /*! @brief Set the WUPE9 field to a new value. */
8759 #define LLWU_WR_PE3_WUPE9(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE9_MASK, LLWU_PE3_WUPE9(value)))
8760 #define LLWU_BWR_PE3_WUPE9(base, value) (BME_BFI8(&LLWU_PE3_REG(base), ((uint8_t)(value) << LLWU_PE3_WUPE9_SHIFT), LLWU_PE3_WUPE9_SHIFT, LLWU_PE3_WUPE9_WIDTH))
8761 /*@}*/
8762 
8763 /*!
8764  * @name Register LLWU_PE3, field WUPE10[5:4] (RW)
8765  *
8766  * Enables and configures the edge detection for the wakeup pin.
8767  *
8768  * Values:
8769  * - 0b00 - External input pin disabled as wakeup input
8770  * - 0b01 - External input pin enabled with rising edge detection
8771  * - 0b10 - External input pin enabled with falling edge detection
8772  * - 0b11 - External input pin enabled with any change detection
8773  */
8774 /*@{*/
8775 /*! @brief Read current value of the LLWU_PE3_WUPE10 field. */
8776 #define LLWU_RD_PE3_WUPE10(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE10_MASK) >> LLWU_PE3_WUPE10_SHIFT)
8777 #define LLWU_BRD_PE3_WUPE10(base) (BME_UBFX8(&LLWU_PE3_REG(base), LLWU_PE3_WUPE10_SHIFT, LLWU_PE3_WUPE10_WIDTH))
8778 
8779 /*! @brief Set the WUPE10 field to a new value. */
8780 #define LLWU_WR_PE3_WUPE10(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE10_MASK, LLWU_PE3_WUPE10(value)))
8781 #define LLWU_BWR_PE3_WUPE10(base, value) (BME_BFI8(&LLWU_PE3_REG(base), ((uint8_t)(value) << LLWU_PE3_WUPE10_SHIFT), LLWU_PE3_WUPE10_SHIFT, LLWU_PE3_WUPE10_WIDTH))
8782 /*@}*/
8783 
8784 /*!
8785  * @name Register LLWU_PE3, field WUPE11[7:6] (RW)
8786  *
8787  * Enables and configures the edge detection for the wakeup pin.
8788  *
8789  * Values:
8790  * - 0b00 - External input pin disabled as wakeup input
8791  * - 0b01 - External input pin enabled with rising edge detection
8792  * - 0b10 - External input pin enabled with falling edge detection
8793  * - 0b11 - External input pin enabled with any change detection
8794  */
8795 /*@{*/
8796 /*! @brief Read current value of the LLWU_PE3_WUPE11 field. */
8797 #define LLWU_RD_PE3_WUPE11(base) ((LLWU_PE3_REG(base) & LLWU_PE3_WUPE11_MASK) >> LLWU_PE3_WUPE11_SHIFT)
8798 #define LLWU_BRD_PE3_WUPE11(base) (BME_UBFX8(&LLWU_PE3_REG(base), LLWU_PE3_WUPE11_SHIFT, LLWU_PE3_WUPE11_WIDTH))
8799 
8800 /*! @brief Set the WUPE11 field to a new value. */
8801 #define LLWU_WR_PE3_WUPE11(base, value) (LLWU_RMW_PE3(base, LLWU_PE3_WUPE11_MASK, LLWU_PE3_WUPE11(value)))
8802 #define LLWU_BWR_PE3_WUPE11(base, value) (BME_BFI8(&LLWU_PE3_REG(base), ((uint8_t)(value) << LLWU_PE3_WUPE11_SHIFT), LLWU_PE3_WUPE11_SHIFT, LLWU_PE3_WUPE11_WIDTH))
8803 /*@}*/
8804 
8805 /*******************************************************************************
8806  * LLWU_PE4 - LLWU Pin Enable 4 register
8807  ******************************************************************************/
8808 
8809 /*!
8810  * @brief LLWU_PE4 - LLWU Pin Enable 4 register (RW)
8811  *
8812  * Reset value: 0x00U
8813  *
8814  * LLWU_PE4 contains the field to enable and select the edge detect type for the
8815  * external wakeup input pins LLWU_P15-LLWU_P12. This register is reset on Chip
8816  * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
8817  * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
8818  * IntroductionInformation found here describes the registers of the Reset Control
8819  * Module (RCM). The RCM implements many of the reset functions for the chip. See the
8820  * chip's reset chapter for more information. details for more information.
8821  */
8822 /*!
8823  * @name Constants and macros for entire LLWU_PE4 register
8824  */
8825 /*@{*/
8826 #define LLWU_RD_PE4(base)        (LLWU_PE4_REG(base))
8827 #define LLWU_WR_PE4(base, value) (LLWU_PE4_REG(base) = (value))
8828 #define LLWU_RMW_PE4(base, mask, value) (LLWU_WR_PE4(base, (LLWU_RD_PE4(base) & ~(mask)) | (value)))
8829 #define LLWU_SET_PE4(base, value) (BME_OR8(&LLWU_PE4_REG(base), (uint8_t)(value)))
8830 #define LLWU_CLR_PE4(base, value) (BME_AND8(&LLWU_PE4_REG(base), (uint8_t)(~(value))))
8831 #define LLWU_TOG_PE4(base, value) (BME_XOR8(&LLWU_PE4_REG(base), (uint8_t)(value)))
8832 /*@}*/
8833 
8834 /*
8835  * Constants & macros for individual LLWU_PE4 bitfields
8836  */
8837 
8838 /*!
8839  * @name Register LLWU_PE4, field WUPE12[1:0] (RW)
8840  *
8841  * Enables and configures the edge detection for the wakeup pin.
8842  *
8843  * Values:
8844  * - 0b00 - External input pin disabled as wakeup input
8845  * - 0b01 - External input pin enabled with rising edge detection
8846  * - 0b10 - External input pin enabled with falling edge detection
8847  * - 0b11 - External input pin enabled with any change detection
8848  */
8849 /*@{*/
8850 /*! @brief Read current value of the LLWU_PE4_WUPE12 field. */
8851 #define LLWU_RD_PE4_WUPE12(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE12_MASK) >> LLWU_PE4_WUPE12_SHIFT)
8852 #define LLWU_BRD_PE4_WUPE12(base) (BME_UBFX8(&LLWU_PE4_REG(base), LLWU_PE4_WUPE12_SHIFT, LLWU_PE4_WUPE12_WIDTH))
8853 
8854 /*! @brief Set the WUPE12 field to a new value. */
8855 #define LLWU_WR_PE4_WUPE12(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE12_MASK, LLWU_PE4_WUPE12(value)))
8856 #define LLWU_BWR_PE4_WUPE12(base, value) (BME_BFI8(&LLWU_PE4_REG(base), ((uint8_t)(value) << LLWU_PE4_WUPE12_SHIFT), LLWU_PE4_WUPE12_SHIFT, LLWU_PE4_WUPE12_WIDTH))
8857 /*@}*/
8858 
8859 /*!
8860  * @name Register LLWU_PE4, field WUPE13[3:2] (RW)
8861  *
8862  * Enables and configures the edge detection for the wakeup pin.
8863  *
8864  * Values:
8865  * - 0b00 - External input pin disabled as wakeup input
8866  * - 0b01 - External input pin enabled with rising edge detection
8867  * - 0b10 - External input pin enabled with falling edge detection
8868  * - 0b11 - External input pin enabled with any change detection
8869  */
8870 /*@{*/
8871 /*! @brief Read current value of the LLWU_PE4_WUPE13 field. */
8872 #define LLWU_RD_PE4_WUPE13(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE13_MASK) >> LLWU_PE4_WUPE13_SHIFT)
8873 #define LLWU_BRD_PE4_WUPE13(base) (BME_UBFX8(&LLWU_PE4_REG(base), LLWU_PE4_WUPE13_SHIFT, LLWU_PE4_WUPE13_WIDTH))
8874 
8875 /*! @brief Set the WUPE13 field to a new value. */
8876 #define LLWU_WR_PE4_WUPE13(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE13_MASK, LLWU_PE4_WUPE13(value)))
8877 #define LLWU_BWR_PE4_WUPE13(base, value) (BME_BFI8(&LLWU_PE4_REG(base), ((uint8_t)(value) << LLWU_PE4_WUPE13_SHIFT), LLWU_PE4_WUPE13_SHIFT, LLWU_PE4_WUPE13_WIDTH))
8878 /*@}*/
8879 
8880 /*!
8881  * @name Register LLWU_PE4, field WUPE14[5:4] (RW)
8882  *
8883  * Enables and configures the edge detection for the wakeup pin.
8884  *
8885  * Values:
8886  * - 0b00 - External input pin disabled as wakeup input
8887  * - 0b01 - External input pin enabled with rising edge detection
8888  * - 0b10 - External input pin enabled with falling edge detection
8889  * - 0b11 - External input pin enabled with any change detection
8890  */
8891 /*@{*/
8892 /*! @brief Read current value of the LLWU_PE4_WUPE14 field. */
8893 #define LLWU_RD_PE4_WUPE14(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE14_MASK) >> LLWU_PE4_WUPE14_SHIFT)
8894 #define LLWU_BRD_PE4_WUPE14(base) (BME_UBFX8(&LLWU_PE4_REG(base), LLWU_PE4_WUPE14_SHIFT, LLWU_PE4_WUPE14_WIDTH))
8895 
8896 /*! @brief Set the WUPE14 field to a new value. */
8897 #define LLWU_WR_PE4_WUPE14(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE14_MASK, LLWU_PE4_WUPE14(value)))
8898 #define LLWU_BWR_PE4_WUPE14(base, value) (BME_BFI8(&LLWU_PE4_REG(base), ((uint8_t)(value) << LLWU_PE4_WUPE14_SHIFT), LLWU_PE4_WUPE14_SHIFT, LLWU_PE4_WUPE14_WIDTH))
8899 /*@}*/
8900 
8901 /*!
8902  * @name Register LLWU_PE4, field WUPE15[7:6] (RW)
8903  *
8904  * Enables and configures the edge detection for the wakeup pin.
8905  *
8906  * Values:
8907  * - 0b00 - External input pin disabled as wakeup input
8908  * - 0b01 - External input pin enabled with rising edge detection
8909  * - 0b10 - External input pin enabled with falling edge detection
8910  * - 0b11 - External input pin enabled with any change detection
8911  */
8912 /*@{*/
8913 /*! @brief Read current value of the LLWU_PE4_WUPE15 field. */
8914 #define LLWU_RD_PE4_WUPE15(base) ((LLWU_PE4_REG(base) & LLWU_PE4_WUPE15_MASK) >> LLWU_PE4_WUPE15_SHIFT)
8915 #define LLWU_BRD_PE4_WUPE15(base) (BME_UBFX8(&LLWU_PE4_REG(base), LLWU_PE4_WUPE15_SHIFT, LLWU_PE4_WUPE15_WIDTH))
8916 
8917 /*! @brief Set the WUPE15 field to a new value. */
8918 #define LLWU_WR_PE4_WUPE15(base, value) (LLWU_RMW_PE4(base, LLWU_PE4_WUPE15_MASK, LLWU_PE4_WUPE15(value)))
8919 #define LLWU_BWR_PE4_WUPE15(base, value) (BME_BFI8(&LLWU_PE4_REG(base), ((uint8_t)(value) << LLWU_PE4_WUPE15_SHIFT), LLWU_PE4_WUPE15_SHIFT, LLWU_PE4_WUPE15_WIDTH))
8920 /*@}*/
8921 
8922 /*******************************************************************************
8923  * LLWU_ME - LLWU Module Enable register
8924  ******************************************************************************/
8925 
8926 /*!
8927  * @brief LLWU_ME - LLWU Module Enable register (RW)
8928  *
8929  * Reset value: 0x00U
8930  *
8931  * LLWU_ME contains the bits to enable the internal module flag as a wakeup
8932  * input source for inputs MWUF7-MWUF0. This register is reset on Chip Reset not VLLS
8933  * and by reset types that trigger Chip Reset not VLLS. It is unaffected by
8934  * reset types that do not trigger Chip Reset not VLLS. See the
8935  * IntroductionInformation found here describes the registers of the Reset Control Module (RCM). The
8936  * RCM implements many of the reset functions for the chip. See the chip's reset
8937  * chapter for more information. details for more information.
8938  */
8939 /*!
8940  * @name Constants and macros for entire LLWU_ME register
8941  */
8942 /*@{*/
8943 #define LLWU_RD_ME(base)         (LLWU_ME_REG(base))
8944 #define LLWU_WR_ME(base, value)  (LLWU_ME_REG(base) = (value))
8945 #define LLWU_RMW_ME(base, mask, value) (LLWU_WR_ME(base, (LLWU_RD_ME(base) & ~(mask)) | (value)))
8946 #define LLWU_SET_ME(base, value) (BME_OR8(&LLWU_ME_REG(base), (uint8_t)(value)))
8947 #define LLWU_CLR_ME(base, value) (BME_AND8(&LLWU_ME_REG(base), (uint8_t)(~(value))))
8948 #define LLWU_TOG_ME(base, value) (BME_XOR8(&LLWU_ME_REG(base), (uint8_t)(value)))
8949 /*@}*/
8950 
8951 /*
8952  * Constants & macros for individual LLWU_ME bitfields
8953  */
8954 
8955 /*!
8956  * @name Register LLWU_ME, field WUME0[0] (RW)
8957  *
8958  * Enables an internal module as a wakeup source input.
8959  *
8960  * Values:
8961  * - 0b0 - Internal module flag not used as wakeup source
8962  * - 0b1 - Internal module flag used as wakeup source
8963  */
8964 /*@{*/
8965 /*! @brief Read current value of the LLWU_ME_WUME0 field. */
8966 #define LLWU_RD_ME_WUME0(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME0_MASK) >> LLWU_ME_WUME0_SHIFT)
8967 #define LLWU_BRD_ME_WUME0(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME0_SHIFT, LLWU_ME_WUME0_WIDTH))
8968 
8969 /*! @brief Set the WUME0 field to a new value. */
8970 #define LLWU_WR_ME_WUME0(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME0_MASK, LLWU_ME_WUME0(value)))
8971 #define LLWU_BWR_ME_WUME0(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_WUME0_SHIFT), LLWU_ME_WUME0_SHIFT, LLWU_ME_WUME0_WIDTH))
8972 /*@}*/
8973 
8974 /*!
8975  * @name Register LLWU_ME, field WUME1[1] (RW)
8976  *
8977  * Enables an internal module as a wakeup source input.
8978  *
8979  * Values:
8980  * - 0b0 - Internal module flag not used as wakeup source
8981  * - 0b1 - Internal module flag used as wakeup source
8982  */
8983 /*@{*/
8984 /*! @brief Read current value of the LLWU_ME_WUME1 field. */
8985 #define LLWU_RD_ME_WUME1(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME1_MASK) >> LLWU_ME_WUME1_SHIFT)
8986 #define LLWU_BRD_ME_WUME1(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME1_SHIFT, LLWU_ME_WUME1_WIDTH))
8987 
8988 /*! @brief Set the WUME1 field to a new value. */
8989 #define LLWU_WR_ME_WUME1(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME1_MASK, LLWU_ME_WUME1(value)))
8990 #define LLWU_BWR_ME_WUME1(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_WUME1_SHIFT), LLWU_ME_WUME1_SHIFT, LLWU_ME_WUME1_WIDTH))
8991 /*@}*/
8992 
8993 /*!
8994  * @name Register LLWU_ME, field WUME2[2] (RW)
8995  *
8996  * Enables an internal module as a wakeup source input.
8997  *
8998  * Values:
8999  * - 0b0 - Internal module flag not used as wakeup source
9000  * - 0b1 - Internal module flag used as wakeup source
9001  */
9002 /*@{*/
9003 /*! @brief Read current value of the LLWU_ME_WUME2 field. */
9004 #define LLWU_RD_ME_WUME2(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME2_MASK) >> LLWU_ME_WUME2_SHIFT)
9005 #define LLWU_BRD_ME_WUME2(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME2_SHIFT, LLWU_ME_WUME2_WIDTH))
9006 
9007 /*! @brief Set the WUME2 field to a new value. */
9008 #define LLWU_WR_ME_WUME2(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME2_MASK, LLWU_ME_WUME2(value)))
9009 #define LLWU_BWR_ME_WUME2(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_WUME2_SHIFT), LLWU_ME_WUME2_SHIFT, LLWU_ME_WUME2_WIDTH))
9010 /*@}*/
9011 
9012 /*!
9013  * @name Register LLWU_ME, field WUME3[3] (RW)
9014  *
9015  * Enables an internal module as a wakeup source input.
9016  *
9017  * Values:
9018  * - 0b0 - Internal module flag not used as wakeup source
9019  * - 0b1 - Internal module flag used as wakeup source
9020  */
9021 /*@{*/
9022 /*! @brief Read current value of the LLWU_ME_WUME3 field. */
9023 #define LLWU_RD_ME_WUME3(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME3_MASK) >> LLWU_ME_WUME3_SHIFT)
9024 #define LLWU_BRD_ME_WUME3(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME3_SHIFT, LLWU_ME_WUME3_WIDTH))
9025 
9026 /*! @brief Set the WUME3 field to a new value. */
9027 #define LLWU_WR_ME_WUME3(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME3_MASK, LLWU_ME_WUME3(value)))
9028 #define LLWU_BWR_ME_WUME3(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_WUME3_SHIFT), LLWU_ME_WUME3_SHIFT, LLWU_ME_WUME3_WIDTH))
9029 /*@}*/
9030 
9031 /*!
9032  * @name Register LLWU_ME, field WUME4[4] (RW)
9033  *
9034  * Enables an internal module as a wakeup source input.
9035  *
9036  * Values:
9037  * - 0b0 - Internal module flag not used as wakeup source
9038  * - 0b1 - Internal module flag used as wakeup source
9039  */
9040 /*@{*/
9041 /*! @brief Read current value of the LLWU_ME_WUME4 field. */
9042 #define LLWU_RD_ME_WUME4(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME4_MASK) >> LLWU_ME_WUME4_SHIFT)
9043 #define LLWU_BRD_ME_WUME4(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME4_SHIFT, LLWU_ME_WUME4_WIDTH))
9044 
9045 /*! @brief Set the WUME4 field to a new value. */
9046 #define LLWU_WR_ME_WUME4(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME4_MASK, LLWU_ME_WUME4(value)))
9047 #define LLWU_BWR_ME_WUME4(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_WUME4_SHIFT), LLWU_ME_WUME4_SHIFT, LLWU_ME_WUME4_WIDTH))
9048 /*@}*/
9049 
9050 /*!
9051  * @name Register LLWU_ME, field WUME5[5] (RW)
9052  *
9053  * Enables an internal module as a wakeup source input.
9054  *
9055  * Values:
9056  * - 0b0 - Internal module flag not used as wakeup source
9057  * - 0b1 - Internal module flag used as wakeup source
9058  */
9059 /*@{*/
9060 /*! @brief Read current value of the LLWU_ME_WUME5 field. */
9061 #define LLWU_RD_ME_WUME5(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME5_MASK) >> LLWU_ME_WUME5_SHIFT)
9062 #define LLWU_BRD_ME_WUME5(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME5_SHIFT, LLWU_ME_WUME5_WIDTH))
9063 
9064 /*! @brief Set the WUME5 field to a new value. */
9065 #define LLWU_WR_ME_WUME5(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME5_MASK, LLWU_ME_WUME5(value)))
9066 #define LLWU_BWR_ME_WUME5(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_WUME5_SHIFT), LLWU_ME_WUME5_SHIFT, LLWU_ME_WUME5_WIDTH))
9067 /*@}*/
9068 
9069 /*!
9070  * @name Register LLWU_ME, field WUME6[6] (RW)
9071  *
9072  * Enables an internal module as a wakeup source input.
9073  *
9074  * Values:
9075  * - 0b0 - Internal module flag not used as wakeup source
9076  * - 0b1 - Internal module flag used as wakeup source
9077  */
9078 /*@{*/
9079 /*! @brief Read current value of the LLWU_ME_WUME6 field. */
9080 #define LLWU_RD_ME_WUME6(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME6_MASK) >> LLWU_ME_WUME6_SHIFT)
9081 #define LLWU_BRD_ME_WUME6(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME6_SHIFT, LLWU_ME_WUME6_WIDTH))
9082 
9083 /*! @brief Set the WUME6 field to a new value. */
9084 #define LLWU_WR_ME_WUME6(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME6_MASK, LLWU_ME_WUME6(value)))
9085 #define LLWU_BWR_ME_WUME6(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_WUME6_SHIFT), LLWU_ME_WUME6_SHIFT, LLWU_ME_WUME6_WIDTH))
9086 /*@}*/
9087 
9088 /*!
9089  * @name Register LLWU_ME, field WUME7[7] (RW)
9090  *
9091  * Enables an internal module as a wakeup source input.
9092  *
9093  * Values:
9094  * - 0b0 - Internal module flag not used as wakeup source
9095  * - 0b1 - Internal module flag used as wakeup source
9096  */
9097 /*@{*/
9098 /*! @brief Read current value of the LLWU_ME_WUME7 field. */
9099 #define LLWU_RD_ME_WUME7(base) ((LLWU_ME_REG(base) & LLWU_ME_WUME7_MASK) >> LLWU_ME_WUME7_SHIFT)
9100 #define LLWU_BRD_ME_WUME7(base) (BME_UBFX8(&LLWU_ME_REG(base), LLWU_ME_WUME7_SHIFT, LLWU_ME_WUME7_WIDTH))
9101 
9102 /*! @brief Set the WUME7 field to a new value. */
9103 #define LLWU_WR_ME_WUME7(base, value) (LLWU_RMW_ME(base, LLWU_ME_WUME7_MASK, LLWU_ME_WUME7(value)))
9104 #define LLWU_BWR_ME_WUME7(base, value) (BME_BFI8(&LLWU_ME_REG(base), ((uint8_t)(value) << LLWU_ME_WUME7_SHIFT), LLWU_ME_WUME7_SHIFT, LLWU_ME_WUME7_WIDTH))
9105 /*@}*/
9106 
9107 /*******************************************************************************
9108  * LLWU_F1 - LLWU Flag 1 register
9109  ******************************************************************************/
9110 
9111 /*!
9112  * @brief LLWU_F1 - LLWU Flag 1 register (W1C)
9113  *
9114  * Reset value: 0x00U
9115  *
9116  * LLWU_F1 contains the wakeup flags indicating which wakeup source caused the
9117  * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
9118  * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
9119  * external wakeup flags are read-only and clearing a flag is accomplished by a write
9120  * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
9121  * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
9122  * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
9123  * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
9124  * IntroductionInformation found here describes the registers of the Reset Control
9125  * Module (RCM). The RCM implements many of the reset functions for the chip. See the
9126  * chip's reset chapter for more information. details for more information.
9127  */
9128 /*!
9129  * @name Constants and macros for entire LLWU_F1 register
9130  */
9131 /*@{*/
9132 #define LLWU_RD_F1(base)         (LLWU_F1_REG(base))
9133 #define LLWU_WR_F1(base, value)  (LLWU_F1_REG(base) = (value))
9134 #define LLWU_RMW_F1(base, mask, value) (LLWU_WR_F1(base, (LLWU_RD_F1(base) & ~(mask)) | (value)))
9135 #define LLWU_SET_F1(base, value) (BME_OR8(&LLWU_F1_REG(base), (uint8_t)(value)))
9136 #define LLWU_CLR_F1(base, value) (BME_AND8(&LLWU_F1_REG(base), (uint8_t)(~(value))))
9137 #define LLWU_TOG_F1(base, value) (BME_XOR8(&LLWU_F1_REG(base), (uint8_t)(value)))
9138 /*@}*/
9139 
9140 /*
9141  * Constants & macros for individual LLWU_F1 bitfields
9142  */
9143 
9144 /*!
9145  * @name Register LLWU_F1, field WUF0[0] (W1C)
9146  *
9147  * Indicates that an enabled external wake-up pin was a source of exiting a
9148  * low-leakage power mode. To clear the flag, write a 1 to WUF0.
9149  *
9150  * Values:
9151  * - 0b0 - LLWU_P0 input was not a wakeup source
9152  * - 0b1 - LLWU_P0 input was a wakeup source
9153  */
9154 /*@{*/
9155 /*! @brief Read current value of the LLWU_F1_WUF0 field. */
9156 #define LLWU_RD_F1_WUF0(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF0_MASK) >> LLWU_F1_WUF0_SHIFT)
9157 #define LLWU_BRD_F1_WUF0(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF0_SHIFT, LLWU_F1_WUF0_WIDTH))
9158 
9159 /*! @brief Set the WUF0 field to a new value. */
9160 #define LLWU_WR_F1_WUF0(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF0(value)))
9161 #define LLWU_BWR_F1_WUF0(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WUF0_SHIFT), LLWU_F1_WUF0_SHIFT, LLWU_F1_WUF0_WIDTH))
9162 /*@}*/
9163 
9164 /*!
9165  * @name Register LLWU_F1, field WUF1[1] (W1C)
9166  *
9167  * Indicates that an enabled external wakeup pin was a source of exiting a
9168  * low-leakage power mode. To clear the flag, write a 1 to WUF1.
9169  *
9170  * Values:
9171  * - 0b0 - LLWU_P1 input was not a wakeup source
9172  * - 0b1 - LLWU_P1 input was a wakeup source
9173  */
9174 /*@{*/
9175 /*! @brief Read current value of the LLWU_F1_WUF1 field. */
9176 #define LLWU_RD_F1_WUF1(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF1_MASK) >> LLWU_F1_WUF1_SHIFT)
9177 #define LLWU_BRD_F1_WUF1(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF1_SHIFT, LLWU_F1_WUF1_WIDTH))
9178 
9179 /*! @brief Set the WUF1 field to a new value. */
9180 #define LLWU_WR_F1_WUF1(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF1_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF1(value)))
9181 #define LLWU_BWR_F1_WUF1(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WUF1_SHIFT), LLWU_F1_WUF1_SHIFT, LLWU_F1_WUF1_WIDTH))
9182 /*@}*/
9183 
9184 /*!
9185  * @name Register LLWU_F1, field WUF2[2] (W1C)
9186  *
9187  * Indicates that an enabled external wakeup pin was a source of exiting a
9188  * low-leakage power mode. To clear the flag, write a 1 to WUF2.
9189  *
9190  * Values:
9191  * - 0b0 - LLWU_P2 input was not a wakeup source
9192  * - 0b1 - LLWU_P2 input was a wakeup source
9193  */
9194 /*@{*/
9195 /*! @brief Read current value of the LLWU_F1_WUF2 field. */
9196 #define LLWU_RD_F1_WUF2(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF2_MASK) >> LLWU_F1_WUF2_SHIFT)
9197 #define LLWU_BRD_F1_WUF2(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF2_SHIFT, LLWU_F1_WUF2_WIDTH))
9198 
9199 /*! @brief Set the WUF2 field to a new value. */
9200 #define LLWU_WR_F1_WUF2(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF2_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF2(value)))
9201 #define LLWU_BWR_F1_WUF2(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WUF2_SHIFT), LLWU_F1_WUF2_SHIFT, LLWU_F1_WUF2_WIDTH))
9202 /*@}*/
9203 
9204 /*!
9205  * @name Register LLWU_F1, field WUF3[3] (W1C)
9206  *
9207  * Indicates that an enabled external wakeup pin was a source of exiting a
9208  * low-leakage power mode. To clear the flag, write a 1 to WUF3.
9209  *
9210  * Values:
9211  * - 0b0 - LLWU_P3 input was not a wake-up source
9212  * - 0b1 - LLWU_P3 input was a wake-up source
9213  */
9214 /*@{*/
9215 /*! @brief Read current value of the LLWU_F1_WUF3 field. */
9216 #define LLWU_RD_F1_WUF3(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF3_MASK) >> LLWU_F1_WUF3_SHIFT)
9217 #define LLWU_BRD_F1_WUF3(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF3_SHIFT, LLWU_F1_WUF3_WIDTH))
9218 
9219 /*! @brief Set the WUF3 field to a new value. */
9220 #define LLWU_WR_F1_WUF3(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF3_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF3(value)))
9221 #define LLWU_BWR_F1_WUF3(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WUF3_SHIFT), LLWU_F1_WUF3_SHIFT, LLWU_F1_WUF3_WIDTH))
9222 /*@}*/
9223 
9224 /*!
9225  * @name Register LLWU_F1, field WUF4[4] (W1C)
9226  *
9227  * Indicates that an enabled external wake-up pin was a source of exiting a
9228  * low-leakage power mode. To clear the flag, write a 1 to WUF4.
9229  *
9230  * Values:
9231  * - 0b0 - LLWU_P4 input was not a wakeup source
9232  * - 0b1 - LLWU_P4 input was a wakeup source
9233  */
9234 /*@{*/
9235 /*! @brief Read current value of the LLWU_F1_WUF4 field. */
9236 #define LLWU_RD_F1_WUF4(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF4_MASK) >> LLWU_F1_WUF4_SHIFT)
9237 #define LLWU_BRD_F1_WUF4(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF4_SHIFT, LLWU_F1_WUF4_WIDTH))
9238 
9239 /*! @brief Set the WUF4 field to a new value. */
9240 #define LLWU_WR_F1_WUF4(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF4_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF4(value)))
9241 #define LLWU_BWR_F1_WUF4(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WUF4_SHIFT), LLWU_F1_WUF4_SHIFT, LLWU_F1_WUF4_WIDTH))
9242 /*@}*/
9243 
9244 /*!
9245  * @name Register LLWU_F1, field WUF5[5] (W1C)
9246  *
9247  * Indicates that an enabled external wakeup pin was a source of exiting a
9248  * low-leakage power mode. To clear the flag, write a 1 to WUF5.
9249  *
9250  * Values:
9251  * - 0b0 - LLWU_P5 input was not a wakeup source
9252  * - 0b1 - LLWU_P5 input was a wakeup source
9253  */
9254 /*@{*/
9255 /*! @brief Read current value of the LLWU_F1_WUF5 field. */
9256 #define LLWU_RD_F1_WUF5(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF5_MASK) >> LLWU_F1_WUF5_SHIFT)
9257 #define LLWU_BRD_F1_WUF5(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF5_SHIFT, LLWU_F1_WUF5_WIDTH))
9258 
9259 /*! @brief Set the WUF5 field to a new value. */
9260 #define LLWU_WR_F1_WUF5(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF5_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF6_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF5(value)))
9261 #define LLWU_BWR_F1_WUF5(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WUF5_SHIFT), LLWU_F1_WUF5_SHIFT, LLWU_F1_WUF5_WIDTH))
9262 /*@}*/
9263 
9264 /*!
9265  * @name Register LLWU_F1, field WUF6[6] (W1C)
9266  *
9267  * Indicates that an enabled external wakeup pin was a source of exiting a
9268  * low-leakage power mode. To clear the flag, write a 1 to WUF6.
9269  *
9270  * Values:
9271  * - 0b0 - LLWU_P6 input was not a wakeup source
9272  * - 0b1 - LLWU_P6 input was a wakeup source
9273  */
9274 /*@{*/
9275 /*! @brief Read current value of the LLWU_F1_WUF6 field. */
9276 #define LLWU_RD_F1_WUF6(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF6_MASK) >> LLWU_F1_WUF6_SHIFT)
9277 #define LLWU_BRD_F1_WUF6(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF6_SHIFT, LLWU_F1_WUF6_WIDTH))
9278 
9279 /*! @brief Set the WUF6 field to a new value. */
9280 #define LLWU_WR_F1_WUF6(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF6_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF7_MASK), LLWU_F1_WUF6(value)))
9281 #define LLWU_BWR_F1_WUF6(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WUF6_SHIFT), LLWU_F1_WUF6_SHIFT, LLWU_F1_WUF6_WIDTH))
9282 /*@}*/
9283 
9284 /*!
9285  * @name Register LLWU_F1, field WUF7[7] (W1C)
9286  *
9287  * Indicates that an enabled external wakeup pin was a source of exiting a
9288  * low-leakage power mode. To clear the flag, write a 1 to WUF7.
9289  *
9290  * Values:
9291  * - 0b0 - LLWU_P7 input was not a wakeup source
9292  * - 0b1 - LLWU_P7 input was a wakeup source
9293  */
9294 /*@{*/
9295 /*! @brief Read current value of the LLWU_F1_WUF7 field. */
9296 #define LLWU_RD_F1_WUF7(base) ((LLWU_F1_REG(base) & LLWU_F1_WUF7_MASK) >> LLWU_F1_WUF7_SHIFT)
9297 #define LLWU_BRD_F1_WUF7(base) (BME_UBFX8(&LLWU_F1_REG(base), LLWU_F1_WUF7_SHIFT, LLWU_F1_WUF7_WIDTH))
9298 
9299 /*! @brief Set the WUF7 field to a new value. */
9300 #define LLWU_WR_F1_WUF7(base, value) (LLWU_RMW_F1(base, (LLWU_F1_WUF7_MASK | LLWU_F1_WUF0_MASK | LLWU_F1_WUF1_MASK | LLWU_F1_WUF2_MASK | LLWU_F1_WUF3_MASK | LLWU_F1_WUF4_MASK | LLWU_F1_WUF5_MASK | LLWU_F1_WUF6_MASK), LLWU_F1_WUF7(value)))
9301 #define LLWU_BWR_F1_WUF7(base, value) (BME_BFI8(&LLWU_F1_REG(base), ((uint8_t)(value) << LLWU_F1_WUF7_SHIFT), LLWU_F1_WUF7_SHIFT, LLWU_F1_WUF7_WIDTH))
9302 /*@}*/
9303 
9304 /*******************************************************************************
9305  * LLWU_F2 - LLWU Flag 2 register
9306  ******************************************************************************/
9307 
9308 /*!
9309  * @brief LLWU_F2 - LLWU Flag 2 register (W1C)
9310  *
9311  * Reset value: 0x00U
9312  *
9313  * LLWU_F2 contains the wakeup flags indicating which wakeup source caused the
9314  * MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU
9315  * interrupt flow. For VLLS, this is the source causing the MCU reset flow. The
9316  * external wakeup flags are read-only and clearing a flag is accomplished by a write
9317  * of a 1 to the corresponding WUFx bit. The wakeup flag (WUFx), if set, will
9318  * remain set if the associated WUPEx bit is cleared. This register is reset on Chip
9319  * Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
9320  * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
9321  * IntroductionInformation found here describes the registers of the Reset Control
9322  * Module (RCM). The RCM implements many of the reset functions for the chip. See the
9323  * chip's reset chapter for more information. details for more information.
9324  */
9325 /*!
9326  * @name Constants and macros for entire LLWU_F2 register
9327  */
9328 /*@{*/
9329 #define LLWU_RD_F2(base)         (LLWU_F2_REG(base))
9330 #define LLWU_WR_F2(base, value)  (LLWU_F2_REG(base) = (value))
9331 #define LLWU_RMW_F2(base, mask, value) (LLWU_WR_F2(base, (LLWU_RD_F2(base) & ~(mask)) | (value)))
9332 #define LLWU_SET_F2(base, value) (BME_OR8(&LLWU_F2_REG(base), (uint8_t)(value)))
9333 #define LLWU_CLR_F2(base, value) (BME_AND8(&LLWU_F2_REG(base), (uint8_t)(~(value))))
9334 #define LLWU_TOG_F2(base, value) (BME_XOR8(&LLWU_F2_REG(base), (uint8_t)(value)))
9335 /*@}*/
9336 
9337 /*
9338  * Constants & macros for individual LLWU_F2 bitfields
9339  */
9340 
9341 /*!
9342  * @name Register LLWU_F2, field WUF8[0] (W1C)
9343  *
9344  * Indicates that an enabled external wakeup pin was a source of exiting a
9345  * low-leakage power mode. To clear the flag, write a 1 to WUF8.
9346  *
9347  * Values:
9348  * - 0b0 - LLWU_P8 input was not a wakeup source
9349  * - 0b1 - LLWU_P8 input was a wakeup source
9350  */
9351 /*@{*/
9352 /*! @brief Read current value of the LLWU_F2_WUF8 field. */
9353 #define LLWU_RD_F2_WUF8(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF8_MASK) >> LLWU_F2_WUF8_SHIFT)
9354 #define LLWU_BRD_F2_WUF8(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF8_SHIFT, LLWU_F2_WUF8_WIDTH))
9355 
9356 /*! @brief Set the WUF8 field to a new value. */
9357 #define LLWU_WR_F2_WUF8(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF8(value)))
9358 #define LLWU_BWR_F2_WUF8(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_WUF8_SHIFT), LLWU_F2_WUF8_SHIFT, LLWU_F2_WUF8_WIDTH))
9359 /*@}*/
9360 
9361 /*!
9362  * @name Register LLWU_F2, field WUF9[1] (W1C)
9363  *
9364  * Indicates that an enabled external wakeup pin was a source of exiting a
9365  * low-leakage power mode. To clear the flag, write a 1 to WUF9.
9366  *
9367  * Values:
9368  * - 0b0 - LLWU_P9 input was not a wakeup source
9369  * - 0b1 - LLWU_P9 input was a wakeup source
9370  */
9371 /*@{*/
9372 /*! @brief Read current value of the LLWU_F2_WUF9 field. */
9373 #define LLWU_RD_F2_WUF9(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF9_MASK) >> LLWU_F2_WUF9_SHIFT)
9374 #define LLWU_BRD_F2_WUF9(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF9_SHIFT, LLWU_F2_WUF9_WIDTH))
9375 
9376 /*! @brief Set the WUF9 field to a new value. */
9377 #define LLWU_WR_F2_WUF9(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF9_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF9(value)))
9378 #define LLWU_BWR_F2_WUF9(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_WUF9_SHIFT), LLWU_F2_WUF9_SHIFT, LLWU_F2_WUF9_WIDTH))
9379 /*@}*/
9380 
9381 /*!
9382  * @name Register LLWU_F2, field WUF10[2] (W1C)
9383  *
9384  * Indicates that an enabled external wakeup pin was a source of exiting a
9385  * low-leakage power mode. To clear the flag, write a 1 to WUF10.
9386  *
9387  * Values:
9388  * - 0b0 - LLWU_P10 input was not a wakeup source
9389  * - 0b1 - LLWU_P10 input was a wakeup source
9390  */
9391 /*@{*/
9392 /*! @brief Read current value of the LLWU_F2_WUF10 field. */
9393 #define LLWU_RD_F2_WUF10(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF10_MASK) >> LLWU_F2_WUF10_SHIFT)
9394 #define LLWU_BRD_F2_WUF10(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF10_SHIFT, LLWU_F2_WUF10_WIDTH))
9395 
9396 /*! @brief Set the WUF10 field to a new value. */
9397 #define LLWU_WR_F2_WUF10(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF10_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF10(value)))
9398 #define LLWU_BWR_F2_WUF10(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_WUF10_SHIFT), LLWU_F2_WUF10_SHIFT, LLWU_F2_WUF10_WIDTH))
9399 /*@}*/
9400 
9401 /*!
9402  * @name Register LLWU_F2, field WUF11[3] (W1C)
9403  *
9404  * Indicates that an enabled external wakeup pin was a source of exiting a
9405  * low-leakage power mode. To clear the flag, write a 1 to WUF11.
9406  *
9407  * Values:
9408  * - 0b0 - LLWU_P11 input was not a wakeup source
9409  * - 0b1 - LLWU_P11 input was a wakeup source
9410  */
9411 /*@{*/
9412 /*! @brief Read current value of the LLWU_F2_WUF11 field. */
9413 #define LLWU_RD_F2_WUF11(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF11_MASK) >> LLWU_F2_WUF11_SHIFT)
9414 #define LLWU_BRD_F2_WUF11(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF11_SHIFT, LLWU_F2_WUF11_WIDTH))
9415 
9416 /*! @brief Set the WUF11 field to a new value. */
9417 #define LLWU_WR_F2_WUF11(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF11_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF11(value)))
9418 #define LLWU_BWR_F2_WUF11(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_WUF11_SHIFT), LLWU_F2_WUF11_SHIFT, LLWU_F2_WUF11_WIDTH))
9419 /*@}*/
9420 
9421 /*!
9422  * @name Register LLWU_F2, field WUF12[4] (W1C)
9423  *
9424  * Indicates that an enabled external wakeup pin was a source of exiting a
9425  * low-leakage power mode. To clear the flag, write a 1 to WUF12.
9426  *
9427  * Values:
9428  * - 0b0 - LLWU_P12 input was not a wakeup source
9429  * - 0b1 - LLWU_P12 input was a wakeup source
9430  */
9431 /*@{*/
9432 /*! @brief Read current value of the LLWU_F2_WUF12 field. */
9433 #define LLWU_RD_F2_WUF12(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF12_MASK) >> LLWU_F2_WUF12_SHIFT)
9434 #define LLWU_BRD_F2_WUF12(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF12_SHIFT, LLWU_F2_WUF12_WIDTH))
9435 
9436 /*! @brief Set the WUF12 field to a new value. */
9437 #define LLWU_WR_F2_WUF12(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF12_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF12(value)))
9438 #define LLWU_BWR_F2_WUF12(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_WUF12_SHIFT), LLWU_F2_WUF12_SHIFT, LLWU_F2_WUF12_WIDTH))
9439 /*@}*/
9440 
9441 /*!
9442  * @name Register LLWU_F2, field WUF13[5] (W1C)
9443  *
9444  * Indicates that an enabled external wakeup pin was a source of exiting a
9445  * low-leakage power mode. To clear the flag, write a 1 to WUF13.
9446  *
9447  * Values:
9448  * - 0b0 - LLWU_P13 input was not a wakeup source
9449  * - 0b1 - LLWU_P13 input was a wakeup source
9450  */
9451 /*@{*/
9452 /*! @brief Read current value of the LLWU_F2_WUF13 field. */
9453 #define LLWU_RD_F2_WUF13(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF13_MASK) >> LLWU_F2_WUF13_SHIFT)
9454 #define LLWU_BRD_F2_WUF13(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF13_SHIFT, LLWU_F2_WUF13_WIDTH))
9455 
9456 /*! @brief Set the WUF13 field to a new value. */
9457 #define LLWU_WR_F2_WUF13(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF13_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF14_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF13(value)))
9458 #define LLWU_BWR_F2_WUF13(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_WUF13_SHIFT), LLWU_F2_WUF13_SHIFT, LLWU_F2_WUF13_WIDTH))
9459 /*@}*/
9460 
9461 /*!
9462  * @name Register LLWU_F2, field WUF14[6] (W1C)
9463  *
9464  * Indicates that an enabled external wakeup pin was a source of exiting a
9465  * low-leakage power mode. To clear the flag, write a 1 to WUF14.
9466  *
9467  * Values:
9468  * - 0b0 - LLWU_P14 input was not a wakeup source
9469  * - 0b1 - LLWU_P14 input was a wakeup source
9470  */
9471 /*@{*/
9472 /*! @brief Read current value of the LLWU_F2_WUF14 field. */
9473 #define LLWU_RD_F2_WUF14(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF14_MASK) >> LLWU_F2_WUF14_SHIFT)
9474 #define LLWU_BRD_F2_WUF14(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF14_SHIFT, LLWU_F2_WUF14_WIDTH))
9475 
9476 /*! @brief Set the WUF14 field to a new value. */
9477 #define LLWU_WR_F2_WUF14(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF14_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF15_MASK), LLWU_F2_WUF14(value)))
9478 #define LLWU_BWR_F2_WUF14(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_WUF14_SHIFT), LLWU_F2_WUF14_SHIFT, LLWU_F2_WUF14_WIDTH))
9479 /*@}*/
9480 
9481 /*!
9482  * @name Register LLWU_F2, field WUF15[7] (W1C)
9483  *
9484  * Indicates that an enabled external wakeup pin was a source of exiting a
9485  * low-leakage power mode. To clear the flag, write a 1 to WUF15.
9486  *
9487  * Values:
9488  * - 0b0 - LLWU_P15 input was not a wakeup source
9489  * - 0b1 - LLWU_P15 input was a wakeup source
9490  */
9491 /*@{*/
9492 /*! @brief Read current value of the LLWU_F2_WUF15 field. */
9493 #define LLWU_RD_F2_WUF15(base) ((LLWU_F2_REG(base) & LLWU_F2_WUF15_MASK) >> LLWU_F2_WUF15_SHIFT)
9494 #define LLWU_BRD_F2_WUF15(base) (BME_UBFX8(&LLWU_F2_REG(base), LLWU_F2_WUF15_SHIFT, LLWU_F2_WUF15_WIDTH))
9495 
9496 /*! @brief Set the WUF15 field to a new value. */
9497 #define LLWU_WR_F2_WUF15(base, value) (LLWU_RMW_F2(base, (LLWU_F2_WUF15_MASK | LLWU_F2_WUF8_MASK | LLWU_F2_WUF9_MASK | LLWU_F2_WUF10_MASK | LLWU_F2_WUF11_MASK | LLWU_F2_WUF12_MASK | LLWU_F2_WUF13_MASK | LLWU_F2_WUF14_MASK), LLWU_F2_WUF15(value)))
9498 #define LLWU_BWR_F2_WUF15(base, value) (BME_BFI8(&LLWU_F2_REG(base), ((uint8_t)(value) << LLWU_F2_WUF15_SHIFT), LLWU_F2_WUF15_SHIFT, LLWU_F2_WUF15_WIDTH))
9499 /*@}*/
9500 
9501 /*******************************************************************************
9502  * LLWU_F3 - LLWU Flag 3 register
9503  ******************************************************************************/
9504 
9505 /*!
9506  * @brief LLWU_F3 - LLWU Flag 3 register (RO)
9507  *
9508  * Reset value: 0x00U
9509  *
9510  * LLWU_F3 contains the wakeup flags indicating which internal wakeup source
9511  * caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the
9512  * CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow.
9513  * For internal peripherals that are capable of running in a low-leakage power
9514  * mode, such as a real time clock module or CMP module, the flag from the
9515  * associated peripheral is accessible as the MWUFx bit. The flag will need to be cleared
9516  * in the peripheral instead of writing a 1 to the MWUFx bit. This register is
9517  * reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not
9518  * VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See
9519  * the IntroductionInformation found here describes the registers of the Reset
9520  * Control Module (RCM). The RCM implements many of the reset functions for the
9521  * chip. See the chip's reset chapter for more information. details for more
9522  * information.
9523  */
9524 /*!
9525  * @name Constants and macros for entire LLWU_F3 register
9526  */
9527 /*@{*/
9528 #define LLWU_RD_F3(base)         (LLWU_F3_REG(base))
9529 /*@}*/
9530 
9531 /*
9532  * Constants & macros for individual LLWU_F3 bitfields
9533  */
9534 
9535 /*!
9536  * @name Register LLWU_F3, field MWUF0[0] (RO)
9537  *
9538  * Indicates that an enabled internal peripheral was a source of exiting a
9539  * low-leakage power mode. To clear the flag, follow the internal peripheral flag
9540  * clearing mechanism.
9541  *
9542  * Values:
9543  * - 0b0 - Module 0 input was not a wakeup source
9544  * - 0b1 - Module 0 input was a wakeup source
9545  */
9546 /*@{*/
9547 /*! @brief Read current value of the LLWU_F3_MWUF0 field. */
9548 #define LLWU_RD_F3_MWUF0(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF0_MASK) >> LLWU_F3_MWUF0_SHIFT)
9549 #define LLWU_BRD_F3_MWUF0(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF0_SHIFT, LLWU_F3_MWUF0_WIDTH))
9550 /*@}*/
9551 
9552 /*!
9553  * @name Register LLWU_F3, field MWUF1[1] (RO)
9554  *
9555  * Indicates that an enabled internal peripheral was a source of exiting a
9556  * low-leakage power mode. To clear the flag, follow the internal peripheral flag
9557  * clearing mechanism.
9558  *
9559  * Values:
9560  * - 0b0 - Module 1 input was not a wakeup source
9561  * - 0b1 - Module 1 input was a wakeup source
9562  */
9563 /*@{*/
9564 /*! @brief Read current value of the LLWU_F3_MWUF1 field. */
9565 #define LLWU_RD_F3_MWUF1(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF1_MASK) >> LLWU_F3_MWUF1_SHIFT)
9566 #define LLWU_BRD_F3_MWUF1(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF1_SHIFT, LLWU_F3_MWUF1_WIDTH))
9567 /*@}*/
9568 
9569 /*!
9570  * @name Register LLWU_F3, field MWUF2[2] (RO)
9571  *
9572  * Indicates that an enabled internal peripheral was a source of exiting a
9573  * low-leakage power mode. To clear the flag, follow the internal peripheral flag
9574  * clearing mechanism.
9575  *
9576  * Values:
9577  * - 0b0 - Module 2 input was not a wakeup source
9578  * - 0b1 - Module 2 input was a wakeup source
9579  */
9580 /*@{*/
9581 /*! @brief Read current value of the LLWU_F3_MWUF2 field. */
9582 #define LLWU_RD_F3_MWUF2(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF2_MASK) >> LLWU_F3_MWUF2_SHIFT)
9583 #define LLWU_BRD_F3_MWUF2(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF2_SHIFT, LLWU_F3_MWUF2_WIDTH))
9584 /*@}*/
9585 
9586 /*!
9587  * @name Register LLWU_F3, field MWUF3[3] (RO)
9588  *
9589  * Indicates that an enabled internal peripheral was a source of exiting a
9590  * low-leakage power mode. To clear the flag, follow the internal peripheral flag
9591  * clearing mechanism.
9592  *
9593  * Values:
9594  * - 0b0 - Module 3 input was not a wakeup source
9595  * - 0b1 - Module 3 input was a wakeup source
9596  */
9597 /*@{*/
9598 /*! @brief Read current value of the LLWU_F3_MWUF3 field. */
9599 #define LLWU_RD_F3_MWUF3(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF3_MASK) >> LLWU_F3_MWUF3_SHIFT)
9600 #define LLWU_BRD_F3_MWUF3(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF3_SHIFT, LLWU_F3_MWUF3_WIDTH))
9601 /*@}*/
9602 
9603 /*!
9604  * @name Register LLWU_F3, field MWUF4[4] (RO)
9605  *
9606  * Indicates that an enabled internal peripheral was a source of exiting a
9607  * low-leakage power mode. To clear the flag, follow the internal peripheral flag
9608  * clearing mechanism.
9609  *
9610  * Values:
9611  * - 0b0 - Module 4 input was not a wakeup source
9612  * - 0b1 - Module 4 input was a wakeup source
9613  */
9614 /*@{*/
9615 /*! @brief Read current value of the LLWU_F3_MWUF4 field. */
9616 #define LLWU_RD_F3_MWUF4(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF4_MASK) >> LLWU_F3_MWUF4_SHIFT)
9617 #define LLWU_BRD_F3_MWUF4(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF4_SHIFT, LLWU_F3_MWUF4_WIDTH))
9618 /*@}*/
9619 
9620 /*!
9621  * @name Register LLWU_F3, field MWUF5[5] (RO)
9622  *
9623  * Indicates that an enabled internal peripheral was a source of exiting a
9624  * low-leakage power mode. To clear the flag, follow the internal peripheral flag
9625  * clearing mechanism.
9626  *
9627  * Values:
9628  * - 0b0 - Module 5 input was not a wakeup source
9629  * - 0b1 - Module 5 input was a wakeup source
9630  */
9631 /*@{*/
9632 /*! @brief Read current value of the LLWU_F3_MWUF5 field. */
9633 #define LLWU_RD_F3_MWUF5(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF5_MASK) >> LLWU_F3_MWUF5_SHIFT)
9634 #define LLWU_BRD_F3_MWUF5(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF5_SHIFT, LLWU_F3_MWUF5_WIDTH))
9635 /*@}*/
9636 
9637 /*!
9638  * @name Register LLWU_F3, field MWUF6[6] (RO)
9639  *
9640  * Indicates that an enabled internal peripheral was a source of exiting a
9641  * low-leakage power mode. To clear the flag, follow the internal peripheral flag
9642  * clearing mechanism.
9643  *
9644  * Values:
9645  * - 0b0 - Module 6 input was not a wakeup source
9646  * - 0b1 - Module 6 input was a wakeup source
9647  */
9648 /*@{*/
9649 /*! @brief Read current value of the LLWU_F3_MWUF6 field. */
9650 #define LLWU_RD_F3_MWUF6(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF6_MASK) >> LLWU_F3_MWUF6_SHIFT)
9651 #define LLWU_BRD_F3_MWUF6(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF6_SHIFT, LLWU_F3_MWUF6_WIDTH))
9652 /*@}*/
9653 
9654 /*!
9655  * @name Register LLWU_F3, field MWUF7[7] (RO)
9656  *
9657  * Indicates that an enabled internal peripheral was a source of exiting a
9658  * low-leakage power mode. To clear the flag, follow the internal peripheral flag
9659  * clearing mechanism.
9660  *
9661  * Values:
9662  * - 0b0 - Module 7 input was not a wakeup source
9663  * - 0b1 - Module 7 input was a wakeup source
9664  */
9665 /*@{*/
9666 /*! @brief Read current value of the LLWU_F3_MWUF7 field. */
9667 #define LLWU_RD_F3_MWUF7(base) ((LLWU_F3_REG(base) & LLWU_F3_MWUF7_MASK) >> LLWU_F3_MWUF7_SHIFT)
9668 #define LLWU_BRD_F3_MWUF7(base) (BME_UBFX8(&LLWU_F3_REG(base), LLWU_F3_MWUF7_SHIFT, LLWU_F3_MWUF7_WIDTH))
9669 /*@}*/
9670 
9671 /*******************************************************************************
9672  * LLWU_FILT1 - LLWU Pin Filter 1 register
9673  ******************************************************************************/
9674 
9675 /*!
9676  * @brief LLWU_FILT1 - LLWU Pin Filter 1 register (RW)
9677  *
9678  * Reset value: 0x00U
9679  *
9680  * LLWU_FILT1 is a control and status register that is used to enable/disable
9681  * the digital filter 1 features for an external pin. This register is reset on
9682  * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
9683  * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
9684  * IntroductionInformation found here describes the registers of the Reset Control
9685  * Module (RCM). The RCM implements many of the reset functions for the chip. See
9686  * the chip's reset chapter for more information. details for more information.
9687  */
9688 /*!
9689  * @name Constants and macros for entire LLWU_FILT1 register
9690  */
9691 /*@{*/
9692 #define LLWU_RD_FILT1(base)      (LLWU_FILT1_REG(base))
9693 #define LLWU_WR_FILT1(base, value) (LLWU_FILT1_REG(base) = (value))
9694 #define LLWU_RMW_FILT1(base, mask, value) (LLWU_WR_FILT1(base, (LLWU_RD_FILT1(base) & ~(mask)) | (value)))
9695 #define LLWU_SET_FILT1(base, value) (BME_OR8(&LLWU_FILT1_REG(base), (uint8_t)(value)))
9696 #define LLWU_CLR_FILT1(base, value) (BME_AND8(&LLWU_FILT1_REG(base), (uint8_t)(~(value))))
9697 #define LLWU_TOG_FILT1(base, value) (BME_XOR8(&LLWU_FILT1_REG(base), (uint8_t)(value)))
9698 /*@}*/
9699 
9700 /*
9701  * Constants & macros for individual LLWU_FILT1 bitfields
9702  */
9703 
9704 /*!
9705  * @name Register LLWU_FILT1, field FILTSEL[3:0] (RW)
9706  *
9707  * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
9708  *
9709  * Values:
9710  * - 0b0000 - Select LLWU_P0 for filter
9711  * - 0b1111 - Select LLWU_P15 for filter
9712  */
9713 /*@{*/
9714 /*! @brief Read current value of the LLWU_FILT1_FILTSEL field. */
9715 #define LLWU_RD_FILT1_FILTSEL(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTSEL_MASK) >> LLWU_FILT1_FILTSEL_SHIFT)
9716 #define LLWU_BRD_FILT1_FILTSEL(base) (BME_UBFX8(&LLWU_FILT1_REG(base), LLWU_FILT1_FILTSEL_SHIFT, LLWU_FILT1_FILTSEL_WIDTH))
9717 
9718 /*! @brief Set the FILTSEL field to a new value. */
9719 #define LLWU_WR_FILT1_FILTSEL(base, value) (LLWU_RMW_FILT1(base, (LLWU_FILT1_FILTSEL_MASK | LLWU_FILT1_FILTF_MASK), LLWU_FILT1_FILTSEL(value)))
9720 #define LLWU_BWR_FILT1_FILTSEL(base, value) (BME_BFI8(&LLWU_FILT1_REG(base), ((uint8_t)(value) << LLWU_FILT1_FILTSEL_SHIFT), LLWU_FILT1_FILTSEL_SHIFT, LLWU_FILT1_FILTSEL_WIDTH))
9721 /*@}*/
9722 
9723 /*!
9724  * @name Register LLWU_FILT1, field FILTE[6:5] (RW)
9725  *
9726  * Controls the digital filter options for the external pin detect.
9727  *
9728  * Values:
9729  * - 0b00 - Filter disabled
9730  * - 0b01 - Filter posedge detect enabled
9731  * - 0b10 - Filter negedge detect enabled
9732  * - 0b11 - Filter any edge detect enabled
9733  */
9734 /*@{*/
9735 /*! @brief Read current value of the LLWU_FILT1_FILTE field. */
9736 #define LLWU_RD_FILT1_FILTE(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTE_MASK) >> LLWU_FILT1_FILTE_SHIFT)
9737 #define LLWU_BRD_FILT1_FILTE(base) (BME_UBFX8(&LLWU_FILT1_REG(base), LLWU_FILT1_FILTE_SHIFT, LLWU_FILT1_FILTE_WIDTH))
9738 
9739 /*! @brief Set the FILTE field to a new value. */
9740 #define LLWU_WR_FILT1_FILTE(base, value) (LLWU_RMW_FILT1(base, (LLWU_FILT1_FILTE_MASK | LLWU_FILT1_FILTF_MASK), LLWU_FILT1_FILTE(value)))
9741 #define LLWU_BWR_FILT1_FILTE(base, value) (BME_BFI8(&LLWU_FILT1_REG(base), ((uint8_t)(value) << LLWU_FILT1_FILTE_SHIFT), LLWU_FILT1_FILTE_SHIFT, LLWU_FILT1_FILTE_WIDTH))
9742 /*@}*/
9743 
9744 /*!
9745  * @name Register LLWU_FILT1, field FILTF[7] (W1C)
9746  *
9747  * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
9748  * source of exiting a low-leakage power mode. To clear the flag write a one to
9749  * FILTF.
9750  *
9751  * Values:
9752  * - 0b0 - Pin Filter 1 was not a wakeup source
9753  * - 0b1 - Pin Filter 1 was a wakeup source
9754  */
9755 /*@{*/
9756 /*! @brief Read current value of the LLWU_FILT1_FILTF field. */
9757 #define LLWU_RD_FILT1_FILTF(base) ((LLWU_FILT1_REG(base) & LLWU_FILT1_FILTF_MASK) >> LLWU_FILT1_FILTF_SHIFT)
9758 #define LLWU_BRD_FILT1_FILTF(base) (BME_UBFX8(&LLWU_FILT1_REG(base), LLWU_FILT1_FILTF_SHIFT, LLWU_FILT1_FILTF_WIDTH))
9759 
9760 /*! @brief Set the FILTF field to a new value. */
9761 #define LLWU_WR_FILT1_FILTF(base, value) (LLWU_RMW_FILT1(base, LLWU_FILT1_FILTF_MASK, LLWU_FILT1_FILTF(value)))
9762 #define LLWU_BWR_FILT1_FILTF(base, value) (BME_BFI8(&LLWU_FILT1_REG(base), ((uint8_t)(value) << LLWU_FILT1_FILTF_SHIFT), LLWU_FILT1_FILTF_SHIFT, LLWU_FILT1_FILTF_WIDTH))
9763 /*@}*/
9764 
9765 /*******************************************************************************
9766  * LLWU_FILT2 - LLWU Pin Filter 2 register
9767  ******************************************************************************/
9768 
9769 /*!
9770  * @brief LLWU_FILT2 - LLWU Pin Filter 2 register (RW)
9771  *
9772  * Reset value: 0x00U
9773  *
9774  * LLWU_FILT2 is a control and status register that is used to enable/disable
9775  * the digital filter 2 features for an external pin. This register is reset on
9776  * Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is
9777  * unaffected by reset types that do not trigger Chip Reset not VLLS. See the
9778  * IntroductionInformation found here describes the registers of the Reset Control
9779  * Module (RCM). The RCM implements many of the reset functions for the chip. See
9780  * the chip's reset chapter for more information. details for more information.
9781  */
9782 /*!
9783  * @name Constants and macros for entire LLWU_FILT2 register
9784  */
9785 /*@{*/
9786 #define LLWU_RD_FILT2(base)      (LLWU_FILT2_REG(base))
9787 #define LLWU_WR_FILT2(base, value) (LLWU_FILT2_REG(base) = (value))
9788 #define LLWU_RMW_FILT2(base, mask, value) (LLWU_WR_FILT2(base, (LLWU_RD_FILT2(base) & ~(mask)) | (value)))
9789 #define LLWU_SET_FILT2(base, value) (BME_OR8(&LLWU_FILT2_REG(base), (uint8_t)(value)))
9790 #define LLWU_CLR_FILT2(base, value) (BME_AND8(&LLWU_FILT2_REG(base), (uint8_t)(~(value))))
9791 #define LLWU_TOG_FILT2(base, value) (BME_XOR8(&LLWU_FILT2_REG(base), (uint8_t)(value)))
9792 /*@}*/
9793 
9794 /*
9795  * Constants & macros for individual LLWU_FILT2 bitfields
9796  */
9797 
9798 /*!
9799  * @name Register LLWU_FILT2, field FILTSEL[3:0] (RW)
9800  *
9801  * Selects 1 out of the 16 wakeup pins to be muxed into the filter.
9802  *
9803  * Values:
9804  * - 0b0000 - Select LLWU_P0 for filter
9805  * - 0b1111 - Select LLWU_P15 for filter
9806  */
9807 /*@{*/
9808 /*! @brief Read current value of the LLWU_FILT2_FILTSEL field. */
9809 #define LLWU_RD_FILT2_FILTSEL(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTSEL_MASK) >> LLWU_FILT2_FILTSEL_SHIFT)
9810 #define LLWU_BRD_FILT2_FILTSEL(base) (BME_UBFX8(&LLWU_FILT2_REG(base), LLWU_FILT2_FILTSEL_SHIFT, LLWU_FILT2_FILTSEL_WIDTH))
9811 
9812 /*! @brief Set the FILTSEL field to a new value. */
9813 #define LLWU_WR_FILT2_FILTSEL(base, value) (LLWU_RMW_FILT2(base, (LLWU_FILT2_FILTSEL_MASK | LLWU_FILT2_FILTF_MASK), LLWU_FILT2_FILTSEL(value)))
9814 #define LLWU_BWR_FILT2_FILTSEL(base, value) (BME_BFI8(&LLWU_FILT2_REG(base), ((uint8_t)(value) << LLWU_FILT2_FILTSEL_SHIFT), LLWU_FILT2_FILTSEL_SHIFT, LLWU_FILT2_FILTSEL_WIDTH))
9815 /*@}*/
9816 
9817 /*!
9818  * @name Register LLWU_FILT2, field FILTE[6:5] (RW)
9819  *
9820  * Controls the digital filter options for the external pin detect.
9821  *
9822  * Values:
9823  * - 0b00 - Filter disabled
9824  * - 0b01 - Filter posedge detect enabled
9825  * - 0b10 - Filter negedge detect enabled
9826  * - 0b11 - Filter any edge detect enabled
9827  */
9828 /*@{*/
9829 /*! @brief Read current value of the LLWU_FILT2_FILTE field. */
9830 #define LLWU_RD_FILT2_FILTE(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTE_MASK) >> LLWU_FILT2_FILTE_SHIFT)
9831 #define LLWU_BRD_FILT2_FILTE(base) (BME_UBFX8(&LLWU_FILT2_REG(base), LLWU_FILT2_FILTE_SHIFT, LLWU_FILT2_FILTE_WIDTH))
9832 
9833 /*! @brief Set the FILTE field to a new value. */
9834 #define LLWU_WR_FILT2_FILTE(base, value) (LLWU_RMW_FILT2(base, (LLWU_FILT2_FILTE_MASK | LLWU_FILT2_FILTF_MASK), LLWU_FILT2_FILTE(value)))
9835 #define LLWU_BWR_FILT2_FILTE(base, value) (BME_BFI8(&LLWU_FILT2_REG(base), ((uint8_t)(value) << LLWU_FILT2_FILTE_SHIFT), LLWU_FILT2_FILTE_SHIFT, LLWU_FILT2_FILTE_WIDTH))
9836 /*@}*/
9837 
9838 /*!
9839  * @name Register LLWU_FILT2, field FILTF[7] (W1C)
9840  *
9841  * Indicates that the filtered external wakeup pin, selected by FILTSEL, was a
9842  * source of exiting a low-leakage power mode. To clear the flag write a one to
9843  * FILTF.
9844  *
9845  * Values:
9846  * - 0b0 - Pin Filter 2 was not a wakeup source
9847  * - 0b1 - Pin Filter 2 was a wakeup source
9848  */
9849 /*@{*/
9850 /*! @brief Read current value of the LLWU_FILT2_FILTF field. */
9851 #define LLWU_RD_FILT2_FILTF(base) ((LLWU_FILT2_REG(base) & LLWU_FILT2_FILTF_MASK) >> LLWU_FILT2_FILTF_SHIFT)
9852 #define LLWU_BRD_FILT2_FILTF(base) (BME_UBFX8(&LLWU_FILT2_REG(base), LLWU_FILT2_FILTF_SHIFT, LLWU_FILT2_FILTF_WIDTH))
9853 
9854 /*! @brief Set the FILTF field to a new value. */
9855 #define LLWU_WR_FILT2_FILTF(base, value) (LLWU_RMW_FILT2(base, LLWU_FILT2_FILTF_MASK, LLWU_FILT2_FILTF(value)))
9856 #define LLWU_BWR_FILT2_FILTF(base, value) (BME_BFI8(&LLWU_FILT2_REG(base), ((uint8_t)(value) << LLWU_FILT2_FILTF_SHIFT), LLWU_FILT2_FILTF_SHIFT, LLWU_FILT2_FILTF_WIDTH))
9857 /*@}*/
9858 
9859 /*
9860  * MKW40Z4 LPTMR
9861  *
9862  * Low Power Timer
9863  *
9864  * Registers defined in this header file:
9865  * - LPTMR_CSR - Low Power Timer Control Status Register
9866  * - LPTMR_PSR - Low Power Timer Prescale Register
9867  * - LPTMR_CMR - Low Power Timer Compare Register
9868  * - LPTMR_CNR - Low Power Timer Counter Register
9869  */
9870 
9871 #define LPTMR_INSTANCE_COUNT (1U) /*!< Number of instances of the LPTMR module. */
9872 #define LPTMR0_IDX (0U) /*!< Instance number for LPTMR0. */
9873 
9874 /*******************************************************************************
9875  * LPTMR_CSR - Low Power Timer Control Status Register
9876  ******************************************************************************/
9877 
9878 /*!
9879  * @brief LPTMR_CSR - Low Power Timer Control Status Register (RW)
9880  *
9881  * Reset value: 0x00000000U
9882  */
9883 /*!
9884  * @name Constants and macros for entire LPTMR_CSR register
9885  */
9886 /*@{*/
9887 #define LPTMR_RD_CSR(base)       (LPTMR_CSR_REG(base))
9888 #define LPTMR_WR_CSR(base, value) (LPTMR_CSR_REG(base) = (value))
9889 #define LPTMR_RMW_CSR(base, mask, value) (LPTMR_WR_CSR(base, (LPTMR_RD_CSR(base) & ~(mask)) | (value)))
9890 #define LPTMR_SET_CSR(base, value) (BME_OR32(&LPTMR_CSR_REG(base), (uint32_t)(value)))
9891 #define LPTMR_CLR_CSR(base, value) (BME_AND32(&LPTMR_CSR_REG(base), (uint32_t)(~(value))))
9892 #define LPTMR_TOG_CSR(base, value) (BME_XOR32(&LPTMR_CSR_REG(base), (uint32_t)(value)))
9893 /*@}*/
9894 
9895 /*
9896  * Constants & macros for individual LPTMR_CSR bitfields
9897  */
9898 
9899 /*!
9900  * @name Register LPTMR_CSR, field TEN[0] (RW)
9901  *
9902  * When TEN is clear, it resets the LPTMR internal logic, including the CNR and
9903  * TCF. When TEN is set, the LPTMR is enabled. While writing 1 to this field,
9904  * CSR[5:1] must not be altered.
9905  *
9906  * Values:
9907  * - 0b0 - LPTMR is disabled and internal logic is reset.
9908  * - 0b1 - LPTMR is enabled.
9909  */
9910 /*@{*/
9911 /*! @brief Read current value of the LPTMR_CSR_TEN field. */
9912 #define LPTMR_RD_CSR_TEN(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TEN_MASK) >> LPTMR_CSR_TEN_SHIFT)
9913 #define LPTMR_BRD_CSR_TEN(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TEN_SHIFT, LPTMR_CSR_TEN_WIDTH))
9914 
9915 /*! @brief Set the TEN field to a new value. */
9916 #define LPTMR_WR_CSR_TEN(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TEN_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TEN(value)))
9917 #define LPTMR_BWR_CSR_TEN(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR_CSR_TEN_SHIFT), LPTMR_CSR_TEN_SHIFT, LPTMR_CSR_TEN_WIDTH))
9918 /*@}*/
9919 
9920 /*!
9921  * @name Register LPTMR_CSR, field TMS[1] (RW)
9922  *
9923  * Configures the mode of the LPTMR. TMS must be altered only when the LPTMR is
9924  * disabled.
9925  *
9926  * Values:
9927  * - 0b0 - Time Counter mode.
9928  * - 0b1 - Pulse Counter mode.
9929  */
9930 /*@{*/
9931 /*! @brief Read current value of the LPTMR_CSR_TMS field. */
9932 #define LPTMR_RD_CSR_TMS(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TMS_MASK) >> LPTMR_CSR_TMS_SHIFT)
9933 #define LPTMR_BRD_CSR_TMS(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TMS_SHIFT, LPTMR_CSR_TMS_WIDTH))
9934 
9935 /*! @brief Set the TMS field to a new value. */
9936 #define LPTMR_WR_CSR_TMS(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TMS_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TMS(value)))
9937 #define LPTMR_BWR_CSR_TMS(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR_CSR_TMS_SHIFT), LPTMR_CSR_TMS_SHIFT, LPTMR_CSR_TMS_WIDTH))
9938 /*@}*/
9939 
9940 /*!
9941  * @name Register LPTMR_CSR, field TFC[2] (RW)
9942  *
9943  * When clear, TFC configures the CNR to reset whenever TCF is set. When set,
9944  * TFC configures the CNR to reset on overflow. TFC must be altered only when the
9945  * LPTMR is disabled.
9946  *
9947  * Values:
9948  * - 0b0 - CNR is reset whenever TCF is set.
9949  * - 0b1 - CNR is reset on overflow.
9950  */
9951 /*@{*/
9952 /*! @brief Read current value of the LPTMR_CSR_TFC field. */
9953 #define LPTMR_RD_CSR_TFC(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TFC_MASK) >> LPTMR_CSR_TFC_SHIFT)
9954 #define LPTMR_BRD_CSR_TFC(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TFC_SHIFT, LPTMR_CSR_TFC_WIDTH))
9955 
9956 /*! @brief Set the TFC field to a new value. */
9957 #define LPTMR_WR_CSR_TFC(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TFC_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TFC(value)))
9958 #define LPTMR_BWR_CSR_TFC(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR_CSR_TFC_SHIFT), LPTMR_CSR_TFC_SHIFT, LPTMR_CSR_TFC_WIDTH))
9959 /*@}*/
9960 
9961 /*!
9962  * @name Register LPTMR_CSR, field TPP[3] (RW)
9963  *
9964  * Configures the polarity of the input source in Pulse Counter mode. TPP must
9965  * be changed only when the LPTMR is disabled.
9966  *
9967  * Values:
9968  * - 0b0 - Pulse Counter input source is active-high, and the CNR will increment
9969  *     on the rising-edge.
9970  * - 0b1 - Pulse Counter input source is active-low, and the CNR will increment
9971  *     on the falling-edge.
9972  */
9973 /*@{*/
9974 /*! @brief Read current value of the LPTMR_CSR_TPP field. */
9975 #define LPTMR_RD_CSR_TPP(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TPP_MASK) >> LPTMR_CSR_TPP_SHIFT)
9976 #define LPTMR_BRD_CSR_TPP(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TPP_SHIFT, LPTMR_CSR_TPP_WIDTH))
9977 
9978 /*! @brief Set the TPP field to a new value. */
9979 #define LPTMR_WR_CSR_TPP(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TPP_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TPP(value)))
9980 #define LPTMR_BWR_CSR_TPP(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR_CSR_TPP_SHIFT), LPTMR_CSR_TPP_SHIFT, LPTMR_CSR_TPP_WIDTH))
9981 /*@}*/
9982 
9983 /*!
9984  * @name Register LPTMR_CSR, field TPS[5:4] (RW)
9985  *
9986  * Configures the input source to be used in Pulse Counter mode. TPS must be
9987  * altered only when the LPTMR is disabled. The input connections vary by device.
9988  * See the chip configuration details for information on the connections to these
9989  * inputs.
9990  *
9991  * Values:
9992  * - 0b00 - Pulse counter input 0 is selected.
9993  * - 0b01 - Pulse counter input 1 is selected.
9994  * - 0b10 - Pulse counter input 2 is selected.
9995  * - 0b11 - Pulse counter input 3 is selected.
9996  */
9997 /*@{*/
9998 /*! @brief Read current value of the LPTMR_CSR_TPS field. */
9999 #define LPTMR_RD_CSR_TPS(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TPS_MASK) >> LPTMR_CSR_TPS_SHIFT)
10000 #define LPTMR_BRD_CSR_TPS(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TPS_SHIFT, LPTMR_CSR_TPS_WIDTH))
10001 
10002 /*! @brief Set the TPS field to a new value. */
10003 #define LPTMR_WR_CSR_TPS(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TPS_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TPS(value)))
10004 #define LPTMR_BWR_CSR_TPS(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR_CSR_TPS_SHIFT), LPTMR_CSR_TPS_SHIFT, LPTMR_CSR_TPS_WIDTH))
10005 /*@}*/
10006 
10007 /*!
10008  * @name Register LPTMR_CSR, field TIE[6] (RW)
10009  *
10010  * When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
10011  *
10012  * Values:
10013  * - 0b0 - Timer interrupt disabled.
10014  * - 0b1 - Timer interrupt enabled.
10015  */
10016 /*@{*/
10017 /*! @brief Read current value of the LPTMR_CSR_TIE field. */
10018 #define LPTMR_RD_CSR_TIE(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TIE_MASK) >> LPTMR_CSR_TIE_SHIFT)
10019 #define LPTMR_BRD_CSR_TIE(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TIE_SHIFT, LPTMR_CSR_TIE_WIDTH))
10020 
10021 /*! @brief Set the TIE field to a new value. */
10022 #define LPTMR_WR_CSR_TIE(base, value) (LPTMR_RMW_CSR(base, (LPTMR_CSR_TIE_MASK | LPTMR_CSR_TCF_MASK), LPTMR_CSR_TIE(value)))
10023 #define LPTMR_BWR_CSR_TIE(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR_CSR_TIE_SHIFT), LPTMR_CSR_TIE_SHIFT, LPTMR_CSR_TIE_WIDTH))
10024 /*@}*/
10025 
10026 /*!
10027  * @name Register LPTMR_CSR, field TCF[7] (W1C)
10028  *
10029  * TCF is set when the LPTMR is enabled and the CNR equals the CMR and
10030  * increments. TCF is cleared when the LPTMR is disabled or a logic 1 is written to it.
10031  *
10032  * Values:
10033  * - 0b0 - The value of CNR is not equal to CMR and increments.
10034  * - 0b1 - The value of CNR is equal to CMR and increments.
10035  */
10036 /*@{*/
10037 /*! @brief Read current value of the LPTMR_CSR_TCF field. */
10038 #define LPTMR_RD_CSR_TCF(base) ((LPTMR_CSR_REG(base) & LPTMR_CSR_TCF_MASK) >> LPTMR_CSR_TCF_SHIFT)
10039 #define LPTMR_BRD_CSR_TCF(base) (BME_UBFX32(&LPTMR_CSR_REG(base), LPTMR_CSR_TCF_SHIFT, LPTMR_CSR_TCF_WIDTH))
10040 
10041 /*! @brief Set the TCF field to a new value. */
10042 #define LPTMR_WR_CSR_TCF(base, value) (LPTMR_RMW_CSR(base, LPTMR_CSR_TCF_MASK, LPTMR_CSR_TCF(value)))
10043 #define LPTMR_BWR_CSR_TCF(base, value) (BME_BFI32(&LPTMR_CSR_REG(base), ((uint32_t)(value) << LPTMR_CSR_TCF_SHIFT), LPTMR_CSR_TCF_SHIFT, LPTMR_CSR_TCF_WIDTH))
10044 /*@}*/
10045 
10046 /*******************************************************************************
10047  * LPTMR_PSR - Low Power Timer Prescale Register
10048  ******************************************************************************/
10049 
10050 /*!
10051  * @brief LPTMR_PSR - Low Power Timer Prescale Register (RW)
10052  *
10053  * Reset value: 0x00000000U
10054  */
10055 /*!
10056  * @name Constants and macros for entire LPTMR_PSR register
10057  */
10058 /*@{*/
10059 #define LPTMR_RD_PSR(base)       (LPTMR_PSR_REG(base))
10060 #define LPTMR_WR_PSR(base, value) (LPTMR_PSR_REG(base) = (value))
10061 #define LPTMR_RMW_PSR(base, mask, value) (LPTMR_WR_PSR(base, (LPTMR_RD_PSR(base) & ~(mask)) | (value)))
10062 #define LPTMR_SET_PSR(base, value) (BME_OR32(&LPTMR_PSR_REG(base), (uint32_t)(value)))
10063 #define LPTMR_CLR_PSR(base, value) (BME_AND32(&LPTMR_PSR_REG(base), (uint32_t)(~(value))))
10064 #define LPTMR_TOG_PSR(base, value) (BME_XOR32(&LPTMR_PSR_REG(base), (uint32_t)(value)))
10065 /*@}*/
10066 
10067 /*
10068  * Constants & macros for individual LPTMR_PSR bitfields
10069  */
10070 
10071 /*!
10072  * @name Register LPTMR_PSR, field PCS[1:0] (RW)
10073  *
10074  * Selects the clock to be used by the LPTMR prescaler/glitch filter. PCS must
10075  * be altered only when the LPTMR is disabled. The clock connections vary by
10076  * device. See the chip configuration details for information on the connections to
10077  * these inputs.
10078  *
10079  * Values:
10080  * - 0b00 - Prescaler/glitch filter clock 0 selected.
10081  * - 0b01 - Prescaler/glitch filter clock 1 selected.
10082  * - 0b10 - Prescaler/glitch filter clock 2 selected.
10083  * - 0b11 - Prescaler/glitch filter clock 3 selected.
10084  */
10085 /*@{*/
10086 /*! @brief Read current value of the LPTMR_PSR_PCS field. */
10087 #define LPTMR_RD_PSR_PCS(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PCS_MASK) >> LPTMR_PSR_PCS_SHIFT)
10088 #define LPTMR_BRD_PSR_PCS(base) (BME_UBFX32(&LPTMR_PSR_REG(base), LPTMR_PSR_PCS_SHIFT, LPTMR_PSR_PCS_WIDTH))
10089 
10090 /*! @brief Set the PCS field to a new value. */
10091 #define LPTMR_WR_PSR_PCS(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PCS_MASK, LPTMR_PSR_PCS(value)))
10092 #define LPTMR_BWR_PSR_PCS(base, value) (BME_BFI32(&LPTMR_PSR_REG(base), ((uint32_t)(value) << LPTMR_PSR_PCS_SHIFT), LPTMR_PSR_PCS_SHIFT, LPTMR_PSR_PCS_WIDTH))
10093 /*@}*/
10094 
10095 /*!
10096  * @name Register LPTMR_PSR, field PBYP[2] (RW)
10097  *
10098  * When PBYP is set, the selected prescaler clock in Time Counter mode or
10099  * selected input source in Pulse Counter mode directly clocks the CNR. When PBYP is
10100  * clear, the CNR is clocked by the output of the prescaler/glitch filter. PBYP
10101  * must be altered only when the LPTMR is disabled.
10102  *
10103  * Values:
10104  * - 0b0 - Prescaler/glitch filter is enabled.
10105  * - 0b1 - Prescaler/glitch filter is bypassed.
10106  */
10107 /*@{*/
10108 /*! @brief Read current value of the LPTMR_PSR_PBYP field. */
10109 #define LPTMR_RD_PSR_PBYP(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PBYP_MASK) >> LPTMR_PSR_PBYP_SHIFT)
10110 #define LPTMR_BRD_PSR_PBYP(base) (BME_UBFX32(&LPTMR_PSR_REG(base), LPTMR_PSR_PBYP_SHIFT, LPTMR_PSR_PBYP_WIDTH))
10111 
10112 /*! @brief Set the PBYP field to a new value. */
10113 #define LPTMR_WR_PSR_PBYP(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PBYP_MASK, LPTMR_PSR_PBYP(value)))
10114 #define LPTMR_BWR_PSR_PBYP(base, value) (BME_BFI32(&LPTMR_PSR_REG(base), ((uint32_t)(value) << LPTMR_PSR_PBYP_SHIFT), LPTMR_PSR_PBYP_SHIFT, LPTMR_PSR_PBYP_WIDTH))
10115 /*@}*/
10116 
10117 /*!
10118  * @name Register LPTMR_PSR, field PRESCALE[6:3] (RW)
10119  *
10120  * Configures the size of the Prescaler in Time Counter mode or width of the
10121  * glitch filter in Pulse Counter mode. PRESCALE must be altered only when the LPTMR
10122  * is disabled.
10123  *
10124  * Values:
10125  * - 0b0000 - Prescaler divides the prescaler clock by 2; glitch filter does not
10126  *     support this configuration.
10127  * - 0b0001 - Prescaler divides the prescaler clock by 4; glitch filter
10128  *     recognizes change on input pin after 2 rising clock edges.
10129  * - 0b0010 - Prescaler divides the prescaler clock by 8; glitch filter
10130  *     recognizes change on input pin after 4 rising clock edges.
10131  * - 0b0011 - Prescaler divides the prescaler clock by 16; glitch filter
10132  *     recognizes change on input pin after 8 rising clock edges.
10133  * - 0b0100 - Prescaler divides the prescaler clock by 32; glitch filter
10134  *     recognizes change on input pin after 16 rising clock edges.
10135  * - 0b0101 - Prescaler divides the prescaler clock by 64; glitch filter
10136  *     recognizes change on input pin after 32 rising clock edges.
10137  * - 0b0110 - Prescaler divides the prescaler clock by 128; glitch filter
10138  *     recognizes change on input pin after 64 rising clock edges.
10139  * - 0b0111 - Prescaler divides the prescaler clock by 256; glitch filter
10140  *     recognizes change on input pin after 128 rising clock edges.
10141  * - 0b1000 - Prescaler divides the prescaler clock by 512; glitch filter
10142  *     recognizes change on input pin after 256 rising clock edges.
10143  * - 0b1001 - Prescaler divides the prescaler clock by 1024; glitch filter
10144  *     recognizes change on input pin after 512 rising clock edges.
10145  * - 0b1010 - Prescaler divides the prescaler clock by 2048; glitch filter
10146  *     recognizes change on input pin after 1024 rising clock edges.
10147  * - 0b1011 - Prescaler divides the prescaler clock by 4096; glitch filter
10148  *     recognizes change on input pin after 2048 rising clock edges.
10149  * - 0b1100 - Prescaler divides the prescaler clock by 8192; glitch filter
10150  *     recognizes change on input pin after 4096 rising clock edges.
10151  * - 0b1101 - Prescaler divides the prescaler clock by 16,384; glitch filter
10152  *     recognizes change on input pin after 8192 rising clock edges.
10153  * - 0b1110 - Prescaler divides the prescaler clock by 32,768; glitch filter
10154  *     recognizes change on input pin after 16,384 rising clock edges.
10155  * - 0b1111 - Prescaler divides the prescaler clock by 65,536; glitch filter
10156  *     recognizes change on input pin after 32,768 rising clock edges.
10157  */
10158 /*@{*/
10159 /*! @brief Read current value of the LPTMR_PSR_PRESCALE field. */
10160 #define LPTMR_RD_PSR_PRESCALE(base) ((LPTMR_PSR_REG(base) & LPTMR_PSR_PRESCALE_MASK) >> LPTMR_PSR_PRESCALE_SHIFT)
10161 #define LPTMR_BRD_PSR_PRESCALE(base) (BME_UBFX32(&LPTMR_PSR_REG(base), LPTMR_PSR_PRESCALE_SHIFT, LPTMR_PSR_PRESCALE_WIDTH))
10162 
10163 /*! @brief Set the PRESCALE field to a new value. */
10164 #define LPTMR_WR_PSR_PRESCALE(base, value) (LPTMR_RMW_PSR(base, LPTMR_PSR_PRESCALE_MASK, LPTMR_PSR_PRESCALE(value)))
10165 #define LPTMR_BWR_PSR_PRESCALE(base, value) (BME_BFI32(&LPTMR_PSR_REG(base), ((uint32_t)(value) << LPTMR_PSR_PRESCALE_SHIFT), LPTMR_PSR_PRESCALE_SHIFT, LPTMR_PSR_PRESCALE_WIDTH))
10166 /*@}*/
10167 
10168 /*******************************************************************************
10169  * LPTMR_CMR - Low Power Timer Compare Register
10170  ******************************************************************************/
10171 
10172 /*!
10173  * @brief LPTMR_CMR - Low Power Timer Compare Register (RW)
10174  *
10175  * Reset value: 0x00000000U
10176  */
10177 /*!
10178  * @name Constants and macros for entire LPTMR_CMR register
10179  */
10180 /*@{*/
10181 #define LPTMR_RD_CMR(base)       (LPTMR_CMR_REG(base))
10182 #define LPTMR_WR_CMR(base, value) (LPTMR_CMR_REG(base) = (value))
10183 #define LPTMR_RMW_CMR(base, mask, value) (LPTMR_WR_CMR(base, (LPTMR_RD_CMR(base) & ~(mask)) | (value)))
10184 #define LPTMR_SET_CMR(base, value) (BME_OR32(&LPTMR_CMR_REG(base), (uint32_t)(value)))
10185 #define LPTMR_CLR_CMR(base, value) (BME_AND32(&LPTMR_CMR_REG(base), (uint32_t)(~(value))))
10186 #define LPTMR_TOG_CMR(base, value) (BME_XOR32(&LPTMR_CMR_REG(base), (uint32_t)(value)))
10187 /*@}*/
10188 
10189 /*
10190  * Constants & macros for individual LPTMR_CMR bitfields
10191  */
10192 
10193 /*!
10194  * @name Register LPTMR_CMR, field COMPARE[15:0] (RW)
10195  *
10196  * When the LPTMR is enabled and the CNR equals the value in the CMR and
10197  * increments, TCF is set and the hardware trigger asserts until the next time the CNR
10198  * increments. If the CMR is 0, the hardware trigger will remain asserted until
10199  * the LPTMR is disabled. If the LPTMR is enabled, the CMR must be altered only
10200  * when TCF is set.
10201  */
10202 /*@{*/
10203 /*! @brief Read current value of the LPTMR_CMR_COMPARE field. */
10204 #define LPTMR_RD_CMR_COMPARE(base) ((LPTMR_CMR_REG(base) & LPTMR_CMR_COMPARE_MASK) >> LPTMR_CMR_COMPARE_SHIFT)
10205 #define LPTMR_BRD_CMR_COMPARE(base) (BME_UBFX32(&LPTMR_CMR_REG(base), LPTMR_CMR_COMPARE_SHIFT, LPTMR_CMR_COMPARE_WIDTH))
10206 
10207 /*! @brief Set the COMPARE field to a new value. */
10208 #define LPTMR_WR_CMR_COMPARE(base, value) (LPTMR_RMW_CMR(base, LPTMR_CMR_COMPARE_MASK, LPTMR_CMR_COMPARE(value)))
10209 #define LPTMR_BWR_CMR_COMPARE(base, value) (BME_BFI32(&LPTMR_CMR_REG(base), ((uint32_t)(value) << LPTMR_CMR_COMPARE_SHIFT), LPTMR_CMR_COMPARE_SHIFT, LPTMR_CMR_COMPARE_WIDTH))
10210 /*@}*/
10211 
10212 /*******************************************************************************
10213  * LPTMR_CNR - Low Power Timer Counter Register
10214  ******************************************************************************/
10215 
10216 /*!
10217  * @brief LPTMR_CNR - Low Power Timer Counter Register (RW)
10218  *
10219  * Reset value: 0x00000000U
10220  */
10221 /*!
10222  * @name Constants and macros for entire LPTMR_CNR register
10223  */
10224 /*@{*/
10225 #define LPTMR_RD_CNR(base)       (LPTMR_CNR_REG(base))
10226 #define LPTMR_WR_CNR(base, value) (LPTMR_CNR_REG(base) = (value))
10227 #define LPTMR_RMW_CNR(base, mask, value) (LPTMR_WR_CNR(base, (LPTMR_RD_CNR(base) & ~(mask)) | (value)))
10228 #define LPTMR_SET_CNR(base, value) (BME_OR32(&LPTMR_CNR_REG(base), (uint32_t)(value)))
10229 #define LPTMR_CLR_CNR(base, value) (BME_AND32(&LPTMR_CNR_REG(base), (uint32_t)(~(value))))
10230 #define LPTMR_TOG_CNR(base, value) (BME_XOR32(&LPTMR_CNR_REG(base), (uint32_t)(value)))
10231 /*@}*/
10232 
10233 /*
10234  * Constants & macros for individual LPTMR_CNR bitfields
10235  */
10236 
10237 /*!
10238  * @name Register LPTMR_CNR, field COUNTER[15:0] (RW)
10239  */
10240 /*@{*/
10241 /*! @brief Read current value of the LPTMR_CNR_COUNTER field. */
10242 #define LPTMR_RD_CNR_COUNTER(base) ((LPTMR_CNR_REG(base) & LPTMR_CNR_COUNTER_MASK) >> LPTMR_CNR_COUNTER_SHIFT)
10243 #define LPTMR_BRD_CNR_COUNTER(base) (BME_UBFX32(&LPTMR_CNR_REG(base), LPTMR_CNR_COUNTER_SHIFT, LPTMR_CNR_COUNTER_WIDTH))
10244 
10245 /*! @brief Set the COUNTER field to a new value. */
10246 #define LPTMR_WR_CNR_COUNTER(base, value) (LPTMR_RMW_CNR(base, LPTMR_CNR_COUNTER_MASK, LPTMR_CNR_COUNTER(value)))
10247 #define LPTMR_BWR_CNR_COUNTER(base, value) (BME_BFI32(&LPTMR_CNR_REG(base), ((uint32_t)(value) << LPTMR_CNR_COUNTER_SHIFT), LPTMR_CNR_COUNTER_SHIFT, LPTMR_CNR_COUNTER_WIDTH))
10248 /*@}*/
10249 
10250 /*
10251  * MKW40Z4 LPUART
10252  *
10253  * Universal Asynchronous Receiver/Transmitter
10254  *
10255  * Registers defined in this header file:
10256  * - LPUART_BAUD - LPUART Baud Rate Register
10257  * - LPUART_STAT - LPUART Status Register
10258  * - LPUART_CTRL - LPUART Control Register
10259  * - LPUART_DATA - LPUART Data Register
10260  * - LPUART_MATCH - LPUART Match Address Register
10261  * - LPUART_MODIR - LPUART Modem IrDA Register
10262  */
10263 
10264 #define LPUART_INSTANCE_COUNT (1U) /*!< Number of instances of the LPUART module. */
10265 #define LPUART0_IDX (0U) /*!< Instance number for LPUART0. */
10266 
10267 /*******************************************************************************
10268  * LPUART_BAUD - LPUART Baud Rate Register
10269  ******************************************************************************/
10270 
10271 /*!
10272  * @brief LPUART_BAUD - LPUART Baud Rate Register (RW)
10273  *
10274  * Reset value: 0x0F000004U
10275  */
10276 /*!
10277  * @name Constants and macros for entire LPUART_BAUD register
10278  */
10279 /*@{*/
10280 #define LPUART_RD_BAUD(base)     (LPUART_BAUD_REG(base))
10281 #define LPUART_WR_BAUD(base, value) (LPUART_BAUD_REG(base) = (value))
10282 #define LPUART_RMW_BAUD(base, mask, value) (LPUART_WR_BAUD(base, (LPUART_RD_BAUD(base) & ~(mask)) | (value)))
10283 #define LPUART_SET_BAUD(base, value) (BME_OR32(&LPUART_BAUD_REG(base), (uint32_t)(value)))
10284 #define LPUART_CLR_BAUD(base, value) (BME_AND32(&LPUART_BAUD_REG(base), (uint32_t)(~(value))))
10285 #define LPUART_TOG_BAUD(base, value) (BME_XOR32(&LPUART_BAUD_REG(base), (uint32_t)(value)))
10286 /*@}*/
10287 
10288 /*
10289  * Constants & macros for individual LPUART_BAUD bitfields
10290  */
10291 
10292 /*!
10293  * @name Register LPUART_BAUD, field SBR[12:0] (RW)
10294  *
10295  * The 13 bits in SBR[12:0] set the modulo divide rate for the baud rate
10296  * generator. When SBR is 1 - 8191, the baud rate equals "baud clock / ((OSR+1) * SBR)".
10297  * The 13-bit baud rate setting [SBR12:SBR0] must only be updated when the
10298  * transmitter and receiver are both disabled (LPUART_CTRL[RE] and LPUART_CTRL[TE] are
10299  * both 0).
10300  */
10301 /*@{*/
10302 /*! @brief Read current value of the LPUART_BAUD_SBR field. */
10303 #define LPUART_RD_BAUD_SBR(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_SBR_MASK) >> LPUART_BAUD_SBR_SHIFT)
10304 #define LPUART_BRD_BAUD_SBR(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_SBR_SHIFT, LPUART_BAUD_SBR_WIDTH))
10305 
10306 /*! @brief Set the SBR field to a new value. */
10307 #define LPUART_WR_BAUD_SBR(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_SBR_MASK, LPUART_BAUD_SBR(value)))
10308 #define LPUART_BWR_BAUD_SBR(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_SBR_SHIFT), LPUART_BAUD_SBR_SHIFT, LPUART_BAUD_SBR_WIDTH))
10309 /*@}*/
10310 
10311 /*!
10312  * @name Register LPUART_BAUD, field SBNS[13] (RW)
10313  *
10314  * SBNS determines whether data characters are one or two stop bits. This bit
10315  * should only be changed when the transmitter and receiver are both disabled.
10316  *
10317  * Values:
10318  * - 0b0 - One stop bit.
10319  * - 0b1 - Two stop bits.
10320  */
10321 /*@{*/
10322 /*! @brief Read current value of the LPUART_BAUD_SBNS field. */
10323 #define LPUART_RD_BAUD_SBNS(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_SBNS_MASK) >> LPUART_BAUD_SBNS_SHIFT)
10324 #define LPUART_BRD_BAUD_SBNS(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_SBNS_SHIFT, LPUART_BAUD_SBNS_WIDTH))
10325 
10326 /*! @brief Set the SBNS field to a new value. */
10327 #define LPUART_WR_BAUD_SBNS(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_SBNS_MASK, LPUART_BAUD_SBNS(value)))
10328 #define LPUART_BWR_BAUD_SBNS(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_SBNS_SHIFT), LPUART_BAUD_SBNS_SHIFT, LPUART_BAUD_SBNS_WIDTH))
10329 /*@}*/
10330 
10331 /*!
10332  * @name Register LPUART_BAUD, field RXEDGIE[14] (RW)
10333  *
10334  * Enables the receive input active edge, RXEDGIF, to generate interrupt
10335  * requests. Changing CTRL[LOOP] or CTRL[RSRC] when RXEDGIE is set can cause the RXEDGIF
10336  * to set.
10337  *
10338  * Values:
10339  * - 0b0 - Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling).
10340  * - 0b1 - Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.
10341  */
10342 /*@{*/
10343 /*! @brief Read current value of the LPUART_BAUD_RXEDGIE field. */
10344 #define LPUART_RD_BAUD_RXEDGIE(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_RXEDGIE_MASK) >> LPUART_BAUD_RXEDGIE_SHIFT)
10345 #define LPUART_BRD_BAUD_RXEDGIE(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_RXEDGIE_SHIFT, LPUART_BAUD_RXEDGIE_WIDTH))
10346 
10347 /*! @brief Set the RXEDGIE field to a new value. */
10348 #define LPUART_WR_BAUD_RXEDGIE(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_RXEDGIE_MASK, LPUART_BAUD_RXEDGIE(value)))
10349 #define LPUART_BWR_BAUD_RXEDGIE(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_RXEDGIE_SHIFT), LPUART_BAUD_RXEDGIE_SHIFT, LPUART_BAUD_RXEDGIE_WIDTH))
10350 /*@}*/
10351 
10352 /*!
10353  * @name Register LPUART_BAUD, field LBKDIE[15] (RW)
10354  *
10355  * LBKDIE enables the LIN break detect flag, LBKDIF, to generate interrupt
10356  * requests.
10357  *
10358  * Values:
10359  * - 0b0 - Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).
10360  * - 0b1 - Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.
10361  */
10362 /*@{*/
10363 /*! @brief Read current value of the LPUART_BAUD_LBKDIE field. */
10364 #define LPUART_RD_BAUD_LBKDIE(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_LBKDIE_MASK) >> LPUART_BAUD_LBKDIE_SHIFT)
10365 #define LPUART_BRD_BAUD_LBKDIE(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_LBKDIE_SHIFT, LPUART_BAUD_LBKDIE_WIDTH))
10366 
10367 /*! @brief Set the LBKDIE field to a new value. */
10368 #define LPUART_WR_BAUD_LBKDIE(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_LBKDIE_MASK, LPUART_BAUD_LBKDIE(value)))
10369 #define LPUART_BWR_BAUD_LBKDIE(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_LBKDIE_SHIFT), LPUART_BAUD_LBKDIE_SHIFT, LPUART_BAUD_LBKDIE_WIDTH))
10370 /*@}*/
10371 
10372 /*!
10373  * @name Register LPUART_BAUD, field RESYNCDIS[16] (RW)
10374  *
10375  * When set, disables the resynchronization of the received data word when a
10376  * data one followed by data zero transition is detected. This bit should only be
10377  * changed when the receiver is disabled.
10378  *
10379  * Values:
10380  * - 0b0 - Resynchronization during received data word is supported
10381  * - 0b1 - Resynchronization during received data word is disabled
10382  */
10383 /*@{*/
10384 /*! @brief Read current value of the LPUART_BAUD_RESYNCDIS field. */
10385 #define LPUART_RD_BAUD_RESYNCDIS(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_RESYNCDIS_MASK) >> LPUART_BAUD_RESYNCDIS_SHIFT)
10386 #define LPUART_BRD_BAUD_RESYNCDIS(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_RESYNCDIS_SHIFT, LPUART_BAUD_RESYNCDIS_WIDTH))
10387 
10388 /*! @brief Set the RESYNCDIS field to a new value. */
10389 #define LPUART_WR_BAUD_RESYNCDIS(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_RESYNCDIS_MASK, LPUART_BAUD_RESYNCDIS(value)))
10390 #define LPUART_BWR_BAUD_RESYNCDIS(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_RESYNCDIS_SHIFT), LPUART_BAUD_RESYNCDIS_SHIFT, LPUART_BAUD_RESYNCDIS_WIDTH))
10391 /*@}*/
10392 
10393 /*!
10394  * @name Register LPUART_BAUD, field BOTHEDGE[17] (RW)
10395  *
10396  * Enables sampling of the received data on both edges of the baud rate clock,
10397  * effectively doubling the number of times the receiver samples the input data
10398  * for a given oversampling ratio. This bit must be set for oversampling ratios
10399  * between x4 and x7 and is optional for higher oversampling ratios. This bit should
10400  * only be changed when the receiver is disabled.
10401  *
10402  * Values:
10403  * - 0b0 - Receiver samples input data using the rising edge of the baud rate
10404  *     clock.
10405  * - 0b1 - Receiver samples input data using the rising and falling edge of the
10406  *     baud rate clock.
10407  */
10408 /*@{*/
10409 /*! @brief Read current value of the LPUART_BAUD_BOTHEDGE field. */
10410 #define LPUART_RD_BAUD_BOTHEDGE(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_BOTHEDGE_MASK) >> LPUART_BAUD_BOTHEDGE_SHIFT)
10411 #define LPUART_BRD_BAUD_BOTHEDGE(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_BOTHEDGE_SHIFT, LPUART_BAUD_BOTHEDGE_WIDTH))
10412 
10413 /*! @brief Set the BOTHEDGE field to a new value. */
10414 #define LPUART_WR_BAUD_BOTHEDGE(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_BOTHEDGE_MASK, LPUART_BAUD_BOTHEDGE(value)))
10415 #define LPUART_BWR_BAUD_BOTHEDGE(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_BOTHEDGE_SHIFT), LPUART_BAUD_BOTHEDGE_SHIFT, LPUART_BAUD_BOTHEDGE_WIDTH))
10416 /*@}*/
10417 
10418 /*!
10419  * @name Register LPUART_BAUD, field MATCFG[19:18] (RW)
10420  *
10421  * Configures the match addressing mode used.
10422  *
10423  * Values:
10424  * - 0b00 - Address Match Wakeup
10425  * - 0b01 - Idle Match Wakeup
10426  * - 0b10 - Match On and Match Off
10427  * - 0b11 - Enables RWU on Data Match and Match On/Off for transmitter CTS input
10428  */
10429 /*@{*/
10430 /*! @brief Read current value of the LPUART_BAUD_MATCFG field. */
10431 #define LPUART_RD_BAUD_MATCFG(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_MATCFG_MASK) >> LPUART_BAUD_MATCFG_SHIFT)
10432 #define LPUART_BRD_BAUD_MATCFG(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_MATCFG_SHIFT, LPUART_BAUD_MATCFG_WIDTH))
10433 
10434 /*! @brief Set the MATCFG field to a new value. */
10435 #define LPUART_WR_BAUD_MATCFG(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_MATCFG_MASK, LPUART_BAUD_MATCFG(value)))
10436 #define LPUART_BWR_BAUD_MATCFG(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_MATCFG_SHIFT), LPUART_BAUD_MATCFG_SHIFT, LPUART_BAUD_MATCFG_WIDTH))
10437 /*@}*/
10438 
10439 /*!
10440  * @name Register LPUART_BAUD, field RDMAE[21] (RW)
10441  *
10442  * RDMAE configures the receiver data register full flag, LPUART_STAT[RDRF], to
10443  * generate a DMA request.
10444  *
10445  * Values:
10446  * - 0b0 - DMA request disabled.
10447  * - 0b1 - DMA request enabled.
10448  */
10449 /*@{*/
10450 /*! @brief Read current value of the LPUART_BAUD_RDMAE field. */
10451 #define LPUART_RD_BAUD_RDMAE(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_RDMAE_MASK) >> LPUART_BAUD_RDMAE_SHIFT)
10452 #define LPUART_BRD_BAUD_RDMAE(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_RDMAE_SHIFT, LPUART_BAUD_RDMAE_WIDTH))
10453 
10454 /*! @brief Set the RDMAE field to a new value. */
10455 #define LPUART_WR_BAUD_RDMAE(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_RDMAE_MASK, LPUART_BAUD_RDMAE(value)))
10456 #define LPUART_BWR_BAUD_RDMAE(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_RDMAE_SHIFT), LPUART_BAUD_RDMAE_SHIFT, LPUART_BAUD_RDMAE_WIDTH))
10457 /*@}*/
10458 
10459 /*!
10460  * @name Register LPUART_BAUD, field TDMAE[23] (RW)
10461  *
10462  * TDMAE configures the transmit data register empty flag, LPUART_STAT[TDRE], to
10463  * generate a DMA request.
10464  *
10465  * Values:
10466  * - 0b0 - DMA request disabled.
10467  * - 0b1 - DMA request enabled.
10468  */
10469 /*@{*/
10470 /*! @brief Read current value of the LPUART_BAUD_TDMAE field. */
10471 #define LPUART_RD_BAUD_TDMAE(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_TDMAE_MASK) >> LPUART_BAUD_TDMAE_SHIFT)
10472 #define LPUART_BRD_BAUD_TDMAE(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_TDMAE_SHIFT, LPUART_BAUD_TDMAE_WIDTH))
10473 
10474 /*! @brief Set the TDMAE field to a new value. */
10475 #define LPUART_WR_BAUD_TDMAE(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_TDMAE_MASK, LPUART_BAUD_TDMAE(value)))
10476 #define LPUART_BWR_BAUD_TDMAE(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_TDMAE_SHIFT), LPUART_BAUD_TDMAE_SHIFT, LPUART_BAUD_TDMAE_WIDTH))
10477 /*@}*/
10478 
10479 /*!
10480  * @name Register LPUART_BAUD, field OSR[28:24] (RW)
10481  *
10482  * This field configures the oversampling ratio for the receiver between 4x
10483  * (00011) and 32x (11111). Writing an invalid oversampling ratio will default to an
10484  * oversampling ratio of 16 (01111). This field should only be changed when the
10485  * transmitter and receiver are both disabled.
10486  */
10487 /*@{*/
10488 /*! @brief Read current value of the LPUART_BAUD_OSR field. */
10489 #define LPUART_RD_BAUD_OSR(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_OSR_MASK) >> LPUART_BAUD_OSR_SHIFT)
10490 #define LPUART_BRD_BAUD_OSR(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_OSR_SHIFT, LPUART_BAUD_OSR_WIDTH))
10491 
10492 /*! @brief Set the OSR field to a new value. */
10493 #define LPUART_WR_BAUD_OSR(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_OSR_MASK, LPUART_BAUD_OSR(value)))
10494 #define LPUART_BWR_BAUD_OSR(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_OSR_SHIFT), LPUART_BAUD_OSR_SHIFT, LPUART_BAUD_OSR_WIDTH))
10495 /*@}*/
10496 
10497 /*!
10498  * @name Register LPUART_BAUD, field M10[29] (RW)
10499  *
10500  * The M10 bit causes a tenth bit to be part of the serial transmission. This
10501  * bit should only be changed when the transmitter and receiver are both disabled.
10502  *
10503  * Values:
10504  * - 0b0 - Receiver and transmitter use 8-bit or 9-bit data characters.
10505  * - 0b1 - Receiver and transmitter use 10-bit data characters.
10506  */
10507 /*@{*/
10508 /*! @brief Read current value of the LPUART_BAUD_M10 field. */
10509 #define LPUART_RD_BAUD_M10(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_M10_MASK) >> LPUART_BAUD_M10_SHIFT)
10510 #define LPUART_BRD_BAUD_M10(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_M10_SHIFT, LPUART_BAUD_M10_WIDTH))
10511 
10512 /*! @brief Set the M10 field to a new value. */
10513 #define LPUART_WR_BAUD_M10(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_M10_MASK, LPUART_BAUD_M10(value)))
10514 #define LPUART_BWR_BAUD_M10(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_M10_SHIFT), LPUART_BAUD_M10_SHIFT, LPUART_BAUD_M10_WIDTH))
10515 /*@}*/
10516 
10517 /*!
10518  * @name Register LPUART_BAUD, field MAEN2[30] (RW)
10519  *
10520  * Values:
10521  * - 0b0 - Normal operation.
10522  * - 0b1 - Enables automatic address matching or data matching mode for
10523  *     MATCH[MA2].
10524  */
10525 /*@{*/
10526 /*! @brief Read current value of the LPUART_BAUD_MAEN2 field. */
10527 #define LPUART_RD_BAUD_MAEN2(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_MAEN2_MASK) >> LPUART_BAUD_MAEN2_SHIFT)
10528 #define LPUART_BRD_BAUD_MAEN2(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_MAEN2_SHIFT, LPUART_BAUD_MAEN2_WIDTH))
10529 
10530 /*! @brief Set the MAEN2 field to a new value. */
10531 #define LPUART_WR_BAUD_MAEN2(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_MAEN2_MASK, LPUART_BAUD_MAEN2(value)))
10532 #define LPUART_BWR_BAUD_MAEN2(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_MAEN2_SHIFT), LPUART_BAUD_MAEN2_SHIFT, LPUART_BAUD_MAEN2_WIDTH))
10533 /*@}*/
10534 
10535 /*!
10536  * @name Register LPUART_BAUD, field MAEN1[31] (RW)
10537  *
10538  * Values:
10539  * - 0b0 - Normal operation.
10540  * - 0b1 - Enables automatic address matching or data matching mode for
10541  *     MATCH[MA1].
10542  */
10543 /*@{*/
10544 /*! @brief Read current value of the LPUART_BAUD_MAEN1 field. */
10545 #define LPUART_RD_BAUD_MAEN1(base) ((LPUART_BAUD_REG(base) & LPUART_BAUD_MAEN1_MASK) >> LPUART_BAUD_MAEN1_SHIFT)
10546 #define LPUART_BRD_BAUD_MAEN1(base) (BME_UBFX32(&LPUART_BAUD_REG(base), LPUART_BAUD_MAEN1_SHIFT, LPUART_BAUD_MAEN1_WIDTH))
10547 
10548 /*! @brief Set the MAEN1 field to a new value. */
10549 #define LPUART_WR_BAUD_MAEN1(base, value) (LPUART_RMW_BAUD(base, LPUART_BAUD_MAEN1_MASK, LPUART_BAUD_MAEN1(value)))
10550 #define LPUART_BWR_BAUD_MAEN1(base, value) (BME_BFI32(&LPUART_BAUD_REG(base), ((uint32_t)(value) << LPUART_BAUD_MAEN1_SHIFT), LPUART_BAUD_MAEN1_SHIFT, LPUART_BAUD_MAEN1_WIDTH))
10551 /*@}*/
10552 
10553 /*******************************************************************************
10554  * LPUART_STAT - LPUART Status Register
10555  ******************************************************************************/
10556 
10557 /*!
10558  * @brief LPUART_STAT - LPUART Status Register (RW)
10559  *
10560  * Reset value: 0x00C00000U
10561  */
10562 /*!
10563  * @name Constants and macros for entire LPUART_STAT register
10564  */
10565 /*@{*/
10566 #define LPUART_RD_STAT(base)     (LPUART_STAT_REG(base))
10567 #define LPUART_WR_STAT(base, value) (LPUART_STAT_REG(base) = (value))
10568 #define LPUART_RMW_STAT(base, mask, value) (LPUART_WR_STAT(base, (LPUART_RD_STAT(base) & ~(mask)) | (value)))
10569 #define LPUART_SET_STAT(base, value) (BME_OR32(&LPUART_STAT_REG(base), (uint32_t)(value)))
10570 #define LPUART_CLR_STAT(base, value) (BME_AND32(&LPUART_STAT_REG(base), (uint32_t)(~(value))))
10571 #define LPUART_TOG_STAT(base, value) (BME_XOR32(&LPUART_STAT_REG(base), (uint32_t)(value)))
10572 /*@}*/
10573 
10574 /*
10575  * Constants & macros for individual LPUART_STAT bitfields
10576  */
10577 
10578 /*!
10579  * @name Register LPUART_STAT, field MA2F[14] (W1C)
10580  *
10581  * MA2F is set whenever the next character to be read from LPUART_DATA matches
10582  * MA2. To clear MA2F, write a logic one to the MA2F.
10583  *
10584  * Values:
10585  * - 0b0 - Received data is not equal to MA2
10586  * - 0b1 - Received data is equal to MA2
10587  */
10588 /*@{*/
10589 /*! @brief Read current value of the LPUART_STAT_MA2F field. */
10590 #define LPUART_RD_STAT_MA2F(base) ((LPUART_STAT_REG(base) & LPUART_STAT_MA2F_MASK) >> LPUART_STAT_MA2F_SHIFT)
10591 #define LPUART_BRD_STAT_MA2F(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_MA2F_SHIFT, LPUART_STAT_MA2F_WIDTH))
10592 
10593 /*! @brief Set the MA2F field to a new value. */
10594 #define LPUART_WR_STAT_MA2F(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_MA2F(value)))
10595 #define LPUART_BWR_STAT_MA2F(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_MA2F_SHIFT), LPUART_STAT_MA2F_SHIFT, LPUART_STAT_MA2F_WIDTH))
10596 /*@}*/
10597 
10598 /*!
10599  * @name Register LPUART_STAT, field MA1F[15] (W1C)
10600  *
10601  * MA1F is set whenever the next character to be read from LPUART_DATA matches
10602  * MA1. To clear MA1F, write a logic one to the MA1F.
10603  *
10604  * Values:
10605  * - 0b0 - Received data is not equal to MA1
10606  * - 0b1 - Received data is equal to MA1
10607  */
10608 /*@{*/
10609 /*! @brief Read current value of the LPUART_STAT_MA1F field. */
10610 #define LPUART_RD_STAT_MA1F(base) ((LPUART_STAT_REG(base) & LPUART_STAT_MA1F_MASK) >> LPUART_STAT_MA1F_SHIFT)
10611 #define LPUART_BRD_STAT_MA1F(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_MA1F_SHIFT, LPUART_STAT_MA1F_WIDTH))
10612 
10613 /*! @brief Set the MA1F field to a new value. */
10614 #define LPUART_WR_STAT_MA1F(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_MA1F_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_MA1F(value)))
10615 #define LPUART_BWR_STAT_MA1F(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_MA1F_SHIFT), LPUART_STAT_MA1F_SHIFT, LPUART_STAT_MA1F_WIDTH))
10616 /*@}*/
10617 
10618 /*!
10619  * @name Register LPUART_STAT, field PF[16] (W1C)
10620  *
10621  * PF is set whenever the next character to be read from LPUART_DATA was
10622  * received when parity is enabled (PE = 1) and the parity bit in the received character
10623  * does not agree with the expected parity value. To clear PF, write a logic one
10624  * to the PF.
10625  *
10626  * Values:
10627  * - 0b0 - No parity error.
10628  * - 0b1 - Parity error.
10629  */
10630 /*@{*/
10631 /*! @brief Read current value of the LPUART_STAT_PF field. */
10632 #define LPUART_RD_STAT_PF(base) ((LPUART_STAT_REG(base) & LPUART_STAT_PF_MASK) >> LPUART_STAT_PF_SHIFT)
10633 #define LPUART_BRD_STAT_PF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_PF_SHIFT, LPUART_STAT_PF_WIDTH))
10634 
10635 /*! @brief Set the PF field to a new value. */
10636 #define LPUART_WR_STAT_PF(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_PF_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_PF(value)))
10637 #define LPUART_BWR_STAT_PF(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_PF_SHIFT), LPUART_STAT_PF_SHIFT, LPUART_STAT_PF_WIDTH))
10638 /*@}*/
10639 
10640 /*!
10641  * @name Register LPUART_STAT, field FE[17] (W1C)
10642  *
10643  * FE is set whenever the next character to be read from LPUART_DATA was
10644  * received with logic 0 detected where a stop bit was expected. To clear NF, write
10645  * logic one to the NF.
10646  *
10647  * Values:
10648  * - 0b0 - No framing error detected. This does not guarantee the framing is
10649  *     correct.
10650  * - 0b1 - Framing error.
10651  */
10652 /*@{*/
10653 /*! @brief Read current value of the LPUART_STAT_FE field. */
10654 #define LPUART_RD_STAT_FE(base) ((LPUART_STAT_REG(base) & LPUART_STAT_FE_MASK) >> LPUART_STAT_FE_SHIFT)
10655 #define LPUART_BRD_STAT_FE(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_FE_SHIFT, LPUART_STAT_FE_WIDTH))
10656 
10657 /*! @brief Set the FE field to a new value. */
10658 #define LPUART_WR_STAT_FE(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_FE_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_FE(value)))
10659 #define LPUART_BWR_STAT_FE(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_FE_SHIFT), LPUART_STAT_FE_SHIFT, LPUART_STAT_FE_WIDTH))
10660 /*@}*/
10661 
10662 /*!
10663  * @name Register LPUART_STAT, field NF[18] (W1C)
10664  *
10665  * The advanced sampling technique used in the receiver takes three samples in
10666  * each of the received bits. If any of these samples disagrees with the rest of
10667  * the samples within any bit time in the frame then noise is detected for that
10668  * character. NF is set whenever the next character to be read from LPUART_DATA was
10669  * received with noise detected within the character. To clear NF, write logic
10670  * one to the NF.
10671  *
10672  * Values:
10673  * - 0b0 - No noise detected.
10674  * - 0b1 - Noise detected in the received character in LPUART_DATA.
10675  */
10676 /*@{*/
10677 /*! @brief Read current value of the LPUART_STAT_NF field. */
10678 #define LPUART_RD_STAT_NF(base) ((LPUART_STAT_REG(base) & LPUART_STAT_NF_MASK) >> LPUART_STAT_NF_SHIFT)
10679 #define LPUART_BRD_STAT_NF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_NF_SHIFT, LPUART_STAT_NF_WIDTH))
10680 
10681 /*! @brief Set the NF field to a new value. */
10682 #define LPUART_WR_STAT_NF(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_NF_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_NF(value)))
10683 #define LPUART_BWR_STAT_NF(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_NF_SHIFT), LPUART_STAT_NF_SHIFT, LPUART_STAT_NF_WIDTH))
10684 /*@}*/
10685 
10686 /*!
10687  * @name Register LPUART_STAT, field OR[19] (W1C)
10688  *
10689  * OR is set when software fails to prevent the receive data register from
10690  * overflowing with data. The OR bit is set immediately after the stop bit has been
10691  * completely received for the dataword that overflows the buffer and all the other
10692  * error flags (FE, NF, and PF) are prevented from setting. The data in the
10693  * shift register is lost, but the data already in the LPUART data registers is not
10694  * affected. If LBKDE is enabled and a LIN Break is detected, the OR field asserts
10695  * if LBKDIF is not cleared before the next data character is received. While
10696  * the OR flag is set, no additional data is stored in the data buffer even if
10697  * sufficient room exists. To clear OR, write logic 1 to the OR flag.
10698  *
10699  * Values:
10700  * - 0b0 - No overrun.
10701  * - 0b1 - Receive overrun (new LPUART data lost).
10702  */
10703 /*@{*/
10704 /*! @brief Read current value of the LPUART_STAT_OR field. */
10705 #define LPUART_RD_STAT_OR(base) ((LPUART_STAT_REG(base) & LPUART_STAT_OR_MASK) >> LPUART_STAT_OR_SHIFT)
10706 #define LPUART_BRD_STAT_OR(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_OR_SHIFT, LPUART_STAT_OR_WIDTH))
10707 
10708 /*! @brief Set the OR field to a new value. */
10709 #define LPUART_WR_STAT_OR(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_OR_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_OR(value)))
10710 #define LPUART_BWR_STAT_OR(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_OR_SHIFT), LPUART_STAT_OR_SHIFT, LPUART_STAT_OR_WIDTH))
10711 /*@}*/
10712 
10713 /*!
10714  * @name Register LPUART_STAT, field IDLE[20] (W1C)
10715  *
10716  * IDLE is set when the LPUART receive line becomes idle for a full character
10717  * time after a period of activity. When ILT is cleared, the receiver starts
10718  * counting idle bit times after the start bit. If the receive character is all 1s,
10719  * these bit times and the stop bits time count toward the full character time of
10720  * logic high, 10 to 13 bit times, needed for the receiver to detect an idle line.
10721  * When ILT is set, the receiver doesn't start counting idle bit times until
10722  * after the stop bits. The stop bits and any logic high bit times at the end of the
10723  * previous character do not count toward the full character time of logic high
10724  * needed for the receiver to detect an idle line. To clear IDLE, write logic 1 to
10725  * the IDLE flag. After IDLE has been cleared, it cannot become set again until
10726  * after a new character has been stored in the receive buffer or a LIN break
10727  * character has set the LBKDIF flag . IDLE is set only once even if the receive
10728  * line remains idle for an extended period.
10729  *
10730  * Values:
10731  * - 0b0 - No idle line detected.
10732  * - 0b1 - Idle line was detected.
10733  */
10734 /*@{*/
10735 /*! @brief Read current value of the LPUART_STAT_IDLE field. */
10736 #define LPUART_RD_STAT_IDLE(base) ((LPUART_STAT_REG(base) & LPUART_STAT_IDLE_MASK) >> LPUART_STAT_IDLE_SHIFT)
10737 #define LPUART_BRD_STAT_IDLE(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_IDLE_SHIFT, LPUART_STAT_IDLE_WIDTH))
10738 
10739 /*! @brief Set the IDLE field to a new value. */
10740 #define LPUART_WR_STAT_IDLE(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_IDLE_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_IDLE(value)))
10741 #define LPUART_BWR_STAT_IDLE(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_IDLE_SHIFT), LPUART_STAT_IDLE_SHIFT, LPUART_STAT_IDLE_WIDTH))
10742 /*@}*/
10743 
10744 /*!
10745  * @name Register LPUART_STAT, field RDRF[21] (RO)
10746  *
10747  * When the receive FIFO is enabled, RDRF is set when the number of datawords in
10748  * the receive buffer is equal to or more than the number indicated by
10749  * LPUART_WATER[RXWATER]. To clear RDRF, read LPUART_DATA until the number of datawords in
10750  * the receive data buffer is less than the number indicated by
10751  * LPUART_WATER[RXWATER]. When the receive FIFO is disabled,RDRF is set when the receive buffer
10752  * (LPUART_DATA) is full. To clear RDRF, read the LPUART_DATA register. A
10753  * character that is in the process of being received does not cause a change in RDRF
10754  * until the entire character is received. Even if RDRF is set, the character will
10755  * continue to be received until an overrun condition occurs once the entire
10756  * character is received.
10757  *
10758  * Values:
10759  * - 0b0 - Receive data buffer empty.
10760  * - 0b1 - Receive data buffer full.
10761  */
10762 /*@{*/
10763 /*! @brief Read current value of the LPUART_STAT_RDRF field. */
10764 #define LPUART_RD_STAT_RDRF(base) ((LPUART_STAT_REG(base) & LPUART_STAT_RDRF_MASK) >> LPUART_STAT_RDRF_SHIFT)
10765 #define LPUART_BRD_STAT_RDRF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_RDRF_SHIFT, LPUART_STAT_RDRF_WIDTH))
10766 /*@}*/
10767 
10768 /*!
10769  * @name Register LPUART_STAT, field TC[22] (RO)
10770  *
10771  * TC is cleared when there is a transmission in progress or when a preamble or
10772  * break character is loaded. TC is set when the transmit buffer is empty and no
10773  * data, preamble, or break character is being transmitted. When TC is set, the
10774  * transmit data output signal becomes idle (logic 1). TC is cleared by writing to
10775  * LPUART_DATA to transmit new data, queuing a preamble by clearing and then
10776  * setting LPUART_CTRL[TE], queuing a break character by writing 1 to
10777  * LPUART_CTRL[SBK].
10778  *
10779  * Values:
10780  * - 0b0 - Transmitter active (sending data, a preamble, or a break).
10781  * - 0b1 - Transmitter idle (transmission activity complete).
10782  */
10783 /*@{*/
10784 /*! @brief Read current value of the LPUART_STAT_TC field. */
10785 #define LPUART_RD_STAT_TC(base) ((LPUART_STAT_REG(base) & LPUART_STAT_TC_MASK) >> LPUART_STAT_TC_SHIFT)
10786 #define LPUART_BRD_STAT_TC(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_TC_SHIFT, LPUART_STAT_TC_WIDTH))
10787 /*@}*/
10788 
10789 /*!
10790  * @name Register LPUART_STAT, field TDRE[23] (RO)
10791  *
10792  * When the transmit FIFO is enabled, TDRE will set when the number of datawords
10793  * in the transmit FIFO (LPUART_DATA) is equal to or less than the number
10794  * indicated by LPUART_WATER[TXWATER]). To clear TDRE, write to the LPUART data
10795  * register (LPUART_DATA) until the number of words in the transmit FIFO is greater than
10796  * the number indicated by LPUART_WATER[TXWATER]. When the transmit FIFO is
10797  * disabled,TDRE will set when the transmit data register (LPUART_DATA) is empty. To
10798  * clear TDRE, write to the LPUART data register (LPUART_DATA). TDRE is not
10799  * affected by a character that is in the process of being transmitted, it is updated
10800  * at the start of each transmitted character.
10801  *
10802  * Values:
10803  * - 0b0 - Transmit data buffer full.
10804  * - 0b1 - Transmit data buffer empty.
10805  */
10806 /*@{*/
10807 /*! @brief Read current value of the LPUART_STAT_TDRE field. */
10808 #define LPUART_RD_STAT_TDRE(base) ((LPUART_STAT_REG(base) & LPUART_STAT_TDRE_MASK) >> LPUART_STAT_TDRE_SHIFT)
10809 #define LPUART_BRD_STAT_TDRE(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_TDRE_SHIFT, LPUART_STAT_TDRE_WIDTH))
10810 /*@}*/
10811 
10812 /*!
10813  * @name Register LPUART_STAT, field RAF[24] (RO)
10814  *
10815  * RAF is set when the receiver detects the beginning of a valid start bit, and
10816  * RAF is cleared automatically when the receiver detects an idle line.
10817  *
10818  * Values:
10819  * - 0b0 - LPUART receiver idle waiting for a start bit.
10820  * - 0b1 - LPUART receiver active (LPUART_RX input not idle).
10821  */
10822 /*@{*/
10823 /*! @brief Read current value of the LPUART_STAT_RAF field. */
10824 #define LPUART_RD_STAT_RAF(base) ((LPUART_STAT_REG(base) & LPUART_STAT_RAF_MASK) >> LPUART_STAT_RAF_SHIFT)
10825 #define LPUART_BRD_STAT_RAF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_RAF_SHIFT, LPUART_STAT_RAF_WIDTH))
10826 /*@}*/
10827 
10828 /*!
10829  * @name Register LPUART_STAT, field LBKDE[25] (RW)
10830  *
10831  * LBKDE selects a longer break character detection length. While LBKDE is set,
10832  * receive data is not stored in the receive data buffer.
10833  *
10834  * Values:
10835  * - 0b0 - Break character is detected at length 10 bit times (if M = 0, SBNS =
10836  *     0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1
10837  *     or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
10838  * - 0b1 - Break character is detected at length of 11 bit times (if M = 0, SBNS
10839  *     = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS
10840  *     = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).
10841  */
10842 /*@{*/
10843 /*! @brief Read current value of the LPUART_STAT_LBKDE field. */
10844 #define LPUART_RD_STAT_LBKDE(base) ((LPUART_STAT_REG(base) & LPUART_STAT_LBKDE_MASK) >> LPUART_STAT_LBKDE_SHIFT)
10845 #define LPUART_BRD_STAT_LBKDE(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_LBKDE_SHIFT, LPUART_STAT_LBKDE_WIDTH))
10846 
10847 /*! @brief Set the LBKDE field to a new value. */
10848 #define LPUART_WR_STAT_LBKDE(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_LBKDE_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_LBKDE(value)))
10849 #define LPUART_BWR_STAT_LBKDE(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_LBKDE_SHIFT), LPUART_STAT_LBKDE_SHIFT, LPUART_STAT_LBKDE_WIDTH))
10850 /*@}*/
10851 
10852 /*!
10853  * @name Register LPUART_STAT, field BRK13[26] (RW)
10854  *
10855  * BRK13 selects a longer transmitted break character length. Detection of a
10856  * framing error is not affected by the state of this bit. This bit should only be
10857  * changed when the transmitter is disabled.
10858  *
10859  * Values:
10860  * - 0b0 - Break character is transmitted with length of 10 bit times (if M = 0,
10861  *     SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1,
10862  *     SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
10863  * - 0b1 - Break character is transmitted with length of 13 bit times (if M = 0,
10864  *     SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1,
10865  *     SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).
10866  */
10867 /*@{*/
10868 /*! @brief Read current value of the LPUART_STAT_BRK13 field. */
10869 #define LPUART_RD_STAT_BRK13(base) ((LPUART_STAT_REG(base) & LPUART_STAT_BRK13_MASK) >> LPUART_STAT_BRK13_SHIFT)
10870 #define LPUART_BRD_STAT_BRK13(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_BRK13_SHIFT, LPUART_STAT_BRK13_WIDTH))
10871 
10872 /*! @brief Set the BRK13 field to a new value. */
10873 #define LPUART_WR_STAT_BRK13(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_BRK13_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_BRK13(value)))
10874 #define LPUART_BWR_STAT_BRK13(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_BRK13_SHIFT), LPUART_STAT_BRK13_SHIFT, LPUART_STAT_BRK13_WIDTH))
10875 /*@}*/
10876 
10877 /*!
10878  * @name Register LPUART_STAT, field RWUID[27] (RW)
10879  *
10880  * For RWU on idle character, RWUID controls whether the idle character that
10881  * wakes up the receiver sets the IDLE bit. For address match wakeup, RWUID controls
10882  * if the IDLE bit is set when the address does not match. This bit should only
10883  * be changed when the receiver is disabled.
10884  *
10885  * Values:
10886  * - 0b0 - During receive standby state (RWU = 1), the IDLE bit does not get set
10887  *     upon detection of an idle character. During address match wakeup, the
10888  *     IDLE bit does not get set when an address does not match.
10889  * - 0b1 - During receive standby state (RWU = 1), the IDLE bit gets set upon
10890  *     detection of an idle character. During address match wakeup, the IDLE bit
10891  *     does get set when an address does not match.
10892  */
10893 /*@{*/
10894 /*! @brief Read current value of the LPUART_STAT_RWUID field. */
10895 #define LPUART_RD_STAT_RWUID(base) ((LPUART_STAT_REG(base) & LPUART_STAT_RWUID_MASK) >> LPUART_STAT_RWUID_SHIFT)
10896 #define LPUART_BRD_STAT_RWUID(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_RWUID_SHIFT, LPUART_STAT_RWUID_WIDTH))
10897 
10898 /*! @brief Set the RWUID field to a new value. */
10899 #define LPUART_WR_STAT_RWUID(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_RWUID_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_RWUID(value)))
10900 #define LPUART_BWR_STAT_RWUID(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_RWUID_SHIFT), LPUART_STAT_RWUID_SHIFT, LPUART_STAT_RWUID_WIDTH))
10901 /*@}*/
10902 
10903 /*!
10904  * @name Register LPUART_STAT, field RXINV[28] (RW)
10905  *
10906  * Setting this bit reverses the polarity of the received data input. Setting
10907  * RXINV inverts the LPUART_RX input for all cases: data bits, start and stop bits,
10908  * break, and idle.
10909  *
10910  * Values:
10911  * - 0b0 - Receive data not inverted.
10912  * - 0b1 - Receive data inverted.
10913  */
10914 /*@{*/
10915 /*! @brief Read current value of the LPUART_STAT_RXINV field. */
10916 #define LPUART_RD_STAT_RXINV(base) ((LPUART_STAT_REG(base) & LPUART_STAT_RXINV_MASK) >> LPUART_STAT_RXINV_SHIFT)
10917 #define LPUART_BRD_STAT_RXINV(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_RXINV_SHIFT, LPUART_STAT_RXINV_WIDTH))
10918 
10919 /*! @brief Set the RXINV field to a new value. */
10920 #define LPUART_WR_STAT_RXINV(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_RXINV_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_RXINV(value)))
10921 #define LPUART_BWR_STAT_RXINV(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_RXINV_SHIFT), LPUART_STAT_RXINV_SHIFT, LPUART_STAT_RXINV_WIDTH))
10922 /*@}*/
10923 
10924 /*!
10925  * @name Register LPUART_STAT, field MSBF[29] (RW)
10926  *
10927  * Setting this bit reverses the order of the bits that are transmitted and
10928  * received on the wire. This bit does not affect the polarity of the bits, the
10929  * location of the parity bit or the location of the start or stop bits. This bit
10930  * should only be changed when the transmitter and receiver are both disabled.
10931  *
10932  * Values:
10933  * - 0b0 - LSB (bit0) is the first bit that is transmitted following the start
10934  *     bit. Further, the first bit received after the start bit is identified as
10935  *     bit0.
10936  * - 0b1 - MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted
10937  *     following the start bit depending on the setting of CTRL[M], CTRL[PE] and
10938  *     BAUD[M10]. Further, the first bit received after the start bit is
10939  *     identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and
10940  *     CTRL[PE].
10941  */
10942 /*@{*/
10943 /*! @brief Read current value of the LPUART_STAT_MSBF field. */
10944 #define LPUART_RD_STAT_MSBF(base) ((LPUART_STAT_REG(base) & LPUART_STAT_MSBF_MASK) >> LPUART_STAT_MSBF_SHIFT)
10945 #define LPUART_BRD_STAT_MSBF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_MSBF_SHIFT, LPUART_STAT_MSBF_WIDTH))
10946 
10947 /*! @brief Set the MSBF field to a new value. */
10948 #define LPUART_WR_STAT_MSBF(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_MSBF_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_MSBF(value)))
10949 #define LPUART_BWR_STAT_MSBF(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_MSBF_SHIFT), LPUART_STAT_MSBF_SHIFT, LPUART_STAT_MSBF_WIDTH))
10950 /*@}*/
10951 
10952 /*!
10953  * @name Register LPUART_STAT, field RXEDGIF[30] (W1C)
10954  *
10955  * RXEDGIF is set when an active edge, falling if RXINV = 0, rising if RXINV=1,
10956  * on the LPUART_RX pin occurs. RXEDGIF is cleared by writing a 1 to it.
10957  *
10958  * Values:
10959  * - 0b0 - No active edge on the receive pin has occurred.
10960  * - 0b1 - An active edge on the receive pin has occurred.
10961  */
10962 /*@{*/
10963 /*! @brief Read current value of the LPUART_STAT_RXEDGIF field. */
10964 #define LPUART_RD_STAT_RXEDGIF(base) ((LPUART_STAT_REG(base) & LPUART_STAT_RXEDGIF_MASK) >> LPUART_STAT_RXEDGIF_SHIFT)
10965 #define LPUART_BRD_STAT_RXEDGIF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_RXEDGIF_SHIFT, LPUART_STAT_RXEDGIF_WIDTH))
10966 
10967 /*! @brief Set the RXEDGIF field to a new value. */
10968 #define LPUART_WR_STAT_RXEDGIF(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_RXEDGIF_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_LBKDIF_MASK), LPUART_STAT_RXEDGIF(value)))
10969 #define LPUART_BWR_STAT_RXEDGIF(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_RXEDGIF_SHIFT), LPUART_STAT_RXEDGIF_SHIFT, LPUART_STAT_RXEDGIF_WIDTH))
10970 /*@}*/
10971 
10972 /*!
10973  * @name Register LPUART_STAT, field LBKDIF[31] (W1C)
10974  *
10975  * LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break
10976  * character is detected. LBKDIF is cleared by writing a 1 to it.
10977  *
10978  * Values:
10979  * - 0b0 - No LIN break character has been detected.
10980  * - 0b1 - LIN break character has been detected.
10981  */
10982 /*@{*/
10983 /*! @brief Read current value of the LPUART_STAT_LBKDIF field. */
10984 #define LPUART_RD_STAT_LBKDIF(base) ((LPUART_STAT_REG(base) & LPUART_STAT_LBKDIF_MASK) >> LPUART_STAT_LBKDIF_SHIFT)
10985 #define LPUART_BRD_STAT_LBKDIF(base) (BME_UBFX32(&LPUART_STAT_REG(base), LPUART_STAT_LBKDIF_SHIFT, LPUART_STAT_LBKDIF_WIDTH))
10986 
10987 /*! @brief Set the LBKDIF field to a new value. */
10988 #define LPUART_WR_STAT_LBKDIF(base, value) (LPUART_RMW_STAT(base, (LPUART_STAT_LBKDIF_MASK | LPUART_STAT_MA2F_MASK | LPUART_STAT_MA1F_MASK | LPUART_STAT_PF_MASK | LPUART_STAT_FE_MASK | LPUART_STAT_NF_MASK | LPUART_STAT_OR_MASK | LPUART_STAT_IDLE_MASK | LPUART_STAT_RXEDGIF_MASK), LPUART_STAT_LBKDIF(value)))
10989 #define LPUART_BWR_STAT_LBKDIF(base, value) (BME_BFI32(&LPUART_STAT_REG(base), ((uint32_t)(value) << LPUART_STAT_LBKDIF_SHIFT), LPUART_STAT_LBKDIF_SHIFT, LPUART_STAT_LBKDIF_WIDTH))
10990 /*@}*/
10991 
10992 /*******************************************************************************
10993  * LPUART_CTRL - LPUART Control Register
10994  ******************************************************************************/
10995 
10996 /*!
10997  * @brief LPUART_CTRL - LPUART Control Register (RW)
10998  *
10999  * Reset value: 0x00000000U
11000  *
11001  * This read/write register controls various optional features of the LPUART
11002  * system. This register should only be altered when the transmitter and receiver
11003  * are both disabled.
11004  */
11005 /*!
11006  * @name Constants and macros for entire LPUART_CTRL register
11007  */
11008 /*@{*/
11009 #define LPUART_RD_CTRL(base)     (LPUART_CTRL_REG(base))
11010 #define LPUART_WR_CTRL(base, value) (LPUART_CTRL_REG(base) = (value))
11011 #define LPUART_RMW_CTRL(base, mask, value) (LPUART_WR_CTRL(base, (LPUART_RD_CTRL(base) & ~(mask)) | (value)))
11012 #define LPUART_SET_CTRL(base, value) (BME_OR32(&LPUART_CTRL_REG(base), (uint32_t)(value)))
11013 #define LPUART_CLR_CTRL(base, value) (BME_AND32(&LPUART_CTRL_REG(base), (uint32_t)(~(value))))
11014 #define LPUART_TOG_CTRL(base, value) (BME_XOR32(&LPUART_CTRL_REG(base), (uint32_t)(value)))
11015 /*@}*/
11016 
11017 /*
11018  * Constants & macros for individual LPUART_CTRL bitfields
11019  */
11020 
11021 /*!
11022  * @name Register LPUART_CTRL, field PT[0] (RW)
11023  *
11024  * Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd
11025  * parity means the total number of 1s in the data character, including the
11026  * parity bit, is odd. Even parity means the total number of 1s in the data
11027  * character, including the parity bit, is even.
11028  *
11029  * Values:
11030  * - 0b0 - Even parity.
11031  * - 0b1 - Odd parity.
11032  */
11033 /*@{*/
11034 /*! @brief Read current value of the LPUART_CTRL_PT field. */
11035 #define LPUART_RD_CTRL_PT(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_PT_MASK) >> LPUART_CTRL_PT_SHIFT)
11036 #define LPUART_BRD_CTRL_PT(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_PT_SHIFT, LPUART_CTRL_PT_WIDTH))
11037 
11038 /*! @brief Set the PT field to a new value. */
11039 #define LPUART_WR_CTRL_PT(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_PT_MASK, LPUART_CTRL_PT(value)))
11040 #define LPUART_BWR_CTRL_PT(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_PT_SHIFT), LPUART_CTRL_PT_SHIFT, LPUART_CTRL_PT_WIDTH))
11041 /*@}*/
11042 
11043 /*!
11044  * @name Register LPUART_CTRL, field PE[1] (RW)
11045  *
11046  * Enables hardware parity generation and checking. When parity is enabled, the
11047  * bit immediately before the stop bit is treated as the parity bit.
11048  *
11049  * Values:
11050  * - 0b0 - No hardware parity generation or checking.
11051  * - 0b1 - Parity enabled.
11052  */
11053 /*@{*/
11054 /*! @brief Read current value of the LPUART_CTRL_PE field. */
11055 #define LPUART_RD_CTRL_PE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_PE_MASK) >> LPUART_CTRL_PE_SHIFT)
11056 #define LPUART_BRD_CTRL_PE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_PE_SHIFT, LPUART_CTRL_PE_WIDTH))
11057 
11058 /*! @brief Set the PE field to a new value. */
11059 #define LPUART_WR_CTRL_PE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_PE_MASK, LPUART_CTRL_PE(value)))
11060 #define LPUART_BWR_CTRL_PE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_PE_SHIFT), LPUART_CTRL_PE_SHIFT, LPUART_CTRL_PE_WIDTH))
11061 /*@}*/
11062 
11063 /*!
11064  * @name Register LPUART_CTRL, field ILT[2] (RW)
11065  *
11066  * Determines when the receiver starts counting logic 1s as idle character bits.
11067  * The count begins either after a valid start bit or after the stop bit. If the
11068  * count begins after the start bit, then a string of logic 1s preceding the
11069  * stop bit can cause false recognition of an idle character. Beginning the count
11070  * after the stop bit avoids false idle character recognition, but requires
11071  * properly synchronized transmissions. In case the LPUART is programmed with ILT = 1, a
11072  * logic 0 is automatically shifted after a received stop bit, therefore
11073  * resetting the idle count.
11074  *
11075  * Values:
11076  * - 0b0 - Idle character bit count starts after start bit.
11077  * - 0b1 - Idle character bit count starts after stop bit.
11078  */
11079 /*@{*/
11080 /*! @brief Read current value of the LPUART_CTRL_ILT field. */
11081 #define LPUART_RD_CTRL_ILT(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_ILT_MASK) >> LPUART_CTRL_ILT_SHIFT)
11082 #define LPUART_BRD_CTRL_ILT(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_ILT_SHIFT, LPUART_CTRL_ILT_WIDTH))
11083 
11084 /*! @brief Set the ILT field to a new value. */
11085 #define LPUART_WR_CTRL_ILT(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_ILT_MASK, LPUART_CTRL_ILT(value)))
11086 #define LPUART_BWR_CTRL_ILT(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_ILT_SHIFT), LPUART_CTRL_ILT_SHIFT, LPUART_CTRL_ILT_WIDTH))
11087 /*@}*/
11088 
11089 /*!
11090  * @name Register LPUART_CTRL, field WAKE[3] (RW)
11091  *
11092  * Determines which condition wakes the LPUART when RWU=1: Address mark in the
11093  * most significant bit position of a received data character, or An idle
11094  * condition on the receive pin input signal.
11095  *
11096  * Values:
11097  * - 0b0 - Configures RWU for idle-line wakeup.
11098  * - 0b1 - Configures RWU with address-mark wakeup.
11099  */
11100 /*@{*/
11101 /*! @brief Read current value of the LPUART_CTRL_WAKE field. */
11102 #define LPUART_RD_CTRL_WAKE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_WAKE_MASK) >> LPUART_CTRL_WAKE_SHIFT)
11103 #define LPUART_BRD_CTRL_WAKE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_WAKE_SHIFT, LPUART_CTRL_WAKE_WIDTH))
11104 
11105 /*! @brief Set the WAKE field to a new value. */
11106 #define LPUART_WR_CTRL_WAKE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_WAKE_MASK, LPUART_CTRL_WAKE(value)))
11107 #define LPUART_BWR_CTRL_WAKE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_WAKE_SHIFT), LPUART_CTRL_WAKE_SHIFT, LPUART_CTRL_WAKE_WIDTH))
11108 /*@}*/
11109 
11110 /*!
11111  * @name Register LPUART_CTRL, field M[4] (RW)
11112  *
11113  * Values:
11114  * - 0b0 - Receiver and transmitter use 8-bit data characters.
11115  * - 0b1 - Receiver and transmitter use 9-bit data characters.
11116  */
11117 /*@{*/
11118 /*! @brief Read current value of the LPUART_CTRL_M field. */
11119 #define LPUART_RD_CTRL_M(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_M_MASK) >> LPUART_CTRL_M_SHIFT)
11120 #define LPUART_BRD_CTRL_M(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_M_SHIFT, LPUART_CTRL_M_WIDTH))
11121 
11122 /*! @brief Set the M field to a new value. */
11123 #define LPUART_WR_CTRL_M(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_M_MASK, LPUART_CTRL_M(value)))
11124 #define LPUART_BWR_CTRL_M(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_M_SHIFT), LPUART_CTRL_M_SHIFT, LPUART_CTRL_M_WIDTH))
11125 /*@}*/
11126 
11127 /*!
11128  * @name Register LPUART_CTRL, field RSRC[5] (RW)
11129  *
11130  * This field has no meaning or effect unless the LOOPS field is set. When LOOPS
11131  * is set, the RSRC field determines the source for the receiver shift register
11132  * input.
11133  *
11134  * Values:
11135  * - 0b0 - Provided LOOPS is set, RSRC is cleared, selects internal loop back
11136  *     mode and the LPUART does not use the LPUART_RX pin.
11137  * - 0b1 - Single-wire LPUART mode where the LPUART_TX pin is connected to the
11138  *     transmitter output and receiver input.
11139  */
11140 /*@{*/
11141 /*! @brief Read current value of the LPUART_CTRL_RSRC field. */
11142 #define LPUART_RD_CTRL_RSRC(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_RSRC_MASK) >> LPUART_CTRL_RSRC_SHIFT)
11143 #define LPUART_BRD_CTRL_RSRC(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_RSRC_SHIFT, LPUART_CTRL_RSRC_WIDTH))
11144 
11145 /*! @brief Set the RSRC field to a new value. */
11146 #define LPUART_WR_CTRL_RSRC(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_RSRC_MASK, LPUART_CTRL_RSRC(value)))
11147 #define LPUART_BWR_CTRL_RSRC(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_RSRC_SHIFT), LPUART_CTRL_RSRC_SHIFT, LPUART_CTRL_RSRC_WIDTH))
11148 /*@}*/
11149 
11150 /*!
11151  * @name Register LPUART_CTRL, field DOZEEN[6] (RW)
11152  *
11153  * Values:
11154  * - 0b0 - LPUART is enabled in Doze mode.
11155  * - 0b1 - LPUART is disabled in Doze mode.
11156  */
11157 /*@{*/
11158 /*! @brief Read current value of the LPUART_CTRL_DOZEEN field. */
11159 #define LPUART_RD_CTRL_DOZEEN(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_DOZEEN_MASK) >> LPUART_CTRL_DOZEEN_SHIFT)
11160 #define LPUART_BRD_CTRL_DOZEEN(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_DOZEEN_SHIFT, LPUART_CTRL_DOZEEN_WIDTH))
11161 
11162 /*! @brief Set the DOZEEN field to a new value. */
11163 #define LPUART_WR_CTRL_DOZEEN(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_DOZEEN_MASK, LPUART_CTRL_DOZEEN(value)))
11164 #define LPUART_BWR_CTRL_DOZEEN(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_DOZEEN_SHIFT), LPUART_CTRL_DOZEEN_SHIFT, LPUART_CTRL_DOZEEN_WIDTH))
11165 /*@}*/
11166 
11167 /*!
11168  * @name Register LPUART_CTRL, field LOOPS[7] (RW)
11169  *
11170  * When LOOPS is set, the LPUART_RX pin is disconnected from the LPUART and the
11171  * transmitter output is internally connected to the receiver input. The
11172  * transmitter and the receiver must be enabled to use the loop function.
11173  *
11174  * Values:
11175  * - 0b0 - Normal operation - LPUART_RX and LPUART_TX use separate pins.
11176  * - 0b1 - Loop mode or single-wire mode where transmitter outputs are
11177  *     internally connected to receiver input (see RSRC bit).
11178  */
11179 /*@{*/
11180 /*! @brief Read current value of the LPUART_CTRL_LOOPS field. */
11181 #define LPUART_RD_CTRL_LOOPS(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_LOOPS_MASK) >> LPUART_CTRL_LOOPS_SHIFT)
11182 #define LPUART_BRD_CTRL_LOOPS(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_LOOPS_SHIFT, LPUART_CTRL_LOOPS_WIDTH))
11183 
11184 /*! @brief Set the LOOPS field to a new value. */
11185 #define LPUART_WR_CTRL_LOOPS(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_LOOPS_MASK, LPUART_CTRL_LOOPS(value)))
11186 #define LPUART_BWR_CTRL_LOOPS(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_LOOPS_SHIFT), LPUART_CTRL_LOOPS_SHIFT, LPUART_CTRL_LOOPS_WIDTH))
11187 /*@}*/
11188 
11189 /*!
11190  * @name Register LPUART_CTRL, field IDLECFG[10:8] (RW)
11191  *
11192  * Configures the number of idle characters that must be received before the
11193  * IDLE flag is set.
11194  *
11195  * Values:
11196  * - 0b000 - 1 idle character
11197  * - 0b001 - 2 idle characters
11198  * - 0b010 - 4 idle characters
11199  * - 0b011 - 8 idle characters
11200  * - 0b100 - 16 idle characters
11201  * - 0b101 - 32 idle characters
11202  * - 0b110 - 64 idle characters
11203  * - 0b111 - 128 idle characters
11204  */
11205 /*@{*/
11206 /*! @brief Read current value of the LPUART_CTRL_IDLECFG field. */
11207 #define LPUART_RD_CTRL_IDLECFG(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_IDLECFG_MASK) >> LPUART_CTRL_IDLECFG_SHIFT)
11208 #define LPUART_BRD_CTRL_IDLECFG(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_IDLECFG_SHIFT, LPUART_CTRL_IDLECFG_WIDTH))
11209 
11210 /*! @brief Set the IDLECFG field to a new value. */
11211 #define LPUART_WR_CTRL_IDLECFG(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_IDLECFG_MASK, LPUART_CTRL_IDLECFG(value)))
11212 #define LPUART_BWR_CTRL_IDLECFG(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_IDLECFG_SHIFT), LPUART_CTRL_IDLECFG_SHIFT, LPUART_CTRL_IDLECFG_WIDTH))
11213 /*@}*/
11214 
11215 /*!
11216  * @name Register LPUART_CTRL, field MA2IE[14] (RW)
11217  *
11218  * Values:
11219  * - 0b0 - MA2F interrupt disabled
11220  * - 0b1 - MA2F interrupt enabled
11221  */
11222 /*@{*/
11223 /*! @brief Read current value of the LPUART_CTRL_MA2IE field. */
11224 #define LPUART_RD_CTRL_MA2IE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_MA2IE_MASK) >> LPUART_CTRL_MA2IE_SHIFT)
11225 #define LPUART_BRD_CTRL_MA2IE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_MA2IE_SHIFT, LPUART_CTRL_MA2IE_WIDTH))
11226 
11227 /*! @brief Set the MA2IE field to a new value. */
11228 #define LPUART_WR_CTRL_MA2IE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_MA2IE_MASK, LPUART_CTRL_MA2IE(value)))
11229 #define LPUART_BWR_CTRL_MA2IE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_MA2IE_SHIFT), LPUART_CTRL_MA2IE_SHIFT, LPUART_CTRL_MA2IE_WIDTH))
11230 /*@}*/
11231 
11232 /*!
11233  * @name Register LPUART_CTRL, field MA1IE[15] (RW)
11234  *
11235  * Values:
11236  * - 0b0 - MA1F interrupt disabled
11237  * - 0b1 - MA1F interrupt enabled
11238  */
11239 /*@{*/
11240 /*! @brief Read current value of the LPUART_CTRL_MA1IE field. */
11241 #define LPUART_RD_CTRL_MA1IE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_MA1IE_MASK) >> LPUART_CTRL_MA1IE_SHIFT)
11242 #define LPUART_BRD_CTRL_MA1IE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_MA1IE_SHIFT, LPUART_CTRL_MA1IE_WIDTH))
11243 
11244 /*! @brief Set the MA1IE field to a new value. */
11245 #define LPUART_WR_CTRL_MA1IE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_MA1IE_MASK, LPUART_CTRL_MA1IE(value)))
11246 #define LPUART_BWR_CTRL_MA1IE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_MA1IE_SHIFT), LPUART_CTRL_MA1IE_SHIFT, LPUART_CTRL_MA1IE_WIDTH))
11247 /*@}*/
11248 
11249 /*!
11250  * @name Register LPUART_CTRL, field SBK[16] (RW)
11251  *
11252  * Writing a 1 and then a 0 to SBK queues a break character in the transmit data
11253  * stream. Additional break characters of 10 to 13, or 13 to 16 if
11254  * LPUART_STATBRK13] is set, bit times of logic 0 are queued as long as SBK is set. Depending
11255  * on the timing of the set and clear of SBK relative to the information
11256  * currently being transmitted, a second break character may be queued before software
11257  * clears SBK.
11258  *
11259  * Values:
11260  * - 0b0 - Normal transmitter operation.
11261  * - 0b1 - Queue break character(s) to be sent.
11262  */
11263 /*@{*/
11264 /*! @brief Read current value of the LPUART_CTRL_SBK field. */
11265 #define LPUART_RD_CTRL_SBK(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_SBK_MASK) >> LPUART_CTRL_SBK_SHIFT)
11266 #define LPUART_BRD_CTRL_SBK(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_SBK_SHIFT, LPUART_CTRL_SBK_WIDTH))
11267 
11268 /*! @brief Set the SBK field to a new value. */
11269 #define LPUART_WR_CTRL_SBK(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_SBK_MASK, LPUART_CTRL_SBK(value)))
11270 #define LPUART_BWR_CTRL_SBK(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_SBK_SHIFT), LPUART_CTRL_SBK_SHIFT, LPUART_CTRL_SBK_WIDTH))
11271 /*@}*/
11272 
11273 /*!
11274  * @name Register LPUART_CTRL, field RWU[17] (RW)
11275  *
11276  * This field can be set to place the LPUART receiver in a standby state. RWU
11277  * automatically clears when an RWU event occurs, that is, an IDLE event when
11278  * CTRL[WAKE] is clear or an address match when CTRL[WAKE] is set with STAT[RWUID] is
11279  * clear. RWU must be set only with CTRL[WAKE] = 0 (wakeup on idle) if the
11280  * channel is currently not idle. This can be determined by STAT[RAF]. If the flag is
11281  * set to wake up an IDLE event and the channel is already idle, it is possible
11282  * that the LPUART will discard data. This is because the data must be received or
11283  * a LIN break detected after an IDLE is detected before IDLE is allowed to be
11284  * reasserted.
11285  *
11286  * Values:
11287  * - 0b0 - Normal receiver operation.
11288  * - 0b1 - LPUART receiver in standby waiting for wakeup condition.
11289  */
11290 /*@{*/
11291 /*! @brief Read current value of the LPUART_CTRL_RWU field. */
11292 #define LPUART_RD_CTRL_RWU(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_RWU_MASK) >> LPUART_CTRL_RWU_SHIFT)
11293 #define LPUART_BRD_CTRL_RWU(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_RWU_SHIFT, LPUART_CTRL_RWU_WIDTH))
11294 
11295 /*! @brief Set the RWU field to a new value. */
11296 #define LPUART_WR_CTRL_RWU(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_RWU_MASK, LPUART_CTRL_RWU(value)))
11297 #define LPUART_BWR_CTRL_RWU(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_RWU_SHIFT), LPUART_CTRL_RWU_SHIFT, LPUART_CTRL_RWU_WIDTH))
11298 /*@}*/
11299 
11300 /*!
11301  * @name Register LPUART_CTRL, field RE[18] (RW)
11302  *
11303  * Enables the LPUART receiver. When RE is written to 0, this register bit will
11304  * read as 1 until the receiver finishes receiving the current character (if any).
11305  *
11306  * Values:
11307  * - 0b0 - Receiver disabled.
11308  * - 0b1 - Receiver enabled.
11309  */
11310 /*@{*/
11311 /*! @brief Read current value of the LPUART_CTRL_RE field. */
11312 #define LPUART_RD_CTRL_RE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_RE_MASK) >> LPUART_CTRL_RE_SHIFT)
11313 #define LPUART_BRD_CTRL_RE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_RE_SHIFT, LPUART_CTRL_RE_WIDTH))
11314 
11315 /*! @brief Set the RE field to a new value. */
11316 #define LPUART_WR_CTRL_RE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_RE_MASK, LPUART_CTRL_RE(value)))
11317 #define LPUART_BWR_CTRL_RE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_RE_SHIFT), LPUART_CTRL_RE_SHIFT, LPUART_CTRL_RE_WIDTH))
11318 /*@}*/
11319 
11320 /*!
11321  * @name Register LPUART_CTRL, field TE[19] (RW)
11322  *
11323  * Enables the LPUART transmitter. TE can also be used to queue an idle preamble
11324  * by clearing and then setting TE. When TE is cleared, this register bit will
11325  * read as 1 until the transmitter has completed the current character and the
11326  * LPUART_TX pin is tristated.
11327  *
11328  * Values:
11329  * - 0b0 - Transmitter disabled.
11330  * - 0b1 - Transmitter enabled.
11331  */
11332 /*@{*/
11333 /*! @brief Read current value of the LPUART_CTRL_TE field. */
11334 #define LPUART_RD_CTRL_TE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_TE_MASK) >> LPUART_CTRL_TE_SHIFT)
11335 #define LPUART_BRD_CTRL_TE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_TE_SHIFT, LPUART_CTRL_TE_WIDTH))
11336 
11337 /*! @brief Set the TE field to a new value. */
11338 #define LPUART_WR_CTRL_TE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_TE_MASK, LPUART_CTRL_TE(value)))
11339 #define LPUART_BWR_CTRL_TE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_TE_SHIFT), LPUART_CTRL_TE_SHIFT, LPUART_CTRL_TE_WIDTH))
11340 /*@}*/
11341 
11342 /*!
11343  * @name Register LPUART_CTRL, field ILIE[20] (RW)
11344  *
11345  * ILIE enables the idle line flag, STAT[IDLE], to generate interrupt requests.
11346  *
11347  * Values:
11348  * - 0b0 - Hardware interrupts from IDLE disabled; use polling.
11349  * - 0b1 - Hardware interrupt requested when IDLE flag is 1.
11350  */
11351 /*@{*/
11352 /*! @brief Read current value of the LPUART_CTRL_ILIE field. */
11353 #define LPUART_RD_CTRL_ILIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_ILIE_MASK) >> LPUART_CTRL_ILIE_SHIFT)
11354 #define LPUART_BRD_CTRL_ILIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_ILIE_SHIFT, LPUART_CTRL_ILIE_WIDTH))
11355 
11356 /*! @brief Set the ILIE field to a new value. */
11357 #define LPUART_WR_CTRL_ILIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_ILIE_MASK, LPUART_CTRL_ILIE(value)))
11358 #define LPUART_BWR_CTRL_ILIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_ILIE_SHIFT), LPUART_CTRL_ILIE_SHIFT, LPUART_CTRL_ILIE_WIDTH))
11359 /*@}*/
11360 
11361 /*!
11362  * @name Register LPUART_CTRL, field RIE[21] (RW)
11363  *
11364  * Enables STAT[RDRF] to generate interrupt requests.
11365  *
11366  * Values:
11367  * - 0b0 - Hardware interrupts from RDRF disabled; use polling.
11368  * - 0b1 - Hardware interrupt requested when RDRF flag is 1.
11369  */
11370 /*@{*/
11371 /*! @brief Read current value of the LPUART_CTRL_RIE field. */
11372 #define LPUART_RD_CTRL_RIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_RIE_MASK) >> LPUART_CTRL_RIE_SHIFT)
11373 #define LPUART_BRD_CTRL_RIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_RIE_SHIFT, LPUART_CTRL_RIE_WIDTH))
11374 
11375 /*! @brief Set the RIE field to a new value. */
11376 #define LPUART_WR_CTRL_RIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_RIE_MASK, LPUART_CTRL_RIE(value)))
11377 #define LPUART_BWR_CTRL_RIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_RIE_SHIFT), LPUART_CTRL_RIE_SHIFT, LPUART_CTRL_RIE_WIDTH))
11378 /*@}*/
11379 
11380 /*!
11381  * @name Register LPUART_CTRL, field TCIE[22] (RW)
11382  *
11383  * TCIE enables the transmission complete flag, TC, to generate interrupt
11384  * requests.
11385  *
11386  * Values:
11387  * - 0b0 - Hardware interrupts from TC disabled; use polling.
11388  * - 0b1 - Hardware interrupt requested when TC flag is 1.
11389  */
11390 /*@{*/
11391 /*! @brief Read current value of the LPUART_CTRL_TCIE field. */
11392 #define LPUART_RD_CTRL_TCIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_TCIE_MASK) >> LPUART_CTRL_TCIE_SHIFT)
11393 #define LPUART_BRD_CTRL_TCIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_TCIE_SHIFT, LPUART_CTRL_TCIE_WIDTH))
11394 
11395 /*! @brief Set the TCIE field to a new value. */
11396 #define LPUART_WR_CTRL_TCIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_TCIE_MASK, LPUART_CTRL_TCIE(value)))
11397 #define LPUART_BWR_CTRL_TCIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_TCIE_SHIFT), LPUART_CTRL_TCIE_SHIFT, LPUART_CTRL_TCIE_WIDTH))
11398 /*@}*/
11399 
11400 /*!
11401  * @name Register LPUART_CTRL, field TIE[23] (RW)
11402  *
11403  * Enables STAT[TDRE] to generate interrupt requests.
11404  *
11405  * Values:
11406  * - 0b0 - Hardware interrupts from TDRE disabled; use polling.
11407  * - 0b1 - Hardware interrupt requested when TDRE flag is 1.
11408  */
11409 /*@{*/
11410 /*! @brief Read current value of the LPUART_CTRL_TIE field. */
11411 #define LPUART_RD_CTRL_TIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_TIE_MASK) >> LPUART_CTRL_TIE_SHIFT)
11412 #define LPUART_BRD_CTRL_TIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_TIE_SHIFT, LPUART_CTRL_TIE_WIDTH))
11413 
11414 /*! @brief Set the TIE field to a new value. */
11415 #define LPUART_WR_CTRL_TIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_TIE_MASK, LPUART_CTRL_TIE(value)))
11416 #define LPUART_BWR_CTRL_TIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_TIE_SHIFT), LPUART_CTRL_TIE_SHIFT, LPUART_CTRL_TIE_WIDTH))
11417 /*@}*/
11418 
11419 /*!
11420  * @name Register LPUART_CTRL, field PEIE[24] (RW)
11421  *
11422  * This bit enables the parity error flag (PF) to generate hardware interrupt
11423  * requests.
11424  *
11425  * Values:
11426  * - 0b0 - PF interrupts disabled; use polling).
11427  * - 0b1 - Hardware interrupt requested when PF is set.
11428  */
11429 /*@{*/
11430 /*! @brief Read current value of the LPUART_CTRL_PEIE field. */
11431 #define LPUART_RD_CTRL_PEIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_PEIE_MASK) >> LPUART_CTRL_PEIE_SHIFT)
11432 #define LPUART_BRD_CTRL_PEIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_PEIE_SHIFT, LPUART_CTRL_PEIE_WIDTH))
11433 
11434 /*! @brief Set the PEIE field to a new value. */
11435 #define LPUART_WR_CTRL_PEIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_PEIE_MASK, LPUART_CTRL_PEIE(value)))
11436 #define LPUART_BWR_CTRL_PEIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_PEIE_SHIFT), LPUART_CTRL_PEIE_SHIFT, LPUART_CTRL_PEIE_WIDTH))
11437 /*@}*/
11438 
11439 /*!
11440  * @name Register LPUART_CTRL, field FEIE[25] (RW)
11441  *
11442  * This bit enables the framing error flag (FE) to generate hardware interrupt
11443  * requests.
11444  *
11445  * Values:
11446  * - 0b0 - FE interrupts disabled; use polling.
11447  * - 0b1 - Hardware interrupt requested when FE is set.
11448  */
11449 /*@{*/
11450 /*! @brief Read current value of the LPUART_CTRL_FEIE field. */
11451 #define LPUART_RD_CTRL_FEIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_FEIE_MASK) >> LPUART_CTRL_FEIE_SHIFT)
11452 #define LPUART_BRD_CTRL_FEIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_FEIE_SHIFT, LPUART_CTRL_FEIE_WIDTH))
11453 
11454 /*! @brief Set the FEIE field to a new value. */
11455 #define LPUART_WR_CTRL_FEIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_FEIE_MASK, LPUART_CTRL_FEIE(value)))
11456 #define LPUART_BWR_CTRL_FEIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_FEIE_SHIFT), LPUART_CTRL_FEIE_SHIFT, LPUART_CTRL_FEIE_WIDTH))
11457 /*@}*/
11458 
11459 /*!
11460  * @name Register LPUART_CTRL, field NEIE[26] (RW)
11461  *
11462  * This bit enables the noise flag (NF) to generate hardware interrupt requests.
11463  *
11464  * Values:
11465  * - 0b0 - NF interrupts disabled; use polling.
11466  * - 0b1 - Hardware interrupt requested when NF is set.
11467  */
11468 /*@{*/
11469 /*! @brief Read current value of the LPUART_CTRL_NEIE field. */
11470 #define LPUART_RD_CTRL_NEIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_NEIE_MASK) >> LPUART_CTRL_NEIE_SHIFT)
11471 #define LPUART_BRD_CTRL_NEIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_NEIE_SHIFT, LPUART_CTRL_NEIE_WIDTH))
11472 
11473 /*! @brief Set the NEIE field to a new value. */
11474 #define LPUART_WR_CTRL_NEIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_NEIE_MASK, LPUART_CTRL_NEIE(value)))
11475 #define LPUART_BWR_CTRL_NEIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_NEIE_SHIFT), LPUART_CTRL_NEIE_SHIFT, LPUART_CTRL_NEIE_WIDTH))
11476 /*@}*/
11477 
11478 /*!
11479  * @name Register LPUART_CTRL, field ORIE[27] (RW)
11480  *
11481  * This bit enables the overrun flag (OR) to generate hardware interrupt
11482  * requests.
11483  *
11484  * Values:
11485  * - 0b0 - OR interrupts disabled; use polling.
11486  * - 0b1 - Hardware interrupt requested when OR is set.
11487  */
11488 /*@{*/
11489 /*! @brief Read current value of the LPUART_CTRL_ORIE field. */
11490 #define LPUART_RD_CTRL_ORIE(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_ORIE_MASK) >> LPUART_CTRL_ORIE_SHIFT)
11491 #define LPUART_BRD_CTRL_ORIE(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_ORIE_SHIFT, LPUART_CTRL_ORIE_WIDTH))
11492 
11493 /*! @brief Set the ORIE field to a new value. */
11494 #define LPUART_WR_CTRL_ORIE(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_ORIE_MASK, LPUART_CTRL_ORIE(value)))
11495 #define LPUART_BWR_CTRL_ORIE(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_ORIE_SHIFT), LPUART_CTRL_ORIE_SHIFT, LPUART_CTRL_ORIE_WIDTH))
11496 /*@}*/
11497 
11498 /*!
11499  * @name Register LPUART_CTRL, field TXINV[28] (RW)
11500  *
11501  * Setting this bit reverses the polarity of the transmitted data output.
11502  * Setting TXINV inverts the LPUART_TX output for all cases: data bits, start and stop
11503  * bits, break, and idle.
11504  *
11505  * Values:
11506  * - 0b0 - Transmit data not inverted.
11507  * - 0b1 - Transmit data inverted.
11508  */
11509 /*@{*/
11510 /*! @brief Read current value of the LPUART_CTRL_TXINV field. */
11511 #define LPUART_RD_CTRL_TXINV(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_TXINV_MASK) >> LPUART_CTRL_TXINV_SHIFT)
11512 #define LPUART_BRD_CTRL_TXINV(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_TXINV_SHIFT, LPUART_CTRL_TXINV_WIDTH))
11513 
11514 /*! @brief Set the TXINV field to a new value. */
11515 #define LPUART_WR_CTRL_TXINV(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_TXINV_MASK, LPUART_CTRL_TXINV(value)))
11516 #define LPUART_BWR_CTRL_TXINV(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_TXINV_SHIFT), LPUART_CTRL_TXINV_SHIFT, LPUART_CTRL_TXINV_WIDTH))
11517 /*@}*/
11518 
11519 /*!
11520  * @name Register LPUART_CTRL, field TXDIR[29] (RW)
11521  *
11522  * When the LPUART is configured for single-wire half-duplex operation (LOOPS =
11523  * RSRC = 1), this bit determines the direction of data at the LPUART_TX pin.
11524  * When clearing TXDIR, the transmitter will finish receiving the current character
11525  * (if any) before the receiver starts receiving data from the LPUART_TX pin.
11526  *
11527  * Values:
11528  * - 0b0 - LPUART_TX pin is an input in single-wire mode.
11529  * - 0b1 - LPUART_TX pin is an output in single-wire mode.
11530  */
11531 /*@{*/
11532 /*! @brief Read current value of the LPUART_CTRL_TXDIR field. */
11533 #define LPUART_RD_CTRL_TXDIR(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_TXDIR_MASK) >> LPUART_CTRL_TXDIR_SHIFT)
11534 #define LPUART_BRD_CTRL_TXDIR(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_TXDIR_SHIFT, LPUART_CTRL_TXDIR_WIDTH))
11535 
11536 /*! @brief Set the TXDIR field to a new value. */
11537 #define LPUART_WR_CTRL_TXDIR(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_TXDIR_MASK, LPUART_CTRL_TXDIR(value)))
11538 #define LPUART_BWR_CTRL_TXDIR(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_TXDIR_SHIFT), LPUART_CTRL_TXDIR_SHIFT, LPUART_CTRL_TXDIR_WIDTH))
11539 /*@}*/
11540 
11541 /*!
11542  * @name Register LPUART_CTRL, field R9T8[30] (RW)
11543  *
11544  * R9 is the tenth data bit received when the LPUART is configured for 10-bit
11545  * data formats. When reading 10-bit data, read R9 before reading LPUART_DATA T8 is
11546  * the ninth data bit received when the LPUART is configured for 9-bit or 10-bit
11547  * data formats. When writing 9-bit or 10-bit data, write T8 before writing
11548  * LPUART_DATA. If T8 does not need to change from its previous value, such as when
11549  * it is used to generate address mark or parity, they it need not be written each
11550  * time LPUART_DATA is written.
11551  */
11552 /*@{*/
11553 /*! @brief Read current value of the LPUART_CTRL_R9T8 field. */
11554 #define LPUART_RD_CTRL_R9T8(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_R9T8_MASK) >> LPUART_CTRL_R9T8_SHIFT)
11555 #define LPUART_BRD_CTRL_R9T8(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_R9T8_SHIFT, LPUART_CTRL_R9T8_WIDTH))
11556 
11557 /*! @brief Set the R9T8 field to a new value. */
11558 #define LPUART_WR_CTRL_R9T8(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_R9T8_MASK, LPUART_CTRL_R9T8(value)))
11559 #define LPUART_BWR_CTRL_R9T8(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_R9T8_SHIFT), LPUART_CTRL_R9T8_SHIFT, LPUART_CTRL_R9T8_WIDTH))
11560 /*@}*/
11561 
11562 /*!
11563  * @name Register LPUART_CTRL, field R8T9[31] (RW)
11564  *
11565  * R8 is the ninth data bit received when the LPUART is configured for 9-bit or
11566  * 10-bit data formats. When reading 9-bit or 10-bit data, read R8 before reading
11567  * LPUART_DATA. T9 is the tenth data bit received when the LPUART is configured
11568  * for 10-bit data formats. When writing 10-bit data, write T9 before writing
11569  * LPUART_DATA. If T9 does not need to change from its previous value, such as when
11570  * it is used to generate address mark or parity, they it need not be written
11571  * each time LPUART_DATA is written.
11572  */
11573 /*@{*/
11574 /*! @brief Read current value of the LPUART_CTRL_R8T9 field. */
11575 #define LPUART_RD_CTRL_R8T9(base) ((LPUART_CTRL_REG(base) & LPUART_CTRL_R8T9_MASK) >> LPUART_CTRL_R8T9_SHIFT)
11576 #define LPUART_BRD_CTRL_R8T9(base) (BME_UBFX32(&LPUART_CTRL_REG(base), LPUART_CTRL_R8T9_SHIFT, LPUART_CTRL_R8T9_WIDTH))
11577 
11578 /*! @brief Set the R8T9 field to a new value. */
11579 #define LPUART_WR_CTRL_R8T9(base, value) (LPUART_RMW_CTRL(base, LPUART_CTRL_R8T9_MASK, LPUART_CTRL_R8T9(value)))
11580 #define LPUART_BWR_CTRL_R8T9(base, value) (BME_BFI32(&LPUART_CTRL_REG(base), ((uint32_t)(value) << LPUART_CTRL_R8T9_SHIFT), LPUART_CTRL_R8T9_SHIFT, LPUART_CTRL_R8T9_WIDTH))
11581 /*@}*/
11582 
11583 /*******************************************************************************
11584  * LPUART_DATA - LPUART Data Register
11585  ******************************************************************************/
11586 
11587 /*!
11588  * @brief LPUART_DATA - LPUART Data Register (RW)
11589  *
11590  * Reset value: 0x00001000U
11591  *
11592  * This register is actually two separate registers. Reads return the contents
11593  * of the read-only receive data buffer and writes go to the write-only transmit
11594  * data buffer. Reads and writes of this register are also involved in the
11595  * automatic flag clearing mechanisms for some of the LPUART status flags.
11596  */
11597 /*!
11598  * @name Constants and macros for entire LPUART_DATA register
11599  */
11600 /*@{*/
11601 #define LPUART_RD_DATA(base)     (LPUART_DATA_REG(base))
11602 #define LPUART_WR_DATA(base, value) (LPUART_DATA_REG(base) = (value))
11603 #define LPUART_RMW_DATA(base, mask, value) (LPUART_WR_DATA(base, (LPUART_RD_DATA(base) & ~(mask)) | (value)))
11604 #define LPUART_SET_DATA(base, value) (BME_OR32(&LPUART_DATA_REG(base), (uint32_t)(value)))
11605 #define LPUART_CLR_DATA(base, value) (BME_AND32(&LPUART_DATA_REG(base), (uint32_t)(~(value))))
11606 #define LPUART_TOG_DATA(base, value) (BME_XOR32(&LPUART_DATA_REG(base), (uint32_t)(value)))
11607 /*@}*/
11608 
11609 /*
11610  * Constants & macros for individual LPUART_DATA bitfields
11611  */
11612 
11613 /*!
11614  * @name Register LPUART_DATA, field R0T0[0] (RW)
11615  *
11616  * Read receive data buffer 0 or write transmit data buffer 0.
11617  */
11618 /*@{*/
11619 /*! @brief Read current value of the LPUART_DATA_R0T0 field. */
11620 #define LPUART_RD_DATA_R0T0(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R0T0_MASK) >> LPUART_DATA_R0T0_SHIFT)
11621 #define LPUART_BRD_DATA_R0T0(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R0T0_SHIFT, LPUART_DATA_R0T0_WIDTH))
11622 
11623 /*! @brief Set the R0T0 field to a new value. */
11624 #define LPUART_WR_DATA_R0T0(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R0T0_MASK, LPUART_DATA_R0T0(value)))
11625 #define LPUART_BWR_DATA_R0T0(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_R0T0_SHIFT), LPUART_DATA_R0T0_SHIFT, LPUART_DATA_R0T0_WIDTH))
11626 /*@}*/
11627 
11628 /*!
11629  * @name Register LPUART_DATA, field R1T1[1] (RW)
11630  *
11631  * Read receive data buffer 1 or write transmit data buffer 1.
11632  */
11633 /*@{*/
11634 /*! @brief Read current value of the LPUART_DATA_R1T1 field. */
11635 #define LPUART_RD_DATA_R1T1(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R1T1_MASK) >> LPUART_DATA_R1T1_SHIFT)
11636 #define LPUART_BRD_DATA_R1T1(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R1T1_SHIFT, LPUART_DATA_R1T1_WIDTH))
11637 
11638 /*! @brief Set the R1T1 field to a new value. */
11639 #define LPUART_WR_DATA_R1T1(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R1T1_MASK, LPUART_DATA_R1T1(value)))
11640 #define LPUART_BWR_DATA_R1T1(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_R1T1_SHIFT), LPUART_DATA_R1T1_SHIFT, LPUART_DATA_R1T1_WIDTH))
11641 /*@}*/
11642 
11643 /*!
11644  * @name Register LPUART_DATA, field R2T2[2] (RW)
11645  *
11646  * Read receive data buffer 2 or write transmit data buffer 2.
11647  */
11648 /*@{*/
11649 /*! @brief Read current value of the LPUART_DATA_R2T2 field. */
11650 #define LPUART_RD_DATA_R2T2(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R2T2_MASK) >> LPUART_DATA_R2T2_SHIFT)
11651 #define LPUART_BRD_DATA_R2T2(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R2T2_SHIFT, LPUART_DATA_R2T2_WIDTH))
11652 
11653 /*! @brief Set the R2T2 field to a new value. */
11654 #define LPUART_WR_DATA_R2T2(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R2T2_MASK, LPUART_DATA_R2T2(value)))
11655 #define LPUART_BWR_DATA_R2T2(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_R2T2_SHIFT), LPUART_DATA_R2T2_SHIFT, LPUART_DATA_R2T2_WIDTH))
11656 /*@}*/
11657 
11658 /*!
11659  * @name Register LPUART_DATA, field R3T3[3] (RW)
11660  *
11661  * Read receive data buffer 3 or write transmit data buffer 3.
11662  */
11663 /*@{*/
11664 /*! @brief Read current value of the LPUART_DATA_R3T3 field. */
11665 #define LPUART_RD_DATA_R3T3(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R3T3_MASK) >> LPUART_DATA_R3T3_SHIFT)
11666 #define LPUART_BRD_DATA_R3T3(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R3T3_SHIFT, LPUART_DATA_R3T3_WIDTH))
11667 
11668 /*! @brief Set the R3T3 field to a new value. */
11669 #define LPUART_WR_DATA_R3T3(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R3T3_MASK, LPUART_DATA_R3T3(value)))
11670 #define LPUART_BWR_DATA_R3T3(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_R3T3_SHIFT), LPUART_DATA_R3T3_SHIFT, LPUART_DATA_R3T3_WIDTH))
11671 /*@}*/
11672 
11673 /*!
11674  * @name Register LPUART_DATA, field R4T4[4] (RW)
11675  *
11676  * Read receive data buffer 4 or write transmit data buffer 4.
11677  */
11678 /*@{*/
11679 /*! @brief Read current value of the LPUART_DATA_R4T4 field. */
11680 #define LPUART_RD_DATA_R4T4(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R4T4_MASK) >> LPUART_DATA_R4T4_SHIFT)
11681 #define LPUART_BRD_DATA_R4T4(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R4T4_SHIFT, LPUART_DATA_R4T4_WIDTH))
11682 
11683 /*! @brief Set the R4T4 field to a new value. */
11684 #define LPUART_WR_DATA_R4T4(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R4T4_MASK, LPUART_DATA_R4T4(value)))
11685 #define LPUART_BWR_DATA_R4T4(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_R4T4_SHIFT), LPUART_DATA_R4T4_SHIFT, LPUART_DATA_R4T4_WIDTH))
11686 /*@}*/
11687 
11688 /*!
11689  * @name Register LPUART_DATA, field R5T5[5] (RW)
11690  *
11691  * Read receive data buffer 5 or write transmit data buffer 5.
11692  */
11693 /*@{*/
11694 /*! @brief Read current value of the LPUART_DATA_R5T5 field. */
11695 #define LPUART_RD_DATA_R5T5(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R5T5_MASK) >> LPUART_DATA_R5T5_SHIFT)
11696 #define LPUART_BRD_DATA_R5T5(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R5T5_SHIFT, LPUART_DATA_R5T5_WIDTH))
11697 
11698 /*! @brief Set the R5T5 field to a new value. */
11699 #define LPUART_WR_DATA_R5T5(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R5T5_MASK, LPUART_DATA_R5T5(value)))
11700 #define LPUART_BWR_DATA_R5T5(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_R5T5_SHIFT), LPUART_DATA_R5T5_SHIFT, LPUART_DATA_R5T5_WIDTH))
11701 /*@}*/
11702 
11703 /*!
11704  * @name Register LPUART_DATA, field R6T6[6] (RW)
11705  *
11706  * Read receive data buffer 6 or write transmit data buffer 6.
11707  */
11708 /*@{*/
11709 /*! @brief Read current value of the LPUART_DATA_R6T6 field. */
11710 #define LPUART_RD_DATA_R6T6(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R6T6_MASK) >> LPUART_DATA_R6T6_SHIFT)
11711 #define LPUART_BRD_DATA_R6T6(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R6T6_SHIFT, LPUART_DATA_R6T6_WIDTH))
11712 
11713 /*! @brief Set the R6T6 field to a new value. */
11714 #define LPUART_WR_DATA_R6T6(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R6T6_MASK, LPUART_DATA_R6T6(value)))
11715 #define LPUART_BWR_DATA_R6T6(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_R6T6_SHIFT), LPUART_DATA_R6T6_SHIFT, LPUART_DATA_R6T6_WIDTH))
11716 /*@}*/
11717 
11718 /*!
11719  * @name Register LPUART_DATA, field R7T7[7] (RW)
11720  *
11721  * Read receive data buffer 7 or write transmit data buffer 7.
11722  */
11723 /*@{*/
11724 /*! @brief Read current value of the LPUART_DATA_R7T7 field. */
11725 #define LPUART_RD_DATA_R7T7(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R7T7_MASK) >> LPUART_DATA_R7T7_SHIFT)
11726 #define LPUART_BRD_DATA_R7T7(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R7T7_SHIFT, LPUART_DATA_R7T7_WIDTH))
11727 
11728 /*! @brief Set the R7T7 field to a new value. */
11729 #define LPUART_WR_DATA_R7T7(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R7T7_MASK, LPUART_DATA_R7T7(value)))
11730 #define LPUART_BWR_DATA_R7T7(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_R7T7_SHIFT), LPUART_DATA_R7T7_SHIFT, LPUART_DATA_R7T7_WIDTH))
11731 /*@}*/
11732 
11733 /*!
11734  * @name Register LPUART_DATA, field R8T8[8] (RW)
11735  *
11736  * Read receive data buffer 8 or write transmit data buffer 8.
11737  */
11738 /*@{*/
11739 /*! @brief Read current value of the LPUART_DATA_R8T8 field. */
11740 #define LPUART_RD_DATA_R8T8(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R8T8_MASK) >> LPUART_DATA_R8T8_SHIFT)
11741 #define LPUART_BRD_DATA_R8T8(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R8T8_SHIFT, LPUART_DATA_R8T8_WIDTH))
11742 
11743 /*! @brief Set the R8T8 field to a new value. */
11744 #define LPUART_WR_DATA_R8T8(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R8T8_MASK, LPUART_DATA_R8T8(value)))
11745 #define LPUART_BWR_DATA_R8T8(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_R8T8_SHIFT), LPUART_DATA_R8T8_SHIFT, LPUART_DATA_R8T8_WIDTH))
11746 /*@}*/
11747 
11748 /*!
11749  * @name Register LPUART_DATA, field R9T9[9] (RW)
11750  *
11751  * Read receive data buffer 9 or write transmit data buffer 9.
11752  */
11753 /*@{*/
11754 /*! @brief Read current value of the LPUART_DATA_R9T9 field. */
11755 #define LPUART_RD_DATA_R9T9(base) ((LPUART_DATA_REG(base) & LPUART_DATA_R9T9_MASK) >> LPUART_DATA_R9T9_SHIFT)
11756 #define LPUART_BRD_DATA_R9T9(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_R9T9_SHIFT, LPUART_DATA_R9T9_WIDTH))
11757 
11758 /*! @brief Set the R9T9 field to a new value. */
11759 #define LPUART_WR_DATA_R9T9(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_R9T9_MASK, LPUART_DATA_R9T9(value)))
11760 #define LPUART_BWR_DATA_R9T9(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_R9T9_SHIFT), LPUART_DATA_R9T9_SHIFT, LPUART_DATA_R9T9_WIDTH))
11761 /*@}*/
11762 
11763 /*!
11764  * @name Register LPUART_DATA, field IDLINE[11] (RO)
11765  *
11766  * Indicates the receiver line was idle before receiving the character in
11767  * DATA[9:0]. Unlike the IDLE flag, this bit can set for the first character received
11768  * when the receiver is first enabled.
11769  *
11770  * Values:
11771  * - 0b0 - Receiver was not idle before receiving this character.
11772  * - 0b1 - Receiver was idle before receiving this character.
11773  */
11774 /*@{*/
11775 /*! @brief Read current value of the LPUART_DATA_IDLINE field. */
11776 #define LPUART_RD_DATA_IDLINE(base) ((LPUART_DATA_REG(base) & LPUART_DATA_IDLINE_MASK) >> LPUART_DATA_IDLINE_SHIFT)
11777 #define LPUART_BRD_DATA_IDLINE(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_IDLINE_SHIFT, LPUART_DATA_IDLINE_WIDTH))
11778 /*@}*/
11779 
11780 /*!
11781  * @name Register LPUART_DATA, field RXEMPT[12] (RO)
11782  *
11783  * Asserts when there is no data in the receive buffer. This field does not take
11784  * into account data that is in the receive shift register.
11785  *
11786  * Values:
11787  * - 0b0 - Receive buffer contains valid data.
11788  * - 0b1 - Receive buffer is empty, data returned on read is not valid.
11789  */
11790 /*@{*/
11791 /*! @brief Read current value of the LPUART_DATA_RXEMPT field. */
11792 #define LPUART_RD_DATA_RXEMPT(base) ((LPUART_DATA_REG(base) & LPUART_DATA_RXEMPT_MASK) >> LPUART_DATA_RXEMPT_SHIFT)
11793 #define LPUART_BRD_DATA_RXEMPT(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_RXEMPT_SHIFT, LPUART_DATA_RXEMPT_WIDTH))
11794 /*@}*/
11795 
11796 /*!
11797  * @name Register LPUART_DATA, field FRETSC[13] (RW)
11798  *
11799  * For reads, indicates the current received dataword contained in DATA[R9:R0]
11800  * was received with a frame error. For writes, indicates a break or idle
11801  * character is to be transmitted instead of the contents in DATA[T9:T0]. T9 is used to
11802  * indicate a break character when 0 and a idle character when 1, he contents of
11803  * DATA[T8:T0] should be zero.
11804  *
11805  * Values:
11806  * - 0b0 - The dataword was received without a frame error on read, transmit a
11807  *     normal character on write.
11808  * - 0b1 - The dataword was received with a frame error, transmit an idle or
11809  *     break character on transmit.
11810  */
11811 /*@{*/
11812 /*! @brief Read current value of the LPUART_DATA_FRETSC field. */
11813 #define LPUART_RD_DATA_FRETSC(base) ((LPUART_DATA_REG(base) & LPUART_DATA_FRETSC_MASK) >> LPUART_DATA_FRETSC_SHIFT)
11814 #define LPUART_BRD_DATA_FRETSC(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_FRETSC_SHIFT, LPUART_DATA_FRETSC_WIDTH))
11815 
11816 /*! @brief Set the FRETSC field to a new value. */
11817 #define LPUART_WR_DATA_FRETSC(base, value) (LPUART_RMW_DATA(base, LPUART_DATA_FRETSC_MASK, LPUART_DATA_FRETSC(value)))
11818 #define LPUART_BWR_DATA_FRETSC(base, value) (BME_BFI32(&LPUART_DATA_REG(base), ((uint32_t)(value) << LPUART_DATA_FRETSC_SHIFT), LPUART_DATA_FRETSC_SHIFT, LPUART_DATA_FRETSC_WIDTH))
11819 /*@}*/
11820 
11821 /*!
11822  * @name Register LPUART_DATA, field PARITYE[14] (RO)
11823  *
11824  * The current received dataword contained in DATA[R9:R0] was received with a
11825  * parity error.
11826  *
11827  * Values:
11828  * - 0b0 - The dataword was received without a parity error.
11829  * - 0b1 - The dataword was received with a parity error.
11830  */
11831 /*@{*/
11832 /*! @brief Read current value of the LPUART_DATA_PARITYE field. */
11833 #define LPUART_RD_DATA_PARITYE(base) ((LPUART_DATA_REG(base) & LPUART_DATA_PARITYE_MASK) >> LPUART_DATA_PARITYE_SHIFT)
11834 #define LPUART_BRD_DATA_PARITYE(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_PARITYE_SHIFT, LPUART_DATA_PARITYE_WIDTH))
11835 /*@}*/
11836 
11837 /*!
11838  * @name Register LPUART_DATA, field NOISY[15] (RO)
11839  *
11840  * The current received dataword contained in DATA[R9:R0] was received with
11841  * noise.
11842  *
11843  * Values:
11844  * - 0b0 - The dataword was received without noise.
11845  * - 0b1 - The data was received with noise.
11846  */
11847 /*@{*/
11848 /*! @brief Read current value of the LPUART_DATA_NOISY field. */
11849 #define LPUART_RD_DATA_NOISY(base) ((LPUART_DATA_REG(base) & LPUART_DATA_NOISY_MASK) >> LPUART_DATA_NOISY_SHIFT)
11850 #define LPUART_BRD_DATA_NOISY(base) (BME_UBFX32(&LPUART_DATA_REG(base), LPUART_DATA_NOISY_SHIFT, LPUART_DATA_NOISY_WIDTH))
11851 /*@}*/
11852 
11853 /*******************************************************************************
11854  * LPUART_MATCH - LPUART Match Address Register
11855  ******************************************************************************/
11856 
11857 /*!
11858  * @brief LPUART_MATCH - LPUART Match Address Register (RW)
11859  *
11860  * Reset value: 0x00000000U
11861  */
11862 /*!
11863  * @name Constants and macros for entire LPUART_MATCH register
11864  */
11865 /*@{*/
11866 #define LPUART_RD_MATCH(base)    (LPUART_MATCH_REG(base))
11867 #define LPUART_WR_MATCH(base, value) (LPUART_MATCH_REG(base) = (value))
11868 #define LPUART_RMW_MATCH(base, mask, value) (LPUART_WR_MATCH(base, (LPUART_RD_MATCH(base) & ~(mask)) | (value)))
11869 #define LPUART_SET_MATCH(base, value) (BME_OR32(&LPUART_MATCH_REG(base), (uint32_t)(value)))
11870 #define LPUART_CLR_MATCH(base, value) (BME_AND32(&LPUART_MATCH_REG(base), (uint32_t)(~(value))))
11871 #define LPUART_TOG_MATCH(base, value) (BME_XOR32(&LPUART_MATCH_REG(base), (uint32_t)(value)))
11872 /*@}*/
11873 
11874 /*
11875  * Constants & macros for individual LPUART_MATCH bitfields
11876  */
11877 
11878 /*!
11879  * @name Register LPUART_MATCH, field MA1[9:0] (RW)
11880  *
11881  * The MA1 and MA2 registers are compared to input data addresses when the most
11882  * significant bit is set and the associated BAUD[MAEN] bit is set. If a match
11883  * occurs, the following data is transferred to the data register. If a match
11884  * fails, the following data is discarded. Software should only write a MA register
11885  * when the associated BAUD[MAEN] bit is clear.
11886  */
11887 /*@{*/
11888 /*! @brief Read current value of the LPUART_MATCH_MA1 field. */
11889 #define LPUART_RD_MATCH_MA1(base) ((LPUART_MATCH_REG(base) & LPUART_MATCH_MA1_MASK) >> LPUART_MATCH_MA1_SHIFT)
11890 #define LPUART_BRD_MATCH_MA1(base) (BME_UBFX32(&LPUART_MATCH_REG(base), LPUART_MATCH_MA1_SHIFT, LPUART_MATCH_MA1_WIDTH))
11891 
11892 /*! @brief Set the MA1 field to a new value. */
11893 #define LPUART_WR_MATCH_MA1(base, value) (LPUART_RMW_MATCH(base, LPUART_MATCH_MA1_MASK, LPUART_MATCH_MA1(value)))
11894 #define LPUART_BWR_MATCH_MA1(base, value) (BME_BFI32(&LPUART_MATCH_REG(base), ((uint32_t)(value) << LPUART_MATCH_MA1_SHIFT), LPUART_MATCH_MA1_SHIFT, LPUART_MATCH_MA1_WIDTH))
11895 /*@}*/
11896 
11897 /*!
11898  * @name Register LPUART_MATCH, field MA2[25:16] (RW)
11899  *
11900  * The MA1 and MA2 registers are compared to input data addresses when the most
11901  * significant bit is set and the associated BAUD[MAEN] bit is set. If a match
11902  * occurs, the following data is transferred to the data register. If a match
11903  * fails, the following data is discarded. Software should only write a MA register
11904  * when the associated BAUD[MAEN] bit is clear.
11905  */
11906 /*@{*/
11907 /*! @brief Read current value of the LPUART_MATCH_MA2 field. */
11908 #define LPUART_RD_MATCH_MA2(base) ((LPUART_MATCH_REG(base) & LPUART_MATCH_MA2_MASK) >> LPUART_MATCH_MA2_SHIFT)
11909 #define LPUART_BRD_MATCH_MA2(base) (BME_UBFX32(&LPUART_MATCH_REG(base), LPUART_MATCH_MA2_SHIFT, LPUART_MATCH_MA2_WIDTH))
11910 
11911 /*! @brief Set the MA2 field to a new value. */
11912 #define LPUART_WR_MATCH_MA2(base, value) (LPUART_RMW_MATCH(base, LPUART_MATCH_MA2_MASK, LPUART_MATCH_MA2(value)))
11913 #define LPUART_BWR_MATCH_MA2(base, value) (BME_BFI32(&LPUART_MATCH_REG(base), ((uint32_t)(value) << LPUART_MATCH_MA2_SHIFT), LPUART_MATCH_MA2_SHIFT, LPUART_MATCH_MA2_WIDTH))
11914 /*@}*/
11915 
11916 /*******************************************************************************
11917  * LPUART_MODIR - LPUART Modem IrDA Register
11918  ******************************************************************************/
11919 
11920 /*!
11921  * @brief LPUART_MODIR - LPUART Modem IrDA Register (RW)
11922  *
11923  * Reset value: 0x00000000U
11924  *
11925  * The MODEM register controls options for setting the modem configuration.
11926  */
11927 /*!
11928  * @name Constants and macros for entire LPUART_MODIR register
11929  */
11930 /*@{*/
11931 #define LPUART_RD_MODIR(base)    (LPUART_MODIR_REG(base))
11932 #define LPUART_WR_MODIR(base, value) (LPUART_MODIR_REG(base) = (value))
11933 #define LPUART_RMW_MODIR(base, mask, value) (LPUART_WR_MODIR(base, (LPUART_RD_MODIR(base) & ~(mask)) | (value)))
11934 #define LPUART_SET_MODIR(base, value) (BME_OR32(&LPUART_MODIR_REG(base), (uint32_t)(value)))
11935 #define LPUART_CLR_MODIR(base, value) (BME_AND32(&LPUART_MODIR_REG(base), (uint32_t)(~(value))))
11936 #define LPUART_TOG_MODIR(base, value) (BME_XOR32(&LPUART_MODIR_REG(base), (uint32_t)(value)))
11937 /*@}*/
11938 
11939 /*
11940  * Constants & macros for individual LPUART_MODIR bitfields
11941  */
11942 
11943 /*!
11944  * @name Register LPUART_MODIR, field TXCTSE[0] (RW)
11945  *
11946  * TXCTSE controls the operation of the transmitter. TXCTSE can be set
11947  * independently from the state of TXRTSE and RXRTSE.
11948  *
11949  * Values:
11950  * - 0b0 - CTS has no effect on the transmitter.
11951  * - 0b1 - Enables clear-to-send operation. The transmitter checks the state of
11952  *     CTS each time it is ready to send a character. If CTS is asserted, the
11953  *     character is sent. If CTS is deasserted, the signal TXD remains in the mark
11954  *     state and transmission is delayed until CTS is asserted. Changes in CTS as
11955  *     a character is being sent do not affect its transmission.
11956  */
11957 /*@{*/
11958 /*! @brief Read current value of the LPUART_MODIR_TXCTSE field. */
11959 #define LPUART_RD_MODIR_TXCTSE(base) ((LPUART_MODIR_REG(base) & LPUART_MODIR_TXCTSE_MASK) >> LPUART_MODIR_TXCTSE_SHIFT)
11960 #define LPUART_BRD_MODIR_TXCTSE(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_TXCTSE_SHIFT, LPUART_MODIR_TXCTSE_WIDTH))
11961 
11962 /*! @brief Set the TXCTSE field to a new value. */
11963 #define LPUART_WR_MODIR_TXCTSE(base, value) (LPUART_RMW_MODIR(base, LPUART_MODIR_TXCTSE_MASK, LPUART_MODIR_TXCTSE(value)))
11964 #define LPUART_BWR_MODIR_TXCTSE(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(value) << LPUART_MODIR_TXCTSE_SHIFT), LPUART_MODIR_TXCTSE_SHIFT, LPUART_MODIR_TXCTSE_WIDTH))
11965 /*@}*/
11966 
11967 /*!
11968  * @name Register LPUART_MODIR, field TXRTSE[1] (RW)
11969  *
11970  * Controls RTS before and after a transmission.
11971  *
11972  * Values:
11973  * - 0b0 - The transmitter has no effect on RTS.
11974  * - 0b1 - When a character is placed into an empty transmitter data buffer ,
11975  *     RTS asserts one bit time before the start bit is transmitted. RTS deasserts
11976  *     one bit time after all characters in the transmitter data buffer and shift
11977  *     register are completely sent, including the last stop bit.
11978  */
11979 /*@{*/
11980 /*! @brief Read current value of the LPUART_MODIR_TXRTSE field. */
11981 #define LPUART_RD_MODIR_TXRTSE(base) ((LPUART_MODIR_REG(base) & LPUART_MODIR_TXRTSE_MASK) >> LPUART_MODIR_TXRTSE_SHIFT)
11982 #define LPUART_BRD_MODIR_TXRTSE(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_TXRTSE_SHIFT, LPUART_MODIR_TXRTSE_WIDTH))
11983 
11984 /*! @brief Set the TXRTSE field to a new value. */
11985 #define LPUART_WR_MODIR_TXRTSE(base, value) (LPUART_RMW_MODIR(base, LPUART_MODIR_TXRTSE_MASK, LPUART_MODIR_TXRTSE(value)))
11986 #define LPUART_BWR_MODIR_TXRTSE(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(value) << LPUART_MODIR_TXRTSE_SHIFT), LPUART_MODIR_TXRTSE_SHIFT, LPUART_MODIR_TXRTSE_WIDTH))
11987 /*@}*/
11988 
11989 /*!
11990  * @name Register LPUART_MODIR, field TXRTSPOL[2] (RW)
11991  *
11992  * Controls the polarity of the transmitter RTS. TXRTSPOL does not affect the
11993  * polarity of the receiver RTS. RTS will remain negated in the active low state
11994  * unless TXRTSE is set.
11995  *
11996  * Values:
11997  * - 0b0 - Transmitter RTS is active low.
11998  * - 0b1 - Transmitter RTS is active high.
11999  */
12000 /*@{*/
12001 /*! @brief Read current value of the LPUART_MODIR_TXRTSPOL field. */
12002 #define LPUART_RD_MODIR_TXRTSPOL(base) ((LPUART_MODIR_REG(base) & LPUART_MODIR_TXRTSPOL_MASK) >> LPUART_MODIR_TXRTSPOL_SHIFT)
12003 #define LPUART_BRD_MODIR_TXRTSPOL(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_TXRTSPOL_SHIFT, LPUART_MODIR_TXRTSPOL_WIDTH))
12004 
12005 /*! @brief Set the TXRTSPOL field to a new value. */
12006 #define LPUART_WR_MODIR_TXRTSPOL(base, value) (LPUART_RMW_MODIR(base, LPUART_MODIR_TXRTSPOL_MASK, LPUART_MODIR_TXRTSPOL(value)))
12007 #define LPUART_BWR_MODIR_TXRTSPOL(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(value) << LPUART_MODIR_TXRTSPOL_SHIFT), LPUART_MODIR_TXRTSPOL_SHIFT, LPUART_MODIR_TXRTSPOL_WIDTH))
12008 /*@}*/
12009 
12010 /*!
12011  * @name Register LPUART_MODIR, field RXRTSE[3] (RW)
12012  *
12013  * Allows the RTS output to control the CTS input of the transmitting device to
12014  * prevent receiver overrun. Do not set both RXRTSE and TXRTSE.
12015  *
12016  * Values:
12017  * - 0b0 - The receiver has no effect on RTS.
12018  * - 0b1 - RTS assertion is configured by the RTSWATER field
12019  */
12020 /*@{*/
12021 /*! @brief Read current value of the LPUART_MODIR_RXRTSE field. */
12022 #define LPUART_RD_MODIR_RXRTSE(base) ((LPUART_MODIR_REG(base) & LPUART_MODIR_RXRTSE_MASK) >> LPUART_MODIR_RXRTSE_SHIFT)
12023 #define LPUART_BRD_MODIR_RXRTSE(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_RXRTSE_SHIFT, LPUART_MODIR_RXRTSE_WIDTH))
12024 
12025 /*! @brief Set the RXRTSE field to a new value. */
12026 #define LPUART_WR_MODIR_RXRTSE(base, value) (LPUART_RMW_MODIR(base, LPUART_MODIR_RXRTSE_MASK, LPUART_MODIR_RXRTSE(value)))
12027 #define LPUART_BWR_MODIR_RXRTSE(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(value) << LPUART_MODIR_RXRTSE_SHIFT), LPUART_MODIR_RXRTSE_SHIFT, LPUART_MODIR_RXRTSE_WIDTH))
12028 /*@}*/
12029 
12030 /*!
12031  * @name Register LPUART_MODIR, field TXCTSC[4] (RW)
12032  *
12033  * Configures if the CTS state is checked at the start of each character or only
12034  * when the transmitter is idle.
12035  *
12036  * Values:
12037  * - 0b0 - CTS input is sampled at the start of each character.
12038  * - 0b1 - CTS input is sampled when the transmitter is idle.
12039  */
12040 /*@{*/
12041 /*! @brief Read current value of the LPUART_MODIR_TXCTSC field. */
12042 #define LPUART_RD_MODIR_TXCTSC(base) ((LPUART_MODIR_REG(base) & LPUART_MODIR_TXCTSC_MASK) >> LPUART_MODIR_TXCTSC_SHIFT)
12043 #define LPUART_BRD_MODIR_TXCTSC(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_TXCTSC_SHIFT, LPUART_MODIR_TXCTSC_WIDTH))
12044 
12045 /*! @brief Set the TXCTSC field to a new value. */
12046 #define LPUART_WR_MODIR_TXCTSC(base, value) (LPUART_RMW_MODIR(base, LPUART_MODIR_TXCTSC_MASK, LPUART_MODIR_TXCTSC(value)))
12047 #define LPUART_BWR_MODIR_TXCTSC(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(value) << LPUART_MODIR_TXCTSC_SHIFT), LPUART_MODIR_TXCTSC_SHIFT, LPUART_MODIR_TXCTSC_WIDTH))
12048 /*@}*/
12049 
12050 /*!
12051  * @name Register LPUART_MODIR, field TXCTSSRC[5] (RW)
12052  *
12053  * Configures the source of the CTS input.
12054  *
12055  * Values:
12056  * - 0b0 - CTS input is the LPUART_CTS pin.
12057  * - 0b1 - CTS input is the inverted Receiver Match result.
12058  */
12059 /*@{*/
12060 /*! @brief Read current value of the LPUART_MODIR_TXCTSSRC field. */
12061 #define LPUART_RD_MODIR_TXCTSSRC(base) ((LPUART_MODIR_REG(base) & LPUART_MODIR_TXCTSSRC_MASK) >> LPUART_MODIR_TXCTSSRC_SHIFT)
12062 #define LPUART_BRD_MODIR_TXCTSSRC(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_TXCTSSRC_SHIFT, LPUART_MODIR_TXCTSSRC_WIDTH))
12063 
12064 /*! @brief Set the TXCTSSRC field to a new value. */
12065 #define LPUART_WR_MODIR_TXCTSSRC(base, value) (LPUART_RMW_MODIR(base, LPUART_MODIR_TXCTSSRC_MASK, LPUART_MODIR_TXCTSSRC(value)))
12066 #define LPUART_BWR_MODIR_TXCTSSRC(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(value) << LPUART_MODIR_TXCTSSRC_SHIFT), LPUART_MODIR_TXCTSSRC_SHIFT, LPUART_MODIR_TXCTSSRC_WIDTH))
12067 /*@}*/
12068 
12069 /*!
12070  * @name Register LPUART_MODIR, field TNP[17:16] (RW)
12071  *
12072  * Enables whether the LPUART transmits a 1/OSR, 2/OSR, 3/OSR or 4/OSR narrow
12073  * pulse.
12074  *
12075  * Values:
12076  * - 0b00 - 1/OSR.
12077  * - 0b01 - 2/OSR.
12078  * - 0b10 - 3/OSR.
12079  * - 0b11 - 4/OSR.
12080  */
12081 /*@{*/
12082 /*! @brief Read current value of the LPUART_MODIR_TNP field. */
12083 #define LPUART_RD_MODIR_TNP(base) ((LPUART_MODIR_REG(base) & LPUART_MODIR_TNP_MASK) >> LPUART_MODIR_TNP_SHIFT)
12084 #define LPUART_BRD_MODIR_TNP(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_TNP_SHIFT, LPUART_MODIR_TNP_WIDTH))
12085 
12086 /*! @brief Set the TNP field to a new value. */
12087 #define LPUART_WR_MODIR_TNP(base, value) (LPUART_RMW_MODIR(base, LPUART_MODIR_TNP_MASK, LPUART_MODIR_TNP(value)))
12088 #define LPUART_BWR_MODIR_TNP(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(value) << LPUART_MODIR_TNP_SHIFT), LPUART_MODIR_TNP_SHIFT, LPUART_MODIR_TNP_WIDTH))
12089 /*@}*/
12090 
12091 /*!
12092  * @name Register LPUART_MODIR, field IREN[18] (RW)
12093  *
12094  * Enables/disables the infrared modulation/demodulation.
12095  *
12096  * Values:
12097  * - 0b0 - IR disabled.
12098  * - 0b1 - IR enabled.
12099  */
12100 /*@{*/
12101 /*! @brief Read current value of the LPUART_MODIR_IREN field. */
12102 #define LPUART_RD_MODIR_IREN(base) ((LPUART_MODIR_REG(base) & LPUART_MODIR_IREN_MASK) >> LPUART_MODIR_IREN_SHIFT)
12103 #define LPUART_BRD_MODIR_IREN(base) (BME_UBFX32(&LPUART_MODIR_REG(base), LPUART_MODIR_IREN_SHIFT, LPUART_MODIR_IREN_WIDTH))
12104 
12105 /*! @brief Set the IREN field to a new value. */
12106 #define LPUART_WR_MODIR_IREN(base, value) (LPUART_RMW_MODIR(base, LPUART_MODIR_IREN_MASK, LPUART_MODIR_IREN(value)))
12107 #define LPUART_BWR_MODIR_IREN(base, value) (BME_BFI32(&LPUART_MODIR_REG(base), ((uint32_t)(value) << LPUART_MODIR_IREN_SHIFT), LPUART_MODIR_IREN_SHIFT, LPUART_MODIR_IREN_WIDTH))
12108 /*@}*/
12109 
12110 /*
12111  * MKW40Z4 LTC
12112  *
12113  * LTC
12114  *
12115  * Registers defined in this header file:
12116  * - LTC_MD - LTC Mode Register (non-PKHA/non-RNG use)
12117  * - LTC_KS - LTC Key Size Register
12118  * - LTC_DS - LTC Data Size Register
12119  * - LTC_ICVS - LTC ICV Size Register
12120  * - LTC_COM - LTC Command Register
12121  * - LTC_CTL - LTC Control Register
12122  * - LTC_CW - LTC Clear Written Register
12123  * - LTC_STA - LTC Status Register
12124  * - LTC_ESTA - LTC Error Status Register
12125  * - LTC_AADSZ - LTC AAD Size Register
12126  * - LTC_CTX - LTC Context Register
12127  * - LTC_KEY - LTC Key Registers
12128  * - LTC_FIFOSTA - LTC FIFO Status Register
12129  * - LTC_IFIFO - LTC Input Data FIFO
12130  * - LTC_OFIFO - LTC Output Data FIFO
12131  * - LTC_VID1 - LTC Version ID Register
12132  * - LTC_CHAVID - LTC CHA Version ID Register
12133  */
12134 
12135 #define LTC_INSTANCE_COUNT (1U) /*!< Number of instances of the LTC module. */
12136 #define LTC0_IDX (0U) /*!< Instance number for LTC0. */
12137 
12138 /*******************************************************************************
12139  * LTC_MD - LTC Mode Register (non-PKHA/non-RNG use)
12140  ******************************************************************************/
12141 
12142 /*!
12143  * @brief LTC_MD - LTC Mode Register (non-PKHA/non-RNG use) (RW)
12144  *
12145  * Reset value: 0x00000000U
12146  *
12147  * The Mode Register is used to tell the cryptographic engines which operation
12148  * is being requested. The interpretation of this register will be unique for each
12149  * CHA. This section defines the format of the Mode Register when used with
12150  * non-public-key algorithms and non-RNG operations.
12151  */
12152 /*!
12153  * @name Constants and macros for entire LTC_MD register
12154  */
12155 /*@{*/
12156 #define LTC_RD_MD(base)          (LTC_MD_REG(base))
12157 #define LTC_WR_MD(base, value)   (LTC_MD_REG(base) = (value))
12158 #define LTC_RMW_MD(base, mask, value) (LTC_WR_MD(base, (LTC_RD_MD(base) & ~(mask)) | (value)))
12159 #define LTC_SET_MD(base, value)  (BME_OR32(&LTC_MD_REG(base), (uint32_t)(value)))
12160 #define LTC_CLR_MD(base, value)  (BME_AND32(&LTC_MD_REG(base), (uint32_t)(~(value))))
12161 #define LTC_TOG_MD(base, value)  (BME_XOR32(&LTC_MD_REG(base), (uint32_t)(value)))
12162 /*@}*/
12163 
12164 /*
12165  * Constants & macros for individual LTC_MD bitfields
12166  */
12167 
12168 /*!
12169  * @name Register LTC_MD, field ENC[0] (RW)
12170  *
12171  * Encrypt/Decrypt. This bit selects encryption or decryption.
12172  *
12173  * Values:
12174  * - 0b0 - Decrypt.
12175  * - 0b1 - Encrypt.
12176  */
12177 /*@{*/
12178 #define LTC_MD_ENC_DECRYPT             (0U)          /*!< Bit field value for LTC_MD_ENC: Decrypt. */
12179 #define LTC_MD_ENC_ENCRYPT             (0x1U)        /*!< Bit field value for LTC_MD_ENC: Encrypt. */
12180 /*! @brief Read current value of the LTC_MD_ENC field. */
12181 #define LTC_RD_MD_ENC(base)  ((LTC_MD_REG(base) & LTC_MD_ENC_MASK) >> LTC_MD_ENC_SHIFT)
12182 #define LTC_BRD_MD_ENC(base) (BME_UBFX32(&LTC_MD_REG(base), LTC_MD_ENC_SHIFT, LTC_MD_ENC_WIDTH))
12183 
12184 /*! @brief Set the ENC field to a new value. */
12185 #define LTC_WR_MD_ENC(base, value) (LTC_RMW_MD(base, LTC_MD_ENC_MASK, LTC_MD_ENC(value)))
12186 #define LTC_BWR_MD_ENC(base, value) (BME_BFI32(&LTC_MD_REG(base), ((uint32_t)(value) << LTC_MD_ENC_SHIFT), LTC_MD_ENC_SHIFT, LTC_MD_ENC_WIDTH))
12187 /*@}*/
12188 
12189 /*!
12190  * @name Register LTC_MD, field ICV_TEST[1] (RW)
12191  *
12192  * ICV Checking / Test AES fault detection. For algorithms other than AES ECB
12193  * mode: ICV CheckingThis bit selects whether the current algorithm should compare
12194  * the known ICV versus the calculated ICV. This bit will be ignored by
12195  * algorithms that do not support ICV checking.0 - Don't compare1 - CompareFor AES ECB
12196  * mode: Test AES fault detectionIn AES ECB mode, this bit activates fault detection
12197  * testing by injecting bit level errors into AES core logic as defined in the
12198  * first 128 bits of the context.0 - Don't inject bit errors1 - Inject bit errors
12199  */
12200 /*@{*/
12201 /*! @brief Read current value of the LTC_MD_ICV_TEST field. */
12202 #define LTC_RD_MD_ICV_TEST(base) ((LTC_MD_REG(base) & LTC_MD_ICV_TEST_MASK) >> LTC_MD_ICV_TEST_SHIFT)
12203 #define LTC_BRD_MD_ICV_TEST(base) (BME_UBFX32(&LTC_MD_REG(base), LTC_MD_ICV_TEST_SHIFT, LTC_MD_ICV_TEST_WIDTH))
12204 
12205 /*! @brief Set the ICV_TEST field to a new value. */
12206 #define LTC_WR_MD_ICV_TEST(base, value) (LTC_RMW_MD(base, LTC_MD_ICV_TEST_MASK, LTC_MD_ICV_TEST(value)))
12207 #define LTC_BWR_MD_ICV_TEST(base, value) (BME_BFI32(&LTC_MD_REG(base), ((uint32_t)(value) << LTC_MD_ICV_TEST_SHIFT), LTC_MD_ICV_TEST_SHIFT, LTC_MD_ICV_TEST_WIDTH))
12208 /*@}*/
12209 
12210 /*!
12211  * @name Register LTC_MD, field AS[3:2] (RW)
12212  *
12213  * Algorithm State. This field defines the state of the algorithm that is being
12214  * executed. This may not be used by every algorithm.
12215  *
12216  * Values:
12217  * - 0b00 - Update
12218  * - 0b01 - Initialize
12219  * - 0b10 - Finalize
12220  * - 0b11 - Initialize/Finalize
12221  */
12222 /*@{*/
12223 #define LTC_MD_AS_UPDATE               (0U)          /*!< Bit field value for LTC_MD_AS: Update */
12224 #define LTC_MD_AS_INITIALIZE           (0x1U)        /*!< Bit field value for LTC_MD_AS: Initialize */
12225 #define LTC_MD_AS_FINALIZE             (0x2U)        /*!< Bit field value for LTC_MD_AS: Finalize */
12226 #define LTC_MD_AS_INIT_FINAL           (0x3U)        /*!< Bit field value for LTC_MD_AS: Initialize/Finalize */
12227 /*! @brief Read current value of the LTC_MD_AS field. */
12228 #define LTC_RD_MD_AS(base)   ((LTC_MD_REG(base) & LTC_MD_AS_MASK) >> LTC_MD_AS_SHIFT)
12229 #define LTC_BRD_MD_AS(base)  (BME_UBFX32(&LTC_MD_REG(base), LTC_MD_AS_SHIFT, LTC_MD_AS_WIDTH))
12230 
12231 /*! @brief Set the AS field to a new value. */
12232 #define LTC_WR_MD_AS(base, value) (LTC_RMW_MD(base, LTC_MD_AS_MASK, LTC_MD_AS(value)))
12233 #define LTC_BWR_MD_AS(base, value) (BME_BFI32(&LTC_MD_REG(base), ((uint32_t)(value) << LTC_MD_AS_SHIFT), LTC_MD_AS_SHIFT, LTC_MD_AS_WIDTH))
12234 /*@}*/
12235 
12236 /*!
12237  * @name Register LTC_MD, field AAI[12:4] (RW)
12238  *
12239  * Additional Algorithm information. This field contains additional mode
12240  * information that is associated with the algorithm that is being executed. See also
12241  * the section describing the appropriate CHA. Some algorithms do not require
12242  * additional algorithm information and in those cases this field should be all 0s.AAI
12243  * Interpretation for AES Modes[For AES the MSB of AAI is the DK (Decrypt Key)
12244  * bit.] CodeThe codes are mutually exclusive (i.e. they cannot be ORed with each
12245  * other).InterpretationCodeInterpretation00h CTR (mod 2128) 80hCCM, CCM*
12246  * 10hCBC90hReserved20hECBA0hCBC_XCBC_MAC30hreservedB0hCTR_XCBC_MAC40hreservedC0hReserved50hReservedD0hReserved60hCMACE0hReserved70hXCBC-MACSetting
12247  * the DK bit (i.e. ORing 100h with any AES code above) causes Key Register to
12248  * be loaded with the AES Dcrypt key, rather than the AES Encrypt key.
12249  */
12250 /*@{*/
12251 /*! @brief Read current value of the LTC_MD_AAI field. */
12252 #define LTC_RD_MD_AAI(base)  ((LTC_MD_REG(base) & LTC_MD_AAI_MASK) >> LTC_MD_AAI_SHIFT)
12253 #define LTC_BRD_MD_AAI(base) (BME_UBFX32(&LTC_MD_REG(base), LTC_MD_AAI_SHIFT, LTC_MD_AAI_WIDTH))
12254 
12255 /*! @brief Set the AAI field to a new value. */
12256 #define LTC_WR_MD_AAI(base, value) (LTC_RMW_MD(base, LTC_MD_AAI_MASK, LTC_MD_AAI(value)))
12257 #define LTC_BWR_MD_AAI(base, value) (BME_BFI32(&LTC_MD_REG(base), ((uint32_t)(value) << LTC_MD_AAI_SHIFT), LTC_MD_AAI_SHIFT, LTC_MD_AAI_WIDTH))
12258 /*@}*/
12259 
12260 /*!
12261  * @name Register LTC_MD, field ALG[23:16] (RW)
12262  *
12263  * Algorithm. This field specifies which algorithm is being selected.
12264  *
12265  * Values:
12266  * - 0b00010000 - AES
12267  */
12268 /*@{*/
12269 #define LTC_MD_ALG_AES                 (0x10U)       /*!< Bit field value for LTC_MD_ALG: AES */
12270 /*! @brief Read current value of the LTC_MD_ALG field. */
12271 #define LTC_RD_MD_ALG(base)  ((LTC_MD_REG(base) & LTC_MD_ALG_MASK) >> LTC_MD_ALG_SHIFT)
12272 #define LTC_BRD_MD_ALG(base) (BME_UBFX32(&LTC_MD_REG(base), LTC_MD_ALG_SHIFT, LTC_MD_ALG_WIDTH))
12273 
12274 /*! @brief Set the ALG field to a new value. */
12275 #define LTC_WR_MD_ALG(base, value) (LTC_RMW_MD(base, LTC_MD_ALG_MASK, LTC_MD_ALG(value)))
12276 #define LTC_BWR_MD_ALG(base, value) (BME_BFI32(&LTC_MD_REG(base), ((uint32_t)(value) << LTC_MD_ALG_SHIFT), LTC_MD_ALG_SHIFT, LTC_MD_ALG_WIDTH))
12277 /*@}*/
12278 
12279 /*******************************************************************************
12280  * LTC_KS - LTC Key Size Register
12281  ******************************************************************************/
12282 
12283 /*!
12284  * @brief LTC_KS - LTC Key Size Register (RW)
12285  *
12286  * Reset value: 0x00000010U
12287  *
12288  * The Key Size Register is used to tell the crypto engine(AES) the size of the
12289  * key that was loaded into the Key Register. The Key Size Register must be
12290  * written after the key is written into the Key Register. Writing to the Key Size
12291  * Register will prevent the user from modifying the Key Register. Only 16 byte keys
12292  * are supported so this register will always read 16 bytes. This register is
12293  * still required to be written to indicate to the AES engine that the key was
12294  * loaded.
12295  */
12296 /*!
12297  * @name Constants and macros for entire LTC_KS register
12298  */
12299 /*@{*/
12300 #define LTC_RD_KS(base)          (LTC_KS_REG(base))
12301 #define LTC_WR_KS(base, value)   (LTC_KS_REG(base) = (value))
12302 #define LTC_RMW_KS(base, mask, value) (LTC_WR_KS(base, (LTC_RD_KS(base) & ~(mask)) | (value)))
12303 #define LTC_SET_KS(base, value)  (BME_OR32(&LTC_KS_REG(base), (uint32_t)(value)))
12304 #define LTC_CLR_KS(base, value)  (BME_AND32(&LTC_KS_REG(base), (uint32_t)(~(value))))
12305 #define LTC_TOG_KS(base, value)  (BME_XOR32(&LTC_KS_REG(base), (uint32_t)(value)))
12306 /*@}*/
12307 
12308 /*******************************************************************************
12309  * LTC_DS - LTC Data Size Register
12310  ******************************************************************************/
12311 
12312 /*!
12313  * @brief LTC_DS - LTC Data Size Register (RW)
12314  *
12315  * Reset value: 0x00000000U
12316  *
12317  * The Data Size Register is used to tell the AES the amount of data that will
12318  * be loaded into the Input Data FIFO. This register should only be written to
12319  * once during a single operation. Note that writing to the , will cause this
12320  * register to also update. When this register is then written directory to then the
12321  * new value will be added to the previous value in the register. That is, if the
12322  * DS field currently has the value 16, writing 2 to the least-significant half of
12323  * the Data Size register (i.e. the DS field) will result in a value of 18 in
12324  * the DS field. Note that AES decrements this register, so reading the register
12325  * may return a value less than sum of the values that were written into it. This
12326  * register is cleared whenever a key is decrypted or encrypted.
12327  */
12328 /*!
12329  * @name Constants and macros for entire LTC_DS register
12330  */
12331 /*@{*/
12332 #define LTC_RD_DS(base)          (LTC_DS_REG(base))
12333 #define LTC_WR_DS(base, value)   (LTC_DS_REG(base) = (value))
12334 #define LTC_RMW_DS(base, mask, value) (LTC_WR_DS(base, (LTC_RD_DS(base) & ~(mask)) | (value)))
12335 #define LTC_SET_DS(base, value)  (BME_OR32(&LTC_DS_REG(base), (uint32_t)(value)))
12336 #define LTC_CLR_DS(base, value)  (BME_AND32(&LTC_DS_REG(base), (uint32_t)(~(value))))
12337 #define LTC_TOG_DS(base, value)  (BME_XOR32(&LTC_DS_REG(base), (uint32_t)(value)))
12338 /*@}*/
12339 
12340 /*
12341  * Constants & macros for individual LTC_DS bitfields
12342  */
12343 
12344 /*!
12345  * @name Register LTC_DS, field DS[11:0] (RW)
12346  *
12347  * Data Size. This is the number of whole bytes of data that will be consumed by
12348  * the CHA. Note that writing the AAD Size Register will result in this register
12349  * also being written to.
12350  */
12351 /*@{*/
12352 /*! @brief Read current value of the LTC_DS_DS field. */
12353 #define LTC_RD_DS_DS(base)   ((LTC_DS_REG(base) & LTC_DS_DS_MASK) >> LTC_DS_DS_SHIFT)
12354 #define LTC_BRD_DS_DS(base)  (BME_UBFX32(&LTC_DS_REG(base), LTC_DS_DS_SHIFT, LTC_DS_DS_WIDTH))
12355 
12356 /*! @brief Set the DS field to a new value. */
12357 #define LTC_WR_DS_DS(base, value) (LTC_RMW_DS(base, LTC_DS_DS_MASK, LTC_DS_DS(value)))
12358 #define LTC_BWR_DS_DS(base, value) (BME_BFI32(&LTC_DS_REG(base), ((uint32_t)(value) << LTC_DS_DS_SHIFT), LTC_DS_DS_SHIFT, LTC_DS_DS_WIDTH))
12359 /*@}*/
12360 
12361 /*******************************************************************************
12362  * LTC_ICVS - LTC ICV Size Register
12363  ******************************************************************************/
12364 
12365 /*!
12366  * @brief LTC_ICVS - LTC ICV Size Register (RW)
12367  *
12368  * Reset value: 0x00000000U
12369  *
12370  * The ICV Size Register indicates how much of the last block of ICV is valid
12371  * when performing AES integrity check modes (e.g. AES-CMAC, AES-XCBC-MAC). This
12372  * register must be written prior to the corresponding word of data being consumed
12373  * by AES. In practical terms, this means the register must be written prior to
12374  * the corresponding data being written to the Input Data FIFO.
12375  */
12376 /*!
12377  * @name Constants and macros for entire LTC_ICVS register
12378  */
12379 /*@{*/
12380 #define LTC_RD_ICVS(base)        (LTC_ICVS_REG(base))
12381 #define LTC_WR_ICVS(base, value) (LTC_ICVS_REG(base) = (value))
12382 #define LTC_RMW_ICVS(base, mask, value) (LTC_WR_ICVS(base, (LTC_RD_ICVS(base) & ~(mask)) | (value)))
12383 #define LTC_SET_ICVS(base, value) (BME_OR32(&LTC_ICVS_REG(base), (uint32_t)(value)))
12384 #define LTC_CLR_ICVS(base, value) (BME_AND32(&LTC_ICVS_REG(base), (uint32_t)(~(value))))
12385 #define LTC_TOG_ICVS(base, value) (BME_XOR32(&LTC_ICVS_REG(base), (uint32_t)(value)))
12386 /*@}*/
12387 
12388 /*
12389  * Constants & macros for individual LTC_ICVS bitfields
12390  */
12391 
12392 /*!
12393  * @name Register LTC_ICVS, field ICVS[4:0] (RW)
12394  *
12395  * ICV Size, in Bytes.
12396  */
12397 /*@{*/
12398 /*! @brief Read current value of the LTC_ICVS_ICVS field. */
12399 #define LTC_RD_ICVS_ICVS(base) ((LTC_ICVS_REG(base) & LTC_ICVS_ICVS_MASK) >> LTC_ICVS_ICVS_SHIFT)
12400 #define LTC_BRD_ICVS_ICVS(base) (BME_UBFX32(&LTC_ICVS_REG(base), LTC_ICVS_ICVS_SHIFT, LTC_ICVS_ICVS_WIDTH))
12401 
12402 /*! @brief Set the ICVS field to a new value. */
12403 #define LTC_WR_ICVS_ICVS(base, value) (LTC_RMW_ICVS(base, LTC_ICVS_ICVS_MASK, LTC_ICVS_ICVS(value)))
12404 #define LTC_BWR_ICVS_ICVS(base, value) (BME_BFI32(&LTC_ICVS_REG(base), ((uint32_t)(value) << LTC_ICVS_ICVS_SHIFT), LTC_ICVS_ICVS_SHIFT, LTC_ICVS_ICVS_WIDTH))
12405 /*@}*/
12406 
12407 /*******************************************************************************
12408  * LTC_COM - LTC Command Register
12409  ******************************************************************************/
12410 
12411 /*!
12412  * @brief LTC_COM - LTC Command Register (WO)
12413  *
12414  * Reset value: 0x00000000U
12415  *
12416  * The LTC Command Register is used to send control signals to the Crypto
12417  * Engines.
12418  */
12419 /*!
12420  * @name Constants and macros for entire LTC_COM register
12421  */
12422 /*@{*/
12423 #define LTC_WR_COM(base, value)  (LTC_COM_REG(base) = (value))
12424 /*@}*/
12425 
12426 /*
12427  * Constants & macros for individual LTC_COM bitfields
12428  */
12429 
12430 /*!
12431  * @name Register LTC_COM, field ALL[0] (WO)
12432  *
12433  * Reset All Internal Logic. Writing to this bit will reset all accelerator
12434  * engines and as well as all the internal registers.
12435  *
12436  * Values:
12437  * - 0b0 - Do Not Reset
12438  * - 0b1 - Reset all CHAs in use by this CCB.
12439  */
12440 /*@{*/
12441 #define LTC_COM_ALL_NO_RESET           (0U)          /*!< Bit field value for LTC_COM_ALL: Do Not Reset */
12442 #define LTC_COM_ALL_RESET_ALL          (0x1U)        /*!< Bit field value for LTC_COM_ALL: Reset all CHAs in use by this CCB. */
12443 /*! @brief Set the ALL field to a new value. */
12444 #define LTC_WR_COM_ALL(base, value) (LTC_WR_COM(base, LTC_COM_ALL(value)))
12445 #define LTC_BWR_COM_ALL(base, value) (LTC_WR_COM_ALL(base, value))
12446 /*@}*/
12447 
12448 /*!
12449  * @name Register LTC_COM, field AES[1] (WO)
12450  *
12451  * Reset AESA. Writing a 1 to this bit resets the AES Accelerator core engine.
12452  *
12453  * Values:
12454  * - 0b0 - Do Not Reset
12455  * - 0b1 - Reset AES Accelerator
12456  */
12457 /*@{*/
12458 #define LTC_COM_AES_NO_RESET           (0U)          /*!< Bit field value for LTC_COM_AES: Do Not Reset */
12459 #define LTC_COM_AES_RESET_AESA         (0x1U)        /*!< Bit field value for LTC_COM_AES: Reset AES Accelerator */
12460 /*! @brief Set the AES field to a new value. */
12461 #define LTC_WR_COM_AES(base, value) (LTC_WR_COM(base, LTC_COM_AES(value)))
12462 #define LTC_BWR_COM_AES(base, value) (LTC_WR_COM_AES(base, value))
12463 /*@}*/
12464 
12465 /*******************************************************************************
12466  * LTC_CTL - LTC Control Register
12467  ******************************************************************************/
12468 
12469 /*!
12470  * @brief LTC_CTL - LTC Control Register (RW)
12471  *
12472  * Reset value: 0x00000000U
12473  *
12474  * This register is used for some of the internal controls of the LTC block.
12475  */
12476 /*!
12477  * @name Constants and macros for entire LTC_CTL register
12478  */
12479 /*@{*/
12480 #define LTC_RD_CTL(base)         (LTC_CTL_REG(base))
12481 #define LTC_WR_CTL(base, value)  (LTC_CTL_REG(base) = (value))
12482 #define LTC_RMW_CTL(base, mask, value) (LTC_WR_CTL(base, (LTC_RD_CTL(base) & ~(mask)) | (value)))
12483 #define LTC_SET_CTL(base, value) (BME_OR32(&LTC_CTL_REG(base), (uint32_t)(value)))
12484 #define LTC_CLR_CTL(base, value) (BME_AND32(&LTC_CTL_REG(base), (uint32_t)(~(value))))
12485 #define LTC_TOG_CTL(base, value) (BME_XOR32(&LTC_CTL_REG(base), (uint32_t)(value)))
12486 /*@}*/
12487 
12488 /*
12489  * Constants & macros for individual LTC_CTL bitfields
12490  */
12491 
12492 /*!
12493  * @name Register LTC_CTL, field IM[0] (RW)
12494  *
12495  * Interrupt Mask. Once this bit is set, it can only be cleared by hard reset.
12496  *
12497  * Values:
12498  * - 0b0 - Interrupt not masked.
12499  * - 0b1 - Interrupt masked
12500  */
12501 /*@{*/
12502 #define LTC_CTL_IM_INT_NOT_MASKED      (0U)          /*!< Bit field value for LTC_CTL_IM: Interrupt not masked. */
12503 #define LTC_CTL_IM_INT_MASKED          (0x1U)        /*!< Bit field value for LTC_CTL_IM: Interrupt masked */
12504 /*! @brief Read current value of the LTC_CTL_IM field. */
12505 #define LTC_RD_CTL_IM(base)  ((LTC_CTL_REG(base) & LTC_CTL_IM_MASK) >> LTC_CTL_IM_SHIFT)
12506 #define LTC_BRD_CTL_IM(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_IM_SHIFT, LTC_CTL_IM_WIDTH))
12507 
12508 /*! @brief Set the IM field to a new value. */
12509 #define LTC_WR_CTL_IM(base, value) (LTC_RMW_CTL(base, LTC_CTL_IM_MASK, LTC_CTL_IM(value)))
12510 #define LTC_BWR_CTL_IM(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_IM_SHIFT), LTC_CTL_IM_SHIFT, LTC_CTL_IM_WIDTH))
12511 /*@}*/
12512 
12513 /*!
12514  * @name Register LTC_CTL, field IFE[8] (RW)
12515  *
12516  * Input FIFO DMA Enable.
12517  *
12518  * Values:
12519  * - 0b0 - DMA Request and Done signals disabled for the Input FIFO.
12520  * - 0b1 - DMA Request and Done signals enabled for the Input FIFO.
12521  */
12522 /*@{*/
12523 #define LTC_CTL_IFE_IFE_DISABLED       (0U)          /*!< Bit field value for LTC_CTL_IFE: DMA Request and Done signals disabled for the Input FIFO. */
12524 #define LTC_CTL_IFE_IFE_ENABLED        (0x1U)        /*!< Bit field value for LTC_CTL_IFE: DMA Request and Done signals enabled for the Input FIFO. */
12525 /*! @brief Read current value of the LTC_CTL_IFE field. */
12526 #define LTC_RD_CTL_IFE(base) ((LTC_CTL_REG(base) & LTC_CTL_IFE_MASK) >> LTC_CTL_IFE_SHIFT)
12527 #define LTC_BRD_CTL_IFE(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_IFE_SHIFT, LTC_CTL_IFE_WIDTH))
12528 
12529 /*! @brief Set the IFE field to a new value. */
12530 #define LTC_WR_CTL_IFE(base, value) (LTC_RMW_CTL(base, LTC_CTL_IFE_MASK, LTC_CTL_IFE(value)))
12531 #define LTC_BWR_CTL_IFE(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_IFE_SHIFT), LTC_CTL_IFE_SHIFT, LTC_CTL_IFE_WIDTH))
12532 /*@}*/
12533 
12534 /*!
12535  * @name Register LTC_CTL, field IFR[9] (RW)
12536  *
12537  * Input FIFO DMA Request Size. The DMA request logic will only request data if
12538  * the INPUT FIFO has enough space for the request size.
12539  *
12540  * Values:
12541  * - 0b0 - DMA request size is 1 entry.
12542  * - 0b1 - DMA request size is 4 entries.
12543  */
12544 /*@{*/
12545 #define LTC_CTL_IFR_IFR_1              (0U)          /*!< Bit field value for LTC_CTL_IFR: DMA request size is 1 entry. */
12546 #define LTC_CTL_IFR_IFR_4              (0x1U)        /*!< Bit field value for LTC_CTL_IFR: DMA request size is 4 entries. */
12547 /*! @brief Read current value of the LTC_CTL_IFR field. */
12548 #define LTC_RD_CTL_IFR(base) ((LTC_CTL_REG(base) & LTC_CTL_IFR_MASK) >> LTC_CTL_IFR_SHIFT)
12549 #define LTC_BRD_CTL_IFR(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_IFR_SHIFT, LTC_CTL_IFR_WIDTH))
12550 
12551 /*! @brief Set the IFR field to a new value. */
12552 #define LTC_WR_CTL_IFR(base, value) (LTC_RMW_CTL(base, LTC_CTL_IFR_MASK, LTC_CTL_IFR(value)))
12553 #define LTC_BWR_CTL_IFR(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_IFR_SHIFT), LTC_CTL_IFR_SHIFT, LTC_CTL_IFR_WIDTH))
12554 /*@}*/
12555 
12556 /*!
12557  * @name Register LTC_CTL, field OFE[12] (RW)
12558  *
12559  * Output FIFO DMA Enable.
12560  *
12561  * Values:
12562  * - 0b0 - DMA Request and Done signals disabled for the Output FIFO.
12563  * - 0b1 - DMA Request and Done signals enabled for the Output FIFO.
12564  */
12565 /*@{*/
12566 #define LTC_CTL_OFE_OFE_DISABLED       (0U)          /*!< Bit field value for LTC_CTL_OFE: DMA Request and Done signals disabled for the Output FIFO. */
12567 #define LTC_CTL_OFE_OFE_ENABLED        (0x1U)        /*!< Bit field value for LTC_CTL_OFE: DMA Request and Done signals enabled for the Output FIFO. */
12568 /*! @brief Read current value of the LTC_CTL_OFE field. */
12569 #define LTC_RD_CTL_OFE(base) ((LTC_CTL_REG(base) & LTC_CTL_OFE_MASK) >> LTC_CTL_OFE_SHIFT)
12570 #define LTC_BRD_CTL_OFE(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_OFE_SHIFT, LTC_CTL_OFE_WIDTH))
12571 
12572 /*! @brief Set the OFE field to a new value. */
12573 #define LTC_WR_CTL_OFE(base, value) (LTC_RMW_CTL(base, LTC_CTL_OFE_MASK, LTC_CTL_OFE(value)))
12574 #define LTC_BWR_CTL_OFE(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_OFE_SHIFT), LTC_CTL_OFE_SHIFT, LTC_CTL_OFE_WIDTH))
12575 /*@}*/
12576 
12577 /*!
12578  * @name Register LTC_CTL, field OFR[13] (RW)
12579  *
12580  * Output FIFO DMA Request Size. The DMA request logic will only request data if
12581  * the OUTPUT FIFO has enough data to satisfy the request.
12582  *
12583  * Values:
12584  * - 0b0 - DMA request size is 1 entry.
12585  * - 0b1 - DMA request size is 4 entries.
12586  */
12587 /*@{*/
12588 #define LTC_CTL_OFR_OFR_1              (0U)          /*!< Bit field value for LTC_CTL_OFR: DMA request size is 1 entry. */
12589 #define LTC_CTL_OFR_OFR_4              (0x1U)        /*!< Bit field value for LTC_CTL_OFR: DMA request size is 4 entries. */
12590 /*! @brief Read current value of the LTC_CTL_OFR field. */
12591 #define LTC_RD_CTL_OFR(base) ((LTC_CTL_REG(base) & LTC_CTL_OFR_MASK) >> LTC_CTL_OFR_SHIFT)
12592 #define LTC_BRD_CTL_OFR(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_OFR_SHIFT, LTC_CTL_OFR_WIDTH))
12593 
12594 /*! @brief Set the OFR field to a new value. */
12595 #define LTC_WR_CTL_OFR(base, value) (LTC_RMW_CTL(base, LTC_CTL_OFR_MASK, LTC_CTL_OFR(value)))
12596 #define LTC_BWR_CTL_OFR(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_OFR_SHIFT), LTC_CTL_OFR_SHIFT, LTC_CTL_OFR_WIDTH))
12597 /*@}*/
12598 
12599 /*!
12600  * @name Register LTC_CTL, field IFS[16] (RW)
12601  *
12602  * Input FIFO Byte Swap. Byte swap all data that is written to the Input FIFO.
12603  *
12604  * Values:
12605  * - 0b0 - Do Not Byte Swap Data.
12606  * - 0b1 - Byte Swap Data.
12607  */
12608 /*@{*/
12609 #define LTC_CTL_IFS_IFS_NO_SWAP        (0U)          /*!< Bit field value for LTC_CTL_IFS: Do Not Byte Swap Data. */
12610 #define LTC_CTL_IFS_IFS_SWAP           (0x1U)        /*!< Bit field value for LTC_CTL_IFS: Byte Swap Data. */
12611 /*! @brief Read current value of the LTC_CTL_IFS field. */
12612 #define LTC_RD_CTL_IFS(base) ((LTC_CTL_REG(base) & LTC_CTL_IFS_MASK) >> LTC_CTL_IFS_SHIFT)
12613 #define LTC_BRD_CTL_IFS(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_IFS_SHIFT, LTC_CTL_IFS_WIDTH))
12614 
12615 /*! @brief Set the IFS field to a new value. */
12616 #define LTC_WR_CTL_IFS(base, value) (LTC_RMW_CTL(base, LTC_CTL_IFS_MASK, LTC_CTL_IFS(value)))
12617 #define LTC_BWR_CTL_IFS(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_IFS_SHIFT), LTC_CTL_IFS_SHIFT, LTC_CTL_IFS_WIDTH))
12618 /*@}*/
12619 
12620 /*!
12621  * @name Register LTC_CTL, field OFS[17] (RW)
12622  *
12623  * Output FIFO Byte Swap. Byte swap all data that is read from the Onput FIFO.
12624  *
12625  * Values:
12626  * - 0b0 - Do Not Byte Swap Data.
12627  * - 0b1 - Byte Swap Data.
12628  */
12629 /*@{*/
12630 #define LTC_CTL_OFS_OFS_NO_SWAP        (0U)          /*!< Bit field value for LTC_CTL_OFS: Do Not Byte Swap Data. */
12631 #define LTC_CTL_OFS_OFS_SWAP           (0x1U)        /*!< Bit field value for LTC_CTL_OFS: Byte Swap Data. */
12632 /*! @brief Read current value of the LTC_CTL_OFS field. */
12633 #define LTC_RD_CTL_OFS(base) ((LTC_CTL_REG(base) & LTC_CTL_OFS_MASK) >> LTC_CTL_OFS_SHIFT)
12634 #define LTC_BRD_CTL_OFS(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_OFS_SHIFT, LTC_CTL_OFS_WIDTH))
12635 
12636 /*! @brief Set the OFS field to a new value. */
12637 #define LTC_WR_CTL_OFS(base, value) (LTC_RMW_CTL(base, LTC_CTL_OFS_MASK, LTC_CTL_OFS(value)))
12638 #define LTC_BWR_CTL_OFS(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_OFS_SHIFT), LTC_CTL_OFS_SHIFT, LTC_CTL_OFS_WIDTH))
12639 /*@}*/
12640 
12641 /*!
12642  * @name Register LTC_CTL, field KIS[20] (RW)
12643  *
12644  * Key Register Input Byte Swap. Byte swap all data that is written to the key
12645  * register. Data is byte swapped only within a single word.
12646  *
12647  * Values:
12648  * - 0b0 - Do Not Byte Swap Data.
12649  * - 0b1 - Byte Swap Data.
12650  */
12651 /*@{*/
12652 #define LTC_CTL_KIS_KIS_NO_SWAP        (0U)          /*!< Bit field value for LTC_CTL_KIS: Do Not Byte Swap Data. */
12653 #define LTC_CTL_KIS_KIS_SWAP           (0x1U)        /*!< Bit field value for LTC_CTL_KIS: Byte Swap Data. */
12654 /*! @brief Read current value of the LTC_CTL_KIS field. */
12655 #define LTC_RD_CTL_KIS(base) ((LTC_CTL_REG(base) & LTC_CTL_KIS_MASK) >> LTC_CTL_KIS_SHIFT)
12656 #define LTC_BRD_CTL_KIS(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_KIS_SHIFT, LTC_CTL_KIS_WIDTH))
12657 
12658 /*! @brief Set the KIS field to a new value. */
12659 #define LTC_WR_CTL_KIS(base, value) (LTC_RMW_CTL(base, LTC_CTL_KIS_MASK, LTC_CTL_KIS(value)))
12660 #define LTC_BWR_CTL_KIS(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_KIS_SHIFT), LTC_CTL_KIS_SHIFT, LTC_CTL_KIS_WIDTH))
12661 /*@}*/
12662 
12663 /*!
12664  * @name Register LTC_CTL, field KOS[21] (RW)
12665  *
12666  * Key Register Output Byte Swap. Byte swap all data that is read from the key
12667  * register. Data is byte swapped only within a single word.
12668  *
12669  * Values:
12670  * - 0b0 - Do Not Byte Swap Data.
12671  * - 0b1 - Byte Swap Data.
12672  */
12673 /*@{*/
12674 #define LTC_CTL_KOS_KOS_NO_SWAP        (0U)          /*!< Bit field value for LTC_CTL_KOS: Do Not Byte Swap Data. */
12675 #define LTC_CTL_KOS_KOS_SWAP           (0x1U)        /*!< Bit field value for LTC_CTL_KOS: Byte Swap Data. */
12676 /*! @brief Read current value of the LTC_CTL_KOS field. */
12677 #define LTC_RD_CTL_KOS(base) ((LTC_CTL_REG(base) & LTC_CTL_KOS_MASK) >> LTC_CTL_KOS_SHIFT)
12678 #define LTC_BRD_CTL_KOS(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_KOS_SHIFT, LTC_CTL_KOS_WIDTH))
12679 
12680 /*! @brief Set the KOS field to a new value. */
12681 #define LTC_WR_CTL_KOS(base, value) (LTC_RMW_CTL(base, LTC_CTL_KOS_MASK, LTC_CTL_KOS(value)))
12682 #define LTC_BWR_CTL_KOS(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_KOS_SHIFT), LTC_CTL_KOS_SHIFT, LTC_CTL_KOS_WIDTH))
12683 /*@}*/
12684 
12685 /*!
12686  * @name Register LTC_CTL, field CIS[22] (RW)
12687  *
12688  * Context Register Input Byte Swap. Byte swap all data that is written to the
12689  * context register. Data is byte swapped only within a single word.
12690  *
12691  * Values:
12692  * - 0b0 - Do Not Byte Swap Data.
12693  * - 0b1 - Byte Swap Data.
12694  */
12695 /*@{*/
12696 #define LTC_CTL_CIS_CIS_NO_SWAP        (0U)          /*!< Bit field value for LTC_CTL_CIS: Do Not Byte Swap Data. */
12697 #define LTC_CTL_CIS_CIS_SWAP           (0x1U)        /*!< Bit field value for LTC_CTL_CIS: Byte Swap Data. */
12698 /*! @brief Read current value of the LTC_CTL_CIS field. */
12699 #define LTC_RD_CTL_CIS(base) ((LTC_CTL_REG(base) & LTC_CTL_CIS_MASK) >> LTC_CTL_CIS_SHIFT)
12700 #define LTC_BRD_CTL_CIS(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_CIS_SHIFT, LTC_CTL_CIS_WIDTH))
12701 
12702 /*! @brief Set the CIS field to a new value. */
12703 #define LTC_WR_CTL_CIS(base, value) (LTC_RMW_CTL(base, LTC_CTL_CIS_MASK, LTC_CTL_CIS(value)))
12704 #define LTC_BWR_CTL_CIS(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_CIS_SHIFT), LTC_CTL_CIS_SHIFT, LTC_CTL_CIS_WIDTH))
12705 /*@}*/
12706 
12707 /*!
12708  * @name Register LTC_CTL, field COS[23] (RW)
12709  *
12710  * Context Register Output Byte Swap. Byte swap all data that is read from the
12711  * context register. Data is byte swapped only within a single word.
12712  *
12713  * Values:
12714  * - 0b0 - Do Not Byte Swap Data.
12715  * - 0b1 - Byte Swap Data.
12716  */
12717 /*@{*/
12718 #define LTC_CTL_COS_COS_NO_SWAP        (0U)          /*!< Bit field value for LTC_CTL_COS: Do Not Byte Swap Data. */
12719 #define LTC_CTL_COS_COS_SWAP           (0x1U)        /*!< Bit field value for LTC_CTL_COS: Byte Swap Data. */
12720 /*! @brief Read current value of the LTC_CTL_COS field. */
12721 #define LTC_RD_CTL_COS(base) ((LTC_CTL_REG(base) & LTC_CTL_COS_MASK) >> LTC_CTL_COS_SHIFT)
12722 #define LTC_BRD_CTL_COS(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_COS_SHIFT, LTC_CTL_COS_WIDTH))
12723 
12724 /*! @brief Set the COS field to a new value. */
12725 #define LTC_WR_CTL_COS(base, value) (LTC_RMW_CTL(base, LTC_CTL_COS_MASK, LTC_CTL_COS(value)))
12726 #define LTC_BWR_CTL_COS(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_COS_SHIFT), LTC_CTL_COS_SHIFT, LTC_CTL_COS_WIDTH))
12727 /*@}*/
12728 
12729 /*!
12730  * @name Register LTC_CTL, field KAL[31] (RW)
12731  *
12732  * Key Register Access Lock. Read access to the key register is blocked. Any
12733  * reads of the key register will only return zero. Once this bit is set, it can
12734  * only be cleared by hard reset.
12735  *
12736  * Values:
12737  * - 0b0 - Key Register is readable.
12738  * - 0b1 - Key Register is not readable.
12739  */
12740 /*@{*/
12741 #define LTC_CTL_KAL_KAL_READABLE       (0U)          /*!< Bit field value for LTC_CTL_KAL: Key Register is readable. */
12742 #define LTC_CTL_KAL_KAL_NOT_READABLE   (0x1U)        /*!< Bit field value for LTC_CTL_KAL: Key Register is not readable. */
12743 /*! @brief Read current value of the LTC_CTL_KAL field. */
12744 #define LTC_RD_CTL_KAL(base) ((LTC_CTL_REG(base) & LTC_CTL_KAL_MASK) >> LTC_CTL_KAL_SHIFT)
12745 #define LTC_BRD_CTL_KAL(base) (BME_UBFX32(&LTC_CTL_REG(base), LTC_CTL_KAL_SHIFT, LTC_CTL_KAL_WIDTH))
12746 
12747 /*! @brief Set the KAL field to a new value. */
12748 #define LTC_WR_CTL_KAL(base, value) (LTC_RMW_CTL(base, LTC_CTL_KAL_MASK, LTC_CTL_KAL(value)))
12749 #define LTC_BWR_CTL_KAL(base, value) (BME_BFI32(&LTC_CTL_REG(base), ((uint32_t)(value) << LTC_CTL_KAL_SHIFT), LTC_CTL_KAL_SHIFT, LTC_CTL_KAL_WIDTH))
12750 /*@}*/
12751 
12752 /*******************************************************************************
12753  * LTC_CW - LTC Clear Written Register
12754  ******************************************************************************/
12755 
12756 /*!
12757  * @brief LTC_CW - LTC Clear Written Register (WO)
12758  *
12759  * Reset value: 0x00000000U
12760  *
12761  * The Clear Written Register is used to clear many of the internal registers.
12762  * All fields of this register are self-clearing.
12763  */
12764 /*!
12765  * @name Constants and macros for entire LTC_CW register
12766  */
12767 /*@{*/
12768 #define LTC_WR_CW(base, value)   (LTC_CW_REG(base) = (value))
12769 /*@}*/
12770 
12771 /*
12772  * Constants & macros for individual LTC_CW bitfields
12773  */
12774 
12775 /*!
12776  * @name Register LTC_CW, field CM[0] (WO)
12777  *
12778  * Clear the Mode Register. Writing a one to this bit causes the Mode Register
12779  * to be cleared.
12780  */
12781 /*@{*/
12782 /*! @brief Set the CM field to a new value. */
12783 #define LTC_WR_CW_CM(base, value) (LTC_WR_CW(base, LTC_CW_CM(value)))
12784 #define LTC_BWR_CW_CM(base, value) (LTC_WR_CW_CM(base, value))
12785 /*@}*/
12786 
12787 /*!
12788  * @name Register LTC_CW, field CDS[2] (WO)
12789  *
12790  * Clear the Data Size Register. Writing a one to this bit causes the Data Size
12791  * Register to be cleared. This clears AAD Size as well.
12792  */
12793 /*@{*/
12794 /*! @brief Set the CDS field to a new value. */
12795 #define LTC_WR_CW_CDS(base, value) (LTC_WR_CW(base, LTC_CW_CDS(value)))
12796 #define LTC_BWR_CW_CDS(base, value) (LTC_WR_CW_CDS(base, value))
12797 /*@}*/
12798 
12799 /*!
12800  * @name Register LTC_CW, field CICV[3] (WO)
12801  *
12802  * Clear the ICV Size Register. Writing a one to this bit causes the ICV Size
12803  * Register to be cleared.
12804  */
12805 /*@{*/
12806 /*! @brief Set the CICV field to a new value. */
12807 #define LTC_WR_CW_CICV(base, value) (LTC_WR_CW(base, LTC_CW_CICV(value)))
12808 #define LTC_BWR_CW_CICV(base, value) (LTC_WR_CW_CICV(base, value))
12809 /*@}*/
12810 
12811 /*!
12812  * @name Register LTC_CW, field CCR[5] (WO)
12813  *
12814  * Clear the Context Register. Writing a one to this bit causes the Context
12815  * Register to be cleared.
12816  */
12817 /*@{*/
12818 /*! @brief Set the CCR field to a new value. */
12819 #define LTC_WR_CW_CCR(base, value) (LTC_WR_CW(base, LTC_CW_CCR(value)))
12820 #define LTC_BWR_CW_CCR(base, value) (LTC_WR_CW_CCR(base, value))
12821 /*@}*/
12822 
12823 /*!
12824  * @name Register LTC_CW, field CKR[6] (WO)
12825  *
12826  * Clear the Key Register. Writing a one to this bit causes the Key and Key Size
12827  * Registers to be cleared.
12828  */
12829 /*@{*/
12830 /*! @brief Set the CKR field to a new value. */
12831 #define LTC_WR_CW_CKR(base, value) (LTC_WR_CW(base, LTC_CW_CKR(value)))
12832 #define LTC_BWR_CW_CKR(base, value) (LTC_WR_CW_CKR(base, value))
12833 /*@}*/
12834 
12835 /*!
12836  * @name Register LTC_CW, field COF[30] (WO)
12837  *
12838  * Clear Output FIFO. Writing a 1 to this bit causes the Output FIFO to be
12839  * cleared.
12840  */
12841 /*@{*/
12842 /*! @brief Set the COF field to a new value. */
12843 #define LTC_WR_CW_COF(base, value) (LTC_WR_CW(base, LTC_CW_COF(value)))
12844 #define LTC_BWR_CW_COF(base, value) (LTC_WR_CW_COF(base, value))
12845 /*@}*/
12846 
12847 /*!
12848  * @name Register LTC_CW, field CIF[31] (WO)
12849  *
12850  * Clear Input FIFO. Writing a 1 to this bit causes the Input Data FIFO.
12851  */
12852 /*@{*/
12853 /*! @brief Set the CIF field to a new value. */
12854 #define LTC_WR_CW_CIF(base, value) (LTC_WR_CW(base, LTC_CW_CIF(value)))
12855 #define LTC_BWR_CW_CIF(base, value) (LTC_WR_CW_CIF(base, value))
12856 /*@}*/
12857 
12858 /*******************************************************************************
12859  * LTC_STA - LTC Status Register
12860  ******************************************************************************/
12861 
12862 /*!
12863  * @brief LTC_STA - LTC Status Register (RW)
12864  *
12865  * Reset value: 0x00000000U
12866  *
12867  * The LTC Status Register shows the status of the internal Crypto engine and
12868  * its internal registers.
12869  */
12870 /*!
12871  * @name Constants and macros for entire LTC_STA register
12872  */
12873 /*@{*/
12874 #define LTC_RD_STA(base)         (LTC_STA_REG(base))
12875 #define LTC_WR_STA(base, value)  (LTC_STA_REG(base) = (value))
12876 #define LTC_RMW_STA(base, mask, value) (LTC_WR_STA(base, (LTC_RD_STA(base) & ~(mask)) | (value)))
12877 #define LTC_SET_STA(base, value) (BME_OR32(&LTC_STA_REG(base), (uint32_t)(value)))
12878 #define LTC_CLR_STA(base, value) (BME_AND32(&LTC_STA_REG(base), (uint32_t)(~(value))))
12879 #define LTC_TOG_STA(base, value) (BME_XOR32(&LTC_STA_REG(base), (uint32_t)(value)))
12880 /*@}*/
12881 
12882 /*
12883  * Constants & macros for individual LTC_STA bitfields
12884  */
12885 
12886 /*!
12887  * @name Register LTC_STA, field AB[1] (RO)
12888  *
12889  * AESA Busy. This bit indicates that the AES Accelertor is busy. The CHA can
12890  * either be busy processing data or resetting.
12891  *
12892  * Values:
12893  * - 0b0 - AESA Idle
12894  * - 0b1 - AESA Busy.
12895  */
12896 /*@{*/
12897 #define LTC_STA_AB_AESA_IDLE           (0U)          /*!< Bit field value for LTC_STA_AB: AESA Idle */
12898 #define LTC_STA_AB_AESA_BUSY           (0x1U)        /*!< Bit field value for LTC_STA_AB: AESA Busy. */
12899 /*! @brief Read current value of the LTC_STA_AB field. */
12900 #define LTC_RD_STA_AB(base)  ((LTC_STA_REG(base) & LTC_STA_AB_MASK) >> LTC_STA_AB_SHIFT)
12901 #define LTC_BRD_STA_AB(base) (BME_UBFX32(&LTC_STA_REG(base), LTC_STA_AB_SHIFT, LTC_STA_AB_WIDTH))
12902 /*@}*/
12903 
12904 /*!
12905  * @name Register LTC_STA, field DI[16] (W1C)
12906  *
12907  * Done Interrupt. The Done Interrupt has been asserted. ValueReadWrite0No Done
12908  * InterruptNo change1Done Interrupt assertedClear the Done Interrupt
12909  */
12910 /*@{*/
12911 /*! @brief Read current value of the LTC_STA_DI field. */
12912 #define LTC_RD_STA_DI(base)  ((LTC_STA_REG(base) & LTC_STA_DI_MASK) >> LTC_STA_DI_SHIFT)
12913 #define LTC_BRD_STA_DI(base) (BME_UBFX32(&LTC_STA_REG(base), LTC_STA_DI_SHIFT, LTC_STA_DI_WIDTH))
12914 
12915 /*! @brief Set the DI field to a new value. */
12916 #define LTC_WR_STA_DI(base, value) (LTC_RMW_STA(base, LTC_STA_DI_MASK, LTC_STA_DI(value)))
12917 #define LTC_BWR_STA_DI(base, value) (BME_BFI32(&LTC_STA_REG(base), ((uint32_t)(value) << LTC_STA_DI_SHIFT), LTC_STA_DI_SHIFT, LTC_STA_DI_WIDTH))
12918 /*@}*/
12919 
12920 /*!
12921  * @name Register LTC_STA, field EI[20] (RO)
12922  *
12923  * Error Interrupt. The Error Interrupt has been asserted. This error can only
12924  * be cleared by resetting LTC.
12925  *
12926  * Values:
12927  * - 0b0 - Not Error.
12928  * - 0b1 - Error Interrupt.
12929  */
12930 /*@{*/
12931 #define LTC_STA_EI_NOT_ERROR_INT       (0U)          /*!< Bit field value for LTC_STA_EI: Not Error. */
12932 #define LTC_STA_EI_ERROR_INT           (0x1U)        /*!< Bit field value for LTC_STA_EI: Error Interrupt. */
12933 /*! @brief Read current value of the LTC_STA_EI field. */
12934 #define LTC_RD_STA_EI(base)  ((LTC_STA_REG(base) & LTC_STA_EI_MASK) >> LTC_STA_EI_SHIFT)
12935 #define LTC_BRD_STA_EI(base) (BME_UBFX32(&LTC_STA_REG(base), LTC_STA_EI_SHIFT, LTC_STA_EI_WIDTH))
12936 /*@}*/
12937 
12938 /*******************************************************************************
12939  * LTC_ESTA - LTC Error Status Register
12940  ******************************************************************************/
12941 
12942 /*!
12943  * @brief LTC_ESTA - LTC Error Status Register (RO)
12944  *
12945  * Reset value: 0x00000000U
12946  *
12947  * The LTC Error Register shows the status of the internal Crypto Engine and its
12948  * internal registers.
12949  */
12950 /*!
12951  * @name Constants and macros for entire LTC_ESTA register
12952  */
12953 /*@{*/
12954 #define LTC_RD_ESTA(base)        (LTC_ESTA_REG(base))
12955 /*@}*/
12956 
12957 /*
12958  * Constants & macros for individual LTC_ESTA bitfields
12959  */
12960 
12961 /*!
12962  * @name Register LTC_ESTA, field ERRID1[3:0] (RO)
12963  *
12964  * Error ID 1. These bits indicate the type of error that was found while
12965  * processing the Descriptor. The Algorithm that is associated with the error can be
12966  * found in the CL1 field.Others reserved.
12967  *
12968  * Values:
12969  * - 0b0001 - Mode Error
12970  * - 0b0010 - Data Size Error
12971  * - 0b0011 - Key Size Error
12972  * - 0b0110 - Data Arrived out of Sequence Error
12973  * - 0b1010 - ICV Check Failed
12974  * - 0b1011 - Internal Hardware Failure
12975  * - 0b1100 - CCM AAD Size Error (either 1. AAD flag in B0 =1 and no AAD type
12976  *     provided, 2. AAD flag in B0 = 0 and AAD povided, or 3. AAD flag in B0 =1 and
12977  *     not enough AAD provided - expecting more based on AAD size.)
12978  * - 0b1111 - Invalid Crypto Engine Selected
12979  */
12980 /*@{*/
12981 #define LTC_ESTA_ERRID1_MODE_ERROR     (0x1U)        /*!< Bit field value for LTC_ESTA_ERRID1: Mode Error */
12982 #define LTC_ESTA_ERRID1_DATA_SIZE_ERROR (0x2U)       /*!< Bit field value for LTC_ESTA_ERRID1: Data Size Error */
12983 #define LTC_ESTA_ERRID1_KEY_SIZE_ERROR (0x3U)        /*!< Bit field value for LTC_ESTA_ERRID1: Key Size Error */
12984 #define LTC_ESTA_ERRID1_DATA_OUT_OF_SEQ_ERROR (0x6U) /*!< Bit field value for LTC_ESTA_ERRID1: Data Arrived out of Sequence Error */
12985 #define LTC_ESTA_ERRID1_ICV_CHECK_FAIL (0xAU)        /*!< Bit field value for LTC_ESTA_ERRID1: ICV Check Failed */
12986 #define LTC_ESTA_ERRID1_INTERNAL_HARD_FAIL (0xBU)    /*!< Bit field value for LTC_ESTA_ERRID1: Internal Hardware Failure */
12987 #define LTC_ESTA_ERRID1_CCM_AAD_SIZE_ERROR (0xCU)    /*!< Bit field value for LTC_ESTA_ERRID1: CCM AAD Size Error (either 1. AAD flag in B0 =1 and no AAD type provided, 2. AAD flag in B0 = 0 and AAD povided, or 3. AAD flag in B0 =1 and not enough AAD provided - expecting more based on AAD size.) */
12988 #define LTC_ESTA_ERRID1_INVALID_ENGINE_SEL_ERROR (0xFU) /*!< Bit field value for LTC_ESTA_ERRID1: Invalid Crypto Engine Selected */
12989 /*! @brief Read current value of the LTC_ESTA_ERRID1 field. */
12990 #define LTC_RD_ESTA_ERRID1(base) ((LTC_ESTA_REG(base) & LTC_ESTA_ERRID1_MASK) >> LTC_ESTA_ERRID1_SHIFT)
12991 #define LTC_BRD_ESTA_ERRID1(base) (BME_UBFX32(&LTC_ESTA_REG(base), LTC_ESTA_ERRID1_SHIFT, LTC_ESTA_ERRID1_WIDTH))
12992 /*@}*/
12993 
12994 /*!
12995  * @name Register LTC_ESTA, field CL1[11:8] (RO)
12996  *
12997  * algorithms. The algorithms field indicates which algorithm is asserting an
12998  * error.Others reserved
12999  *
13000  * Values:
13001  * - 0b0000 - LTC General Error
13002  * - 0b0001 - AES
13003  */
13004 /*@{*/
13005 #define LTC_ESTA_CL1_GEN_ERROR         (0U)          /*!< Bit field value for LTC_ESTA_CL1: LTC General Error */
13006 #define LTC_ESTA_CL1_AES_ERROR         (0x1U)        /*!< Bit field value for LTC_ESTA_CL1: AES */
13007 /*! @brief Read current value of the LTC_ESTA_CL1 field. */
13008 #define LTC_RD_ESTA_CL1(base) ((LTC_ESTA_REG(base) & LTC_ESTA_CL1_MASK) >> LTC_ESTA_CL1_SHIFT)
13009 #define LTC_BRD_ESTA_CL1(base) (BME_UBFX32(&LTC_ESTA_REG(base), LTC_ESTA_CL1_SHIFT, LTC_ESTA_CL1_WIDTH))
13010 /*@}*/
13011 
13012 /*******************************************************************************
13013  * LTC_AADSZ - LTC AAD Size Register
13014  ******************************************************************************/
13015 
13016 /*!
13017  * @brief LTC_AADSZ - LTC AAD Size Register (RW)
13018  *
13019  * Reset value: 0x00000000U
13020  *
13021  * The AAD Size Register is used by AESA to determine how much of the last block
13022  * of AAD is valid. The write to this register should be the entire size of the
13023  * AAD as it is also added directly to the Data Size Register. The size added to
13024  * the Data Size Register is the AAD size rounded up to the next 16 byte
13025  * boundary. For instance a size of 20 bytes written to the AAD size register will cause
13026  * 32 bytes to be added to the Data Size Register. The size stored in the AADSZ
13027  * field represents the number of bytes valid in the final block of AAD. However
13028  * the entire size of AAD should be written to the Register address location. When
13029  * authentication only is being done then the AL bit needs to be written to tell
13030  * the AES engine that this is the last of the data.
13031  */
13032 /*!
13033  * @name Constants and macros for entire LTC_AADSZ register
13034  */
13035 /*@{*/
13036 #define LTC_RD_AADSZ(base)       (LTC_AADSZ_REG(base))
13037 #define LTC_WR_AADSZ(base, value) (LTC_AADSZ_REG(base) = (value))
13038 #define LTC_RMW_AADSZ(base, mask, value) (LTC_WR_AADSZ(base, (LTC_RD_AADSZ(base) & ~(mask)) | (value)))
13039 #define LTC_SET_AADSZ(base, value) (BME_OR32(&LTC_AADSZ_REG(base), (uint32_t)(value)))
13040 #define LTC_CLR_AADSZ(base, value) (BME_AND32(&LTC_AADSZ_REG(base), (uint32_t)(~(value))))
13041 #define LTC_TOG_AADSZ(base, value) (BME_XOR32(&LTC_AADSZ_REG(base), (uint32_t)(value)))
13042 /*@}*/
13043 
13044 /*
13045  * Constants & macros for individual LTC_AADSZ bitfields
13046  */
13047 
13048 /*!
13049  * @name Register LTC_AADSZ, field AADSZ[3:0] (RW)
13050  *
13051  * AAD size in Bytes, mod 16.
13052  */
13053 /*@{*/
13054 /*! @brief Read current value of the LTC_AADSZ_AADSZ field. */
13055 #define LTC_RD_AADSZ_AADSZ(base) ((LTC_AADSZ_REG(base) & LTC_AADSZ_AADSZ_MASK) >> LTC_AADSZ_AADSZ_SHIFT)
13056 #define LTC_BRD_AADSZ_AADSZ(base) (BME_UBFX32(&LTC_AADSZ_REG(base), LTC_AADSZ_AADSZ_SHIFT, LTC_AADSZ_AADSZ_WIDTH))
13057 
13058 /*! @brief Set the AADSZ field to a new value. */
13059 #define LTC_WR_AADSZ_AADSZ(base, value) (LTC_RMW_AADSZ(base, LTC_AADSZ_AADSZ_MASK, LTC_AADSZ_AADSZ(value)))
13060 #define LTC_BWR_AADSZ_AADSZ(base, value) (BME_BFI32(&LTC_AADSZ_REG(base), ((uint32_t)(value) << LTC_AADSZ_AADSZ_SHIFT), LTC_AADSZ_AADSZ_SHIFT, LTC_AADSZ_AADSZ_WIDTH))
13061 /*@}*/
13062 
13063 /*!
13064  * @name Register LTC_AADSZ, field AL[31] (RW)
13065  *
13066  * AAD Last. Only AAD data will be written into the Input FIFO.
13067  */
13068 /*@{*/
13069 /*! @brief Read current value of the LTC_AADSZ_AL field. */
13070 #define LTC_RD_AADSZ_AL(base) ((LTC_AADSZ_REG(base) & LTC_AADSZ_AL_MASK) >> LTC_AADSZ_AL_SHIFT)
13071 #define LTC_BRD_AADSZ_AL(base) (BME_UBFX32(&LTC_AADSZ_REG(base), LTC_AADSZ_AL_SHIFT, LTC_AADSZ_AL_WIDTH))
13072 
13073 /*! @brief Set the AL field to a new value. */
13074 #define LTC_WR_AADSZ_AL(base, value) (LTC_RMW_AADSZ(base, LTC_AADSZ_AL_MASK, LTC_AADSZ_AL(value)))
13075 #define LTC_BWR_AADSZ_AL(base, value) (BME_BFI32(&LTC_AADSZ_REG(base), ((uint32_t)(value) << LTC_AADSZ_AL_SHIFT), LTC_AADSZ_AL_SHIFT, LTC_AADSZ_AL_WIDTH))
13076 /*@}*/
13077 
13078 /*******************************************************************************
13079  * LTC_CTX - LTC Context Register
13080  ******************************************************************************/
13081 
13082 /*!
13083  * @brief LTC_CTX - LTC Context Register (RW)
13084  *
13085  * Reset value: 0x00000000U
13086  *
13087  * The Context Register holds the context for the internal crypto engine. This
13088  * register is 512 bits in length. The IP bus write to the Context Register is
13089  * accessible only as full-word reads or writes to sixteen 32-bit registers. The MSB
13090  * is located at offset 0100h with respect to the register page. The bit
13091  * assignments of this register are dependent on the algorithm, and in some cases the
13092  * mode of that algorithm. See the appropriate section for the Context Register
13093  * format used for that algorithm: AES ECB: Section AES CBC: Section AES CTR:
13094  * Section AES CCM: Section
13095  */
13096 /*!
13097  * @name Constants and macros for entire LTC_CTX register
13098  */
13099 /*@{*/
13100 #define LTC_RD_CTX(base, index)  (LTC_CTX_REG(base, index))
13101 #define LTC_WR_CTX(base, index, value) (LTC_CTX_REG(base, index) = (value))
13102 #define LTC_RMW_CTX(base, index, mask, value) (LTC_WR_CTX(base, index, (LTC_RD_CTX(base, index) & ~(mask)) | (value)))
13103 #define LTC_SET_CTX(base, index, value) (BME_OR32(&LTC_CTX_REG(base, index), (uint32_t)(value)))
13104 #define LTC_CLR_CTX(base, index, value) (BME_AND32(&LTC_CTX_REG(base, index), (uint32_t)(~(value))))
13105 #define LTC_TOG_CTX(base, index, value) (BME_XOR32(&LTC_CTX_REG(base, index), (uint32_t)(value)))
13106 /*@}*/
13107 
13108 /*******************************************************************************
13109  * LTC_KEY - LTC Key Registers
13110  ******************************************************************************/
13111 
13112 /*!
13113  * @brief LTC_KEY - LTC Key Registers (RW)
13114  *
13115  * Reset value: 0x00000000U
13116  *
13117  * The Key Register normally holds the left-aligned key for the internal crypto
13118  * engine. The MSB is in offset 200h. The Key Register is 128 bits in length. The
13119  * IP bus write to the Context Register is accessible only as full-word reads or
13120  * writes to four 32-bit registers. Before the value in the Key Register can be
13121  * used in a cryptographic operation, the size of the key must be written into
13122  * the Key Size Register. Once the Key Size Register has been written, the Key
13123  * Register cannot be written again until the Key Size Register has been cleared.
13124  */
13125 /*!
13126  * @name Constants and macros for entire LTC_KEY register
13127  */
13128 /*@{*/
13129 #define LTC_RD_KEY(base, index)  (LTC_KEY_REG(base, index))
13130 #define LTC_WR_KEY(base, index, value) (LTC_KEY_REG(base, index) = (value))
13131 #define LTC_RMW_KEY(base, index, mask, value) (LTC_WR_KEY(base, index, (LTC_RD_KEY(base, index) & ~(mask)) | (value)))
13132 #define LTC_SET_KEY(base, index, value) (BME_OR32(&LTC_KEY_REG(base, index), (uint32_t)(value)))
13133 #define LTC_CLR_KEY(base, index, value) (BME_AND32(&LTC_KEY_REG(base, index), (uint32_t)(~(value))))
13134 #define LTC_TOG_KEY(base, index, value) (BME_XOR32(&LTC_KEY_REG(base, index), (uint32_t)(value)))
13135 /*@}*/
13136 
13137 /*******************************************************************************
13138  * LTC_FIFOSTA - LTC FIFO Status Register
13139  ******************************************************************************/
13140 
13141 /*!
13142  * @brief LTC_FIFOSTA - LTC FIFO Status Register (RO)
13143  *
13144  * Reset value: 0x00000000U
13145  *
13146  * The LTC FIFO Status shows the current levels of the Input and Output FIFO.
13147  */
13148 /*!
13149  * @name Constants and macros for entire LTC_FIFOSTA register
13150  */
13151 /*@{*/
13152 #define LTC_RD_FIFOSTA(base)     (LTC_FIFOSTA_REG(base))
13153 /*@}*/
13154 
13155 /*
13156  * Constants & macros for individual LTC_FIFOSTA bitfields
13157  */
13158 
13159 /*!
13160  * @name Register LTC_FIFOSTA, field IFL[6:0] (RO)
13161  *
13162  * Input FIFO Level. These bits indicate the current number of entries in the
13163  * Input FIFO.
13164  */
13165 /*@{*/
13166 /*! @brief Read current value of the LTC_FIFOSTA_IFL field. */
13167 #define LTC_RD_FIFOSTA_IFL(base) ((LTC_FIFOSTA_REG(base) & LTC_FIFOSTA_IFL_MASK) >> LTC_FIFOSTA_IFL_SHIFT)
13168 #define LTC_BRD_FIFOSTA_IFL(base) (BME_UBFX32(&LTC_FIFOSTA_REG(base), LTC_FIFOSTA_IFL_SHIFT, LTC_FIFOSTA_IFL_WIDTH))
13169 /*@}*/
13170 
13171 /*!
13172  * @name Register LTC_FIFOSTA, field IFF[15] (RO)
13173  *
13174  * Input FIFO Full. The Input FIFO is full and should not be written to.
13175  */
13176 /*@{*/
13177 /*! @brief Read current value of the LTC_FIFOSTA_IFF field. */
13178 #define LTC_RD_FIFOSTA_IFF(base) ((LTC_FIFOSTA_REG(base) & LTC_FIFOSTA_IFF_MASK) >> LTC_FIFOSTA_IFF_SHIFT)
13179 #define LTC_BRD_FIFOSTA_IFF(base) (BME_UBFX32(&LTC_FIFOSTA_REG(base), LTC_FIFOSTA_IFF_SHIFT, LTC_FIFOSTA_IFF_WIDTH))
13180 /*@}*/
13181 
13182 /*!
13183  * @name Register LTC_FIFOSTA, field OFL[22:16] (RO)
13184  *
13185  * Output FIFO Level. These bits indicate the current number of entries in the
13186  * Output FIFO.
13187  */
13188 /*@{*/
13189 /*! @brief Read current value of the LTC_FIFOSTA_OFL field. */
13190 #define LTC_RD_FIFOSTA_OFL(base) ((LTC_FIFOSTA_REG(base) & LTC_FIFOSTA_OFL_MASK) >> LTC_FIFOSTA_OFL_SHIFT)
13191 #define LTC_BRD_FIFOSTA_OFL(base) (BME_UBFX32(&LTC_FIFOSTA_REG(base), LTC_FIFOSTA_OFL_SHIFT, LTC_FIFOSTA_OFL_WIDTH))
13192 /*@}*/
13193 
13194 /*!
13195  * @name Register LTC_FIFOSTA, field OFF[31] (RO)
13196  *
13197  * Output FIFO Full. The Output FIFO is full and should not be written to.
13198  */
13199 /*@{*/
13200 /*! @brief Read current value of the LTC_FIFOSTA_OFF field. */
13201 #define LTC_RD_FIFOSTA_OFF(base) ((LTC_FIFOSTA_REG(base) & LTC_FIFOSTA_OFF_MASK) >> LTC_FIFOSTA_OFF_SHIFT)
13202 #define LTC_BRD_FIFOSTA_OFF(base) (BME_UBFX32(&LTC_FIFOSTA_REG(base), LTC_FIFOSTA_OFF_SHIFT, LTC_FIFOSTA_OFF_WIDTH))
13203 /*@}*/
13204 
13205 /*******************************************************************************
13206  * LTC_IFIFO - LTC Input Data FIFO
13207  ******************************************************************************/
13208 
13209 /*!
13210  * @brief LTC_IFIFO - LTC Input Data FIFO (WO)
13211  *
13212  * Reset value: 0x00000000U
13213  *
13214  * Data to be processed by the various crypto engines is first pushed into the
13215  * Input Data FIFO. The Input Data FIFO supports byte enables, allowing one to
13216  * four bytes to be written to the IFIFO from the IP bus. The IFIFO is four entries
13217  * deep, and each entry is four bytes. Care must be used to not overflow the
13218  * Input Data FIFO. Reads from this address will always return 0x0.
13219  */
13220 /*!
13221  * @name Constants and macros for entire LTC_IFIFO register
13222  */
13223 /*@{*/
13224 #define LTC_WR_IFIFO(base, value) (LTC_IFIFO_REG(base) = (value))
13225 /*@}*/
13226 
13227 /*******************************************************************************
13228  * LTC_OFIFO - LTC Output Data FIFO
13229  ******************************************************************************/
13230 
13231 /*!
13232  * @brief LTC_OFIFO - LTC Output Data FIFO (RO)
13233  *
13234  * Reset value: 0x00000000U
13235  *
13236  * Data that is output from the AES is pushed into the Output Data FIFO. The
13237  * OFIFO is four entries deep, and each entry is four bytes. During normal
13238  * operation, the AES will never overflow the Output Data FIFO. Writes to this register
13239  * are ignored.
13240  */
13241 /*!
13242  * @name Constants and macros for entire LTC_OFIFO register
13243  */
13244 /*@{*/
13245 #define LTC_RD_OFIFO(base)       (LTC_OFIFO_REG(base))
13246 /*@}*/
13247 
13248 /*******************************************************************************
13249  * LTC_VID1 - LTC Version ID Register
13250  ******************************************************************************/
13251 
13252 /*!
13253  * @brief LTC_VID1 - LTC Version ID Register (RO)
13254  *
13255  * Reset value: 0x00340100U
13256  *
13257  * This register contains the ID for LTC and major and minor revision numbers.
13258  */
13259 /*!
13260  * @name Constants and macros for entire LTC_VID1 register
13261  */
13262 /*@{*/
13263 #define LTC_RD_VID1(base)        (LTC_VID1_REG(base))
13264 /*@}*/
13265 
13266 /*
13267  * Constants & macros for individual LTC_VID1 bitfields
13268  */
13269 
13270 /*!
13271  * @name Register LTC_VID1, field MIN_REV[7:0] (RO)
13272  *
13273  * Minor revision number(0x00).
13274  */
13275 /*@{*/
13276 /*! @brief Read current value of the LTC_VID1_MIN_REV field. */
13277 #define LTC_RD_VID1_MIN_REV(base) ((LTC_VID1_REG(base) & LTC_VID1_MIN_REV_MASK) >> LTC_VID1_MIN_REV_SHIFT)
13278 #define LTC_BRD_VID1_MIN_REV(base) (BME_UBFX32(&LTC_VID1_REG(base), LTC_VID1_MIN_REV_SHIFT, LTC_VID1_MIN_REV_WIDTH))
13279 /*@}*/
13280 
13281 /*!
13282  * @name Register LTC_VID1, field MAJ_REV[15:8] (RO)
13283  *
13284  * Major revision number(0x01).
13285  */
13286 /*@{*/
13287 /*! @brief Read current value of the LTC_VID1_MAJ_REV field. */
13288 #define LTC_RD_VID1_MAJ_REV(base) ((LTC_VID1_REG(base) & LTC_VID1_MAJ_REV_MASK) >> LTC_VID1_MAJ_REV_SHIFT)
13289 #define LTC_BRD_VID1_MAJ_REV(base) (BME_UBFX32(&LTC_VID1_REG(base), LTC_VID1_MAJ_REV_SHIFT, LTC_VID1_MAJ_REV_WIDTH))
13290 /*@}*/
13291 
13292 /*!
13293  * @name Register LTC_VID1, field IP_ID[31:16] (RO)
13294  */
13295 /*@{*/
13296 /*! @brief Read current value of the LTC_VID1_IP_ID field. */
13297 #define LTC_RD_VID1_IP_ID(base) ((LTC_VID1_REG(base) & LTC_VID1_IP_ID_MASK) >> LTC_VID1_IP_ID_SHIFT)
13298 #define LTC_BRD_VID1_IP_ID(base) (BME_UBFX32(&LTC_VID1_REG(base), LTC_VID1_IP_ID_SHIFT, LTC_VID1_IP_ID_WIDTH))
13299 /*@}*/
13300 
13301 /*******************************************************************************
13302  * LTC_CHAVID - LTC CHA Version ID Register
13303  ******************************************************************************/
13304 
13305 /*!
13306  * @brief LTC_CHAVID - LTC CHA Version ID Register (RO)
13307  *
13308  * Reset value: 0x00000050U
13309  *
13310  * This register contains the Version ID and Revision Number for the CHAs
13311  * contained within LTC.
13312  */
13313 /*!
13314  * @name Constants and macros for entire LTC_CHAVID register
13315  */
13316 /*@{*/
13317 #define LTC_RD_CHAVID(base)      (LTC_CHAVID_REG(base))
13318 /*@}*/
13319 
13320 /*
13321  * Constants & macros for individual LTC_CHAVID bitfields
13322  */
13323 
13324 /*!
13325  * @name Register LTC_CHAVID, field AESREV[3:0] (RO)
13326  *
13327  * AES Revision Number(0x0).
13328  */
13329 /*@{*/
13330 /*! @brief Read current value of the LTC_CHAVID_AESREV field. */
13331 #define LTC_RD_CHAVID_AESREV(base) ((LTC_CHAVID_REG(base) & LTC_CHAVID_AESREV_MASK) >> LTC_CHAVID_AESREV_SHIFT)
13332 #define LTC_BRD_CHAVID_AESREV(base) (BME_UBFX32(&LTC_CHAVID_REG(base), LTC_CHAVID_AESREV_SHIFT, LTC_CHAVID_AESREV_WIDTH))
13333 /*@}*/
13334 
13335 /*!
13336  * @name Register LTC_CHAVID, field AESVID[7:4] (RO)
13337  *
13338  * AES Version ID(0x5).
13339  */
13340 /*@{*/
13341 /*! @brief Read current value of the LTC_CHAVID_AESVID field. */
13342 #define LTC_RD_CHAVID_AESVID(base) ((LTC_CHAVID_REG(base) & LTC_CHAVID_AESVID_MASK) >> LTC_CHAVID_AESVID_SHIFT)
13343 #define LTC_BRD_CHAVID_AESVID(base) (BME_UBFX32(&LTC_CHAVID_REG(base), LTC_CHAVID_AESVID_SHIFT, LTC_CHAVID_AESVID_WIDTH))
13344 /*@}*/
13345 
13346 /*
13347  * MKW40Z4 MCG
13348  *
13349  * Multipurpose Clock Generator module
13350  *
13351  * Registers defined in this header file:
13352  * - MCG_C1 - MCG Control 1 Register
13353  * - MCG_C2 - MCG Control 2 Register
13354  * - MCG_C3 - MCG Control 3 Register
13355  * - MCG_C4 - MCG Control 4 Register
13356  * - MCG_C5 - MCG Control 5 Register
13357  * - MCG_C6 - MCG Control 6 Register
13358  * - MCG_S - MCG Status Register
13359  * - MCG_SC - MCG Status and Control Register
13360  * - MCG_ATCVH - MCG Auto Trim Compare Value High Register
13361  * - MCG_ATCVL - MCG Auto Trim Compare Value Low Register
13362  * - MCG_C7 - MCG Control 7 Register
13363  * - MCG_C8 - MCG Control 8 Register
13364  */
13365 
13366 #define MCG_INSTANCE_COUNT (1U) /*!< Number of instances of the MCG module. */
13367 #define MCG_IDX (0U) /*!< Instance number for MCG. */
13368 
13369 /*******************************************************************************
13370  * MCG_C1 - MCG Control 1 Register
13371  ******************************************************************************/
13372 
13373 /*!
13374  * @brief MCG_C1 - MCG Control 1 Register (RW)
13375  *
13376  * Reset value: 0x04U
13377  */
13378 /*!
13379  * @name Constants and macros for entire MCG_C1 register
13380  */
13381 /*@{*/
13382 #define MCG_RD_C1(base)          (MCG_C1_REG(base))
13383 #define MCG_WR_C1(base, value)   (MCG_C1_REG(base) = (value))
13384 #define MCG_RMW_C1(base, mask, value) (MCG_WR_C1(base, (MCG_RD_C1(base) & ~(mask)) | (value)))
13385 #define MCG_SET_C1(base, value)  (BME_OR8(&MCG_C1_REG(base), (uint8_t)(value)))
13386 #define MCG_CLR_C1(base, value)  (BME_AND8(&MCG_C1_REG(base), (uint8_t)(~(value))))
13387 #define MCG_TOG_C1(base, value)  (BME_XOR8(&MCG_C1_REG(base), (uint8_t)(value)))
13388 /*@}*/
13389 
13390 /*
13391  * Constants & macros for individual MCG_C1 bitfields
13392  */
13393 
13394 /*!
13395  * @name Register MCG_C1, field IREFSTEN[0] (RW)
13396  *
13397  * Controls whether or not the internal reference clock remains enabled when the
13398  * MCG enters Stop mode.
13399  *
13400  * Values:
13401  * - 0b0 - Internal reference clock is disabled in Stop mode.
13402  * - 0b1 - Internal reference clock is enabled in Stop mode if IRCLKEN is set or
13403  *     if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
13404  */
13405 /*@{*/
13406 /*! @brief Read current value of the MCG_C1_IREFSTEN field. */
13407 #define MCG_RD_C1_IREFSTEN(base) ((MCG_C1_REG(base) & MCG_C1_IREFSTEN_MASK) >> MCG_C1_IREFSTEN_SHIFT)
13408 #define MCG_BRD_C1_IREFSTEN(base) (BME_UBFX8(&MCG_C1_REG(base), MCG_C1_IREFSTEN_SHIFT, MCG_C1_IREFSTEN_WIDTH))
13409 
13410 /*! @brief Set the IREFSTEN field to a new value. */
13411 #define MCG_WR_C1_IREFSTEN(base, value) (MCG_RMW_C1(base, MCG_C1_IREFSTEN_MASK, MCG_C1_IREFSTEN(value)))
13412 #define MCG_BWR_C1_IREFSTEN(base, value) (BME_BFI8(&MCG_C1_REG(base), ((uint8_t)(value) << MCG_C1_IREFSTEN_SHIFT), MCG_C1_IREFSTEN_SHIFT, MCG_C1_IREFSTEN_WIDTH))
13413 /*@}*/
13414 
13415 /*!
13416  * @name Register MCG_C1, field IRCLKEN[1] (RW)
13417  *
13418  * Enables the internal reference clock for use as MCGIRCLK.
13419  *
13420  * Values:
13421  * - 0b0 - MCGIRCLK inactive.
13422  * - 0b1 - MCGIRCLK active.
13423  */
13424 /*@{*/
13425 /*! @brief Read current value of the MCG_C1_IRCLKEN field. */
13426 #define MCG_RD_C1_IRCLKEN(base) ((MCG_C1_REG(base) & MCG_C1_IRCLKEN_MASK) >> MCG_C1_IRCLKEN_SHIFT)
13427 #define MCG_BRD_C1_IRCLKEN(base) (BME_UBFX8(&MCG_C1_REG(base), MCG_C1_IRCLKEN_SHIFT, MCG_C1_IRCLKEN_WIDTH))
13428 
13429 /*! @brief Set the IRCLKEN field to a new value. */
13430 #define MCG_WR_C1_IRCLKEN(base, value) (MCG_RMW_C1(base, MCG_C1_IRCLKEN_MASK, MCG_C1_IRCLKEN(value)))
13431 #define MCG_BWR_C1_IRCLKEN(base, value) (BME_BFI8(&MCG_C1_REG(base), ((uint8_t)(value) << MCG_C1_IRCLKEN_SHIFT), MCG_C1_IRCLKEN_SHIFT, MCG_C1_IRCLKEN_WIDTH))
13432 /*@}*/
13433 
13434 /*!
13435  * @name Register MCG_C1, field IREFS[2] (RW)
13436  *
13437  * Selects the reference clock source for the FLL. IREFS also controls the MCG
13438  * clock mode configuration. See "MCG Modes of Operation" table and "MCG Mode
13439  * Switching" for further details regarding MCG clock mode selection and MCG mode
13440  * switching.
13441  *
13442  * Values:
13443  * - 0b0 - External reference clock is selected.
13444  * - 0b1 - The slow internal reference clock is selected.
13445  */
13446 /*@{*/
13447 /*! @brief Read current value of the MCG_C1_IREFS field. */
13448 #define MCG_RD_C1_IREFS(base) ((MCG_C1_REG(base) & MCG_C1_IREFS_MASK) >> MCG_C1_IREFS_SHIFT)
13449 #define MCG_BRD_C1_IREFS(base) (BME_UBFX8(&MCG_C1_REG(base), MCG_C1_IREFS_SHIFT, MCG_C1_IREFS_WIDTH))
13450 
13451 /*! @brief Set the IREFS field to a new value. */
13452 #define MCG_WR_C1_IREFS(base, value) (MCG_RMW_C1(base, MCG_C1_IREFS_MASK, MCG_C1_IREFS(value)))
13453 #define MCG_BWR_C1_IREFS(base, value) (BME_BFI8(&MCG_C1_REG(base), ((uint8_t)(value) << MCG_C1_IREFS_SHIFT), MCG_C1_IREFS_SHIFT, MCG_C1_IREFS_WIDTH))
13454 /*@}*/
13455 
13456 /*!
13457  * @name Register MCG_C1, field FRDIV[5:3] (RW)
13458  *
13459  * Selects the amount to divide down the external reference clock for the FLL.
13460  * The resulting frequency must be in the range 31.25 kHz to 39.0625 kHz (This is
13461  * required when FLL/DCO is the clock source for MCGOUTCLK "mcg_out_clk". In FBE
13462  * mode, it is not required to meet this range, but it is recommended in the
13463  * cases when trying to enter a FLL mode from FBE).
13464  *
13465  * Values:
13466  * - 0b000 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE
13467  *     values, Divide Factor is 32.
13468  * - 0b001 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE
13469  *     values, Divide Factor is 64.
13470  * - 0b010 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE
13471  *     values, Divide Factor is 128.
13472  * - 0b011 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE
13473  *     values, Divide Factor is 256.
13474  * - 0b100 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE
13475  *     values, Divide Factor is 512.
13476  * - 0b101 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE
13477  *     values, Divide Factor is 1024.
13478  * - 0b110 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE
13479  *     values, Divide Factor is 1280 .
13480  * - 0b111 - If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other
13481  *     RANGE values, Divide Factor is 1536 .
13482  */
13483 /*@{*/
13484 /*! @brief Read current value of the MCG_C1_FRDIV field. */
13485 #define MCG_RD_C1_FRDIV(base) ((MCG_C1_REG(base) & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)
13486 #define MCG_BRD_C1_FRDIV(base) (BME_UBFX8(&MCG_C1_REG(base), MCG_C1_FRDIV_SHIFT, MCG_C1_FRDIV_WIDTH))
13487 
13488 /*! @brief Set the FRDIV field to a new value. */
13489 #define MCG_WR_C1_FRDIV(base, value) (MCG_RMW_C1(base, MCG_C1_FRDIV_MASK, MCG_C1_FRDIV(value)))
13490 #define MCG_BWR_C1_FRDIV(base, value) (BME_BFI8(&MCG_C1_REG(base), ((uint8_t)(value) << MCG_C1_FRDIV_SHIFT), MCG_C1_FRDIV_SHIFT, MCG_C1_FRDIV_WIDTH))
13491 /*@}*/
13492 
13493 /*!
13494  * @name Register MCG_C1, field CLKS[7:6] (RW)
13495  *
13496  * Selects the clock source for MCGOUTCLK "mcg_out_clk". For more details
13497  * regarding MCG clock source selection and MCG mode switching, see "MCG Modes of
13498  * Operation" table and "MCG Mode Switching"
13499  *
13500  * Values:
13501  * - 0b00 - Encoding 0 - Output of FLL is selected.
13502  * - 0b01 - Encoding 1 - Internal reference clock is selected.
13503  * - 0b10 - Encoding 2 - External reference clock is selected.
13504  * - 0b11 - Encoding 3 - Reserved.
13505  */
13506 /*@{*/
13507 /*! @brief Read current value of the MCG_C1_CLKS field. */
13508 #define MCG_RD_C1_CLKS(base) ((MCG_C1_REG(base) & MCG_C1_CLKS_MASK) >> MCG_C1_CLKS_SHIFT)
13509 #define MCG_BRD_C1_CLKS(base) (BME_UBFX8(&MCG_C1_REG(base), MCG_C1_CLKS_SHIFT, MCG_C1_CLKS_WIDTH))
13510 
13511 /*! @brief Set the CLKS field to a new value. */
13512 #define MCG_WR_C1_CLKS(base, value) (MCG_RMW_C1(base, MCG_C1_CLKS_MASK, MCG_C1_CLKS(value)))
13513 #define MCG_BWR_C1_CLKS(base, value) (BME_BFI8(&MCG_C1_REG(base), ((uint8_t)(value) << MCG_C1_CLKS_SHIFT), MCG_C1_CLKS_SHIFT, MCG_C1_CLKS_WIDTH))
13514 /*@}*/
13515 
13516 /*******************************************************************************
13517  * MCG_C2 - MCG Control 2 Register
13518  ******************************************************************************/
13519 
13520 /*!
13521  * @brief MCG_C2 - MCG Control 2 Register (RW)
13522  *
13523  * Reset value: 0xC0U
13524  */
13525 /*!
13526  * @name Constants and macros for entire MCG_C2 register
13527  */
13528 /*@{*/
13529 #define MCG_RD_C2(base)          (MCG_C2_REG(base))
13530 #define MCG_WR_C2(base, value)   (MCG_C2_REG(base) = (value))
13531 #define MCG_RMW_C2(base, mask, value) (MCG_WR_C2(base, (MCG_RD_C2(base) & ~(mask)) | (value)))
13532 #define MCG_SET_C2(base, value)  (BME_OR8(&MCG_C2_REG(base), (uint8_t)(value)))
13533 #define MCG_CLR_C2(base, value)  (BME_AND8(&MCG_C2_REG(base), (uint8_t)(~(value))))
13534 #define MCG_TOG_C2(base, value)  (BME_XOR8(&MCG_C2_REG(base), (uint8_t)(value)))
13535 /*@}*/
13536 
13537 /*
13538  * Constants & macros for individual MCG_C2 bitfields
13539  */
13540 
13541 /*!
13542  * @name Register MCG_C2, field IRCS[0] (RW)
13543  *
13544  * Selects between the fast or slow internal reference clock source.
13545  *
13546  * Values:
13547  * - 0b0 - Slow internal reference clock selected. (32 kHz Internal Reference
13548  *     Clock (32 kHz IRC)).
13549  * - 0b1 - Fast internal reference clock selected. (4 MHz Internal Reference
13550  *     Clock (4 MHz IRC)).
13551  */
13552 /*@{*/
13553 /*! @brief Read current value of the MCG_C2_IRCS field. */
13554 #define MCG_RD_C2_IRCS(base) ((MCG_C2_REG(base) & MCG_C2_IRCS_MASK) >> MCG_C2_IRCS_SHIFT)
13555 #define MCG_BRD_C2_IRCS(base) (BME_UBFX8(&MCG_C2_REG(base), MCG_C2_IRCS_SHIFT, MCG_C2_IRCS_WIDTH))
13556 
13557 /*! @brief Set the IRCS field to a new value. */
13558 #define MCG_WR_C2_IRCS(base, value) (MCG_RMW_C2(base, MCG_C2_IRCS_MASK, MCG_C2_IRCS(value)))
13559 #define MCG_BWR_C2_IRCS(base, value) (BME_BFI8(&MCG_C2_REG(base), ((uint8_t)(value) << MCG_C2_IRCS_SHIFT), MCG_C2_IRCS_SHIFT, MCG_C2_IRCS_WIDTH))
13560 /*@}*/
13561 
13562 /*!
13563  * @name Register MCG_C2, field LP[1] (RW)
13564  *
13565  * Controls whether the FLL is disabled in BLPI and BLPE modes. In FBE mode,
13566  * setting this bit to 1 will transition the MCG into BLPE mode; in FBI mode,
13567  * setting this bit to 1 will transition the MCG into BLPI mode. In any other MCG mode,
13568  * LP bit has no affect.
13569  *
13570  * Values:
13571  * - 0b0 - FLL is not disabled in bypass modes.
13572  * - 0b1 - FLL is disabled in bypass modes (lower power)
13573  */
13574 /*@{*/
13575 /*! @brief Read current value of the MCG_C2_LP field. */
13576 #define MCG_RD_C2_LP(base)   ((MCG_C2_REG(base) & MCG_C2_LP_MASK) >> MCG_C2_LP_SHIFT)
13577 #define MCG_BRD_C2_LP(base)  (BME_UBFX8(&MCG_C2_REG(base), MCG_C2_LP_SHIFT, MCG_C2_LP_WIDTH))
13578 
13579 /*! @brief Set the LP field to a new value. */
13580 #define MCG_WR_C2_LP(base, value) (MCG_RMW_C2(base, MCG_C2_LP_MASK, MCG_C2_LP(value)))
13581 #define MCG_BWR_C2_LP(base, value) (BME_BFI8(&MCG_C2_REG(base), ((uint8_t)(value) << MCG_C2_LP_SHIFT), MCG_C2_LP_SHIFT, MCG_C2_LP_WIDTH))
13582 /*@}*/
13583 
13584 /*!
13585  * @name Register MCG_C2, field EREFS[2] (RW)
13586  *
13587  * Selects the source for the external reference clock. See the Oscillator (OSC)
13588  * chapter for more details.
13589  *
13590  * Values:
13591  * - 0b0 - External reference clock requested.
13592  * - 0b1 - Oscillator requested.
13593  */
13594 /*@{*/
13595 /*! @brief Read current value of the MCG_C2_EREFS field. */
13596 #define MCG_RD_C2_EREFS(base) ((MCG_C2_REG(base) & MCG_C2_EREFS_MASK) >> MCG_C2_EREFS_SHIFT)
13597 #define MCG_BRD_C2_EREFS(base) (BME_UBFX8(&MCG_C2_REG(base), MCG_C2_EREFS_SHIFT, MCG_C2_EREFS_WIDTH))
13598 
13599 /*! @brief Set the EREFS field to a new value. */
13600 #define MCG_WR_C2_EREFS(base, value) (MCG_RMW_C2(base, MCG_C2_EREFS_MASK, MCG_C2_EREFS(value)))
13601 #define MCG_BWR_C2_EREFS(base, value) (BME_BFI8(&MCG_C2_REG(base), ((uint8_t)(value) << MCG_C2_EREFS_SHIFT), MCG_C2_EREFS_SHIFT, MCG_C2_EREFS_WIDTH))
13602 /*@}*/
13603 
13604 /*!
13605  * @name Register MCG_C2, field HGO[3] (RW)
13606  *
13607  * Controls the crystal oscillator mode of operation. See the Oscillator (OSC)
13608  * chapter for more details.
13609  *
13610  * Values:
13611  * - 0b0 - Configure crystal oscillator for low-power operation.
13612  * - 0b1 - Configure crystal oscillator for high-gain operation.
13613  */
13614 /*@{*/
13615 /*! @brief Read current value of the MCG_C2_HGO field. */
13616 #define MCG_RD_C2_HGO(base)  ((MCG_C2_REG(base) & MCG_C2_HGO_MASK) >> MCG_C2_HGO_SHIFT)
13617 #define MCG_BRD_C2_HGO(base) (BME_UBFX8(&MCG_C2_REG(base), MCG_C2_HGO_SHIFT, MCG_C2_HGO_WIDTH))
13618 
13619 /*! @brief Set the HGO field to a new value. */
13620 #define MCG_WR_C2_HGO(base, value) (MCG_RMW_C2(base, MCG_C2_HGO_MASK, MCG_C2_HGO(value)))
13621 #define MCG_BWR_C2_HGO(base, value) (BME_BFI8(&MCG_C2_REG(base), ((uint8_t)(value) << MCG_C2_HGO_SHIFT), MCG_C2_HGO_SHIFT, MCG_C2_HGO_WIDTH))
13622 /*@}*/
13623 
13624 /*!
13625  * @name Register MCG_C2, field RANGE[5:4] (RW)
13626  *
13627  * Selects the frequency range for the crystal oscillator or external clock
13628  * source. See the Oscillator (OSC) chapter for more details and the device data
13629  * sheet for the frequency ranges used.
13630  *
13631  * Values:
13632  * - 0b00 - Encoding 0 - Low frequency range selected for the crystal oscillator
13633  *     .
13634  * - 0b01 - Encoding 1 - High frequency range selected for the crystal
13635  *     oscillator .
13636  */
13637 /*@{*/
13638 /*! @brief Read current value of the MCG_C2_RANGE field. */
13639 #define MCG_RD_C2_RANGE(base) ((MCG_C2_REG(base) & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
13640 #define MCG_BRD_C2_RANGE(base) (BME_UBFX8(&MCG_C2_REG(base), MCG_C2_RANGE_SHIFT, MCG_C2_RANGE_WIDTH))
13641 
13642 /*! @brief Set the RANGE field to a new value. */
13643 #define MCG_WR_C2_RANGE(base, value) (MCG_RMW_C2(base, MCG_C2_RANGE_MASK, MCG_C2_RANGE(value)))
13644 #define MCG_BWR_C2_RANGE(base, value) (BME_BFI8(&MCG_C2_REG(base), ((uint8_t)(value) << MCG_C2_RANGE_SHIFT), MCG_C2_RANGE_SHIFT, MCG_C2_RANGE_WIDTH))
13645 /*@}*/
13646 
13647 /*!
13648  * @name Register MCG_C2, field FCFTRIM[6] (RW)
13649  *
13650  * FCFTRIM controls the smallest adjustment of the fast internal reference clock
13651  * frequency. Setting FCFTRIM increases the period and clearing FCFTRIM
13652  * decreases the period by the smallest amount possible. If an FCFTRIM value stored in
13653  * nonvolatile memory is to be used, it is your responsibility to copy that value
13654  * from the nonvolatile memory location to this bit.
13655  */
13656 /*@{*/
13657 /*! @brief Read current value of the MCG_C2_FCFTRIM field. */
13658 #define MCG_RD_C2_FCFTRIM(base) ((MCG_C2_REG(base) & MCG_C2_FCFTRIM_MASK) >> MCG_C2_FCFTRIM_SHIFT)
13659 #define MCG_BRD_C2_FCFTRIM(base) (BME_UBFX8(&MCG_C2_REG(base), MCG_C2_FCFTRIM_SHIFT, MCG_C2_FCFTRIM_WIDTH))
13660 
13661 /*! @brief Set the FCFTRIM field to a new value. */
13662 #define MCG_WR_C2_FCFTRIM(base, value) (MCG_RMW_C2(base, MCG_C2_FCFTRIM_MASK, MCG_C2_FCFTRIM(value)))
13663 #define MCG_BWR_C2_FCFTRIM(base, value) (BME_BFI8(&MCG_C2_REG(base), ((uint8_t)(value) << MCG_C2_FCFTRIM_SHIFT), MCG_C2_FCFTRIM_SHIFT, MCG_C2_FCFTRIM_WIDTH))
13664 /*@}*/
13665 
13666 /*!
13667  * @name Register MCG_C2, field LOCRE0[7] (RW)
13668  *
13669  * Determines whether an interrupt or a reset request is made following a loss
13670  * of OSC0 external reference clock. The LOCRE0 only has an affect when CME0 is
13671  * set.
13672  *
13673  * Values:
13674  * - 0b0 - Interrupt request is generated on a loss of OSC0 external reference
13675  *     clock.
13676  * - 0b1 - Generate a reset request on a loss of OSC0 external reference clock.
13677  */
13678 /*@{*/
13679 /*! @brief Read current value of the MCG_C2_LOCRE0 field. */
13680 #define MCG_RD_C2_LOCRE0(base) ((MCG_C2_REG(base) & MCG_C2_LOCRE0_MASK) >> MCG_C2_LOCRE0_SHIFT)
13681 #define MCG_BRD_C2_LOCRE0(base) (BME_UBFX8(&MCG_C2_REG(base), MCG_C2_LOCRE0_SHIFT, MCG_C2_LOCRE0_WIDTH))
13682 
13683 /*! @brief Set the LOCRE0 field to a new value. */
13684 #define MCG_WR_C2_LOCRE0(base, value) (MCG_RMW_C2(base, MCG_C2_LOCRE0_MASK, MCG_C2_LOCRE0(value)))
13685 #define MCG_BWR_C2_LOCRE0(base, value) (BME_BFI8(&MCG_C2_REG(base), ((uint8_t)(value) << MCG_C2_LOCRE0_SHIFT), MCG_C2_LOCRE0_SHIFT, MCG_C2_LOCRE0_WIDTH))
13686 /*@}*/
13687 
13688 /*******************************************************************************
13689  * MCG_C3 - MCG Control 3 Register
13690  ******************************************************************************/
13691 
13692 /*!
13693  * @brief MCG_C3 - MCG Control 3 Register (RW)
13694  *
13695  * Reset value: 0x00U
13696  */
13697 /*!
13698  * @name Constants and macros for entire MCG_C3 register
13699  */
13700 /*@{*/
13701 #define MCG_RD_C3(base)          (MCG_C3_REG(base))
13702 #define MCG_WR_C3(base, value)   (MCG_C3_REG(base) = (value))
13703 #define MCG_RMW_C3(base, mask, value) (MCG_WR_C3(base, (MCG_RD_C3(base) & ~(mask)) | (value)))
13704 #define MCG_SET_C3(base, value)  (BME_OR8(&MCG_C3_REG(base), (uint8_t)(value)))
13705 #define MCG_CLR_C3(base, value)  (BME_AND8(&MCG_C3_REG(base), (uint8_t)(~(value))))
13706 #define MCG_TOG_C3(base, value)  (BME_XOR8(&MCG_C3_REG(base), (uint8_t)(value)))
13707 /*@}*/
13708 
13709 /*******************************************************************************
13710  * MCG_C4 - MCG Control 4 Register
13711  ******************************************************************************/
13712 
13713 /*!
13714  * @brief MCG_C4 - MCG Control 4 Register (RW)
13715  *
13716  * Reset value: 0x00U
13717  *
13718  * Reset values for DRST and DMX32 bits are 0.
13719  */
13720 /*!
13721  * @name Constants and macros for entire MCG_C4 register
13722  */
13723 /*@{*/
13724 #define MCG_RD_C4(base)          (MCG_C4_REG(base))
13725 #define MCG_WR_C4(base, value)   (MCG_C4_REG(base) = (value))
13726 #define MCG_RMW_C4(base, mask, value) (MCG_WR_C4(base, (MCG_RD_C4(base) & ~(mask)) | (value)))
13727 #define MCG_SET_C4(base, value)  (BME_OR8(&MCG_C4_REG(base), (uint8_t)(value)))
13728 #define MCG_CLR_C4(base, value)  (BME_AND8(&MCG_C4_REG(base), (uint8_t)(~(value))))
13729 #define MCG_TOG_C4(base, value)  (BME_XOR8(&MCG_C4_REG(base), (uint8_t)(value)))
13730 /*@}*/
13731 
13732 /*
13733  * Constants & macros for individual MCG_C4 bitfields
13734  */
13735 
13736 /*!
13737  * @name Register MCG_C4, field SCFTRIM[0] (RW)
13738  *
13739  * SCFTRIM A value for SCFTRIM is loaded during reset from a factory programmed
13740  * location . Initially out of reset, SCFTRIM gets reset to 0x0, bus soon after
13741  * reset, the IFR load enable gets asserted causing SCFTRIM value to get replaced
13742  * with the IFR (SCFTRIM=IFR[0]) value. controls the smallest adjustment of the
13743  * slow internal reference clock frequency. Setting SCFTRIM increases the period
13744  * and clearing SCFTRIM decreases the period by the smallest amount possible. If
13745  * an SCFTRIM value stored in nonvolatile memory is to be used, it is your
13746  * responsibility to copy that value from the nonvolatile memory location to this bit.
13747  */
13748 /*@{*/
13749 /*! @brief Read current value of the MCG_C4_SCFTRIM field. */
13750 #define MCG_RD_C4_SCFTRIM(base) ((MCG_C4_REG(base) & MCG_C4_SCFTRIM_MASK) >> MCG_C4_SCFTRIM_SHIFT)
13751 #define MCG_BRD_C4_SCFTRIM(base) (BME_UBFX8(&MCG_C4_REG(base), MCG_C4_SCFTRIM_SHIFT, MCG_C4_SCFTRIM_WIDTH))
13752 
13753 /*! @brief Set the SCFTRIM field to a new value. */
13754 #define MCG_WR_C4_SCFTRIM(base, value) (MCG_RMW_C4(base, MCG_C4_SCFTRIM_MASK, MCG_C4_SCFTRIM(value)))
13755 #define MCG_BWR_C4_SCFTRIM(base, value) (BME_BFI8(&MCG_C4_REG(base), ((uint8_t)(value) << MCG_C4_SCFTRIM_SHIFT), MCG_C4_SCFTRIM_SHIFT, MCG_C4_SCFTRIM_WIDTH))
13756 /*@}*/
13757 
13758 /*!
13759  * @name Register MCG_C4, field FCTRIM[4:1] (RW)
13760  *
13761  * FCTRIM A value for FCTRIM is loaded during reset from a factory programmed
13762  * location. Initially out of reset, FCTRIM gets reset to 0x8, bus soon after
13763  * reset, the IFR load enable gets asserted causing FCTRIM value to get replaced with
13764  * the IFR (FCTRIM=IFR[12:9]) value. controls the fast internal reference clock
13765  * frequency by controlling the fast internal reference clock period. The FCTRIM
13766  * bits are binary weighted, that is, bit 1 adjusts twice as much as bit 0.
13767  * Increasing the binary value increases the period, and decreasing the value decreases
13768  * the period. If an FCTRIM[3:0] value stored in nonvolatile memory is to be
13769  * used, it is your responsibility to copy that value from the nonvolatile memory
13770  * location to this register.
13771  */
13772 /*@{*/
13773 /*! @brief Read current value of the MCG_C4_FCTRIM field. */
13774 #define MCG_RD_C4_FCTRIM(base) ((MCG_C4_REG(base) & MCG_C4_FCTRIM_MASK) >> MCG_C4_FCTRIM_SHIFT)
13775 #define MCG_BRD_C4_FCTRIM(base) (BME_UBFX8(&MCG_C4_REG(base), MCG_C4_FCTRIM_SHIFT, MCG_C4_FCTRIM_WIDTH))
13776 
13777 /*! @brief Set the FCTRIM field to a new value. */
13778 #define MCG_WR_C4_FCTRIM(base, value) (MCG_RMW_C4(base, MCG_C4_FCTRIM_MASK, MCG_C4_FCTRIM(value)))
13779 #define MCG_BWR_C4_FCTRIM(base, value) (BME_BFI8(&MCG_C4_REG(base), ((uint8_t)(value) << MCG_C4_FCTRIM_SHIFT), MCG_C4_FCTRIM_SHIFT, MCG_C4_FCTRIM_WIDTH))
13780 /*@}*/
13781 
13782 /*!
13783  * @name Register MCG_C4, field DRST_DRS[6:5] (RW)
13784  *
13785  * The DRS bits select the frequency range for the FLL output, DCOOUT. When the
13786  * LP bit is set, writes to the DRS bits are ignored. The DRST read field
13787  * indicates the current frequency range for DCOOUT. The DRST field does not update
13788  * immediately after a write to the DRS field due to internal synchronization between
13789  * clock domains. See the DCO Frequency Range table for more details.
13790  *
13791  * Values:
13792  * - 0b00 - Encoding 0 - Low range (reset default).
13793  * - 0b01 - Encoding 1 - Mid range.
13794  * - 0b10 - Encoding 2 - Mid-high range.
13795  * - 0b11 - Encoding 3 - High range.
13796  */
13797 /*@{*/
13798 /*! @brief Read current value of the MCG_C4_DRST_DRS field. */
13799 #define MCG_RD_C4_DRST_DRS(base) ((MCG_C4_REG(base) & MCG_C4_DRST_DRS_MASK) >> MCG_C4_DRST_DRS_SHIFT)
13800 #define MCG_BRD_C4_DRST_DRS(base) (BME_UBFX8(&MCG_C4_REG(base), MCG_C4_DRST_DRS_SHIFT, MCG_C4_DRST_DRS_WIDTH))
13801 
13802 /*! @brief Set the DRST_DRS field to a new value. */
13803 #define MCG_WR_C4_DRST_DRS(base, value) (MCG_RMW_C4(base, MCG_C4_DRST_DRS_MASK, MCG_C4_DRST_DRS(value)))
13804 #define MCG_BWR_C4_DRST_DRS(base, value) (BME_BFI8(&MCG_C4_REG(base), ((uint8_t)(value) << MCG_C4_DRST_DRS_SHIFT), MCG_C4_DRST_DRS_SHIFT, MCG_C4_DRST_DRS_WIDTH))
13805 /*@}*/
13806 
13807 /*!
13808  * @name Register MCG_C4, field DMX32[7] (RW)
13809  *
13810  * The DMX32 bit controls whether the DCO frequency range is narrowed to its
13811  * maximum frequency with a 32.768 kHz reference. The following table identifies
13812  * settings for the DCO frequency range. The system clocks derived from this source
13813  * should not exceed their specified maximums. DRST_DRS DMX32 Reference Range FLL
13814  * Factor DCO Range 00 0 31.25-39.0625 kHz 640 20-25 MHz 1 32.768 kHz 732 24 MHz
13815  * 01 0 31.25-39.0625 kHz 1280 40-50 MHz 1 32.768 kHz 1464 48 MHz 10 0
13816  * 31.25-39.0625 kHz 1920 60-75 MHz 1 32.768 kHz 2197 72 MHz 11 0 31.25-39.0625 kHz 2560
13817  * 80-100 MHz 1 32.768 kHz 2929 96 MHz
13818  *
13819  * Values:
13820  * - 0b0 - DCO has a default range of 25%.
13821  * - 0b1 - DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
13822  */
13823 /*@{*/
13824 /*! @brief Read current value of the MCG_C4_DMX32 field. */
13825 #define MCG_RD_C4_DMX32(base) ((MCG_C4_REG(base) & MCG_C4_DMX32_MASK) >> MCG_C4_DMX32_SHIFT)
13826 #define MCG_BRD_C4_DMX32(base) (BME_UBFX8(&MCG_C4_REG(base), MCG_C4_DMX32_SHIFT, MCG_C4_DMX32_WIDTH))
13827 
13828 /*! @brief Set the DMX32 field to a new value. */
13829 #define MCG_WR_C4_DMX32(base, value) (MCG_RMW_C4(base, MCG_C4_DMX32_MASK, MCG_C4_DMX32(value)))
13830 #define MCG_BWR_C4_DMX32(base, value) (BME_BFI8(&MCG_C4_REG(base), ((uint8_t)(value) << MCG_C4_DMX32_SHIFT), MCG_C4_DMX32_SHIFT, MCG_C4_DMX32_WIDTH))
13831 /*@}*/
13832 
13833 /*******************************************************************************
13834  * MCG_C5 - MCG Control 5 Register
13835  ******************************************************************************/
13836 
13837 /*!
13838  * @brief MCG_C5 - MCG Control 5 Register (ROZ)
13839  *
13840  * Reset value: 0x00U
13841  */
13842 /*!
13843  * @name Constants and macros for entire MCG_C5 register
13844  */
13845 /*@{*/
13846 #define MCG_RD_C5(base)          (MCG_C5_REG(base))
13847 /*@}*/
13848 
13849 /*******************************************************************************
13850  * MCG_C6 - MCG Control 6 Register
13851  ******************************************************************************/
13852 
13853 /*!
13854  * @brief MCG_C6 - MCG Control 6 Register (RW)
13855  *
13856  * Reset value: 0x00U
13857  */
13858 /*!
13859  * @name Constants and macros for entire MCG_C6 register
13860  */
13861 /*@{*/
13862 #define MCG_RD_C6(base)          (MCG_C6_REG(base))
13863 #define MCG_WR_C6(base, value)   (MCG_C6_REG(base) = (value))
13864 #define MCG_RMW_C6(base, mask, value) (MCG_WR_C6(base, (MCG_RD_C6(base) & ~(mask)) | (value)))
13865 #define MCG_SET_C6(base, value)  (BME_OR8(&MCG_C6_REG(base), (uint8_t)(value)))
13866 #define MCG_CLR_C6(base, value)  (BME_AND8(&MCG_C6_REG(base), (uint8_t)(~(value))))
13867 #define MCG_TOG_C6(base, value)  (BME_XOR8(&MCG_C6_REG(base), (uint8_t)(value)))
13868 /*@}*/
13869 
13870 /*
13871  * Constants & macros for individual MCG_C6 bitfields
13872  */
13873 
13874 /*!
13875  * @name Register MCG_C6, field CME[5] (RW)
13876  *
13877  * Determines if a reset request is made following a loss of external clock
13878  * indication. The CME bit should only be set to a logic 1 when the MCG is in an
13879  * operational mode that uses the external clock (FEE, FBE, or BLPE). Whenever the
13880  * CME bit is set to a logic 1, the value of the RANGE bits in the C2 register
13881  * should not be changed. CME bit should be set to a logic 0 before the MCG enters
13882  * any Stop mode. Otherwise, a reset request may occur when in Stop mode. CME
13883  * should also be set to a logic 0 before entering VLPR or VLPW power modes if the MCG
13884  * is in BLPE mode.
13885  *
13886  * Values:
13887  * - 0b0 - External clock monitor is disabled.
13888  * - 0b1 - Generate a reset request on loss of external clock.
13889  */
13890 /*@{*/
13891 /*! @brief Read current value of the MCG_C6_CME field. */
13892 #define MCG_RD_C6_CME(base)  ((MCG_C6_REG(base) & MCG_C6_CME_MASK) >> MCG_C6_CME_SHIFT)
13893 #define MCG_BRD_C6_CME(base) (BME_UBFX8(&MCG_C6_REG(base), MCG_C6_CME_SHIFT, MCG_C6_CME_WIDTH))
13894 
13895 /*! @brief Set the CME field to a new value. */
13896 #define MCG_WR_C6_CME(base, value) (MCG_RMW_C6(base, MCG_C6_CME_MASK, MCG_C6_CME(value)))
13897 #define MCG_BWR_C6_CME(base, value) (BME_BFI8(&MCG_C6_REG(base), ((uint8_t)(value) << MCG_C6_CME_SHIFT), MCG_C6_CME_SHIFT, MCG_C6_CME_WIDTH))
13898 /*@}*/
13899 
13900 /*******************************************************************************
13901  * MCG_S - MCG Status Register
13902  ******************************************************************************/
13903 
13904 /*!
13905  * @brief MCG_S - MCG Status Register (RO)
13906  *
13907  * Reset value: 0x10U
13908  */
13909 /*!
13910  * @name Constants and macros for entire MCG_S register
13911  */
13912 /*@{*/
13913 #define MCG_RD_S(base)           (MCG_S_REG(base))
13914 /*@}*/
13915 
13916 /*
13917  * Constants & macros for individual MCG_S bitfields
13918  */
13919 
13920 /*!
13921  * @name Register MCG_S, field IRCST[0] (RO)
13922  *
13923  * The IRCST bit indicates the current source for the internal reference clock
13924  * select clock (IRCSCLK). The IRCST bit does not update immediately after a write
13925  * to the IRCS bit due to internal synchronization between clock domains. The
13926  * IRCST bit will only be updated if the internal reference clock is enabled,
13927  * either by the MCG being in a mode that uses the IRC or by setting the C1[IRCLKEN]
13928  * bit .
13929  *
13930  * Values:
13931  * - 0b0 - Source of internal reference clock is the slow clock (32 kHz IRC).
13932  * - 0b1 - Source of internal reference clock is the fast clock (4 MHz IRC).
13933  */
13934 /*@{*/
13935 /*! @brief Read current value of the MCG_S_IRCST field. */
13936 #define MCG_RD_S_IRCST(base) ((MCG_S_REG(base) & MCG_S_IRCST_MASK) >> MCG_S_IRCST_SHIFT)
13937 #define MCG_BRD_S_IRCST(base) (BME_UBFX8(&MCG_S_REG(base), MCG_S_IRCST_SHIFT, MCG_S_IRCST_WIDTH))
13938 /*@}*/
13939 
13940 /*!
13941  * @name Register MCG_S, field OSCINIT0[1] (RO)
13942  *
13943  * This bit, which resets to 0, is set to 1 after the initialization cycles of
13944  * the crystal oscillator clock have completed. After being set, the bit is
13945  * cleared to 0 if the OSC is subsequently disabled. See the OSC module's detailed
13946  * description for more information.
13947  */
13948 /*@{*/
13949 /*! @brief Read current value of the MCG_S_OSCINIT0 field. */
13950 #define MCG_RD_S_OSCINIT0(base) ((MCG_S_REG(base) & MCG_S_OSCINIT0_MASK) >> MCG_S_OSCINIT0_SHIFT)
13951 #define MCG_BRD_S_OSCINIT0(base) (BME_UBFX8(&MCG_S_REG(base), MCG_S_OSCINIT0_SHIFT, MCG_S_OSCINIT0_WIDTH))
13952 /*@}*/
13953 
13954 /*!
13955  * @name Register MCG_S, field CLKST[3:2] (RO)
13956  *
13957  * These bits indicate the current clock mode. The CLKST bits do not update
13958  * immediately after a write to the CLKS bits due to internal synchronization between
13959  * clock domains.
13960  *
13961  * Values:
13962  * - 0b00 - Encoding 0 - Output of the FLL is selected (reset default).
13963  * - 0b01 - Encoding 1 - Internal reference clock is selected.
13964  * - 0b10 - Encoding 2 - External reference clock is selected.
13965  * - 0b11 - Reserved.
13966  */
13967 /*@{*/
13968 /*! @brief Read current value of the MCG_S_CLKST field. */
13969 #define MCG_RD_S_CLKST(base) ((MCG_S_REG(base) & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT)
13970 #define MCG_BRD_S_CLKST(base) (BME_UBFX8(&MCG_S_REG(base), MCG_S_CLKST_SHIFT, MCG_S_CLKST_WIDTH))
13971 /*@}*/
13972 
13973 /*!
13974  * @name Register MCG_S, field IREFST[4] (RO)
13975  *
13976  * This bit indicates the current source for the FLL reference clock. The IREFST
13977  * bit does not update immediately after a write to the IREFS bit due to
13978  * internal synchronization between clock domains.
13979  *
13980  * Values:
13981  * - 0b0 - Source of FLL reference clock is the external reference clock.
13982  * - 0b1 - Source of FLL reference clock is the internal reference clock.
13983  */
13984 /*@{*/
13985 /*! @brief Read current value of the MCG_S_IREFST field. */
13986 #define MCG_RD_S_IREFST(base) ((MCG_S_REG(base) & MCG_S_IREFST_MASK) >> MCG_S_IREFST_SHIFT)
13987 #define MCG_BRD_S_IREFST(base) (BME_UBFX8(&MCG_S_REG(base), MCG_S_IREFST_SHIFT, MCG_S_IREFST_WIDTH))
13988 /*@}*/
13989 
13990 /*******************************************************************************
13991  * MCG_SC - MCG Status and Control Register
13992  ******************************************************************************/
13993 
13994 /*!
13995  * @brief MCG_SC - MCG Status and Control Register (RW)
13996  *
13997  * Reset value: 0x02U
13998  */
13999 /*!
14000  * @name Constants and macros for entire MCG_SC register
14001  */
14002 /*@{*/
14003 #define MCG_RD_SC(base)          (MCG_SC_REG(base))
14004 #define MCG_WR_SC(base, value)   (MCG_SC_REG(base) = (value))
14005 #define MCG_RMW_SC(base, mask, value) (MCG_WR_SC(base, (MCG_RD_SC(base) & ~(mask)) | (value)))
14006 #define MCG_SET_SC(base, value)  (BME_OR8(&MCG_SC_REG(base), (uint8_t)(value)))
14007 #define MCG_CLR_SC(base, value)  (BME_AND8(&MCG_SC_REG(base), (uint8_t)(~(value))))
14008 #define MCG_TOG_SC(base, value)  (BME_XOR8(&MCG_SC_REG(base), (uint8_t)(value)))
14009 /*@}*/
14010 
14011 /*
14012  * Constants & macros for individual MCG_SC bitfields
14013  */
14014 
14015 /*!
14016  * @name Register MCG_SC, field LOCS0[0] (W1C)
14017  *
14018  * The LOCS0 indicates when a loss of OSC0 reference clock has occurred. The
14019  * LOCS0 bit only has an effect when CME0 is set. This bit is cleared by writing a
14020  * logic 1 to it when set.
14021  *
14022  * Values:
14023  * - 0b0 - Loss of OSC0 has not occurred.
14024  * - 0b1 - Loss of OSC0 has occurred.
14025  */
14026 /*@{*/
14027 /*! @brief Read current value of the MCG_SC_LOCS0 field. */
14028 #define MCG_RD_SC_LOCS0(base) ((MCG_SC_REG(base) & MCG_SC_LOCS0_MASK) >> MCG_SC_LOCS0_SHIFT)
14029 #define MCG_BRD_SC_LOCS0(base) (BME_UBFX8(&MCG_SC_REG(base), MCG_SC_LOCS0_SHIFT, MCG_SC_LOCS0_WIDTH))
14030 
14031 /*! @brief Set the LOCS0 field to a new value. */
14032 #define MCG_WR_SC_LOCS0(base, value) (MCG_RMW_SC(base, (MCG_SC_LOCS0_MASK | MCG_SC_ATMF_MASK), MCG_SC_LOCS0(value)))
14033 #define MCG_BWR_SC_LOCS0(base, value) (BME_BFI8(&MCG_SC_REG(base), ((uint8_t)(value) << MCG_SC_LOCS0_SHIFT), MCG_SC_LOCS0_SHIFT, MCG_SC_LOCS0_WIDTH))
14034 /*@}*/
14035 
14036 /*!
14037  * @name Register MCG_SC, field FCRDIV[3:1] (RW)
14038  *
14039  * Selects the amount to divide down the fast internal reference clock. The
14040  * resulting frequency will be in the range 31.25 kHz to 4 MHz (Note: Changing the
14041  * divider when the Fast IRC is enabled is not supported).
14042  *
14043  * Values:
14044  * - 0b000 - Divide Factor is 1
14045  * - 0b001 - Divide Factor is 2.
14046  * - 0b010 - Divide Factor is 4.
14047  * - 0b011 - Divide Factor is 8.
14048  * - 0b100 - Divide Factor is 16
14049  * - 0b101 - Divide Factor is 32
14050  * - 0b110 - Divide Factor is 64
14051  * - 0b111 - Divide Factor is 128.
14052  */
14053 /*@{*/
14054 /*! @brief Read current value of the MCG_SC_FCRDIV field. */
14055 #define MCG_RD_SC_FCRDIV(base) ((MCG_SC_REG(base) & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
14056 #define MCG_BRD_SC_FCRDIV(base) (BME_UBFX8(&MCG_SC_REG(base), MCG_SC_FCRDIV_SHIFT, MCG_SC_FCRDIV_WIDTH))
14057 
14058 /*! @brief Set the FCRDIV field to a new value. */
14059 #define MCG_WR_SC_FCRDIV(base, value) (MCG_RMW_SC(base, (MCG_SC_FCRDIV_MASK | MCG_SC_LOCS0_MASK | MCG_SC_ATMF_MASK), MCG_SC_FCRDIV(value)))
14060 #define MCG_BWR_SC_FCRDIV(base, value) (BME_BFI8(&MCG_SC_REG(base), ((uint8_t)(value) << MCG_SC_FCRDIV_SHIFT), MCG_SC_FCRDIV_SHIFT, MCG_SC_FCRDIV_WIDTH))
14061 /*@}*/
14062 
14063 /*!
14064  * @name Register MCG_SC, field FLTPRSRV[4] (RW)
14065  *
14066  * This bit will prevent the FLL filter values from resetting allowing the FLL
14067  * output frequency to remain the same during clock mode changes where the FLL/DCO
14068  * output is still valid. (Note: This requires that the FLL reference frequency
14069  * to remain the same as what it was prior to the new clock mode switch.
14070  * Otherwise FLL filter and frequency values will change.)
14071  *
14072  * Values:
14073  * - 0b0 - FLL filter and FLL frequency will reset on changes to currect clock
14074  *     mode.
14075  * - 0b1 - Fll filter and FLL frequency retain their previous values during new
14076  *     clock mode change.
14077  */
14078 /*@{*/
14079 /*! @brief Read current value of the MCG_SC_FLTPRSRV field. */
14080 #define MCG_RD_SC_FLTPRSRV(base) ((MCG_SC_REG(base) & MCG_SC_FLTPRSRV_MASK) >> MCG_SC_FLTPRSRV_SHIFT)
14081 #define MCG_BRD_SC_FLTPRSRV(base) (BME_UBFX8(&MCG_SC_REG(base), MCG_SC_FLTPRSRV_SHIFT, MCG_SC_FLTPRSRV_WIDTH))
14082 
14083 /*! @brief Set the FLTPRSRV field to a new value. */
14084 #define MCG_WR_SC_FLTPRSRV(base, value) (MCG_RMW_SC(base, (MCG_SC_FLTPRSRV_MASK | MCG_SC_LOCS0_MASK | MCG_SC_ATMF_MASK), MCG_SC_FLTPRSRV(value)))
14085 #define MCG_BWR_SC_FLTPRSRV(base, value) (BME_BFI8(&MCG_SC_REG(base), ((uint8_t)(value) << MCG_SC_FLTPRSRV_SHIFT), MCG_SC_FLTPRSRV_SHIFT, MCG_SC_FLTPRSRV_WIDTH))
14086 /*@}*/
14087 
14088 /*!
14089  * @name Register MCG_SC, field ATMF[5] (W1C)
14090  *
14091  * Fail flag for the Automatic Trim Machine (ATM). This bit asserts when the
14092  * Automatic Trim Machine is enabled, ATME=1, and a write to the C1, C3, C4, and SC
14093  * registers is detected or the MCG enters into any Stop mode. A write to ATMF
14094  * clears the flag.
14095  *
14096  * Values:
14097  * - 0b0 - Automatic Trim Machine completed normally.
14098  * - 0b1 - Automatic Trim Machine failed.
14099  */
14100 /*@{*/
14101 /*! @brief Read current value of the MCG_SC_ATMF field. */
14102 #define MCG_RD_SC_ATMF(base) ((MCG_SC_REG(base) & MCG_SC_ATMF_MASK) >> MCG_SC_ATMF_SHIFT)
14103 #define MCG_BRD_SC_ATMF(base) (BME_UBFX8(&MCG_SC_REG(base), MCG_SC_ATMF_SHIFT, MCG_SC_ATMF_WIDTH))
14104 
14105 /*! @brief Set the ATMF field to a new value. */
14106 #define MCG_WR_SC_ATMF(base, value) (MCG_RMW_SC(base, (MCG_SC_ATMF_MASK | MCG_SC_LOCS0_MASK), MCG_SC_ATMF(value)))
14107 #define MCG_BWR_SC_ATMF(base, value) (BME_BFI8(&MCG_SC_REG(base), ((uint8_t)(value) << MCG_SC_ATMF_SHIFT), MCG_SC_ATMF_SHIFT, MCG_SC_ATMF_WIDTH))
14108 /*@}*/
14109 
14110 /*!
14111  * @name Register MCG_SC, field ATMS[6] (RW)
14112  *
14113  * Selects the IRCS clock for Auto Trim Test.
14114  *
14115  * Values:
14116  * - 0b0 - 32 kHz Internal Reference Clock selected.
14117  * - 0b1 - 4 MHz Internal Reference Clock selected.
14118  */
14119 /*@{*/
14120 /*! @brief Read current value of the MCG_SC_ATMS field. */
14121 #define MCG_RD_SC_ATMS(base) ((MCG_SC_REG(base) & MCG_SC_ATMS_MASK) >> MCG_SC_ATMS_SHIFT)
14122 #define MCG_BRD_SC_ATMS(base) (BME_UBFX8(&MCG_SC_REG(base), MCG_SC_ATMS_SHIFT, MCG_SC_ATMS_WIDTH))
14123 
14124 /*! @brief Set the ATMS field to a new value. */
14125 #define MCG_WR_SC_ATMS(base, value) (MCG_RMW_SC(base, (MCG_SC_ATMS_MASK | MCG_SC_LOCS0_MASK | MCG_SC_ATMF_MASK), MCG_SC_ATMS(value)))
14126 #define MCG_BWR_SC_ATMS(base, value) (BME_BFI8(&MCG_SC_REG(base), ((uint8_t)(value) << MCG_SC_ATMS_SHIFT), MCG_SC_ATMS_SHIFT, MCG_SC_ATMS_WIDTH))
14127 /*@}*/
14128 
14129 /*!
14130  * @name Register MCG_SC, field ATME[7] (RW)
14131  *
14132  * Enables the Auto Trim Machine to start automatically trimming the selected
14133  * Internal Reference Clock. ATME deasserts after the Auto Trim Machine has
14134  * completed trimming all trim bits of the IRCS clock selected by the ATMS bit. Writing
14135  * to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim
14136  * operation and clears this bit.
14137  *
14138  * Values:
14139  * - 0b0 - Auto Trim Machine disabled.
14140  * - 0b1 - Auto Trim Machine enabled.
14141  */
14142 /*@{*/
14143 /*! @brief Read current value of the MCG_SC_ATME field. */
14144 #define MCG_RD_SC_ATME(base) ((MCG_SC_REG(base) & MCG_SC_ATME_MASK) >> MCG_SC_ATME_SHIFT)
14145 #define MCG_BRD_SC_ATME(base) (BME_UBFX8(&MCG_SC_REG(base), MCG_SC_ATME_SHIFT, MCG_SC_ATME_WIDTH))
14146 
14147 /*! @brief Set the ATME field to a new value. */
14148 #define MCG_WR_SC_ATME(base, value) (MCG_RMW_SC(base, (MCG_SC_ATME_MASK | MCG_SC_LOCS0_MASK | MCG_SC_ATMF_MASK), MCG_SC_ATME(value)))
14149 #define MCG_BWR_SC_ATME(base, value) (BME_BFI8(&MCG_SC_REG(base), ((uint8_t)(value) << MCG_SC_ATME_SHIFT), MCG_SC_ATME_SHIFT, MCG_SC_ATME_WIDTH))
14150 /*@}*/
14151 
14152 /*******************************************************************************
14153  * MCG_ATCVH - MCG Auto Trim Compare Value High Register
14154  ******************************************************************************/
14155 
14156 /*!
14157  * @brief MCG_ATCVH - MCG Auto Trim Compare Value High Register (RW)
14158  *
14159  * Reset value: 0x00U
14160  */
14161 /*!
14162  * @name Constants and macros for entire MCG_ATCVH register
14163  */
14164 /*@{*/
14165 #define MCG_RD_ATCVH(base)       (MCG_ATCVH_REG(base))
14166 #define MCG_WR_ATCVH(base, value) (MCG_ATCVH_REG(base) = (value))
14167 #define MCG_RMW_ATCVH(base, mask, value) (MCG_WR_ATCVH(base, (MCG_RD_ATCVH(base) & ~(mask)) | (value)))
14168 #define MCG_SET_ATCVH(base, value) (BME_OR8(&MCG_ATCVH_REG(base), (uint8_t)(value)))
14169 #define MCG_CLR_ATCVH(base, value) (BME_AND8(&MCG_ATCVH_REG(base), (uint8_t)(~(value))))
14170 #define MCG_TOG_ATCVH(base, value) (BME_XOR8(&MCG_ATCVH_REG(base), (uint8_t)(value)))
14171 /*@}*/
14172 
14173 /*******************************************************************************
14174  * MCG_ATCVL - MCG Auto Trim Compare Value Low Register
14175  ******************************************************************************/
14176 
14177 /*!
14178  * @brief MCG_ATCVL - MCG Auto Trim Compare Value Low Register (RW)
14179  *
14180  * Reset value: 0x00U
14181  */
14182 /*!
14183  * @name Constants and macros for entire MCG_ATCVL register
14184  */
14185 /*@{*/
14186 #define MCG_RD_ATCVL(base)       (MCG_ATCVL_REG(base))
14187 #define MCG_WR_ATCVL(base, value) (MCG_ATCVL_REG(base) = (value))
14188 #define MCG_RMW_ATCVL(base, mask, value) (MCG_WR_ATCVL(base, (MCG_RD_ATCVL(base) & ~(mask)) | (value)))
14189 #define MCG_SET_ATCVL(base, value) (BME_OR8(&MCG_ATCVL_REG(base), (uint8_t)(value)))
14190 #define MCG_CLR_ATCVL(base, value) (BME_AND8(&MCG_ATCVL_REG(base), (uint8_t)(~(value))))
14191 #define MCG_TOG_ATCVL(base, value) (BME_XOR8(&MCG_ATCVL_REG(base), (uint8_t)(value)))
14192 /*@}*/
14193 
14194 /*******************************************************************************
14195  * MCG_C7 - MCG Control 7 Register
14196  ******************************************************************************/
14197 
14198 /*!
14199  * @brief MCG_C7 - MCG Control 7 Register (RW)
14200  *
14201  * Reset value: 0x00U
14202  */
14203 /*!
14204  * @name Constants and macros for entire MCG_C7 register
14205  */
14206 /*@{*/
14207 #define MCG_RD_C7(base)          (MCG_C7_REG(base))
14208 #define MCG_WR_C7(base, value)   (MCG_C7_REG(base) = (value))
14209 #define MCG_RMW_C7(base, mask, value) (MCG_WR_C7(base, (MCG_RD_C7(base) & ~(mask)) | (value)))
14210 #define MCG_SET_C7(base, value)  (BME_OR8(&MCG_C7_REG(base), (uint8_t)(value)))
14211 #define MCG_CLR_C7(base, value)  (BME_AND8(&MCG_C7_REG(base), (uint8_t)(~(value))))
14212 #define MCG_TOG_C7(base, value)  (BME_XOR8(&MCG_C7_REG(base), (uint8_t)(value)))
14213 /*@}*/
14214 
14215 /*
14216  * Constants & macros for individual MCG_C7 bitfields
14217  */
14218 
14219 /*!
14220  * @name Register MCG_C7, field OSCSEL[0] (RW)
14221  *
14222  * Selects the MCG FLL external reference clock
14223  *
14224  * Values:
14225  * - 0b0 - Selects Oscillator (OSCCLK).
14226  * - 0b1 - Selects 32 kHz RTC Oscillator.
14227  */
14228 /*@{*/
14229 /*! @brief Read current value of the MCG_C7_OSCSEL field. */
14230 #define MCG_RD_C7_OSCSEL(base) ((MCG_C7_REG(base) & MCG_C7_OSCSEL_MASK) >> MCG_C7_OSCSEL_SHIFT)
14231 #define MCG_BRD_C7_OSCSEL(base) (BME_UBFX8(&MCG_C7_REG(base), MCG_C7_OSCSEL_SHIFT, MCG_C7_OSCSEL_WIDTH))
14232 
14233 /*! @brief Set the OSCSEL field to a new value. */
14234 #define MCG_WR_C7_OSCSEL(base, value) (MCG_RMW_C7(base, MCG_C7_OSCSEL_MASK, MCG_C7_OSCSEL(value)))
14235 #define MCG_BWR_C7_OSCSEL(base, value) (BME_BFI8(&MCG_C7_REG(base), ((uint8_t)(value) << MCG_C7_OSCSEL_SHIFT), MCG_C7_OSCSEL_SHIFT, MCG_C7_OSCSEL_WIDTH))
14236 /*@}*/
14237 
14238 /*******************************************************************************
14239  * MCG_C8 - MCG Control 8 Register
14240  ******************************************************************************/
14241 
14242 /*!
14243  * @brief MCG_C8 - MCG Control 8 Register (RW)
14244  *
14245  * Reset value: 0x80U
14246  */
14247 /*!
14248  * @name Constants and macros for entire MCG_C8 register
14249  */
14250 /*@{*/
14251 #define MCG_RD_C8(base)          (MCG_C8_REG(base))
14252 #define MCG_WR_C8(base, value)   (MCG_C8_REG(base) = (value))
14253 #define MCG_RMW_C8(base, mask, value) (MCG_WR_C8(base, (MCG_RD_C8(base) & ~(mask)) | (value)))
14254 #define MCG_SET_C8(base, value)  (BME_OR8(&MCG_C8_REG(base), (uint8_t)(value)))
14255 #define MCG_CLR_C8(base, value)  (BME_AND8(&MCG_C8_REG(base), (uint8_t)(~(value))))
14256 #define MCG_TOG_C8(base, value)  (BME_XOR8(&MCG_C8_REG(base), (uint8_t)(value)))
14257 /*@}*/
14258 
14259 /*
14260  * Constants & macros for individual MCG_C8 bitfields
14261  */
14262 
14263 /*!
14264  * @name Register MCG_C8, field LOCS1[0] (W1C)
14265  *
14266  * This bit indicates when a loss of clock has occurred. This bit is cleared by
14267  * writing a logic 1 to it when set.
14268  *
14269  * Values:
14270  * - 0b0 - Loss of RTC has not occur.
14271  * - 0b1 - Loss of RTC has occur
14272  */
14273 /*@{*/
14274 /*! @brief Read current value of the MCG_C8_LOCS1 field. */
14275 #define MCG_RD_C8_LOCS1(base) ((MCG_C8_REG(base) & MCG_C8_LOCS1_MASK) >> MCG_C8_LOCS1_SHIFT)
14276 #define MCG_BRD_C8_LOCS1(base) (BME_UBFX8(&MCG_C8_REG(base), MCG_C8_LOCS1_SHIFT, MCG_C8_LOCS1_WIDTH))
14277 
14278 /*! @brief Set the LOCS1 field to a new value. */
14279 #define MCG_WR_C8_LOCS1(base, value) (MCG_RMW_C8(base, MCG_C8_LOCS1_MASK, MCG_C8_LOCS1(value)))
14280 #define MCG_BWR_C8_LOCS1(base, value) (BME_BFI8(&MCG_C8_REG(base), ((uint8_t)(value) << MCG_C8_LOCS1_SHIFT), MCG_C8_LOCS1_SHIFT, MCG_C8_LOCS1_WIDTH))
14281 /*@}*/
14282 
14283 /*!
14284  * @name Register MCG_C8, field CME1[5] (RW)
14285  *
14286  * Enables the loss of clock monitoring circuit for the output of the RTC
14287  * external reference clock. The LOCRE1 bit will determine whether an interrupt or a
14288  * reset request is generated following a loss of RTC clock indication. The CME1
14289  * bit should be set to a logic 1 when the MCG is in an operational mode that uses
14290  * the RTC as its external reference clock or if the RTC is operational. CME1 bit
14291  * must be set to a logic 0 before the MCG enters any Stop mode. Otherwise, a
14292  * reset request may occur when in Stop mode. CME1 should also be set to a logic 0
14293  * before entering VLPR or VLPW power modes.
14294  *
14295  * Values:
14296  * - 0b0 - External clock monitor is disabled for RTC clock.
14297  * - 0b1 - External clock monitor is enabled for RTC clock.
14298  */
14299 /*@{*/
14300 /*! @brief Read current value of the MCG_C8_CME1 field. */
14301 #define MCG_RD_C8_CME1(base) ((MCG_C8_REG(base) & MCG_C8_CME1_MASK) >> MCG_C8_CME1_SHIFT)
14302 #define MCG_BRD_C8_CME1(base) (BME_UBFX8(&MCG_C8_REG(base), MCG_C8_CME1_SHIFT, MCG_C8_CME1_WIDTH))
14303 
14304 /*! @brief Set the CME1 field to a new value. */
14305 #define MCG_WR_C8_CME1(base, value) (MCG_RMW_C8(base, (MCG_C8_CME1_MASK | MCG_C8_LOCS1_MASK), MCG_C8_CME1(value)))
14306 #define MCG_BWR_C8_CME1(base, value) (BME_BFI8(&MCG_C8_REG(base), ((uint8_t)(value) << MCG_C8_CME1_SHIFT), MCG_C8_CME1_SHIFT, MCG_C8_CME1_WIDTH))
14307 /*@}*/
14308 
14309 /*!
14310  * @name Register MCG_C8, field LOCRE1[7] (RW)
14311  *
14312  * Determines if a interrupt or a reset request is made following a loss of RTC
14313  * external reference clock. The LOCRE1 only has an affect when CME1 is set.
14314  *
14315  * Values:
14316  * - 0b0 - Interrupt request is generated on a loss of RTC external reference
14317  *     clock.
14318  * - 0b1 - Generate a reset request on a loss of RTC external reference clock
14319  */
14320 /*@{*/
14321 /*! @brief Read current value of the MCG_C8_LOCRE1 field. */
14322 #define MCG_RD_C8_LOCRE1(base) ((MCG_C8_REG(base) & MCG_C8_LOCRE1_MASK) >> MCG_C8_LOCRE1_SHIFT)
14323 #define MCG_BRD_C8_LOCRE1(base) (BME_UBFX8(&MCG_C8_REG(base), MCG_C8_LOCRE1_SHIFT, MCG_C8_LOCRE1_WIDTH))
14324 
14325 /*! @brief Set the LOCRE1 field to a new value. */
14326 #define MCG_WR_C8_LOCRE1(base, value) (MCG_RMW_C8(base, (MCG_C8_LOCRE1_MASK | MCG_C8_LOCS1_MASK), MCG_C8_LOCRE1(value)))
14327 #define MCG_BWR_C8_LOCRE1(base, value) (BME_BFI8(&MCG_C8_REG(base), ((uint8_t)(value) << MCG_C8_LOCRE1_SHIFT), MCG_C8_LOCRE1_SHIFT, MCG_C8_LOCRE1_WIDTH))
14328 /*@}*/
14329 
14330 /*
14331  * MKW40Z4 MCM
14332  *
14333  * Core Platform Miscellaneous Control Module
14334  *
14335  * Registers defined in this header file:
14336  * - MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
14337  * - MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
14338  * - MCM_PLACR - Platform Control Register
14339  * - MCM_CPO - Compute Operation Control Register
14340  */
14341 
14342 #define MCM_INSTANCE_COUNT (1U) /*!< Number of instances of the MCM module. */
14343 #define MCM_IDX (0U) /*!< Instance number for MCM. */
14344 
14345 /*******************************************************************************
14346  * MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration
14347  ******************************************************************************/
14348 
14349 /*!
14350  * @brief MCM_PLASC - Crossbar Switch (AXBS) Slave Configuration (RO)
14351  *
14352  * Reset value: 0x0007U
14353  *
14354  * PLASC is a 16-bit read-only register identifying the presence/absence of bus
14355  * slave connections to the device's crossbar switch.
14356  */
14357 /*!
14358  * @name Constants and macros for entire MCM_PLASC register
14359  */
14360 /*@{*/
14361 #define MCM_RD_PLASC(base)       (MCM_PLASC_REG(base))
14362 /*@}*/
14363 
14364 /*
14365  * Constants & macros for individual MCM_PLASC bitfields
14366  */
14367 
14368 /*!
14369  * @name Register MCM_PLASC, field ASC[7:0] (RO)
14370  *
14371  * Values:
14372  * - 0b00000000 - A bus slave connection to AXBS input port n is absent.
14373  * - 0b00000001 - A bus slave connection to AXBS input port n is present.
14374  */
14375 /*@{*/
14376 /*! @brief Read current value of the MCM_PLASC_ASC field. */
14377 #define MCM_RD_PLASC_ASC(base) ((MCM_PLASC_REG(base) & MCM_PLASC_ASC_MASK) >> MCM_PLASC_ASC_SHIFT)
14378 #define MCM_BRD_PLASC_ASC(base) (MCM_RD_PLASC_ASC(base))
14379 /*@}*/
14380 
14381 /*******************************************************************************
14382  * MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration
14383  ******************************************************************************/
14384 
14385 /*!
14386  * @brief MCM_PLAMC - Crossbar Switch (AXBS) Master Configuration (RO)
14387  *
14388  * Reset value: 0x0005U
14389  *
14390  * PLAMC is a 16-bit read-only register identifying the presence/absence of bus
14391  * master connections to the device's crossbar switch.
14392  */
14393 /*!
14394  * @name Constants and macros for entire MCM_PLAMC register
14395  */
14396 /*@{*/
14397 #define MCM_RD_PLAMC(base)       (MCM_PLAMC_REG(base))
14398 /*@}*/
14399 
14400 /*
14401  * Constants & macros for individual MCM_PLAMC bitfields
14402  */
14403 
14404 /*!
14405  * @name Register MCM_PLAMC, field AMC[7:0] (RO)
14406  *
14407  * Values:
14408  * - 0b00000000 - A bus master connection to AXBS input port n is absent
14409  * - 0b00000001 - A bus master connection to AXBS input port n is present
14410  */
14411 /*@{*/
14412 /*! @brief Read current value of the MCM_PLAMC_AMC field. */
14413 #define MCM_RD_PLAMC_AMC(base) ((MCM_PLAMC_REG(base) & MCM_PLAMC_AMC_MASK) >> MCM_PLAMC_AMC_SHIFT)
14414 #define MCM_BRD_PLAMC_AMC(base) (MCM_RD_PLAMC_AMC(base))
14415 /*@}*/
14416 
14417 /*******************************************************************************
14418  * MCM_PLACR - Platform Control Register
14419  ******************************************************************************/
14420 
14421 /*!
14422  * @brief MCM_PLACR - Platform Control Register (RW)
14423  *
14424  * Reset value: 0x00000050U
14425  *
14426  * The PLACR register selects the arbitration policy for the crossbar masters
14427  * and configures the flash memory controller. The speculation buffer and cache in
14428  * the flash memory controller is configurable via PLACR[15:10 ]. The speculation
14429  * buffer is enabled only for instructions after reset. It is possible to have
14430  * these states for the speculation buffer: DFCS EFDS Description 0 0 Speculation
14431  * buffer is on for instruction and off for data. 0 1 Speculation buffer is on
14432  * for instruction and on for data. 1 X Speculation buffer is off. The cache in
14433  * flash controller is enabled and caching both instruction and data type fetches
14434  * after reset. It is possible to have these states for the cache: DFCC DFCIC DFCDA
14435  * Description 0 0 0 Cache is on for both instruction and data. 0 0 1 Cache is
14436  * on for instruction and off for data. 0 1 0 Cache is off for instruction and on
14437  * for data. 0 1 1 Cache is off for both instruction and data. 1 X X Cache is
14438  * off. ***FOR APACHE ONLY (as far as Alan Ratliff knows on 17 June 2014) from...
14439  * Document Number: APACHE PLATREQ, Rev 6.0, Oct.15, 2013*** Some of these bits may
14440  * be for internal use only: [1:0] AXBS stall FSM (read-only) [2] AXBS stall
14441  * request (read-only) [3] AXBS halted (read-only) [4] PFLASHC idle (read-only) [6]
14442  * PBRIDGE Idle (read-only) [18] Enable inserting 1T delay on BME undecorated
14443  * read data path [19] Enable inserting 1T delay on BME undecorated write data path
14444  */
14445 /*!
14446  * @name Constants and macros for entire MCM_PLACR register
14447  */
14448 /*@{*/
14449 #define MCM_RD_PLACR(base)       (MCM_PLACR_REG(base))
14450 #define MCM_WR_PLACR(base, value) (MCM_PLACR_REG(base) = (value))
14451 #define MCM_RMW_PLACR(base, mask, value) (MCM_WR_PLACR(base, (MCM_RD_PLACR(base) & ~(mask)) | (value)))
14452 #define MCM_SET_PLACR(base, value) (MCM_WR_PLACR(base, MCM_RD_PLACR(base) |  (value)))
14453 #define MCM_CLR_PLACR(base, value) (MCM_WR_PLACR(base, MCM_RD_PLACR(base) & ~(value)))
14454 #define MCM_TOG_PLACR(base, value) (MCM_WR_PLACR(base, MCM_RD_PLACR(base) ^  (value)))
14455 /*@}*/
14456 
14457 /*
14458  * Constants & macros for individual MCM_PLACR bitfields
14459  */
14460 
14461 /*!
14462  * @name Register MCM_PLACR, field ARB[9] (RW)
14463  *
14464  * Values:
14465  * - 0b0 - Fixed-priority arbitration for the crossbar masters
14466  * - 0b1 - Round-robin arbitration for the crossbar masters
14467  */
14468 /*@{*/
14469 /*! @brief Read current value of the MCM_PLACR_ARB field. */
14470 #define MCM_RD_PLACR_ARB(base) ((MCM_PLACR_REG(base) & MCM_PLACR_ARB_MASK) >> MCM_PLACR_ARB_SHIFT)
14471 #define MCM_BRD_PLACR_ARB(base) (MCM_RD_PLACR_ARB(base))
14472 
14473 /*! @brief Set the ARB field to a new value. */
14474 #define MCM_WR_PLACR_ARB(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_ARB_MASK, MCM_PLACR_ARB(value)))
14475 #define MCM_BWR_PLACR_ARB(base, value) (MCM_WR_PLACR_ARB(base, value))
14476 /*@}*/
14477 
14478 /*!
14479  * @name Register MCM_PLACR, field CFCC[10] (WORZ)
14480  *
14481  * Writing a 1 to this field clears the cache. Writing a 0 to this field is
14482  * ignored. This field always reads as 0.
14483  */
14484 /*@{*/
14485 /*! @brief Set the CFCC field to a new value. */
14486 #define MCM_WR_PLACR_CFCC(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_CFCC_MASK, MCM_PLACR_CFCC(value)))
14487 #define MCM_BWR_PLACR_CFCC(base, value) (MCM_WR_PLACR_CFCC(base, value))
14488 /*@}*/
14489 
14490 /*!
14491  * @name Register MCM_PLACR, field DFCDA[11] (RW)
14492  *
14493  * Disables flash controller data caching.
14494  *
14495  * Values:
14496  * - 0b0 - Enable flash controller data caching
14497  * - 0b1 - Disable flash controller data caching.
14498  */
14499 /*@{*/
14500 /*! @brief Read current value of the MCM_PLACR_DFCDA field. */
14501 #define MCM_RD_PLACR_DFCDA(base) ((MCM_PLACR_REG(base) & MCM_PLACR_DFCDA_MASK) >> MCM_PLACR_DFCDA_SHIFT)
14502 #define MCM_BRD_PLACR_DFCDA(base) (MCM_RD_PLACR_DFCDA(base))
14503 
14504 /*! @brief Set the DFCDA field to a new value. */
14505 #define MCM_WR_PLACR_DFCDA(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_DFCDA_MASK, MCM_PLACR_DFCDA(value)))
14506 #define MCM_BWR_PLACR_DFCDA(base, value) (MCM_WR_PLACR_DFCDA(base, value))
14507 /*@}*/
14508 
14509 /*!
14510  * @name Register MCM_PLACR, field DFCIC[12] (RW)
14511  *
14512  * Disables flash controller instruction caching.
14513  *
14514  * Values:
14515  * - 0b0 - Enable flash controller instruction caching.
14516  * - 0b1 - Disable flash controller instruction caching.
14517  */
14518 /*@{*/
14519 /*! @brief Read current value of the MCM_PLACR_DFCIC field. */
14520 #define MCM_RD_PLACR_DFCIC(base) ((MCM_PLACR_REG(base) & MCM_PLACR_DFCIC_MASK) >> MCM_PLACR_DFCIC_SHIFT)
14521 #define MCM_BRD_PLACR_DFCIC(base) (MCM_RD_PLACR_DFCIC(base))
14522 
14523 /*! @brief Set the DFCIC field to a new value. */
14524 #define MCM_WR_PLACR_DFCIC(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_DFCIC_MASK, MCM_PLACR_DFCIC(value)))
14525 #define MCM_BWR_PLACR_DFCIC(base, value) (MCM_WR_PLACR_DFCIC(base, value))
14526 /*@}*/
14527 
14528 /*!
14529  * @name Register MCM_PLACR, field DFCC[13] (RW)
14530  *
14531  * Disables flash controller cache.
14532  *
14533  * Values:
14534  * - 0b0 - Enable flash controller cache.
14535  * - 0b1 - Disable flash controller cache.
14536  */
14537 /*@{*/
14538 /*! @brief Read current value of the MCM_PLACR_DFCC field. */
14539 #define MCM_RD_PLACR_DFCC(base) ((MCM_PLACR_REG(base) & MCM_PLACR_DFCC_MASK) >> MCM_PLACR_DFCC_SHIFT)
14540 #define MCM_BRD_PLACR_DFCC(base) (MCM_RD_PLACR_DFCC(base))
14541 
14542 /*! @brief Set the DFCC field to a new value. */
14543 #define MCM_WR_PLACR_DFCC(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_DFCC_MASK, MCM_PLACR_DFCC(value)))
14544 #define MCM_BWR_PLACR_DFCC(base, value) (MCM_WR_PLACR_DFCC(base, value))
14545 /*@}*/
14546 
14547 /*!
14548  * @name Register MCM_PLACR, field EFDS[14] (RW)
14549  *
14550  * Enables flash data speculation.
14551  *
14552  * Values:
14553  * - 0b0 - Disable flash data speculation.
14554  * - 0b1 - Enable flash data speculation.
14555  */
14556 /*@{*/
14557 /*! @brief Read current value of the MCM_PLACR_EFDS field. */
14558 #define MCM_RD_PLACR_EFDS(base) ((MCM_PLACR_REG(base) & MCM_PLACR_EFDS_MASK) >> MCM_PLACR_EFDS_SHIFT)
14559 #define MCM_BRD_PLACR_EFDS(base) (MCM_RD_PLACR_EFDS(base))
14560 
14561 /*! @brief Set the EFDS field to a new value. */
14562 #define MCM_WR_PLACR_EFDS(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_EFDS_MASK, MCM_PLACR_EFDS(value)))
14563 #define MCM_BWR_PLACR_EFDS(base, value) (MCM_WR_PLACR_EFDS(base, value))
14564 /*@}*/
14565 
14566 /*!
14567  * @name Register MCM_PLACR, field DFCS[15] (RW)
14568  *
14569  * Disables flash controller speculation.
14570  *
14571  * Values:
14572  * - 0b0 - Enable flash controller speculation.
14573  * - 0b1 - Disable flash controller speculation.
14574  */
14575 /*@{*/
14576 /*! @brief Read current value of the MCM_PLACR_DFCS field. */
14577 #define MCM_RD_PLACR_DFCS(base) ((MCM_PLACR_REG(base) & MCM_PLACR_DFCS_MASK) >> MCM_PLACR_DFCS_SHIFT)
14578 #define MCM_BRD_PLACR_DFCS(base) (MCM_RD_PLACR_DFCS(base))
14579 
14580 /*! @brief Set the DFCS field to a new value. */
14581 #define MCM_WR_PLACR_DFCS(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_DFCS_MASK, MCM_PLACR_DFCS(value)))
14582 #define MCM_BWR_PLACR_DFCS(base, value) (MCM_WR_PLACR_DFCS(base, value))
14583 /*@}*/
14584 
14585 /*!
14586  * @name Register MCM_PLACR, field ESFC[16] (RW)
14587  *
14588  * Enables stalling flash controller when flash is busy. When software needs to
14589  * access the flash memory while a flash memory resource is being manipulated by
14590  * a flash command, software can enable a stall mechanism to avoid a read
14591  * collision. The stall mechanism allows software to execute code from the same block on
14592  * which flash operations are being performed. However, software must ensure the
14593  * sector the flash operations are being performed on is not the same sector
14594  * from which the code is executing. ESFC enables the stall mechanism. This bit must
14595  * be set only just before the flash operation is executed and must be cleared
14596  * when the operation completes.
14597  *
14598  * Values:
14599  * - 0b0 - Disable stalling flash controller when flash is busy.
14600  * - 0b1 - Enable stalling flash controller when flash is busy.
14601  */
14602 /*@{*/
14603 /*! @brief Read current value of the MCM_PLACR_ESFC field. */
14604 #define MCM_RD_PLACR_ESFC(base) ((MCM_PLACR_REG(base) & MCM_PLACR_ESFC_MASK) >> MCM_PLACR_ESFC_SHIFT)
14605 #define MCM_BRD_PLACR_ESFC(base) (MCM_RD_PLACR_ESFC(base))
14606 
14607 /*! @brief Set the ESFC field to a new value. */
14608 #define MCM_WR_PLACR_ESFC(base, value) (MCM_RMW_PLACR(base, MCM_PLACR_ESFC_MASK, MCM_PLACR_ESFC(value)))
14609 #define MCM_BWR_PLACR_ESFC(base, value) (MCM_WR_PLACR_ESFC(base, value))
14610 /*@}*/
14611 
14612 /*******************************************************************************
14613  * MCM_CPO - Compute Operation Control Register
14614  ******************************************************************************/
14615 
14616 /*!
14617  * @brief MCM_CPO - Compute Operation Control Register (RW)
14618  *
14619  * Reset value: 0x00000000U
14620  *
14621  * This register controls the Compute Operation.
14622  */
14623 /*!
14624  * @name Constants and macros for entire MCM_CPO register
14625  */
14626 /*@{*/
14627 #define MCM_RD_CPO(base)         (MCM_CPO_REG(base))
14628 #define MCM_WR_CPO(base, value)  (MCM_CPO_REG(base) = (value))
14629 #define MCM_RMW_CPO(base, mask, value) (MCM_WR_CPO(base, (MCM_RD_CPO(base) & ~(mask)) | (value)))
14630 #define MCM_SET_CPO(base, value) (MCM_WR_CPO(base, MCM_RD_CPO(base) |  (value)))
14631 #define MCM_CLR_CPO(base, value) (MCM_WR_CPO(base, MCM_RD_CPO(base) & ~(value)))
14632 #define MCM_TOG_CPO(base, value) (MCM_WR_CPO(base, MCM_RD_CPO(base) ^  (value)))
14633 /*@}*/
14634 
14635 /*
14636  * Constants & macros for individual MCM_CPO bitfields
14637  */
14638 
14639 /*!
14640  * @name Register MCM_CPO, field CPOREQ[0] (RW)
14641  *
14642  * This bit is auto-cleared by vector fetching if CPOWOI = 1.
14643  *
14644  * Values:
14645  * - 0b0 - Request is cleared.
14646  * - 0b1 - Request Compute Operation.
14647  */
14648 /*@{*/
14649 /*! @brief Read current value of the MCM_CPO_CPOREQ field. */
14650 #define MCM_RD_CPO_CPOREQ(base) ((MCM_CPO_REG(base) & MCM_CPO_CPOREQ_MASK) >> MCM_CPO_CPOREQ_SHIFT)
14651 #define MCM_BRD_CPO_CPOREQ(base) (MCM_RD_CPO_CPOREQ(base))
14652 
14653 /*! @brief Set the CPOREQ field to a new value. */
14654 #define MCM_WR_CPO_CPOREQ(base, value) (MCM_RMW_CPO(base, MCM_CPO_CPOREQ_MASK, MCM_CPO_CPOREQ(value)))
14655 #define MCM_BWR_CPO_CPOREQ(base, value) (MCM_WR_CPO_CPOREQ(base, value))
14656 /*@}*/
14657 
14658 /*!
14659  * @name Register MCM_CPO, field CPOACK[1] (RO)
14660  *
14661  * Values:
14662  * - 0b0 - Compute operation entry has not completed or compute operation exit
14663  *     has completed.
14664  * - 0b1 - Compute operation entry has completed or compute operation exit has
14665  *     not completed.
14666  */
14667 /*@{*/
14668 /*! @brief Read current value of the MCM_CPO_CPOACK field. */
14669 #define MCM_RD_CPO_CPOACK(base) ((MCM_CPO_REG(base) & MCM_CPO_CPOACK_MASK) >> MCM_CPO_CPOACK_SHIFT)
14670 #define MCM_BRD_CPO_CPOACK(base) (MCM_RD_CPO_CPOACK(base))
14671 /*@}*/
14672 
14673 /*!
14674  * @name Register MCM_CPO, field CPOWOI[2] (RW)
14675  *
14676  * Values:
14677  * - 0b0 - No effect.
14678  * - 0b1 - When set, the CPOREQ is cleared on any interrupt or exception vector
14679  *     fetch.
14680  */
14681 /*@{*/
14682 /*! @brief Read current value of the MCM_CPO_CPOWOI field. */
14683 #define MCM_RD_CPO_CPOWOI(base) ((MCM_CPO_REG(base) & MCM_CPO_CPOWOI_MASK) >> MCM_CPO_CPOWOI_SHIFT)
14684 #define MCM_BRD_CPO_CPOWOI(base) (MCM_RD_CPO_CPOWOI(base))
14685 
14686 /*! @brief Set the CPOWOI field to a new value. */
14687 #define MCM_WR_CPO_CPOWOI(base, value) (MCM_RMW_CPO(base, MCM_CPO_CPOWOI_MASK, MCM_CPO_CPOWOI(value)))
14688 #define MCM_BWR_CPO_CPOWOI(base, value) (MCM_WR_CPO_CPOWOI(base, value))
14689 /*@}*/
14690 
14691 /*
14692  * MKW40Z4 MTB
14693  *
14694  * Micro Trace Buffer
14695  *
14696  * Registers defined in this header file:
14697  * - MTB_POSITION - MTB Position Register
14698  * - MTB_MASTER - MTB Master Register
14699  * - MTB_FLOW - MTB Flow Register
14700  * - MTB_BASE - MTB Base Register
14701  * - MTB_MODECTRL - Integration Mode Control Register
14702  * - MTB_TAGSET - Claim TAG Set Register
14703  * - MTB_TAGCLEAR - Claim TAG Clear Register
14704  * - MTB_LOCKACCESS - Lock Access Register
14705  * - MTB_LOCKSTAT - Lock Status Register
14706  * - MTB_AUTHSTAT - Authentication Status Register
14707  * - MTB_DEVICEARCH - Device Architecture Register
14708  * - MTB_DEVICECFG - Device Configuration Register
14709  * - MTB_DEVICETYPID - Device Type Identifier Register
14710  * - MTB_PERIPHID - Peripheral ID Register
14711  * - MTB_COMPID - Component ID Register
14712  */
14713 
14714 #define MTB_INSTANCE_COUNT (1U) /*!< Number of instances of the MTB module. */
14715 #define MTB_IDX (0U) /*!< Instance number for MTB. */
14716 
14717 /*******************************************************************************
14718  * MTB_POSITION - MTB Position Register
14719  ******************************************************************************/
14720 
14721 /*!
14722  * @brief MTB_POSITION - MTB Position Register (RW)
14723  *
14724  * Reset value: 0x00000000U
14725  *
14726  * The MTB_POSITION register contains the Trace Write Address Pointer and Wrap
14727  * fields. This register can be modified by the explicit programming model writes.
14728  * It is also automatically updated by the MTB hardware when trace packets are
14729  * being recorded. The base address of the system RAM in the memory map dictates
14730  * special consideration for the placement of the MTB. Consider the following
14731  * guidelines: For the standard configuration where the size of the MTB is <= 25% of
14732  * the total RAM capacity, it is recommended the MTB be based at the address
14733  * defined by the MTB_BASE register. The read-only MTB_BASE register is defined by
14734  * the expression (0x2000_0000 - (RAM_Size/4)). For this configuration, the
14735  * MTB_POSITION register is initialized to MTB_BASE & 0x0000_7FF8. If the size of the
14736  * MTB is more than 25% but less than or equal to 50% of the total RAM capacity, it
14737  * is recommended the MTB be based at address 0x2000_0000. In this
14738  * configuration, the MTB_POSITION register is initialized to (0x2000_0000 & 0x0000_7FF8) =
14739  * 0x0000_00000. Following these two suggested placements provides a full-featured
14740  * circular memory buffer containing program trace packets. In the unlikely event
14741  * an even larger trace buffer is required, a write-once capacity of 75% of the
14742  * total RAM capacity can be based at address 0x2000_0000. The MTB_POSITION
14743  * register is initialized to (0x2000_0000 & 0x0000_7FF8) = 0x0000_0000. However, this
14744  * configuration cannot support operation as a circular queue and instead
14745  * requires the use of the MTB_FLOW[WATERMARK] capability to automatically disable
14746  * tracing or halting the processor as the number of packet writes approach the
14747  * buffer capacity. See the MTB_FLOW register description for more details.
14748  */
14749 /*!
14750  * @name Constants and macros for entire MTB_POSITION register
14751  */
14752 /*@{*/
14753 #define MTB_RD_POSITION(base)    (MTB_POSITION_REG(base))
14754 #define MTB_WR_POSITION(base, value) (MTB_POSITION_REG(base) = (value))
14755 #define MTB_RMW_POSITION(base, mask, value) (MTB_WR_POSITION(base, (MTB_RD_POSITION(base) & ~(mask)) | (value)))
14756 #define MTB_SET_POSITION(base, value) (MTB_WR_POSITION(base, MTB_RD_POSITION(base) |  (value)))
14757 #define MTB_CLR_POSITION(base, value) (MTB_WR_POSITION(base, MTB_RD_POSITION(base) & ~(value)))
14758 #define MTB_TOG_POSITION(base, value) (MTB_WR_POSITION(base, MTB_RD_POSITION(base) ^  (value)))
14759 /*@}*/
14760 
14761 /*
14762  * Constants & macros for individual MTB_POSITION bitfields
14763  */
14764 
14765 /*!
14766  * @name Register MTB_POSITION, field WRAP[2] (RW)
14767  *
14768  * This field is set to 1 automatically when the POINTER value wraps as
14769  * determined by the MTB_MASTER[MASK] field in the MASTER Trace Control Register. A debug
14770  * agent might use the WRAP field to determine whether the trace information
14771  * above and below the pointer address is valid.
14772  */
14773 /*@{*/
14774 /*! @brief Read current value of the MTB_POSITION_WRAP field. */
14775 #define MTB_RD_POSITION_WRAP(base) ((MTB_POSITION_REG(base) & MTB_POSITION_WRAP_MASK) >> MTB_POSITION_WRAP_SHIFT)
14776 #define MTB_BRD_POSITION_WRAP(base) (MTB_RD_POSITION_WRAP(base))
14777 
14778 /*! @brief Set the WRAP field to a new value. */
14779 #define MTB_WR_POSITION_WRAP(base, value) (MTB_RMW_POSITION(base, MTB_POSITION_WRAP_MASK, MTB_POSITION_WRAP(value)))
14780 #define MTB_BWR_POSITION_WRAP(base, value) (MTB_WR_POSITION_WRAP(base, value))
14781 /*@}*/
14782 
14783 /*!
14784  * @name Register MTB_POSITION, field POINTER[31:3] (RW)
14785  *
14786  * Because a packet consists of two words, the POINTER field is the address of
14787  * the first word of a packet. This field contains bits[31:3] of the RAM address
14788  * where the next trace packet is written. Therefore, it points to an unused
14789  * location and is automatically incremented. A debug agent can calculate the system
14790  * memory map address for the current location in the MTB using the following
14791  * "generic" equation: Given mtb_size = 1 << (MTB_MASTER[MASK] + 4), systemAddress =
14792  * MTB_BASE + (((MTB_POSITION & 0xFFFF_FFF8) + (mtb_size - (MTB_BASE &
14793  * (mtb_size-1)))) & 0x0000_7FF8); For this device, a simpler expression also applies. See
14794  * the following pseudo-code: if ((MTB_POSITION >> 13) == 0x3) systemAddress =
14795  * (0x1FFF << 16) + (0x1 << 15) + (MTB_POSITION & 0x7FF8); else systemAddress =
14796  * (0x2000 << 16) + (0x0 << 15) + (MTB_POSITION & 0x7FF8); The size of the RAM is
14797  * parameterized and the most significant bits of the POINTER field are RAZ/WI. For
14798  * these devices, POSITION[31:15] == POSITION[POINTER[28:12]] are RAZ/WI.
14799  * Therefore, the active bits in this field are POSITION[14:3] ==
14800  * POSITION[POINTER[11:0]].
14801  */
14802 /*@{*/
14803 /*! @brief Read current value of the MTB_POSITION_POINTER field. */
14804 #define MTB_RD_POSITION_POINTER(base) ((MTB_POSITION_REG(base) & MTB_POSITION_POINTER_MASK) >> MTB_POSITION_POINTER_SHIFT)
14805 #define MTB_BRD_POSITION_POINTER(base) (MTB_RD_POSITION_POINTER(base))
14806 
14807 /*! @brief Set the POINTER field to a new value. */
14808 #define MTB_WR_POSITION_POINTER(base, value) (MTB_RMW_POSITION(base, MTB_POSITION_POINTER_MASK, MTB_POSITION_POINTER(value)))
14809 #define MTB_BWR_POSITION_POINTER(base, value) (MTB_WR_POSITION_POINTER(base, value))
14810 /*@}*/
14811 
14812 /*******************************************************************************
14813  * MTB_MASTER - MTB Master Register
14814  ******************************************************************************/
14815 
14816 /*!
14817  * @brief MTB_MASTER - MTB Master Register (RW)
14818  *
14819  * Reset value: 0x00000080U
14820  *
14821  * The MTB_MASTER register contains the main program trace enable plus other
14822  * trace controls. This register can be modified by the explicit programming model
14823  * writes. MTB_MASTER[EN] and MTB_MASTER[HALTREQ] fields are also automatically
14824  * updated by the MTB hardware. Before MTB_MASTER[EN] or MTB_MASTER[TSTARTEN] are
14825  * set to 1, the software must initialize the MTB_POSITION and MTB_FLOW registers.
14826  * If MTB_FLOW[WATERMARK] is used to stop tracing or to halt the processor,
14827  * MTB_MASTER[MASK] must still be set to a value that prevents MTB_POSITION[POINTER]
14828  * from wrapping before it reaches the MTB_FLOW[WATERMARK] value. The format of
14829  * this mask field is different than MTBDWT_MASKn[MASK].
14830  */
14831 /*!
14832  * @name Constants and macros for entire MTB_MASTER register
14833  */
14834 /*@{*/
14835 #define MTB_RD_MASTER(base)      (MTB_MASTER_REG(base))
14836 #define MTB_WR_MASTER(base, value) (MTB_MASTER_REG(base) = (value))
14837 #define MTB_RMW_MASTER(base, mask, value) (MTB_WR_MASTER(base, (MTB_RD_MASTER(base) & ~(mask)) | (value)))
14838 #define MTB_SET_MASTER(base, value) (MTB_WR_MASTER(base, MTB_RD_MASTER(base) |  (value)))
14839 #define MTB_CLR_MASTER(base, value) (MTB_WR_MASTER(base, MTB_RD_MASTER(base) & ~(value)))
14840 #define MTB_TOG_MASTER(base, value) (MTB_WR_MASTER(base, MTB_RD_MASTER(base) ^  (value)))
14841 /*@}*/
14842 
14843 /*
14844  * Constants & macros for individual MTB_MASTER bitfields
14845  */
14846 
14847 /*!
14848  * @name Register MTB_MASTER, field MASK[4:0] (RW)
14849  *
14850  * This value determines the maximum size of the trace buffer in RAM. It
14851  * specifies the most-significant bit of the MTB_POSITION[POINTER] field that can be
14852  * updated by automatic increment. If the trace tries to advance past this power of
14853  * 2, the MTB_POSITION[WRAP] bit is set to 1, the MTB_POSITION[MASK+3:3] ==
14854  * MTB_POSITION[POINTER[MASK:0]] bits are set to 0, and the MTB_POSITION[14:MASK+3] ==
14855  * MTB_POSITION[POINTER[11:MASK+1]] bits remain unchanged. This field causes the
14856  * trace packet information to be stored in a circular buffer of size 2^[MASK+4]
14857  * bytes, that can be positioned in memory at multiples of this size. As
14858  * detailed in the MTB_POSITION description, typical "upper limits" for the MTB size are
14859  * RAM_Size/4 or RAM_Size/2. Values greater than the maximum have the same
14860  * effect as the maximum.
14861  */
14862 /*@{*/
14863 /*! @brief Read current value of the MTB_MASTER_MASK field. */
14864 #define MTB_RD_MASTER_MASK(base) ((MTB_MASTER_REG(base) & MTB_MASTER_MASK_MASK) >> MTB_MASTER_MASK_SHIFT)
14865 #define MTB_BRD_MASTER_MASK(base) (MTB_RD_MASTER_MASK(base))
14866 
14867 /*! @brief Set the MASK field to a new value. */
14868 #define MTB_WR_MASTER_MASK(base, value) (MTB_RMW_MASTER(base, MTB_MASTER_MASK_MASK, MTB_MASTER_MASK(value)))
14869 #define MTB_BWR_MASTER_MASK(base, value) (MTB_WR_MASTER_MASK(base, value))
14870 /*@}*/
14871 
14872 /*!
14873  * @name Register MTB_MASTER, field TSTARTEN[5] (RW)
14874  *
14875  * If this field is 1 and the TSTART signal is HIGH, then EN is set to 1.
14876  * Tracing continues until a stop condition occurs.
14877  */
14878 /*@{*/
14879 /*! @brief Read current value of the MTB_MASTER_TSTARTEN field. */
14880 #define MTB_RD_MASTER_TSTARTEN(base) ((MTB_MASTER_REG(base) & MTB_MASTER_TSTARTEN_MASK) >> MTB_MASTER_TSTARTEN_SHIFT)
14881 #define MTB_BRD_MASTER_TSTARTEN(base) (MTB_RD_MASTER_TSTARTEN(base))
14882 
14883 /*! @brief Set the TSTARTEN field to a new value. */
14884 #define MTB_WR_MASTER_TSTARTEN(base, value) (MTB_RMW_MASTER(base, MTB_MASTER_TSTARTEN_MASK, MTB_MASTER_TSTARTEN(value)))
14885 #define MTB_BWR_MASTER_TSTARTEN(base, value) (MTB_WR_MASTER_TSTARTEN(base, value))
14886 /*@}*/
14887 
14888 /*!
14889  * @name Register MTB_MASTER, field TSTOPEN[6] (RW)
14890  *
14891  * If this field is 1 and the TSTOP signal is HIGH, then EN is set to 0. If a
14892  * trace packet is being written to memory, the write is completed before tracing
14893  * is stopped.
14894  */
14895 /*@{*/
14896 /*! @brief Read current value of the MTB_MASTER_TSTOPEN field. */
14897 #define MTB_RD_MASTER_TSTOPEN(base) ((MTB_MASTER_REG(base) & MTB_MASTER_TSTOPEN_MASK) >> MTB_MASTER_TSTOPEN_SHIFT)
14898 #define MTB_BRD_MASTER_TSTOPEN(base) (MTB_RD_MASTER_TSTOPEN(base))
14899 
14900 /*! @brief Set the TSTOPEN field to a new value. */
14901 #define MTB_WR_MASTER_TSTOPEN(base, value) (MTB_RMW_MASTER(base, MTB_MASTER_TSTOPEN_MASK, MTB_MASTER_TSTOPEN(value)))
14902 #define MTB_BWR_MASTER_TSTOPEN(base, value) (MTB_WR_MASTER_TSTOPEN(base, value))
14903 /*@}*/
14904 
14905 /*!
14906  * @name Register MTB_MASTER, field SFRWPRIV[7] (RW)
14907  *
14908  * If this field is 0, then user or privileged AHB read and write accesses to
14909  * the MTB_RAM Special Function Registers (programming model) are permitted. If
14910  * this field is 1, then only privileged write accesses are permitted; user write
14911  * accesses are ignored. The HPROT[1] signal determines if an access is user or
14912  * privileged. Note MTB_RAM SFR read access are not controlled by this bit and are
14913  * always permitted.
14914  */
14915 /*@{*/
14916 /*! @brief Read current value of the MTB_MASTER_SFRWPRIV field. */
14917 #define MTB_RD_MASTER_SFRWPRIV(base) ((MTB_MASTER_REG(base) & MTB_MASTER_SFRWPRIV_MASK) >> MTB_MASTER_SFRWPRIV_SHIFT)
14918 #define MTB_BRD_MASTER_SFRWPRIV(base) (MTB_RD_MASTER_SFRWPRIV(base))
14919 
14920 /*! @brief Set the SFRWPRIV field to a new value. */
14921 #define MTB_WR_MASTER_SFRWPRIV(base, value) (MTB_RMW_MASTER(base, MTB_MASTER_SFRWPRIV_MASK, MTB_MASTER_SFRWPRIV(value)))
14922 #define MTB_BWR_MASTER_SFRWPRIV(base, value) (MTB_WR_MASTER_SFRWPRIV(base, value))
14923 /*@}*/
14924 
14925 /*!
14926  * @name Register MTB_MASTER, field RAMPRIV[8] (RW)
14927  *
14928  * If this field is 0, then user or privileged AHB read and write accesses to
14929  * the RAM are permitted. If this field is 1, then only privileged AHB read and
14930  * write accesses to the RAM are permitted and user accesses are RAZ/WI. The
14931  * HPROT[1] signal determines if an access is a user or privileged mode reference.
14932  */
14933 /*@{*/
14934 /*! @brief Read current value of the MTB_MASTER_RAMPRIV field. */
14935 #define MTB_RD_MASTER_RAMPRIV(base) ((MTB_MASTER_REG(base) & MTB_MASTER_RAMPRIV_MASK) >> MTB_MASTER_RAMPRIV_SHIFT)
14936 #define MTB_BRD_MASTER_RAMPRIV(base) (MTB_RD_MASTER_RAMPRIV(base))
14937 
14938 /*! @brief Set the RAMPRIV field to a new value. */
14939 #define MTB_WR_MASTER_RAMPRIV(base, value) (MTB_RMW_MASTER(base, MTB_MASTER_RAMPRIV_MASK, MTB_MASTER_RAMPRIV(value)))
14940 #define MTB_BWR_MASTER_RAMPRIV(base, value) (MTB_WR_MASTER_RAMPRIV(base, value))
14941 /*@}*/
14942 
14943 /*!
14944  * @name Register MTB_MASTER, field HALTREQ[9] (RW)
14945  *
14946  * This field is connected to the halt request signal of the trace logic,
14947  * EDBGRQ. When HALTREQ is set to 1, the EDBFGRQ is asserted if DBGEN (invasive debug
14948  * enable, one of the debug authentication interface signals) is also HIGH.
14949  * HALTREQ can be automatically set to 1 using MTB_FLOW[WATERMARK].
14950  */
14951 /*@{*/
14952 /*! @brief Read current value of the MTB_MASTER_HALTREQ field. */
14953 #define MTB_RD_MASTER_HALTREQ(base) ((MTB_MASTER_REG(base) & MTB_MASTER_HALTREQ_MASK) >> MTB_MASTER_HALTREQ_SHIFT)
14954 #define MTB_BRD_MASTER_HALTREQ(base) (MTB_RD_MASTER_HALTREQ(base))
14955 
14956 /*! @brief Set the HALTREQ field to a new value. */
14957 #define MTB_WR_MASTER_HALTREQ(base, value) (MTB_RMW_MASTER(base, MTB_MASTER_HALTREQ_MASK, MTB_MASTER_HALTREQ(value)))
14958 #define MTB_BWR_MASTER_HALTREQ(base, value) (MTB_WR_MASTER_HALTREQ(base, value))
14959 /*@}*/
14960 
14961 /*!
14962  * @name Register MTB_MASTER, field EN[31] (RW)
14963  *
14964  * When this field is 1, trace data is written into the RAM memory location
14965  * addressed by MTB_POSITION[POINTER]. The MTB_POSITION[POINTER] value auto
14966  * increments after the trace data packet is written. EN can be automatically set to 0
14967  * using the MTB_FLOW[WATERMARK] field and the MTB_FLOW[AUTOSTOP] bit. EN is
14968  * automatically set to 1 if TSTARTEN is 1 and the TSTART signal is HIGH. EN is
14969  * automatically set to 0 if TSTOPEN is 1 and the TSTOP signal is HIGH. If EN is set to 0
14970  * because MTB_FLOW[WATERMARK] is set, then it is not automatically set to 1 if
14971  * TSTARTEN is 1 and the TSTART input is HIGH. In this case, tracing can only be
14972  * restarted if MTB_FLOW[WATERMARK] or MTB_POSITION[POINTER] value is changed by
14973  * software.
14974  */
14975 /*@{*/
14976 /*! @brief Read current value of the MTB_MASTER_EN field. */
14977 #define MTB_RD_MASTER_EN(base) ((MTB_MASTER_REG(base) & MTB_MASTER_EN_MASK) >> MTB_MASTER_EN_SHIFT)
14978 #define MTB_BRD_MASTER_EN(base) (MTB_RD_MASTER_EN(base))
14979 
14980 /*! @brief Set the EN field to a new value. */
14981 #define MTB_WR_MASTER_EN(base, value) (MTB_RMW_MASTER(base, MTB_MASTER_EN_MASK, MTB_MASTER_EN(value)))
14982 #define MTB_BWR_MASTER_EN(base, value) (MTB_WR_MASTER_EN(base, value))
14983 /*@}*/
14984 
14985 /*******************************************************************************
14986  * MTB_FLOW - MTB Flow Register
14987  ******************************************************************************/
14988 
14989 /*!
14990  * @brief MTB_FLOW - MTB Flow Register (RW)
14991  *
14992  * Reset value: 0x00000000U
14993  *
14994  * The MTB_FLOW register contains the watermark address and the
14995  * autostop/autohalt control bits. If tracing is stopped using the watermark autostop feature, it
14996  * cannot be restarted until software clears the watermark autostop. This can be
14997  * achieved in one of the following ways: Changing the MTB_POSITION[POINTER]
14998  * field value to point to the beginning of the trace buffer, or Setting
14999  * MTB_FLOW[AUTOSTOP] = 0. A debug agent can use MTB_FLOW[AUTOSTOP] to fill the trace buffer
15000  * once only without halting the processor. A debug agent can use
15001  * MTB_FLOW[AUTOHALT] to fill the trace buffer once before causing the Cortex-M0+ processor to
15002  * enter the Debug state. To enter Debug state, the Cortex-M0+ processor might
15003  * have to perform additional branch type operations. Therefore, the
15004  * MTB_FLOW[WATERMARK] field must be set below the final entry in the trace buffer region.
15005  */
15006 /*!
15007  * @name Constants and macros for entire MTB_FLOW register
15008  */
15009 /*@{*/
15010 #define MTB_RD_FLOW(base)        (MTB_FLOW_REG(base))
15011 #define MTB_WR_FLOW(base, value) (MTB_FLOW_REG(base) = (value))
15012 #define MTB_RMW_FLOW(base, mask, value) (MTB_WR_FLOW(base, (MTB_RD_FLOW(base) & ~(mask)) | (value)))
15013 #define MTB_SET_FLOW(base, value) (MTB_WR_FLOW(base, MTB_RD_FLOW(base) |  (value)))
15014 #define MTB_CLR_FLOW(base, value) (MTB_WR_FLOW(base, MTB_RD_FLOW(base) & ~(value)))
15015 #define MTB_TOG_FLOW(base, value) (MTB_WR_FLOW(base, MTB_RD_FLOW(base) ^  (value)))
15016 /*@}*/
15017 
15018 /*
15019  * Constants & macros for individual MTB_FLOW bitfields
15020  */
15021 
15022 /*!
15023  * @name Register MTB_FLOW, field AUTOSTOP[0] (RW)
15024  *
15025  * If this field is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then
15026  * MTB_MASTER[EN] is automatically set to 0. This stops tracing.
15027  */
15028 /*@{*/
15029 /*! @brief Read current value of the MTB_FLOW_AUTOSTOP field. */
15030 #define MTB_RD_FLOW_AUTOSTOP(base) ((MTB_FLOW_REG(base) & MTB_FLOW_AUTOSTOP_MASK) >> MTB_FLOW_AUTOSTOP_SHIFT)
15031 #define MTB_BRD_FLOW_AUTOSTOP(base) (MTB_RD_FLOW_AUTOSTOP(base))
15032 
15033 /*! @brief Set the AUTOSTOP field to a new value. */
15034 #define MTB_WR_FLOW_AUTOSTOP(base, value) (MTB_RMW_FLOW(base, MTB_FLOW_AUTOSTOP_MASK, MTB_FLOW_AUTOSTOP(value)))
15035 #define MTB_BWR_FLOW_AUTOSTOP(base, value) (MTB_WR_FLOW_AUTOSTOP(base, value))
15036 /*@}*/
15037 
15038 /*!
15039  * @name Register MTB_FLOW, field AUTOHALT[1] (RW)
15040  *
15041  * If this field is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then
15042  * MTB_MASTER[HALTREQ] is automatically set to 1. If the DBGEN signal is HIGH, the
15043  * MTB asserts this halt request to the Cortex-M0+ processor by asserting the
15044  * EDBGRQ signal.
15045  */
15046 /*@{*/
15047 /*! @brief Read current value of the MTB_FLOW_AUTOHALT field. */
15048 #define MTB_RD_FLOW_AUTOHALT(base) ((MTB_FLOW_REG(base) & MTB_FLOW_AUTOHALT_MASK) >> MTB_FLOW_AUTOHALT_SHIFT)
15049 #define MTB_BRD_FLOW_AUTOHALT(base) (MTB_RD_FLOW_AUTOHALT(base))
15050 
15051 /*! @brief Set the AUTOHALT field to a new value. */
15052 #define MTB_WR_FLOW_AUTOHALT(base, value) (MTB_RMW_FLOW(base, MTB_FLOW_AUTOHALT_MASK, MTB_FLOW_AUTOHALT(value)))
15053 #define MTB_BWR_FLOW_AUTOHALT(base, value) (MTB_WR_FLOW_AUTOHALT(base, value))
15054 /*@}*/
15055 
15056 /*!
15057  * @name Register MTB_FLOW, field WATERMARK[31:3] (RW)
15058  *
15059  * This field contains an address in the same format as the
15060  * MTB_POSITION[POINTER] field. When MTB_POSITION[POINTER] matches the WATERMARK field value, actions
15061  * defined by the AUTOHALT and AUTOSTOP bits are performed.
15062  */
15063 /*@{*/
15064 /*! @brief Read current value of the MTB_FLOW_WATERMARK field. */
15065 #define MTB_RD_FLOW_WATERMARK(base) ((MTB_FLOW_REG(base) & MTB_FLOW_WATERMARK_MASK) >> MTB_FLOW_WATERMARK_SHIFT)
15066 #define MTB_BRD_FLOW_WATERMARK(base) (MTB_RD_FLOW_WATERMARK(base))
15067 
15068 /*! @brief Set the WATERMARK field to a new value. */
15069 #define MTB_WR_FLOW_WATERMARK(base, value) (MTB_RMW_FLOW(base, MTB_FLOW_WATERMARK_MASK, MTB_FLOW_WATERMARK(value)))
15070 #define MTB_BWR_FLOW_WATERMARK(base, value) (MTB_WR_FLOW_WATERMARK(base, value))
15071 /*@}*/
15072 
15073 /*******************************************************************************
15074  * MTB_BASE - MTB Base Register
15075  ******************************************************************************/
15076 
15077 /*!
15078  * @brief MTB_BASE - MTB Base Register (RO)
15079  *
15080  * Reset value: 0x00000000U
15081  *
15082  * The read-only MTB_BASE Register indicates where the RAM is located in the
15083  * system memory map. This register is provided to enable auto discovery of the MTB
15084  * RAM location, by a debug agent and is defined by a hardware design parameter.
15085  * For this device, the base address is defined by the expression:
15086  * MTB_BASE[BASEADDR] = 0x2000_0000 - (RAM_Size/4)
15087  */
15088 /*!
15089  * @name Constants and macros for entire MTB_BASE register
15090  */
15091 /*@{*/
15092 #define MTB_RD_BASE(base)        (MTB_BASE_REG(base))
15093 /*@}*/
15094 
15095 /*******************************************************************************
15096  * MTB_MODECTRL - Integration Mode Control Register
15097  ******************************************************************************/
15098 
15099 /*!
15100  * @brief MTB_MODECTRL - Integration Mode Control Register (RO)
15101  *
15102  * Reset value: 0x00000000U
15103  *
15104  * This register enables the device to switch from a functional mode, or default
15105  * behavior, into integration mode. It is hardwired to specific values used
15106  * during the auto-discovery process by an external debug agent.
15107  */
15108 /*!
15109  * @name Constants and macros for entire MTB_MODECTRL register
15110  */
15111 /*@{*/
15112 #define MTB_RD_MODECTRL(base)    (MTB_MODECTRL_REG(base))
15113 /*@}*/
15114 
15115 /*******************************************************************************
15116  * MTB_TAGSET - Claim TAG Set Register
15117  ******************************************************************************/
15118 
15119 /*!
15120  * @brief MTB_TAGSET - Claim TAG Set Register (RO)
15121  *
15122  * Reset value: 0x00000000U
15123  *
15124  * The Claim Tag Set Register returns the number of bits that can be set on a
15125  * read, and enables individual bits to be set on a write. It is hardwired to
15126  * specific values used during the auto-discovery process by an external debug agent.
15127  */
15128 /*!
15129  * @name Constants and macros for entire MTB_TAGSET register
15130  */
15131 /*@{*/
15132 #define MTB_RD_TAGSET(base)      (MTB_TAGSET_REG(base))
15133 /*@}*/
15134 
15135 /*******************************************************************************
15136  * MTB_TAGCLEAR - Claim TAG Clear Register
15137  ******************************************************************************/
15138 
15139 /*!
15140  * @brief MTB_TAGCLEAR - Claim TAG Clear Register (RO)
15141  *
15142  * Reset value: 0x00000000U
15143  *
15144  * The read/write Claim Tag Clear Register is used to read the claim status on
15145  * debug resources. A read indicates the claim tag status. Writing 1 to a specific
15146  * bit clears the corresponding claim tag to 0. It is hardwired to specific
15147  * values used during the auto-discovery process by an external debug agent.
15148  */
15149 /*!
15150  * @name Constants and macros for entire MTB_TAGCLEAR register
15151  */
15152 /*@{*/
15153 #define MTB_RD_TAGCLEAR(base)    (MTB_TAGCLEAR_REG(base))
15154 /*@}*/
15155 
15156 /*******************************************************************************
15157  * MTB_LOCKACCESS - Lock Access Register
15158  ******************************************************************************/
15159 
15160 /*!
15161  * @brief MTB_LOCKACCESS - Lock Access Register (RO)
15162  *
15163  * Reset value: 0x00000000U
15164  *
15165  * The Lock Access Register enables a write access to component registers. It is
15166  * hardwired to specific values used during the auto-discovery process by an
15167  * external debug agent.
15168  */
15169 /*!
15170  * @name Constants and macros for entire MTB_LOCKACCESS register
15171  */
15172 /*@{*/
15173 #define MTB_RD_LOCKACCESS(base)  (MTB_LOCKACCESS_REG(base))
15174 /*@}*/
15175 
15176 /*******************************************************************************
15177  * MTB_LOCKSTAT - Lock Status Register
15178  ******************************************************************************/
15179 
15180 /*!
15181  * @brief MTB_LOCKSTAT - Lock Status Register (RO)
15182  *
15183  * Reset value: 0x00000000U
15184  *
15185  * The Lock Status Register indicates the status of the lock control mechanism.
15186  * This register is used in conjunction with the Lock Access Register. It is
15187  * hardwired to specific values used during the auto-discovery process by an external
15188  * debug agent.
15189  */
15190 /*!
15191  * @name Constants and macros for entire MTB_LOCKSTAT register
15192  */
15193 /*@{*/
15194 #define MTB_RD_LOCKSTAT(base)    (MTB_LOCKSTAT_REG(base))
15195 /*@}*/
15196 
15197 /*******************************************************************************
15198  * MTB_AUTHSTAT - Authentication Status Register
15199  ******************************************************************************/
15200 
15201 /*!
15202  * @brief MTB_AUTHSTAT - Authentication Status Register (RO)
15203  *
15204  * Reset value: 0x00000000U
15205  *
15206  * The Authentication Status Register reports the required security level and
15207  * current status of the security enable bit pairs. Where functionality changes on
15208  * a given security level, this change must be reported in this register. It is
15209  * connected to specific signals used during the auto-discovery process by an
15210  * external debug agent. MTB_AUTHSTAT[3:2] indicates if nonsecure, noninvasive debug
15211  * is enabled or disabled, while MTB_AUTHSTAT[1:0] indicates the enabled/disabled
15212  * state of nonsecure, invasive debug. For both 2-bit fields, 0b10 indicates the
15213  * functionality is disabled and 0b11 indicates it is enabled.
15214  */
15215 /*!
15216  * @name Constants and macros for entire MTB_AUTHSTAT register
15217  */
15218 /*@{*/
15219 #define MTB_RD_AUTHSTAT(base)    (MTB_AUTHSTAT_REG(base))
15220 /*@}*/
15221 
15222 /*
15223  * Constants & macros for individual MTB_AUTHSTAT bitfields
15224  */
15225 
15226 /*!
15227  * @name Register MTB_AUTHSTAT, field BIT0[0] (RO)
15228  *
15229  * Connected to DBGEN.
15230  */
15231 /*@{*/
15232 /*! @brief Read current value of the MTB_AUTHSTAT_BIT0 field. */
15233 #define MTB_RD_AUTHSTAT_BIT0(base) ((MTB_AUTHSTAT_REG(base) & MTB_AUTHSTAT_BIT0_MASK) >> MTB_AUTHSTAT_BIT0_SHIFT)
15234 #define MTB_BRD_AUTHSTAT_BIT0(base) (MTB_RD_AUTHSTAT_BIT0(base))
15235 /*@}*/
15236 
15237 /*!
15238  * @name Register MTB_AUTHSTAT, field BIT1[1] (ROO)
15239  *
15240  * Hardwired to 1.
15241  */
15242 /*@{*/
15243 /*! @brief Read current value of the MTB_AUTHSTAT_BIT1 field. */
15244 #define MTB_RD_AUTHSTAT_BIT1(base) ((MTB_AUTHSTAT_REG(base) & MTB_AUTHSTAT_BIT1_MASK) >> MTB_AUTHSTAT_BIT1_SHIFT)
15245 #define MTB_BRD_AUTHSTAT_BIT1(base) (MTB_RD_AUTHSTAT_BIT1(base))
15246 /*@}*/
15247 
15248 /*!
15249  * @name Register MTB_AUTHSTAT, field BIT2[2] (RO)
15250  *
15251  * Connected to NIDEN or DBGEN signal.
15252  */
15253 /*@{*/
15254 /*! @brief Read current value of the MTB_AUTHSTAT_BIT2 field. */
15255 #define MTB_RD_AUTHSTAT_BIT2(base) ((MTB_AUTHSTAT_REG(base) & MTB_AUTHSTAT_BIT2_MASK) >> MTB_AUTHSTAT_BIT2_SHIFT)
15256 #define MTB_BRD_AUTHSTAT_BIT2(base) (MTB_RD_AUTHSTAT_BIT2(base))
15257 /*@}*/
15258 
15259 /*!
15260  * @name Register MTB_AUTHSTAT, field BIT3[3] (ROO)
15261  *
15262  * Hardwired to 1.
15263  */
15264 /*@{*/
15265 /*! @brief Read current value of the MTB_AUTHSTAT_BIT3 field. */
15266 #define MTB_RD_AUTHSTAT_BIT3(base) ((MTB_AUTHSTAT_REG(base) & MTB_AUTHSTAT_BIT3_MASK) >> MTB_AUTHSTAT_BIT3_SHIFT)
15267 #define MTB_BRD_AUTHSTAT_BIT3(base) (MTB_RD_AUTHSTAT_BIT3(base))
15268 /*@}*/
15269 
15270 /*******************************************************************************
15271  * MTB_DEVICEARCH - Device Architecture Register
15272  ******************************************************************************/
15273 
15274 /*!
15275  * @brief MTB_DEVICEARCH - Device Architecture Register (RO)
15276  *
15277  * Reset value: 0x47700A31U
15278  *
15279  * This register indicates the device architecture. It is hardwired to specific
15280  * values used during the auto-discovery process by an external debug agent.
15281  */
15282 /*!
15283  * @name Constants and macros for entire MTB_DEVICEARCH register
15284  */
15285 /*@{*/
15286 #define MTB_RD_DEVICEARCH(base)  (MTB_DEVICEARCH_REG(base))
15287 /*@}*/
15288 
15289 /*******************************************************************************
15290  * MTB_DEVICECFG - Device Configuration Register
15291  ******************************************************************************/
15292 
15293 /*!
15294  * @brief MTB_DEVICECFG - Device Configuration Register (RO)
15295  *
15296  * Reset value: 0x00000000U
15297  *
15298  * This register indicates the device configuration. It is hardwired to specific
15299  * values used during the auto-discovery process by an external debug agent.
15300  */
15301 /*!
15302  * @name Constants and macros for entire MTB_DEVICECFG register
15303  */
15304 /*@{*/
15305 #define MTB_RD_DEVICECFG(base)   (MTB_DEVICECFG_REG(base))
15306 /*@}*/
15307 
15308 /*******************************************************************************
15309  * MTB_DEVICETYPID - Device Type Identifier Register
15310  ******************************************************************************/
15311 
15312 /*!
15313  * @brief MTB_DEVICETYPID - Device Type Identifier Register (RO)
15314  *
15315  * Reset value: 0x00000031U
15316  *
15317  * This register indicates the device type ID. It is hardwired to specific
15318  * values used during the auto-discovery process by an external debug agent.
15319  */
15320 /*!
15321  * @name Constants and macros for entire MTB_DEVICETYPID register
15322  */
15323 /*@{*/
15324 #define MTB_RD_DEVICETYPID(base) (MTB_DEVICETYPID_REG(base))
15325 /*@}*/
15326 
15327 /*******************************************************************************
15328  * MTB_PERIPHID - Peripheral ID Register
15329  ******************************************************************************/
15330 
15331 /*!
15332  * @brief MTB_PERIPHID - Peripheral ID Register (RO)
15333  *
15334  * Reset value: 0x00000000U
15335  *
15336  * These registers indicate the peripheral IDs. They are hardwired to specific
15337  * values used during the auto-discovery process by an external debug agent.
15338  */
15339 /*!
15340  * @name Constants and macros for entire MTB_PERIPHID register
15341  */
15342 /*@{*/
15343 #define MTB_RD_PERIPHID(base, index) (MTB_PERIPHID_REG(base, index))
15344 /*@}*/
15345 
15346 /*******************************************************************************
15347  * MTB_COMPID - Component ID Register
15348  ******************************************************************************/
15349 
15350 /*!
15351  * @brief MTB_COMPID - Component ID Register (RO)
15352  *
15353  * Reset value: 0x00000000U
15354  *
15355  * These registers indicate the component IDs. They are hardwired to specific
15356  * values used during the auto-discovery process by an external debug agent.
15357  */
15358 /*!
15359  * @name Constants and macros for entire MTB_COMPID register
15360  */
15361 /*@{*/
15362 #define MTB_RD_COMPID(base, index) (MTB_COMPID_REG(base, index))
15363 /*@}*/
15364 
15365 /*
15366  * MKW40Z4 MTBDWT
15367  *
15368  * MTB data watchpoint and trace
15369  *
15370  * Registers defined in this header file:
15371  * - MTBDWT_CTRL - MTB DWT Control Register
15372  * - MTBDWT_COMP - MTB_DWT Comparator Register
15373  * - MTBDWT_MASK - MTB_DWT Comparator Mask Register
15374  * - MTBDWT_FCT - MTB_DWT Comparator Function Register 0
15375  * - MTBDWT_TBCTRL - MTB_DWT Trace Buffer Control Register
15376  * - MTBDWT_DEVICECFG - Device Configuration Register
15377  * - MTBDWT_DEVICETYPID - Device Type Identifier Register
15378  * - MTBDWT_PERIPHID - Peripheral ID Register
15379  * - MTBDWT_COMPID - Component ID Register
15380  */
15381 
15382 #define MTBDWT_INSTANCE_COUNT (1U) /*!< Number of instances of the MTBDWT module. */
15383 #define MTBDWT_IDX (0U) /*!< Instance number for MTBDWT. */
15384 
15385 /*******************************************************************************
15386  * MTBDWT_CTRL - MTB DWT Control Register
15387  ******************************************************************************/
15388 
15389 /*!
15390  * @brief MTBDWT_CTRL - MTB DWT Control Register (RO)
15391  *
15392  * Reset value: 0x2F000000U
15393  *
15394  * The MTBDWT_CTRL register provides read-only information on the watchpoint
15395  * configuration for the MTB_DWT.
15396  */
15397 /*!
15398  * @name Constants and macros for entire MTBDWT_CTRL register
15399  */
15400 /*@{*/
15401 #define MTBDWT_RD_CTRL(base)     (MTBDWT_CTRL_REG(base))
15402 /*@}*/
15403 
15404 /*
15405  * Constants & macros for individual MTBDWT_CTRL bitfields
15406  */
15407 
15408 /*!
15409  * @name Register MTBDWT_CTRL, field DWTCFGCTRL[27:0] (RO)
15410  *
15411  * This field is hardwired to 0xF00_0000, disabling all the remaining DWT
15412  * functionality. The specific fields and their state are: MTBDWT_CTRL[27] = NOTRCPKT =
15413  * 1, trace sample and exception trace is not supported MTBDWT_CTRL[26] =
15414  * NOEXTTRIG = 1, external match signals are not supported MTBDWT_CTRL[25] = NOCYCCNT =
15415  * 1, cycle counter is not supported MTBDWT_CTRL[24] = NOPRFCNT = 1, profiling
15416  * counters are not supported MTBDWT_CTRL[22] = CYCEBTENA = 0, no POSTCNT
15417  * underflow packets generated MTBDWT_CTRL[21] = FOLDEVTENA = 0, no folded instruction
15418  * counter overflow events MTBDWT_CTRL[20] = LSUEVTENA = 0, no LSU counter overflow
15419  * events MTBDWT_CTRL[19] = SLEEPEVTENA = 0, no sleep counter overflow events
15420  * MTBDWT_CTRL[18] = EXCEVTENA = 0, no exception overhead counter events
15421  * MTBDWT_CTRL[17] = CPIEVTENA = 0, no CPI counter overflow events MTBDWT_CTRL[16] =
15422  * EXCTRCENA = 0, generation of exception trace disabled MTBDWT_CTRL[12] = PCSAMPLENA =
15423  * 0, no periodic PC sample packets generated MTBDWT_CTRL[11:10] = SYNCTAP = 0,
15424  * no synchronization packets MTBDWT_CTRL[9] = CYCTAP = 0, cycle counter is not
15425  * supported MTBDWT_CTRL[8:5] = POSTINIT = 0, cycle counter is not supported
15426  * MTBDWT_CTRL[4:1] = POSTPRESET = 0, cycle counter is not supported MTBDWT_CTRL[0] =
15427  * CYCCNTENA = 0, cycle counter is not supported
15428  */
15429 /*@{*/
15430 /*! @brief Read current value of the MTBDWT_CTRL_DWTCFGCTRL field. */
15431 #define MTBDWT_RD_CTRL_DWTCFGCTRL(base) ((MTBDWT_CTRL_REG(base) & MTBDWT_CTRL_DWTCFGCTRL_MASK) >> MTBDWT_CTRL_DWTCFGCTRL_SHIFT)
15432 #define MTBDWT_BRD_CTRL_DWTCFGCTRL(base) (MTBDWT_RD_CTRL_DWTCFGCTRL(base))
15433 /*@}*/
15434 
15435 /*!
15436  * @name Register MTBDWT_CTRL, field NUMCMP[31:28] (RO)
15437  *
15438  * The MTB_DWT implements two comparators.
15439  */
15440 /*@{*/
15441 /*! @brief Read current value of the MTBDWT_CTRL_NUMCMP field. */
15442 #define MTBDWT_RD_CTRL_NUMCMP(base) ((MTBDWT_CTRL_REG(base) & MTBDWT_CTRL_NUMCMP_MASK) >> MTBDWT_CTRL_NUMCMP_SHIFT)
15443 #define MTBDWT_BRD_CTRL_NUMCMP(base) (MTBDWT_RD_CTRL_NUMCMP(base))
15444 /*@}*/
15445 
15446 /*******************************************************************************
15447  * MTBDWT_COMP - MTB_DWT Comparator Register
15448  ******************************************************************************/
15449 
15450 /*!
15451  * @brief MTBDWT_COMP - MTB_DWT Comparator Register (RW)
15452  *
15453  * Reset value: 0x00000000U
15454  *
15455  * The MTBDWT_COMPn registers provide the reference value for comparator n.
15456  */
15457 /*!
15458  * @name Constants and macros for entire MTBDWT_COMP register
15459  */
15460 /*@{*/
15461 #define MTBDWT_RD_COMP(base, index) (MTBDWT_COMP_REG(base, index))
15462 #define MTBDWT_WR_COMP(base, index, value) (MTBDWT_COMP_REG(base, index) = (value))
15463 #define MTBDWT_RMW_COMP(base, index, mask, value) (MTBDWT_WR_COMP(base, index, (MTBDWT_RD_COMP(base, index) & ~(mask)) | (value)))
15464 #define MTBDWT_SET_COMP(base, index, value) (MTBDWT_WR_COMP(base, index, MTBDWT_RD_COMP(base, index) |  (value)))
15465 #define MTBDWT_CLR_COMP(base, index, value) (MTBDWT_WR_COMP(base, index, MTBDWT_RD_COMP(base, index) & ~(value)))
15466 #define MTBDWT_TOG_COMP(base, index, value) (MTBDWT_WR_COMP(base, index, MTBDWT_RD_COMP(base, index) ^  (value)))
15467 /*@}*/
15468 
15469 /*******************************************************************************
15470  * MTBDWT_MASK - MTB_DWT Comparator Mask Register
15471  ******************************************************************************/
15472 
15473 /*!
15474  * @brief MTBDWT_MASK - MTB_DWT Comparator Mask Register (RW)
15475  *
15476  * Reset value: 0x00000000U
15477  *
15478  * The MTBDWT_MASKn registers define the size of the ignore mask applied to the
15479  * reference address for address range matching by comparator n. Note the format
15480  * of this mask field is different than the MTB_MASTER[MASK].
15481  */
15482 /*!
15483  * @name Constants and macros for entire MTBDWT_MASK register
15484  */
15485 /*@{*/
15486 #define MTBDWT_RD_MASK(base, index) (MTBDWT_MASK_REG(base, index))
15487 #define MTBDWT_WR_MASK(base, index, value) (MTBDWT_MASK_REG(base, index) = (value))
15488 #define MTBDWT_RMW_MASK(base, index, mask, value) (MTBDWT_WR_MASK(base, index, (MTBDWT_RD_MASK(base, index) & ~(mask)) | (value)))
15489 #define MTBDWT_SET_MASK(base, index, value) (MTBDWT_WR_MASK(base, index, MTBDWT_RD_MASK(base, index) |  (value)))
15490 #define MTBDWT_CLR_MASK(base, index, value) (MTBDWT_WR_MASK(base, index, MTBDWT_RD_MASK(base, index) & ~(value)))
15491 #define MTBDWT_TOG_MASK(base, index, value) (MTBDWT_WR_MASK(base, index, MTBDWT_RD_MASK(base, index) ^  (value)))
15492 /*@}*/
15493 
15494 /*
15495  * Constants & macros for individual MTBDWT_MASK bitfields
15496  */
15497 
15498 /*!
15499  * @name Register MTBDWT_MASK, field MASK[4:0] (RW)
15500  *
15501  * The value of the ignore mask, 0-31 bits, is applied to address range
15502  * matching. MASK = 0 is used to include all bits of the address in the comparison,
15503  * except if MASK = 0 and the comparator is configured to watch instruction fetch
15504  * addresses, address bit [0] is ignored by the hardware since all fetches must be at
15505  * least halfword aligned. For MASK != 0 and regardless of watch type, address
15506  * bits [x-1:0] are ignored in the address comparison. Using a mask means the
15507  * comparator matches on a range of addresses, defined by the unmasked most
15508  * significant bits of the address, bits [31:x]. The maximum MASK value is 24, producing a
15509  * 16 Mbyte mask. An attempted write of a MASK value > 24 is limited by the
15510  * MTBDWT hardware to 24. If MTBDWT_COMP0 is used as a data value comparator, then
15511  * MTBDWT_MASK0 should be programmed to zero.
15512  */
15513 /*@{*/
15514 /*! @brief Read current value of the MTBDWT_MASK_MASK field. */
15515 #define MTBDWT_RD_MASK_MASK(base, index) ((MTBDWT_MASK_REG(base, index) & MTBDWT_MASK_MASK_MASK) >> MTBDWT_MASK_MASK_SHIFT)
15516 #define MTBDWT_BRD_MASK_MASK(base, index) (MTBDWT_RD_MASK_MASK(base, index))
15517 
15518 /*! @brief Set the MASK field to a new value. */
15519 #define MTBDWT_WR_MASK_MASK(base, index, value) (MTBDWT_RMW_MASK(base, index, MTBDWT_MASK_MASK_MASK, MTBDWT_MASK_MASK(value)))
15520 #define MTBDWT_BWR_MASK_MASK(base, index, value) (MTBDWT_WR_MASK_MASK(base, index, value))
15521 /*@}*/
15522 
15523 /*******************************************************************************
15524  * MTBDWT_FCT - MTB_DWT Comparator Function Register 0
15525  ******************************************************************************/
15526 
15527 /*!
15528  * @brief MTBDWT_FCT - MTB_DWT Comparator Function Register 0 (RW)
15529  *
15530  * Reset value: 0x00000000U
15531  *
15532  * The MTBDWT_FCTn registers control the operation of comparator n.
15533  */
15534 /*!
15535  * @name Constants and macros for entire MTBDWT_FCT register
15536  */
15537 /*@{*/
15538 #define MTBDWT_RD_FCT(base, index) (MTBDWT_FCT_REG(base, index))
15539 #define MTBDWT_WR_FCT(base, index, value) (MTBDWT_FCT_REG(base, index) = (value))
15540 #define MTBDWT_RMW_FCT(base, index, mask, value) (MTBDWT_WR_FCT(base, index, (MTBDWT_RD_FCT(base, index) & ~(mask)) | (value)))
15541 #define MTBDWT_SET_FCT(base, index, value) (MTBDWT_WR_FCT(base, index, MTBDWT_RD_FCT(base, index) |  (value)))
15542 #define MTBDWT_CLR_FCT(base, index, value) (MTBDWT_WR_FCT(base, index, MTBDWT_RD_FCT(base, index) & ~(value)))
15543 #define MTBDWT_TOG_FCT(base, index, value) (MTBDWT_WR_FCT(base, index, MTBDWT_RD_FCT(base, index) ^  (value)))
15544 /*@}*/
15545 
15546 /*
15547  * Constants & macros for individual MTBDWT_FCT bitfields
15548  */
15549 
15550 /*!
15551  * @name Register MTBDWT_FCT, field FUNCTION[3:0] (RW)
15552  *
15553  * Selects the action taken on a comparator match. If MTBDWT_COMP0 is used for a
15554  * data value and MTBDWT_COMP1 for an address value, then MTBDWT_FCT1[FUNCTION]
15555  * must be set to zero. For this configuration, MTBDWT_MASK1 can be set to a
15556  * non-zero value, so the combined comparators match on a range of addresses.
15557  *
15558  * Values:
15559  * - 0b0000 - Disabled.
15560  * - 0b0100 - Instruction fetch.
15561  * - 0b0101 - Data operand read.
15562  * - 0b0110 - Data operand write.
15563  * - 0b0111 - Data operand (read + write).
15564  */
15565 /*@{*/
15566 /*! @brief Read current value of the MTBDWT_FCT_FUNCTION field. */
15567 #define MTBDWT_RD_FCT_FUNCTION(base, index) ((MTBDWT_FCT_REG(base, index) & MTBDWT_FCT_FUNCTION_MASK) >> MTBDWT_FCT_FUNCTION_SHIFT)
15568 #define MTBDWT_BRD_FCT_FUNCTION(base, index) (MTBDWT_RD_FCT_FUNCTION(base, index))
15569 
15570 /*! @brief Set the FUNCTION field to a new value. */
15571 #define MTBDWT_WR_FCT_FUNCTION(base, index, value) (MTBDWT_RMW_FCT(base, index, MTBDWT_FCT_FUNCTION_MASK, MTBDWT_FCT_FUNCTION(value)))
15572 #define MTBDWT_BWR_FCT_FUNCTION(base, index, value) (MTBDWT_WR_FCT_FUNCTION(base, index, value))
15573 /*@}*/
15574 
15575 /*!
15576  * @name Register MTBDWT_FCT, field DATAVMATCH[8] (RW)
15577  *
15578  * When this field is 1, it enables data value comparison. For this
15579  * implementation, MTBDWT_COMP0 supports address or data value comparisons; MTBDWT_COMP1 only
15580  * supports address comparisons.
15581  *
15582  * Values:
15583  * - 0b0 - Perform address comparison.
15584  * - 0b1 - Perform data value comparison.
15585  */
15586 /*@{*/
15587 /*! @brief Read current value of the MTBDWT_FCT_DATAVMATCH field. */
15588 #define MTBDWT_RD_FCT_DATAVMATCH(base, index) ((MTBDWT_FCT_REG(base, index) & MTBDWT_FCT_DATAVMATCH_MASK) >> MTBDWT_FCT_DATAVMATCH_SHIFT)
15589 #define MTBDWT_BRD_FCT_DATAVMATCH(base, index) (MTBDWT_RD_FCT_DATAVMATCH(base, index))
15590 
15591 /*! @brief Set the DATAVMATCH field to a new value. */
15592 #define MTBDWT_WR_FCT_DATAVMATCH(base, index, value) (MTBDWT_RMW_FCT(base, index, MTBDWT_FCT_DATAVMATCH_MASK, MTBDWT_FCT_DATAVMATCH(value)))
15593 #define MTBDWT_BWR_FCT_DATAVMATCH(base, index, value) (MTBDWT_WR_FCT_DATAVMATCH(base, index, value))
15594 /*@}*/
15595 
15596 /*!
15597  * @name Register MTBDWT_FCT, field DATAVSIZE[11:10] (RW)
15598  *
15599  * For data value matching, this field defines the size of the required data
15600  * comparison.
15601  *
15602  * Values:
15603  * - 0b00 - Byte.
15604  * - 0b01 - Halfword.
15605  * - 0b10 - Word.
15606  * - 0b11 - Reserved. Any attempts to use this value results in UNPREDICTABLE
15607  *     behavior.
15608  */
15609 /*@{*/
15610 /*! @brief Read current value of the MTBDWT_FCT_DATAVSIZE field. */
15611 #define MTBDWT_RD_FCT_DATAVSIZE(base, index) ((MTBDWT_FCT_REG(base, index) & MTBDWT_FCT_DATAVSIZE_MASK) >> MTBDWT_FCT_DATAVSIZE_SHIFT)
15612 #define MTBDWT_BRD_FCT_DATAVSIZE(base, index) (MTBDWT_RD_FCT_DATAVSIZE(base, index))
15613 
15614 /*! @brief Set the DATAVSIZE field to a new value. */
15615 #define MTBDWT_WR_FCT_DATAVSIZE(base, index, value) (MTBDWT_RMW_FCT(base, index, MTBDWT_FCT_DATAVSIZE_MASK, MTBDWT_FCT_DATAVSIZE(value)))
15616 #define MTBDWT_BWR_FCT_DATAVSIZE(base, index, value) (MTBDWT_WR_FCT_DATAVSIZE(base, index, value))
15617 /*@}*/
15618 
15619 /*!
15620  * @name Register MTBDWT_FCT, field DATAVADDR0[15:12] (RW)
15621  *
15622  * Since the MTB_DWT implements two comparators, the DATAVADDR0 field is
15623  * restricted to values {0,1}. When the DATAVMATCH bit is asserted, this field defines
15624  * the comparator number to use for linked address comparison. If MTBDWT_COMP0 is
15625  * used as a data watchpoint and MTBDWT_COMP1 as an address watchpoint,
15626  * DATAVADDR0 must be set.
15627  */
15628 /*@{*/
15629 /*! @brief Read current value of the MTBDWT_FCT_DATAVADDR0 field. */
15630 #define MTBDWT_RD_FCT_DATAVADDR0(base, index) ((MTBDWT_FCT_REG(base, index) & MTBDWT_FCT_DATAVADDR0_MASK) >> MTBDWT_FCT_DATAVADDR0_SHIFT)
15631 #define MTBDWT_BRD_FCT_DATAVADDR0(base, index) (MTBDWT_RD_FCT_DATAVADDR0(base, index))
15632 
15633 /*! @brief Set the DATAVADDR0 field to a new value. */
15634 #define MTBDWT_WR_FCT_DATAVADDR0(base, index, value) (MTBDWT_RMW_FCT(base, index, MTBDWT_FCT_DATAVADDR0_MASK, MTBDWT_FCT_DATAVADDR0(value)))
15635 #define MTBDWT_BWR_FCT_DATAVADDR0(base, index, value) (MTBDWT_WR_FCT_DATAVADDR0(base, index, value))
15636 /*@}*/
15637 
15638 /*!
15639  * @name Register MTBDWT_FCT, field MATCHED[24] (RO)
15640  *
15641  * If this read-only flag is asserted, it indicates the operation defined by the
15642  * FUNCTION field occurred since the last read of the register. Reading the
15643  * register clears this bit.
15644  *
15645  * Values:
15646  * - 0b0 - No match.
15647  * - 0b1 - Match occurred.
15648  */
15649 /*@{*/
15650 /*! @brief Read current value of the MTBDWT_FCT_MATCHED field. */
15651 #define MTBDWT_RD_FCT_MATCHED(base, index) ((MTBDWT_FCT_REG(base, index) & MTBDWT_FCT_MATCHED_MASK) >> MTBDWT_FCT_MATCHED_SHIFT)
15652 #define MTBDWT_BRD_FCT_MATCHED(base, index) (MTBDWT_RD_FCT_MATCHED(base, index))
15653 /*@}*/
15654 
15655 /*******************************************************************************
15656  * MTBDWT_TBCTRL - MTB_DWT Trace Buffer Control Register
15657  ******************************************************************************/
15658 
15659 /*!
15660  * @brief MTBDWT_TBCTRL - MTB_DWT Trace Buffer Control Register (RW)
15661  *
15662  * Reset value: 0x20000000U
15663  *
15664  * The MTBDWT_TBCTRL register defines how the watchpoint comparisons control the
15665  * actual trace buffer operation. Recall the MTB supports starting and stopping
15666  * the program trace based on the watchpoint comparisons signaled via TSTART and
15667  * TSTOP. The watchpoint comparison signals are enabled in the MTB's control
15668  * logic by setting the appropriate enable bits, MTB_MASTER[TSTARTEN, TSTOPEN]. In
15669  * the event of simultaneous assertion of both TSTART and TSTOP, TSTART takes
15670  * priority.
15671  */
15672 /*!
15673  * @name Constants and macros for entire MTBDWT_TBCTRL register
15674  */
15675 /*@{*/
15676 #define MTBDWT_RD_TBCTRL(base)   (MTBDWT_TBCTRL_REG(base))
15677 #define MTBDWT_WR_TBCTRL(base, value) (MTBDWT_TBCTRL_REG(base) = (value))
15678 #define MTBDWT_RMW_TBCTRL(base, mask, value) (MTBDWT_WR_TBCTRL(base, (MTBDWT_RD_TBCTRL(base) & ~(mask)) | (value)))
15679 #define MTBDWT_SET_TBCTRL(base, value) (MTBDWT_WR_TBCTRL(base, MTBDWT_RD_TBCTRL(base) |  (value)))
15680 #define MTBDWT_CLR_TBCTRL(base, value) (MTBDWT_WR_TBCTRL(base, MTBDWT_RD_TBCTRL(base) & ~(value)))
15681 #define MTBDWT_TOG_TBCTRL(base, value) (MTBDWT_WR_TBCTRL(base, MTBDWT_RD_TBCTRL(base) ^  (value)))
15682 /*@}*/
15683 
15684 /*
15685  * Constants & macros for individual MTBDWT_TBCTRL bitfields
15686  */
15687 
15688 /*!
15689  * @name Register MTBDWT_TBCTRL, field ACOMP0[0] (RW)
15690  *
15691  * When the MTBDWT_FCT0[MATCHED] is set, it indicates MTBDWT_COMP0 address
15692  * compare has triggered and the trace buffer's recording state is changed. The
15693  * assertion of MTBDWT_FCT0[MATCHED] is caused by the following conditions: Address
15694  * match in MTBDWT_COMP0 when MTBDWT_FCT0[DATAVMATCH] = 0 Data match in MTBDWT_COMP0
15695  * when MTBDWT_FCT0[DATAVMATCH, DATAVADDR0] = {1,0} Data match in MTBDWT_COMP0
15696  * and address match in MTBDWT_COMP1 when MTBDWT_FCT0[DATAVMATCH, DATAVADDR0] =
15697  * {1,1}
15698  *
15699  * Values:
15700  * - 0b0 - Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED].
15701  * - 0b1 - Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED].
15702  */
15703 /*@{*/
15704 /*! @brief Read current value of the MTBDWT_TBCTRL_ACOMP0 field. */
15705 #define MTBDWT_RD_TBCTRL_ACOMP0(base) ((MTBDWT_TBCTRL_REG(base) & MTBDWT_TBCTRL_ACOMP0_MASK) >> MTBDWT_TBCTRL_ACOMP0_SHIFT)
15706 #define MTBDWT_BRD_TBCTRL_ACOMP0(base) (MTBDWT_RD_TBCTRL_ACOMP0(base))
15707 
15708 /*! @brief Set the ACOMP0 field to a new value. */
15709 #define MTBDWT_WR_TBCTRL_ACOMP0(base, value) (MTBDWT_RMW_TBCTRL(base, MTBDWT_TBCTRL_ACOMP0_MASK, MTBDWT_TBCTRL_ACOMP0(value)))
15710 #define MTBDWT_BWR_TBCTRL_ACOMP0(base, value) (MTBDWT_WR_TBCTRL_ACOMP0(base, value))
15711 /*@}*/
15712 
15713 /*!
15714  * @name Register MTBDWT_TBCTRL, field ACOMP1[1] (RW)
15715  *
15716  * When the MTBDWT_FCT1[MATCHED] is set, it indicates MTBDWT_COMP1 address
15717  * compare has triggered and the trace buffer's recording state is changed.
15718  *
15719  * Values:
15720  * - 0b0 - Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED].
15721  * - 0b1 - Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED].
15722  */
15723 /*@{*/
15724 /*! @brief Read current value of the MTBDWT_TBCTRL_ACOMP1 field. */
15725 #define MTBDWT_RD_TBCTRL_ACOMP1(base) ((MTBDWT_TBCTRL_REG(base) & MTBDWT_TBCTRL_ACOMP1_MASK) >> MTBDWT_TBCTRL_ACOMP1_SHIFT)
15726 #define MTBDWT_BRD_TBCTRL_ACOMP1(base) (MTBDWT_RD_TBCTRL_ACOMP1(base))
15727 
15728 /*! @brief Set the ACOMP1 field to a new value. */
15729 #define MTBDWT_WR_TBCTRL_ACOMP1(base, value) (MTBDWT_RMW_TBCTRL(base, MTBDWT_TBCTRL_ACOMP1_MASK, MTBDWT_TBCTRL_ACOMP1(value)))
15730 #define MTBDWT_BWR_TBCTRL_ACOMP1(base, value) (MTBDWT_WR_TBCTRL_ACOMP1(base, value))
15731 /*@}*/
15732 
15733 /*!
15734  * @name Register MTBDWT_TBCTRL, field NUMCOMP[31:28] (RO)
15735  *
15736  * This read-only field specifies the number of comparators in the MTB_DWT. This
15737  * implementation includes two registers.
15738  */
15739 /*@{*/
15740 /*! @brief Read current value of the MTBDWT_TBCTRL_NUMCOMP field. */
15741 #define MTBDWT_RD_TBCTRL_NUMCOMP(base) ((MTBDWT_TBCTRL_REG(base) & MTBDWT_TBCTRL_NUMCOMP_MASK) >> MTBDWT_TBCTRL_NUMCOMP_SHIFT)
15742 #define MTBDWT_BRD_TBCTRL_NUMCOMP(base) (MTBDWT_RD_TBCTRL_NUMCOMP(base))
15743 /*@}*/
15744 
15745 /*******************************************************************************
15746  * MTBDWT_DEVICECFG - Device Configuration Register
15747  ******************************************************************************/
15748 
15749 /*!
15750  * @brief MTBDWT_DEVICECFG - Device Configuration Register (RO)
15751  *
15752  * Reset value: 0x00000000U
15753  *
15754  * This register indicates the device configuration. It is hardwired to specific
15755  * values used during the auto-discovery process by an external debug agent.
15756  */
15757 /*!
15758  * @name Constants and macros for entire MTBDWT_DEVICECFG register
15759  */
15760 /*@{*/
15761 #define MTBDWT_RD_DEVICECFG(base) (MTBDWT_DEVICECFG_REG(base))
15762 /*@}*/
15763 
15764 /*******************************************************************************
15765  * MTBDWT_DEVICETYPID - Device Type Identifier Register
15766  ******************************************************************************/
15767 
15768 /*!
15769  * @brief MTBDWT_DEVICETYPID - Device Type Identifier Register (RO)
15770  *
15771  * Reset value: 0x00000004U
15772  *
15773  * This register indicates the device type ID. It is hardwired to specific
15774  * values used during the auto-discovery process by an external debug agent.
15775  */
15776 /*!
15777  * @name Constants and macros for entire MTBDWT_DEVICETYPID register
15778  */
15779 /*@{*/
15780 #define MTBDWT_RD_DEVICETYPID(base) (MTBDWT_DEVICETYPID_REG(base))
15781 /*@}*/
15782 
15783 /*******************************************************************************
15784  * MTBDWT_PERIPHID - Peripheral ID Register
15785  ******************************************************************************/
15786 
15787 /*!
15788  * @brief MTBDWT_PERIPHID - Peripheral ID Register (RO)
15789  *
15790  * Reset value: 0x00000000U
15791  *
15792  * These registers indicate the peripheral IDs. They are hardwired to specific
15793  * values used during the auto-discovery process by an external debug agent.
15794  */
15795 /*!
15796  * @name Constants and macros for entire MTBDWT_PERIPHID register
15797  */
15798 /*@{*/
15799 #define MTBDWT_RD_PERIPHID(base, index) (MTBDWT_PERIPHID_REG(base, index))
15800 /*@}*/
15801 
15802 /*******************************************************************************
15803  * MTBDWT_COMPID - Component ID Register
15804  ******************************************************************************/
15805 
15806 /*!
15807  * @brief MTBDWT_COMPID - Component ID Register (RO)
15808  *
15809  * Reset value: 0x00000000U
15810  *
15811  * These registers indicate the component IDs. They are hardwired to specific
15812  * values used during the auto-discovery process by an external debug agent.
15813  */
15814 /*!
15815  * @name Constants and macros for entire MTBDWT_COMPID register
15816  */
15817 /*@{*/
15818 #define MTBDWT_RD_COMPID(base, index) (MTBDWT_COMPID_REG(base, index))
15819 /*@}*/
15820 
15821 /*
15822  * MKW40Z4 NV
15823  *
15824  * Flash configuration field
15825  *
15826  * Registers defined in this header file:
15827  * - NV_BACKKEY3 - Backdoor Comparison Key 3.
15828  * - NV_BACKKEY2 - Backdoor Comparison Key 2.
15829  * - NV_BACKKEY1 - Backdoor Comparison Key 1.
15830  * - NV_BACKKEY0 - Backdoor Comparison Key 0.
15831  * - NV_BACKKEY7 - Backdoor Comparison Key 7.
15832  * - NV_BACKKEY6 - Backdoor Comparison Key 6.
15833  * - NV_BACKKEY5 - Backdoor Comparison Key 5.
15834  * - NV_BACKKEY4 - Backdoor Comparison Key 4.
15835  * - NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
15836  * - NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
15837  * - NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
15838  * - NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
15839  * - NV_FSEC - Non-volatile Flash Security Register
15840  * - NV_FOPT - Non-volatile Flash Option Register
15841  */
15842 
15843 #define NV_INSTANCE_COUNT (1U) /*!< Number of instances of the NV module. */
15844 #define FTFA_FlashConfig_IDX (0U) /*!< Instance number for FTFA_FlashConfig. */
15845 
15846 /*******************************************************************************
15847  * NV_BACKKEY3 - Backdoor Comparison Key 3.
15848  ******************************************************************************/
15849 
15850 /*!
15851  * @brief NV_BACKKEY3 - Backdoor Comparison Key 3. (RO)
15852  *
15853  * Reset value: 0xFFU
15854  */
15855 /*!
15856  * @name Constants and macros for entire NV_BACKKEY3 register
15857  */
15858 /*@{*/
15859 #define NV_RD_BACKKEY3(base)     (NV_BACKKEY3_REG(base))
15860 /*@}*/
15861 
15862 /*******************************************************************************
15863  * NV_BACKKEY2 - Backdoor Comparison Key 2.
15864  ******************************************************************************/
15865 
15866 /*!
15867  * @brief NV_BACKKEY2 - Backdoor Comparison Key 2. (RO)
15868  *
15869  * Reset value: 0xFFU
15870  */
15871 /*!
15872  * @name Constants and macros for entire NV_BACKKEY2 register
15873  */
15874 /*@{*/
15875 #define NV_RD_BACKKEY2(base)     (NV_BACKKEY2_REG(base))
15876 /*@}*/
15877 
15878 /*******************************************************************************
15879  * NV_BACKKEY1 - Backdoor Comparison Key 1.
15880  ******************************************************************************/
15881 
15882 /*!
15883  * @brief NV_BACKKEY1 - Backdoor Comparison Key 1. (RO)
15884  *
15885  * Reset value: 0xFFU
15886  */
15887 /*!
15888  * @name Constants and macros for entire NV_BACKKEY1 register
15889  */
15890 /*@{*/
15891 #define NV_RD_BACKKEY1(base)     (NV_BACKKEY1_REG(base))
15892 /*@}*/
15893 
15894 /*******************************************************************************
15895  * NV_BACKKEY0 - Backdoor Comparison Key 0.
15896  ******************************************************************************/
15897 
15898 /*!
15899  * @brief NV_BACKKEY0 - Backdoor Comparison Key 0. (RO)
15900  *
15901  * Reset value: 0xFFU
15902  */
15903 /*!
15904  * @name Constants and macros for entire NV_BACKKEY0 register
15905  */
15906 /*@{*/
15907 #define NV_RD_BACKKEY0(base)     (NV_BACKKEY0_REG(base))
15908 /*@}*/
15909 
15910 /*******************************************************************************
15911  * NV_BACKKEY7 - Backdoor Comparison Key 7.
15912  ******************************************************************************/
15913 
15914 /*!
15915  * @brief NV_BACKKEY7 - Backdoor Comparison Key 7. (RO)
15916  *
15917  * Reset value: 0xFFU
15918  */
15919 /*!
15920  * @name Constants and macros for entire NV_BACKKEY7 register
15921  */
15922 /*@{*/
15923 #define NV_RD_BACKKEY7(base)     (NV_BACKKEY7_REG(base))
15924 /*@}*/
15925 
15926 /*******************************************************************************
15927  * NV_BACKKEY6 - Backdoor Comparison Key 6.
15928  ******************************************************************************/
15929 
15930 /*!
15931  * @brief NV_BACKKEY6 - Backdoor Comparison Key 6. (RO)
15932  *
15933  * Reset value: 0xFFU
15934  */
15935 /*!
15936  * @name Constants and macros for entire NV_BACKKEY6 register
15937  */
15938 /*@{*/
15939 #define NV_RD_BACKKEY6(base)     (NV_BACKKEY6_REG(base))
15940 /*@}*/
15941 
15942 /*******************************************************************************
15943  * NV_BACKKEY5 - Backdoor Comparison Key 5.
15944  ******************************************************************************/
15945 
15946 /*!
15947  * @brief NV_BACKKEY5 - Backdoor Comparison Key 5. (RO)
15948  *
15949  * Reset value: 0xFFU
15950  */
15951 /*!
15952  * @name Constants and macros for entire NV_BACKKEY5 register
15953  */
15954 /*@{*/
15955 #define NV_RD_BACKKEY5(base)     (NV_BACKKEY5_REG(base))
15956 /*@}*/
15957 
15958 /*******************************************************************************
15959  * NV_BACKKEY4 - Backdoor Comparison Key 4.
15960  ******************************************************************************/
15961 
15962 /*!
15963  * @brief NV_BACKKEY4 - Backdoor Comparison Key 4. (RO)
15964  *
15965  * Reset value: 0xFFU
15966  */
15967 /*!
15968  * @name Constants and macros for entire NV_BACKKEY4 register
15969  */
15970 /*@{*/
15971 #define NV_RD_BACKKEY4(base)     (NV_BACKKEY4_REG(base))
15972 /*@}*/
15973 
15974 /*******************************************************************************
15975  * NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register
15976  ******************************************************************************/
15977 
15978 /*!
15979  * @brief NV_FPROT3 - Non-volatile P-Flash Protection 1 - Low Register (RO)
15980  *
15981  * Reset value: 0xFFU
15982  */
15983 /*!
15984  * @name Constants and macros for entire NV_FPROT3 register
15985  */
15986 /*@{*/
15987 #define NV_RD_FPROT3(base)       (NV_FPROT3_REG(base))
15988 /*@}*/
15989 
15990 /*******************************************************************************
15991  * NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register
15992  ******************************************************************************/
15993 
15994 /*!
15995  * @brief NV_FPROT2 - Non-volatile P-Flash Protection 1 - High Register (RO)
15996  *
15997  * Reset value: 0xFFU
15998  */
15999 /*!
16000  * @name Constants and macros for entire NV_FPROT2 register
16001  */
16002 /*@{*/
16003 #define NV_RD_FPROT2(base)       (NV_FPROT2_REG(base))
16004 /*@}*/
16005 
16006 /*******************************************************************************
16007  * NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register
16008  ******************************************************************************/
16009 
16010 /*!
16011  * @brief NV_FPROT1 - Non-volatile P-Flash Protection 0 - Low Register (RO)
16012  *
16013  * Reset value: 0xFFU
16014  */
16015 /*!
16016  * @name Constants and macros for entire NV_FPROT1 register
16017  */
16018 /*@{*/
16019 #define NV_RD_FPROT1(base)       (NV_FPROT1_REG(base))
16020 /*@}*/
16021 
16022 /*******************************************************************************
16023  * NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register
16024  ******************************************************************************/
16025 
16026 /*!
16027  * @brief NV_FPROT0 - Non-volatile P-Flash Protection 0 - High Register (RO)
16028  *
16029  * Reset value: 0xFFU
16030  */
16031 /*!
16032  * @name Constants and macros for entire NV_FPROT0 register
16033  */
16034 /*@{*/
16035 #define NV_RD_FPROT0(base)       (NV_FPROT0_REG(base))
16036 /*@}*/
16037 
16038 /*******************************************************************************
16039  * NV_FSEC - Non-volatile Flash Security Register
16040  ******************************************************************************/
16041 
16042 /*!
16043  * @brief NV_FSEC - Non-volatile Flash Security Register (RO)
16044  *
16045  * Reset value: 0xFFU
16046  *
16047  * Allows the user to customize the operation of the MCU at boot time
16048  */
16049 /*!
16050  * @name Constants and macros for entire NV_FSEC register
16051  */
16052 /*@{*/
16053 #define NV_RD_FSEC(base)         (NV_FSEC_REG(base))
16054 /*@}*/
16055 
16056 /*
16057  * Constants & macros for individual NV_FSEC bitfields
16058  */
16059 
16060 /*!
16061  * @name Register NV_FSEC, field SEC[1:0] (RO)
16062  *
16063  * Values:
16064  * - 0b10 - MCU security status is unsecure
16065  * - 0b11 - MCU security status is secure
16066  */
16067 /*@{*/
16068 /*! @brief Read current value of the NV_FSEC_SEC field. */
16069 #define NV_RD_FSEC_SEC(base) ((NV_FSEC_REG(base) & NV_FSEC_SEC_MASK) >> NV_FSEC_SEC_SHIFT)
16070 #define NV_BRD_FSEC_SEC(base) (NV_RD_FSEC_SEC(base))
16071 /*@}*/
16072 
16073 /*!
16074  * @name Register NV_FSEC, field FSLACC[3:2] (RO)
16075  *
16076  * Values:
16077  * - 0b10 - Freescale factory access denied
16078  * - 0b11 - Freescale factory access granted
16079  */
16080 /*@{*/
16081 /*! @brief Read current value of the NV_FSEC_FSLACC field. */
16082 #define NV_RD_FSEC_FSLACC(base) ((NV_FSEC_REG(base) & NV_FSEC_FSLACC_MASK) >> NV_FSEC_FSLACC_SHIFT)
16083 #define NV_BRD_FSEC_FSLACC(base) (NV_RD_FSEC_FSLACC(base))
16084 /*@}*/
16085 
16086 /*!
16087  * @name Register NV_FSEC, field MEEN[5:4] (RO)
16088  *
16089  * Values:
16090  * - 0b10 - Mass erase is disabled
16091  * - 0b11 - Mass erase is enabled
16092  */
16093 /*@{*/
16094 /*! @brief Read current value of the NV_FSEC_MEEN field. */
16095 #define NV_RD_FSEC_MEEN(base) ((NV_FSEC_REG(base) & NV_FSEC_MEEN_MASK) >> NV_FSEC_MEEN_SHIFT)
16096 #define NV_BRD_FSEC_MEEN(base) (NV_RD_FSEC_MEEN(base))
16097 /*@}*/
16098 
16099 /*!
16100  * @name Register NV_FSEC, field KEYEN[7:6] (RO)
16101  *
16102  * Values:
16103  * - 0b10 - Backdoor key access enabled
16104  * - 0b11 - Backdoor key access disabled
16105  */
16106 /*@{*/
16107 /*! @brief Read current value of the NV_FSEC_KEYEN field. */
16108 #define NV_RD_FSEC_KEYEN(base) ((NV_FSEC_REG(base) & NV_FSEC_KEYEN_MASK) >> NV_FSEC_KEYEN_SHIFT)
16109 #define NV_BRD_FSEC_KEYEN(base) (NV_RD_FSEC_KEYEN(base))
16110 /*@}*/
16111 
16112 /*******************************************************************************
16113  * NV_FOPT - Non-volatile Flash Option Register
16114  ******************************************************************************/
16115 
16116 /*!
16117  * @brief NV_FOPT - Non-volatile Flash Option Register (RO)
16118  *
16119  * Reset value: 0xFFU
16120  */
16121 /*!
16122  * @name Constants and macros for entire NV_FOPT register
16123  */
16124 /*@{*/
16125 #define NV_RD_FOPT(base)         (NV_FOPT_REG(base))
16126 /*@}*/
16127 
16128 /*
16129  * Constants & macros for individual NV_FOPT bitfields
16130  */
16131 
16132 /*!
16133  * @name Register NV_FOPT, field LPBOOT0[0] (RO)
16134  *
16135  * Values:
16136  * - 0b0 - Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when
16137  *     LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1.
16138  * - 0b1 - Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when
16139  *     LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1.
16140  */
16141 /*@{*/
16142 /*! @brief Read current value of the NV_FOPT_LPBOOT0 field. */
16143 #define NV_RD_FOPT_LPBOOT0(base) ((NV_FOPT_REG(base) & NV_FOPT_LPBOOT0_MASK) >> NV_FOPT_LPBOOT0_SHIFT)
16144 #define NV_BRD_FOPT_LPBOOT0(base) (NV_RD_FOPT_LPBOOT0(base))
16145 /*@}*/
16146 
16147 /*!
16148  * @name Register NV_FOPT, field NMI_DIS[2] (RO)
16149  *
16150  * Values:
16151  * - 0b0 - NMI interrupts are always blocked
16152  * - 0b1 - NMI_b pin/interrupts reset default to enabled
16153  */
16154 /*@{*/
16155 /*! @brief Read current value of the NV_FOPT_NMI_DIS field. */
16156 #define NV_RD_FOPT_NMI_DIS(base) ((NV_FOPT_REG(base) & NV_FOPT_NMI_DIS_MASK) >> NV_FOPT_NMI_DIS_SHIFT)
16157 #define NV_BRD_FOPT_NMI_DIS(base) (NV_RD_FOPT_NMI_DIS(base))
16158 /*@}*/
16159 
16160 /*!
16161  * @name Register NV_FOPT, field RESET_PIN_CFG[3] (RO)
16162  *
16163  * Values:
16164  * - 0b0 - RESET pin is disabled following a POR and cannot be enabled as reset
16165  *     function
16166  * - 0b1 - RESET_b pin is dedicated
16167  */
16168 /*@{*/
16169 /*! @brief Read current value of the NV_FOPT_RESET_PIN_CFG field. */
16170 #define NV_RD_FOPT_RESET_PIN_CFG(base) ((NV_FOPT_REG(base) & NV_FOPT_RESET_PIN_CFG_MASK) >> NV_FOPT_RESET_PIN_CFG_SHIFT)
16171 #define NV_BRD_FOPT_RESET_PIN_CFG(base) (NV_RD_FOPT_RESET_PIN_CFG(base))
16172 /*@}*/
16173 
16174 /*!
16175  * @name Register NV_FOPT, field LPBOOT1[4] (RO)
16176  *
16177  * Values:
16178  * - 0b0 - Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when
16179  *     LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1.
16180  * - 0b1 - Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when
16181  *     LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1.
16182  */
16183 /*@{*/
16184 /*! @brief Read current value of the NV_FOPT_LPBOOT1 field. */
16185 #define NV_RD_FOPT_LPBOOT1(base) ((NV_FOPT_REG(base) & NV_FOPT_LPBOOT1_MASK) >> NV_FOPT_LPBOOT1_SHIFT)
16186 #define NV_BRD_FOPT_LPBOOT1(base) (NV_RD_FOPT_LPBOOT1(base))
16187 /*@}*/
16188 
16189 /*!
16190  * @name Register NV_FOPT, field FAST_INIT[5] (RO)
16191  *
16192  * Values:
16193  * - 0b0 - Slower initialization
16194  * - 0b1 - Fast Initialization
16195  */
16196 /*@{*/
16197 /*! @brief Read current value of the NV_FOPT_FAST_INIT field. */
16198 #define NV_RD_FOPT_FAST_INIT(base) ((NV_FOPT_REG(base) & NV_FOPT_FAST_INIT_MASK) >> NV_FOPT_FAST_INIT_SHIFT)
16199 #define NV_BRD_FOPT_FAST_INIT(base) (NV_RD_FOPT_FAST_INIT(base))
16200 /*@}*/
16201 
16202 /*
16203  * MKW40Z4 PIT
16204  *
16205  * Periodic Interrupt Timer
16206  *
16207  * Registers defined in this header file:
16208  * - PIT_MCR - PIT Module Control Register
16209  * - PIT_LTMR64H - PIT Upper Lifetime Timer Register
16210  * - PIT_LTMR64L - PIT Lower Lifetime Timer Register
16211  * - PIT_LDVAL - Timer Load Value Register
16212  * - PIT_CVAL - Current Timer Value Register
16213  * - PIT_TCTRL - Timer Control Register
16214  * - PIT_TFLG - Timer Flag Register
16215  */
16216 
16217 #define PIT_INSTANCE_COUNT (1U) /*!< Number of instances of the PIT module. */
16218 #define PIT_IDX (0U) /*!< Instance number for PIT. */
16219 
16220 /*******************************************************************************
16221  * PIT_MCR - PIT Module Control Register
16222  ******************************************************************************/
16223 
16224 /*!
16225  * @brief PIT_MCR - PIT Module Control Register (RW)
16226  *
16227  * Reset value: 0x00000006U
16228  *
16229  * This register enables or disables the PIT timer clocks and controls the
16230  * timers when the PIT enters the Debug mode. The clock gating function of the MDIS
16231  * bit is described in more detail in the integraton guide. Access: User read/write
16232  */
16233 /*!
16234  * @name Constants and macros for entire PIT_MCR register
16235  */
16236 /*@{*/
16237 #define PIT_RD_MCR(base)         (PIT_MCR_REG(base))
16238 #define PIT_WR_MCR(base, value)  (PIT_MCR_REG(base) = (value))
16239 #define PIT_RMW_MCR(base, mask, value) (PIT_WR_MCR(base, (PIT_RD_MCR(base) & ~(mask)) | (value)))
16240 #define PIT_SET_MCR(base, value) (BME_OR32(&PIT_MCR_REG(base), (uint32_t)(value)))
16241 #define PIT_CLR_MCR(base, value) (BME_AND32(&PIT_MCR_REG(base), (uint32_t)(~(value))))
16242 #define PIT_TOG_MCR(base, value) (BME_XOR32(&PIT_MCR_REG(base), (uint32_t)(value)))
16243 /*@}*/
16244 
16245 /*
16246  * Constants & macros for individual PIT_MCR bitfields
16247  */
16248 
16249 /*!
16250  * @name Register PIT_MCR, field FRZ[0] (RW)
16251  *
16252  * Allows the timers to be stopped when the device enters the Debug mode.
16253  *
16254  * Values:
16255  * - 0b0 - Timers continue to run in Debug mode.
16256  * - 0b1 - Timers are stopped in Debug mode.
16257  */
16258 /*@{*/
16259 /*! @brief Read current value of the PIT_MCR_FRZ field. */
16260 #define PIT_RD_MCR_FRZ(base) ((PIT_MCR_REG(base) & PIT_MCR_FRZ_MASK) >> PIT_MCR_FRZ_SHIFT)
16261 #define PIT_BRD_MCR_FRZ(base) (BME_UBFX32(&PIT_MCR_REG(base), PIT_MCR_FRZ_SHIFT, PIT_MCR_FRZ_WIDTH))
16262 
16263 /*! @brief Set the FRZ field to a new value. */
16264 #define PIT_WR_MCR_FRZ(base, value) (PIT_RMW_MCR(base, PIT_MCR_FRZ_MASK, PIT_MCR_FRZ(value)))
16265 #define PIT_BWR_MCR_FRZ(base, value) (BME_BFI32(&PIT_MCR_REG(base), ((uint32_t)(value) << PIT_MCR_FRZ_SHIFT), PIT_MCR_FRZ_SHIFT, PIT_MCR_FRZ_WIDTH))
16266 /*@}*/
16267 
16268 /*!
16269  * @name Register PIT_MCR, field MDIS[1] (RW)
16270  *
16271  * Disables the standard timers. This field must be enabled before any other
16272  * setup is done.
16273  *
16274  * Values:
16275  * - 0b0 - Clock for standard PIT timers is enabled.
16276  * - 0b1 - Clock for standard PIT timers is disabled.
16277  */
16278 /*@{*/
16279 /*! @brief Read current value of the PIT_MCR_MDIS field. */
16280 #define PIT_RD_MCR_MDIS(base) ((PIT_MCR_REG(base) & PIT_MCR_MDIS_MASK) >> PIT_MCR_MDIS_SHIFT)
16281 #define PIT_BRD_MCR_MDIS(base) (BME_UBFX32(&PIT_MCR_REG(base), PIT_MCR_MDIS_SHIFT, PIT_MCR_MDIS_WIDTH))
16282 
16283 /*! @brief Set the MDIS field to a new value. */
16284 #define PIT_WR_MCR_MDIS(base, value) (PIT_RMW_MCR(base, PIT_MCR_MDIS_MASK, PIT_MCR_MDIS(value)))
16285 #define PIT_BWR_MCR_MDIS(base, value) (BME_BFI32(&PIT_MCR_REG(base), ((uint32_t)(value) << PIT_MCR_MDIS_SHIFT), PIT_MCR_MDIS_SHIFT, PIT_MCR_MDIS_WIDTH))
16286 /*@}*/
16287 
16288 /*******************************************************************************
16289  * PIT_LTMR64H - PIT Upper Lifetime Timer Register
16290  ******************************************************************************/
16291 
16292 /*!
16293  * @brief PIT_LTMR64H - PIT Upper Lifetime Timer Register (RO)
16294  *
16295  * Reset value: 0x00000000U
16296  *
16297  * This register is intended for applications that chain timer 0 and timer 1 to
16298  * build a 64-bit lifetimer. Access: User read only
16299  */
16300 /*!
16301  * @name Constants and macros for entire PIT_LTMR64H register
16302  */
16303 /*@{*/
16304 #define PIT_RD_LTMR64H(base)     (PIT_LTMR64H_REG(base))
16305 /*@}*/
16306 
16307 /*******************************************************************************
16308  * PIT_LTMR64L - PIT Lower Lifetime Timer Register
16309  ******************************************************************************/
16310 
16311 /*!
16312  * @brief PIT_LTMR64L - PIT Lower Lifetime Timer Register (RO)
16313  *
16314  * Reset value: 0x00000000U
16315  *
16316  * This register is intended for applications that chain timer 0 and timer 1 to
16317  * build a 64-bit lifetimer. To use LTMR64H and LTMR64L, timer 0 and timer 1 need
16318  * to be chained. To obtain the correct value, first read LTMR64H and then
16319  * LTMR64L. LTMR64H will have the value of CVAL1 at the time of the first access,
16320  * LTMR64L will have the value of CVAL0 at the time of the first access, therefore
16321  * the application does not need to worry about carry-over effects of the running
16322  * counter. Access: User read only
16323  */
16324 /*!
16325  * @name Constants and macros for entire PIT_LTMR64L register
16326  */
16327 /*@{*/
16328 #define PIT_RD_LTMR64L(base)     (PIT_LTMR64L_REG(base))
16329 /*@}*/
16330 
16331 /*******************************************************************************
16332  * PIT_LDVAL - Timer Load Value Register
16333  ******************************************************************************/
16334 
16335 /*!
16336  * @brief PIT_LDVAL - Timer Load Value Register (RW)
16337  *
16338  * Reset value: 0x00000000U
16339  *
16340  * These registers select the timeout period for the timer interrupts. Access:
16341  * User read/write
16342  */
16343 /*!
16344  * @name Constants and macros for entire PIT_LDVAL register
16345  */
16346 /*@{*/
16347 #define PIT_RD_LDVAL(base, index) (PIT_LDVAL_REG(base, index))
16348 #define PIT_WR_LDVAL(base, index, value) (PIT_LDVAL_REG(base, index) = (value))
16349 #define PIT_RMW_LDVAL(base, index, mask, value) (PIT_WR_LDVAL(base, index, (PIT_RD_LDVAL(base, index) & ~(mask)) | (value)))
16350 #define PIT_SET_LDVAL(base, index, value) (BME_OR32(&PIT_LDVAL_REG(base, index), (uint32_t)(value)))
16351 #define PIT_CLR_LDVAL(base, index, value) (BME_AND32(&PIT_LDVAL_REG(base, index), (uint32_t)(~(value))))
16352 #define PIT_TOG_LDVAL(base, index, value) (BME_XOR32(&PIT_LDVAL_REG(base, index), (uint32_t)(value)))
16353 /*@}*/
16354 
16355 /*******************************************************************************
16356  * PIT_CVAL - Current Timer Value Register
16357  ******************************************************************************/
16358 
16359 /*!
16360  * @brief PIT_CVAL - Current Timer Value Register (RO)
16361  *
16362  * Reset value: 0x00000000U
16363  *
16364  * These registers indicate the current timer position. Access: User read only
16365  */
16366 /*!
16367  * @name Constants and macros for entire PIT_CVAL register
16368  */
16369 /*@{*/
16370 #define PIT_RD_CVAL(base, index) (PIT_CVAL_REG(base, index))
16371 /*@}*/
16372 
16373 /*******************************************************************************
16374  * PIT_TCTRL - Timer Control Register
16375  ******************************************************************************/
16376 
16377 /*!
16378  * @brief PIT_TCTRL - Timer Control Register (RW)
16379  *
16380  * Reset value: 0x00000000U
16381  *
16382  * These registers contain the control bits for each timer. Access: User
16383  * read/write
16384  */
16385 /*!
16386  * @name Constants and macros for entire PIT_TCTRL register
16387  */
16388 /*@{*/
16389 #define PIT_RD_TCTRL(base, index) (PIT_TCTRL_REG(base, index))
16390 #define PIT_WR_TCTRL(base, index, value) (PIT_TCTRL_REG(base, index) = (value))
16391 #define PIT_RMW_TCTRL(base, index, mask, value) (PIT_WR_TCTRL(base, index, (PIT_RD_TCTRL(base, index) & ~(mask)) | (value)))
16392 #define PIT_SET_TCTRL(base, index, value) (BME_OR32(&PIT_TCTRL_REG(base, index), (uint32_t)(value)))
16393 #define PIT_CLR_TCTRL(base, index, value) (BME_AND32(&PIT_TCTRL_REG(base, index), (uint32_t)(~(value))))
16394 #define PIT_TOG_TCTRL(base, index, value) (BME_XOR32(&PIT_TCTRL_REG(base, index), (uint32_t)(value)))
16395 /*@}*/
16396 
16397 /*
16398  * Constants & macros for individual PIT_TCTRL bitfields
16399  */
16400 
16401 /*!
16402  * @name Register PIT_TCTRL, field TEN[0] (RW)
16403  *
16404  * Enables or disables the timer.
16405  *
16406  * Values:
16407  * - 0b0 - Timer n is disabled.
16408  * - 0b1 - Timer n is enabled.
16409  */
16410 /*@{*/
16411 /*! @brief Read current value of the PIT_TCTRL_TEN field. */
16412 #define PIT_RD_TCTRL_TEN(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_TEN_MASK) >> PIT_TCTRL_TEN_SHIFT)
16413 #define PIT_BRD_TCTRL_TEN(base, index) (BME_UBFX32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TEN_SHIFT, PIT_TCTRL_TEN_WIDTH))
16414 
16415 /*! @brief Set the TEN field to a new value. */
16416 #define PIT_WR_TCTRL_TEN(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_TEN_MASK, PIT_TCTRL_TEN(value)))
16417 #define PIT_BWR_TCTRL_TEN(base, index, value) (BME_BFI32(&PIT_TCTRL_REG(base, index), ((uint32_t)(value) << PIT_TCTRL_TEN_SHIFT), PIT_TCTRL_TEN_SHIFT, PIT_TCTRL_TEN_WIDTH))
16418 /*@}*/
16419 
16420 /*!
16421  * @name Register PIT_TCTRL, field TIE[1] (RW)
16422  *
16423  * When an interrupt is pending, or, TFLGn[TIF] is set, enabling the interrupt
16424  * will immediately cause an interrupt event. To avoid this, the associated
16425  * TFLGn[TIF] must be cleared first.
16426  *
16427  * Values:
16428  * - 0b0 - Interrupt requests from Timer n are disabled.
16429  * - 0b1 - Interrupt will be requested whenever TIF is set.
16430  */
16431 /*@{*/
16432 /*! @brief Read current value of the PIT_TCTRL_TIE field. */
16433 #define PIT_RD_TCTRL_TIE(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_TIE_MASK) >> PIT_TCTRL_TIE_SHIFT)
16434 #define PIT_BRD_TCTRL_TIE(base, index) (BME_UBFX32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_TIE_SHIFT, PIT_TCTRL_TIE_WIDTH))
16435 
16436 /*! @brief Set the TIE field to a new value. */
16437 #define PIT_WR_TCTRL_TIE(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_TIE_MASK, PIT_TCTRL_TIE(value)))
16438 #define PIT_BWR_TCTRL_TIE(base, index, value) (BME_BFI32(&PIT_TCTRL_REG(base, index), ((uint32_t)(value) << PIT_TCTRL_TIE_SHIFT), PIT_TCTRL_TIE_SHIFT, PIT_TCTRL_TIE_WIDTH))
16439 /*@}*/
16440 
16441 /*!
16442  * @name Register PIT_TCTRL, field CHN[2] (RW)
16443  *
16444  * When activated, Timer n-1 needs to expire before timer n can decrement by 1.
16445  * Timer 0 cannot be chained.
16446  *
16447  * Values:
16448  * - 0b0 - Timer is not chained.
16449  * - 0b1 - Timer is chained to previous timer. For example, for Channel 2, if
16450  *     this field is set, Timer 2 is chained to Timer 1.
16451  */
16452 /*@{*/
16453 /*! @brief Read current value of the PIT_TCTRL_CHN field. */
16454 #define PIT_RD_TCTRL_CHN(base, index) ((PIT_TCTRL_REG(base, index) & PIT_TCTRL_CHN_MASK) >> PIT_TCTRL_CHN_SHIFT)
16455 #define PIT_BRD_TCTRL_CHN(base, index) (BME_UBFX32(&PIT_TCTRL_REG(base, index), PIT_TCTRL_CHN_SHIFT, PIT_TCTRL_CHN_WIDTH))
16456 
16457 /*! @brief Set the CHN field to a new value. */
16458 #define PIT_WR_TCTRL_CHN(base, index, value) (PIT_RMW_TCTRL(base, index, PIT_TCTRL_CHN_MASK, PIT_TCTRL_CHN(value)))
16459 #define PIT_BWR_TCTRL_CHN(base, index, value) (BME_BFI32(&PIT_TCTRL_REG(base, index), ((uint32_t)(value) << PIT_TCTRL_CHN_SHIFT), PIT_TCTRL_CHN_SHIFT, PIT_TCTRL_CHN_WIDTH))
16460 /*@}*/
16461 
16462 /*******************************************************************************
16463  * PIT_TFLG - Timer Flag Register
16464  ******************************************************************************/
16465 
16466 /*!
16467  * @brief PIT_TFLG - Timer Flag Register (RW)
16468  *
16469  * Reset value: 0x00000000U
16470  *
16471  * These registers hold the PIT interrupt flags. Access: User read/write
16472  */
16473 /*!
16474  * @name Constants and macros for entire PIT_TFLG register
16475  */
16476 /*@{*/
16477 #define PIT_RD_TFLG(base, index) (PIT_TFLG_REG(base, index))
16478 #define PIT_WR_TFLG(base, index, value) (PIT_TFLG_REG(base, index) = (value))
16479 #define PIT_RMW_TFLG(base, index, mask, value) (PIT_WR_TFLG(base, index, (PIT_RD_TFLG(base, index) & ~(mask)) | (value)))
16480 #define PIT_SET_TFLG(base, index, value) (BME_OR32(&PIT_TFLG_REG(base, index), (uint32_t)(value)))
16481 #define PIT_CLR_TFLG(base, index, value) (BME_AND32(&PIT_TFLG_REG(base, index), (uint32_t)(~(value))))
16482 #define PIT_TOG_TFLG(base, index, value) (BME_XOR32(&PIT_TFLG_REG(base, index), (uint32_t)(value)))
16483 /*@}*/
16484 
16485 /*
16486  * Constants & macros for individual PIT_TFLG bitfields
16487  */
16488 
16489 /*!
16490  * @name Register PIT_TFLG, field TIF[0] (W1C)
16491  *
16492  * Sets to 1 at the end of the timer period. Writing 1 to this flag clears it.
16493  * Writing 0 has no effect. If enabled, or, when TCTRLn[TIE] = 1, TIF causes an
16494  * interrupt request.
16495  *
16496  * Values:
16497  * - 0b0 - Timeout has not yet occurred.
16498  * - 0b1 - Timeout has occurred.
16499  */
16500 /*@{*/
16501 /*! @brief Read current value of the PIT_TFLG_TIF field. */
16502 #define PIT_RD_TFLG_TIF(base, index) ((PIT_TFLG_REG(base, index) & PIT_TFLG_TIF_MASK) >> PIT_TFLG_TIF_SHIFT)
16503 #define PIT_BRD_TFLG_TIF(base, index) (BME_UBFX32(&PIT_TFLG_REG(base, index), PIT_TFLG_TIF_SHIFT, PIT_TFLG_TIF_WIDTH))
16504 
16505 /*! @brief Set the TIF field to a new value. */
16506 #define PIT_WR_TFLG_TIF(base, index, value) (PIT_RMW_TFLG(base, index, PIT_TFLG_TIF_MASK, PIT_TFLG_TIF(value)))
16507 #define PIT_BWR_TFLG_TIF(base, index, value) (BME_BFI32(&PIT_TFLG_REG(base, index), ((uint32_t)(value) << PIT_TFLG_TIF_SHIFT), PIT_TFLG_TIF_SHIFT, PIT_TFLG_TIF_WIDTH))
16508 /*@}*/
16509 
16510 /*
16511  * MKW40Z4 PMC
16512  *
16513  * Power Management Controller
16514  *
16515  * Registers defined in this header file:
16516  * - PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
16517  * - PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
16518  * - PMC_REGSC - Regulator Status And Control register
16519  */
16520 
16521 #define PMC_INSTANCE_COUNT (1U) /*!< Number of instances of the PMC module. */
16522 #define PMC_IDX (0U) /*!< Instance number for PMC. */
16523 
16524 /*******************************************************************************
16525  * PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register
16526  ******************************************************************************/
16527 
16528 /*!
16529  * @brief PMC_LVDSC1 - Low Voltage Detect Status And Control 1 register (RW)
16530  *
16531  * Reset value: 0x10U
16532  *
16533  * This register contains status and control bits to support the low voltage
16534  * detect function. This register should be written during the reset initialization
16535  * program to set the desired controls even if the desired settings are the same
16536  * as the reset settings. While the device is in the very low power or low
16537  * leakage modes, the LVD system is disabled regardless of LVDSC1 settings. To protect
16538  * systems that must have LVD always on, configure the Power Mode Protection
16539  * (PMPROT) register of the SMC module (SMC_PMPROT) to disallow any very low power or
16540  * low leakage modes from being enabled. See the device's data sheet for the
16541  * exact LVD trip voltages. The LVDV bits are reset solely on a POR Only event. The
16542  * register's other bits are reset on Chip Reset Not VLLS. For more information
16543  * about these reset types, refer to the Reset section details.
16544  */
16545 /*!
16546  * @name Constants and macros for entire PMC_LVDSC1 register
16547  */
16548 /*@{*/
16549 #define PMC_RD_LVDSC1(base)      (PMC_LVDSC1_REG(base))
16550 #define PMC_WR_LVDSC1(base, value) (PMC_LVDSC1_REG(base) = (value))
16551 #define PMC_RMW_LVDSC1(base, mask, value) (PMC_WR_LVDSC1(base, (PMC_RD_LVDSC1(base) & ~(mask)) | (value)))
16552 #define PMC_SET_LVDSC1(base, value) (BME_OR8(&PMC_LVDSC1_REG(base), (uint8_t)(value)))
16553 #define PMC_CLR_LVDSC1(base, value) (BME_AND8(&PMC_LVDSC1_REG(base), (uint8_t)(~(value))))
16554 #define PMC_TOG_LVDSC1(base, value) (BME_XOR8(&PMC_LVDSC1_REG(base), (uint8_t)(value)))
16555 /*@}*/
16556 
16557 /*
16558  * Constants & macros for individual PMC_LVDSC1 bitfields
16559  */
16560 
16561 /*!
16562  * @name Register PMC_LVDSC1, field LVDV[1:0] (RW)
16563  *
16564  * Selects the LVD trip point voltage (V LVD ).
16565  *
16566  * Values:
16567  * - 0b00 - Low trip point selected (V LVD = V LVDL )
16568  * - 0b01 - High trip point selected (V LVD = V LVDH )
16569  * - 0b10 - Reserved
16570  * - 0b11 - NON-CUSTOMER INFO: High trip point selected (VLVD = VLVDH). Change
16571  *     11 from reserved on 5V devices to high trip point.
16572  */
16573 /*@{*/
16574 /*! @brief Read current value of the PMC_LVDSC1_LVDV field. */
16575 #define PMC_RD_LVDSC1_LVDV(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDV_MASK) >> PMC_LVDSC1_LVDV_SHIFT)
16576 #define PMC_BRD_LVDSC1_LVDV(base) (BME_UBFX8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDV_SHIFT, PMC_LVDSC1_LVDV_WIDTH))
16577 
16578 /*! @brief Set the LVDV field to a new value. */
16579 #define PMC_WR_LVDSC1_LVDV(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDV_MASK, PMC_LVDSC1_LVDV(value)))
16580 #define PMC_BWR_LVDSC1_LVDV(base, value) (BME_BFI8(&PMC_LVDSC1_REG(base), ((uint8_t)(value) << PMC_LVDSC1_LVDV_SHIFT), PMC_LVDSC1_LVDV_SHIFT, PMC_LVDSC1_LVDV_WIDTH))
16581 /*@}*/
16582 
16583 /*!
16584  * @name Register PMC_LVDSC1, field LVDRE[4] (RW)
16585  *
16586  * This write-once bit enables LVDF events to generate a hardware reset.
16587  * Additional writes are ignored.
16588  *
16589  * Values:
16590  * - 0b0 - LVDF does not generate hardware resets
16591  * - 0b1 - Force an MCU reset when LVDF = 1
16592  */
16593 /*@{*/
16594 /*! @brief Read current value of the PMC_LVDSC1_LVDRE field. */
16595 #define PMC_RD_LVDSC1_LVDRE(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDRE_MASK) >> PMC_LVDSC1_LVDRE_SHIFT)
16596 #define PMC_BRD_LVDSC1_LVDRE(base) (BME_UBFX8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDRE_SHIFT, PMC_LVDSC1_LVDRE_WIDTH))
16597 
16598 /*! @brief Set the LVDRE field to a new value. */
16599 #define PMC_WR_LVDSC1_LVDRE(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDRE_MASK, PMC_LVDSC1_LVDRE(value)))
16600 #define PMC_BWR_LVDSC1_LVDRE(base, value) (BME_BFI8(&PMC_LVDSC1_REG(base), ((uint8_t)(value) << PMC_LVDSC1_LVDRE_SHIFT), PMC_LVDSC1_LVDRE_SHIFT, PMC_LVDSC1_LVDRE_WIDTH))
16601 /*@}*/
16602 
16603 /*!
16604  * @name Register PMC_LVDSC1, field LVDIE[5] (RW)
16605  *
16606  * Enables hardware interrupt requests for LVDF.
16607  *
16608  * Values:
16609  * - 0b0 - Hardware interrupt disabled (use polling)
16610  * - 0b1 - Request a hardware interrupt when LVDF = 1
16611  */
16612 /*@{*/
16613 /*! @brief Read current value of the PMC_LVDSC1_LVDIE field. */
16614 #define PMC_RD_LVDSC1_LVDIE(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDIE_MASK) >> PMC_LVDSC1_LVDIE_SHIFT)
16615 #define PMC_BRD_LVDSC1_LVDIE(base) (BME_UBFX8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDIE_SHIFT, PMC_LVDSC1_LVDIE_WIDTH))
16616 
16617 /*! @brief Set the LVDIE field to a new value. */
16618 #define PMC_WR_LVDSC1_LVDIE(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDIE_MASK, PMC_LVDSC1_LVDIE(value)))
16619 #define PMC_BWR_LVDSC1_LVDIE(base, value) (BME_BFI8(&PMC_LVDSC1_REG(base), ((uint8_t)(value) << PMC_LVDSC1_LVDIE_SHIFT), PMC_LVDSC1_LVDIE_SHIFT, PMC_LVDSC1_LVDIE_WIDTH))
16620 /*@}*/
16621 
16622 /*!
16623  * @name Register PMC_LVDSC1, field LVDACK[6] (WORZ)
16624  *
16625  * This write-only field is used to acknowledge low voltage detection errors.
16626  * Write 1 to clear LVDF. Reads always return 0.
16627  */
16628 /*@{*/
16629 /*! @brief Set the LVDACK field to a new value. */
16630 #define PMC_WR_LVDSC1_LVDACK(base, value) (PMC_RMW_LVDSC1(base, PMC_LVDSC1_LVDACK_MASK, PMC_LVDSC1_LVDACK(value)))
16631 #define PMC_BWR_LVDSC1_LVDACK(base, value) (BME_BFI8(&PMC_LVDSC1_REG(base), ((uint8_t)(value) << PMC_LVDSC1_LVDACK_SHIFT), PMC_LVDSC1_LVDACK_SHIFT, PMC_LVDSC1_LVDACK_WIDTH))
16632 /*@}*/
16633 
16634 /*!
16635  * @name Register PMC_LVDSC1, field LVDF[7] (RO)
16636  *
16637  * This read-only status field indicates a low-voltage detect event.
16638  *
16639  * Values:
16640  * - 0b0 - Low-voltage event not detected
16641  * - 0b1 - Low-voltage event detected
16642  */
16643 /*@{*/
16644 /*! @brief Read current value of the PMC_LVDSC1_LVDF field. */
16645 #define PMC_RD_LVDSC1_LVDF(base) ((PMC_LVDSC1_REG(base) & PMC_LVDSC1_LVDF_MASK) >> PMC_LVDSC1_LVDF_SHIFT)
16646 #define PMC_BRD_LVDSC1_LVDF(base) (BME_UBFX8(&PMC_LVDSC1_REG(base), PMC_LVDSC1_LVDF_SHIFT, PMC_LVDSC1_LVDF_WIDTH))
16647 /*@}*/
16648 
16649 /*******************************************************************************
16650  * PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register
16651  ******************************************************************************/
16652 
16653 /*!
16654  * @brief PMC_LVDSC2 - Low Voltage Detect Status And Control 2 register (RW)
16655  *
16656  * Reset value: 0x00U
16657  *
16658  * This register contains status and control bits to support the low voltage
16659  * warning function. While the device is in the very low power or low leakage modes,
16660  * the LVD system is disabled regardless of LVDSC2 settings. See the device's
16661  * data sheet for the exact LVD trip voltages. The LVW trip voltages depend on LVWV
16662  * and LVDV. LVWV is reset solely on a POR Only event. The other fields of the
16663  * register are reset on Chip Reset Not VLLS. For more information about these
16664  * reset types, refer to the Reset section details.
16665  */
16666 /*!
16667  * @name Constants and macros for entire PMC_LVDSC2 register
16668  */
16669 /*@{*/
16670 #define PMC_RD_LVDSC2(base)      (PMC_LVDSC2_REG(base))
16671 #define PMC_WR_LVDSC2(base, value) (PMC_LVDSC2_REG(base) = (value))
16672 #define PMC_RMW_LVDSC2(base, mask, value) (PMC_WR_LVDSC2(base, (PMC_RD_LVDSC2(base) & ~(mask)) | (value)))
16673 #define PMC_SET_LVDSC2(base, value) (BME_OR8(&PMC_LVDSC2_REG(base), (uint8_t)(value)))
16674 #define PMC_CLR_LVDSC2(base, value) (BME_AND8(&PMC_LVDSC2_REG(base), (uint8_t)(~(value))))
16675 #define PMC_TOG_LVDSC2(base, value) (BME_XOR8(&PMC_LVDSC2_REG(base), (uint8_t)(value)))
16676 /*@}*/
16677 
16678 /*
16679  * Constants & macros for individual PMC_LVDSC2 bitfields
16680  */
16681 
16682 /*!
16683  * @name Register PMC_LVDSC2, field LVWV[1:0] (RW)
16684  *
16685  * Selects the LVW trip point voltage (VLVW). The actual voltage for the warning
16686  * depends on LVDSC1[LVDV].
16687  *
16688  * Values:
16689  * - 0b00 - Low trip point selected (VLVW = VLVW1)
16690  * - 0b01 - Mid 1 trip point selected (VLVW = VLVW2)
16691  * - 0b10 - Mid 2 trip point selected (VLVW = VLVW3)
16692  * - 0b11 - High trip point selected (VLVW = VLVW4)
16693  */
16694 /*@{*/
16695 /*! @brief Read current value of the PMC_LVDSC2_LVWV field. */
16696 #define PMC_RD_LVDSC2_LVWV(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWV_MASK) >> PMC_LVDSC2_LVWV_SHIFT)
16697 #define PMC_BRD_LVDSC2_LVWV(base) (BME_UBFX8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWV_SHIFT, PMC_LVDSC2_LVWV_WIDTH))
16698 
16699 /*! @brief Set the LVWV field to a new value. */
16700 #define PMC_WR_LVDSC2_LVWV(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWV_MASK, PMC_LVDSC2_LVWV(value)))
16701 #define PMC_BWR_LVDSC2_LVWV(base, value) (BME_BFI8(&PMC_LVDSC2_REG(base), ((uint8_t)(value) << PMC_LVDSC2_LVWV_SHIFT), PMC_LVDSC2_LVWV_SHIFT, PMC_LVDSC2_LVWV_WIDTH))
16702 /*@}*/
16703 
16704 /*!
16705  * @name Register PMC_LVDSC2, field LVWIE[5] (RW)
16706  *
16707  * Enables hardware interrupt requests for LVWF.
16708  *
16709  * Values:
16710  * - 0b0 - Hardware interrupt disabled (use polling)
16711  * - 0b1 - Request a hardware interrupt when LVWF = 1
16712  */
16713 /*@{*/
16714 /*! @brief Read current value of the PMC_LVDSC2_LVWIE field. */
16715 #define PMC_RD_LVDSC2_LVWIE(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWIE_MASK) >> PMC_LVDSC2_LVWIE_SHIFT)
16716 #define PMC_BRD_LVDSC2_LVWIE(base) (BME_UBFX8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWIE_SHIFT, PMC_LVDSC2_LVWIE_WIDTH))
16717 
16718 /*! @brief Set the LVWIE field to a new value. */
16719 #define PMC_WR_LVDSC2_LVWIE(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWIE_MASK, PMC_LVDSC2_LVWIE(value)))
16720 #define PMC_BWR_LVDSC2_LVWIE(base, value) (BME_BFI8(&PMC_LVDSC2_REG(base), ((uint8_t)(value) << PMC_LVDSC2_LVWIE_SHIFT), PMC_LVDSC2_LVWIE_SHIFT, PMC_LVDSC2_LVWIE_WIDTH))
16721 /*@}*/
16722 
16723 /*!
16724  * @name Register PMC_LVDSC2, field LVWACK[6] (WORZ)
16725  *
16726  * This write-only field is used to acknowledge low voltage warning errors.
16727  * Write 1 to clear LVWF. Reads always return 0.
16728  */
16729 /*@{*/
16730 /*! @brief Set the LVWACK field to a new value. */
16731 #define PMC_WR_LVDSC2_LVWACK(base, value) (PMC_RMW_LVDSC2(base, PMC_LVDSC2_LVWACK_MASK, PMC_LVDSC2_LVWACK(value)))
16732 #define PMC_BWR_LVDSC2_LVWACK(base, value) (BME_BFI8(&PMC_LVDSC2_REG(base), ((uint8_t)(value) << PMC_LVDSC2_LVWACK_SHIFT), PMC_LVDSC2_LVWACK_SHIFT, PMC_LVDSC2_LVWACK_WIDTH))
16733 /*@}*/
16734 
16735 /*!
16736  * @name Register PMC_LVDSC2, field LVWF[7] (RO)
16737  *
16738  * This read-only status field indicates a low-voltage warning event. LVWF is
16739  * set when VSupply transitions below the trip point, or after reset and VSupply is
16740  * already below VLVW. LVWF may be 1 after power-on reset, therefore, to use LVW
16741  * interrupt function, before enabling LVWIE, LVWF must be cleared by writing
16742  * LVWACK first.
16743  *
16744  * Values:
16745  * - 0b0 - Low-voltage warning event not detected
16746  * - 0b1 - Low-voltage warning event detected
16747  */
16748 /*@{*/
16749 /*! @brief Read current value of the PMC_LVDSC2_LVWF field. */
16750 #define PMC_RD_LVDSC2_LVWF(base) ((PMC_LVDSC2_REG(base) & PMC_LVDSC2_LVWF_MASK) >> PMC_LVDSC2_LVWF_SHIFT)
16751 #define PMC_BRD_LVDSC2_LVWF(base) (BME_UBFX8(&PMC_LVDSC2_REG(base), PMC_LVDSC2_LVWF_SHIFT, PMC_LVDSC2_LVWF_WIDTH))
16752 /*@}*/
16753 
16754 /*******************************************************************************
16755  * PMC_REGSC - Regulator Status And Control register
16756  ******************************************************************************/
16757 
16758 /*!
16759  * @brief PMC_REGSC - Regulator Status And Control register (RW)
16760  *
16761  * Reset value: 0x04U
16762  *
16763  * The PMC contains an internal voltage regulator. The voltage regulator design
16764  * uses a bandgap reference that is also available through a buffer as input to
16765  * certain internal peripherals, such as the CMP and ADC. The internal regulator
16766  * provides a status bit (REGONS) indicating the regulator is in run regulation.
16767  * This register is reset on Chip Reset Not VLLS and by reset types that trigger
16768  * Chip Reset not VLLS. See the Reset section details for more information.
16769  */
16770 /*!
16771  * @name Constants and macros for entire PMC_REGSC register
16772  */
16773 /*@{*/
16774 #define PMC_RD_REGSC(base)       (PMC_REGSC_REG(base))
16775 #define PMC_WR_REGSC(base, value) (PMC_REGSC_REG(base) = (value))
16776 #define PMC_RMW_REGSC(base, mask, value) (PMC_WR_REGSC(base, (PMC_RD_REGSC(base) & ~(mask)) | (value)))
16777 #define PMC_SET_REGSC(base, value) (BME_OR8(&PMC_REGSC_REG(base), (uint8_t)(value)))
16778 #define PMC_CLR_REGSC(base, value) (BME_AND8(&PMC_REGSC_REG(base), (uint8_t)(~(value))))
16779 #define PMC_TOG_REGSC(base, value) (BME_XOR8(&PMC_REGSC_REG(base), (uint8_t)(value)))
16780 /*@}*/
16781 
16782 /*
16783  * Constants & macros for individual PMC_REGSC bitfields
16784  */
16785 
16786 /*!
16787  * @name Register PMC_REGSC, field BGBE[0] (RW)
16788  *
16789  * Enables the bandgap buffer.
16790  *
16791  * Values:
16792  * - 0b0 - Bandgap buffer not enabled
16793  * - 0b1 - Bandgap buffer enabled
16794  */
16795 /*@{*/
16796 /*! @brief Read current value of the PMC_REGSC_BGBE field. */
16797 #define PMC_RD_REGSC_BGBE(base) ((PMC_REGSC_REG(base) & PMC_REGSC_BGBE_MASK) >> PMC_REGSC_BGBE_SHIFT)
16798 #define PMC_BRD_REGSC_BGBE(base) (BME_UBFX8(&PMC_REGSC_REG(base), PMC_REGSC_BGBE_SHIFT, PMC_REGSC_BGBE_WIDTH))
16799 
16800 /*! @brief Set the BGBE field to a new value. */
16801 #define PMC_WR_REGSC_BGBE(base, value) (PMC_RMW_REGSC(base, (PMC_REGSC_BGBE_MASK | PMC_REGSC_ACKISO_MASK), PMC_REGSC_BGBE(value)))
16802 #define PMC_BWR_REGSC_BGBE(base, value) (BME_BFI8(&PMC_REGSC_REG(base), ((uint8_t)(value) << PMC_REGSC_BGBE_SHIFT), PMC_REGSC_BGBE_SHIFT, PMC_REGSC_BGBE_WIDTH))
16803 /*@}*/
16804 
16805 /*!
16806  * @name Register PMC_REGSC, field REGONS[2] (RO)
16807  *
16808  * This read-only field provides the current status of the internal voltage
16809  * regulator.
16810  *
16811  * Values:
16812  * - 0b0 - Regulator is in stop regulation or in transition to/from it
16813  * - 0b1 - Regulator is in run regulation
16814  */
16815 /*@{*/
16816 /*! @brief Read current value of the PMC_REGSC_REGONS field. */
16817 #define PMC_RD_REGSC_REGONS(base) ((PMC_REGSC_REG(base) & PMC_REGSC_REGONS_MASK) >> PMC_REGSC_REGONS_SHIFT)
16818 #define PMC_BRD_REGSC_REGONS(base) (BME_UBFX8(&PMC_REGSC_REG(base), PMC_REGSC_REGONS_SHIFT, PMC_REGSC_REGONS_WIDTH))
16819 /*@}*/
16820 
16821 /*!
16822  * @name Register PMC_REGSC, field ACKISO[3] (W1C)
16823  *
16824  * Reading this field indicates whether certain peripherals and the I/O pads are
16825  * in a latched state as a result of having been in a VLLS mode. Writing 1 to
16826  * this field when it is set releases the I/O pads and certain peripherals to their
16827  * normal run mode state. After recovering from a VLLS mode, user should restore
16828  * chip configuration before clearing ACKISO. In particular, pin configuration
16829  * for enabled LLWU wakeup pins should be restored to avoid any LLWU flag from
16830  * being falsely set when ACKISO is cleared.
16831  *
16832  * Values:
16833  * - 0b0 - Peripherals and I/O pads are in normal run state.
16834  * - 0b1 - Certain peripherals and I/O pads are in an isolated and latched state.
16835  */
16836 /*@{*/
16837 /*! @brief Read current value of the PMC_REGSC_ACKISO field. */
16838 #define PMC_RD_REGSC_ACKISO(base) ((PMC_REGSC_REG(base) & PMC_REGSC_ACKISO_MASK) >> PMC_REGSC_ACKISO_SHIFT)
16839 #define PMC_BRD_REGSC_ACKISO(base) (BME_UBFX8(&PMC_REGSC_REG(base), PMC_REGSC_ACKISO_SHIFT, PMC_REGSC_ACKISO_WIDTH))
16840 
16841 /*! @brief Set the ACKISO field to a new value. */
16842 #define PMC_WR_REGSC_ACKISO(base, value) (PMC_RMW_REGSC(base, PMC_REGSC_ACKISO_MASK, PMC_REGSC_ACKISO(value)))
16843 #define PMC_BWR_REGSC_ACKISO(base, value) (BME_BFI8(&PMC_REGSC_REG(base), ((uint8_t)(value) << PMC_REGSC_ACKISO_SHIFT), PMC_REGSC_ACKISO_SHIFT, PMC_REGSC_ACKISO_WIDTH))
16844 /*@}*/
16845 
16846 /*!
16847  * @name Register PMC_REGSC, field VLPO[6] (RW)
16848  *
16849  * When used in conjunction with BGEN, this bit allows additional clock sources
16850  * and higher frequency operation (at the cost of higher power) to be selected
16851  * during VLPx modes.
16852  *
16853  * Values:
16854  * - 0b0 - Operating frequencies and MCG clocking modes are restricted during
16855  *     VLPx modes as listed in the Power Management chapter.
16856  * - 0b1 - If BGEN is also set, operating frequencies and MCG clocking modes are
16857  *     unrestricted during VLPx modes. Note that flash access frequency is still
16858  *     restricted however.
16859  */
16860 /*@{*/
16861 /*! @brief Read current value of the PMC_REGSC_VLPO field. */
16862 #define PMC_RD_REGSC_VLPO(base) ((PMC_REGSC_REG(base) & PMC_REGSC_VLPO_MASK) >> PMC_REGSC_VLPO_SHIFT)
16863 #define PMC_BRD_REGSC_VLPO(base) (BME_UBFX8(&PMC_REGSC_REG(base), PMC_REGSC_VLPO_SHIFT, PMC_REGSC_VLPO_WIDTH))
16864 
16865 /*! @brief Set the VLPO field to a new value. */
16866 #define PMC_WR_REGSC_VLPO(base, value) (PMC_RMW_REGSC(base, (PMC_REGSC_VLPO_MASK | PMC_REGSC_ACKISO_MASK), PMC_REGSC_VLPO(value)))
16867 #define PMC_BWR_REGSC_VLPO(base, value) (BME_BFI8(&PMC_REGSC_REG(base), ((uint8_t)(value) << PMC_REGSC_VLPO_SHIFT), PMC_REGSC_VLPO_SHIFT, PMC_REGSC_VLPO_WIDTH))
16868 /*@}*/
16869 
16870 /*
16871  * MKW40Z4 PORT
16872  *
16873  * Pin Control and Interrupts
16874  *
16875  * Registers defined in this header file:
16876  * - PORT_PCR - Pin Control Register n
16877  * - PORT_GPCLR - Global Pin Control Low Register
16878  * - PORT_GPCHR - Global Pin Control High Register
16879  * - PORT_ISFR - Interrupt Status Flag Register
16880  */
16881 
16882 #define PORT_INSTANCE_COUNT (3U) /*!< Number of instances of the PORT module. */
16883 #define PORTA_IDX (0U) /*!< Instance number for PORTA. */
16884 #define PORTB_IDX (1U) /*!< Instance number for PORTB. */
16885 #define PORTC_IDX (2U) /*!< Instance number for PORTC. */
16886 
16887 /*******************************************************************************
16888  * PORT_PCR - Pin Control Register n
16889  ******************************************************************************/
16890 
16891 /*!
16892  * @brief PORT_PCR - Pin Control Register n (RW)
16893  *
16894  * Reset value: 0x00000706U
16895  *
16896  * See the Signal Multiplexing and Pin Assignment chapter for the reset value of
16897  * this device. See the GPIO Configuration section for details on the available
16898  * functions for each pin. Do not modify pin configuration registers associated
16899  * with pins not available in your selected package. All unbonded pins not
16900  * available in your package will default to DISABLE state for lowest power consumption.
16901  */
16902 /*!
16903  * @name Constants and macros for entire PORT_PCR register
16904  */
16905 /*@{*/
16906 #define PORT_RD_PCR(base, index) (PORT_PCR_REG(base, index))
16907 #define PORT_WR_PCR(base, index, value) (PORT_PCR_REG(base, index) = (value))
16908 #define PORT_RMW_PCR(base, index, mask, value) (PORT_WR_PCR(base, index, (PORT_RD_PCR(base, index) & ~(mask)) | (value)))
16909 #define PORT_SET_PCR(base, index, value) (BME_OR32(&PORT_PCR_REG(base, index), (uint32_t)(value)))
16910 #define PORT_CLR_PCR(base, index, value) (BME_AND32(&PORT_PCR_REG(base, index), (uint32_t)(~(value))))
16911 #define PORT_TOG_PCR(base, index, value) (BME_XOR32(&PORT_PCR_REG(base, index), (uint32_t)(value)))
16912 /*@}*/
16913 
16914 /*
16915  * Constants & macros for individual PORT_PCR bitfields
16916  */
16917 
16918 /*!
16919  * @name Register PORT_PCR, field PS[0] (RW)
16920  *
16921  * This bit is read only for pins that do not support a configurable pull
16922  * resistor direction. Pull configuration is valid in all digital pin muxing modes.
16923  *
16924  * Values:
16925  * - 0b0 - Internal pulldown resistor is enabled on the corresponding pin, if
16926  *     the corresponding PE field is set.
16927  * - 0b1 - Internal pullup resistor is enabled on the corresponding pin, if the
16928  *     corresponding PE field is set.
16929  */
16930 /*@{*/
16931 /*! @brief Read current value of the PORT_PCR_PS field. */
16932 #define PORT_RD_PCR_PS(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PS_MASK) >> PORT_PCR_PS_SHIFT)
16933 #define PORT_BRD_PCR_PS(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_PS_SHIFT, PORT_PCR_PS_WIDTH))
16934 
16935 /*! @brief Set the PS field to a new value. */
16936 #define PORT_WR_PCR_PS(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PS_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PS(value)))
16937 #define PORT_BWR_PCR_PS(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(value) << PORT_PCR_PS_SHIFT), PORT_PCR_PS_SHIFT, PORT_PCR_PS_WIDTH))
16938 /*@}*/
16939 
16940 /*!
16941  * @name Register PORT_PCR, field PE[1] (RW)
16942  *
16943  * This field is read-only for pins that do not support a configurable pull
16944  * resistor. Refer to the Chapter of Signal Multiplexing and Signal Descriptions for
16945  * the pins that support a configurable pull resistor. Pull configuration is
16946  * valid in all digital pin muxing modes.
16947  *
16948  * Values:
16949  * - 0b0 - Internal pullup or pulldown resistor is not enabled on the
16950  *     corresponding pin.
16951  * - 0b1 - Internal pullup or pulldown resistor is enabled on the corresponding
16952  *     pin, if the pin is configured as a digital input.
16953  */
16954 /*@{*/
16955 /*! @brief Read current value of the PORT_PCR_PE field. */
16956 #define PORT_RD_PCR_PE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PE_MASK) >> PORT_PCR_PE_SHIFT)
16957 #define PORT_BRD_PCR_PE(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_PE_SHIFT, PORT_PCR_PE_WIDTH))
16958 
16959 /*! @brief Set the PE field to a new value. */
16960 #define PORT_WR_PCR_PE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PE(value)))
16961 #define PORT_BWR_PCR_PE(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(value) << PORT_PCR_PE_SHIFT), PORT_PCR_PE_SHIFT, PORT_PCR_PE_WIDTH))
16962 /*@}*/
16963 
16964 /*!
16965  * @name Register PORT_PCR, field SRE[2] (RW)
16966  *
16967  * This field is read-only for pins that do not support a configurable slew
16968  * rate. Slew rate configuration is valid in all digital pin muxing modes.
16969  *
16970  * Values:
16971  * - 0b0 - Fast slew rate is configured on the corresponding pin, if the pin is
16972  *     configured as a digital output.
16973  * - 0b1 - Slow slew rate is configured on the corresponding pin, if the pin is
16974  *     configured as a digital output.
16975  */
16976 /*@{*/
16977 /*! @brief Read current value of the PORT_PCR_SRE field. */
16978 #define PORT_RD_PCR_SRE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_SRE_MASK) >> PORT_PCR_SRE_SHIFT)
16979 #define PORT_BRD_PCR_SRE(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_SRE_SHIFT, PORT_PCR_SRE_WIDTH))
16980 
16981 /*! @brief Set the SRE field to a new value. */
16982 #define PORT_WR_PCR_SRE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_SRE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_SRE(value)))
16983 #define PORT_BWR_PCR_SRE(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(value) << PORT_PCR_SRE_SHIFT), PORT_PCR_SRE_SHIFT, PORT_PCR_SRE_WIDTH))
16984 /*@}*/
16985 
16986 /*!
16987  * @name Register PORT_PCR, field PFE[4] (RW)
16988  *
16989  * This field is read-only for pins that do not support a configurable passive
16990  * input filter. Passive filter configuration is valid in all digital pin muxing
16991  * modes.
16992  *
16993  * Values:
16994  * - 0b0 - Passive input filter is disabled on the corresponding pin.
16995  * - 0b1 - Passive input filter is enabled on the corresponding pin, if the pin
16996  *     is configured as a digital input. Refer to the device data sheet for
16997  *     filter characteristics.
16998  */
16999 /*@{*/
17000 /*! @brief Read current value of the PORT_PCR_PFE field. */
17001 #define PORT_RD_PCR_PFE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_PFE_MASK) >> PORT_PCR_PFE_SHIFT)
17002 #define PORT_BRD_PCR_PFE(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_PFE_SHIFT, PORT_PCR_PFE_WIDTH))
17003 
17004 /*! @brief Set the PFE field to a new value. */
17005 #define PORT_WR_PCR_PFE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_PFE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_PFE(value)))
17006 #define PORT_BWR_PCR_PFE(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(value) << PORT_PCR_PFE_SHIFT), PORT_PCR_PFE_SHIFT, PORT_PCR_PFE_WIDTH))
17007 /*@}*/
17008 
17009 /*!
17010  * @name Register PORT_PCR, field DSE[6] (RW)
17011  *
17012  * This field is read-only for pins that do not support a configurable drive
17013  * strength. Drive strength configuration is valid in all digital pin muxing modes.
17014  *
17015  * Values:
17016  * - 0b0 - Low drive strength is configured on the corresponding pin, if pin is
17017  *     configured as a digital output.
17018  * - 0b1 - High drive strength is configured on the corresponding pin, if pin is
17019  *     configured as a digital output.
17020  */
17021 /*@{*/
17022 /*! @brief Read current value of the PORT_PCR_DSE field. */
17023 #define PORT_RD_PCR_DSE(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_DSE_MASK) >> PORT_PCR_DSE_SHIFT)
17024 #define PORT_BRD_PCR_DSE(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_DSE_SHIFT, PORT_PCR_DSE_WIDTH))
17025 
17026 /*! @brief Set the DSE field to a new value. */
17027 #define PORT_WR_PCR_DSE(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_DSE_MASK | PORT_PCR_ISF_MASK), PORT_PCR_DSE(value)))
17028 #define PORT_BWR_PCR_DSE(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(value) << PORT_PCR_DSE_SHIFT), PORT_PCR_DSE_SHIFT, PORT_PCR_DSE_WIDTH))
17029 /*@}*/
17030 
17031 /*!
17032  * @name Register PORT_PCR, field MUX[10:8] (RW)
17033  *
17034  * Not all pins support all pin muxing slots. Unimplemented pin muxing slots are
17035  * reserved and may result in configuring the pin for a different pin muxing
17036  * slot. The corresponding pin is configured in the following pin muxing slot as
17037  * follows:
17038  *
17039  * Values:
17040  * - 0b000 - Pin disabled (analog).
17041  * - 0b001 - Alternative 1 (GPIO).
17042  * - 0b010 - Alternative 2 (chip-specific).
17043  * - 0b011 - Alternative 3 (chip-specific).
17044  * - 0b100 - Alternative 4 (chip-specific).
17045  * - 0b101 - Alternative 5 (chip-specific).
17046  * - 0b110 - Alternative 6 (chip-specific).
17047  * - 0b111 - Alternative 7 (chip-specific).
17048  */
17049 /*@{*/
17050 /*! @brief Read current value of the PORT_PCR_MUX field. */
17051 #define PORT_RD_PCR_MUX(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_MUX_MASK) >> PORT_PCR_MUX_SHIFT)
17052 #define PORT_BRD_PCR_MUX(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_MUX_SHIFT, PORT_PCR_MUX_WIDTH))
17053 
17054 /*! @brief Set the MUX field to a new value. */
17055 #define PORT_WR_PCR_MUX(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_MUX_MASK | PORT_PCR_ISF_MASK), PORT_PCR_MUX(value)))
17056 #define PORT_BWR_PCR_MUX(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(value) << PORT_PCR_MUX_SHIFT), PORT_PCR_MUX_SHIFT, PORT_PCR_MUX_WIDTH))
17057 /*@}*/
17058 
17059 /*!
17060  * @name Register PORT_PCR, field IRQC[19:16] (RW)
17061  *
17062  * This field is read-only for pins that do not support interrupt generation.
17063  * The pin interrupt configuration is valid in all digital pin muxing modes. The
17064  * corresponding pin is configured to generate interrupt/DMA request as follows:
17065  *
17066  * Values:
17067  * - 0b0000 - Interrupt Status Flag (ISF) is disabled.
17068  * - 0b0001 - ISF flag and DMA request on rising edge.
17069  * - 0b0010 - ISF flag and DMA request on falling edge.
17070  * - 0b0011 - ISF flag and DMA request on either edge.
17071  * - 0b0100 - Reserved.
17072  * - 0b0101 - Reserved.
17073  * - 0b0110 - Reserved.
17074  * - 0b0111 - Reserved.
17075  * - 0b1000 - ISF flag and Interrupt when logic 0.
17076  * - 0b1001 - ISF flag and Interrupt on rising-edge.
17077  * - 0b1010 - ISF flag and Interrupt on falling-edge.
17078  * - 0b1011 - ISF flag and Interrupt on either edge.
17079  * - 0b1100 - ISF flag and Interrupt when logic 1.
17080  * - 0b1101 - Reserved.
17081  * - 0b1110 - Reserved.
17082  * - 0b1111 - Reserved.
17083  */
17084 /*@{*/
17085 /*! @brief Read current value of the PORT_PCR_IRQC field. */
17086 #define PORT_RD_PCR_IRQC(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_IRQC_MASK) >> PORT_PCR_IRQC_SHIFT)
17087 #define PORT_BRD_PCR_IRQC(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_IRQC_SHIFT, PORT_PCR_IRQC_WIDTH))
17088 
17089 /*! @brief Set the IRQC field to a new value. */
17090 #define PORT_WR_PCR_IRQC(base, index, value) (PORT_RMW_PCR(base, index, (PORT_PCR_IRQC_MASK | PORT_PCR_ISF_MASK), PORT_PCR_IRQC(value)))
17091 #define PORT_BWR_PCR_IRQC(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(value) << PORT_PCR_IRQC_SHIFT), PORT_PCR_IRQC_SHIFT, PORT_PCR_IRQC_WIDTH))
17092 /*@}*/
17093 
17094 /*!
17095  * @name Register PORT_PCR, field ISF[24] (W1C)
17096  *
17097  * This field is read-only for pins that do not support interrupt generation.
17098  * The pin interrupt configuration is valid in all digital pin muxing modes.
17099  *
17100  * Values:
17101  * - 0b0 - Configured interrupt is not detected.
17102  * - 0b1 - Configured interrupt is detected. If the pin is configured to
17103  *     generate a DMA request, then the corresponding flag will be cleared automatically
17104  *     at the completion of the requested DMA transfer. Otherwise, the flag
17105  *     remains set until a logic 1 is written to the flag. If the pin is configured
17106  *     for a level sensitive interrupt and the pin remains asserted, then the flag
17107  *     is set again immediately after it is cleared.
17108  */
17109 /*@{*/
17110 /*! @brief Read current value of the PORT_PCR_ISF field. */
17111 #define PORT_RD_PCR_ISF(base, index) ((PORT_PCR_REG(base, index) & PORT_PCR_ISF_MASK) >> PORT_PCR_ISF_SHIFT)
17112 #define PORT_BRD_PCR_ISF(base, index) (BME_UBFX32(&PORT_PCR_REG(base, index), PORT_PCR_ISF_SHIFT, PORT_PCR_ISF_WIDTH))
17113 
17114 /*! @brief Set the ISF field to a new value. */
17115 #define PORT_WR_PCR_ISF(base, index, value) (PORT_RMW_PCR(base, index, PORT_PCR_ISF_MASK, PORT_PCR_ISF(value)))
17116 #define PORT_BWR_PCR_ISF(base, index, value) (BME_BFI32(&PORT_PCR_REG(base, index), ((uint32_t)(value) << PORT_PCR_ISF_SHIFT), PORT_PCR_ISF_SHIFT, PORT_PCR_ISF_WIDTH))
17117 /*@}*/
17118 
17119 /*******************************************************************************
17120  * PORT_GPCLR - Global Pin Control Low Register
17121  ******************************************************************************/
17122 
17123 /*!
17124  * @brief PORT_GPCLR - Global Pin Control Low Register (WORZ)
17125  *
17126  * Reset value: 0x00000000U
17127  *
17128  * Only 32-bit writes are supported to this register.
17129  */
17130 /*!
17131  * @name Constants and macros for entire PORT_GPCLR register
17132  */
17133 /*@{*/
17134 #define PORT_RD_GPCLR(base)      (PORT_GPCLR_REG(base))
17135 #define PORT_WR_GPCLR(base, value) (PORT_GPCLR_REG(base) = (value))
17136 #define PORT_RMW_GPCLR(base, mask, value) (PORT_WR_GPCLR(base, (PORT_RD_GPCLR(base) & ~(mask)) | (value)))
17137 /*@}*/
17138 
17139 /*
17140  * Constants & macros for individual PORT_GPCLR bitfields
17141  */
17142 
17143 /*!
17144  * @name Register PORT_GPCLR, field GPWD[15:0] (WORZ)
17145  *
17146  * Write value that is written to all Pin Control Registers bits [15:0] that are
17147  * selected by GPWE.
17148  */
17149 /*@{*/
17150 /*! @brief Set the GPWD field to a new value. */
17151 #define PORT_WR_GPCLR_GPWD(base, value) (PORT_RMW_GPCLR(base, PORT_GPCLR_GPWD_MASK, PORT_GPCLR_GPWD(value)))
17152 #define PORT_BWR_GPCLR_GPWD(base, value) (BME_BFI32(&PORT_GPCLR_REG(base), ((uint32_t)(value) << PORT_GPCLR_GPWD_SHIFT), PORT_GPCLR_GPWD_SHIFT, PORT_GPCLR_GPWD_WIDTH))
17153 /*@}*/
17154 
17155 /*!
17156  * @name Register PORT_GPCLR, field GPWE[31:16] (WORZ)
17157  *
17158  * Selects which Pin Control Registers (15 through 0) bits [15:0] update with
17159  * the value in GPWD.
17160  *
17161  * Values:
17162  * - 0b0000000000000000 - Corresponding Pin Control Register is not updated with
17163  *     the value in GPWD.
17164  * - 0b0000000000000001 - Corresponding Pin Control Register is updated with the
17165  *     value in GPWD.
17166  */
17167 /*@{*/
17168 /*! @brief Set the GPWE field to a new value. */
17169 #define PORT_WR_GPCLR_GPWE(base, value) (PORT_RMW_GPCLR(base, PORT_GPCLR_GPWE_MASK, PORT_GPCLR_GPWE(value)))
17170 #define PORT_BWR_GPCLR_GPWE(base, value) (BME_BFI32(&PORT_GPCLR_REG(base), ((uint32_t)(value) << PORT_GPCLR_GPWE_SHIFT), PORT_GPCLR_GPWE_SHIFT, PORT_GPCLR_GPWE_WIDTH))
17171 /*@}*/
17172 
17173 /*******************************************************************************
17174  * PORT_GPCHR - Global Pin Control High Register
17175  ******************************************************************************/
17176 
17177 /*!
17178  * @brief PORT_GPCHR - Global Pin Control High Register (WORZ)
17179  *
17180  * Reset value: 0x00000000U
17181  *
17182  * Only 32-bit writes are supported to this register.
17183  */
17184 /*!
17185  * @name Constants and macros for entire PORT_GPCHR register
17186  */
17187 /*@{*/
17188 #define PORT_RD_GPCHR(base)      (PORT_GPCHR_REG(base))
17189 #define PORT_WR_GPCHR(base, value) (PORT_GPCHR_REG(base) = (value))
17190 #define PORT_RMW_GPCHR(base, mask, value) (PORT_WR_GPCHR(base, (PORT_RD_GPCHR(base) & ~(mask)) | (value)))
17191 /*@}*/
17192 
17193 /*
17194  * Constants & macros for individual PORT_GPCHR bitfields
17195  */
17196 
17197 /*!
17198  * @name Register PORT_GPCHR, field GPWD[15:0] (WORZ)
17199  *
17200  * Write value that is written to all Pin Control Registers bits [15:0] that are
17201  * selected by GPWE.
17202  */
17203 /*@{*/
17204 /*! @brief Set the GPWD field to a new value. */
17205 #define PORT_WR_GPCHR_GPWD(base, value) (PORT_RMW_GPCHR(base, PORT_GPCHR_GPWD_MASK, PORT_GPCHR_GPWD(value)))
17206 #define PORT_BWR_GPCHR_GPWD(base, value) (BME_BFI32(&PORT_GPCHR_REG(base), ((uint32_t)(value) << PORT_GPCHR_GPWD_SHIFT), PORT_GPCHR_GPWD_SHIFT, PORT_GPCHR_GPWD_WIDTH))
17207 /*@}*/
17208 
17209 /*!
17210  * @name Register PORT_GPCHR, field GPWE[31:16] (WORZ)
17211  *
17212  * Selects which Pin Control Registers (31 through 16) bits [15:0] update with
17213  * the value in GPWD.
17214  *
17215  * Values:
17216  * - 0b0000000000000000 - Corresponding Pin Control Register is not updated with
17217  *     the value in GPWD.
17218  * - 0b0000000000000001 - Corresponding Pin Control Register is updated with the
17219  *     value in GPWD.
17220  */
17221 /*@{*/
17222 /*! @brief Set the GPWE field to a new value. */
17223 #define PORT_WR_GPCHR_GPWE(base, value) (PORT_RMW_GPCHR(base, PORT_GPCHR_GPWE_MASK, PORT_GPCHR_GPWE(value)))
17224 #define PORT_BWR_GPCHR_GPWE(base, value) (BME_BFI32(&PORT_GPCHR_REG(base), ((uint32_t)(value) << PORT_GPCHR_GPWE_SHIFT), PORT_GPCHR_GPWE_SHIFT, PORT_GPCHR_GPWE_WIDTH))
17225 /*@}*/
17226 
17227 /*******************************************************************************
17228  * PORT_ISFR - Interrupt Status Flag Register
17229  ******************************************************************************/
17230 
17231 /*!
17232  * @brief PORT_ISFR - Interrupt Status Flag Register (W1C)
17233  *
17234  * Reset value: 0x00000000U
17235  *
17236  * The corresponding bit is read only for pins that do not support interrupt
17237  * generation. The pin interrupt configuration is valid in all digital pin muxing
17238  * modes. The Interrupt Status Flag for each pin is also visible in the
17239  * corresponding Pin Control Register, and each flag can be cleared in either location.
17240  */
17241 /*!
17242  * @name Constants and macros for entire PORT_ISFR register
17243  */
17244 /*@{*/
17245 #define PORT_RD_ISFR(base)       (PORT_ISFR_REG(base))
17246 #define PORT_WR_ISFR(base, value) (PORT_ISFR_REG(base) = (value))
17247 #define PORT_RMW_ISFR(base, mask, value) (PORT_WR_ISFR(base, (PORT_RD_ISFR(base) & ~(mask)) | (value)))
17248 #define PORT_SET_ISFR(base, value) (BME_OR32(&PORT_ISFR_REG(base), (uint32_t)(value)))
17249 #define PORT_CLR_ISFR(base, value) (BME_AND32(&PORT_ISFR_REG(base), (uint32_t)(~(value))))
17250 #define PORT_TOG_ISFR(base, value) (BME_XOR32(&PORT_ISFR_REG(base), (uint32_t)(value)))
17251 /*@}*/
17252 
17253 /*
17254  * MKW40Z4 RCM
17255  *
17256  * Reset Control Module
17257  *
17258  * Registers defined in this header file:
17259  * - RCM_SRS0 - System Reset Status Register 0
17260  * - RCM_SRS1 - System Reset Status Register 1
17261  * - RCM_RPFC - Reset Pin Filter Control register
17262  * - RCM_RPFW - Reset Pin Filter Width register
17263  */
17264 
17265 #define RCM_INSTANCE_COUNT (1U) /*!< Number of instances of the RCM module. */
17266 #define RCM_IDX (0U) /*!< Instance number for RCM. */
17267 
17268 /*******************************************************************************
17269  * RCM_SRS0 - System Reset Status Register 0
17270  ******************************************************************************/
17271 
17272 /*!
17273  * @brief RCM_SRS0 - System Reset Status Register 0 (RO)
17274  *
17275  * Reset value: 0x82U
17276  *
17277  * This register includes read-only status flags to indicate the source of the
17278  * most recent reset. The reset state of these bits depends on what caused the MCU
17279  * to reset. The reset value of this register depends on the reset source: POR
17280  * (including LVD) - 0x82 LVD (without POR) - 0x02 VLLS mode wakeup due to RESET
17281  * pin assertion - 0x41 VLLS mode wakeup due to other wakeup sources - 0x01 Other
17282  * reset - a bit is set if its corresponding reset source caused the reset
17283  */
17284 /*!
17285  * @name Constants and macros for entire RCM_SRS0 register
17286  */
17287 /*@{*/
17288 #define RCM_RD_SRS0(base)        (RCM_SRS0_REG(base))
17289 /*@}*/
17290 
17291 /*
17292  * Constants & macros for individual RCM_SRS0 bitfields
17293  */
17294 
17295 /*!
17296  * @name Register RCM_SRS0, field WAKEUP[0] (RO)
17297  *
17298  * Indicates a reset has been caused by an enabled LLWU module wakeup source
17299  * while the chip was in a low leakage mode. In LLS mode, the RESET pin is the only
17300  * wakeup source that can cause this reset. Any enabled wakeup source in a VLLSx
17301  * mode causes a reset. This bit is cleared by any reset except WAKEUP.
17302  *
17303  * Values:
17304  * - 0b0 - Reset not caused by LLWU module wakeup source
17305  * - 0b1 - Reset caused by LLWU module wakeup source
17306  */
17307 /*@{*/
17308 /*! @brief Read current value of the RCM_SRS0_WAKEUP field. */
17309 #define RCM_RD_SRS0_WAKEUP(base) ((RCM_SRS0_REG(base) & RCM_SRS0_WAKEUP_MASK) >> RCM_SRS0_WAKEUP_SHIFT)
17310 #define RCM_BRD_SRS0_WAKEUP(base) (BME_UBFX8(&RCM_SRS0_REG(base), RCM_SRS0_WAKEUP_SHIFT, RCM_SRS0_WAKEUP_WIDTH))
17311 /*@}*/
17312 
17313 /*!
17314  * @name Register RCM_SRS0, field LVD[1] (RO)
17315  *
17316  * If PMC_LVDSC1[LVDRE] is set and the supply drops below the LVD trip voltage,
17317  * an LVD reset occurs. This field is also set by POR.
17318  *
17319  * Values:
17320  * - 0b0 - Reset not caused by LVD trip or POR
17321  * - 0b1 - Reset caused by LVD trip or POR
17322  */
17323 /*@{*/
17324 /*! @brief Read current value of the RCM_SRS0_LVD field. */
17325 #define RCM_RD_SRS0_LVD(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LVD_MASK) >> RCM_SRS0_LVD_SHIFT)
17326 #define RCM_BRD_SRS0_LVD(base) (BME_UBFX8(&RCM_SRS0_REG(base), RCM_SRS0_LVD_SHIFT, RCM_SRS0_LVD_WIDTH))
17327 /*@}*/
17328 
17329 /*!
17330  * @name Register RCM_SRS0, field LOC[2] (RO)
17331  *
17332  * Indicates a reset has been caused by a loss of external clock. The MCG clock
17333  * monitor must be enabled for a loss of clock to be detected. Refer to the
17334  * detailed MCG description for information on enabling the clock monitor.
17335  *
17336  * Values:
17337  * - 0b0 - Reset not caused by a loss of external clock.
17338  * - 0b1 - Reset caused by a loss of external clock.
17339  */
17340 /*@{*/
17341 /*! @brief Read current value of the RCM_SRS0_LOC field. */
17342 #define RCM_RD_SRS0_LOC(base) ((RCM_SRS0_REG(base) & RCM_SRS0_LOC_MASK) >> RCM_SRS0_LOC_SHIFT)
17343 #define RCM_BRD_SRS0_LOC(base) (BME_UBFX8(&RCM_SRS0_REG(base), RCM_SRS0_LOC_SHIFT, RCM_SRS0_LOC_WIDTH))
17344 /*@}*/
17345 
17346 /*!
17347  * @name Register RCM_SRS0, field WDOG[5] (RO)
17348  *
17349  * Indicates a reset has been caused by the watchdog timer timing out. This
17350  * reset source can be blocked by disabling the watchdog.
17351  *
17352  * Values:
17353  * - 0b0 - Reset not caused by watchdog timeout
17354  * - 0b1 - Reset caused by watchdog timeout
17355  */
17356 /*@{*/
17357 /*! @brief Read current value of the RCM_SRS0_WDOG field. */
17358 #define RCM_RD_SRS0_WDOG(base) ((RCM_SRS0_REG(base) & RCM_SRS0_WDOG_MASK) >> RCM_SRS0_WDOG_SHIFT)
17359 #define RCM_BRD_SRS0_WDOG(base) (BME_UBFX8(&RCM_SRS0_REG(base), RCM_SRS0_WDOG_SHIFT, RCM_SRS0_WDOG_WIDTH))
17360 /*@}*/
17361 
17362 /*!
17363  * @name Register RCM_SRS0, field PIN[6] (RO)
17364  *
17365  * Indicates a reset has been caused by an active-low level on the external
17366  * RESET pin.
17367  *
17368  * Values:
17369  * - 0b0 - Reset not caused by external reset pin
17370  * - 0b1 - Reset caused by external reset pin
17371  */
17372 /*@{*/
17373 /*! @brief Read current value of the RCM_SRS0_PIN field. */
17374 #define RCM_RD_SRS0_PIN(base) ((RCM_SRS0_REG(base) & RCM_SRS0_PIN_MASK) >> RCM_SRS0_PIN_SHIFT)
17375 #define RCM_BRD_SRS0_PIN(base) (BME_UBFX8(&RCM_SRS0_REG(base), RCM_SRS0_PIN_SHIFT, RCM_SRS0_PIN_WIDTH))
17376 /*@}*/
17377 
17378 /*!
17379  * @name Register RCM_SRS0, field POR[7] (RO)
17380  *
17381  * Indicates a reset has been caused by the power-on detection logic. Because
17382  * the internal supply voltage was ramping up at the time, the low-voltage reset
17383  * (LVD) status bit is also set to indicate that the reset occurred while the
17384  * internal supply was below the LVD threshold.
17385  *
17386  * Values:
17387  * - 0b0 - Reset not caused by POR
17388  * - 0b1 - Reset caused by POR
17389  */
17390 /*@{*/
17391 /*! @brief Read current value of the RCM_SRS0_POR field. */
17392 #define RCM_RD_SRS0_POR(base) ((RCM_SRS0_REG(base) & RCM_SRS0_POR_MASK) >> RCM_SRS0_POR_SHIFT)
17393 #define RCM_BRD_SRS0_POR(base) (BME_UBFX8(&RCM_SRS0_REG(base), RCM_SRS0_POR_SHIFT, RCM_SRS0_POR_WIDTH))
17394 /*@}*/
17395 
17396 /*******************************************************************************
17397  * RCM_SRS1 - System Reset Status Register 1
17398  ******************************************************************************/
17399 
17400 /*!
17401  * @brief RCM_SRS1 - System Reset Status Register 1 (RO)
17402  *
17403  * Reset value: 0x00U
17404  *
17405  * This register includes read-only status flags to indicate the source of the
17406  * most recent reset. The reset state of these bits depends on what caused the MCU
17407  * to reset. The reset value of this register depends on the reset source: POR
17408  * (including LVD) - 0x00 LVD (without POR) - 0x00 VLLS mode wakeup - 0x00 Other
17409  * reset - a bit is set if its corresponding reset source caused the reset
17410  */
17411 /*!
17412  * @name Constants and macros for entire RCM_SRS1 register
17413  */
17414 /*@{*/
17415 #define RCM_RD_SRS1(base)        (RCM_SRS1_REG(base))
17416 /*@}*/
17417 
17418 /*
17419  * Constants & macros for individual RCM_SRS1 bitfields
17420  */
17421 
17422 /*!
17423  * @name Register RCM_SRS1, field LOCKUP[1] (RO)
17424  *
17425  * Indicates a reset has been caused by the ARM core indication of a LOCKUP
17426  * event.
17427  *
17428  * Values:
17429  * - 0b0 - Reset not caused by core LOCKUP event
17430  * - 0b1 - Reset caused by core LOCKUP event
17431  */
17432 /*@{*/
17433 /*! @brief Read current value of the RCM_SRS1_LOCKUP field. */
17434 #define RCM_RD_SRS1_LOCKUP(base) ((RCM_SRS1_REG(base) & RCM_SRS1_LOCKUP_MASK) >> RCM_SRS1_LOCKUP_SHIFT)
17435 #define RCM_BRD_SRS1_LOCKUP(base) (BME_UBFX8(&RCM_SRS1_REG(base), RCM_SRS1_LOCKUP_SHIFT, RCM_SRS1_LOCKUP_WIDTH))
17436 /*@}*/
17437 
17438 /*!
17439  * @name Register RCM_SRS1, field SW[2] (RO)
17440  *
17441  * Indicates a reset has been caused by software setting of SYSRESETREQ bit in
17442  * Application Interrupt and Reset Control Register in the ARM core.
17443  *
17444  * Values:
17445  * - 0b0 - Reset not caused by software setting of SYSRESETREQ bit
17446  * - 0b1 - Reset caused by software setting of SYSRESETREQ bit
17447  */
17448 /*@{*/
17449 /*! @brief Read current value of the RCM_SRS1_SW field. */
17450 #define RCM_RD_SRS1_SW(base) ((RCM_SRS1_REG(base) & RCM_SRS1_SW_MASK) >> RCM_SRS1_SW_SHIFT)
17451 #define RCM_BRD_SRS1_SW(base) (BME_UBFX8(&RCM_SRS1_REG(base), RCM_SRS1_SW_SHIFT, RCM_SRS1_SW_WIDTH))
17452 /*@}*/
17453 
17454 /*!
17455  * @name Register RCM_SRS1, field MDM_AP[3] (RO)
17456  *
17457  * Indicates a reset has been caused by the host debugger system setting of the
17458  * System Reset Request bit in the MDM-AP Control Register.
17459  *
17460  * Values:
17461  * - 0b0 - Reset not caused by host debugger system setting of the System Reset
17462  *     Request bit
17463  * - 0b1 - Reset caused by host debugger system setting of the System Reset
17464  *     Request bit
17465  */
17466 /*@{*/
17467 /*! @brief Read current value of the RCM_SRS1_MDM_AP field. */
17468 #define RCM_RD_SRS1_MDM_AP(base) ((RCM_SRS1_REG(base) & RCM_SRS1_MDM_AP_MASK) >> RCM_SRS1_MDM_AP_SHIFT)
17469 #define RCM_BRD_SRS1_MDM_AP(base) (BME_UBFX8(&RCM_SRS1_REG(base), RCM_SRS1_MDM_AP_SHIFT, RCM_SRS1_MDM_AP_WIDTH))
17470 /*@}*/
17471 
17472 /*!
17473  * @name Register RCM_SRS1, field SACKERR[5] (RO)
17474  *
17475  * Indicates that after an attempt to enter Stop mode, a reset has been caused
17476  * by a failure of one or more peripherals to acknowledge within approximately one
17477  * second to enter stop mode.
17478  *
17479  * Values:
17480  * - 0b0 - Reset not caused by peripheral failure to acknowledge attempt to
17481  *     enter stop mode
17482  * - 0b1 - Reset caused by peripheral failure to acknowledge attempt to enter
17483  *     stop mode
17484  */
17485 /*@{*/
17486 /*! @brief Read current value of the RCM_SRS1_SACKERR field. */
17487 #define RCM_RD_SRS1_SACKERR(base) ((RCM_SRS1_REG(base) & RCM_SRS1_SACKERR_MASK) >> RCM_SRS1_SACKERR_SHIFT)
17488 #define RCM_BRD_SRS1_SACKERR(base) (BME_UBFX8(&RCM_SRS1_REG(base), RCM_SRS1_SACKERR_SHIFT, RCM_SRS1_SACKERR_WIDTH))
17489 /*@}*/
17490 
17491 /*******************************************************************************
17492  * RCM_RPFC - Reset Pin Filter Control register
17493  ******************************************************************************/
17494 
17495 /*!
17496  * @brief RCM_RPFC - Reset Pin Filter Control register (RW)
17497  *
17498  * Reset value: 0x00U
17499  *
17500  * The reset values of bits 2-0 are for Chip POR only. They are unaffected by
17501  * other reset types. The bus clock filter is reset when disabled or when entering
17502  * stop mode. The LPO filter is reset when disabled .
17503  */
17504 /*!
17505  * @name Constants and macros for entire RCM_RPFC register
17506  */
17507 /*@{*/
17508 #define RCM_RD_RPFC(base)        (RCM_RPFC_REG(base))
17509 #define RCM_WR_RPFC(base, value) (RCM_RPFC_REG(base) = (value))
17510 #define RCM_RMW_RPFC(base, mask, value) (RCM_WR_RPFC(base, (RCM_RD_RPFC(base) & ~(mask)) | (value)))
17511 #define RCM_SET_RPFC(base, value) (BME_OR8(&RCM_RPFC_REG(base), (uint8_t)(value)))
17512 #define RCM_CLR_RPFC(base, value) (BME_AND8(&RCM_RPFC_REG(base), (uint8_t)(~(value))))
17513 #define RCM_TOG_RPFC(base, value) (BME_XOR8(&RCM_RPFC_REG(base), (uint8_t)(value)))
17514 /*@}*/
17515 
17516 /*
17517  * Constants & macros for individual RCM_RPFC bitfields
17518  */
17519 
17520 /*!
17521  * @name Register RCM_RPFC, field RSTFLTSRW[1:0] (RW)
17522  *
17523  * Selects how the reset pin filter is enabled in run and wait modes.
17524  *
17525  * Values:
17526  * - 0b00 - All filtering disabled
17527  * - 0b01 - Bus clock filter enabled for normal operation
17528  * - 0b10 - LPO clock filter enabled for normal operation
17529  * - 0b11 - Reserved (all filtering disabled)
17530  */
17531 /*@{*/
17532 /*! @brief Read current value of the RCM_RPFC_RSTFLTSRW field. */
17533 #define RCM_RD_RPFC_RSTFLTSRW(base) ((RCM_RPFC_REG(base) & RCM_RPFC_RSTFLTSRW_MASK) >> RCM_RPFC_RSTFLTSRW_SHIFT)
17534 #define RCM_BRD_RPFC_RSTFLTSRW(base) (BME_UBFX8(&RCM_RPFC_REG(base), RCM_RPFC_RSTFLTSRW_SHIFT, RCM_RPFC_RSTFLTSRW_WIDTH))
17535 
17536 /*! @brief Set the RSTFLTSRW field to a new value. */
17537 #define RCM_WR_RPFC_RSTFLTSRW(base, value) (RCM_RMW_RPFC(base, RCM_RPFC_RSTFLTSRW_MASK, RCM_RPFC_RSTFLTSRW(value)))
17538 #define RCM_BWR_RPFC_RSTFLTSRW(base, value) (BME_BFI8(&RCM_RPFC_REG(base), ((uint8_t)(value) << RCM_RPFC_RSTFLTSRW_SHIFT), RCM_RPFC_RSTFLTSRW_SHIFT, RCM_RPFC_RSTFLTSRW_WIDTH))
17539 /*@}*/
17540 
17541 /*!
17542  * @name Register RCM_RPFC, field RSTFLTSS[2] (RW)
17543  *
17544  * Selects how the reset pin filter is enabled in Stop and VLPS modes , and also
17545  * during LLS and VLLS modes. On exit from VLLS mode, this bit should be
17546  * reconfigured before clearing PMC_REGSC[ACKISO].
17547  *
17548  * Values:
17549  * - 0b0 - All filtering disabled
17550  * - 0b1 - LPO clock filter enabled
17551  */
17552 /*@{*/
17553 /*! @brief Read current value of the RCM_RPFC_RSTFLTSS field. */
17554 #define RCM_RD_RPFC_RSTFLTSS(base) ((RCM_RPFC_REG(base) & RCM_RPFC_RSTFLTSS_MASK) >> RCM_RPFC_RSTFLTSS_SHIFT)
17555 #define RCM_BRD_RPFC_RSTFLTSS(base) (BME_UBFX8(&RCM_RPFC_REG(base), RCM_RPFC_RSTFLTSS_SHIFT, RCM_RPFC_RSTFLTSS_WIDTH))
17556 
17557 /*! @brief Set the RSTFLTSS field to a new value. */
17558 #define RCM_WR_RPFC_RSTFLTSS(base, value) (RCM_RMW_RPFC(base, RCM_RPFC_RSTFLTSS_MASK, RCM_RPFC_RSTFLTSS(value)))
17559 #define RCM_BWR_RPFC_RSTFLTSS(base, value) (BME_BFI8(&RCM_RPFC_REG(base), ((uint8_t)(value) << RCM_RPFC_RSTFLTSS_SHIFT), RCM_RPFC_RSTFLTSS_SHIFT, RCM_RPFC_RSTFLTSS_WIDTH))
17560 /*@}*/
17561 
17562 /*******************************************************************************
17563  * RCM_RPFW - Reset Pin Filter Width register
17564  ******************************************************************************/
17565 
17566 /*!
17567  * @brief RCM_RPFW - Reset Pin Filter Width register (RW)
17568  *
17569  * Reset value: 0x00U
17570  *
17571  * The reset values of the bits in the RSTFLTSEL field are for Chip POR only.
17572  * They are unaffected by other reset types.
17573  */
17574 /*!
17575  * @name Constants and macros for entire RCM_RPFW register
17576  */
17577 /*@{*/
17578 #define RCM_RD_RPFW(base)        (RCM_RPFW_REG(base))
17579 #define RCM_WR_RPFW(base, value) (RCM_RPFW_REG(base) = (value))
17580 #define RCM_RMW_RPFW(base, mask, value) (RCM_WR_RPFW(base, (RCM_RD_RPFW(base) & ~(mask)) | (value)))
17581 #define RCM_SET_RPFW(base, value) (BME_OR8(&RCM_RPFW_REG(base), (uint8_t)(value)))
17582 #define RCM_CLR_RPFW(base, value) (BME_AND8(&RCM_RPFW_REG(base), (uint8_t)(~(value))))
17583 #define RCM_TOG_RPFW(base, value) (BME_XOR8(&RCM_RPFW_REG(base), (uint8_t)(value)))
17584 /*@}*/
17585 
17586 /*
17587  * Constants & macros for individual RCM_RPFW bitfields
17588  */
17589 
17590 /*!
17591  * @name Register RCM_RPFW, field RSTFLTSEL[4:0] (RW)
17592  *
17593  * Selects the reset pin bus clock filter width.
17594  *
17595  * Values:
17596  * - 0b00000 - Bus clock filter count is 1
17597  * - 0b00001 - Bus clock filter count is 2
17598  * - 0b00010 - Bus clock filter count is 3
17599  * - 0b00011 - Bus clock filter count is 4
17600  * - 0b00100 - Bus clock filter count is 5
17601  * - 0b00101 - Bus clock filter count is 6
17602  * - 0b00110 - Bus clock filter count is 7
17603  * - 0b00111 - Bus clock filter count is 8
17604  * - 0b01000 - Bus clock filter count is 9
17605  * - 0b01001 - Bus clock filter count is 10
17606  * - 0b01010 - Bus clock filter count is 11
17607  * - 0b01011 - Bus clock filter count is 12
17608  * - 0b01100 - Bus clock filter count is 13
17609  * - 0b01101 - Bus clock filter count is 14
17610  * - 0b01110 - Bus clock filter count is 15
17611  * - 0b01111 - Bus clock filter count is 16
17612  * - 0b10000 - Bus clock filter count is 17
17613  * - 0b10001 - Bus clock filter count is 18
17614  * - 0b10010 - Bus clock filter count is 19
17615  * - 0b10011 - Bus clock filter count is 20
17616  * - 0b10100 - Bus clock filter count is 21
17617  * - 0b10101 - Bus clock filter count is 22
17618  * - 0b10110 - Bus clock filter count is 23
17619  * - 0b10111 - Bus clock filter count is 24
17620  * - 0b11000 - Bus clock filter count is 25
17621  * - 0b11001 - Bus clock filter count is 26
17622  * - 0b11010 - Bus clock filter count is 27
17623  * - 0b11011 - Bus clock filter count is 28
17624  * - 0b11100 - Bus clock filter count is 29
17625  * - 0b11101 - Bus clock filter count is 30
17626  * - 0b11110 - Bus clock filter count is 31
17627  * - 0b11111 - Bus clock filter count is 32
17628  */
17629 /*@{*/
17630 /*! @brief Read current value of the RCM_RPFW_RSTFLTSEL field. */
17631 #define RCM_RD_RPFW_RSTFLTSEL(base) ((RCM_RPFW_REG(base) & RCM_RPFW_RSTFLTSEL_MASK) >> RCM_RPFW_RSTFLTSEL_SHIFT)
17632 #define RCM_BRD_RPFW_RSTFLTSEL(base) (BME_UBFX8(&RCM_RPFW_REG(base), RCM_RPFW_RSTFLTSEL_SHIFT, RCM_RPFW_RSTFLTSEL_WIDTH))
17633 
17634 /*! @brief Set the RSTFLTSEL field to a new value. */
17635 #define RCM_WR_RPFW_RSTFLTSEL(base, value) (RCM_RMW_RPFW(base, RCM_RPFW_RSTFLTSEL_MASK, RCM_RPFW_RSTFLTSEL(value)))
17636 #define RCM_BWR_RPFW_RSTFLTSEL(base, value) (BME_BFI8(&RCM_RPFW_REG(base), ((uint8_t)(value) << RCM_RPFW_RSTFLTSEL_SHIFT), RCM_RPFW_RSTFLTSEL_SHIFT, RCM_RPFW_RSTFLTSEL_WIDTH))
17637 /*@}*/
17638 
17639 /*
17640  * MKW40Z4 ROM
17641  *
17642  * System ROM
17643  *
17644  * Registers defined in this header file:
17645  * - ROM_ENTRY - Entry
17646  * - ROM_TABLEMARK - End of Table Marker Register
17647  * - ROM_SYSACCESS - System Access Register
17648  * - ROM_PERIPHID4 - Peripheral ID Register
17649  * - ROM_PERIPHID5 - Peripheral ID Register
17650  * - ROM_PERIPHID6 - Peripheral ID Register
17651  * - ROM_PERIPHID7 - Peripheral ID Register
17652  * - ROM_PERIPHID0 - Peripheral ID Register
17653  * - ROM_PERIPHID1 - Peripheral ID Register
17654  * - ROM_PERIPHID2 - Peripheral ID Register
17655  * - ROM_PERIPHID3 - Peripheral ID Register
17656  * - ROM_COMPID - Component ID Register
17657  */
17658 
17659 #define ROM_INSTANCE_COUNT (1U) /*!< Number of instances of the ROM module. */
17660 #define ROM_IDX (0U) /*!< Instance number for ROM. */
17661 
17662 /*******************************************************************************
17663  * ROM_ENTRY - Entry
17664  ******************************************************************************/
17665 
17666 /*!
17667  * @brief ROM_ENTRY - Entry (RO)
17668  *
17669  * Reset value: 0x00000000U
17670  *
17671  * The System ROM Table begins with "n" relative 32-bit addresses, one for each
17672  * debug component present in the device and terminating with an all-zero value
17673  * signaling the end of the table at the "n+1"-th value. It is hardwired to
17674  * specific values used during the auto-discovery process by an external debug agent.
17675  */
17676 /*!
17677  * @name Constants and macros for entire ROM_ENTRY register
17678  */
17679 /*@{*/
17680 #define ROM_RD_ENTRY(base, index) (ROM_ENTRY_REG(base, index))
17681 /*@}*/
17682 
17683 /*******************************************************************************
17684  * ROM_TABLEMARK - End of Table Marker Register
17685  ******************************************************************************/
17686 
17687 /*!
17688  * @brief ROM_TABLEMARK - End of Table Marker Register (RO)
17689  *
17690  * Reset value: 0x00000000U
17691  *
17692  * This register indicates end of table marker. It is hardwired to specific
17693  * values used during the auto-discovery process by an external debug agent.
17694  */
17695 /*!
17696  * @name Constants and macros for entire ROM_TABLEMARK register
17697  */
17698 /*@{*/
17699 #define ROM_RD_TABLEMARK(base)   (ROM_TABLEMARK_REG(base))
17700 /*@}*/
17701 
17702 /*******************************************************************************
17703  * ROM_SYSACCESS - System Access Register
17704  ******************************************************************************/
17705 
17706 /*!
17707  * @brief ROM_SYSACCESS - System Access Register (RO)
17708  *
17709  * Reset value: 0x00000001U
17710  *
17711  * This register indicates system access. It is hardwired to specific values
17712  * used during the auto-discovery process by an external debug agent.
17713  */
17714 /*!
17715  * @name Constants and macros for entire ROM_SYSACCESS register
17716  */
17717 /*@{*/
17718 #define ROM_RD_SYSACCESS(base)   (ROM_SYSACCESS_REG(base))
17719 /*@}*/
17720 
17721 /*******************************************************************************
17722  * ROM_PERIPHID4 - Peripheral ID Register
17723  ******************************************************************************/
17724 
17725 /*!
17726  * @brief ROM_PERIPHID4 - Peripheral ID Register (RO)
17727  *
17728  * Reset value: 0x00000000U
17729  *
17730  * These registers indicate the peripheral IDs. They are hardwired to specific
17731  * values used during the auto-discovery process by an external debug agent.
17732  */
17733 /*!
17734  * @name Constants and macros for entire ROM_PERIPHID4 register
17735  */
17736 /*@{*/
17737 #define ROM_RD_PERIPHID4(base)   (ROM_PERIPHID4_REG(base))
17738 /*@}*/
17739 
17740 /*******************************************************************************
17741  * ROM_PERIPHID5 - Peripheral ID Register
17742  ******************************************************************************/
17743 
17744 /*!
17745  * @brief ROM_PERIPHID5 - Peripheral ID Register (RO)
17746  *
17747  * Reset value: 0x00000000U
17748  *
17749  * These registers indicate the peripheral IDs. They are hardwired to specific
17750  * values used during the auto-discovery process by an external debug agent.
17751  */
17752 /*!
17753  * @name Constants and macros for entire ROM_PERIPHID5 register
17754  */
17755 /*@{*/
17756 #define ROM_RD_PERIPHID5(base)   (ROM_PERIPHID5_REG(base))
17757 /*@}*/
17758 
17759 /*******************************************************************************
17760  * ROM_PERIPHID6 - Peripheral ID Register
17761  ******************************************************************************/
17762 
17763 /*!
17764  * @brief ROM_PERIPHID6 - Peripheral ID Register (RO)
17765  *
17766  * Reset value: 0x00000000U
17767  *
17768  * These registers indicate the peripheral IDs. They are hardwired to specific
17769  * values used during the auto-discovery process by an external debug agent.
17770  */
17771 /*!
17772  * @name Constants and macros for entire ROM_PERIPHID6 register
17773  */
17774 /*@{*/
17775 #define ROM_RD_PERIPHID6(base)   (ROM_PERIPHID6_REG(base))
17776 /*@}*/
17777 
17778 /*******************************************************************************
17779  * ROM_PERIPHID7 - Peripheral ID Register
17780  ******************************************************************************/
17781 
17782 /*!
17783  * @brief ROM_PERIPHID7 - Peripheral ID Register (RO)
17784  *
17785  * Reset value: 0x00000000U
17786  *
17787  * These registers indicate the peripheral IDs. They are hardwired to specific
17788  * values used during the auto-discovery process by an external debug agent.
17789  */
17790 /*!
17791  * @name Constants and macros for entire ROM_PERIPHID7 register
17792  */
17793 /*@{*/
17794 #define ROM_RD_PERIPHID7(base)   (ROM_PERIPHID7_REG(base))
17795 /*@}*/
17796 
17797 /*******************************************************************************
17798  * ROM_PERIPHID0 - Peripheral ID Register
17799  ******************************************************************************/
17800 
17801 /*!
17802  * @brief ROM_PERIPHID0 - Peripheral ID Register (RO)
17803  *
17804  * Reset value: 0x00000000U
17805  *
17806  * These registers indicate the peripheral IDs. They are hardwired to specific
17807  * values used during the auto-discovery process by an external debug agent.
17808  */
17809 /*!
17810  * @name Constants and macros for entire ROM_PERIPHID0 register
17811  */
17812 /*@{*/
17813 #define ROM_RD_PERIPHID0(base)   (ROM_PERIPHID0_REG(base))
17814 /*@}*/
17815 
17816 /*******************************************************************************
17817  * ROM_PERIPHID1 - Peripheral ID Register
17818  ******************************************************************************/
17819 
17820 /*!
17821  * @brief ROM_PERIPHID1 - Peripheral ID Register (RO)
17822  *
17823  * Reset value: 0x00000000U
17824  *
17825  * These registers indicate the peripheral IDs. They are hardwired to specific
17826  * values used during the auto-discovery process by an external debug agent.
17827  */
17828 /*!
17829  * @name Constants and macros for entire ROM_PERIPHID1 register
17830  */
17831 /*@{*/
17832 #define ROM_RD_PERIPHID1(base)   (ROM_PERIPHID1_REG(base))
17833 /*@}*/
17834 
17835 /*******************************************************************************
17836  * ROM_PERIPHID2 - Peripheral ID Register
17837  ******************************************************************************/
17838 
17839 /*!
17840  * @brief ROM_PERIPHID2 - Peripheral ID Register (RO)
17841  *
17842  * Reset value: 0x00000000U
17843  *
17844  * These registers indicate the peripheral IDs. They are hardwired to specific
17845  * values used during the auto-discovery process by an external debug agent.
17846  */
17847 /*!
17848  * @name Constants and macros for entire ROM_PERIPHID2 register
17849  */
17850 /*@{*/
17851 #define ROM_RD_PERIPHID2(base)   (ROM_PERIPHID2_REG(base))
17852 /*@}*/
17853 
17854 /*******************************************************************************
17855  * ROM_PERIPHID3 - Peripheral ID Register
17856  ******************************************************************************/
17857 
17858 /*!
17859  * @brief ROM_PERIPHID3 - Peripheral ID Register (RO)
17860  *
17861  * Reset value: 0x00000000U
17862  *
17863  * These registers indicate the peripheral IDs. They are hardwired to specific
17864  * values used during the auto-discovery process by an external debug agent.
17865  */
17866 /*!
17867  * @name Constants and macros for entire ROM_PERIPHID3 register
17868  */
17869 /*@{*/
17870 #define ROM_RD_PERIPHID3(base)   (ROM_PERIPHID3_REG(base))
17871 /*@}*/
17872 
17873 /*******************************************************************************
17874  * ROM_COMPID - Component ID Register
17875  ******************************************************************************/
17876 
17877 /*!
17878  * @brief ROM_COMPID - Component ID Register (RO)
17879  *
17880  * Reset value: 0x00000000U
17881  *
17882  * These registers indicate the component IDs. They are hardwired to specific
17883  * values used during the auto-discovery process by an external debug agent.
17884  */
17885 /*!
17886  * @name Constants and macros for entire ROM_COMPID register
17887  */
17888 /*@{*/
17889 #define ROM_RD_COMPID(base, index) (ROM_COMPID_REG(base, index))
17890 /*@}*/
17891 
17892 /*
17893  * MKW40Z4 RSIM
17894  *
17895  * Radio System Integration Module
17896  *
17897  * Registers defined in this header file:
17898  * - RSIM_CONTROL - RSIM Control
17899  * - RSIM_ACTIVE_DELAY - RSIM BLE Active Delay
17900  * - RSIM_MAC_MSB - RSIM MAC MSB
17901  * - RSIM_MAC_LSB - RSIM MAC LSB
17902  * - RSIM_ANA_TEST - RSIM Analog Test
17903  */
17904 
17905 #define RSIM_INSTANCE_COUNT (1U) /*!< Number of instances of the RSIM module. */
17906 #define RSIM_IDX (0U) /*!< Instance number for RSIM. */
17907 
17908 /*******************************************************************************
17909  * RSIM_CONTROL - RSIM Control
17910  ******************************************************************************/
17911 
17912 /*!
17913  * @brief RSIM_CONTROL - RSIM Control (RW)
17914  *
17915  * Reset value: 0x00C00000U
17916  *
17917  * The RSIM Control register provides various control bits for the Radio System
17918  * and for its interaction with the SoC Systems.
17919  */
17920 /*!
17921  * @name Constants and macros for entire RSIM_CONTROL register
17922  */
17923 /*@{*/
17924 #define RSIM_RD_CONTROL(base)    (RSIM_CONTROL_REG(base))
17925 #define RSIM_WR_CONTROL(base, value) (RSIM_CONTROL_REG(base) = (value))
17926 #define RSIM_RMW_CONTROL(base, mask, value) (RSIM_WR_CONTROL(base, (RSIM_RD_CONTROL(base) & ~(mask)) | (value)))
17927 #define RSIM_SET_CONTROL(base, value) (BME_OR32(&RSIM_CONTROL_REG(base), (uint32_t)(value)))
17928 #define RSIM_CLR_CONTROL(base, value) (BME_AND32(&RSIM_CONTROL_REG(base), (uint32_t)(~(value))))
17929 #define RSIM_TOG_CONTROL(base, value) (BME_XOR32(&RSIM_CONTROL_REG(base), (uint32_t)(value)))
17930 /*@}*/
17931 
17932 /*
17933  * Constants & macros for individual RSIM_CONTROL bitfields
17934  */
17935 
17936 /*!
17937  * @name Register RSIM_CONTROL, field BLE_RF_OSC_REQ_EN[0] (RW)
17938  *
17939  * This bit resets on POR only. If this bit is cleared (the default state), then
17940  * all BLE link layer requests to turn on the RF Ref Oscillator (Sysclk Req)
17941  * will be blocked and ignored. In BLE protocols the BLE link layer will always
17942  * restart when exiting reset by first Requesting the RF Ref Osc (Sysclk Req), this
17943  * bit blocks that behavior until software configures the Radio and enables the
17944  * requests.
17945  */
17946 /*@{*/
17947 /*! @brief Read current value of the RSIM_CONTROL_BLE_RF_OSC_REQ_EN field. */
17948 #define RSIM_RD_CONTROL_BLE_RF_OSC_REQ_EN(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_BLE_RF_OSC_REQ_EN_MASK) >> RSIM_CONTROL_BLE_RF_OSC_REQ_EN_SHIFT)
17949 #define RSIM_BRD_CONTROL_BLE_RF_OSC_REQ_EN(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_BLE_RF_OSC_REQ_EN_SHIFT, RSIM_CONTROL_BLE_RF_OSC_REQ_EN_WIDTH))
17950 
17951 /*! @brief Set the BLE_RF_OSC_REQ_EN field to a new value. */
17952 #define RSIM_WR_CONTROL_BLE_RF_OSC_REQ_EN(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_BLE_RF_OSC_REQ_EN_MASK | RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK), RSIM_CONTROL_BLE_RF_OSC_REQ_EN(value)))
17953 #define RSIM_BWR_CONTROL_BLE_RF_OSC_REQ_EN(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)(value) << RSIM_CONTROL_BLE_RF_OSC_REQ_EN_SHIFT), RSIM_CONTROL_BLE_RF_OSC_REQ_EN_SHIFT, RSIM_CONTROL_BLE_RF_OSC_REQ_EN_WIDTH))
17954 /*@}*/
17955 
17956 /*!
17957  * @name Register RSIM_CONTROL, field BLE_RF_OSC_REQ_STAT[1] (RO)
17958  *
17959  * This bit indicates the current status of the BLE link layer request to turn
17960  * on the RF Ref Oscillator (Sysclk Req).
17961  */
17962 /*@{*/
17963 /*! @brief Read current value of the RSIM_CONTROL_BLE_RF_OSC_REQ_STAT field. */
17964 #define RSIM_RD_CONTROL_BLE_RF_OSC_REQ_STAT(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_BLE_RF_OSC_REQ_STAT_MASK) >> RSIM_CONTROL_BLE_RF_OSC_REQ_STAT_SHIFT)
17965 #define RSIM_BRD_CONTROL_BLE_RF_OSC_REQ_STAT(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_BLE_RF_OSC_REQ_STAT_SHIFT, RSIM_CONTROL_BLE_RF_OSC_REQ_STAT_WIDTH))
17966 /*@}*/
17967 
17968 /*!
17969  * @name Register RSIM_CONTROL, field BLE_RF_OSC_REQ_INT_EN[4] (RW)
17970  *
17971  * This bit enables an interrupt request when the enabled version of the BLE Ref
17972  * Osc (Sysclk) Request is asserted high.
17973  */
17974 /*@{*/
17975 /*! @brief Read current value of the RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN field. */
17976 #define RSIM_RD_CONTROL_BLE_RF_OSC_REQ_INT_EN(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN_MASK) >> RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN_SHIFT)
17977 #define RSIM_BRD_CONTROL_BLE_RF_OSC_REQ_INT_EN(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN_SHIFT, RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN_WIDTH))
17978 
17979 /*! @brief Set the BLE_RF_OSC_REQ_INT_EN field to a new value. */
17980 #define RSIM_WR_CONTROL_BLE_RF_OSC_REQ_INT_EN(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN_MASK | RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK), RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN(value)))
17981 #define RSIM_BWR_CONTROL_BLE_RF_OSC_REQ_INT_EN(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)(value) << RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN_SHIFT), RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN_SHIFT, RSIM_CONTROL_BLE_RF_OSC_REQ_INT_EN_WIDTH))
17982 /*@}*/
17983 
17984 /*!
17985  * @name Register RSIM_CONTROL, field BLE_RF_OSC_REQ_INT[5] (W1C)
17986  *
17987  * This bit is an interrupt flag that is set when the enabled version of the BLE
17988  * Ref Osc (Sysclk) Request is asserted high. This interrupt flag is cleared by
17989  * writing a 1 to it.
17990  */
17991 /*@{*/
17992 /*! @brief Read current value of the RSIM_CONTROL_BLE_RF_OSC_REQ_INT field. */
17993 #define RSIM_RD_CONTROL_BLE_RF_OSC_REQ_INT(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK) >> RSIM_CONTROL_BLE_RF_OSC_REQ_INT_SHIFT)
17994 #define RSIM_BRD_CONTROL_BLE_RF_OSC_REQ_INT(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_BLE_RF_OSC_REQ_INT_SHIFT, RSIM_CONTROL_BLE_RF_OSC_REQ_INT_WIDTH))
17995 
17996 /*! @brief Set the BLE_RF_OSC_REQ_INT field to a new value. */
17997 #define RSIM_WR_CONTROL_BLE_RF_OSC_REQ_INT(base, value) (RSIM_RMW_CONTROL(base, RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK, RSIM_CONTROL_BLE_RF_OSC_REQ_INT(value)))
17998 #define RSIM_BWR_CONTROL_BLE_RF_OSC_REQ_INT(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)(value) << RSIM_CONTROL_BLE_RF_OSC_REQ_INT_SHIFT), RSIM_CONTROL_BLE_RF_OSC_REQ_INT_SHIFT, RSIM_CONTROL_BLE_RF_OSC_REQ_INT_WIDTH))
17999 /*@}*/
18000 
18001 /*!
18002  * @name Register RSIM_CONTROL, field RF_OSC_EN[11:8] (RW)
18003  *
18004  * The RF Reference Oscillator can be enabled by the BLE link layer, by an SoC
18005  * MCG mode, or by these bits. If these bits are all cleared, 0000, then the RF
18006  * Ref Osc will be controlled by the SoC or the BLE link layer. If any of these
18007  * bits are set then the RF Ref Osc will be on in the SoC power modes as shown
18008  * below. Note that the enables are additive; each bit adds another low power mode.
18009  *
18010  * Values:
18011  * - 0b0000 - RF Ref Osc will be controlled by the SoC or the BLE link layer
18012  * - 0b0001 - RF Ref Osc on in Run/Wait
18013  * - 0b0011 - RF Ref Osc on in Stop
18014  * - 0b0111 - RF Ref Osc on in VLPR/VLPW
18015  * - 0b1111 - RF Ref Osc on in VLPS
18016  */
18017 /*@{*/
18018 /*! @brief Read current value of the RSIM_CONTROL_RF_OSC_EN field. */
18019 #define RSIM_RD_CONTROL_RF_OSC_EN(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_RF_OSC_EN_MASK) >> RSIM_CONTROL_RF_OSC_EN_SHIFT)
18020 #define RSIM_BRD_CONTROL_RF_OSC_EN(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_RF_OSC_EN_SHIFT, RSIM_CONTROL_RF_OSC_EN_WIDTH))
18021 
18022 /*! @brief Set the RF_OSC_EN field to a new value. */
18023 #define RSIM_WR_CONTROL_RF_OSC_EN(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_RF_OSC_EN_MASK | RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK), RSIM_CONTROL_RF_OSC_EN(value)))
18024 #define RSIM_BWR_CONTROL_RF_OSC_EN(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)(value) << RSIM_CONTROL_RF_OSC_EN_SHIFT), RSIM_CONTROL_RF_OSC_EN_SHIFT, RSIM_CONTROL_RF_OSC_EN_WIDTH))
18025 /*@}*/
18026 
18027 /*!
18028  * @name Register RSIM_CONTROL, field GASKET_BYPASS_OVRD_EN[12] (RW)
18029  *
18030  * The SoC platform has an asynchronous gasket that allows register access for
18031  * the Radio registers in all SoC clocking modes. This bit allows software to
18032  * directly control the SoC platform asynchronous gasket bypass signal.
18033  */
18034 /*@{*/
18035 /*! @brief Read current value of the RSIM_CONTROL_GASKET_BYPASS_OVRD_EN field. */
18036 #define RSIM_RD_CONTROL_GASKET_BYPASS_OVRD_EN(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_GASKET_BYPASS_OVRD_EN_MASK) >> RSIM_CONTROL_GASKET_BYPASS_OVRD_EN_SHIFT)
18037 #define RSIM_BRD_CONTROL_GASKET_BYPASS_OVRD_EN(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_GASKET_BYPASS_OVRD_EN_SHIFT, RSIM_CONTROL_GASKET_BYPASS_OVRD_EN_WIDTH))
18038 
18039 /*! @brief Set the GASKET_BYPASS_OVRD_EN field to a new value. */
18040 #define RSIM_WR_CONTROL_GASKET_BYPASS_OVRD_EN(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_GASKET_BYPASS_OVRD_EN_MASK | RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK), RSIM_CONTROL_GASKET_BYPASS_OVRD_EN(value)))
18041 #define RSIM_BWR_CONTROL_GASKET_BYPASS_OVRD_EN(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)(value) << RSIM_CONTROL_GASKET_BYPASS_OVRD_EN_SHIFT), RSIM_CONTROL_GASKET_BYPASS_OVRD_EN_SHIFT, RSIM_CONTROL_GASKET_BYPASS_OVRD_EN_WIDTH))
18042 /*@}*/
18043 
18044 /*!
18045  * @name Register RSIM_CONTROL, field GASKET_BYPASS_OVRD[13] (RW)
18046  *
18047  * This bit directly controls the SoC platform asynchronous gasket bypass signal
18048  * when the Gasket Bypass Override is enabled. The default behavior of the SoC
18049  * Asynchronous Gasket is Not Bypassed, which means the Radio registers are
18050  * accessed using the RF Ref Osc clock. The Radio sends the RF Ref Osc to the
18051  * asynchronous gasket which then uses that clock for SoC register accesses of the Radio
18052  * registers. This requires the RF Ref Osc to be Enabled and Ready. If the RF Ref
18053  * Osc is not Enabled and Ready, then the IPS Gasket can be overridden to be in
18054  * Bypass Mode, which forces the use of the SoC IPG clock as the register access
18055  * clock. If the RF Ref Osc IS Enabled and Ready, then the IPS Gasket can be
18056  * overridden to be in Bypass Mode, but this is an ILLEGALL ACCESS if the Radio is
18057  * operational, DO NOT write Radio registers with the Asynchronous Gasket Bypassed
18058  * when the Radio is Operating. Test mode access is allowed but glitches may
18059  * occur. The intent of Bypass Mode is to allow software to configure the Radio before
18060  * the RF Ref Osc is Enabled and Ready. Note that the BLE Link Layer registers
18061  * can only be accessed when the RF Ref Osc is Enabled and Ready. The following
18062  * table shows which clock is being used to access the Radio XCVR and Zigbee
18063  * registers. Gasket Bypass Override Enable Gasket Bypass Override XCVR and Zigbee
18064  * Register Clock 1 0 RF Ref Osc Clock 1 1 SoC IPG Clock 0 x RF Ref Osc Clock
18065  */
18066 /*@{*/
18067 /*! @brief Read current value of the RSIM_CONTROL_GASKET_BYPASS_OVRD field. */
18068 #define RSIM_RD_CONTROL_GASKET_BYPASS_OVRD(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_GASKET_BYPASS_OVRD_MASK) >> RSIM_CONTROL_GASKET_BYPASS_OVRD_SHIFT)
18069 #define RSIM_BRD_CONTROL_GASKET_BYPASS_OVRD(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_GASKET_BYPASS_OVRD_SHIFT, RSIM_CONTROL_GASKET_BYPASS_OVRD_WIDTH))
18070 
18071 /*! @brief Set the GASKET_BYPASS_OVRD field to a new value. */
18072 #define RSIM_WR_CONTROL_GASKET_BYPASS_OVRD(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_GASKET_BYPASS_OVRD_MASK | RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK), RSIM_CONTROL_GASKET_BYPASS_OVRD(value)))
18073 #define RSIM_BWR_CONTROL_GASKET_BYPASS_OVRD(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)(value) << RSIM_CONTROL_GASKET_BYPASS_OVRD_SHIFT), RSIM_CONTROL_GASKET_BYPASS_OVRD_SHIFT, RSIM_CONTROL_GASKET_BYPASS_OVRD_WIDTH))
18074 /*@}*/
18075 
18076 /*!
18077  * @name Register RSIM_CONTROL, field RF_OSC_BYPASS_EN[14] (RW)
18078  *
18079  * This bit engages the RF Ref Osc analog bypass circuit if the RF Ref Osc is
18080  * enabled. When the RF Ref Osc is in bypass mode it passes the EXTAL clock as the
18081  * RF Ref Osc clock. Note that the RF Ref Osc Ready signal is always asserted in
18082  * RF Ref Osc Bypass mode, unless overridden with the RF_OSC_READY_OVRD_EN bit.
18083  */
18084 /*@{*/
18085 /*! @brief Read current value of the RSIM_CONTROL_RF_OSC_BYPASS_EN field. */
18086 #define RSIM_RD_CONTROL_RF_OSC_BYPASS_EN(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_RF_OSC_BYPASS_EN_MASK) >> RSIM_CONTROL_RF_OSC_BYPASS_EN_SHIFT)
18087 #define RSIM_BRD_CONTROL_RF_OSC_BYPASS_EN(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_RF_OSC_BYPASS_EN_SHIFT, RSIM_CONTROL_RF_OSC_BYPASS_EN_WIDTH))
18088 
18089 /*! @brief Set the RF_OSC_BYPASS_EN field to a new value. */
18090 #define RSIM_WR_CONTROL_RF_OSC_BYPASS_EN(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_RF_OSC_BYPASS_EN_MASK | RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK), RSIM_CONTROL_RF_OSC_BYPASS_EN(value)))
18091 #define RSIM_BWR_CONTROL_RF_OSC_BYPASS_EN(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)(value) << RSIM_CONTROL_RF_OSC_BYPASS_EN_SHIFT), RSIM_CONTROL_RF_OSC_BYPASS_EN_SHIFT, RSIM_CONTROL_RF_OSC_BYPASS_EN_WIDTH))
18092 /*@}*/
18093 
18094 /*!
18095  * @name Register RSIM_CONTROL, field BLE_ACTIVE_PORT_1_SEL[16] (RW)
18096  *
18097  * This bit enables the Output Driver (OBE) on the SoC port 1 that provides the
18098  * BLE Active signal as a pad interface option.
18099  */
18100 /*@{*/
18101 /*! @brief Read current value of the RSIM_CONTROL_BLE_ACTIVE_PORT_1_SEL field. */
18102 #define RSIM_RD_CONTROL_BLE_ACTIVE_PORT_1_SEL(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_BLE_ACTIVE_PORT_1_SEL_MASK) >> RSIM_CONTROL_BLE_ACTIVE_PORT_1_SEL_SHIFT)
18103 #define RSIM_BRD_CONTROL_BLE_ACTIVE_PORT_1_SEL(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_BLE_ACTIVE_PORT_1_SEL_SHIFT, RSIM_CONTROL_BLE_ACTIVE_PORT_1_SEL_WIDTH))
18104 
18105 /*! @brief Set the BLE_ACTIVE_PORT_1_SEL field to a new value. */
18106 #define RSIM_WR_CONTROL_BLE_ACTIVE_PORT_1_SEL(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_BLE_ACTIVE_PORT_1_SEL_MASK | RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK), RSIM_CONTROL_BLE_ACTIVE_PORT_1_SEL(value)))
18107 #define RSIM_BWR_CONTROL_BLE_ACTIVE_PORT_1_SEL(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)(value) << RSIM_CONTROL_BLE_ACTIVE_PORT_1_SEL_SHIFT), RSIM_CONTROL_BLE_ACTIVE_PORT_1_SEL_SHIFT, RSIM_CONTROL_BLE_ACTIVE_PORT_1_SEL_WIDTH))
18108 /*@}*/
18109 
18110 /*!
18111  * @name Register RSIM_CONTROL, field BLE_ACTIVE_PORT_2_SEL[17] (RW)
18112  *
18113  * This bit enables the Output Driver (OBE) on the SoC port 2 that provides the
18114  * BLE Active signal as a pad interface option.
18115  */
18116 /*@{*/
18117 /*! @brief Read current value of the RSIM_CONTROL_BLE_ACTIVE_PORT_2_SEL field. */
18118 #define RSIM_RD_CONTROL_BLE_ACTIVE_PORT_2_SEL(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_BLE_ACTIVE_PORT_2_SEL_MASK) >> RSIM_CONTROL_BLE_ACTIVE_PORT_2_SEL_SHIFT)
18119 #define RSIM_BRD_CONTROL_BLE_ACTIVE_PORT_2_SEL(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_BLE_ACTIVE_PORT_2_SEL_SHIFT, RSIM_CONTROL_BLE_ACTIVE_PORT_2_SEL_WIDTH))
18120 
18121 /*! @brief Set the BLE_ACTIVE_PORT_2_SEL field to a new value. */
18122 #define RSIM_WR_CONTROL_BLE_ACTIVE_PORT_2_SEL(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_BLE_ACTIVE_PORT_2_SEL_MASK | RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK), RSIM_CONTROL_BLE_ACTIVE_PORT_2_SEL(value)))
18123 #define RSIM_BWR_CONTROL_BLE_ACTIVE_PORT_2_SEL(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)(value) << RSIM_CONTROL_BLE_ACTIVE_PORT_2_SEL_SHIFT), RSIM_CONTROL_BLE_ACTIVE_PORT_2_SEL_SHIFT, RSIM_CONTROL_BLE_ACTIVE_PORT_2_SEL_WIDTH))
18124 /*@}*/
18125 
18126 /*!
18127  * @name Register RSIM_CONTROL, field BLE_DEEP_SLEEP_EXIT[20] (RW)
18128  *
18129  * This bit forces the BLE link layer to wakeup from Deep Sleep Mode.
18130  */
18131 /*@{*/
18132 /*! @brief Read current value of the RSIM_CONTROL_BLE_DEEP_SLEEP_EXIT field. */
18133 #define RSIM_RD_CONTROL_BLE_DEEP_SLEEP_EXIT(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_BLE_DEEP_SLEEP_EXIT_MASK) >> RSIM_CONTROL_BLE_DEEP_SLEEP_EXIT_SHIFT)
18134 #define RSIM_BRD_CONTROL_BLE_DEEP_SLEEP_EXIT(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_BLE_DEEP_SLEEP_EXIT_SHIFT, RSIM_CONTROL_BLE_DEEP_SLEEP_EXIT_WIDTH))
18135 
18136 /*! @brief Set the BLE_DEEP_SLEEP_EXIT field to a new value. */
18137 #define RSIM_WR_CONTROL_BLE_DEEP_SLEEP_EXIT(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_BLE_DEEP_SLEEP_EXIT_MASK | RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK), RSIM_CONTROL_BLE_DEEP_SLEEP_EXIT(value)))
18138 #define RSIM_BWR_CONTROL_BLE_DEEP_SLEEP_EXIT(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)(value) << RSIM_CONTROL_BLE_DEEP_SLEEP_EXIT_SHIFT), RSIM_CONTROL_BLE_DEEP_SLEEP_EXIT_SHIFT, RSIM_CONTROL_BLE_DEEP_SLEEP_EXIT_WIDTH))
18139 /*@}*/
18140 
18141 /*!
18142  * @name Register RSIM_CONTROL, field STOP_ACK_OVRD_EN[22] (RW)
18143  *
18144  * This bit enables an override of the Stop Acknowledge signal. If not
18145  * overwritten, Radio Stop Acknowledge is nominally based on the enabled version of the
18146  * BLE Ref Osc (Sysclk) Request. The following table shows the state of the nominal
18147  * Radio Stop Acknowledge signal as presented to the SoC Core Platform BLE Ref
18148  * Osc (Sysclk) Request Enable BLE Ref Osc (Sysclk) Request Radio Stop Acknowledge
18149  * to SoC 1 0 1 1 1 0 0 x 1
18150  */
18151 /*@{*/
18152 /*! @brief Read current value of the RSIM_CONTROL_STOP_ACK_OVRD_EN field. */
18153 #define RSIM_RD_CONTROL_STOP_ACK_OVRD_EN(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_STOP_ACK_OVRD_EN_MASK) >> RSIM_CONTROL_STOP_ACK_OVRD_EN_SHIFT)
18154 #define RSIM_BRD_CONTROL_STOP_ACK_OVRD_EN(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_STOP_ACK_OVRD_EN_SHIFT, RSIM_CONTROL_STOP_ACK_OVRD_EN_WIDTH))
18155 
18156 /*! @brief Set the STOP_ACK_OVRD_EN field to a new value. */
18157 #define RSIM_WR_CONTROL_STOP_ACK_OVRD_EN(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_STOP_ACK_OVRD_EN_MASK | RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK), RSIM_CONTROL_STOP_ACK_OVRD_EN(value)))
18158 #define RSIM_BWR_CONTROL_STOP_ACK_OVRD_EN(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)(value) << RSIM_CONTROL_STOP_ACK_OVRD_EN_SHIFT), RSIM_CONTROL_STOP_ACK_OVRD_EN_SHIFT, RSIM_CONTROL_STOP_ACK_OVRD_EN_WIDTH))
18159 /*@}*/
18160 
18161 /*!
18162  * @name Register RSIM_CONTROL, field STOP_ACK_OVRD[23] (RW)
18163  *
18164  * This bit controls the Stop Acknowledge signal to the SoC Core Platform in
18165  * Override mode.
18166  */
18167 /*@{*/
18168 /*! @brief Read current value of the RSIM_CONTROL_STOP_ACK_OVRD field. */
18169 #define RSIM_RD_CONTROL_STOP_ACK_OVRD(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_STOP_ACK_OVRD_MASK) >> RSIM_CONTROL_STOP_ACK_OVRD_SHIFT)
18170 #define RSIM_BRD_CONTROL_STOP_ACK_OVRD(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_STOP_ACK_OVRD_SHIFT, RSIM_CONTROL_STOP_ACK_OVRD_WIDTH))
18171 
18172 /*! @brief Set the STOP_ACK_OVRD field to a new value. */
18173 #define RSIM_WR_CONTROL_STOP_ACK_OVRD(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_STOP_ACK_OVRD_MASK | RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK), RSIM_CONTROL_STOP_ACK_OVRD(value)))
18174 #define RSIM_BWR_CONTROL_STOP_ACK_OVRD(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)(value) << RSIM_CONTROL_STOP_ACK_OVRD_SHIFT), RSIM_CONTROL_STOP_ACK_OVRD_SHIFT, RSIM_CONTROL_STOP_ACK_OVRD_WIDTH))
18175 /*@}*/
18176 
18177 /*!
18178  * @name Register RSIM_CONTROL, field RF_OSC_READY[24] (RO)
18179  *
18180  * The RF Reference Oscillator has an internal counter that gates off the RF Ref
18181  * Osc clock until the selected count is reached. This bit shows the status of
18182  * the RF Ref Osc ready signal that comes from that counter, except in RF Ref Osc
18183  * Bypass Mode. In RF Ref Osc Bypass Mode this bit will always be asserted, but
18184  * the signals that are derived from the RF Ref Osc Ready signal can be overridden
18185  * using the RF_OSC_READY_OVRD bit
18186  */
18187 /*@{*/
18188 /*! @brief Read current value of the RSIM_CONTROL_RF_OSC_READY field. */
18189 #define RSIM_RD_CONTROL_RF_OSC_READY(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_RF_OSC_READY_MASK) >> RSIM_CONTROL_RF_OSC_READY_SHIFT)
18190 #define RSIM_BRD_CONTROL_RF_OSC_READY(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_RF_OSC_READY_SHIFT, RSIM_CONTROL_RF_OSC_READY_WIDTH))
18191 /*@}*/
18192 
18193 /*!
18194  * @name Register RSIM_CONTROL, field RF_OSC_READY_OVRD_EN[25] (RW)
18195  *
18196  * This bit enables the RF Ref Osc Ready Override bit.
18197  */
18198 /*@{*/
18199 /*! @brief Read current value of the RSIM_CONTROL_RF_OSC_READY_OVRD_EN field. */
18200 #define RSIM_RD_CONTROL_RF_OSC_READY_OVRD_EN(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_RF_OSC_READY_OVRD_EN_MASK) >> RSIM_CONTROL_RF_OSC_READY_OVRD_EN_SHIFT)
18201 #define RSIM_BRD_CONTROL_RF_OSC_READY_OVRD_EN(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_RF_OSC_READY_OVRD_EN_SHIFT, RSIM_CONTROL_RF_OSC_READY_OVRD_EN_WIDTH))
18202 
18203 /*! @brief Set the RF_OSC_READY_OVRD_EN field to a new value. */
18204 #define RSIM_WR_CONTROL_RF_OSC_READY_OVRD_EN(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_RF_OSC_READY_OVRD_EN_MASK | RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK), RSIM_CONTROL_RF_OSC_READY_OVRD_EN(value)))
18205 #define RSIM_BWR_CONTROL_RF_OSC_READY_OVRD_EN(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)(value) << RSIM_CONTROL_RF_OSC_READY_OVRD_EN_SHIFT), RSIM_CONTROL_RF_OSC_READY_OVRD_EN_SHIFT, RSIM_CONTROL_RF_OSC_READY_OVRD_EN_WIDTH))
18206 /*@}*/
18207 
18208 /*!
18209  * @name Register RSIM_CONTROL, field RF_OSC_READY_OVRD[26] (RW)
18210  *
18211  * This bit directly controls the Radio RF Ref Osc Ready signal when the RF Ref
18212  * Osc Ready Override is enabled. All Radio and SoC signals that are derived from
18213  * the RF Ref Osc Ready signal can be overridden using this bit.
18214  */
18215 /*@{*/
18216 /*! @brief Read current value of the RSIM_CONTROL_RF_OSC_READY_OVRD field. */
18217 #define RSIM_RD_CONTROL_RF_OSC_READY_OVRD(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_RF_OSC_READY_OVRD_MASK) >> RSIM_CONTROL_RF_OSC_READY_OVRD_SHIFT)
18218 #define RSIM_BRD_CONTROL_RF_OSC_READY_OVRD(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_RF_OSC_READY_OVRD_SHIFT, RSIM_CONTROL_RF_OSC_READY_OVRD_WIDTH))
18219 
18220 /*! @brief Set the RF_OSC_READY_OVRD field to a new value. */
18221 #define RSIM_WR_CONTROL_RF_OSC_READY_OVRD(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_RF_OSC_READY_OVRD_MASK | RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK), RSIM_CONTROL_RF_OSC_READY_OVRD(value)))
18222 #define RSIM_BWR_CONTROL_RF_OSC_READY_OVRD(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)(value) << RSIM_CONTROL_RF_OSC_READY_OVRD_SHIFT), RSIM_CONTROL_RF_OSC_READY_OVRD_SHIFT, RSIM_CONTROL_RF_OSC_READY_OVRD_WIDTH))
18223 /*@}*/
18224 
18225 /*!
18226  * @name Register RSIM_CONTROL, field BLOCK_RADIO_RESETS[28] (RW)
18227  *
18228  * This bit resets on POR only. This bit is intended to allow the SoC to perform
18229  * concurrent testing of various SoC logic while the Radio is operating
18230  * independently. Any SoC resets will be blocked and the Radio will not be affected by
18231  * them when this bit is set.
18232  */
18233 /*@{*/
18234 /*! @brief Read current value of the RSIM_CONTROL_BLOCK_RADIO_RESETS field. */
18235 #define RSIM_RD_CONTROL_BLOCK_RADIO_RESETS(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_BLOCK_RADIO_RESETS_MASK) >> RSIM_CONTROL_BLOCK_RADIO_RESETS_SHIFT)
18236 #define RSIM_BRD_CONTROL_BLOCK_RADIO_RESETS(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_BLOCK_RADIO_RESETS_SHIFT, RSIM_CONTROL_BLOCK_RADIO_RESETS_WIDTH))
18237 
18238 /*! @brief Set the BLOCK_RADIO_RESETS field to a new value. */
18239 #define RSIM_WR_CONTROL_BLOCK_RADIO_RESETS(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_BLOCK_RADIO_RESETS_MASK | RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK), RSIM_CONTROL_BLOCK_RADIO_RESETS(value)))
18240 #define RSIM_BWR_CONTROL_BLOCK_RADIO_RESETS(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)(value) << RSIM_CONTROL_BLOCK_RADIO_RESETS_SHIFT), RSIM_CONTROL_BLOCK_RADIO_RESETS_SHIFT, RSIM_CONTROL_BLOCK_RADIO_RESETS_WIDTH))
18241 /*@}*/
18242 
18243 /*!
18244  * @name Register RSIM_CONTROL, field BLOCK_RADIO_OUTPUTS[29] (RW)
18245  *
18246  * This bit resets on POR only. This bit is intended to allow the SoC to perform
18247  * concurrent testing of various SoC logic while the Radio is operating
18248  * independently. Any Radio output signals that go to the SoC will be blocked so as to
18249  * not affect the SoC testing when this bit is set.
18250  */
18251 /*@{*/
18252 /*! @brief Read current value of the RSIM_CONTROL_BLOCK_RADIO_OUTPUTS field. */
18253 #define RSIM_RD_CONTROL_BLOCK_RADIO_OUTPUTS(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_BLOCK_RADIO_OUTPUTS_MASK) >> RSIM_CONTROL_BLOCK_RADIO_OUTPUTS_SHIFT)
18254 #define RSIM_BRD_CONTROL_BLOCK_RADIO_OUTPUTS(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_BLOCK_RADIO_OUTPUTS_SHIFT, RSIM_CONTROL_BLOCK_RADIO_OUTPUTS_WIDTH))
18255 
18256 /*! @brief Set the BLOCK_RADIO_OUTPUTS field to a new value. */
18257 #define RSIM_WR_CONTROL_BLOCK_RADIO_OUTPUTS(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_BLOCK_RADIO_OUTPUTS_MASK | RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK), RSIM_CONTROL_BLOCK_RADIO_OUTPUTS(value)))
18258 #define RSIM_BWR_CONTROL_BLOCK_RADIO_OUTPUTS(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)(value) << RSIM_CONTROL_BLOCK_RADIO_OUTPUTS_SHIFT), RSIM_CONTROL_BLOCK_RADIO_OUTPUTS_SHIFT, RSIM_CONTROL_BLOCK_RADIO_OUTPUTS_WIDTH))
18259 /*@}*/
18260 
18261 /*!
18262  * @name Register RSIM_CONTROL, field RADIO_RESET[31] (RW)
18263  *
18264  * This bit resets on POR only. When the Radio Resets are Blocked, setting this
18265  * bit will reset all the radio logic until this bit is cleared. Note that due to
18266  * internal Radio Reset Exit synchronizing logic there must be a second access
18267  * to an RSIM register to clear this software reset, so please write this bit to 0
18268  * twice when clearing it.
18269  */
18270 /*@{*/
18271 /*! @brief Read current value of the RSIM_CONTROL_RADIO_RESET field. */
18272 #define RSIM_RD_CONTROL_RADIO_RESET(base) ((RSIM_CONTROL_REG(base) & RSIM_CONTROL_RADIO_RESET_MASK) >> RSIM_CONTROL_RADIO_RESET_SHIFT)
18273 #define RSIM_BRD_CONTROL_RADIO_RESET(base) (BME_UBFX32(&RSIM_CONTROL_REG(base), RSIM_CONTROL_RADIO_RESET_SHIFT, RSIM_CONTROL_RADIO_RESET_WIDTH))
18274 
18275 /*! @brief Set the RADIO_RESET field to a new value. */
18276 #define RSIM_WR_CONTROL_RADIO_RESET(base, value) (RSIM_RMW_CONTROL(base, (RSIM_CONTROL_RADIO_RESET_MASK | RSIM_CONTROL_BLE_RF_OSC_REQ_INT_MASK), RSIM_CONTROL_RADIO_RESET(value)))
18277 #define RSIM_BWR_CONTROL_RADIO_RESET(base, value) (BME_BFI32(&RSIM_CONTROL_REG(base), ((uint32_t)(value) << RSIM_CONTROL_RADIO_RESET_SHIFT), RSIM_CONTROL_RADIO_RESET_SHIFT, RSIM_CONTROL_RADIO_RESET_WIDTH))
18278 /*@}*/
18279 
18280 /*******************************************************************************
18281  * RSIM_ACTIVE_DELAY - RSIM BLE Active Delay
18282  ******************************************************************************/
18283 
18284 /*!
18285  * @brief RSIM_ACTIVE_DELAY - RSIM BLE Active Delay (RW)
18286  *
18287  * Reset value: 0x00000000U
18288  *
18289  * The RSIM BLE Active Delay register provides control bits to adjust the delay
18290  * of the BLE Active signal that is presented to the SoC Flash System.
18291  */
18292 /*!
18293  * @name Constants and macros for entire RSIM_ACTIVE_DELAY register
18294  */
18295 /*@{*/
18296 #define RSIM_RD_ACTIVE_DELAY(base) (RSIM_ACTIVE_DELAY_REG(base))
18297 #define RSIM_WR_ACTIVE_DELAY(base, value) (RSIM_ACTIVE_DELAY_REG(base) = (value))
18298 #define RSIM_RMW_ACTIVE_DELAY(base, mask, value) (RSIM_WR_ACTIVE_DELAY(base, (RSIM_RD_ACTIVE_DELAY(base) & ~(mask)) | (value)))
18299 #define RSIM_SET_ACTIVE_DELAY(base, value) (BME_OR32(&RSIM_ACTIVE_DELAY_REG(base), (uint32_t)(value)))
18300 #define RSIM_CLR_ACTIVE_DELAY(base, value) (BME_AND32(&RSIM_ACTIVE_DELAY_REG(base), (uint32_t)(~(value))))
18301 #define RSIM_TOG_ACTIVE_DELAY(base, value) (BME_XOR32(&RSIM_ACTIVE_DELAY_REG(base), (uint32_t)(value)))
18302 /*@}*/
18303 
18304 /*
18305  * Constants & macros for individual RSIM_ACTIVE_DELAY bitfields
18306  */
18307 
18308 /*!
18309  * @name Register RSIM_ACTIVE_DELAY, field BLE_ACTIVE_FINE_DELAY[5:0] (RW)
18310  *
18311  * The SoC Flash is presented with a BLE Active early warning signal to allow
18312  * the Flash to complete any program or erase activities prior to a Radio
18313  * communication event. This warning signal is delayed from the BLE Active signal provided
18314  * by the BLE link layer. The amount of the delay from the BLE link layer is
18315  * calculated as follows: BLE Active link layer delay - ( BLE Active Flash Fine
18316  * Delay x 32 kHz clock period x 4 ) - ( BLE Active Flash Coarse Delay x 32 kHz clock
18317  * period x 64 )
18318  */
18319 /*@{*/
18320 /*! @brief Read current value of the RSIM_ACTIVE_DELAY_BLE_ACTIVE_FINE_DELAY field. */
18321 #define RSIM_RD_ACTIVE_DELAY_BLE_ACTIVE_FINE_DELAY(base) ((RSIM_ACTIVE_DELAY_REG(base) & RSIM_ACTIVE_DELAY_BLE_ACTIVE_FINE_DELAY_MASK) >> RSIM_ACTIVE_DELAY_BLE_ACTIVE_FINE_DELAY_SHIFT)
18322 #define RSIM_BRD_ACTIVE_DELAY_BLE_ACTIVE_FINE_DELAY(base) (BME_UBFX32(&RSIM_ACTIVE_DELAY_REG(base), RSIM_ACTIVE_DELAY_BLE_ACTIVE_FINE_DELAY_SHIFT, RSIM_ACTIVE_DELAY_BLE_ACTIVE_FINE_DELAY_WIDTH))
18323 
18324 /*! @brief Set the BLE_ACTIVE_FINE_DELAY field to a new value. */
18325 #define RSIM_WR_ACTIVE_DELAY_BLE_ACTIVE_FINE_DELAY(base, value) (RSIM_RMW_ACTIVE_DELAY(base, RSIM_ACTIVE_DELAY_BLE_ACTIVE_FINE_DELAY_MASK, RSIM_ACTIVE_DELAY_BLE_ACTIVE_FINE_DELAY(value)))
18326 #define RSIM_BWR_ACTIVE_DELAY_BLE_ACTIVE_FINE_DELAY(base, value) (BME_BFI32(&RSIM_ACTIVE_DELAY_REG(base), ((uint32_t)(value) << RSIM_ACTIVE_DELAY_BLE_ACTIVE_FINE_DELAY_SHIFT), RSIM_ACTIVE_DELAY_BLE_ACTIVE_FINE_DELAY_SHIFT, RSIM_ACTIVE_DELAY_BLE_ACTIVE_FINE_DELAY_WIDTH))
18327 /*@}*/
18328 
18329 /*!
18330  * @name Register RSIM_ACTIVE_DELAY, field BLE_ACTIVE_COARSE_DELAY[19:16] (RW)
18331  *
18332  * The SoC Flash is presented with a BLE Active early warning signal to allow
18333  * the Flash to complete any program or erase activities prior to a Radio
18334  * communication event. This warning signal is delayed from the BLE Active signal provided
18335  * by the BLE link layer. The timing of the Flash delay is calculated as
18336  * follows: BLE Active link layer delay - ( BLE Active Flash Fine Delay x 32 kHz clock
18337  * period x 4 ) - ( BLE Active Flash Coarse Delay x 32 kHz clock period x 64 )
18338  */
18339 /*@{*/
18340 /*! @brief Read current value of the RSIM_ACTIVE_DELAY_BLE_ACTIVE_COARSE_DELAY field. */
18341 #define RSIM_RD_ACTIVE_DELAY_BLE_ACTIVE_COARSE_DELAY(base) ((RSIM_ACTIVE_DELAY_REG(base) & RSIM_ACTIVE_DELAY_BLE_ACTIVE_COARSE_DELAY_MASK) >> RSIM_ACTIVE_DELAY_BLE_ACTIVE_COARSE_DELAY_SHIFT)
18342 #define RSIM_BRD_ACTIVE_DELAY_BLE_ACTIVE_COARSE_DELAY(base) (BME_UBFX32(&RSIM_ACTIVE_DELAY_REG(base), RSIM_ACTIVE_DELAY_BLE_ACTIVE_COARSE_DELAY_SHIFT, RSIM_ACTIVE_DELAY_BLE_ACTIVE_COARSE_DELAY_WIDTH))
18343 
18344 /*! @brief Set the BLE_ACTIVE_COARSE_DELAY field to a new value. */
18345 #define RSIM_WR_ACTIVE_DELAY_BLE_ACTIVE_COARSE_DELAY(base, value) (RSIM_RMW_ACTIVE_DELAY(base, RSIM_ACTIVE_DELAY_BLE_ACTIVE_COARSE_DELAY_MASK, RSIM_ACTIVE_DELAY_BLE_ACTIVE_COARSE_DELAY(value)))
18346 #define RSIM_BWR_ACTIVE_DELAY_BLE_ACTIVE_COARSE_DELAY(base, value) (BME_BFI32(&RSIM_ACTIVE_DELAY_REG(base), ((uint32_t)(value) << RSIM_ACTIVE_DELAY_BLE_ACTIVE_COARSE_DELAY_SHIFT), RSIM_ACTIVE_DELAY_BLE_ACTIVE_COARSE_DELAY_SHIFT, RSIM_ACTIVE_DELAY_BLE_ACTIVE_COARSE_DELAY_WIDTH))
18347 /*@}*/
18348 
18349 /*******************************************************************************
18350  * RSIM_MAC_MSB - RSIM MAC MSB
18351  ******************************************************************************/
18352 
18353 /*!
18354  * @brief RSIM_MAC_MSB - RSIM MAC MSB (RO)
18355  *
18356  * Reset value: 0x00000000U
18357  *
18358  * The RSIM MAC Address registers provide a unique ID that is stored in the
18359  * Flash during factory test
18360  */
18361 /*!
18362  * @name Constants and macros for entire RSIM_MAC_MSB register
18363  */
18364 /*@{*/
18365 #define RSIM_RD_MAC_MSB(base)    (RSIM_MAC_MSB_REG(base))
18366 /*@}*/
18367 
18368 /*
18369  * Constants & macros for individual RSIM_MAC_MSB bitfields
18370  */
18371 
18372 /*!
18373  * @name Register RSIM_MAC_MSB, field MAC_ADDR_MSB[7:0] (RO)
18374  *
18375  * The RSIM MAC Address is loaded from the Flash IFR during the SoC Power on
18376  * Reset sequence. The MAC Address is a unique ID that is stored in the Flash during
18377  * factory test.
18378  */
18379 /*@{*/
18380 /*! @brief Read current value of the RSIM_MAC_MSB_MAC_ADDR_MSB field. */
18381 #define RSIM_RD_MAC_MSB_MAC_ADDR_MSB(base) ((RSIM_MAC_MSB_REG(base) & RSIM_MAC_MSB_MAC_ADDR_MSB_MASK) >> RSIM_MAC_MSB_MAC_ADDR_MSB_SHIFT)
18382 #define RSIM_BRD_MAC_MSB_MAC_ADDR_MSB(base) (BME_UBFX32(&RSIM_MAC_MSB_REG(base), RSIM_MAC_MSB_MAC_ADDR_MSB_SHIFT, RSIM_MAC_MSB_MAC_ADDR_MSB_WIDTH))
18383 /*@}*/
18384 
18385 /*******************************************************************************
18386  * RSIM_MAC_LSB - RSIM MAC LSB
18387  ******************************************************************************/
18388 
18389 /*!
18390  * @brief RSIM_MAC_LSB - RSIM MAC LSB (RO)
18391  *
18392  * Reset value: 0x00000000U
18393  *
18394  * The RSIM MAC Address registers provide a unique ID that is stored in the
18395  * Flash during factory test
18396  */
18397 /*!
18398  * @name Constants and macros for entire RSIM_MAC_LSB register
18399  */
18400 /*@{*/
18401 #define RSIM_RD_MAC_LSB(base)    (RSIM_MAC_LSB_REG(base))
18402 /*@}*/
18403 
18404 /*******************************************************************************
18405  * RSIM_ANA_TEST - RSIM Analog Test
18406  ******************************************************************************/
18407 
18408 /*!
18409  * @brief RSIM_ANA_TEST - RSIM Analog Test (RW)
18410  *
18411  * Reset value: 0x01000000U
18412  *
18413  * The RSIM Analog Test register provides controls for validation and factory
18414  * test of the RF Analog Circuits.
18415  */
18416 /*!
18417  * @name Constants and macros for entire RSIM_ANA_TEST register
18418  */
18419 /*@{*/
18420 #define RSIM_RD_ANA_TEST(base)   (RSIM_ANA_TEST_REG(base))
18421 #define RSIM_WR_ANA_TEST(base, value) (RSIM_ANA_TEST_REG(base) = (value))
18422 #define RSIM_RMW_ANA_TEST(base, mask, value) (RSIM_WR_ANA_TEST(base, (RSIM_RD_ANA_TEST(base) & ~(mask)) | (value)))
18423 #define RSIM_SET_ANA_TEST(base, value) (BME_OR32(&RSIM_ANA_TEST_REG(base), (uint32_t)(value)))
18424 #define RSIM_CLR_ANA_TEST(base, value) (BME_AND32(&RSIM_ANA_TEST_REG(base), (uint32_t)(~(value))))
18425 #define RSIM_TOG_ANA_TEST(base, value) (BME_XOR32(&RSIM_ANA_TEST_REG(base), (uint32_t)(value)))
18426 /*@}*/
18427 
18428 /*
18429  * Constants & macros for individual RSIM_ANA_TEST bitfields
18430  */
18431 
18432 /*!
18433  * @name Register RSIM_ANA_TEST, field ATST_GATE_EN[4:0] (RW)
18434  *
18435  * The RSIM Analog Transmission Gate Enables open up the transmissions gates in
18436  * the pads to allow testing of the Radio analog signals. Each bit opens up one
18437  * Analog Transmission gate in the padring.
18438  */
18439 /*@{*/
18440 /*! @brief Read current value of the RSIM_ANA_TEST_ATST_GATE_EN field. */
18441 #define RSIM_RD_ANA_TEST_ATST_GATE_EN(base) ((RSIM_ANA_TEST_REG(base) & RSIM_ANA_TEST_ATST_GATE_EN_MASK) >> RSIM_ANA_TEST_ATST_GATE_EN_SHIFT)
18442 #define RSIM_BRD_ANA_TEST_ATST_GATE_EN(base) (BME_UBFX32(&RSIM_ANA_TEST_REG(base), RSIM_ANA_TEST_ATST_GATE_EN_SHIFT, RSIM_ANA_TEST_ATST_GATE_EN_WIDTH))
18443 
18444 /*! @brief Set the ATST_GATE_EN field to a new value. */
18445 #define RSIM_WR_ANA_TEST_ATST_GATE_EN(base, value) (RSIM_RMW_ANA_TEST(base, RSIM_ANA_TEST_ATST_GATE_EN_MASK, RSIM_ANA_TEST_ATST_GATE_EN(value)))
18446 #define RSIM_BWR_ANA_TEST_ATST_GATE_EN(base, value) (BME_BFI32(&RSIM_ANA_TEST_REG(base), ((uint32_t)(value) << RSIM_ANA_TEST_ATST_GATE_EN_SHIFT), RSIM_ANA_TEST_ATST_GATE_EN_SHIFT, RSIM_ANA_TEST_ATST_GATE_EN_WIDTH))
18447 /*@}*/
18448 
18449 /*!
18450  * @name Register RSIM_ANA_TEST, field RADIO_ID[27:24] (RO)
18451  *
18452  * This register value can be read to identify the Version of the Radio.
18453  *
18454  * Values:
18455  * - 0b0001 - Apache 1.0
18456  * - 0b0010 - Apache 2.0
18457  * - 0b0011 - 2.4 GHz Radio 2.0, Used by various SoC implementations
18458  */
18459 /*@{*/
18460 /*! @brief Read current value of the RSIM_ANA_TEST_RADIO_ID field. */
18461 #define RSIM_RD_ANA_TEST_RADIO_ID(base) ((RSIM_ANA_TEST_REG(base) & RSIM_ANA_TEST_RADIO_ID_MASK) >> RSIM_ANA_TEST_RADIO_ID_SHIFT)
18462 #define RSIM_BRD_ANA_TEST_RADIO_ID(base) (BME_UBFX32(&RSIM_ANA_TEST_REG(base), RSIM_ANA_TEST_RADIO_ID_SHIFT, RSIM_ANA_TEST_RADIO_ID_WIDTH))
18463 /*@}*/
18464 
18465 /*
18466  * MKW40Z4 RTC
18467  *
18468  * Secure Real Time Clock
18469  *
18470  * Registers defined in this header file:
18471  * - RTC_TSR - RTC Time Seconds Register
18472  * - RTC_TPR - RTC Time Prescaler Register
18473  * - RTC_TAR - RTC Time Alarm Register
18474  * - RTC_TCR - RTC Time Compensation Register
18475  * - RTC_CR - RTC Control Register
18476  * - RTC_SR - RTC Status Register
18477  * - RTC_LR - RTC Lock Register
18478  * - RTC_IER - RTC Interrupt Enable Register
18479  */
18480 
18481 #define RTC_INSTANCE_COUNT (1U) /*!< Number of instances of the RTC module. */
18482 #define RTC_IDX (0U) /*!< Instance number for RTC. */
18483 
18484 /*******************************************************************************
18485  * RTC_TSR - RTC Time Seconds Register
18486  ******************************************************************************/
18487 
18488 /*!
18489  * @brief RTC_TSR - RTC Time Seconds Register (RW)
18490  *
18491  * Reset value: 0x00000000U
18492  */
18493 /*!
18494  * @name Constants and macros for entire RTC_TSR register
18495  */
18496 /*@{*/
18497 #define RTC_RD_TSR(base)         (RTC_TSR_REG(base))
18498 #define RTC_WR_TSR(base, value)  (RTC_TSR_REG(base) = (value))
18499 #define RTC_RMW_TSR(base, mask, value) (RTC_WR_TSR(base, (RTC_RD_TSR(base) & ~(mask)) | (value)))
18500 #define RTC_SET_TSR(base, value) (BME_OR32(&RTC_TSR_REG(base), (uint32_t)(value)))
18501 #define RTC_CLR_TSR(base, value) (BME_AND32(&RTC_TSR_REG(base), (uint32_t)(~(value))))
18502 #define RTC_TOG_TSR(base, value) (BME_XOR32(&RTC_TSR_REG(base), (uint32_t)(value)))
18503 /*@}*/
18504 
18505 /*******************************************************************************
18506  * RTC_TPR - RTC Time Prescaler Register
18507  ******************************************************************************/
18508 
18509 /*!
18510  * @brief RTC_TPR - RTC Time Prescaler Register (RW)
18511  *
18512  * Reset value: 0x00000000U
18513  */
18514 /*!
18515  * @name Constants and macros for entire RTC_TPR register
18516  */
18517 /*@{*/
18518 #define RTC_RD_TPR(base)         (RTC_TPR_REG(base))
18519 #define RTC_WR_TPR(base, value)  (RTC_TPR_REG(base) = (value))
18520 #define RTC_RMW_TPR(base, mask, value) (RTC_WR_TPR(base, (RTC_RD_TPR(base) & ~(mask)) | (value)))
18521 #define RTC_SET_TPR(base, value) (BME_OR32(&RTC_TPR_REG(base), (uint32_t)(value)))
18522 #define RTC_CLR_TPR(base, value) (BME_AND32(&RTC_TPR_REG(base), (uint32_t)(~(value))))
18523 #define RTC_TOG_TPR(base, value) (BME_XOR32(&RTC_TPR_REG(base), (uint32_t)(value)))
18524 /*@}*/
18525 
18526 /*
18527  * Constants & macros for individual RTC_TPR bitfields
18528  */
18529 
18530 /*!
18531  * @name Register RTC_TPR, field TPR[15:0] (RW)
18532  *
18533  * When the time counter is enabled, the TPR is read only and increments every
18534  * 32.768 kHz clock cycle. The time counter will read as zero when SR[TOF] or
18535  * SR[TIF] are set. When the time counter is disabled, the TPR can be read or
18536  * written. The TSR[TSR] increments when bit 14 of the TPR transitions from a logic one
18537  * to a logic zero.
18538  */
18539 /*@{*/
18540 /*! @brief Read current value of the RTC_TPR_TPR field. */
18541 #define RTC_RD_TPR_TPR(base) ((RTC_TPR_REG(base) & RTC_TPR_TPR_MASK) >> RTC_TPR_TPR_SHIFT)
18542 #define RTC_BRD_TPR_TPR(base) (BME_UBFX32(&RTC_TPR_REG(base), RTC_TPR_TPR_SHIFT, RTC_TPR_TPR_WIDTH))
18543 
18544 /*! @brief Set the TPR field to a new value. */
18545 #define RTC_WR_TPR_TPR(base, value) (RTC_RMW_TPR(base, RTC_TPR_TPR_MASK, RTC_TPR_TPR(value)))
18546 #define RTC_BWR_TPR_TPR(base, value) (BME_BFI32(&RTC_TPR_REG(base), ((uint32_t)(value) << RTC_TPR_TPR_SHIFT), RTC_TPR_TPR_SHIFT, RTC_TPR_TPR_WIDTH))
18547 /*@}*/
18548 
18549 /*******************************************************************************
18550  * RTC_TAR - RTC Time Alarm Register
18551  ******************************************************************************/
18552 
18553 /*!
18554  * @brief RTC_TAR - RTC Time Alarm Register (RW)
18555  *
18556  * Reset value: 0x00000000U
18557  */
18558 /*!
18559  * @name Constants and macros for entire RTC_TAR register
18560  */
18561 /*@{*/
18562 #define RTC_RD_TAR(base)         (RTC_TAR_REG(base))
18563 #define RTC_WR_TAR(base, value)  (RTC_TAR_REG(base) = (value))
18564 #define RTC_RMW_TAR(base, mask, value) (RTC_WR_TAR(base, (RTC_RD_TAR(base) & ~(mask)) | (value)))
18565 #define RTC_SET_TAR(base, value) (BME_OR32(&RTC_TAR_REG(base), (uint32_t)(value)))
18566 #define RTC_CLR_TAR(base, value) (BME_AND32(&RTC_TAR_REG(base), (uint32_t)(~(value))))
18567 #define RTC_TOG_TAR(base, value) (BME_XOR32(&RTC_TAR_REG(base), (uint32_t)(value)))
18568 /*@}*/
18569 
18570 /*******************************************************************************
18571  * RTC_TCR - RTC Time Compensation Register
18572  ******************************************************************************/
18573 
18574 /*!
18575  * @brief RTC_TCR - RTC Time Compensation Register (RW)
18576  *
18577  * Reset value: 0x00000000U
18578  */
18579 /*!
18580  * @name Constants and macros for entire RTC_TCR register
18581  */
18582 /*@{*/
18583 #define RTC_RD_TCR(base)         (RTC_TCR_REG(base))
18584 #define RTC_WR_TCR(base, value)  (RTC_TCR_REG(base) = (value))
18585 #define RTC_RMW_TCR(base, mask, value) (RTC_WR_TCR(base, (RTC_RD_TCR(base) & ~(mask)) | (value)))
18586 #define RTC_SET_TCR(base, value) (BME_OR32(&RTC_TCR_REG(base), (uint32_t)(value)))
18587 #define RTC_CLR_TCR(base, value) (BME_AND32(&RTC_TCR_REG(base), (uint32_t)(~(value))))
18588 #define RTC_TOG_TCR(base, value) (BME_XOR32(&RTC_TCR_REG(base), (uint32_t)(value)))
18589 /*@}*/
18590 
18591 /*
18592  * Constants & macros for individual RTC_TCR bitfields
18593  */
18594 
18595 /*!
18596  * @name Register RTC_TCR, field TCR[7:0] (RW)
18597  *
18598  * Configures the number of 32.768 kHz clock cycles in each second. This
18599  * register is double buffered and writes do not take affect until the end of the
18600  * current compensation interval.
18601  *
18602  * Values:
18603  * - 0b10000000 - Time Prescaler Register overflows every 32896 clock cycles.
18604  * - 0b11111111 - Time Prescaler Register overflows every 32769 clock cycles.
18605  * - 0b00000000 - Time Prescaler Register overflows every 32768 clock cycles.
18606  * - 0b00000001 - Time Prescaler Register overflows every 32767 clock cycles.
18607  * - 0b01111111 - Time Prescaler Register overflows every 32641 clock cycles.
18608  */
18609 /*@{*/
18610 /*! @brief Read current value of the RTC_TCR_TCR field. */
18611 #define RTC_RD_TCR_TCR(base) ((RTC_TCR_REG(base) & RTC_TCR_TCR_MASK) >> RTC_TCR_TCR_SHIFT)
18612 #define RTC_BRD_TCR_TCR(base) (BME_UBFX32(&RTC_TCR_REG(base), RTC_TCR_TCR_SHIFT, RTC_TCR_TCR_WIDTH))
18613 
18614 /*! @brief Set the TCR field to a new value. */
18615 #define RTC_WR_TCR_TCR(base, value) (RTC_RMW_TCR(base, RTC_TCR_TCR_MASK, RTC_TCR_TCR(value)))
18616 #define RTC_BWR_TCR_TCR(base, value) (BME_BFI32(&RTC_TCR_REG(base), ((uint32_t)(value) << RTC_TCR_TCR_SHIFT), RTC_TCR_TCR_SHIFT, RTC_TCR_TCR_WIDTH))
18617 /*@}*/
18618 
18619 /*!
18620  * @name Register RTC_TCR, field CIR[15:8] (RW)
18621  *
18622  * Configures the compensation interval in seconds from 1 to 256 to control how
18623  * frequently the TCR should adjust the number of 32.768 kHz cycles in each
18624  * second. The value written should be one less than the number of seconds. For
18625  * example, write zero to configure for a compensation interval of one second. This
18626  * register is double buffered and writes do not take affect until the end of the
18627  * current compensation interval.
18628  */
18629 /*@{*/
18630 /*! @brief Read current value of the RTC_TCR_CIR field. */
18631 #define RTC_RD_TCR_CIR(base) ((RTC_TCR_REG(base) & RTC_TCR_CIR_MASK) >> RTC_TCR_CIR_SHIFT)
18632 #define RTC_BRD_TCR_CIR(base) (BME_UBFX32(&RTC_TCR_REG(base), RTC_TCR_CIR_SHIFT, RTC_TCR_CIR_WIDTH))
18633 
18634 /*! @brief Set the CIR field to a new value. */
18635 #define RTC_WR_TCR_CIR(base, value) (RTC_RMW_TCR(base, RTC_TCR_CIR_MASK, RTC_TCR_CIR(value)))
18636 #define RTC_BWR_TCR_CIR(base, value) (BME_BFI32(&RTC_TCR_REG(base), ((uint32_t)(value) << RTC_TCR_CIR_SHIFT), RTC_TCR_CIR_SHIFT, RTC_TCR_CIR_WIDTH))
18637 /*@}*/
18638 
18639 /*!
18640  * @name Register RTC_TCR, field TCV[23:16] (RO)
18641  *
18642  * Current value used by the compensation logic for the present second interval.
18643  * Updated once a second if the CIC equals 0 with the contents of the TCR field.
18644  * If the CIC does not equal zero then it is loaded with zero (compensation is
18645  * not enabled for that second increment).
18646  */
18647 /*@{*/
18648 /*! @brief Read current value of the RTC_TCR_TCV field. */
18649 #define RTC_RD_TCR_TCV(base) ((RTC_TCR_REG(base) & RTC_TCR_TCV_MASK) >> RTC_TCR_TCV_SHIFT)
18650 #define RTC_BRD_TCR_TCV(base) (BME_UBFX32(&RTC_TCR_REG(base), RTC_TCR_TCV_SHIFT, RTC_TCR_TCV_WIDTH))
18651 /*@}*/
18652 
18653 /*!
18654  * @name Register RTC_TCR, field CIC[31:24] (RO)
18655  *
18656  * Current value of the compensation interval counter. If the compensation
18657  * interval counter equals zero then it is loaded with the contents of the CIR. If the
18658  * CIC does not equal zero then it is decremented once a second.
18659  */
18660 /*@{*/
18661 /*! @brief Read current value of the RTC_TCR_CIC field. */
18662 #define RTC_RD_TCR_CIC(base) ((RTC_TCR_REG(base) & RTC_TCR_CIC_MASK) >> RTC_TCR_CIC_SHIFT)
18663 #define RTC_BRD_TCR_CIC(base) (BME_UBFX32(&RTC_TCR_REG(base), RTC_TCR_CIC_SHIFT, RTC_TCR_CIC_WIDTH))
18664 /*@}*/
18665 
18666 /*******************************************************************************
18667  * RTC_CR - RTC Control Register
18668  ******************************************************************************/
18669 
18670 /*!
18671  * @brief RTC_CR - RTC Control Register (RW)
18672  *
18673  * Reset value: 0x00000000U
18674  */
18675 /*!
18676  * @name Constants and macros for entire RTC_CR register
18677  */
18678 /*@{*/
18679 #define RTC_RD_CR(base)          (RTC_CR_REG(base))
18680 #define RTC_WR_CR(base, value)   (RTC_CR_REG(base) = (value))
18681 #define RTC_RMW_CR(base, mask, value) (RTC_WR_CR(base, (RTC_RD_CR(base) & ~(mask)) | (value)))
18682 #define RTC_SET_CR(base, value)  (BME_OR32(&RTC_CR_REG(base), (uint32_t)(value)))
18683 #define RTC_CLR_CR(base, value)  (BME_AND32(&RTC_CR_REG(base), (uint32_t)(~(value))))
18684 #define RTC_TOG_CR(base, value)  (BME_XOR32(&RTC_CR_REG(base), (uint32_t)(value)))
18685 /*@}*/
18686 
18687 /*
18688  * Constants & macros for individual RTC_CR bitfields
18689  */
18690 
18691 /*!
18692  * @name Register RTC_CR, field SWR[0] (RW)
18693  *
18694  * Values:
18695  * - 0b0 - No effect.
18696  * - 0b1 - Resets all RTC registers except for the SWR bit . The SWR bit is
18697  *     cleared by POR and by software explicitly clearing it.
18698  */
18699 /*@{*/
18700 /*! @brief Read current value of the RTC_CR_SWR field. */
18701 #define RTC_RD_CR_SWR(base)  ((RTC_CR_REG(base) & RTC_CR_SWR_MASK) >> RTC_CR_SWR_SHIFT)
18702 #define RTC_BRD_CR_SWR(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SWR_SHIFT, RTC_CR_SWR_WIDTH))
18703 
18704 /*! @brief Set the SWR field to a new value. */
18705 #define RTC_WR_CR_SWR(base, value) (RTC_RMW_CR(base, RTC_CR_SWR_MASK, RTC_CR_SWR(value)))
18706 #define RTC_BWR_CR_SWR(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SWR_SHIFT), RTC_CR_SWR_SHIFT, RTC_CR_SWR_WIDTH))
18707 /*@}*/
18708 
18709 /*!
18710  * @name Register RTC_CR, field WPE[1] (RW)
18711  *
18712  * The wakeup pin is optional and not available on all devices.
18713  *
18714  * Values:
18715  * - 0b0 - Wakeup pin is disabled.
18716  * - 0b1 - Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt
18717  *     asserts or the wakeup pin is turned on.
18718  */
18719 /*@{*/
18720 /*! @brief Read current value of the RTC_CR_WPE field. */
18721 #define RTC_RD_CR_WPE(base)  ((RTC_CR_REG(base) & RTC_CR_WPE_MASK) >> RTC_CR_WPE_SHIFT)
18722 #define RTC_BRD_CR_WPE(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_WPE_SHIFT, RTC_CR_WPE_WIDTH))
18723 
18724 /*! @brief Set the WPE field to a new value. */
18725 #define RTC_WR_CR_WPE(base, value) (RTC_RMW_CR(base, RTC_CR_WPE_MASK, RTC_CR_WPE(value)))
18726 #define RTC_BWR_CR_WPE(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_WPE_SHIFT), RTC_CR_WPE_SHIFT, RTC_CR_WPE_WIDTH))
18727 /*@}*/
18728 
18729 /*!
18730  * @name Register RTC_CR, field SUP[2] (RW)
18731  *
18732  * Values:
18733  * - 0b0 - Non-supervisor mode write accesses are not supported and generate a
18734  *     bus error.
18735  * - 0b1 - Non-supervisor mode write accesses are supported.
18736  */
18737 /*@{*/
18738 /*! @brief Read current value of the RTC_CR_SUP field. */
18739 #define RTC_RD_CR_SUP(base)  ((RTC_CR_REG(base) & RTC_CR_SUP_MASK) >> RTC_CR_SUP_SHIFT)
18740 #define RTC_BRD_CR_SUP(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SUP_SHIFT, RTC_CR_SUP_WIDTH))
18741 
18742 /*! @brief Set the SUP field to a new value. */
18743 #define RTC_WR_CR_SUP(base, value) (RTC_RMW_CR(base, RTC_CR_SUP_MASK, RTC_CR_SUP(value)))
18744 #define RTC_BWR_CR_SUP(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SUP_SHIFT), RTC_CR_SUP_SHIFT, RTC_CR_SUP_WIDTH))
18745 /*@}*/
18746 
18747 /*!
18748  * @name Register RTC_CR, field UM[3] (RW)
18749  *
18750  * Allows SR[TCE] to be written even when the Status Register is locked. When
18751  * set, the SR[TCE] can always be written if the SR[TIF] or SR[TOF] are set or if
18752  * the SR[TCE] is clear.
18753  *
18754  * Values:
18755  * - 0b0 - Registers cannot be written when locked.
18756  * - 0b1 - Registers can be written when locked under limited conditions.
18757  */
18758 /*@{*/
18759 /*! @brief Read current value of the RTC_CR_UM field. */
18760 #define RTC_RD_CR_UM(base)   ((RTC_CR_REG(base) & RTC_CR_UM_MASK) >> RTC_CR_UM_SHIFT)
18761 #define RTC_BRD_CR_UM(base)  (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_UM_SHIFT, RTC_CR_UM_WIDTH))
18762 
18763 /*! @brief Set the UM field to a new value. */
18764 #define RTC_WR_CR_UM(base, value) (RTC_RMW_CR(base, RTC_CR_UM_MASK, RTC_CR_UM(value)))
18765 #define RTC_BWR_CR_UM(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_UM_SHIFT), RTC_CR_UM_SHIFT, RTC_CR_UM_WIDTH))
18766 /*@}*/
18767 
18768 /*!
18769  * @name Register RTC_CR, field WPS[4] (RW)
18770  *
18771  * The wakeup pin is optional and not available on all devices.
18772  *
18773  * Values:
18774  * - 0b0 - Wakeup pin asserts (active low, open drain) if the RTC interrupt
18775  *     asserts or the wakeup pin is turned on.
18776  * - 0b1 - Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup
18777  *     pin is turned on and the 32kHz clock is output to other peripherals.
18778  */
18779 /*@{*/
18780 /*! @brief Read current value of the RTC_CR_WPS field. */
18781 #define RTC_RD_CR_WPS(base)  ((RTC_CR_REG(base) & RTC_CR_WPS_MASK) >> RTC_CR_WPS_SHIFT)
18782 #define RTC_BRD_CR_WPS(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_WPS_SHIFT, RTC_CR_WPS_WIDTH))
18783 
18784 /*! @brief Set the WPS field to a new value. */
18785 #define RTC_WR_CR_WPS(base, value) (RTC_RMW_CR(base, RTC_CR_WPS_MASK, RTC_CR_WPS(value)))
18786 #define RTC_BWR_CR_WPS(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_WPS_SHIFT), RTC_CR_WPS_SHIFT, RTC_CR_WPS_WIDTH))
18787 /*@}*/
18788 
18789 /*!
18790  * @name Register RTC_CR, field OSCE[8] (RW)
18791  *
18792  * Values:
18793  * - 0b0 - 32.768 kHz oscillator is disabled.
18794  * - 0b1 - 32.768 kHz oscillator is enabled. After setting this bit, wait the
18795  *     oscillator startup time before enabling the time counter to allow the 32.768
18796  *     kHz clock time to stabilize.
18797  */
18798 /*@{*/
18799 /*! @brief Read current value of the RTC_CR_OSCE field. */
18800 #define RTC_RD_CR_OSCE(base) ((RTC_CR_REG(base) & RTC_CR_OSCE_MASK) >> RTC_CR_OSCE_SHIFT)
18801 #define RTC_BRD_CR_OSCE(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_OSCE_SHIFT, RTC_CR_OSCE_WIDTH))
18802 
18803 /*! @brief Set the OSCE field to a new value. */
18804 #define RTC_WR_CR_OSCE(base, value) (RTC_RMW_CR(base, RTC_CR_OSCE_MASK, RTC_CR_OSCE(value)))
18805 #define RTC_BWR_CR_OSCE(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_OSCE_SHIFT), RTC_CR_OSCE_SHIFT, RTC_CR_OSCE_WIDTH))
18806 /*@}*/
18807 
18808 /*!
18809  * @name Register RTC_CR, field CLKO[9] (RW)
18810  *
18811  * Values:
18812  * - 0b0 - The 32 kHz clock is output to other peripherals.
18813  * - 0b1 - The 32 kHz clock is not output to other peripherals.
18814  */
18815 /*@{*/
18816 /*! @brief Read current value of the RTC_CR_CLKO field. */
18817 #define RTC_RD_CR_CLKO(base) ((RTC_CR_REG(base) & RTC_CR_CLKO_MASK) >> RTC_CR_CLKO_SHIFT)
18818 #define RTC_BRD_CR_CLKO(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_CLKO_SHIFT, RTC_CR_CLKO_WIDTH))
18819 
18820 /*! @brief Set the CLKO field to a new value. */
18821 #define RTC_WR_CR_CLKO(base, value) (RTC_RMW_CR(base, RTC_CR_CLKO_MASK, RTC_CR_CLKO(value)))
18822 #define RTC_BWR_CR_CLKO(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_CLKO_SHIFT), RTC_CR_CLKO_SHIFT, RTC_CR_CLKO_WIDTH))
18823 /*@}*/
18824 
18825 /*!
18826  * @name Register RTC_CR, field SC16P[10] (RW)
18827  *
18828  * Values:
18829  * - 0b0 - Disable the load.
18830  * - 0b1 - Enable the additional load.
18831  */
18832 /*@{*/
18833 /*! @brief Read current value of the RTC_CR_SC16P field. */
18834 #define RTC_RD_CR_SC16P(base) ((RTC_CR_REG(base) & RTC_CR_SC16P_MASK) >> RTC_CR_SC16P_SHIFT)
18835 #define RTC_BRD_CR_SC16P(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SC16P_SHIFT, RTC_CR_SC16P_WIDTH))
18836 
18837 /*! @brief Set the SC16P field to a new value. */
18838 #define RTC_WR_CR_SC16P(base, value) (RTC_RMW_CR(base, RTC_CR_SC16P_MASK, RTC_CR_SC16P(value)))
18839 #define RTC_BWR_CR_SC16P(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SC16P_SHIFT), RTC_CR_SC16P_SHIFT, RTC_CR_SC16P_WIDTH))
18840 /*@}*/
18841 
18842 /*!
18843  * @name Register RTC_CR, field SC8P[11] (RW)
18844  *
18845  * Values:
18846  * - 0b0 - Disable the load.
18847  * - 0b1 - Enable the additional load.
18848  */
18849 /*@{*/
18850 /*! @brief Read current value of the RTC_CR_SC8P field. */
18851 #define RTC_RD_CR_SC8P(base) ((RTC_CR_REG(base) & RTC_CR_SC8P_MASK) >> RTC_CR_SC8P_SHIFT)
18852 #define RTC_BRD_CR_SC8P(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SC8P_SHIFT, RTC_CR_SC8P_WIDTH))
18853 
18854 /*! @brief Set the SC8P field to a new value. */
18855 #define RTC_WR_CR_SC8P(base, value) (RTC_RMW_CR(base, RTC_CR_SC8P_MASK, RTC_CR_SC8P(value)))
18856 #define RTC_BWR_CR_SC8P(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SC8P_SHIFT), RTC_CR_SC8P_SHIFT, RTC_CR_SC8P_WIDTH))
18857 /*@}*/
18858 
18859 /*!
18860  * @name Register RTC_CR, field SC4P[12] (RW)
18861  *
18862  * Values:
18863  * - 0b0 - Disable the load.
18864  * - 0b1 - Enable the additional load.
18865  */
18866 /*@{*/
18867 /*! @brief Read current value of the RTC_CR_SC4P field. */
18868 #define RTC_RD_CR_SC4P(base) ((RTC_CR_REG(base) & RTC_CR_SC4P_MASK) >> RTC_CR_SC4P_SHIFT)
18869 #define RTC_BRD_CR_SC4P(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SC4P_SHIFT, RTC_CR_SC4P_WIDTH))
18870 
18871 /*! @brief Set the SC4P field to a new value. */
18872 #define RTC_WR_CR_SC4P(base, value) (RTC_RMW_CR(base, RTC_CR_SC4P_MASK, RTC_CR_SC4P(value)))
18873 #define RTC_BWR_CR_SC4P(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SC4P_SHIFT), RTC_CR_SC4P_SHIFT, RTC_CR_SC4P_WIDTH))
18874 /*@}*/
18875 
18876 /*!
18877  * @name Register RTC_CR, field SC2P[13] (RW)
18878  *
18879  * Values:
18880  * - 0b0 - Disable the load.
18881  * - 0b1 - Enable the additional load.
18882  */
18883 /*@{*/
18884 /*! @brief Read current value of the RTC_CR_SC2P field. */
18885 #define RTC_RD_CR_SC2P(base) ((RTC_CR_REG(base) & RTC_CR_SC2P_MASK) >> RTC_CR_SC2P_SHIFT)
18886 #define RTC_BRD_CR_SC2P(base) (BME_UBFX32(&RTC_CR_REG(base), RTC_CR_SC2P_SHIFT, RTC_CR_SC2P_WIDTH))
18887 
18888 /*! @brief Set the SC2P field to a new value. */
18889 #define RTC_WR_CR_SC2P(base, value) (RTC_RMW_CR(base, RTC_CR_SC2P_MASK, RTC_CR_SC2P(value)))
18890 #define RTC_BWR_CR_SC2P(base, value) (BME_BFI32(&RTC_CR_REG(base), ((uint32_t)(value) << RTC_CR_SC2P_SHIFT), RTC_CR_SC2P_SHIFT, RTC_CR_SC2P_WIDTH))
18891 /*@}*/
18892 
18893 /*******************************************************************************
18894  * RTC_SR - RTC Status Register
18895  ******************************************************************************/
18896 
18897 /*!
18898  * @brief RTC_SR - RTC Status Register (RW)
18899  *
18900  * Reset value: 0x00000001U
18901  */
18902 /*!
18903  * @name Constants and macros for entire RTC_SR register
18904  */
18905 /*@{*/
18906 #define RTC_RD_SR(base)          (RTC_SR_REG(base))
18907 #define RTC_WR_SR(base, value)   (RTC_SR_REG(base) = (value))
18908 #define RTC_RMW_SR(base, mask, value) (RTC_WR_SR(base, (RTC_RD_SR(base) & ~(mask)) | (value)))
18909 #define RTC_SET_SR(base, value)  (BME_OR32(&RTC_SR_REG(base), (uint32_t)(value)))
18910 #define RTC_CLR_SR(base, value)  (BME_AND32(&RTC_SR_REG(base), (uint32_t)(~(value))))
18911 #define RTC_TOG_SR(base, value)  (BME_XOR32(&RTC_SR_REG(base), (uint32_t)(value)))
18912 /*@}*/
18913 
18914 /*
18915  * Constants & macros for individual RTC_SR bitfields
18916  */
18917 
18918 /*!
18919  * @name Register RTC_SR, field TIF[0] (RO)
18920  *
18921  * The time invalid flag is set on POR or software reset. The TSR and TPR do not
18922  * increment and read as zero when this bit is set. This bit is cleared by
18923  * writing the TSR register when the time counter is disabled.
18924  *
18925  * Values:
18926  * - 0b0 - Time is valid.
18927  * - 0b1 - Time is invalid and time counter is read as zero.
18928  */
18929 /*@{*/
18930 /*! @brief Read current value of the RTC_SR_TIF field. */
18931 #define RTC_RD_SR_TIF(base)  ((RTC_SR_REG(base) & RTC_SR_TIF_MASK) >> RTC_SR_TIF_SHIFT)
18932 #define RTC_BRD_SR_TIF(base) (BME_UBFX32(&RTC_SR_REG(base), RTC_SR_TIF_SHIFT, RTC_SR_TIF_WIDTH))
18933 /*@}*/
18934 
18935 /*!
18936  * @name Register RTC_SR, field TOF[1] (RO)
18937  *
18938  * Time overflow flag is set when the time counter is enabled and overflows. The
18939  * TSR and TPR do not increment and read as zero when this bit is set. This bit
18940  * is cleared by writing the TSR register when the time counter is disabled.
18941  *
18942  * Values:
18943  * - 0b0 - Time overflow has not occurred.
18944  * - 0b1 - Time overflow has occurred and time counter is read as zero.
18945  */
18946 /*@{*/
18947 /*! @brief Read current value of the RTC_SR_TOF field. */
18948 #define RTC_RD_SR_TOF(base)  ((RTC_SR_REG(base) & RTC_SR_TOF_MASK) >> RTC_SR_TOF_SHIFT)
18949 #define RTC_BRD_SR_TOF(base) (BME_UBFX32(&RTC_SR_REG(base), RTC_SR_TOF_SHIFT, RTC_SR_TOF_WIDTH))
18950 /*@}*/
18951 
18952 /*!
18953  * @name Register RTC_SR, field TAF[2] (RO)
18954  *
18955  * Time alarm flag is set when the TAR[TAR] equals the TSR[TSR] and the TSR[TSR]
18956  * increments. This bit is cleared by writing the TAR register.
18957  *
18958  * Values:
18959  * - 0b0 - Time alarm has not occurred.
18960  * - 0b1 - Time alarm has occurred.
18961  */
18962 /*@{*/
18963 /*! @brief Read current value of the RTC_SR_TAF field. */
18964 #define RTC_RD_SR_TAF(base)  ((RTC_SR_REG(base) & RTC_SR_TAF_MASK) >> RTC_SR_TAF_SHIFT)
18965 #define RTC_BRD_SR_TAF(base) (BME_UBFX32(&RTC_SR_REG(base), RTC_SR_TAF_SHIFT, RTC_SR_TAF_WIDTH))
18966 /*@}*/
18967 
18968 /*!
18969  * @name Register RTC_SR, field TCE[4] (RW)
18970  *
18971  * When time counter is disabled the TSR register and TPR register are
18972  * writeable, but do not increment. When time counter is enabled the TSR register and TPR
18973  * register are not writeable, but increment.
18974  *
18975  * Values:
18976  * - 0b0 - Time counter is disabled.
18977  * - 0b1 - Time counter is enabled.
18978  */
18979 /*@{*/
18980 /*! @brief Read current value of the RTC_SR_TCE field. */
18981 #define RTC_RD_SR_TCE(base)  ((RTC_SR_REG(base) & RTC_SR_TCE_MASK) >> RTC_SR_TCE_SHIFT)
18982 #define RTC_BRD_SR_TCE(base) (BME_UBFX32(&RTC_SR_REG(base), RTC_SR_TCE_SHIFT, RTC_SR_TCE_WIDTH))
18983 
18984 /*! @brief Set the TCE field to a new value. */
18985 #define RTC_WR_SR_TCE(base, value) (RTC_RMW_SR(base, RTC_SR_TCE_MASK, RTC_SR_TCE(value)))
18986 #define RTC_BWR_SR_TCE(base, value) (BME_BFI32(&RTC_SR_REG(base), ((uint32_t)(value) << RTC_SR_TCE_SHIFT), RTC_SR_TCE_SHIFT, RTC_SR_TCE_WIDTH))
18987 /*@}*/
18988 
18989 /*******************************************************************************
18990  * RTC_LR - RTC Lock Register
18991  ******************************************************************************/
18992 
18993 /*!
18994  * @brief RTC_LR - RTC Lock Register (RW)
18995  *
18996  * Reset value: 0x000000FFU
18997  */
18998 /*!
18999  * @name Constants and macros for entire RTC_LR register
19000  */
19001 /*@{*/
19002 #define RTC_RD_LR(base)          (RTC_LR_REG(base))
19003 #define RTC_WR_LR(base, value)   (RTC_LR_REG(base) = (value))
19004 #define RTC_RMW_LR(base, mask, value) (RTC_WR_LR(base, (RTC_RD_LR(base) & ~(mask)) | (value)))
19005 #define RTC_SET_LR(base, value)  (BME_OR32(&RTC_LR_REG(base), (uint32_t)(value)))
19006 #define RTC_CLR_LR(base, value)  (BME_AND32(&RTC_LR_REG(base), (uint32_t)(~(value))))
19007 #define RTC_TOG_LR(base, value)  (BME_XOR32(&RTC_LR_REG(base), (uint32_t)(value)))
19008 /*@}*/
19009 
19010 /*
19011  * Constants & macros for individual RTC_LR bitfields
19012  */
19013 
19014 /*!
19015  * @name Register RTC_LR, field TCL[3] (RW)
19016  *
19017  * After being cleared, this bit can be set only by POR or software reset.
19018  *
19019  * Values:
19020  * - 0b0 - Time Compensation Register is locked and writes are ignored.
19021  * - 0b1 - Time Compensation Register is not locked and writes complete as
19022  *     normal.
19023  */
19024 /*@{*/
19025 /*! @brief Read current value of the RTC_LR_TCL field. */
19026 #define RTC_RD_LR_TCL(base)  ((RTC_LR_REG(base) & RTC_LR_TCL_MASK) >> RTC_LR_TCL_SHIFT)
19027 #define RTC_BRD_LR_TCL(base) (BME_UBFX32(&RTC_LR_REG(base), RTC_LR_TCL_SHIFT, RTC_LR_TCL_WIDTH))
19028 
19029 /*! @brief Set the TCL field to a new value. */
19030 #define RTC_WR_LR_TCL(base, value) (RTC_RMW_LR(base, RTC_LR_TCL_MASK, RTC_LR_TCL(value)))
19031 #define RTC_BWR_LR_TCL(base, value) (BME_BFI32(&RTC_LR_REG(base), ((uint32_t)(value) << RTC_LR_TCL_SHIFT), RTC_LR_TCL_SHIFT, RTC_LR_TCL_WIDTH))
19032 /*@}*/
19033 
19034 /*!
19035  * @name Register RTC_LR, field CRL[4] (RW)
19036  *
19037  * After being cleared, this bit can only be set by POR.
19038  *
19039  * Values:
19040  * - 0b0 - Control Register is locked and writes are ignored.
19041  * - 0b1 - Control Register is not locked and writes complete as normal.
19042  */
19043 /*@{*/
19044 /*! @brief Read current value of the RTC_LR_CRL field. */
19045 #define RTC_RD_LR_CRL(base)  ((RTC_LR_REG(base) & RTC_LR_CRL_MASK) >> RTC_LR_CRL_SHIFT)
19046 #define RTC_BRD_LR_CRL(base) (BME_UBFX32(&RTC_LR_REG(base), RTC_LR_CRL_SHIFT, RTC_LR_CRL_WIDTH))
19047 
19048 /*! @brief Set the CRL field to a new value. */
19049 #define RTC_WR_LR_CRL(base, value) (RTC_RMW_LR(base, RTC_LR_CRL_MASK, RTC_LR_CRL(value)))
19050 #define RTC_BWR_LR_CRL(base, value) (BME_BFI32(&RTC_LR_REG(base), ((uint32_t)(value) << RTC_LR_CRL_SHIFT), RTC_LR_CRL_SHIFT, RTC_LR_CRL_WIDTH))
19051 /*@}*/
19052 
19053 /*!
19054  * @name Register RTC_LR, field SRL[5] (RW)
19055  *
19056  * After being cleared, this bit can be set only by POR or software reset.
19057  *
19058  * Values:
19059  * - 0b0 - Status Register is locked and writes are ignored.
19060  * - 0b1 - Status Register is not locked and writes complete as normal.
19061  */
19062 /*@{*/
19063 /*! @brief Read current value of the RTC_LR_SRL field. */
19064 #define RTC_RD_LR_SRL(base)  ((RTC_LR_REG(base) & RTC_LR_SRL_MASK) >> RTC_LR_SRL_SHIFT)
19065 #define RTC_BRD_LR_SRL(base) (BME_UBFX32(&RTC_LR_REG(base), RTC_LR_SRL_SHIFT, RTC_LR_SRL_WIDTH))
19066 
19067 /*! @brief Set the SRL field to a new value. */
19068 #define RTC_WR_LR_SRL(base, value) (RTC_RMW_LR(base, RTC_LR_SRL_MASK, RTC_LR_SRL(value)))
19069 #define RTC_BWR_LR_SRL(base, value) (BME_BFI32(&RTC_LR_REG(base), ((uint32_t)(value) << RTC_LR_SRL_SHIFT), RTC_LR_SRL_SHIFT, RTC_LR_SRL_WIDTH))
19070 /*@}*/
19071 
19072 /*!
19073  * @name Register RTC_LR, field LRL[6] (RW)
19074  *
19075  * After being cleared, this bit can be set only by POR or software reset.
19076  *
19077  * Values:
19078  * - 0b0 - Lock Register is locked and writes are ignored.
19079  * - 0b1 - Lock Register is not locked and writes complete as normal.
19080  */
19081 /*@{*/
19082 /*! @brief Read current value of the RTC_LR_LRL field. */
19083 #define RTC_RD_LR_LRL(base)  ((RTC_LR_REG(base) & RTC_LR_LRL_MASK) >> RTC_LR_LRL_SHIFT)
19084 #define RTC_BRD_LR_LRL(base) (BME_UBFX32(&RTC_LR_REG(base), RTC_LR_LRL_SHIFT, RTC_LR_LRL_WIDTH))
19085 
19086 /*! @brief Set the LRL field to a new value. */
19087 #define RTC_WR_LR_LRL(base, value) (RTC_RMW_LR(base, RTC_LR_LRL_MASK, RTC_LR_LRL(value)))
19088 #define RTC_BWR_LR_LRL(base, value) (BME_BFI32(&RTC_LR_REG(base), ((uint32_t)(value) << RTC_LR_LRL_SHIFT), RTC_LR_LRL_SHIFT, RTC_LR_LRL_WIDTH))
19089 /*@}*/
19090 
19091 /*******************************************************************************
19092  * RTC_IER - RTC Interrupt Enable Register
19093  ******************************************************************************/
19094 
19095 /*!
19096  * @brief RTC_IER - RTC Interrupt Enable Register (RW)
19097  *
19098  * Reset value: 0x00000007U
19099  */
19100 /*!
19101  * @name Constants and macros for entire RTC_IER register
19102  */
19103 /*@{*/
19104 #define RTC_RD_IER(base)         (RTC_IER_REG(base))
19105 #define RTC_WR_IER(base, value)  (RTC_IER_REG(base) = (value))
19106 #define RTC_RMW_IER(base, mask, value) (RTC_WR_IER(base, (RTC_RD_IER(base) & ~(mask)) | (value)))
19107 #define RTC_SET_IER(base, value) (BME_OR32(&RTC_IER_REG(base), (uint32_t)(value)))
19108 #define RTC_CLR_IER(base, value) (BME_AND32(&RTC_IER_REG(base), (uint32_t)(~(value))))
19109 #define RTC_TOG_IER(base, value) (BME_XOR32(&RTC_IER_REG(base), (uint32_t)(value)))
19110 /*@}*/
19111 
19112 /*
19113  * Constants & macros for individual RTC_IER bitfields
19114  */
19115 
19116 /*!
19117  * @name Register RTC_IER, field TIIE[0] (RW)
19118  *
19119  * Values:
19120  * - 0b0 - Time invalid flag does not generate an interrupt.
19121  * - 0b1 - Time invalid flag does generate an interrupt.
19122  */
19123 /*@{*/
19124 /*! @brief Read current value of the RTC_IER_TIIE field. */
19125 #define RTC_RD_IER_TIIE(base) ((RTC_IER_REG(base) & RTC_IER_TIIE_MASK) >> RTC_IER_TIIE_SHIFT)
19126 #define RTC_BRD_IER_TIIE(base) (BME_UBFX32(&RTC_IER_REG(base), RTC_IER_TIIE_SHIFT, RTC_IER_TIIE_WIDTH))
19127 
19128 /*! @brief Set the TIIE field to a new value. */
19129 #define RTC_WR_IER_TIIE(base, value) (RTC_RMW_IER(base, RTC_IER_TIIE_MASK, RTC_IER_TIIE(value)))
19130 #define RTC_BWR_IER_TIIE(base, value) (BME_BFI32(&RTC_IER_REG(base), ((uint32_t)(value) << RTC_IER_TIIE_SHIFT), RTC_IER_TIIE_SHIFT, RTC_IER_TIIE_WIDTH))
19131 /*@}*/
19132 
19133 /*!
19134  * @name Register RTC_IER, field TOIE[1] (RW)
19135  *
19136  * Values:
19137  * - 0b0 - Time overflow flag does not generate an interrupt.
19138  * - 0b1 - Time overflow flag does generate an interrupt.
19139  */
19140 /*@{*/
19141 /*! @brief Read current value of the RTC_IER_TOIE field. */
19142 #define RTC_RD_IER_TOIE(base) ((RTC_IER_REG(base) & RTC_IER_TOIE_MASK) >> RTC_IER_TOIE_SHIFT)
19143 #define RTC_BRD_IER_TOIE(base) (BME_UBFX32(&RTC_IER_REG(base), RTC_IER_TOIE_SHIFT, RTC_IER_TOIE_WIDTH))
19144 
19145 /*! @brief Set the TOIE field to a new value. */
19146 #define RTC_WR_IER_TOIE(base, value) (RTC_RMW_IER(base, RTC_IER_TOIE_MASK, RTC_IER_TOIE(value)))
19147 #define RTC_BWR_IER_TOIE(base, value) (BME_BFI32(&RTC_IER_REG(base), ((uint32_t)(value) << RTC_IER_TOIE_SHIFT), RTC_IER_TOIE_SHIFT, RTC_IER_TOIE_WIDTH))
19148 /*@}*/
19149 
19150 /*!
19151  * @name Register RTC_IER, field TAIE[2] (RW)
19152  *
19153  * Values:
19154  * - 0b0 - Time alarm flag does not generate an interrupt.
19155  * - 0b1 - Time alarm flag does generate an interrupt.
19156  */
19157 /*@{*/
19158 /*! @brief Read current value of the RTC_IER_TAIE field. */
19159 #define RTC_RD_IER_TAIE(base) ((RTC_IER_REG(base) & RTC_IER_TAIE_MASK) >> RTC_IER_TAIE_SHIFT)
19160 #define RTC_BRD_IER_TAIE(base) (BME_UBFX32(&RTC_IER_REG(base), RTC_IER_TAIE_SHIFT, RTC_IER_TAIE_WIDTH))
19161 
19162 /*! @brief Set the TAIE field to a new value. */
19163 #define RTC_WR_IER_TAIE(base, value) (RTC_RMW_IER(base, RTC_IER_TAIE_MASK, RTC_IER_TAIE(value)))
19164 #define RTC_BWR_IER_TAIE(base, value) (BME_BFI32(&RTC_IER_REG(base), ((uint32_t)(value) << RTC_IER_TAIE_SHIFT), RTC_IER_TAIE_SHIFT, RTC_IER_TAIE_WIDTH))
19165 /*@}*/
19166 
19167 /*!
19168  * @name Register RTC_IER, field TSIE[4] (RW)
19169  *
19170  * The seconds interrupt is an edge-sensitive interrupt with a dedicated
19171  * interrupt vector. It is generated once a second and requires no software overhead
19172  * (there is no corresponding status flag to clear).
19173  *
19174  * Values:
19175  * - 0b0 - Seconds interrupt is disabled.
19176  * - 0b1 - Seconds interrupt is enabled.
19177  */
19178 /*@{*/
19179 /*! @brief Read current value of the RTC_IER_TSIE field. */
19180 #define RTC_RD_IER_TSIE(base) ((RTC_IER_REG(base) & RTC_IER_TSIE_MASK) >> RTC_IER_TSIE_SHIFT)
19181 #define RTC_BRD_IER_TSIE(base) (BME_UBFX32(&RTC_IER_REG(base), RTC_IER_TSIE_SHIFT, RTC_IER_TSIE_WIDTH))
19182 
19183 /*! @brief Set the TSIE field to a new value. */
19184 #define RTC_WR_IER_TSIE(base, value) (RTC_RMW_IER(base, RTC_IER_TSIE_MASK, RTC_IER_TSIE(value)))
19185 #define RTC_BWR_IER_TSIE(base, value) (BME_BFI32(&RTC_IER_REG(base), ((uint32_t)(value) << RTC_IER_TSIE_SHIFT), RTC_IER_TSIE_SHIFT, RTC_IER_TSIE_WIDTH))
19186 /*@}*/
19187 
19188 /*!
19189  * @name Register RTC_IER, field WPON[7] (RW)
19190  *
19191  * The wakeup pin is optional and not available on all devices. Whenever the
19192  * wakeup pin is enabled and this bit is set, the wakeup pin will assert.
19193  *
19194  * Values:
19195  * - 0b0 - No effect.
19196  * - 0b1 - If the wakeup pin is enabled, then the wakeup pin will assert.
19197  */
19198 /*@{*/
19199 /*! @brief Read current value of the RTC_IER_WPON field. */
19200 #define RTC_RD_IER_WPON(base) ((RTC_IER_REG(base) & RTC_IER_WPON_MASK) >> RTC_IER_WPON_SHIFT)
19201 #define RTC_BRD_IER_WPON(base) (BME_UBFX32(&RTC_IER_REG(base), RTC_IER_WPON_SHIFT, RTC_IER_WPON_WIDTH))
19202 
19203 /*! @brief Set the WPON field to a new value. */
19204 #define RTC_WR_IER_WPON(base, value) (RTC_RMW_IER(base, RTC_IER_WPON_MASK, RTC_IER_WPON(value)))
19205 #define RTC_BWR_IER_WPON(base, value) (BME_BFI32(&RTC_IER_REG(base), ((uint32_t)(value) << RTC_IER_WPON_SHIFT), RTC_IER_WPON_SHIFT, RTC_IER_WPON_WIDTH))
19206 /*@}*/
19207 
19208 /*
19209  * MKW40Z4 SIM
19210  *
19211  * System Integration Module
19212  *
19213  * Registers defined in this header file:
19214  * - SIM_SOPT1 - System Options Register 1
19215  * - SIM_SOPT2 - System Options Register 2
19216  * - SIM_SOPT4 - System Options Register 4
19217  * - SIM_SOPT5 - System Options Register 5
19218  * - SIM_SOPT7 - System Options Register 7
19219  * - SIM_SDID - System Device Identification Register
19220  * - SIM_SCGC4 - System Clock Gating Control Register 4
19221  * - SIM_SCGC5 - System Clock Gating Control Register 5
19222  * - SIM_SCGC6 - System Clock Gating Control Register 6
19223  * - SIM_SCGC7 - System Clock Gating Control Register 7
19224  * - SIM_CLKDIV1 - System Clock Divider Register 1
19225  * - SIM_FCFG1 - Flash Configuration Register 1
19226  * - SIM_FCFG2 - Flash Configuration Register 2
19227  * - SIM_UIDMH - Unique Identification Register Mid-High
19228  * - SIM_UIDML - Unique Identification Register Mid Low
19229  * - SIM_UIDL - Unique Identification Register Low
19230  * - SIM_COPC - COP Control Register
19231  * - SIM_SRVCOP - Service COP
19232  */
19233 
19234 #define SIM_INSTANCE_COUNT (1U) /*!< Number of instances of the SIM module. */
19235 #define SIM_IDX (0U) /*!< Instance number for SIM. */
19236 
19237 /*******************************************************************************
19238  * SIM_SOPT1 - System Options Register 1
19239  ******************************************************************************/
19240 
19241 /*!
19242  * @brief SIM_SOPT1 - System Options Register 1 (RW)
19243  *
19244  * Reset value: 0x00000000U
19245  *
19246  * The SOPT1 register is only reset on POR or LVD. Reset value loaded during
19247  * System Reset from Flash IFR.
19248  */
19249 /*!
19250  * @name Constants and macros for entire SIM_SOPT1 register
19251  */
19252 /*@{*/
19253 #define SIM_RD_SOPT1(base)       (SIM_SOPT1_REG(base))
19254 #define SIM_WR_SOPT1(base, value) (SIM_SOPT1_REG(base) = (value))
19255 #define SIM_RMW_SOPT1(base, mask, value) (SIM_WR_SOPT1(base, (SIM_RD_SOPT1(base) & ~(mask)) | (value)))
19256 #define SIM_SET_SOPT1(base, value) (BME_OR32(&SIM_SOPT1_REG(base), (uint32_t)(value)))
19257 #define SIM_CLR_SOPT1(base, value) (BME_AND32(&SIM_SOPT1_REG(base), (uint32_t)(~(value))))
19258 #define SIM_TOG_SOPT1(base, value) (BME_XOR32(&SIM_SOPT1_REG(base), (uint32_t)(value)))
19259 /*@}*/
19260 
19261 /*
19262  * Constants & macros for individual SIM_SOPT1 bitfields
19263  */
19264 
19265 /*!
19266  * @name Register SIM_SOPT1, field OSC32KOUT[17:16] (RW)
19267  *
19268  * Outputs the ERCLK32K on the selected pin in all modes of operation (including
19269  * LLS/VLLS and System Reset), overriding the existing pin mux configuration for
19270  * that pin. This field is reset only on POR/LVD.
19271  *
19272  * Values:
19273  * - 0b00 - ERCLK32K is not output.
19274  * - 0b01 - ERCLK32K is output on PTB3.
19275  * - 0b10 - Reserved.
19276  * - 0b11 - Reserved.
19277  */
19278 /*@{*/
19279 /*! @brief Read current value of the SIM_SOPT1_OSC32KOUT field. */
19280 #define SIM_RD_SOPT1_OSC32KOUT(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_OSC32KOUT_MASK) >> SIM_SOPT1_OSC32KOUT_SHIFT)
19281 #define SIM_BRD_SOPT1_OSC32KOUT(base) (BME_UBFX32(&SIM_SOPT1_REG(base), SIM_SOPT1_OSC32KOUT_SHIFT, SIM_SOPT1_OSC32KOUT_WIDTH))
19282 
19283 /*! @brief Set the OSC32KOUT field to a new value. */
19284 #define SIM_WR_SOPT1_OSC32KOUT(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_OSC32KOUT_MASK, SIM_SOPT1_OSC32KOUT(value)))
19285 #define SIM_BWR_SOPT1_OSC32KOUT(base, value) (BME_BFI32(&SIM_SOPT1_REG(base), ((uint32_t)(value) << SIM_SOPT1_OSC32KOUT_SHIFT), SIM_SOPT1_OSC32KOUT_SHIFT, SIM_SOPT1_OSC32KOUT_WIDTH))
19286 /*@}*/
19287 
19288 /*!
19289  * @name Register SIM_SOPT1, field OSC32KSEL[19:18] (RW)
19290  *
19291  * Selects the 32 kHz clock source (ERCLK32K) for RTC and LPTMR. This field is
19292  * reset only on POR/LVD.
19293  *
19294  * Values:
19295  * - 0b00 - 32kHz oscillator (OSC32KCLK)
19296  * - 0b01 - Reserved
19297  * - 0b10 - RTC_CLKIN
19298  * - 0b11 - LPO 1kHz
19299  */
19300 /*@{*/
19301 /*! @brief Read current value of the SIM_SOPT1_OSC32KSEL field. */
19302 #define SIM_RD_SOPT1_OSC32KSEL(base) ((SIM_SOPT1_REG(base) & SIM_SOPT1_OSC32KSEL_MASK) >> SIM_SOPT1_OSC32KSEL_SHIFT)
19303 #define SIM_BRD_SOPT1_OSC32KSEL(base) (BME_UBFX32(&SIM_SOPT1_REG(base), SIM_SOPT1_OSC32KSEL_SHIFT, SIM_SOPT1_OSC32KSEL_WIDTH))
19304 
19305 /*! @brief Set the OSC32KSEL field to a new value. */
19306 #define SIM_WR_SOPT1_OSC32KSEL(base, value) (SIM_RMW_SOPT1(base, SIM_SOPT1_OSC32KSEL_MASK, SIM_SOPT1_OSC32KSEL(value)))
19307 #define SIM_BWR_SOPT1_OSC32KSEL(base, value) (BME_BFI32(&SIM_SOPT1_REG(base), ((uint32_t)(value) << SIM_SOPT1_OSC32KSEL_SHIFT), SIM_SOPT1_OSC32KSEL_SHIFT, SIM_SOPT1_OSC32KSEL_WIDTH))
19308 /*@}*/
19309 
19310 /*******************************************************************************
19311  * SIM_SOPT2 - System Options Register 2
19312  ******************************************************************************/
19313 
19314 /*!
19315  * @brief SIM_SOPT2 - System Options Register 2 (RW)
19316  *
19317  * Reset value: 0x00000000U
19318  *
19319  * SOPT2 contains the controls for selecting many of the module clock source
19320  * options on this device. See the Clock Distribution chapter for more information
19321  * including clocking diagrams and definitions of device clocks.
19322  */
19323 /*!
19324  * @name Constants and macros for entire SIM_SOPT2 register
19325  */
19326 /*@{*/
19327 #define SIM_RD_SOPT2(base)       (SIM_SOPT2_REG(base))
19328 #define SIM_WR_SOPT2(base, value) (SIM_SOPT2_REG(base) = (value))
19329 #define SIM_RMW_SOPT2(base, mask, value) (SIM_WR_SOPT2(base, (SIM_RD_SOPT2(base) & ~(mask)) | (value)))
19330 #define SIM_SET_SOPT2(base, value) (BME_OR32(&SIM_SOPT2_REG(base), (uint32_t)(value)))
19331 #define SIM_CLR_SOPT2(base, value) (BME_AND32(&SIM_SOPT2_REG(base), (uint32_t)(~(value))))
19332 #define SIM_TOG_SOPT2(base, value) (BME_XOR32(&SIM_SOPT2_REG(base), (uint32_t)(value)))
19333 /*@}*/
19334 
19335 /*
19336  * Constants & macros for individual SIM_SOPT2 bitfields
19337  */
19338 
19339 /*!
19340  * @name Register SIM_SOPT2, field CLKOUTSEL[7:5] (RW)
19341  *
19342  * Selects the clock to output on the CLKOUT pin.
19343  *
19344  * Values:
19345  * - 0b000 - OSCERCLK DIV2
19346  * - 0b001 - OSCERCLK DIV4
19347  * - 0b010 - Bus clock
19348  * - 0b011 - LPO clock 1 kHz
19349  * - 0b100 - MCGIRCLK
19350  * - 0b101 - OSCERCLK DIV8
19351  * - 0b110 - OSCERCLK
19352  * - 0b111 - Reserved
19353  */
19354 /*@{*/
19355 /*! @brief Read current value of the SIM_SOPT2_CLKOUTSEL field. */
19356 #define SIM_RD_SOPT2_CLKOUTSEL(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_CLKOUTSEL_MASK) >> SIM_SOPT2_CLKOUTSEL_SHIFT)
19357 #define SIM_BRD_SOPT2_CLKOUTSEL(base) (BME_UBFX32(&SIM_SOPT2_REG(base), SIM_SOPT2_CLKOUTSEL_SHIFT, SIM_SOPT2_CLKOUTSEL_WIDTH))
19358 
19359 /*! @brief Set the CLKOUTSEL field to a new value. */
19360 #define SIM_WR_SOPT2_CLKOUTSEL(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_CLKOUTSEL_MASK, SIM_SOPT2_CLKOUTSEL(value)))
19361 #define SIM_BWR_SOPT2_CLKOUTSEL(base, value) (BME_BFI32(&SIM_SOPT2_REG(base), ((uint32_t)(value) << SIM_SOPT2_CLKOUTSEL_SHIFT), SIM_SOPT2_CLKOUTSEL_SHIFT, SIM_SOPT2_CLKOUTSEL_WIDTH))
19362 /*@}*/
19363 
19364 /*!
19365  * @name Register SIM_SOPT2, field TPMSRC[25:24] (RW)
19366  *
19367  * Selects the clock source for the TPM counter clock
19368  *
19369  * Values:
19370  * - 0b00 - Clock disabled
19371  * - 0b01 - MCGFLLCLK clock
19372  * - 0b10 - OSCERCLK clock
19373  * - 0b11 - MCGIRCLK clock
19374  */
19375 /*@{*/
19376 /*! @brief Read current value of the SIM_SOPT2_TPMSRC field. */
19377 #define SIM_RD_SOPT2_TPMSRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_TPMSRC_MASK) >> SIM_SOPT2_TPMSRC_SHIFT)
19378 #define SIM_BRD_SOPT2_TPMSRC(base) (BME_UBFX32(&SIM_SOPT2_REG(base), SIM_SOPT2_TPMSRC_SHIFT, SIM_SOPT2_TPMSRC_WIDTH))
19379 
19380 /*! @brief Set the TPMSRC field to a new value. */
19381 #define SIM_WR_SOPT2_TPMSRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_TPMSRC_MASK, SIM_SOPT2_TPMSRC(value)))
19382 #define SIM_BWR_SOPT2_TPMSRC(base, value) (BME_BFI32(&SIM_SOPT2_REG(base), ((uint32_t)(value) << SIM_SOPT2_TPMSRC_SHIFT), SIM_SOPT2_TPMSRC_SHIFT, SIM_SOPT2_TPMSRC_WIDTH))
19383 /*@}*/
19384 
19385 /*!
19386  * @name Register SIM_SOPT2, field LPUART0SRC[27:26] (RW)
19387  *
19388  * Selects the clock source for the LPUART0 transmit and receive clock.
19389  *
19390  * Values:
19391  * - 0b00 - Clock disabled
19392  * - 0b01 - MCGFLLCLK clock
19393  * - 0b10 - OSCERCLK clock
19394  * - 0b11 - MCGIRCLK clock
19395  */
19396 /*@{*/
19397 /*! @brief Read current value of the SIM_SOPT2_LPUART0SRC field. */
19398 #define SIM_RD_SOPT2_LPUART0SRC(base) ((SIM_SOPT2_REG(base) & SIM_SOPT2_LPUART0SRC_MASK) >> SIM_SOPT2_LPUART0SRC_SHIFT)
19399 #define SIM_BRD_SOPT2_LPUART0SRC(base) (BME_UBFX32(&SIM_SOPT2_REG(base), SIM_SOPT2_LPUART0SRC_SHIFT, SIM_SOPT2_LPUART0SRC_WIDTH))
19400 
19401 /*! @brief Set the LPUART0SRC field to a new value. */
19402 #define SIM_WR_SOPT2_LPUART0SRC(base, value) (SIM_RMW_SOPT2(base, SIM_SOPT2_LPUART0SRC_MASK, SIM_SOPT2_LPUART0SRC(value)))
19403 #define SIM_BWR_SOPT2_LPUART0SRC(base, value) (BME_BFI32(&SIM_SOPT2_REG(base), ((uint32_t)(value) << SIM_SOPT2_LPUART0SRC_SHIFT), SIM_SOPT2_LPUART0SRC_SHIFT, SIM_SOPT2_LPUART0SRC_WIDTH))
19404 /*@}*/
19405 
19406 /*******************************************************************************
19407  * SIM_SOPT4 - System Options Register 4
19408  ******************************************************************************/
19409 
19410 /*!
19411  * @brief SIM_SOPT4 - System Options Register 4 (RW)
19412  *
19413  * Reset value: 0x00000000U
19414  */
19415 /*!
19416  * @name Constants and macros for entire SIM_SOPT4 register
19417  */
19418 /*@{*/
19419 #define SIM_RD_SOPT4(base)       (SIM_SOPT4_REG(base))
19420 #define SIM_WR_SOPT4(base, value) (SIM_SOPT4_REG(base) = (value))
19421 #define SIM_RMW_SOPT4(base, mask, value) (SIM_WR_SOPT4(base, (SIM_RD_SOPT4(base) & ~(mask)) | (value)))
19422 #define SIM_SET_SOPT4(base, value) (BME_OR32(&SIM_SOPT4_REG(base), (uint32_t)(value)))
19423 #define SIM_CLR_SOPT4(base, value) (BME_AND32(&SIM_SOPT4_REG(base), (uint32_t)(~(value))))
19424 #define SIM_TOG_SOPT4(base, value) (BME_XOR32(&SIM_SOPT4_REG(base), (uint32_t)(value)))
19425 /*@}*/
19426 
19427 /*
19428  * Constants & macros for individual SIM_SOPT4 bitfields
19429  */
19430 
19431 /*!
19432  * @name Register SIM_SOPT4, field TPM1CH0SRC[18] (RW)
19433  *
19434  * Selects the source for TPM1 channel 0 input capture. When TPM1 is not in
19435  * input capture mode, clear this field.
19436  *
19437  * Values:
19438  * - 0b0 - TPM1_CH0 signal
19439  * - 0b1 - CMP0 output
19440  */
19441 /*@{*/
19442 /*! @brief Read current value of the SIM_SOPT4_TPM1CH0SRC field. */
19443 #define SIM_RD_SOPT4_TPM1CH0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_TPM1CH0SRC_MASK) >> SIM_SOPT4_TPM1CH0SRC_SHIFT)
19444 #define SIM_BRD_SOPT4_TPM1CH0SRC(base) (BME_UBFX32(&SIM_SOPT4_REG(base), SIM_SOPT4_TPM1CH0SRC_SHIFT, SIM_SOPT4_TPM1CH0SRC_WIDTH))
19445 
19446 /*! @brief Set the TPM1CH0SRC field to a new value. */
19447 #define SIM_WR_SOPT4_TPM1CH0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_TPM1CH0SRC_MASK, SIM_SOPT4_TPM1CH0SRC(value)))
19448 #define SIM_BWR_SOPT4_TPM1CH0SRC(base, value) (BME_BFI32(&SIM_SOPT4_REG(base), ((uint32_t)(value) << SIM_SOPT4_TPM1CH0SRC_SHIFT), SIM_SOPT4_TPM1CH0SRC_SHIFT, SIM_SOPT4_TPM1CH0SRC_WIDTH))
19449 /*@}*/
19450 
19451 /*!
19452  * @name Register SIM_SOPT4, field TPM2CH0SRC[20] (RW)
19453  *
19454  * Selects the source for TPM2 channel 0 input capture. When TPM2 is not in
19455  * input capture mode, clear this field.
19456  *
19457  * Values:
19458  * - 0b0 - TPM2_CH0 signal
19459  * - 0b1 - CMP0 output
19460  */
19461 /*@{*/
19462 /*! @brief Read current value of the SIM_SOPT4_TPM2CH0SRC field. */
19463 #define SIM_RD_SOPT4_TPM2CH0SRC(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_TPM2CH0SRC_MASK) >> SIM_SOPT4_TPM2CH0SRC_SHIFT)
19464 #define SIM_BRD_SOPT4_TPM2CH0SRC(base) (BME_UBFX32(&SIM_SOPT4_REG(base), SIM_SOPT4_TPM2CH0SRC_SHIFT, SIM_SOPT4_TPM2CH0SRC_WIDTH))
19465 
19466 /*! @brief Set the TPM2CH0SRC field to a new value. */
19467 #define SIM_WR_SOPT4_TPM2CH0SRC(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_TPM2CH0SRC_MASK, SIM_SOPT4_TPM2CH0SRC(value)))
19468 #define SIM_BWR_SOPT4_TPM2CH0SRC(base, value) (BME_BFI32(&SIM_SOPT4_REG(base), ((uint32_t)(value) << SIM_SOPT4_TPM2CH0SRC_SHIFT), SIM_SOPT4_TPM2CH0SRC_SHIFT, SIM_SOPT4_TPM2CH0SRC_WIDTH))
19469 /*@}*/
19470 
19471 /*!
19472  * @name Register SIM_SOPT4, field TPM0CLKSEL[24] (RW)
19473  *
19474  * Selects the external pin used to drive the clock to the TPM0 module. The
19475  * selected pin must also be configured for the TPM external clock function through
19476  * the appropriate pin control register in the port control module.
19477  *
19478  * Values:
19479  * - 0b0 - TPM0 external clock driven by TPM_CLKIN0 pin.
19480  * - 0b1 - TPM0 external clock driven by TPM_CLKIN1 pin.
19481  */
19482 /*@{*/
19483 /*! @brief Read current value of the SIM_SOPT4_TPM0CLKSEL field. */
19484 #define SIM_RD_SOPT4_TPM0CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_TPM0CLKSEL_MASK) >> SIM_SOPT4_TPM0CLKSEL_SHIFT)
19485 #define SIM_BRD_SOPT4_TPM0CLKSEL(base) (BME_UBFX32(&SIM_SOPT4_REG(base), SIM_SOPT4_TPM0CLKSEL_SHIFT, SIM_SOPT4_TPM0CLKSEL_WIDTH))
19486 
19487 /*! @brief Set the TPM0CLKSEL field to a new value. */
19488 #define SIM_WR_SOPT4_TPM0CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_TPM0CLKSEL_MASK, SIM_SOPT4_TPM0CLKSEL(value)))
19489 #define SIM_BWR_SOPT4_TPM0CLKSEL(base, value) (BME_BFI32(&SIM_SOPT4_REG(base), ((uint32_t)(value) << SIM_SOPT4_TPM0CLKSEL_SHIFT), SIM_SOPT4_TPM0CLKSEL_SHIFT, SIM_SOPT4_TPM0CLKSEL_WIDTH))
19490 /*@}*/
19491 
19492 /*!
19493  * @name Register SIM_SOPT4, field TPM1CLKSEL[25] (RW)
19494  *
19495  * Selects the external pin used to drive the clock to the TPM1 module. The
19496  * selected pin must also be configured for the TPM external clock function through
19497  * the appropriate pin control register in the port control module.
19498  *
19499  * Values:
19500  * - 0b0 - TPM1 external clock driven by TPM_CLKIN0 pin.
19501  * - 0b1 - TPM1 external clock driven by TPM_CLKIN1 pin.
19502  */
19503 /*@{*/
19504 /*! @brief Read current value of the SIM_SOPT4_TPM1CLKSEL field. */
19505 #define SIM_RD_SOPT4_TPM1CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_TPM1CLKSEL_MASK) >> SIM_SOPT4_TPM1CLKSEL_SHIFT)
19506 #define SIM_BRD_SOPT4_TPM1CLKSEL(base) (BME_UBFX32(&SIM_SOPT4_REG(base), SIM_SOPT4_TPM1CLKSEL_SHIFT, SIM_SOPT4_TPM1CLKSEL_WIDTH))
19507 
19508 /*! @brief Set the TPM1CLKSEL field to a new value. */
19509 #define SIM_WR_SOPT4_TPM1CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_TPM1CLKSEL_MASK, SIM_SOPT4_TPM1CLKSEL(value)))
19510 #define SIM_BWR_SOPT4_TPM1CLKSEL(base, value) (BME_BFI32(&SIM_SOPT4_REG(base), ((uint32_t)(value) << SIM_SOPT4_TPM1CLKSEL_SHIFT), SIM_SOPT4_TPM1CLKSEL_SHIFT, SIM_SOPT4_TPM1CLKSEL_WIDTH))
19511 /*@}*/
19512 
19513 /*!
19514  * @name Register SIM_SOPT4, field TPM2CLKSEL[26] (RW)
19515  *
19516  * Selects the external pin used to drive the clock to the TPM2 module. The
19517  * selected pin must also be configured for the TPM external clock function through
19518  * the appropriate Pin Control Register in the Port Control module.
19519  *
19520  * Values:
19521  * - 0b0 - TPM2 external clock driven by TPM_CLKIN0 pin.
19522  * - 0b1 - TPM2 external clock driven by TPM_CLKIN1 pin.
19523  */
19524 /*@{*/
19525 /*! @brief Read current value of the SIM_SOPT4_TPM2CLKSEL field. */
19526 #define SIM_RD_SOPT4_TPM2CLKSEL(base) ((SIM_SOPT4_REG(base) & SIM_SOPT4_TPM2CLKSEL_MASK) >> SIM_SOPT4_TPM2CLKSEL_SHIFT)
19527 #define SIM_BRD_SOPT4_TPM2CLKSEL(base) (BME_UBFX32(&SIM_SOPT4_REG(base), SIM_SOPT4_TPM2CLKSEL_SHIFT, SIM_SOPT4_TPM2CLKSEL_WIDTH))
19528 
19529 /*! @brief Set the TPM2CLKSEL field to a new value. */
19530 #define SIM_WR_SOPT4_TPM2CLKSEL(base, value) (SIM_RMW_SOPT4(base, SIM_SOPT4_TPM2CLKSEL_MASK, SIM_SOPT4_TPM2CLKSEL(value)))
19531 #define SIM_BWR_SOPT4_TPM2CLKSEL(base, value) (BME_BFI32(&SIM_SOPT4_REG(base), ((uint32_t)(value) << SIM_SOPT4_TPM2CLKSEL_SHIFT), SIM_SOPT4_TPM2CLKSEL_SHIFT, SIM_SOPT4_TPM2CLKSEL_WIDTH))
19532 /*@}*/
19533 
19534 /*******************************************************************************
19535  * SIM_SOPT5 - System Options Register 5
19536  ******************************************************************************/
19537 
19538 /*!
19539  * @brief SIM_SOPT5 - System Options Register 5 (RW)
19540  *
19541  * Reset value: 0x00000000U
19542  */
19543 /*!
19544  * @name Constants and macros for entire SIM_SOPT5 register
19545  */
19546 /*@{*/
19547 #define SIM_RD_SOPT5(base)       (SIM_SOPT5_REG(base))
19548 #define SIM_WR_SOPT5(base, value) (SIM_SOPT5_REG(base) = (value))
19549 #define SIM_RMW_SOPT5(base, mask, value) (SIM_WR_SOPT5(base, (SIM_RD_SOPT5(base) & ~(mask)) | (value)))
19550 #define SIM_SET_SOPT5(base, value) (BME_OR32(&SIM_SOPT5_REG(base), (uint32_t)(value)))
19551 #define SIM_CLR_SOPT5(base, value) (BME_AND32(&SIM_SOPT5_REG(base), (uint32_t)(~(value))))
19552 #define SIM_TOG_SOPT5(base, value) (BME_XOR32(&SIM_SOPT5_REG(base), (uint32_t)(value)))
19553 /*@}*/
19554 
19555 /*
19556  * Constants & macros for individual SIM_SOPT5 bitfields
19557  */
19558 
19559 /*!
19560  * @name Register SIM_SOPT5, field LPUART0TXSRC[1:0] (RW)
19561  *
19562  * Selects the source for the LPUART0 transmit data.
19563  *
19564  * Values:
19565  * - 0b00 - LPUART0_TX pin
19566  * - 0b01 - LPUART0_TX pin modulated with TPM1 channel 0 output
19567  * - 0b10 - LPUART0_TX pin modulated with TPM2 channel 0 output
19568  * - 0b11 - Reserved
19569  */
19570 /*@{*/
19571 /*! @brief Read current value of the SIM_SOPT5_LPUART0TXSRC field. */
19572 #define SIM_RD_SOPT5_LPUART0TXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_LPUART0TXSRC_MASK) >> SIM_SOPT5_LPUART0TXSRC_SHIFT)
19573 #define SIM_BRD_SOPT5_LPUART0TXSRC(base) (BME_UBFX32(&SIM_SOPT5_REG(base), SIM_SOPT5_LPUART0TXSRC_SHIFT, SIM_SOPT5_LPUART0TXSRC_WIDTH))
19574 
19575 /*! @brief Set the LPUART0TXSRC field to a new value. */
19576 #define SIM_WR_SOPT5_LPUART0TXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_LPUART0TXSRC_MASK, SIM_SOPT5_LPUART0TXSRC(value)))
19577 #define SIM_BWR_SOPT5_LPUART0TXSRC(base, value) (BME_BFI32(&SIM_SOPT5_REG(base), ((uint32_t)(value) << SIM_SOPT5_LPUART0TXSRC_SHIFT), SIM_SOPT5_LPUART0TXSRC_SHIFT, SIM_SOPT5_LPUART0TXSRC_WIDTH))
19578 /*@}*/
19579 
19580 /*!
19581  * @name Register SIM_SOPT5, field LPUART0RXSRC[2] (RW)
19582  *
19583  * Selects the source for the LPUART0 receive data.
19584  *
19585  * Values:
19586  * - 0b0 - LPUART_RX pin
19587  * - 0b1 - CMP0 output
19588  */
19589 /*@{*/
19590 /*! @brief Read current value of the SIM_SOPT5_LPUART0RXSRC field. */
19591 #define SIM_RD_SOPT5_LPUART0RXSRC(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_LPUART0RXSRC_MASK) >> SIM_SOPT5_LPUART0RXSRC_SHIFT)
19592 #define SIM_BRD_SOPT5_LPUART0RXSRC(base) (BME_UBFX32(&SIM_SOPT5_REG(base), SIM_SOPT5_LPUART0RXSRC_SHIFT, SIM_SOPT5_LPUART0RXSRC_WIDTH))
19593 
19594 /*! @brief Set the LPUART0RXSRC field to a new value. */
19595 #define SIM_WR_SOPT5_LPUART0RXSRC(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_LPUART0RXSRC_MASK, SIM_SOPT5_LPUART0RXSRC(value)))
19596 #define SIM_BWR_SOPT5_LPUART0RXSRC(base, value) (BME_BFI32(&SIM_SOPT5_REG(base), ((uint32_t)(value) << SIM_SOPT5_LPUART0RXSRC_SHIFT), SIM_SOPT5_LPUART0RXSRC_SHIFT, SIM_SOPT5_LPUART0RXSRC_WIDTH))
19597 /*@}*/
19598 
19599 /*!
19600  * @name Register SIM_SOPT5, field LPUART0ODE[16] (RW)
19601  *
19602  * Values:
19603  * - 0b0 - Open drain is disabled on LPUART0.
19604  * - 0b1 - Open drain is enabled on LPUART0.
19605  */
19606 /*@{*/
19607 /*! @brief Read current value of the SIM_SOPT5_LPUART0ODE field. */
19608 #define SIM_RD_SOPT5_LPUART0ODE(base) ((SIM_SOPT5_REG(base) & SIM_SOPT5_LPUART0ODE_MASK) >> SIM_SOPT5_LPUART0ODE_SHIFT)
19609 #define SIM_BRD_SOPT5_LPUART0ODE(base) (BME_UBFX32(&SIM_SOPT5_REG(base), SIM_SOPT5_LPUART0ODE_SHIFT, SIM_SOPT5_LPUART0ODE_WIDTH))
19610 
19611 /*! @brief Set the LPUART0ODE field to a new value. */
19612 #define SIM_WR_SOPT5_LPUART0ODE(base, value) (SIM_RMW_SOPT5(base, SIM_SOPT5_LPUART0ODE_MASK, SIM_SOPT5_LPUART0ODE(value)))
19613 #define SIM_BWR_SOPT5_LPUART0ODE(base, value) (BME_BFI32(&SIM_SOPT5_REG(base), ((uint32_t)(value) << SIM_SOPT5_LPUART0ODE_SHIFT), SIM_SOPT5_LPUART0ODE_SHIFT, SIM_SOPT5_LPUART0ODE_WIDTH))
19614 /*@}*/
19615 
19616 /*******************************************************************************
19617  * SIM_SOPT7 - System Options Register 7
19618  ******************************************************************************/
19619 
19620 /*!
19621  * @brief SIM_SOPT7 - System Options Register 7 (RW)
19622  *
19623  * Reset value: 0x00000000U
19624  */
19625 /*!
19626  * @name Constants and macros for entire SIM_SOPT7 register
19627  */
19628 /*@{*/
19629 #define SIM_RD_SOPT7(base)       (SIM_SOPT7_REG(base))
19630 #define SIM_WR_SOPT7(base, value) (SIM_SOPT7_REG(base) = (value))
19631 #define SIM_RMW_SOPT7(base, mask, value) (SIM_WR_SOPT7(base, (SIM_RD_SOPT7(base) & ~(mask)) | (value)))
19632 #define SIM_SET_SOPT7(base, value) (BME_OR32(&SIM_SOPT7_REG(base), (uint32_t)(value)))
19633 #define SIM_CLR_SOPT7(base, value) (BME_AND32(&SIM_SOPT7_REG(base), (uint32_t)(~(value))))
19634 #define SIM_TOG_SOPT7(base, value) (BME_XOR32(&SIM_SOPT7_REG(base), (uint32_t)(value)))
19635 /*@}*/
19636 
19637 /*
19638  * Constants & macros for individual SIM_SOPT7 bitfields
19639  */
19640 
19641 /*!
19642  * @name Register SIM_SOPT7, field ADC0TRGSEL[3:0] (RW)
19643  *
19644  * Selects 1 of 16 peripherals to initiate an ADC conversion via the ADHWDT
19645  * input, when ADC0ALTTRGEN =1, else is ignored by ADC0.
19646  *
19647  * Values:
19648  * - 0b0000 - External trigger pin input (EXTRG_IN)
19649  * - 0b0001 - CMP0 output
19650  * - 0b0010 - Reserved
19651  * - 0b0011 - Reserved
19652  * - 0b0100 - PIT trigger 0
19653  * - 0b0101 - PIT trigger 1
19654  * - 0b0110 - Reserved
19655  * - 0b0111 - Reserved
19656  * - 0b1000 - TPM0 overflow
19657  * - 0b1001 - TPM1 overflow
19658  * - 0b1010 - TPM2 overflow
19659  * - 0b1011 - Reserved
19660  * - 0b1100 - RTC alarm
19661  * - 0b1101 - RTC seconds
19662  * - 0b1110 - LPTMR0 trigger
19663  * - 0b1111 - Radio TSM
19664  */
19665 /*@{*/
19666 /*! @brief Read current value of the SIM_SOPT7_ADC0TRGSEL field. */
19667 #define SIM_RD_SOPT7_ADC0TRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0TRGSEL_MASK) >> SIM_SOPT7_ADC0TRGSEL_SHIFT)
19668 #define SIM_BRD_SOPT7_ADC0TRGSEL(base) (BME_UBFX32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0TRGSEL_SHIFT, SIM_SOPT7_ADC0TRGSEL_WIDTH))
19669 
19670 /*! @brief Set the ADC0TRGSEL field to a new value. */
19671 #define SIM_WR_SOPT7_ADC0TRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0TRGSEL_MASK, SIM_SOPT7_ADC0TRGSEL(value)))
19672 #define SIM_BWR_SOPT7_ADC0TRGSEL(base, value) (BME_BFI32(&SIM_SOPT7_REG(base), ((uint32_t)(value) << SIM_SOPT7_ADC0TRGSEL_SHIFT), SIM_SOPT7_ADC0TRGSEL_SHIFT, SIM_SOPT7_ADC0TRGSEL_WIDTH))
19673 /*@}*/
19674 
19675 /*!
19676  * @name Register SIM_SOPT7, field ADC0PRETRGSEL[4] (RW)
19677  *
19678  * Selects the ADC0 pre-trigger source when alternative triggers are enabled
19679  * through ADC0ALTTRGEN.The ADC0PRETRGSEL function is ignored if ADC0ALTTRGEN = 0.
19680  *
19681  * Values:
19682  * - 0b0 - Pre-trigger ADHDWTSA is selected, thus ADC0 will use ADC0_SC1A
19683  *     configuration for the next ADC conversion and store the result in ADC0_RA
19684  *     register.
19685  * - 0b1 - Pre-trigger ADHDWTSB is selected, thus ADC0 will use ADC0_SC1B
19686  *     configuration for the next ADC conversion and store the result in ADC0_RB
19687  *     register.
19688  */
19689 /*@{*/
19690 /*! @brief Read current value of the SIM_SOPT7_ADC0PRETRGSEL field. */
19691 #define SIM_RD_SOPT7_ADC0PRETRGSEL(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0PRETRGSEL_MASK) >> SIM_SOPT7_ADC0PRETRGSEL_SHIFT)
19692 #define SIM_BRD_SOPT7_ADC0PRETRGSEL(base) (BME_UBFX32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0PRETRGSEL_SHIFT, SIM_SOPT7_ADC0PRETRGSEL_WIDTH))
19693 
19694 /*! @brief Set the ADC0PRETRGSEL field to a new value. */
19695 #define SIM_WR_SOPT7_ADC0PRETRGSEL(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0PRETRGSEL_MASK, SIM_SOPT7_ADC0PRETRGSEL(value)))
19696 #define SIM_BWR_SOPT7_ADC0PRETRGSEL(base, value) (BME_BFI32(&SIM_SOPT7_REG(base), ((uint32_t)(value) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT), SIM_SOPT7_ADC0PRETRGSEL_SHIFT, SIM_SOPT7_ADC0PRETRGSEL_WIDTH))
19697 /*@}*/
19698 
19699 /*!
19700  * @name Register SIM_SOPT7, field ADC0ALTTRGEN[7] (RW)
19701  *
19702  * Enables alternative conversion triggers for ADC0.
19703  *
19704  * Values:
19705  * - 0b0 - ADC ADHWT trigger comes from TPM1 channel 0 and channel1. Prior to
19706  *     the assertion of TPM1 channel 0, a pre-trigger pulse will be sent to ADHWTSA
19707  *     to initiate an ADC acquisition using ADCx_SC1A configuration and store
19708  *     ADC conversion in ADCx_RA Register. Prior to the assertion of TPM1 channel 1
19709  *     a pre-trigger pulse will be sent to ADHWTSB to initiate an ADC
19710  *     acquisition using ADCx_SC1Bconfiguration and store ADC conversion in ADCx_RB
19711  *     Register.
19712  * - 0b1 - ADC ADHWT trigger comes from a peripheral event selected by
19713  *     ADC0TRGSEL bits.ADC0PRETRGSEL bit will select the optional ADHWTSA or ADHWTSB
19714  *     select lines for choosing the ADCx_SC1x config and ADCx_Rx result regsiter to
19715  *     store the ADC conversion.
19716  */
19717 /*@{*/
19718 /*! @brief Read current value of the SIM_SOPT7_ADC0ALTTRGEN field. */
19719 #define SIM_RD_SOPT7_ADC0ALTTRGEN(base) ((SIM_SOPT7_REG(base) & SIM_SOPT7_ADC0ALTTRGEN_MASK) >> SIM_SOPT7_ADC0ALTTRGEN_SHIFT)
19720 #define SIM_BRD_SOPT7_ADC0ALTTRGEN(base) (BME_UBFX32(&SIM_SOPT7_REG(base), SIM_SOPT7_ADC0ALTTRGEN_SHIFT, SIM_SOPT7_ADC0ALTTRGEN_WIDTH))
19721 
19722 /*! @brief Set the ADC0ALTTRGEN field to a new value. */
19723 #define SIM_WR_SOPT7_ADC0ALTTRGEN(base, value) (SIM_RMW_SOPT7(base, SIM_SOPT7_ADC0ALTTRGEN_MASK, SIM_SOPT7_ADC0ALTTRGEN(value)))
19724 #define SIM_BWR_SOPT7_ADC0ALTTRGEN(base, value) (BME_BFI32(&SIM_SOPT7_REG(base), ((uint32_t)(value) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT), SIM_SOPT7_ADC0ALTTRGEN_SHIFT, SIM_SOPT7_ADC0ALTTRGEN_WIDTH))
19725 /*@}*/
19726 
19727 /*******************************************************************************
19728  * SIM_SDID - System Device Identification Register
19729  ******************************************************************************/
19730 
19731 /*!
19732  * @brief SIM_SDID - System Device Identification Register (RO)
19733  *
19734  * Reset value: 0x00500000U
19735  *
19736  * Reset value loaded during System Reset from Flash IFR.
19737  */
19738 /*!
19739  * @name Constants and macros for entire SIM_SDID register
19740  */
19741 /*@{*/
19742 #define SIM_RD_SDID(base)        (SIM_SDID_REG(base))
19743 /*@}*/
19744 
19745 /*
19746  * Constants & macros for individual SIM_SDID bitfields
19747  */
19748 
19749 /*!
19750  * @name Register SIM_SDID, field PINID[3:0] (RO)
19751  *
19752  * Specifies the pin count of the device.
19753  *
19754  * Values:
19755  * - 0b0000 - Reserved
19756  * - 0b0001 - Reserved
19757  * - 0b0010 - 32-pin
19758  * - 0b0011 - Reserved
19759  * - 0b0100 - 48-pin
19760  * - 0b0101 - Reserved
19761  * - 0b0110 - Reserved
19762  * - 0b0111 - Reserved
19763  * - 0b1000 - Reserved
19764  * - 0b1001 - Reserved
19765  * - 0b1010 - Reserved
19766  * - 0b1011 - CSP
19767  * - 0b1100 - Reserved
19768  * - 0b1101 - Reserved
19769  * - 0b1110 - Reserved
19770  * - 0b1111 - Reserved
19771  */
19772 /*@{*/
19773 /*! @brief Read current value of the SIM_SDID_PINID field. */
19774 #define SIM_RD_SDID_PINID(base) ((SIM_SDID_REG(base) & SIM_SDID_PINID_MASK) >> SIM_SDID_PINID_SHIFT)
19775 #define SIM_BRD_SDID_PINID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_PINID_SHIFT, SIM_SDID_PINID_WIDTH))
19776 /*@}*/
19777 
19778 /*!
19779  * @name Register SIM_SDID, field DIEID[11:7] (RO)
19780  *
19781  * Specifies the silicon implementation number for the device.
19782  */
19783 /*@{*/
19784 /*! @brief Read current value of the SIM_SDID_DIEID field. */
19785 #define SIM_RD_SDID_DIEID(base) ((SIM_SDID_REG(base) & SIM_SDID_DIEID_MASK) >> SIM_SDID_DIEID_SHIFT)
19786 #define SIM_BRD_SDID_DIEID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_DIEID_SHIFT, SIM_SDID_DIEID_WIDTH))
19787 /*@}*/
19788 
19789 /*!
19790  * @name Register SIM_SDID, field REVID[15:12] (RO)
19791  *
19792  * Specifies the silicon implementation number for the device.
19793  */
19794 /*@{*/
19795 /*! @brief Read current value of the SIM_SDID_REVID field. */
19796 #define SIM_RD_SDID_REVID(base) ((SIM_SDID_REG(base) & SIM_SDID_REVID_MASK) >> SIM_SDID_REVID_SHIFT)
19797 #define SIM_BRD_SDID_REVID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_REVID_SHIFT, SIM_SDID_REVID_WIDTH))
19798 /*@}*/
19799 
19800 /*!
19801  * @name Register SIM_SDID, field SRAMSIZE[19:16] (RO)
19802  *
19803  * Specifies the size of the System SRAM
19804  */
19805 /*@{*/
19806 /*! @brief Read current value of the SIM_SDID_SRAMSIZE field. */
19807 #define SIM_RD_SDID_SRAMSIZE(base) ((SIM_SDID_REG(base) & SIM_SDID_SRAMSIZE_MASK) >> SIM_SDID_SRAMSIZE_SHIFT)
19808 #define SIM_BRD_SDID_SRAMSIZE(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_SRAMSIZE_SHIFT, SIM_SDID_SRAMSIZE_WIDTH))
19809 /*@}*/
19810 
19811 /*!
19812  * @name Register SIM_SDID, field SERIESID[23:20] (RO)
19813  *
19814  * Specifies the Kinetis family of the device.
19815  *
19816  * Values:
19817  * - 0b0101 - KW family
19818  */
19819 /*@{*/
19820 /*! @brief Read current value of the SIM_SDID_SERIESID field. */
19821 #define SIM_RD_SDID_SERIESID(base) ((SIM_SDID_REG(base) & SIM_SDID_SERIESID_MASK) >> SIM_SDID_SERIESID_SHIFT)
19822 #define SIM_BRD_SDID_SERIESID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_SERIESID_SHIFT, SIM_SDID_SERIESID_WIDTH))
19823 /*@}*/
19824 
19825 /*!
19826  * @name Register SIM_SDID, field SUBFAMID[25:24] (RO)
19827  *
19828  * Specifies the Kinetis sub-family of the device.
19829  *
19830  * Values:
19831  * - 0b00 - KWx0 Subfamily
19832  * - 0b01 - KWx1 Subfamily
19833  * - 0b10 - KWx2 Subfamily
19834  * - 0b11 - KWx3 Subfamily
19835  */
19836 /*@{*/
19837 /*! @brief Read current value of the SIM_SDID_SUBFAMID field. */
19838 #define SIM_RD_SDID_SUBFAMID(base) ((SIM_SDID_REG(base) & SIM_SDID_SUBFAMID_MASK) >> SIM_SDID_SUBFAMID_SHIFT)
19839 #define SIM_BRD_SDID_SUBFAMID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_SUBFAMID_SHIFT, SIM_SDID_SUBFAMID_WIDTH))
19840 /*@}*/
19841 
19842 /*!
19843  * @name Register SIM_SDID, field FAMID[31:28] (RO)
19844  *
19845  * Specifies the Kinetis family of the device. The FAMID will be loaded from the
19846  * BLE_EN and ZIGBEE_EN IFR bits.
19847  *
19848  * Values:
19849  * - 0b0010 - KW20 Family (802.15.4/ZigBee)
19850  * - 0b0011 - KW30 Family (BTLE)
19851  * - 0b0100 - KW40 Family (802.15.4/ZigBee or BTLE)
19852  */
19853 /*@{*/
19854 /*! @brief Read current value of the SIM_SDID_FAMID field. */
19855 #define SIM_RD_SDID_FAMID(base) ((SIM_SDID_REG(base) & SIM_SDID_FAMID_MASK) >> SIM_SDID_FAMID_SHIFT)
19856 #define SIM_BRD_SDID_FAMID(base) (BME_UBFX32(&SIM_SDID_REG(base), SIM_SDID_FAMID_SHIFT, SIM_SDID_FAMID_WIDTH))
19857 /*@}*/
19858 
19859 /*******************************************************************************
19860  * SIM_SCGC4 - System Clock Gating Control Register 4
19861  ******************************************************************************/
19862 
19863 /*!
19864  * @brief SIM_SCGC4 - System Clock Gating Control Register 4 (RW)
19865  *
19866  * Reset value: 0xF0000030U
19867  */
19868 /*!
19869  * @name Constants and macros for entire SIM_SCGC4 register
19870  */
19871 /*@{*/
19872 #define SIM_RD_SCGC4(base)       (SIM_SCGC4_REG(base))
19873 #define SIM_WR_SCGC4(base, value) (SIM_SCGC4_REG(base) = (value))
19874 #define SIM_RMW_SCGC4(base, mask, value) (SIM_WR_SCGC4(base, (SIM_RD_SCGC4(base) & ~(mask)) | (value)))
19875 #define SIM_SET_SCGC4(base, value) (BME_OR32(&SIM_SCGC4_REG(base), (uint32_t)(value)))
19876 #define SIM_CLR_SCGC4(base, value) (BME_AND32(&SIM_SCGC4_REG(base), (uint32_t)(~(value))))
19877 #define SIM_TOG_SCGC4(base, value) (BME_XOR32(&SIM_SCGC4_REG(base), (uint32_t)(value)))
19878 /*@}*/
19879 
19880 /* Unified clock gate bit access macros */
19881 #define SIM_SCGC_BIT_REG(base, index)        (*((volatile uint32_t *)&SIM_SCGC4_REG(base) + (((uint32_t)(index) >> 5) - 3U)))
19882 #define SIM_SCGC_BIT_SHIFT(index)            ((uint32_t)(index) & ((1U << 5) - 1U))
19883 #define SIM_RD_SCGC_BIT(base, index)         (SIM_SCGC_BIT_REG((base), (index)) & (1U << SIM_SCGC_BIT_SHIFT(index)))
19884 #define SIM_BRD_SCGC_BIT(base, index)        (BME_UBFX32(&SIM_SCGC_BIT_REG((base), (index)), SIM_SCGC_BIT_SHIFT(index), 1))
19885 #define SIM_WR_SCGC_BIT(base, index, value)  (SIM_SCGC_BIT_REG((base), (index)) = (SIM_SCGC_BIT_REG((base), (index)) & ~(1U << SIM_SCGC_BIT_SHIFT(index))) | ((uint32_t)(value) << SIM_SCGC_BIT_SHIFT(index)))
19886 #define SIM_BWR_SCGC_BIT(base, index, value) (BME_BFI32(&SIM_SCGC_BIT_REG((base), (index)), ((uint32_t)(value) << SIM_SCGC_BIT_SHIFT(index)), SIM_SCGC_BIT_SHIFT(index), 1))
19887 
19888 /*
19889  * Constants & macros for individual SIM_SCGC4 bitfields
19890  */
19891 
19892 /*!
19893  * @name Register SIM_SCGC4, field CMT[2] (RW)
19894  *
19895  * Controls the clock gate to the CMT module.
19896  *
19897  * Values:
19898  * - 0b0 - Clock disabled
19899  * - 0b1 - Clock enabled
19900  */
19901 /*@{*/
19902 /*! @brief Read current value of the SIM_SCGC4_CMT field. */
19903 #define SIM_RD_SCGC4_CMT(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_CMT_MASK) >> SIM_SCGC4_CMT_SHIFT)
19904 #define SIM_BRD_SCGC4_CMT(base) (BME_UBFX32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMT_SHIFT, SIM_SCGC4_CMT_WIDTH))
19905 
19906 /*! @brief Set the CMT field to a new value. */
19907 #define SIM_WR_SCGC4_CMT(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_CMT_MASK, SIM_SCGC4_CMT(value)))
19908 #define SIM_BWR_SCGC4_CMT(base, value) (BME_BFI32(&SIM_SCGC4_REG(base), ((uint32_t)(value) << SIM_SCGC4_CMT_SHIFT), SIM_SCGC4_CMT_SHIFT, SIM_SCGC4_CMT_WIDTH))
19909 /*@}*/
19910 
19911 /*!
19912  * @name Register SIM_SCGC4, field I2C0[6] (RW)
19913  *
19914  * Controls the clock gate to the I2C0 module.
19915  *
19916  * Values:
19917  * - 0b0 - Clock disabled
19918  * - 0b1 - Clock enabled
19919  */
19920 /*@{*/
19921 /*! @brief Read current value of the SIM_SCGC4_I2C0 field. */
19922 #define SIM_RD_SCGC4_I2C0(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_I2C0_MASK) >> SIM_SCGC4_I2C0_SHIFT)
19923 #define SIM_BRD_SCGC4_I2C0(base) (BME_UBFX32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C0_SHIFT, SIM_SCGC4_I2C0_WIDTH))
19924 
19925 /*! @brief Set the I2C0 field to a new value. */
19926 #define SIM_WR_SCGC4_I2C0(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_I2C0_MASK, SIM_SCGC4_I2C0(value)))
19927 #define SIM_BWR_SCGC4_I2C0(base, value) (BME_BFI32(&SIM_SCGC4_REG(base), ((uint32_t)(value) << SIM_SCGC4_I2C0_SHIFT), SIM_SCGC4_I2C0_SHIFT, SIM_SCGC4_I2C0_WIDTH))
19928 /*@}*/
19929 
19930 /*!
19931  * @name Register SIM_SCGC4, field I2C1[7] (RW)
19932  *
19933  * Controls the clock gate to the I2C1 module.
19934  *
19935  * Values:
19936  * - 0b0 - Clock disabled
19937  * - 0b1 - Clock enabled
19938  */
19939 /*@{*/
19940 /*! @brief Read current value of the SIM_SCGC4_I2C1 field. */
19941 #define SIM_RD_SCGC4_I2C1(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_I2C1_MASK) >> SIM_SCGC4_I2C1_SHIFT)
19942 #define SIM_BRD_SCGC4_I2C1(base) (BME_UBFX32(&SIM_SCGC4_REG(base), SIM_SCGC4_I2C1_SHIFT, SIM_SCGC4_I2C1_WIDTH))
19943 
19944 /*! @brief Set the I2C1 field to a new value. */
19945 #define SIM_WR_SCGC4_I2C1(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_I2C1_MASK, SIM_SCGC4_I2C1(value)))
19946 #define SIM_BWR_SCGC4_I2C1(base, value) (BME_BFI32(&SIM_SCGC4_REG(base), ((uint32_t)(value) << SIM_SCGC4_I2C1_SHIFT), SIM_SCGC4_I2C1_SHIFT, SIM_SCGC4_I2C1_WIDTH))
19947 /*@}*/
19948 
19949 /*!
19950  * @name Register SIM_SCGC4, field CMP[19] (RW)
19951  *
19952  * Controls the clock gate to the comparator module.
19953  *
19954  * Values:
19955  * - 0b0 - Clock disabled
19956  * - 0b1 - Clock enabled
19957  */
19958 /*@{*/
19959 /*! @brief Read current value of the SIM_SCGC4_CMP field. */
19960 #define SIM_RD_SCGC4_CMP(base) ((SIM_SCGC4_REG(base) & SIM_SCGC4_CMP_MASK) >> SIM_SCGC4_CMP_SHIFT)
19961 #define SIM_BRD_SCGC4_CMP(base) (BME_UBFX32(&SIM_SCGC4_REG(base), SIM_SCGC4_CMP_SHIFT, SIM_SCGC4_CMP_WIDTH))
19962 
19963 /*! @brief Set the CMP field to a new value. */
19964 #define SIM_WR_SCGC4_CMP(base, value) (SIM_RMW_SCGC4(base, SIM_SCGC4_CMP_MASK, SIM_SCGC4_CMP(value)))
19965 #define SIM_BWR_SCGC4_CMP(base, value) (BME_BFI32(&SIM_SCGC4_REG(base), ((uint32_t)(value) << SIM_SCGC4_CMP_SHIFT), SIM_SCGC4_CMP_SHIFT, SIM_SCGC4_CMP_WIDTH))
19966 /*@}*/
19967 
19968 /*******************************************************************************
19969  * SIM_SCGC5 - System Clock Gating Control Register 5
19970  ******************************************************************************/
19971 
19972 /*!
19973  * @brief SIM_SCGC5 - System Clock Gating Control Register 5 (RW)
19974  *
19975  * Reset value: 0x02000182U
19976  */
19977 /*!
19978  * @name Constants and macros for entire SIM_SCGC5 register
19979  */
19980 /*@{*/
19981 #define SIM_RD_SCGC5(base)       (SIM_SCGC5_REG(base))
19982 #define SIM_WR_SCGC5(base, value) (SIM_SCGC5_REG(base) = (value))
19983 #define SIM_RMW_SCGC5(base, mask, value) (SIM_WR_SCGC5(base, (SIM_RD_SCGC5(base) & ~(mask)) | (value)))
19984 #define SIM_SET_SCGC5(base, value) (BME_OR32(&SIM_SCGC5_REG(base), (uint32_t)(value)))
19985 #define SIM_CLR_SCGC5(base, value) (BME_AND32(&SIM_SCGC5_REG(base), (uint32_t)(~(value))))
19986 #define SIM_TOG_SCGC5(base, value) (BME_XOR32(&SIM_SCGC5_REG(base), (uint32_t)(value)))
19987 /*@}*/
19988 
19989 /*
19990  * Constants & macros for individual SIM_SCGC5 bitfields
19991  */
19992 
19993 /*!
19994  * @name Register SIM_SCGC5, field LPTMR[0] (RW)
19995  *
19996  * Controls software access to the Low Power Timer module.
19997  *
19998  * Values:
19999  * - 0b0 - Access disabled
20000  * - 0b1 - Access enabled
20001  */
20002 /*@{*/
20003 /*! @brief Read current value of the SIM_SCGC5_LPTMR field. */
20004 #define SIM_RD_SCGC5_LPTMR(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_LPTMR_MASK) >> SIM_SCGC5_LPTMR_SHIFT)
20005 #define SIM_BRD_SCGC5_LPTMR(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_LPTMR_SHIFT, SIM_SCGC5_LPTMR_WIDTH))
20006 
20007 /*! @brief Set the LPTMR field to a new value. */
20008 #define SIM_WR_SCGC5_LPTMR(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_LPTMR_MASK, SIM_SCGC5_LPTMR(value)))
20009 #define SIM_BWR_SCGC5_LPTMR(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_SCGC5_LPTMR_SHIFT), SIM_SCGC5_LPTMR_SHIFT, SIM_SCGC5_LPTMR_WIDTH))
20010 /*@}*/
20011 
20012 /*!
20013  * @name Register SIM_SCGC5, field TSI[5] (RW)
20014  *
20015  * Controls software access to the TSI module.
20016  *
20017  * Values:
20018  * - 0b0 - Access disabled
20019  * - 0b1 - Access enabled
20020  */
20021 /*@{*/
20022 /*! @brief Read current value of the SIM_SCGC5_TSI field. */
20023 #define SIM_RD_SCGC5_TSI(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_TSI_MASK) >> SIM_SCGC5_TSI_SHIFT)
20024 #define SIM_BRD_SCGC5_TSI(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_TSI_SHIFT, SIM_SCGC5_TSI_WIDTH))
20025 
20026 /*! @brief Set the TSI field to a new value. */
20027 #define SIM_WR_SCGC5_TSI(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_TSI_MASK, SIM_SCGC5_TSI(value)))
20028 #define SIM_BWR_SCGC5_TSI(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_SCGC5_TSI_SHIFT), SIM_SCGC5_TSI_SHIFT, SIM_SCGC5_TSI_WIDTH))
20029 /*@}*/
20030 
20031 /*!
20032  * @name Register SIM_SCGC5, field PORTA[9] (RW)
20033  *
20034  * Controls the clock gate to the Port A module.
20035  *
20036  * Values:
20037  * - 0b0 - Clock disabled
20038  * - 0b1 - Clock enabled
20039  */
20040 /*@{*/
20041 /*! @brief Read current value of the SIM_SCGC5_PORTA field. */
20042 #define SIM_RD_SCGC5_PORTA(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTA_MASK) >> SIM_SCGC5_PORTA_SHIFT)
20043 #define SIM_BRD_SCGC5_PORTA(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTA_SHIFT, SIM_SCGC5_PORTA_WIDTH))
20044 
20045 /*! @brief Set the PORTA field to a new value. */
20046 #define SIM_WR_SCGC5_PORTA(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTA_MASK, SIM_SCGC5_PORTA(value)))
20047 #define SIM_BWR_SCGC5_PORTA(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_SCGC5_PORTA_SHIFT), SIM_SCGC5_PORTA_SHIFT, SIM_SCGC5_PORTA_WIDTH))
20048 /*@}*/
20049 
20050 /*!
20051  * @name Register SIM_SCGC5, field PORTB[10] (RW)
20052  *
20053  * Controls the clock gate to the Port B module.
20054  *
20055  * Values:
20056  * - 0b0 - Clock disabled
20057  * - 0b1 - Clock enabled
20058  */
20059 /*@{*/
20060 /*! @brief Read current value of the SIM_SCGC5_PORTB field. */
20061 #define SIM_RD_SCGC5_PORTB(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTB_MASK) >> SIM_SCGC5_PORTB_SHIFT)
20062 #define SIM_BRD_SCGC5_PORTB(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTB_SHIFT, SIM_SCGC5_PORTB_WIDTH))
20063 
20064 /*! @brief Set the PORTB field to a new value. */
20065 #define SIM_WR_SCGC5_PORTB(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTB_MASK, SIM_SCGC5_PORTB(value)))
20066 #define SIM_BWR_SCGC5_PORTB(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_SCGC5_PORTB_SHIFT), SIM_SCGC5_PORTB_SHIFT, SIM_SCGC5_PORTB_WIDTH))
20067 /*@}*/
20068 
20069 /*!
20070  * @name Register SIM_SCGC5, field PORTC[11] (RW)
20071  *
20072  * Controls the clock gate to the Port C module.
20073  *
20074  * Values:
20075  * - 0b0 - Clock disabled
20076  * - 0b1 - Clock enabled
20077  */
20078 /*@{*/
20079 /*! @brief Read current value of the SIM_SCGC5_PORTC field. */
20080 #define SIM_RD_SCGC5_PORTC(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PORTC_MASK) >> SIM_SCGC5_PORTC_SHIFT)
20081 #define SIM_BRD_SCGC5_PORTC(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_PORTC_SHIFT, SIM_SCGC5_PORTC_WIDTH))
20082 
20083 /*! @brief Set the PORTC field to a new value. */
20084 #define SIM_WR_SCGC5_PORTC(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PORTC_MASK, SIM_SCGC5_PORTC(value)))
20085 #define SIM_BWR_SCGC5_PORTC(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_SCGC5_PORTC_SHIFT), SIM_SCGC5_PORTC_SHIFT, SIM_SCGC5_PORTC_WIDTH))
20086 /*@}*/
20087 
20088 /*!
20089  * @name Register SIM_SCGC5, field LPUART0[20] (RW)
20090  *
20091  * This bit controls the clock gate to the LPUART0 module.
20092  *
20093  * Values:
20094  * - 0b0 - Clock disabled
20095  * - 0b1 - Clock enabled
20096  */
20097 /*@{*/
20098 /*! @brief Read current value of the SIM_SCGC5_LPUART0 field. */
20099 #define SIM_RD_SCGC5_LPUART0(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_LPUART0_MASK) >> SIM_SCGC5_LPUART0_SHIFT)
20100 #define SIM_BRD_SCGC5_LPUART0(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_LPUART0_SHIFT, SIM_SCGC5_LPUART0_WIDTH))
20101 
20102 /*! @brief Set the LPUART0 field to a new value. */
20103 #define SIM_WR_SCGC5_LPUART0(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_LPUART0_MASK, SIM_SCGC5_LPUART0(value)))
20104 #define SIM_BWR_SCGC5_LPUART0(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_SCGC5_LPUART0_SHIFT), SIM_SCGC5_LPUART0_SHIFT, SIM_SCGC5_LPUART0_WIDTH))
20105 /*@}*/
20106 
20107 /*!
20108  * @name Register SIM_SCGC5, field LTC[24] (RW)
20109  *
20110  * This bit controls the clock gate to the LTC Security module.
20111  *
20112  * Values:
20113  * - 0b0 - Clock disabled
20114  * - 0b1 - Clock enabled
20115  */
20116 /*@{*/
20117 /*! @brief Read current value of the SIM_SCGC5_LTC field. */
20118 #define SIM_RD_SCGC5_LTC(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_LTC_MASK) >> SIM_SCGC5_LTC_SHIFT)
20119 #define SIM_BRD_SCGC5_LTC(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_LTC_SHIFT, SIM_SCGC5_LTC_WIDTH))
20120 
20121 /*! @brief Set the LTC field to a new value. */
20122 #define SIM_WR_SCGC5_LTC(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_LTC_MASK, SIM_SCGC5_LTC(value)))
20123 #define SIM_BWR_SCGC5_LTC(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_SCGC5_LTC_SHIFT), SIM_SCGC5_LTC_SHIFT, SIM_SCGC5_LTC_WIDTH))
20124 /*@}*/
20125 
20126 /*!
20127  * @name Register SIM_SCGC5, field RSIM[25] (RO)
20128  *
20129  * This bit controls the clock gate to the Radio SIM (RSIM) module. Always
20130  * enabled.
20131  */
20132 /*@{*/
20133 /*! @brief Read current value of the SIM_SCGC5_RSIM field. */
20134 #define SIM_RD_SCGC5_RSIM(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_RSIM_MASK) >> SIM_SCGC5_RSIM_SHIFT)
20135 #define SIM_BRD_SCGC5_RSIM(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_RSIM_SHIFT, SIM_SCGC5_RSIM_WIDTH))
20136 /*@}*/
20137 
20138 /*!
20139  * @name Register SIM_SCGC5, field DCDC[26] (RW)
20140  *
20141  * This bit controls the clock gate to the DCDC module.
20142  *
20143  * Values:
20144  * - 0b0 - Clock disabled
20145  * - 0b1 - Clock enabled
20146  */
20147 /*@{*/
20148 /*! @brief Read current value of the SIM_SCGC5_DCDC field. */
20149 #define SIM_RD_SCGC5_DCDC(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_DCDC_MASK) >> SIM_SCGC5_DCDC_SHIFT)
20150 #define SIM_BRD_SCGC5_DCDC(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_DCDC_SHIFT, SIM_SCGC5_DCDC_WIDTH))
20151 
20152 /*! @brief Set the DCDC field to a new value. */
20153 #define SIM_WR_SCGC5_DCDC(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_DCDC_MASK, SIM_SCGC5_DCDC(value)))
20154 #define SIM_BWR_SCGC5_DCDC(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_SCGC5_DCDC_SHIFT), SIM_SCGC5_DCDC_SHIFT, SIM_SCGC5_DCDC_WIDTH))
20155 /*@}*/
20156 
20157 /*!
20158  * @name Register SIM_SCGC5, field BTLL[27] (RW)
20159  *
20160  * This bit controls the clock gate to the BlueTooth Link Layer (BTLL) module.
20161  *
20162  * Values:
20163  * - 0b0 - Clock disabled
20164  * - 0b1 - Clock enabled
20165  */
20166 /*@{*/
20167 /*! @brief Read current value of the SIM_SCGC5_BTLL field. */
20168 #define SIM_RD_SCGC5_BTLL(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_BTLL_MASK) >> SIM_SCGC5_BTLL_SHIFT)
20169 #define SIM_BRD_SCGC5_BTLL(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_BTLL_SHIFT, SIM_SCGC5_BTLL_WIDTH))
20170 
20171 /*! @brief Set the BTLL field to a new value. */
20172 #define SIM_WR_SCGC5_BTLL(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_BTLL_MASK, SIM_SCGC5_BTLL(value)))
20173 #define SIM_BWR_SCGC5_BTLL(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_SCGC5_BTLL_SHIFT), SIM_SCGC5_BTLL_SHIFT, SIM_SCGC5_BTLL_WIDTH))
20174 /*@}*/
20175 
20176 /*!
20177  * @name Register SIM_SCGC5, field PHYDIG[28] (RW)
20178  *
20179  * This bit controls the clock gate to the Physical Layer (PHY) Digital module.
20180  *
20181  * Values:
20182  * - 0b0 - Clock disabled
20183  * - 0b1 - Clock enabled
20184  */
20185 /*@{*/
20186 /*! @brief Read current value of the SIM_SCGC5_PHYDIG field. */
20187 #define SIM_RD_SCGC5_PHYDIG(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_PHYDIG_MASK) >> SIM_SCGC5_PHYDIG_SHIFT)
20188 #define SIM_BRD_SCGC5_PHYDIG(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_PHYDIG_SHIFT, SIM_SCGC5_PHYDIG_WIDTH))
20189 
20190 /*! @brief Set the PHYDIG field to a new value. */
20191 #define SIM_WR_SCGC5_PHYDIG(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_PHYDIG_MASK, SIM_SCGC5_PHYDIG(value)))
20192 #define SIM_BWR_SCGC5_PHYDIG(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_SCGC5_PHYDIG_SHIFT), SIM_SCGC5_PHYDIG_SHIFT, SIM_SCGC5_PHYDIG_WIDTH))
20193 /*@}*/
20194 
20195 /*!
20196  * @name Register SIM_SCGC5, field ZigBee[29] (RW)
20197  *
20198  * This bit controls the clock gate to the ZigBee module.
20199  *
20200  * Values:
20201  * - 0b0 - Clock disabled
20202  * - 0b1 - Clock enabled
20203  */
20204 /*@{*/
20205 /*! @brief Read current value of the SIM_SCGC5_ZigBee field. */
20206 #define SIM_RD_SCGC5_ZigBee(base) ((SIM_SCGC5_REG(base) & SIM_SCGC5_ZigBee_MASK) >> SIM_SCGC5_ZigBee_SHIFT)
20207 #define SIM_BRD_SCGC5_ZigBee(base) (BME_UBFX32(&SIM_SCGC5_REG(base), SIM_SCGC5_ZigBee_SHIFT, SIM_SCGC5_ZigBee_WIDTH))
20208 
20209 /*! @brief Set the ZigBee field to a new value. */
20210 #define SIM_WR_SCGC5_ZigBee(base, value) (SIM_RMW_SCGC5(base, SIM_SCGC5_ZigBee_MASK, SIM_SCGC5_ZigBee(value)))
20211 #define SIM_BWR_SCGC5_ZigBee(base, value) (BME_BFI32(&SIM_SCGC5_REG(base), ((uint32_t)(value) << SIM_SCGC5_ZigBee_SHIFT), SIM_SCGC5_ZigBee_SHIFT, SIM_SCGC5_ZigBee_WIDTH))
20212 /*@}*/
20213 
20214 /*******************************************************************************
20215  * SIM_SCGC6 - System Clock Gating Control Register 6
20216  ******************************************************************************/
20217 
20218 /*!
20219  * @brief SIM_SCGC6 - System Clock Gating Control Register 6 (RW)
20220  *
20221  * Reset value: 0x00000001U
20222  */
20223 /*!
20224  * @name Constants and macros for entire SIM_SCGC6 register
20225  */
20226 /*@{*/
20227 #define SIM_RD_SCGC6(base)       (SIM_SCGC6_REG(base))
20228 #define SIM_WR_SCGC6(base, value) (SIM_SCGC6_REG(base) = (value))
20229 #define SIM_RMW_SCGC6(base, mask, value) (SIM_WR_SCGC6(base, (SIM_RD_SCGC6(base) & ~(mask)) | (value)))
20230 #define SIM_SET_SCGC6(base, value) (BME_OR32(&SIM_SCGC6_REG(base), (uint32_t)(value)))
20231 #define SIM_CLR_SCGC6(base, value) (BME_AND32(&SIM_SCGC6_REG(base), (uint32_t)(~(value))))
20232 #define SIM_TOG_SCGC6(base, value) (BME_XOR32(&SIM_SCGC6_REG(base), (uint32_t)(value)))
20233 /*@}*/
20234 
20235 /*
20236  * Constants & macros for individual SIM_SCGC6 bitfields
20237  */
20238 
20239 /*!
20240  * @name Register SIM_SCGC6, field FTF[0] (RW)
20241  *
20242  * Controls the clock gate to the flash memory. Flash reads are still supported
20243  * while the flash memory is clock gated, but entry into low power modes is
20244  * blocked.
20245  *
20246  * Values:
20247  * - 0b0 - Clock disabled
20248  * - 0b1 - Clock enabled
20249  */
20250 /*@{*/
20251 /*! @brief Read current value of the SIM_SCGC6_FTF field. */
20252 #define SIM_RD_SCGC6_FTF(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_FTF_MASK) >> SIM_SCGC6_FTF_SHIFT)
20253 #define SIM_BRD_SCGC6_FTF(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_FTF_SHIFT, SIM_SCGC6_FTF_WIDTH))
20254 
20255 /*! @brief Set the FTF field to a new value. */
20256 #define SIM_WR_SCGC6_FTF(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_FTF_MASK, SIM_SCGC6_FTF(value)))
20257 #define SIM_BWR_SCGC6_FTF(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_FTF_SHIFT), SIM_SCGC6_FTF_SHIFT, SIM_SCGC6_FTF_WIDTH))
20258 /*@}*/
20259 
20260 /*!
20261  * @name Register SIM_SCGC6, field DMAMUX[1] (RW)
20262  *
20263  * Controls the clock gate to the DMA Mux module.
20264  *
20265  * Values:
20266  * - 0b0 - Clock disabled
20267  * - 0b1 - Clock enabled
20268  */
20269 /*@{*/
20270 /*! @brief Read current value of the SIM_SCGC6_DMAMUX field. */
20271 #define SIM_RD_SCGC6_DMAMUX(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_DMAMUX_MASK) >> SIM_SCGC6_DMAMUX_SHIFT)
20272 #define SIM_BRD_SCGC6_DMAMUX(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_DMAMUX_SHIFT, SIM_SCGC6_DMAMUX_WIDTH))
20273 
20274 /*! @brief Set the DMAMUX field to a new value. */
20275 #define SIM_WR_SCGC6_DMAMUX(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_DMAMUX_MASK, SIM_SCGC6_DMAMUX(value)))
20276 #define SIM_BWR_SCGC6_DMAMUX(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_DMAMUX_SHIFT), SIM_SCGC6_DMAMUX_SHIFT, SIM_SCGC6_DMAMUX_WIDTH))
20277 /*@}*/
20278 
20279 /*!
20280  * @name Register SIM_SCGC6, field TRNG[9] (RW)
20281  *
20282  * Controls the clock gate to the Random Number Generator (TRNG) module.
20283  *
20284  * Values:
20285  * - 0b0 - Clock disabled
20286  * - 0b1 - Clock enabled
20287  */
20288 /*@{*/
20289 /*! @brief Read current value of the SIM_SCGC6_TRNG field. */
20290 #define SIM_RD_SCGC6_TRNG(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_TRNG_MASK) >> SIM_SCGC6_TRNG_SHIFT)
20291 #define SIM_BRD_SCGC6_TRNG(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_TRNG_SHIFT, SIM_SCGC6_TRNG_WIDTH))
20292 
20293 /*! @brief Set the TRNG field to a new value. */
20294 #define SIM_WR_SCGC6_TRNG(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_TRNG_MASK, SIM_SCGC6_TRNG(value)))
20295 #define SIM_BWR_SCGC6_TRNG(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_TRNG_SHIFT), SIM_SCGC6_TRNG_SHIFT, SIM_SCGC6_TRNG_WIDTH))
20296 /*@}*/
20297 
20298 /*!
20299  * @name Register SIM_SCGC6, field SPI0[12] (RW)
20300  *
20301  * Controls the clock gate to the Serial Peripheral Interface (SPI0) module.
20302  *
20303  * Values:
20304  * - 0b0 - Clock disabled
20305  * - 0b1 - Clock enabled
20306  */
20307 /*@{*/
20308 /*! @brief Read current value of the SIM_SCGC6_SPI0 field. */
20309 #define SIM_RD_SCGC6_SPI0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_SPI0_MASK) >> SIM_SCGC6_SPI0_SHIFT)
20310 #define SIM_BRD_SCGC6_SPI0(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI0_SHIFT, SIM_SCGC6_SPI0_WIDTH))
20311 
20312 /*! @brief Set the SPI0 field to a new value. */
20313 #define SIM_WR_SCGC6_SPI0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_SPI0_MASK, SIM_SCGC6_SPI0(value)))
20314 #define SIM_BWR_SCGC6_SPI0(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_SPI0_SHIFT), SIM_SCGC6_SPI0_SHIFT, SIM_SCGC6_SPI0_WIDTH))
20315 /*@}*/
20316 
20317 /*!
20318  * @name Register SIM_SCGC6, field SPI1[13] (RW)
20319  *
20320  * Controls the clock gate to the Serial Peripheral Interface (SPI1) module.
20321  *
20322  * Values:
20323  * - 0b0 - Clock disabled
20324  * - 0b1 - Clock enabled
20325  */
20326 /*@{*/
20327 /*! @brief Read current value of the SIM_SCGC6_SPI1 field. */
20328 #define SIM_RD_SCGC6_SPI1(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_SPI1_MASK) >> SIM_SCGC6_SPI1_SHIFT)
20329 #define SIM_BRD_SCGC6_SPI1(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_SPI1_SHIFT, SIM_SCGC6_SPI1_WIDTH))
20330 
20331 /*! @brief Set the SPI1 field to a new value. */
20332 #define SIM_WR_SCGC6_SPI1(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_SPI1_MASK, SIM_SCGC6_SPI1(value)))
20333 #define SIM_BWR_SCGC6_SPI1(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_SPI1_SHIFT), SIM_SCGC6_SPI1_SHIFT, SIM_SCGC6_SPI1_WIDTH))
20334 /*@}*/
20335 
20336 /*!
20337  * @name Register SIM_SCGC6, field PIT[23] (RW)
20338  *
20339  * This bit controls the clock gate to the PIT module.
20340  *
20341  * Values:
20342  * - 0b0 - Clock disabled
20343  * - 0b1 - Clock enabled
20344  */
20345 /*@{*/
20346 /*! @brief Read current value of the SIM_SCGC6_PIT field. */
20347 #define SIM_RD_SCGC6_PIT(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_PIT_MASK) >> SIM_SCGC6_PIT_SHIFT)
20348 #define SIM_BRD_SCGC6_PIT(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_PIT_SHIFT, SIM_SCGC6_PIT_WIDTH))
20349 
20350 /*! @brief Set the PIT field to a new value. */
20351 #define SIM_WR_SCGC6_PIT(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_PIT_MASK, SIM_SCGC6_PIT(value)))
20352 #define SIM_BWR_SCGC6_PIT(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_PIT_SHIFT), SIM_SCGC6_PIT_SHIFT, SIM_SCGC6_PIT_WIDTH))
20353 /*@}*/
20354 
20355 /*!
20356  * @name Register SIM_SCGC6, field TPM0[24] (RW)
20357  *
20358  * Controls the clock gate to the TPM0 module.
20359  *
20360  * Values:
20361  * - 0b0 - Clock disabled
20362  * - 0b1 - Clock enabled
20363  */
20364 /*@{*/
20365 /*! @brief Read current value of the SIM_SCGC6_TPM0 field. */
20366 #define SIM_RD_SCGC6_TPM0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_TPM0_MASK) >> SIM_SCGC6_TPM0_SHIFT)
20367 #define SIM_BRD_SCGC6_TPM0(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_TPM0_SHIFT, SIM_SCGC6_TPM0_WIDTH))
20368 
20369 /*! @brief Set the TPM0 field to a new value. */
20370 #define SIM_WR_SCGC6_TPM0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_TPM0_MASK, SIM_SCGC6_TPM0(value)))
20371 #define SIM_BWR_SCGC6_TPM0(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_TPM0_SHIFT), SIM_SCGC6_TPM0_SHIFT, SIM_SCGC6_TPM0_WIDTH))
20372 /*@}*/
20373 
20374 /*!
20375  * @name Register SIM_SCGC6, field TPM1[25] (RW)
20376  *
20377  * Controls the clock gate to the TPM1 module.
20378  *
20379  * Values:
20380  * - 0b0 - Clock disabled
20381  * - 0b1 - Clock enabled
20382  */
20383 /*@{*/
20384 /*! @brief Read current value of the SIM_SCGC6_TPM1 field. */
20385 #define SIM_RD_SCGC6_TPM1(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_TPM1_MASK) >> SIM_SCGC6_TPM1_SHIFT)
20386 #define SIM_BRD_SCGC6_TPM1(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_TPM1_SHIFT, SIM_SCGC6_TPM1_WIDTH))
20387 
20388 /*! @brief Set the TPM1 field to a new value. */
20389 #define SIM_WR_SCGC6_TPM1(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_TPM1_MASK, SIM_SCGC6_TPM1(value)))
20390 #define SIM_BWR_SCGC6_TPM1(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_TPM1_SHIFT), SIM_SCGC6_TPM1_SHIFT, SIM_SCGC6_TPM1_WIDTH))
20391 /*@}*/
20392 
20393 /*!
20394  * @name Register SIM_SCGC6, field TPM2[26] (RW)
20395  *
20396  * Controls the clock gate to the TPM2 module.
20397  *
20398  * Values:
20399  * - 0b0 - Clock disabled
20400  * - 0b1 - Clock enabled
20401  */
20402 /*@{*/
20403 /*! @brief Read current value of the SIM_SCGC6_TPM2 field. */
20404 #define SIM_RD_SCGC6_TPM2(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_TPM2_MASK) >> SIM_SCGC6_TPM2_SHIFT)
20405 #define SIM_BRD_SCGC6_TPM2(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_TPM2_SHIFT, SIM_SCGC6_TPM2_WIDTH))
20406 
20407 /*! @brief Set the TPM2 field to a new value. */
20408 #define SIM_WR_SCGC6_TPM2(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_TPM2_MASK, SIM_SCGC6_TPM2(value)))
20409 #define SIM_BWR_SCGC6_TPM2(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_TPM2_SHIFT), SIM_SCGC6_TPM2_SHIFT, SIM_SCGC6_TPM2_WIDTH))
20410 /*@}*/
20411 
20412 /*!
20413  * @name Register SIM_SCGC6, field ADC0[27] (RW)
20414  *
20415  * Controls the clock gate to the ADC0 module.
20416  *
20417  * Values:
20418  * - 0b0 - Clock disabled
20419  * - 0b1 - Clock enabled
20420  */
20421 /*@{*/
20422 /*! @brief Read current value of the SIM_SCGC6_ADC0 field. */
20423 #define SIM_RD_SCGC6_ADC0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_ADC0_MASK) >> SIM_SCGC6_ADC0_SHIFT)
20424 #define SIM_BRD_SCGC6_ADC0(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_ADC0_SHIFT, SIM_SCGC6_ADC0_WIDTH))
20425 
20426 /*! @brief Set the ADC0 field to a new value. */
20427 #define SIM_WR_SCGC6_ADC0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_ADC0_MASK, SIM_SCGC6_ADC0(value)))
20428 #define SIM_BWR_SCGC6_ADC0(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_ADC0_SHIFT), SIM_SCGC6_ADC0_SHIFT, SIM_SCGC6_ADC0_WIDTH))
20429 /*@}*/
20430 
20431 /*!
20432  * @name Register SIM_SCGC6, field RTC[29] (RW)
20433  *
20434  * Controls software access and interrupts to the RTC module.
20435  *
20436  * Values:
20437  * - 0b0 - Access and interrupts disabled
20438  * - 0b1 - Access and interrupts enabled
20439  */
20440 /*@{*/
20441 /*! @brief Read current value of the SIM_SCGC6_RTC field. */
20442 #define SIM_RD_SCGC6_RTC(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_RTC_MASK) >> SIM_SCGC6_RTC_SHIFT)
20443 #define SIM_BRD_SCGC6_RTC(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_RTC_SHIFT, SIM_SCGC6_RTC_WIDTH))
20444 
20445 /*! @brief Set the RTC field to a new value. */
20446 #define SIM_WR_SCGC6_RTC(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_RTC_MASK, SIM_SCGC6_RTC(value)))
20447 #define SIM_BWR_SCGC6_RTC(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_RTC_SHIFT), SIM_SCGC6_RTC_SHIFT, SIM_SCGC6_RTC_WIDTH))
20448 /*@}*/
20449 
20450 /*!
20451  * @name Register SIM_SCGC6, field DAC0[31] (RW)
20452  *
20453  * This bit controls the clock gate to the DAC0 module.
20454  *
20455  * Values:
20456  * - 0b0 - Clock disabled
20457  * - 0b1 - Clock enabled
20458  */
20459 /*@{*/
20460 /*! @brief Read current value of the SIM_SCGC6_DAC0 field. */
20461 #define SIM_RD_SCGC6_DAC0(base) ((SIM_SCGC6_REG(base) & SIM_SCGC6_DAC0_MASK) >> SIM_SCGC6_DAC0_SHIFT)
20462 #define SIM_BRD_SCGC6_DAC0(base) (BME_UBFX32(&SIM_SCGC6_REG(base), SIM_SCGC6_DAC0_SHIFT, SIM_SCGC6_DAC0_WIDTH))
20463 
20464 /*! @brief Set the DAC0 field to a new value. */
20465 #define SIM_WR_SCGC6_DAC0(base, value) (SIM_RMW_SCGC6(base, SIM_SCGC6_DAC0_MASK, SIM_SCGC6_DAC0(value)))
20466 #define SIM_BWR_SCGC6_DAC0(base, value) (BME_BFI32(&SIM_SCGC6_REG(base), ((uint32_t)(value) << SIM_SCGC6_DAC0_SHIFT), SIM_SCGC6_DAC0_SHIFT, SIM_SCGC6_DAC0_WIDTH))
20467 /*@}*/
20468 
20469 /*******************************************************************************
20470  * SIM_SCGC7 - System Clock Gating Control Register 7
20471  ******************************************************************************/
20472 
20473 /*!
20474  * @brief SIM_SCGC7 - System Clock Gating Control Register 7 (RW)
20475  *
20476  * Reset value: 0x00000100U
20477  */
20478 /*!
20479  * @name Constants and macros for entire SIM_SCGC7 register
20480  */
20481 /*@{*/
20482 #define SIM_RD_SCGC7(base)       (SIM_SCGC7_REG(base))
20483 #define SIM_WR_SCGC7(base, value) (SIM_SCGC7_REG(base) = (value))
20484 #define SIM_RMW_SCGC7(base, mask, value) (SIM_WR_SCGC7(base, (SIM_RD_SCGC7(base) & ~(mask)) | (value)))
20485 #define SIM_SET_SCGC7(base, value) (BME_OR32(&SIM_SCGC7_REG(base), (uint32_t)(value)))
20486 #define SIM_CLR_SCGC7(base, value) (BME_AND32(&SIM_SCGC7_REG(base), (uint32_t)(~(value))))
20487 #define SIM_TOG_SCGC7(base, value) (BME_XOR32(&SIM_SCGC7_REG(base), (uint32_t)(value)))
20488 /*@}*/
20489 
20490 /*
20491  * Constants & macros for individual SIM_SCGC7 bitfields
20492  */
20493 
20494 /*!
20495  * @name Register SIM_SCGC7, field DMA[8] (RW)
20496  *
20497  * Controls the clock gate to the DMA module.
20498  *
20499  * Values:
20500  * - 0b0 - Clock disabled
20501  * - 0b1 - Clock enabled
20502  */
20503 /*@{*/
20504 /*! @brief Read current value of the SIM_SCGC7_DMA field. */
20505 #define SIM_RD_SCGC7_DMA(base) ((SIM_SCGC7_REG(base) & SIM_SCGC7_DMA_MASK) >> SIM_SCGC7_DMA_SHIFT)
20506 #define SIM_BRD_SCGC7_DMA(base) (BME_UBFX32(&SIM_SCGC7_REG(base), SIM_SCGC7_DMA_SHIFT, SIM_SCGC7_DMA_WIDTH))
20507 
20508 /*! @brief Set the DMA field to a new value. */
20509 #define SIM_WR_SCGC7_DMA(base, value) (SIM_RMW_SCGC7(base, SIM_SCGC7_DMA_MASK, SIM_SCGC7_DMA(value)))
20510 #define SIM_BWR_SCGC7_DMA(base, value) (BME_BFI32(&SIM_SCGC7_REG(base), ((uint32_t)(value) << SIM_SCGC7_DMA_SHIFT), SIM_SCGC7_DMA_SHIFT, SIM_SCGC7_DMA_WIDTH))
20511 /*@}*/
20512 
20513 /*******************************************************************************
20514  * SIM_CLKDIV1 - System Clock Divider Register 1
20515  ******************************************************************************/
20516 
20517 /*!
20518  * @brief SIM_CLKDIV1 - System Clock Divider Register 1 (RW)
20519  *
20520  * Reset value: 0x00010000U
20521  *
20522  * The CLKDIV1 register cannot be written to when the device is in VLPR mode.
20523  * Reset value loaded during System Reset from FTFA_FOPT[LPBOOT]"/>).
20524  */
20525 /*!
20526  * @name Constants and macros for entire SIM_CLKDIV1 register
20527  */
20528 /*@{*/
20529 #define SIM_RD_CLKDIV1(base)     (SIM_CLKDIV1_REG(base))
20530 #define SIM_WR_CLKDIV1(base, value) (SIM_CLKDIV1_REG(base) = (value))
20531 #define SIM_RMW_CLKDIV1(base, mask, value) (SIM_WR_CLKDIV1(base, (SIM_RD_CLKDIV1(base) & ~(mask)) | (value)))
20532 #define SIM_SET_CLKDIV1(base, value) (BME_OR32(&SIM_CLKDIV1_REG(base), (uint32_t)(value)))
20533 #define SIM_CLR_CLKDIV1(base, value) (BME_AND32(&SIM_CLKDIV1_REG(base), (uint32_t)(~(value))))
20534 #define SIM_TOG_CLKDIV1(base, value) (BME_XOR32(&SIM_CLKDIV1_REG(base), (uint32_t)(value)))
20535 /*@}*/
20536 
20537 /*
20538  * Constants & macros for individual SIM_CLKDIV1 bitfields
20539  */
20540 
20541 /*!
20542  * @name Register SIM_CLKDIV1, field OUTDIV4[18:16] (RW)
20543  *
20544  * Sets the divide value for the bus and flash clock and is in addition to the
20545  * System clock divide ratio. At the end of reset, it is loaded with 0001 (divide
20546  * by 2).
20547  *
20548  * Values:
20549  * - 0b000 - Divide-by-1.
20550  * - 0b001 - Divide-by-2.
20551  * - 0b010 - Divide-by-3.
20552  * - 0b011 - Divide-by-4.
20553  * - 0b100 - Divide-by-5.
20554  * - 0b101 - Divide-by-6.
20555  * - 0b110 - Divide-by-7.
20556  * - 0b111 - Divide-by-8.
20557  */
20558 /*@{*/
20559 /*! @brief Read current value of the SIM_CLKDIV1_OUTDIV4 field. */
20560 #define SIM_RD_CLKDIV1_OUTDIV4(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT)
20561 #define SIM_BRD_CLKDIV1_OUTDIV4(base) (BME_UBFX32(&SIM_CLKDIV1_REG(base), SIM_CLKDIV1_OUTDIV4_SHIFT, SIM_CLKDIV1_OUTDIV4_WIDTH))
20562 
20563 /*! @brief Set the OUTDIV4 field to a new value. */
20564 #define SIM_WR_CLKDIV1_OUTDIV4(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV4_MASK, SIM_CLKDIV1_OUTDIV4(value)))
20565 #define SIM_BWR_CLKDIV1_OUTDIV4(base, value) (BME_BFI32(&SIM_CLKDIV1_REG(base), ((uint32_t)(value) << SIM_CLKDIV1_OUTDIV4_SHIFT), SIM_CLKDIV1_OUTDIV4_SHIFT, SIM_CLKDIV1_OUTDIV4_WIDTH))
20566 /*@}*/
20567 
20568 /*!
20569  * @name Register SIM_CLKDIV1, field OUTDIV1[31:28] (RW)
20570  *
20571  * Sets the divide value for the core/system clock, as well as the bus/flash
20572  * clocks. At the end of reset, it is loaded with 0000 (divide by one), 0001 (divide
20573  * by two), 0011 (divide by four), or 0111 (divide by eight) depending on the
20574  * setting of the FTFA_FOPT[LPBOOT]".
20575  *
20576  * Values:
20577  * - 0b0000 - Divide-by-1.
20578  * - 0b0001 - Divide-by-2.
20579  * - 0b0010 - Divide-by-3.
20580  * - 0b0011 - Divide-by-4.
20581  * - 0b0100 - Divide-by-5.
20582  * - 0b0101 - Divide-by-6.
20583  * - 0b0110 - Divide-by-7.
20584  * - 0b0111 - Divide-by-8.
20585  * - 0b1000 - Divide-by-9.
20586  * - 0b1001 - Divide-by-10.
20587  * - 0b1010 - Divide-by-11.
20588  * - 0b1011 - Divide-by-12.
20589  * - 0b1100 - Divide-by-13.
20590  * - 0b1101 - Divide-by-14.
20591  * - 0b1110 - Divide-by-15.
20592  * - 0b1111 - Divide-by-16.
20593  */
20594 /*@{*/
20595 /*! @brief Read current value of the SIM_CLKDIV1_OUTDIV1 field. */
20596 #define SIM_RD_CLKDIV1_OUTDIV1(base) ((SIM_CLKDIV1_REG(base) & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)
20597 #define SIM_BRD_CLKDIV1_OUTDIV1(base) (BME_UBFX32(&SIM_CLKDIV1_REG(base), SIM_CLKDIV1_OUTDIV1_SHIFT, SIM_CLKDIV1_OUTDIV1_WIDTH))
20598 
20599 /*! @brief Set the OUTDIV1 field to a new value. */
20600 #define SIM_WR_CLKDIV1_OUTDIV1(base, value) (SIM_RMW_CLKDIV1(base, SIM_CLKDIV1_OUTDIV1_MASK, SIM_CLKDIV1_OUTDIV1(value)))
20601 #define SIM_BWR_CLKDIV1_OUTDIV1(base, value) (BME_BFI32(&SIM_CLKDIV1_REG(base), ((uint32_t)(value) << SIM_CLKDIV1_OUTDIV1_SHIFT), SIM_CLKDIV1_OUTDIV1_SHIFT, SIM_CLKDIV1_OUTDIV1_WIDTH))
20602 /*@}*/
20603 
20604 /*******************************************************************************
20605  * SIM_FCFG1 - Flash Configuration Register 1
20606  ******************************************************************************/
20607 
20608 /*!
20609  * @brief SIM_FCFG1 - Flash Configuration Register 1 (RW)
20610  *
20611  * Reset value: 0x00000000U
20612  *
20613  * Reset value of PFSIZE loaded during System Reset from Flash IFR.
20614  */
20615 /*!
20616  * @name Constants and macros for entire SIM_FCFG1 register
20617  */
20618 /*@{*/
20619 #define SIM_RD_FCFG1(base)       (SIM_FCFG1_REG(base))
20620 #define SIM_WR_FCFG1(base, value) (SIM_FCFG1_REG(base) = (value))
20621 #define SIM_RMW_FCFG1(base, mask, value) (SIM_WR_FCFG1(base, (SIM_RD_FCFG1(base) & ~(mask)) | (value)))
20622 #define SIM_SET_FCFG1(base, value) (BME_OR32(&SIM_FCFG1_REG(base), (uint32_t)(value)))
20623 #define SIM_CLR_FCFG1(base, value) (BME_AND32(&SIM_FCFG1_REG(base), (uint32_t)(~(value))))
20624 #define SIM_TOG_FCFG1(base, value) (BME_XOR32(&SIM_FCFG1_REG(base), (uint32_t)(value)))
20625 /*@}*/
20626 
20627 /*
20628  * Constants & macros for individual SIM_FCFG1 bitfields
20629  */
20630 
20631 /*!
20632  * @name Register SIM_FCFG1, field FLASHDIS[0] (RW)
20633  *
20634  * Flash accesses are disabled (and generate a bus error) and the flash memory
20635  * is placed in a low-power state. This field should not be changed during VLP
20636  * modes. Relocate the interrupt vectors out of Flash memory before disabling the
20637  * Flash.
20638  *
20639  * Values:
20640  * - 0b0 - Flash is enabled.
20641  * - 0b1 - Flash is disabled.
20642  */
20643 /*@{*/
20644 /*! @brief Read current value of the SIM_FCFG1_FLASHDIS field. */
20645 #define SIM_RD_FCFG1_FLASHDIS(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_FLASHDIS_MASK) >> SIM_FCFG1_FLASHDIS_SHIFT)
20646 #define SIM_BRD_FCFG1_FLASHDIS(base) (BME_UBFX32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDIS_SHIFT, SIM_FCFG1_FLASHDIS_WIDTH))
20647 
20648 /*! @brief Set the FLASHDIS field to a new value. */
20649 #define SIM_WR_FCFG1_FLASHDIS(base, value) (SIM_RMW_FCFG1(base, SIM_FCFG1_FLASHDIS_MASK, SIM_FCFG1_FLASHDIS(value)))
20650 #define SIM_BWR_FCFG1_FLASHDIS(base, value) (BME_BFI32(&SIM_FCFG1_REG(base), ((uint32_t)(value) << SIM_FCFG1_FLASHDIS_SHIFT), SIM_FCFG1_FLASHDIS_SHIFT, SIM_FCFG1_FLASHDIS_WIDTH))
20651 /*@}*/
20652 
20653 /*!
20654  * @name Register SIM_FCFG1, field FLASHDOZE[1] (RW)
20655  *
20656  * When set, flash memory is disabled for the duration of Doze mode. This field
20657  * must be clear during VLP modes. The flash will be automatically enabled again
20658  * at the end of Doze mode so interrupt vectors do not need to be relocated out
20659  * of flash memory. The wake-up time from Doze mode is extended when this field is
20660  * set. An attempt by the DMA or other bus master to access the flash memory
20661  * when the flash is disabled will result in a bus error.
20662  *
20663  * Values:
20664  * - 0b0 - Flash remains enabled during Doze mode.
20665  * - 0b1 - Flash is disabled for the duration of Doze mode.
20666  */
20667 /*@{*/
20668 /*! @brief Read current value of the SIM_FCFG1_FLASHDOZE field. */
20669 #define SIM_RD_FCFG1_FLASHDOZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_FLASHDOZE_MASK) >> SIM_FCFG1_FLASHDOZE_SHIFT)
20670 #define SIM_BRD_FCFG1_FLASHDOZE(base) (BME_UBFX32(&SIM_FCFG1_REG(base), SIM_FCFG1_FLASHDOZE_SHIFT, SIM_FCFG1_FLASHDOZE_WIDTH))
20671 
20672 /*! @brief Set the FLASHDOZE field to a new value. */
20673 #define SIM_WR_FCFG1_FLASHDOZE(base, value) (SIM_RMW_FCFG1(base, SIM_FCFG1_FLASHDOZE_MASK, SIM_FCFG1_FLASHDOZE(value)))
20674 #define SIM_BWR_FCFG1_FLASHDOZE(base, value) (BME_BFI32(&SIM_FCFG1_REG(base), ((uint32_t)(value) << SIM_FCFG1_FLASHDOZE_SHIFT), SIM_FCFG1_FLASHDOZE_SHIFT, SIM_FCFG1_FLASHDOZE_WIDTH))
20675 /*@}*/
20676 
20677 /*!
20678  * @name Register SIM_FCFG1, field PFSIZE[27:24] (RO)
20679  *
20680  * Specifies the amount of program flash memory available on the device, as set
20681  * by IFR bits. These bits are used for device testing only and are read-only .
20682  */
20683 /*@{*/
20684 /*! @brief Read current value of the SIM_FCFG1_PFSIZE field. */
20685 #define SIM_RD_FCFG1_PFSIZE(base) ((SIM_FCFG1_REG(base) & SIM_FCFG1_PFSIZE_MASK) >> SIM_FCFG1_PFSIZE_SHIFT)
20686 #define SIM_BRD_FCFG1_PFSIZE(base) (BME_UBFX32(&SIM_FCFG1_REG(base), SIM_FCFG1_PFSIZE_SHIFT, SIM_FCFG1_PFSIZE_WIDTH))
20687 /*@}*/
20688 
20689 /*******************************************************************************
20690  * SIM_FCFG2 - Flash Configuration Register 2
20691  ******************************************************************************/
20692 
20693 /*!
20694  * @brief SIM_FCFG2 - Flash Configuration Register 2 (RO)
20695  *
20696  * Reset value: 0x7FFF0000U
20697  *
20698  * This is read only register, any write to this register will cause transfer
20699  * error. Reset value of MAXADDR loaded during System Reset from Flash IFR.
20700  */
20701 /*!
20702  * @name Constants and macros for entire SIM_FCFG2 register
20703  */
20704 /*@{*/
20705 #define SIM_RD_FCFG2(base)       (SIM_FCFG2_REG(base))
20706 /*@}*/
20707 
20708 /*
20709  * Constants & macros for individual SIM_FCFG2 bitfields
20710  */
20711 
20712 /*!
20713  * @name Register SIM_FCFG2, field MAXADDR1[22:16] (RO)
20714  *
20715  * This field concatenated with leading zeros plus the value of the MAXADDR1
20716  * field indicates the first invalid address of the second program flash block
20717  * (flash block 1). For example, if MAXADDR0 = MAXADDR1 = 0x10 the first invalid
20718  * address of flash block 1 is 0x2_0000 + 0x2_0000. This would be the MAXADDR1 value
20719  * for a device with 256 KB program flash memory across two flash blocks. Set by
20720  * IFR option.
20721  */
20722 /*@{*/
20723 /*! @brief Read current value of the SIM_FCFG2_MAXADDR1 field. */
20724 #define SIM_RD_FCFG2_MAXADDR1(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_MAXADDR1_MASK) >> SIM_FCFG2_MAXADDR1_SHIFT)
20725 #define SIM_BRD_FCFG2_MAXADDR1(base) (BME_UBFX32(&SIM_FCFG2_REG(base), SIM_FCFG2_MAXADDR1_SHIFT, SIM_FCFG2_MAXADDR1_WIDTH))
20726 /*@}*/
20727 
20728 /*!
20729  * @name Register SIM_FCFG2, field MAXADDR0[30:24] (RO)
20730  *
20731  * This field concatenated with 13 trailing zeros indicates the first invalid
20732  * address of program flash (block 0). Set by IFR option. For example, if MAXADDR0
20733  * = 0x10, the first invalid address of program flash (block 0) is 0x0002_0000.
20734  * This would be the MAXADDR0 value for a device with 128 KB program flash in
20735  * flash block 0.
20736  */
20737 /*@{*/
20738 /*! @brief Read current value of the SIM_FCFG2_MAXADDR0 field. */
20739 #define SIM_RD_FCFG2_MAXADDR0(base) ((SIM_FCFG2_REG(base) & SIM_FCFG2_MAXADDR0_MASK) >> SIM_FCFG2_MAXADDR0_SHIFT)
20740 #define SIM_BRD_FCFG2_MAXADDR0(base) (BME_UBFX32(&SIM_FCFG2_REG(base), SIM_FCFG2_MAXADDR0_SHIFT, SIM_FCFG2_MAXADDR0_WIDTH))
20741 /*@}*/
20742 
20743 /*******************************************************************************
20744  * SIM_UIDMH - Unique Identification Register Mid-High
20745  ******************************************************************************/
20746 
20747 /*!
20748  * @brief SIM_UIDMH - Unique Identification Register Mid-High (RO)
20749  *
20750  * Reset value: 0x00000000U
20751  *
20752  * Reset value loaded during System Reset from Flash IFR.
20753  */
20754 /*!
20755  * @name Constants and macros for entire SIM_UIDMH register
20756  */
20757 /*@{*/
20758 #define SIM_RD_UIDMH(base)       (SIM_UIDMH_REG(base))
20759 /*@}*/
20760 
20761 /*
20762  * Constants & macros for individual SIM_UIDMH bitfields
20763  */
20764 
20765 /*!
20766  * @name Register SIM_UIDMH, field UID[15:0] (RO)
20767  *
20768  * Unique identification for the device. It is set by IFR bits.
20769  */
20770 /*@{*/
20771 /*! @brief Read current value of the SIM_UIDMH_UID field. */
20772 #define SIM_RD_UIDMH_UID(base) ((SIM_UIDMH_REG(base) & SIM_UIDMH_UID_MASK) >> SIM_UIDMH_UID_SHIFT)
20773 #define SIM_BRD_UIDMH_UID(base) (BME_UBFX32(&SIM_UIDMH_REG(base), SIM_UIDMH_UID_SHIFT, SIM_UIDMH_UID_WIDTH))
20774 /*@}*/
20775 
20776 /*******************************************************************************
20777  * SIM_UIDML - Unique Identification Register Mid Low
20778  ******************************************************************************/
20779 
20780 /*!
20781  * @brief SIM_UIDML - Unique Identification Register Mid Low (RO)
20782  *
20783  * Reset value: 0x00000000U
20784  *
20785  * Reset value loaded during System Reset from Flash IFR.
20786  */
20787 /*!
20788  * @name Constants and macros for entire SIM_UIDML register
20789  */
20790 /*@{*/
20791 #define SIM_RD_UIDML(base)       (SIM_UIDML_REG(base))
20792 /*@}*/
20793 
20794 /*******************************************************************************
20795  * SIM_UIDL - Unique Identification Register Low
20796  ******************************************************************************/
20797 
20798 /*!
20799  * @brief SIM_UIDL - Unique Identification Register Low (RO)
20800  *
20801  * Reset value: 0x00000000U
20802  *
20803  * Reset value loaded during System Reset from Flash IFR.
20804  */
20805 /*!
20806  * @name Constants and macros for entire SIM_UIDL register
20807  */
20808 /*@{*/
20809 #define SIM_RD_UIDL(base)        (SIM_UIDL_REG(base))
20810 /*@}*/
20811 
20812 /*******************************************************************************
20813  * SIM_COPC - COP Control Register
20814  ******************************************************************************/
20815 
20816 /*!
20817  * @brief SIM_COPC - COP Control Register (RW)
20818  *
20819  * Reset value: 0x0000000CU
20820  *
20821  * All of the bits in this register can be written only once after a reset,
20822  * writing this register will also reset the COP counter.
20823  */
20824 /*!
20825  * @name Constants and macros for entire SIM_COPC register
20826  */
20827 /*@{*/
20828 #define SIM_RD_COPC(base)        (SIM_COPC_REG(base))
20829 #define SIM_WR_COPC(base, value) (SIM_COPC_REG(base) = (value))
20830 #define SIM_RMW_COPC(base, mask, value) (SIM_WR_COPC(base, (SIM_RD_COPC(base) & ~(mask)) | (value)))
20831 #define SIM_SET_COPC(base, value) (BME_OR32(&SIM_COPC_REG(base), (uint32_t)(value)))
20832 #define SIM_CLR_COPC(base, value) (BME_AND32(&SIM_COPC_REG(base), (uint32_t)(~(value))))
20833 #define SIM_TOG_COPC(base, value) (BME_XOR32(&SIM_COPC_REG(base), (uint32_t)(value)))
20834 /*@}*/
20835 
20836 /*
20837  * Constants & macros for individual SIM_COPC bitfields
20838  */
20839 
20840 /*!
20841  * @name Register SIM_COPC, field COPW[0] (RW)
20842  *
20843  * Windowed mode is supported for all COP clock sources, but only when the COP
20844  * is configured for a long timeout. The COP window is opened three quarters
20845  * through the timeout period and will generate a system reset if the COP is serviced
20846  * outside of that time.
20847  *
20848  * Values:
20849  * - 0b0 - Normal mode
20850  * - 0b1 - Windowed mode
20851  */
20852 /*@{*/
20853 /*! @brief Read current value of the SIM_COPC_COPW field. */
20854 #define SIM_RD_COPC_COPW(base) ((SIM_COPC_REG(base) & SIM_COPC_COPW_MASK) >> SIM_COPC_COPW_SHIFT)
20855 #define SIM_BRD_COPC_COPW(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPW_SHIFT, SIM_COPC_COPW_WIDTH))
20856 
20857 /*! @brief Set the COPW field to a new value. */
20858 #define SIM_WR_COPC_COPW(base, value) (SIM_RMW_COPC(base, SIM_COPC_COPW_MASK, SIM_COPC_COPW(value)))
20859 #define SIM_BWR_COPC_COPW(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SIM_COPC_COPW_SHIFT), SIM_COPC_COPW_SHIFT, SIM_COPC_COPW_WIDTH))
20860 /*@}*/
20861 
20862 /*!
20863  * @name Register SIM_COPC, field COPCLKS[1] (RW)
20864  *
20865  * This write-once field selects between a short timeout or a long timeout, the
20866  * COP clock source is configured by COPCLKSEL.
20867  *
20868  * Values:
20869  * - 0b0 - COP configured for short timeout
20870  * - 0b1 - COP configured for long timeout
20871  */
20872 /*@{*/
20873 /*! @brief Read current value of the SIM_COPC_COPCLKS field. */
20874 #define SIM_RD_COPC_COPCLKS(base) ((SIM_COPC_REG(base) & SIM_COPC_COPCLKS_MASK) >> SIM_COPC_COPCLKS_SHIFT)
20875 #define SIM_BRD_COPC_COPCLKS(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPCLKS_SHIFT, SIM_COPC_COPCLKS_WIDTH))
20876 
20877 /*! @brief Set the COPCLKS field to a new value. */
20878 #define SIM_WR_COPC_COPCLKS(base, value) (SIM_RMW_COPC(base, SIM_COPC_COPCLKS_MASK, SIM_COPC_COPCLKS(value)))
20879 #define SIM_BWR_COPC_COPCLKS(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SIM_COPC_COPCLKS_SHIFT), SIM_COPC_COPCLKS_SHIFT, SIM_COPC_COPCLKS_WIDTH))
20880 /*@}*/
20881 
20882 /*!
20883  * @name Register SIM_COPC, field COPT[3:2] (RW)
20884  *
20885  * This write-once field selects the timeout period of the COP. COPT along with
20886  * the COPCLKS field define the COP timeout period.
20887  *
20888  * Values:
20889  * - 0b00 - COP disabled
20890  * - 0b01 - COP timeout after 25 cycles for short timeout or 213 cycles for long
20891  *     timeout
20892  * - 0b10 - COP timeout after 28 cycles for short timeout or 216 cycles for long
20893  *     timeout
20894  * - 0b11 - COP timeout after 210 cycles for short timeout or 218 cycles for
20895  *     long timeout
20896  */
20897 /*@{*/
20898 /*! @brief Read current value of the SIM_COPC_COPT field. */
20899 #define SIM_RD_COPC_COPT(base) ((SIM_COPC_REG(base) & SIM_COPC_COPT_MASK) >> SIM_COPC_COPT_SHIFT)
20900 #define SIM_BRD_COPC_COPT(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPT_SHIFT, SIM_COPC_COPT_WIDTH))
20901 
20902 /*! @brief Set the COPT field to a new value. */
20903 #define SIM_WR_COPC_COPT(base, value) (SIM_RMW_COPC(base, SIM_COPC_COPT_MASK, SIM_COPC_COPT(value)))
20904 #define SIM_BWR_COPC_COPT(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SIM_COPC_COPT_SHIFT), SIM_COPC_COPT_SHIFT, SIM_COPC_COPT_WIDTH))
20905 /*@}*/
20906 
20907 /*!
20908  * @name Register SIM_COPC, field COPSTPEN[4] (RW)
20909  *
20910  * Values:
20911  * - 0b0 - COP is disabled and the counter is reset in Stop modes
20912  * - 0b1 - COP is enabled in Stop modes
20913  */
20914 /*@{*/
20915 /*! @brief Read current value of the SIM_COPC_COPSTPEN field. */
20916 #define SIM_RD_COPC_COPSTPEN(base) ((SIM_COPC_REG(base) & SIM_COPC_COPSTPEN_MASK) >> SIM_COPC_COPSTPEN_SHIFT)
20917 #define SIM_BRD_COPC_COPSTPEN(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPSTPEN_SHIFT, SIM_COPC_COPSTPEN_WIDTH))
20918 
20919 /*! @brief Set the COPSTPEN field to a new value. */
20920 #define SIM_WR_COPC_COPSTPEN(base, value) (SIM_RMW_COPC(base, SIM_COPC_COPSTPEN_MASK, SIM_COPC_COPSTPEN(value)))
20921 #define SIM_BWR_COPC_COPSTPEN(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SIM_COPC_COPSTPEN_SHIFT), SIM_COPC_COPSTPEN_SHIFT, SIM_COPC_COPSTPEN_WIDTH))
20922 /*@}*/
20923 
20924 /*!
20925  * @name Register SIM_COPC, field COPDBGEN[5] (RW)
20926  *
20927  * Values:
20928  * - 0b0 - COP is disabled and the counter is reset in Debug mode
20929  * - 0b1 - COP is enabled in Debug mode
20930  */
20931 /*@{*/
20932 /*! @brief Read current value of the SIM_COPC_COPDBGEN field. */
20933 #define SIM_RD_COPC_COPDBGEN(base) ((SIM_COPC_REG(base) & SIM_COPC_COPDBGEN_MASK) >> SIM_COPC_COPDBGEN_SHIFT)
20934 #define SIM_BRD_COPC_COPDBGEN(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPDBGEN_SHIFT, SIM_COPC_COPDBGEN_WIDTH))
20935 
20936 /*! @brief Set the COPDBGEN field to a new value. */
20937 #define SIM_WR_COPC_COPDBGEN(base, value) (SIM_RMW_COPC(base, SIM_COPC_COPDBGEN_MASK, SIM_COPC_COPDBGEN(value)))
20938 #define SIM_BWR_COPC_COPDBGEN(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SIM_COPC_COPDBGEN_SHIFT), SIM_COPC_COPDBGEN_SHIFT, SIM_COPC_COPDBGEN_WIDTH))
20939 /*@}*/
20940 
20941 /*!
20942  * @name Register SIM_COPC, field COPCLKSEL[7:6] (RW)
20943  *
20944  * This write-once field selects the clock source of the COP watchdog.
20945  *
20946  * Values:
20947  * - 0b00 - LPO clock (1 kHz)
20948  * - 0b01 - MCGIRCLK
20949  * - 0b10 - OSCERCLK
20950  * - 0b11 - Bus clock
20951  */
20952 /*@{*/
20953 /*! @brief Read current value of the SIM_COPC_COPCLKSEL field. */
20954 #define SIM_RD_COPC_COPCLKSEL(base) ((SIM_COPC_REG(base) & SIM_COPC_COPCLKSEL_MASK) >> SIM_COPC_COPCLKSEL_SHIFT)
20955 #define SIM_BRD_COPC_COPCLKSEL(base) (BME_UBFX32(&SIM_COPC_REG(base), SIM_COPC_COPCLKSEL_SHIFT, SIM_COPC_COPCLKSEL_WIDTH))
20956 
20957 /*! @brief Set the COPCLKSEL field to a new value. */
20958 #define SIM_WR_COPC_COPCLKSEL(base, value) (SIM_RMW_COPC(base, SIM_COPC_COPCLKSEL_MASK, SIM_COPC_COPCLKSEL(value)))
20959 #define SIM_BWR_COPC_COPCLKSEL(base, value) (BME_BFI32(&SIM_COPC_REG(base), ((uint32_t)(value) << SIM_COPC_COPCLKSEL_SHIFT), SIM_COPC_COPCLKSEL_SHIFT, SIM_COPC_COPCLKSEL_WIDTH))
20960 /*@}*/
20961 
20962 /*******************************************************************************
20963  * SIM_SRVCOP - Service COP
20964  ******************************************************************************/
20965 
20966 /*!
20967  * @brief SIM_SRVCOP - Service COP (WO)
20968  *
20969  * Reset value: 0x00000000U
20970  *
20971  * This is write only register, any read to this register will cause transfer
20972  * error.
20973  */
20974 /*!
20975  * @name Constants and macros for entire SIM_SRVCOP register
20976  */
20977 /*@{*/
20978 #define SIM_WR_SRVCOP(base, value) (SIM_SRVCOP_REG(base) = (value))
20979 /*@}*/
20980 
20981 /*
20982  * Constants & macros for individual SIM_SRVCOP bitfields
20983  */
20984 
20985 /*!
20986  * @name Register SIM_SRVCOP, field SRVCOP[7:0] (WO)
20987  *
20988  * Write 0x55 and then 0xAA (in that order) to reset the COP timeout counter,
20989  * writing any other value will generate a system reset.
20990  */
20991 /*@{*/
20992 /*! @brief Set the SRVCOP field to a new value. */
20993 #define SIM_WR_SRVCOP_SRVCOP(base, value) (SIM_WR_SRVCOP(base, SIM_SRVCOP_SRVCOP(value)))
20994 #define SIM_BWR_SRVCOP_SRVCOP(base, value) (SIM_WR_SRVCOP_SRVCOP(base, value))
20995 /*@}*/
20996 
20997 /*
20998  * MKW40Z4 SMC
20999  *
21000  * System Mode Controller
21001  *
21002  * Registers defined in this header file:
21003  * - SMC_PMPROT - Power Mode Protection register
21004  * - SMC_PMCTRL - Power Mode Control register
21005  * - SMC_STOPCTRL - Stop Control Register
21006  * - SMC_PMSTAT - Power Mode Status register
21007  */
21008 
21009 #define SMC_INSTANCE_COUNT (1U) /*!< Number of instances of the SMC module. */
21010 #define SMC_IDX (0U) /*!< Instance number for SMC. */
21011 
21012 /*******************************************************************************
21013  * SMC_PMPROT - Power Mode Protection register
21014  ******************************************************************************/
21015 
21016 /*!
21017  * @brief SMC_PMPROT - Power Mode Protection register (RW)
21018  *
21019  * Reset value: 0x00U
21020  *
21021  * This register provides protection for entry into any low-power run or stop
21022  * mode. The enabling of the low-power run or stop mode occurs by configuring the
21023  * Power Mode Control register (PMCTRL). The PMPROT register can be written only
21024  * once after any system reset. If the MCU is configured for a disallowed or
21025  * reserved power mode, the MCU remains in its current power mode. For example, if the
21026  * MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using
21027  * PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is
21028  * still in Normal Run mode. This register is reset on Chip Reset not VLLS and by
21029  * reset types that trigger Chip Reset not VLLS. It is unaffected by reset types
21030  * that do not trigger Chip Reset not VLLS. See the Reset section details for more
21031  * information.
21032  */
21033 /*!
21034  * @name Constants and macros for entire SMC_PMPROT register
21035  */
21036 /*@{*/
21037 #define SMC_RD_PMPROT(base)      (SMC_PMPROT_REG(base))
21038 #define SMC_WR_PMPROT(base, value) (SMC_PMPROT_REG(base) = (value))
21039 #define SMC_RMW_PMPROT(base, mask, value) (SMC_WR_PMPROT(base, (SMC_RD_PMPROT(base) & ~(mask)) | (value)))
21040 #define SMC_SET_PMPROT(base, value) (BME_OR8(&SMC_PMPROT_REG(base), (uint8_t)(value)))
21041 #define SMC_CLR_PMPROT(base, value) (BME_AND8(&SMC_PMPROT_REG(base), (uint8_t)(~(value))))
21042 #define SMC_TOG_PMPROT(base, value) (BME_XOR8(&SMC_PMPROT_REG(base), (uint8_t)(value)))
21043 /*@}*/
21044 
21045 /*
21046  * Constants & macros for individual SMC_PMPROT bitfields
21047  */
21048 
21049 /*!
21050  * @name Register SMC_PMPROT, field AVLLS[1] (RW)
21051  *
21052  * Provided the appropriate control bits are set up in PMCTRL, this write once
21053  * bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
21054  *
21055  * Values:
21056  * - 0b0 - Any VLLSx mode is not allowed
21057  * - 0b1 - Any VLLSx mode is allowed
21058  */
21059 /*@{*/
21060 /*! @brief Read current value of the SMC_PMPROT_AVLLS field. */
21061 #define SMC_RD_PMPROT_AVLLS(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_AVLLS_MASK) >> SMC_PMPROT_AVLLS_SHIFT)
21062 #define SMC_BRD_PMPROT_AVLLS(base) (BME_UBFX8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLLS_SHIFT, SMC_PMPROT_AVLLS_WIDTH))
21063 
21064 /*! @brief Set the AVLLS field to a new value. */
21065 #define SMC_WR_PMPROT_AVLLS(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_AVLLS_MASK, SMC_PMPROT_AVLLS(value)))
21066 #define SMC_BWR_PMPROT_AVLLS(base, value) (BME_BFI8(&SMC_PMPROT_REG(base), ((uint8_t)(value) << SMC_PMPROT_AVLLS_SHIFT), SMC_PMPROT_AVLLS_SHIFT, SMC_PMPROT_AVLLS_WIDTH))
21067 /*@}*/
21068 
21069 /*!
21070  * @name Register SMC_PMPROT, field ALLS[3] (RW)
21071  *
21072  * Provided the appropriate control bits are set up in PMCTRL, this write-once
21073  * field allows the MCU to enter any low-leakage stop mode (LLS).
21074  *
21075  * Values:
21076  * - 0b0 - Any LLSx mode is not allowed
21077  * - 0b1 - Any LLSx mode is allowed
21078  */
21079 /*@{*/
21080 /*! @brief Read current value of the SMC_PMPROT_ALLS field. */
21081 #define SMC_RD_PMPROT_ALLS(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_ALLS_MASK) >> SMC_PMPROT_ALLS_SHIFT)
21082 #define SMC_BRD_PMPROT_ALLS(base) (BME_UBFX8(&SMC_PMPROT_REG(base), SMC_PMPROT_ALLS_SHIFT, SMC_PMPROT_ALLS_WIDTH))
21083 
21084 /*! @brief Set the ALLS field to a new value. */
21085 #define SMC_WR_PMPROT_ALLS(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_ALLS_MASK, SMC_PMPROT_ALLS(value)))
21086 #define SMC_BWR_PMPROT_ALLS(base, value) (BME_BFI8(&SMC_PMPROT_REG(base), ((uint8_t)(value) << SMC_PMPROT_ALLS_SHIFT), SMC_PMPROT_ALLS_SHIFT, SMC_PMPROT_ALLS_WIDTH))
21087 /*@}*/
21088 
21089 /*!
21090  * @name Register SMC_PMPROT, field AVLP[5] (RW)
21091  *
21092  * Provided the appropriate control bits are set up in PMCTRL, this write-once
21093  * field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
21094  *
21095  * Values:
21096  * - 0b0 - VLPR, VLPW, and VLPS are not allowed.
21097  * - 0b1 - VLPR, VLPW, and VLPS are allowed.
21098  */
21099 /*@{*/
21100 /*! @brief Read current value of the SMC_PMPROT_AVLP field. */
21101 #define SMC_RD_PMPROT_AVLP(base) ((SMC_PMPROT_REG(base) & SMC_PMPROT_AVLP_MASK) >> SMC_PMPROT_AVLP_SHIFT)
21102 #define SMC_BRD_PMPROT_AVLP(base) (BME_UBFX8(&SMC_PMPROT_REG(base), SMC_PMPROT_AVLP_SHIFT, SMC_PMPROT_AVLP_WIDTH))
21103 
21104 /*! @brief Set the AVLP field to a new value. */
21105 #define SMC_WR_PMPROT_AVLP(base, value) (SMC_RMW_PMPROT(base, SMC_PMPROT_AVLP_MASK, SMC_PMPROT_AVLP(value)))
21106 #define SMC_BWR_PMPROT_AVLP(base, value) (BME_BFI8(&SMC_PMPROT_REG(base), ((uint8_t)(value) << SMC_PMPROT_AVLP_SHIFT), SMC_PMPROT_AVLP_SHIFT, SMC_PMPROT_AVLP_WIDTH))
21107 /*@}*/
21108 
21109 /*******************************************************************************
21110  * SMC_PMCTRL - Power Mode Control register
21111  ******************************************************************************/
21112 
21113 /*!
21114  * @brief SMC_PMCTRL - Power Mode Control register (RW)
21115  *
21116  * Reset value: 0x00U
21117  *
21118  * The PMCTRL register controls entry into low-power Run and Stop modes,
21119  * provided that the selected power mode is allowed via an appropriate setting of the
21120  * protection (PMPROT) register. This register is reset on Chip POR not VLLS and by
21121  * reset types that trigger Chip POR not VLLS. It is unaffected by reset types
21122  * that do not trigger Chip POR not VLLS. See the Reset section details for more
21123  * information.
21124  */
21125 /*!
21126  * @name Constants and macros for entire SMC_PMCTRL register
21127  */
21128 /*@{*/
21129 #define SMC_RD_PMCTRL(base)      (SMC_PMCTRL_REG(base))
21130 #define SMC_WR_PMCTRL(base, value) (SMC_PMCTRL_REG(base) = (value))
21131 #define SMC_RMW_PMCTRL(base, mask, value) (SMC_WR_PMCTRL(base, (SMC_RD_PMCTRL(base) & ~(mask)) | (value)))
21132 #define SMC_SET_PMCTRL(base, value) (BME_OR8(&SMC_PMCTRL_REG(base), (uint8_t)(value)))
21133 #define SMC_CLR_PMCTRL(base, value) (BME_AND8(&SMC_PMCTRL_REG(base), (uint8_t)(~(value))))
21134 #define SMC_TOG_PMCTRL(base, value) (BME_XOR8(&SMC_PMCTRL_REG(base), (uint8_t)(value)))
21135 /*@}*/
21136 
21137 /*
21138  * Constants & macros for individual SMC_PMCTRL bitfields
21139  */
21140 
21141 /*!
21142  * @name Register SMC_PMCTRL, field STOPM[2:0] (RW)
21143  *
21144  * When written, controls entry into the selected stop mode when Sleep-Now or
21145  * Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are
21146  * blocked if the protection level has not been enabled using the PMPROT register.
21147  * After any system reset, this field is cleared by hardware on any successful write
21148  * to the PMPROT register. When set to VLLSxor LLSx, the LLSM in the STOPCTRL
21149  * register is used to further select the particular VLLSor LLS submode which will
21150  * be entered. When set to STOP, the PSTOPO bits in the STOPCTRL register can be
21151  * used to select a Partial Stop mode if desired.
21152  *
21153  * Values:
21154  * - 0b000 - Normal Stop (STOP)
21155  * - 0b001 - Reserved
21156  * - 0b010 - Very-Low-Power Stop (VLPS)
21157  * - 0b011 - Low-Leakage Stop (LLSx)
21158  * - 0b100 - Very-Low-Leakage Stop (VLLSx)
21159  * - 0b101 - Reserved
21160  * - 0b110 - Reseved
21161  * - 0b111 - Reserved
21162  */
21163 /*@{*/
21164 /*! @brief Read current value of the SMC_PMCTRL_STOPM field. */
21165 #define SMC_RD_PMCTRL_STOPM(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_STOPM_MASK) >> SMC_PMCTRL_STOPM_SHIFT)
21166 #define SMC_BRD_PMCTRL_STOPM(base) (BME_UBFX8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_STOPM_SHIFT, SMC_PMCTRL_STOPM_WIDTH))
21167 
21168 /*! @brief Set the STOPM field to a new value. */
21169 #define SMC_WR_PMCTRL_STOPM(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_STOPM_MASK, SMC_PMCTRL_STOPM(value)))
21170 #define SMC_BWR_PMCTRL_STOPM(base, value) (BME_BFI8(&SMC_PMCTRL_REG(base), ((uint8_t)(value) << SMC_PMCTRL_STOPM_SHIFT), SMC_PMCTRL_STOPM_SHIFT, SMC_PMCTRL_STOPM_WIDTH))
21171 /*@}*/
21172 
21173 /*!
21174  * @name Register SMC_PMCTRL, field STOPA[3] (RO)
21175  *
21176  * When set, this read-only status bit indicates an interrupt or reset occured
21177  * during the previous stop mode entry sequence, preventing the system from
21178  * entering that mode. This field is cleared by hardware at the beginning of any stop
21179  * mode entry sequence and is set if the sequence was aborted.
21180  *
21181  * Values:
21182  * - 0b0 - The previous stop mode entry was successsful.
21183  * - 0b1 - The previous stop mode entry was aborted.
21184  */
21185 /*@{*/
21186 /*! @brief Read current value of the SMC_PMCTRL_STOPA field. */
21187 #define SMC_RD_PMCTRL_STOPA(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_STOPA_MASK) >> SMC_PMCTRL_STOPA_SHIFT)
21188 #define SMC_BRD_PMCTRL_STOPA(base) (BME_UBFX8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_STOPA_SHIFT, SMC_PMCTRL_STOPA_WIDTH))
21189 /*@}*/
21190 
21191 /*!
21192  * @name Register SMC_PMCTRL, field RUNM[6:5] (RW)
21193  *
21194  * When written, causes entry into the selected run mode. Writes to this field
21195  * are blocked if the protection level has not been enabled using the PMPROT
21196  * register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to
21197  * VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR.
21198  *
21199  * Values:
21200  * - 0b00 - Normal Run mode (RUN)
21201  * - 0b01 - Reserved
21202  * - 0b10 - Very-Low-Power Run mode (VLPR)
21203  * - 0b11 - Reserved
21204  */
21205 /*@{*/
21206 /*! @brief Read current value of the SMC_PMCTRL_RUNM field. */
21207 #define SMC_RD_PMCTRL_RUNM(base) ((SMC_PMCTRL_REG(base) & SMC_PMCTRL_RUNM_MASK) >> SMC_PMCTRL_RUNM_SHIFT)
21208 #define SMC_BRD_PMCTRL_RUNM(base) (BME_UBFX8(&SMC_PMCTRL_REG(base), SMC_PMCTRL_RUNM_SHIFT, SMC_PMCTRL_RUNM_WIDTH))
21209 
21210 /*! @brief Set the RUNM field to a new value. */
21211 #define SMC_WR_PMCTRL_RUNM(base, value) (SMC_RMW_PMCTRL(base, SMC_PMCTRL_RUNM_MASK, SMC_PMCTRL_RUNM(value)))
21212 #define SMC_BWR_PMCTRL_RUNM(base, value) (BME_BFI8(&SMC_PMCTRL_REG(base), ((uint8_t)(value) << SMC_PMCTRL_RUNM_SHIFT), SMC_PMCTRL_RUNM_SHIFT, SMC_PMCTRL_RUNM_WIDTH))
21213 /*@}*/
21214 
21215 /*******************************************************************************
21216  * SMC_STOPCTRL - Stop Control Register
21217  ******************************************************************************/
21218 
21219 /*!
21220  * @brief SMC_STOPCTRL - Stop Control Register (RW)
21221  *
21222  * Reset value: 0x03U
21223  *
21224  * The STOPCTRL register provides various control bits allowing the user to fine
21225  * tune power consumption during the stop mode selected by the STOPM field. This
21226  * register is reset on Chip POR not VLLS and by reset types that trigger Chip
21227  * POR not VLLS. It is unaffected by reset types that do not trigger Chip POR not
21228  * VLLS. See the Reset section details for more information.
21229  */
21230 /*!
21231  * @name Constants and macros for entire SMC_STOPCTRL register
21232  */
21233 /*@{*/
21234 #define SMC_RD_STOPCTRL(base)    (SMC_STOPCTRL_REG(base))
21235 #define SMC_WR_STOPCTRL(base, value) (SMC_STOPCTRL_REG(base) = (value))
21236 #define SMC_RMW_STOPCTRL(base, mask, value) (SMC_WR_STOPCTRL(base, (SMC_RD_STOPCTRL(base) & ~(mask)) | (value)))
21237 #define SMC_SET_STOPCTRL(base, value) (BME_OR8(&SMC_STOPCTRL_REG(base), (uint8_t)(value)))
21238 #define SMC_CLR_STOPCTRL(base, value) (BME_AND8(&SMC_STOPCTRL_REG(base), (uint8_t)(~(value))))
21239 #define SMC_TOG_STOPCTRL(base, value) (BME_XOR8(&SMC_STOPCTRL_REG(base), (uint8_t)(value)))
21240 /*@}*/
21241 
21242 /*
21243  * Constants & macros for individual SMC_STOPCTRL bitfields
21244  */
21245 
21246 /*!
21247  * @name Register SMC_STOPCTRL, field LLSM[2:0] (RW)
21248  *
21249  * This field controls which LLS orVLLS sub-mode to enter if STOPM = LLSx
21250  * orVLLSx.
21251  *
21252  * Values:
21253  * - 0b000 - VLLS0 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx
21254  * - 0b001 - VLLS1 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx
21255  * - 0b010 - VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
21256  * - 0b011 - VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx
21257  * - 0b100 - Reserved
21258  * - 0b101 - Reserved
21259  * - 0b110 - Reserved
21260  * - 0b111 - Reserved
21261  */
21262 /*@{*/
21263 /*! @brief Read current value of the SMC_STOPCTRL_LLSM field. */
21264 #define SMC_RD_STOPCTRL_LLSM(base) ((SMC_STOPCTRL_REG(base) & SMC_STOPCTRL_LLSM_MASK) >> SMC_STOPCTRL_LLSM_SHIFT)
21265 #define SMC_BRD_STOPCTRL_LLSM(base) (BME_UBFX8(&SMC_STOPCTRL_REG(base), SMC_STOPCTRL_LLSM_SHIFT, SMC_STOPCTRL_LLSM_WIDTH))
21266 
21267 /*! @brief Set the LLSM field to a new value. */
21268 #define SMC_WR_STOPCTRL_LLSM(base, value) (SMC_RMW_STOPCTRL(base, SMC_STOPCTRL_LLSM_MASK, SMC_STOPCTRL_LLSM(value)))
21269 #define SMC_BWR_STOPCTRL_LLSM(base, value) (BME_BFI8(&SMC_STOPCTRL_REG(base), ((uint8_t)(value) << SMC_STOPCTRL_LLSM_SHIFT), SMC_STOPCTRL_LLSM_SHIFT, SMC_STOPCTRL_LLSM_WIDTH))
21270 /*@}*/
21271 
21272 /*!
21273  * @name Register SMC_STOPCTRL, field PORPO[5] (RW)
21274  *
21275  * This bit controls whether the POR detect circuit is enabled in VLLS0 mode.
21276  *
21277  * Values:
21278  * - 0b0 - POR detect circuit is enabled in VLLS0
21279  * - 0b1 - POR detect circuit is disabled in VLLS0
21280  */
21281 /*@{*/
21282 /*! @brief Read current value of the SMC_STOPCTRL_PORPO field. */
21283 #define SMC_RD_STOPCTRL_PORPO(base) ((SMC_STOPCTRL_REG(base) & SMC_STOPCTRL_PORPO_MASK) >> SMC_STOPCTRL_PORPO_SHIFT)
21284 #define SMC_BRD_STOPCTRL_PORPO(base) (BME_UBFX8(&SMC_STOPCTRL_REG(base), SMC_STOPCTRL_PORPO_SHIFT, SMC_STOPCTRL_PORPO_WIDTH))
21285 
21286 /*! @brief Set the PORPO field to a new value. */
21287 #define SMC_WR_STOPCTRL_PORPO(base, value) (SMC_RMW_STOPCTRL(base, SMC_STOPCTRL_PORPO_MASK, SMC_STOPCTRL_PORPO(value)))
21288 #define SMC_BWR_STOPCTRL_PORPO(base, value) (BME_BFI8(&SMC_STOPCTRL_REG(base), ((uint8_t)(value) << SMC_STOPCTRL_PORPO_SHIFT), SMC_STOPCTRL_PORPO_SHIFT, SMC_STOPCTRL_PORPO_WIDTH))
21289 /*@}*/
21290 
21291 /*!
21292  * @name Register SMC_STOPCTRL, field PSTOPO[7:6] (RW)
21293  *
21294  * These bits control whether a Partial Stop mode is entered when STOPM=STOP.
21295  * When entering a Partial Stop mode from RUN (or VLPR) mode, the PMC, MCG and
21296  * flash remain fully powered, allowing the device to wakeup almost instantaneously
21297  * at the expense of higher power consumption. In PSTOP2, only system clocks are
21298  * gated allowing peripherals running on bus clock to remain fully functional. In
21299  * PSTOP1, both system and bus clocks are gated.
21300  *
21301  * Values:
21302  * - 0b00 - STOP - Normal Stop mode
21303  * - 0b01 - PSTOP1 - Partial Stop with both system and bus clocks disabled
21304  * - 0b10 - PSTOP2 - Partial Stop with system clock disabled and bus clock
21305  *     enabled
21306  * - 0b11 - Reserved
21307  */
21308 /*@{*/
21309 /*! @brief Read current value of the SMC_STOPCTRL_PSTOPO field. */
21310 #define SMC_RD_STOPCTRL_PSTOPO(base) ((SMC_STOPCTRL_REG(base) & SMC_STOPCTRL_PSTOPO_MASK) >> SMC_STOPCTRL_PSTOPO_SHIFT)
21311 #define SMC_BRD_STOPCTRL_PSTOPO(base) (BME_UBFX8(&SMC_STOPCTRL_REG(base), SMC_STOPCTRL_PSTOPO_SHIFT, SMC_STOPCTRL_PSTOPO_WIDTH))
21312 
21313 /*! @brief Set the PSTOPO field to a new value. */
21314 #define SMC_WR_STOPCTRL_PSTOPO(base, value) (SMC_RMW_STOPCTRL(base, SMC_STOPCTRL_PSTOPO_MASK, SMC_STOPCTRL_PSTOPO(value)))
21315 #define SMC_BWR_STOPCTRL_PSTOPO(base, value) (BME_BFI8(&SMC_STOPCTRL_REG(base), ((uint8_t)(value) << SMC_STOPCTRL_PSTOPO_SHIFT), SMC_STOPCTRL_PSTOPO_SHIFT, SMC_STOPCTRL_PSTOPO_WIDTH))
21316 /*@}*/
21317 
21318 /*******************************************************************************
21319  * SMC_PMSTAT - Power Mode Status register
21320  ******************************************************************************/
21321 
21322 /*!
21323  * @brief SMC_PMSTAT - Power Mode Status register (RO)
21324  *
21325  * Reset value: 0x01U
21326  *
21327  * PMSTAT is a read-only, one-hot register which indicates the current power
21328  * mode of the system. This register is reset on Chip POR not VLLS and by reset
21329  * types that trigger Chip POR not VLLS. It is unaffected by reset types that do not
21330  * trigger Chip POR not VLLS. See the Reset section details for more information.
21331  */
21332 /*!
21333  * @name Constants and macros for entire SMC_PMSTAT register
21334  */
21335 /*@{*/
21336 #define SMC_RD_PMSTAT(base)      (SMC_PMSTAT_REG(base))
21337 /*@}*/
21338 
21339 /*
21340  * MKW40Z4 SPI
21341  *
21342  * Serial Peripheral Interface
21343  *
21344  * Registers defined in this header file:
21345  * - SPI_MCR - Module Configuration Register
21346  * - SPI_TCR - Transfer Count Register
21347  * - SPI_CTAR - Clock and Transfer Attributes Register (In Master Mode)
21348  * - SPI_CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
21349  * - SPI_SR - Status Register
21350  * - SPI_RSER - DMA/Interrupt Request Select and Enable Register
21351  * - SPI_PUSHR - PUSH TX FIFO Register In Master Mode
21352  * - SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
21353  * - SPI_POPR - POP RX FIFO Register
21354  * - SPI_TXFR0 - Transmit FIFO Registers
21355  * - SPI_TXFR1 - Transmit FIFO Registers
21356  * - SPI_TXFR2 - Transmit FIFO Registers
21357  * - SPI_TXFR3 - Transmit FIFO Registers
21358  * - SPI_RXFR0 - Receive FIFO Registers
21359  * - SPI_RXFR1 - Receive FIFO Registers
21360  * - SPI_RXFR2 - Receive FIFO Registers
21361  * - SPI_RXFR3 - Receive FIFO Registers
21362  */
21363 
21364 #define SPI_INSTANCE_COUNT (2U) /*!< Number of instances of the SPI module. */
21365 #define SPI0_IDX (0U) /*!< Instance number for SPI0. */
21366 #define SPI1_IDX (1U) /*!< Instance number for SPI1. */
21367 
21368 /*******************************************************************************
21369  * SPI_MCR - Module Configuration Register
21370  ******************************************************************************/
21371 
21372 /*!
21373  * @brief SPI_MCR - Module Configuration Register (RW)
21374  *
21375  * Reset value: 0x00004001U
21376  *
21377  * Contains bits to configure various attributes associated with the module
21378  * operations. The HALT and MDIS bits can be changed at any time, but the effect
21379  * takes place only on the next frame boundary. Only the HALT and MDIS bits in the
21380  * MCR can be changed, while the module is in the Running state.
21381  */
21382 /*!
21383  * @name Constants and macros for entire SPI_MCR register
21384  */
21385 /*@{*/
21386 #define SPI_RD_MCR(base)         (SPI_MCR_REG(base))
21387 #define SPI_WR_MCR(base, value)  (SPI_MCR_REG(base) = (value))
21388 #define SPI_RMW_MCR(base, mask, value) (SPI_WR_MCR(base, (SPI_RD_MCR(base) & ~(mask)) | (value)))
21389 #define SPI_SET_MCR(base, value) (BME_OR32(&SPI_MCR_REG(base), (uint32_t)(value)))
21390 #define SPI_CLR_MCR(base, value) (BME_AND32(&SPI_MCR_REG(base), (uint32_t)(~(value))))
21391 #define SPI_TOG_MCR(base, value) (BME_XOR32(&SPI_MCR_REG(base), (uint32_t)(value)))
21392 /*@}*/
21393 
21394 /*
21395  * Constants & macros for individual SPI_MCR bitfields
21396  */
21397 
21398 /*!
21399  * @name Register SPI_MCR, field HALT[0] (RW)
21400  *
21401  * The HALT bit starts and stops frame transfers. See Start and Stop of Module
21402  * transfers
21403  *
21404  * Values:
21405  * - 0b0 - Start transfers.
21406  * - 0b1 - Stop transfers.
21407  */
21408 /*@{*/
21409 /*! @brief Read current value of the SPI_MCR_HALT field. */
21410 #define SPI_RD_MCR_HALT(base) ((SPI_MCR_REG(base) & SPI_MCR_HALT_MASK) >> SPI_MCR_HALT_SHIFT)
21411 #define SPI_BRD_MCR_HALT(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_HALT_SHIFT, SPI_MCR_HALT_WIDTH))
21412 
21413 /*! @brief Set the HALT field to a new value. */
21414 #define SPI_WR_MCR_HALT(base, value) (SPI_RMW_MCR(base, SPI_MCR_HALT_MASK, SPI_MCR_HALT(value)))
21415 #define SPI_BWR_MCR_HALT(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_HALT_SHIFT), SPI_MCR_HALT_SHIFT, SPI_MCR_HALT_WIDTH))
21416 /*@}*/
21417 
21418 /*!
21419  * @name Register SPI_MCR, field SMPL_PT[9:8] (RW)
21420  *
21421  * Controls when the module master samples SIN in Modified Transfer Format. This
21422  * field is valid only when CPHA bit in CTARn[CPHA] is 0.
21423  *
21424  * Values:
21425  * - 0b00 - 0 protocol clock cycles between SCK edge and SIN sample
21426  * - 0b01 - 1 protocol clock cycle between SCK edge and SIN sample
21427  * - 0b10 - 2 protocol clock cycles between SCK edge and SIN sample
21428  * - 0b11 - Reserved
21429  */
21430 /*@{*/
21431 /*! @brief Read current value of the SPI_MCR_SMPL_PT field. */
21432 #define SPI_RD_MCR_SMPL_PT(base) ((SPI_MCR_REG(base) & SPI_MCR_SMPL_PT_MASK) >> SPI_MCR_SMPL_PT_SHIFT)
21433 #define SPI_BRD_MCR_SMPL_PT(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_SMPL_PT_SHIFT, SPI_MCR_SMPL_PT_WIDTH))
21434 
21435 /*! @brief Set the SMPL_PT field to a new value. */
21436 #define SPI_WR_MCR_SMPL_PT(base, value) (SPI_RMW_MCR(base, SPI_MCR_SMPL_PT_MASK, SPI_MCR_SMPL_PT(value)))
21437 #define SPI_BWR_MCR_SMPL_PT(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_SMPL_PT_SHIFT), SPI_MCR_SMPL_PT_SHIFT, SPI_MCR_SMPL_PT_WIDTH))
21438 /*@}*/
21439 
21440 /*!
21441  * @name Register SPI_MCR, field CLR_RXF[10] (WORZ)
21442  *
21443  * Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The
21444  * CLR_RXF bit is always read as zero.
21445  *
21446  * Values:
21447  * - 0b0 - Do not clear the RX FIFO counter.
21448  * - 0b1 - Clear the RX FIFO counter.
21449  */
21450 /*@{*/
21451 /*! @brief Set the CLR_RXF field to a new value. */
21452 #define SPI_WR_MCR_CLR_RXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_CLR_RXF_MASK, SPI_MCR_CLR_RXF(value)))
21453 #define SPI_BWR_MCR_CLR_RXF(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_CLR_RXF_SHIFT), SPI_MCR_CLR_RXF_SHIFT, SPI_MCR_CLR_RXF_WIDTH))
21454 /*@}*/
21455 
21456 /*!
21457  * @name Register SPI_MCR, field CLR_TXF[11] (WORZ)
21458  *
21459  * Flushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The
21460  * CLR_TXF bit is always read as zero.
21461  *
21462  * Values:
21463  * - 0b0 - Do not clear the TX FIFO counter.
21464  * - 0b1 - Clear the TX FIFO counter.
21465  */
21466 /*@{*/
21467 /*! @brief Set the CLR_TXF field to a new value. */
21468 #define SPI_WR_MCR_CLR_TXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_CLR_TXF_MASK, SPI_MCR_CLR_TXF(value)))
21469 #define SPI_BWR_MCR_CLR_TXF(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_CLR_TXF_SHIFT), SPI_MCR_CLR_TXF_SHIFT, SPI_MCR_CLR_TXF_WIDTH))
21470 /*@}*/
21471 
21472 /*!
21473  * @name Register SPI_MCR, field DIS_RXF[12] (RW)
21474  *
21475  * When the RX FIFO is disabled, the receive part of the module operates as a
21476  * simplified double-buffered SPI. This bit can only be written when the MDIS bit
21477  * is cleared.
21478  *
21479  * Values:
21480  * - 0b0 - RX FIFO is enabled.
21481  * - 0b1 - RX FIFO is disabled.
21482  */
21483 /*@{*/
21484 /*! @brief Read current value of the SPI_MCR_DIS_RXF field. */
21485 #define SPI_RD_MCR_DIS_RXF(base) ((SPI_MCR_REG(base) & SPI_MCR_DIS_RXF_MASK) >> SPI_MCR_DIS_RXF_SHIFT)
21486 #define SPI_BRD_MCR_DIS_RXF(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_DIS_RXF_SHIFT, SPI_MCR_DIS_RXF_WIDTH))
21487 
21488 /*! @brief Set the DIS_RXF field to a new value. */
21489 #define SPI_WR_MCR_DIS_RXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_DIS_RXF_MASK, SPI_MCR_DIS_RXF(value)))
21490 #define SPI_BWR_MCR_DIS_RXF(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_DIS_RXF_SHIFT), SPI_MCR_DIS_RXF_SHIFT, SPI_MCR_DIS_RXF_WIDTH))
21491 /*@}*/
21492 
21493 /*!
21494  * @name Register SPI_MCR, field DIS_TXF[13] (RW)
21495  *
21496  * When the TX FIFO is disabled, the transmit part of the module operates as a
21497  * simplified double-buffered SPI. This bit can be written only when the MDIS bit
21498  * is cleared.
21499  *
21500  * Values:
21501  * - 0b0 - TX FIFO is enabled.
21502  * - 0b1 - TX FIFO is disabled.
21503  */
21504 /*@{*/
21505 /*! @brief Read current value of the SPI_MCR_DIS_TXF field. */
21506 #define SPI_RD_MCR_DIS_TXF(base) ((SPI_MCR_REG(base) & SPI_MCR_DIS_TXF_MASK) >> SPI_MCR_DIS_TXF_SHIFT)
21507 #define SPI_BRD_MCR_DIS_TXF(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_DIS_TXF_SHIFT, SPI_MCR_DIS_TXF_WIDTH))
21508 
21509 /*! @brief Set the DIS_TXF field to a new value. */
21510 #define SPI_WR_MCR_DIS_TXF(base, value) (SPI_RMW_MCR(base, SPI_MCR_DIS_TXF_MASK, SPI_MCR_DIS_TXF(value)))
21511 #define SPI_BWR_MCR_DIS_TXF(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_DIS_TXF_SHIFT), SPI_MCR_DIS_TXF_SHIFT, SPI_MCR_DIS_TXF_WIDTH))
21512 /*@}*/
21513 
21514 /*!
21515  * @name Register SPI_MCR, field MDIS[14] (RW)
21516  *
21517  * Allows the clock to be stopped to the non-memory mapped logic in the module
21518  * effectively putting it in a software-controlled power-saving state. The reset
21519  * value of the MDIS bit is parameterized, with a default reset value of 0. When
21520  * the module is used in Slave Mode, it is recommended to leave this bit 0,
21521  * because a slave doesn't have control over master transactions.
21522  *
21523  * Values:
21524  * - 0b0 - Enables the module clocks.
21525  * - 0b1 - Allows external logic to disable the module clocks.
21526  */
21527 /*@{*/
21528 /*! @brief Read current value of the SPI_MCR_MDIS field. */
21529 #define SPI_RD_MCR_MDIS(base) ((SPI_MCR_REG(base) & SPI_MCR_MDIS_MASK) >> SPI_MCR_MDIS_SHIFT)
21530 #define SPI_BRD_MCR_MDIS(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_MDIS_SHIFT, SPI_MCR_MDIS_WIDTH))
21531 
21532 /*! @brief Set the MDIS field to a new value. */
21533 #define SPI_WR_MCR_MDIS(base, value) (SPI_RMW_MCR(base, SPI_MCR_MDIS_MASK, SPI_MCR_MDIS(value)))
21534 #define SPI_BWR_MCR_MDIS(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_MDIS_SHIFT), SPI_MCR_MDIS_SHIFT, SPI_MCR_MDIS_WIDTH))
21535 /*@}*/
21536 
21537 /*!
21538  * @name Register SPI_MCR, field DOZE[15] (RW)
21539  *
21540  * Provides support for an externally controlled Doze mode power-saving
21541  * mechanism.
21542  *
21543  * Values:
21544  * - 0b0 - Doze mode has no effect on the module.
21545  * - 0b1 - Doze mode disables the module.
21546  */
21547 /*@{*/
21548 /*! @brief Read current value of the SPI_MCR_DOZE field. */
21549 #define SPI_RD_MCR_DOZE(base) ((SPI_MCR_REG(base) & SPI_MCR_DOZE_MASK) >> SPI_MCR_DOZE_SHIFT)
21550 #define SPI_BRD_MCR_DOZE(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_DOZE_SHIFT, SPI_MCR_DOZE_WIDTH))
21551 
21552 /*! @brief Set the DOZE field to a new value. */
21553 #define SPI_WR_MCR_DOZE(base, value) (SPI_RMW_MCR(base, SPI_MCR_DOZE_MASK, SPI_MCR_DOZE(value)))
21554 #define SPI_BWR_MCR_DOZE(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_DOZE_SHIFT), SPI_MCR_DOZE_SHIFT, SPI_MCR_DOZE_WIDTH))
21555 /*@}*/
21556 
21557 /*!
21558  * @name Register SPI_MCR, field PCSIS[19:16] (RW)
21559  *
21560  * Determines the inactive state of PCSx. Refer to the chip-specific SPI
21561  * information for the number of PCS signals used in this MCU.
21562  *
21563  * Values:
21564  * - 0b0000 - The inactive state of PCSx is low.
21565  * - 0b0001 - The inactive state of PCSx is high.
21566  */
21567 /*@{*/
21568 /*! @brief Read current value of the SPI_MCR_PCSIS field. */
21569 #define SPI_RD_MCR_PCSIS(base) ((SPI_MCR_REG(base) & SPI_MCR_PCSIS_MASK) >> SPI_MCR_PCSIS_SHIFT)
21570 #define SPI_BRD_MCR_PCSIS(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_PCSIS_SHIFT, SPI_MCR_PCSIS_WIDTH))
21571 
21572 /*! @brief Set the PCSIS field to a new value. */
21573 #define SPI_WR_MCR_PCSIS(base, value) (SPI_RMW_MCR(base, SPI_MCR_PCSIS_MASK, SPI_MCR_PCSIS(value)))
21574 #define SPI_BWR_MCR_PCSIS(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_PCSIS_SHIFT), SPI_MCR_PCSIS_SHIFT, SPI_MCR_PCSIS_WIDTH))
21575 /*@}*/
21576 
21577 /*!
21578  * @name Register SPI_MCR, field ROOE[24] (RW)
21579  *
21580  * In the RX FIFO overflow condition, configures the module to ignore the
21581  * incoming serial data or overwrite existing data. If the RX FIFO is full and new data
21582  * is received, the data from the transfer, generating the overflow, is ignored
21583  * or shifted into the shift register.
21584  *
21585  * Values:
21586  * - 0b0 - Incoming data is ignored.
21587  * - 0b1 - Incoming data is shifted into the shift register.
21588  */
21589 /*@{*/
21590 /*! @brief Read current value of the SPI_MCR_ROOE field. */
21591 #define SPI_RD_MCR_ROOE(base) ((SPI_MCR_REG(base) & SPI_MCR_ROOE_MASK) >> SPI_MCR_ROOE_SHIFT)
21592 #define SPI_BRD_MCR_ROOE(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_ROOE_SHIFT, SPI_MCR_ROOE_WIDTH))
21593 
21594 /*! @brief Set the ROOE field to a new value. */
21595 #define SPI_WR_MCR_ROOE(base, value) (SPI_RMW_MCR(base, SPI_MCR_ROOE_MASK, SPI_MCR_ROOE(value)))
21596 #define SPI_BWR_MCR_ROOE(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_ROOE_SHIFT), SPI_MCR_ROOE_SHIFT, SPI_MCR_ROOE_WIDTH))
21597 /*@}*/
21598 
21599 /*!
21600  * @name Register SPI_MCR, field MTFE[26] (RW)
21601  *
21602  * Enables a modified transfer format to be used.
21603  *
21604  * Values:
21605  * - 0b0 - Modified SPI transfer format disabled.
21606  * - 0b1 - Modified SPI transfer format enabled.
21607  */
21608 /*@{*/
21609 /*! @brief Read current value of the SPI_MCR_MTFE field. */
21610 #define SPI_RD_MCR_MTFE(base) ((SPI_MCR_REG(base) & SPI_MCR_MTFE_MASK) >> SPI_MCR_MTFE_SHIFT)
21611 #define SPI_BRD_MCR_MTFE(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_MTFE_SHIFT, SPI_MCR_MTFE_WIDTH))
21612 
21613 /*! @brief Set the MTFE field to a new value. */
21614 #define SPI_WR_MCR_MTFE(base, value) (SPI_RMW_MCR(base, SPI_MCR_MTFE_MASK, SPI_MCR_MTFE(value)))
21615 #define SPI_BWR_MCR_MTFE(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_MTFE_SHIFT), SPI_MCR_MTFE_SHIFT, SPI_MCR_MTFE_WIDTH))
21616 /*@}*/
21617 
21618 /*!
21619  * @name Register SPI_MCR, field FRZ[27] (RW)
21620  *
21621  * Enables transfers to be stopped on the next frame boundary when the device
21622  * enters Debug mode.
21623  *
21624  * Values:
21625  * - 0b0 - Do not halt serial transfers in Debug mode.
21626  * - 0b1 - Halt serial transfers in Debug mode.
21627  */
21628 /*@{*/
21629 /*! @brief Read current value of the SPI_MCR_FRZ field. */
21630 #define SPI_RD_MCR_FRZ(base) ((SPI_MCR_REG(base) & SPI_MCR_FRZ_MASK) >> SPI_MCR_FRZ_SHIFT)
21631 #define SPI_BRD_MCR_FRZ(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_FRZ_SHIFT, SPI_MCR_FRZ_WIDTH))
21632 
21633 /*! @brief Set the FRZ field to a new value. */
21634 #define SPI_WR_MCR_FRZ(base, value) (SPI_RMW_MCR(base, SPI_MCR_FRZ_MASK, SPI_MCR_FRZ(value)))
21635 #define SPI_BWR_MCR_FRZ(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_FRZ_SHIFT), SPI_MCR_FRZ_SHIFT, SPI_MCR_FRZ_WIDTH))
21636 /*@}*/
21637 
21638 /*!
21639  * @name Register SPI_MCR, field DCONF[29:28] (RO)
21640  *
21641  * Selects among the different configurations of the module.
21642  *
21643  * Values:
21644  * - 0b00 - SPI
21645  * - 0b01 - Reserved
21646  * - 0b10 - Reserved
21647  * - 0b11 - Reserved
21648  */
21649 /*@{*/
21650 /*! @brief Read current value of the SPI_MCR_DCONF field. */
21651 #define SPI_RD_MCR_DCONF(base) ((SPI_MCR_REG(base) & SPI_MCR_DCONF_MASK) >> SPI_MCR_DCONF_SHIFT)
21652 #define SPI_BRD_MCR_DCONF(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_DCONF_SHIFT, SPI_MCR_DCONF_WIDTH))
21653 /*@}*/
21654 
21655 /*!
21656  * @name Register SPI_MCR, field CONT_SCKE[30] (RW)
21657  *
21658  * Enables the Serial Communication Clock (SCK) to run continuously.
21659  *
21660  * Values:
21661  * - 0b0 - Continuous SCK disabled.
21662  * - 0b1 - Continuous SCK enabled.
21663  */
21664 /*@{*/
21665 /*! @brief Read current value of the SPI_MCR_CONT_SCKE field. */
21666 #define SPI_RD_MCR_CONT_SCKE(base) ((SPI_MCR_REG(base) & SPI_MCR_CONT_SCKE_MASK) >> SPI_MCR_CONT_SCKE_SHIFT)
21667 #define SPI_BRD_MCR_CONT_SCKE(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_CONT_SCKE_SHIFT, SPI_MCR_CONT_SCKE_WIDTH))
21668 
21669 /*! @brief Set the CONT_SCKE field to a new value. */
21670 #define SPI_WR_MCR_CONT_SCKE(base, value) (SPI_RMW_MCR(base, SPI_MCR_CONT_SCKE_MASK, SPI_MCR_CONT_SCKE(value)))
21671 #define SPI_BWR_MCR_CONT_SCKE(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_CONT_SCKE_SHIFT), SPI_MCR_CONT_SCKE_SHIFT, SPI_MCR_CONT_SCKE_WIDTH))
21672 /*@}*/
21673 
21674 /*!
21675  * @name Register SPI_MCR, field MSTR[31] (RW)
21676  *
21677  * Enables either Master mode (if supported) or Slave mode (if supported)
21678  * operation.
21679  *
21680  * Values:
21681  * - 0b0 - Enables Slave mode
21682  * - 0b1 - Enables Master mode
21683  */
21684 /*@{*/
21685 /*! @brief Read current value of the SPI_MCR_MSTR field. */
21686 #define SPI_RD_MCR_MSTR(base) ((SPI_MCR_REG(base) & SPI_MCR_MSTR_MASK) >> SPI_MCR_MSTR_SHIFT)
21687 #define SPI_BRD_MCR_MSTR(base) (BME_UBFX32(&SPI_MCR_REG(base), SPI_MCR_MSTR_SHIFT, SPI_MCR_MSTR_WIDTH))
21688 
21689 /*! @brief Set the MSTR field to a new value. */
21690 #define SPI_WR_MCR_MSTR(base, value) (SPI_RMW_MCR(base, SPI_MCR_MSTR_MASK, SPI_MCR_MSTR(value)))
21691 #define SPI_BWR_MCR_MSTR(base, value) (BME_BFI32(&SPI_MCR_REG(base), ((uint32_t)(value) << SPI_MCR_MSTR_SHIFT), SPI_MCR_MSTR_SHIFT, SPI_MCR_MSTR_WIDTH))
21692 /*@}*/
21693 
21694 /*******************************************************************************
21695  * SPI_TCR - Transfer Count Register
21696  ******************************************************************************/
21697 
21698 /*!
21699  * @brief SPI_TCR - Transfer Count Register (RW)
21700  *
21701  * Reset value: 0x00000000U
21702  *
21703  * TCR contains a counter that indicates the number of SPI transfers made. The
21704  * transfer counter is intended to assist in queue management. Do not write the
21705  * TCR when the module is in the Running state.
21706  */
21707 /*!
21708  * @name Constants and macros for entire SPI_TCR register
21709  */
21710 /*@{*/
21711 #define SPI_RD_TCR(base)         (SPI_TCR_REG(base))
21712 #define SPI_WR_TCR(base, value)  (SPI_TCR_REG(base) = (value))
21713 #define SPI_RMW_TCR(base, mask, value) (SPI_WR_TCR(base, (SPI_RD_TCR(base) & ~(mask)) | (value)))
21714 #define SPI_SET_TCR(base, value) (BME_OR32(&SPI_TCR_REG(base), (uint32_t)(value)))
21715 #define SPI_CLR_TCR(base, value) (BME_AND32(&SPI_TCR_REG(base), (uint32_t)(~(value))))
21716 #define SPI_TOG_TCR(base, value) (BME_XOR32(&SPI_TCR_REG(base), (uint32_t)(value)))
21717 /*@}*/
21718 
21719 /*
21720  * Constants & macros for individual SPI_TCR bitfields
21721  */
21722 
21723 /*!
21724  * @name Register SPI_TCR, field SPI_TCNT[31:16] (RW)
21725  *
21726  * Counts the number of SPI transfers the module makes. The SPI_TCNT field
21727  * increments every time the last bit of an SPI frame is transmitted. A value written
21728  * to SPI_TCNT presets the counter to that value. SPI_TCNT is reset to zero at
21729  * the beginning of the frame when the CTCNT field is set in the executing SPI
21730  * command. The Transfer Counter wraps around; incrementing the counter past 65535
21731  * resets the counter to zero.
21732  */
21733 /*@{*/
21734 /*! @brief Read current value of the SPI_TCR_SPI_TCNT field. */
21735 #define SPI_RD_TCR_SPI_TCNT(base) ((SPI_TCR_REG(base) & SPI_TCR_SPI_TCNT_MASK) >> SPI_TCR_SPI_TCNT_SHIFT)
21736 #define SPI_BRD_TCR_SPI_TCNT(base) (BME_UBFX32(&SPI_TCR_REG(base), SPI_TCR_SPI_TCNT_SHIFT, SPI_TCR_SPI_TCNT_WIDTH))
21737 
21738 /*! @brief Set the SPI_TCNT field to a new value. */
21739 #define SPI_WR_TCR_SPI_TCNT(base, value) (SPI_RMW_TCR(base, SPI_TCR_SPI_TCNT_MASK, SPI_TCR_SPI_TCNT(value)))
21740 #define SPI_BWR_TCR_SPI_TCNT(base, value) (BME_BFI32(&SPI_TCR_REG(base), ((uint32_t)(value) << SPI_TCR_SPI_TCNT_SHIFT), SPI_TCR_SPI_TCNT_SHIFT, SPI_TCR_SPI_TCNT_WIDTH))
21741 /*@}*/
21742 
21743 /*******************************************************************************
21744  * SPI_CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode)
21745  ******************************************************************************/
21746 
21747 /*!
21748  * @brief SPI_CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) (RW)
21749  *
21750  * Reset value: 0x78000000U
21751  *
21752  * When the module is configured as an SPI bus slave, the CTAR0 register is used.
21753  */
21754 /*!
21755  * @name Constants and macros for entire SPI_CTAR_SLAVE register
21756  */
21757 /*@{*/
21758 #define SPI_RD_CTAR_SLAVE(base, index) (SPI_CTAR_SLAVE_REG(base, index))
21759 #define SPI_WR_CTAR_SLAVE(base, index, value) (SPI_CTAR_SLAVE_REG(base, index) = (value))
21760 #define SPI_RMW_CTAR_SLAVE(base, index, mask, value) (SPI_WR_CTAR_SLAVE(base, index, (SPI_RD_CTAR_SLAVE(base, index) & ~(mask)) | (value)))
21761 #define SPI_SET_CTAR_SLAVE(base, index, value) (BME_OR32(&SPI_CTAR_SLAVE_REG(base, index), (uint32_t)(value)))
21762 #define SPI_CLR_CTAR_SLAVE(base, index, value) (BME_AND32(&SPI_CTAR_SLAVE_REG(base, index), (uint32_t)(~(value))))
21763 #define SPI_TOG_CTAR_SLAVE(base, index, value) (BME_XOR32(&SPI_CTAR_SLAVE_REG(base, index), (uint32_t)(value)))
21764 /*@}*/
21765 
21766 /*
21767  * Constants & macros for individual SPI_CTAR_SLAVE bitfields
21768  */
21769 
21770 /*!
21771  * @name Register SPI_CTAR_SLAVE, field CPHA[25] (RW)
21772  *
21773  * Selects which edge of SCK causes data to change and which edge causes data to
21774  * be captured. This bit is used in both master and slave mode. For successful
21775  * communication between serial devices, the devices must have identical clock
21776  * phase settings. In Continuous SCK mode, the bit value is ignored and the
21777  * transfers are done as if the CPHA bit is set to 1.
21778  *
21779  * Values:
21780  * - 0b0 - Data is captured on the leading edge of SCK and changed on the
21781  *     following edge.
21782  * - 0b1 - Data is changed on the leading edge of SCK and captured on the
21783  *     following edge.
21784  */
21785 /*@{*/
21786 /*! @brief Read current value of the SPI_CTAR_SLAVE_CPHA field. */
21787 #define SPI_RD_CTAR_SLAVE_CPHA(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_CPHA_MASK) >> SPI_CTAR_SLAVE_CPHA_SHIFT)
21788 #define SPI_BRD_CTAR_SLAVE_CPHA(base, index) (BME_UBFX32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPHA_SHIFT, SPI_CTAR_SLAVE_CPHA_WIDTH))
21789 
21790 /*! @brief Set the CPHA field to a new value. */
21791 #define SPI_WR_CTAR_SLAVE_CPHA(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_CPHA_MASK, SPI_CTAR_SLAVE_CPHA(value)))
21792 #define SPI_BWR_CTAR_SLAVE_CPHA(base, index, value) (BME_BFI32(&SPI_CTAR_SLAVE_REG(base, index), ((uint32_t)(value) << SPI_CTAR_SLAVE_CPHA_SHIFT), SPI_CTAR_SLAVE_CPHA_SHIFT, SPI_CTAR_SLAVE_CPHA_WIDTH))
21793 /*@}*/
21794 
21795 /*!
21796  * @name Register SPI_CTAR_SLAVE, field CPOL[26] (RW)
21797  *
21798  * Selects the inactive state of the Serial Communications Clock (SCK). In case
21799  * of Continuous SCK mode, when the module goes in low power mode(disabled),
21800  * inactive state of SCK is not guaranted.
21801  *
21802  * Values:
21803  * - 0b0 - The inactive state value of SCK is low.
21804  * - 0b1 - The inactive state value of SCK is high.
21805  */
21806 /*@{*/
21807 /*! @brief Read current value of the SPI_CTAR_SLAVE_CPOL field. */
21808 #define SPI_RD_CTAR_SLAVE_CPOL(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_CPOL_MASK) >> SPI_CTAR_SLAVE_CPOL_SHIFT)
21809 #define SPI_BRD_CTAR_SLAVE_CPOL(base, index) (BME_UBFX32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_CPOL_SHIFT, SPI_CTAR_SLAVE_CPOL_WIDTH))
21810 
21811 /*! @brief Set the CPOL field to a new value. */
21812 #define SPI_WR_CTAR_SLAVE_CPOL(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_CPOL_MASK, SPI_CTAR_SLAVE_CPOL(value)))
21813 #define SPI_BWR_CTAR_SLAVE_CPOL(base, index, value) (BME_BFI32(&SPI_CTAR_SLAVE_REG(base, index), ((uint32_t)(value) << SPI_CTAR_SLAVE_CPOL_SHIFT), SPI_CTAR_SLAVE_CPOL_SHIFT, SPI_CTAR_SLAVE_CPOL_WIDTH))
21814 /*@}*/
21815 
21816 /*!
21817  * @name Register SPI_CTAR_SLAVE, field FMSZ[30:27] (RW)
21818  *
21819  * The number of bits transfered per frame is equal to the FMSZ field value plus
21820  * 1. Note that the minimum valid value of frame size is 4.
21821  */
21822 /*@{*/
21823 /*! @brief Read current value of the SPI_CTAR_SLAVE_FMSZ field. */
21824 #define SPI_RD_CTAR_SLAVE_FMSZ(base, index) ((SPI_CTAR_SLAVE_REG(base, index) & SPI_CTAR_SLAVE_FMSZ_MASK) >> SPI_CTAR_SLAVE_FMSZ_SHIFT)
21825 #define SPI_BRD_CTAR_SLAVE_FMSZ(base, index) (BME_UBFX32(&SPI_CTAR_SLAVE_REG(base, index), SPI_CTAR_SLAVE_FMSZ_SHIFT, SPI_CTAR_SLAVE_FMSZ_WIDTH))
21826 
21827 /*! @brief Set the FMSZ field to a new value. */
21828 #define SPI_WR_CTAR_SLAVE_FMSZ(base, index, value) (SPI_RMW_CTAR_SLAVE(base, index, SPI_CTAR_SLAVE_FMSZ_MASK, SPI_CTAR_SLAVE_FMSZ(value)))
21829 #define SPI_BWR_CTAR_SLAVE_FMSZ(base, index, value) (BME_BFI32(&SPI_CTAR_SLAVE_REG(base, index), ((uint32_t)(value) << SPI_CTAR_SLAVE_FMSZ_SHIFT), SPI_CTAR_SLAVE_FMSZ_SHIFT, SPI_CTAR_SLAVE_FMSZ_WIDTH))
21830 /*@}*/
21831 
21832 /*******************************************************************************
21833  * SPI_CTAR - Clock and Transfer Attributes Register (In Master Mode)
21834  ******************************************************************************/
21835 
21836 /*!
21837  * @brief SPI_CTAR - Clock and Transfer Attributes Register (In Master Mode) (RW)
21838  *
21839  * Reset value: 0x78000000U
21840  *
21841  * CTAR registers are used to define different transfer attributes. The number
21842  * of CTAR registers is parameterized in the RTL and can be from two to eight
21843  * registers. Do not write to the CTAR registers while the module is in the Running
21844  * state. In Master mode, the CTAR registers define combinations of transfer
21845  * attributes such as frame size, clock phase and polarity, data bit ordering, baud
21846  * rate, and various delays. In slave mode, a subset of the bitfields in CTAR0 are
21847  * used to set the slave transfer attributes. When the module is configured as an
21848  * SPI master, the CTAS field in the command portion of the TX FIFO entry
21849  * selects which of the CTAR registers is used. When the module is configured as an SPI
21850  * bus slave, it uses the CTAR0 register.
21851  */
21852 /*!
21853  * @name Constants and macros for entire SPI_CTAR register
21854  */
21855 /*@{*/
21856 #define SPI_RD_CTAR(base, index) (SPI_CTAR_REG(base, index))
21857 #define SPI_WR_CTAR(base, index, value) (SPI_CTAR_REG(base, index) = (value))
21858 #define SPI_RMW_CTAR(base, index, mask, value) (SPI_WR_CTAR(base, index, (SPI_RD_CTAR(base, index) & ~(mask)) | (value)))
21859 #define SPI_SET_CTAR(base, index, value) (BME_OR32(&SPI_CTAR_REG(base, index), (uint32_t)(value)))
21860 #define SPI_CLR_CTAR(base, index, value) (BME_AND32(&SPI_CTAR_REG(base, index), (uint32_t)(~(value))))
21861 #define SPI_TOG_CTAR(base, index, value) (BME_XOR32(&SPI_CTAR_REG(base, index), (uint32_t)(value)))
21862 /*@}*/
21863 
21864 /*
21865  * Constants & macros for individual SPI_CTAR bitfields
21866  */
21867 
21868 /*!
21869  * @name Register SPI_CTAR, field BR[3:0] (RW)
21870  *
21871  * Selects the scaler value for the baud rate. This field is used only in master
21872  * mode. The prescaled protocol clock is divided by the Baud Rate Scaler to
21873  * generate the frequency of the SCK. The baud rate is computed according to the
21874  * following equation: SCK baud rate = (fP /PBR) x [(1+DBR)/BR] The following table
21875  * lists the baud rate scaler values. Baud Rate Scaler CTARn[BR] Baud Rate Scaler
21876  * Value 0000 2 0001 4 0010 6 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256
21877  * 1001 512 1010 1024 1011 2048 1100 4096 1101 8192 1110 16384 1111 32768
21878  */
21879 /*@{*/
21880 /*! @brief Read current value of the SPI_CTAR_BR field. */
21881 #define SPI_RD_CTAR_BR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_BR_MASK) >> SPI_CTAR_BR_SHIFT)
21882 #define SPI_BRD_CTAR_BR(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_BR_SHIFT, SPI_CTAR_BR_WIDTH))
21883 
21884 /*! @brief Set the BR field to a new value. */
21885 #define SPI_WR_CTAR_BR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_BR_MASK, SPI_CTAR_BR(value)))
21886 #define SPI_BWR_CTAR_BR(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(value) << SPI_CTAR_BR_SHIFT), SPI_CTAR_BR_SHIFT, SPI_CTAR_BR_WIDTH))
21887 /*@}*/
21888 
21889 /*!
21890  * @name Register SPI_CTAR, field DT[7:4] (RW)
21891  *
21892  * Selects the Delay after Transfer Scaler. This field is used only in master
21893  * mode. The Delay after Transfer is the time between the negation of the PCS
21894  * signal at the end of a frame and the assertion of PCS at the beginning of the next
21895  * frame. In the Continuous Serial Communications Clock operation, the DT value
21896  * is fixed to one SCK clock period, The Delay after Transfer is a multiple of the
21897  * protocol clock period, and it is computed according to the following
21898  * equation: tDT = (1/fP ) x PDT x DT See Delay Scaler Encoding table in CTARn[CSSCK] bit
21899  * field description for scaler values.
21900  */
21901 /*@{*/
21902 /*! @brief Read current value of the SPI_CTAR_DT field. */
21903 #define SPI_RD_CTAR_DT(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_DT_MASK) >> SPI_CTAR_DT_SHIFT)
21904 #define SPI_BRD_CTAR_DT(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_DT_SHIFT, SPI_CTAR_DT_WIDTH))
21905 
21906 /*! @brief Set the DT field to a new value. */
21907 #define SPI_WR_CTAR_DT(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_DT_MASK, SPI_CTAR_DT(value)))
21908 #define SPI_BWR_CTAR_DT(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(value) << SPI_CTAR_DT_SHIFT), SPI_CTAR_DT_SHIFT, SPI_CTAR_DT_WIDTH))
21909 /*@}*/
21910 
21911 /*!
21912  * @name Register SPI_CTAR, field ASC[11:8] (RW)
21913  *
21914  * Selects the scaler value for the After SCK Delay. This field is used only in
21915  * master mode. The After SCK Delay is the delay between the last edge of SCK and
21916  * the negation of PCS. The delay is a multiple of the protocol clock period,
21917  * and it is computed according to the following equation: t ASC = (1/fP) x PASC x
21918  * ASC See Delay Scaler Encoding table in CTARn[CSSCK] bit field description for
21919  * scaler values. Refer After SCK Delay (tASC ) for more details.
21920  */
21921 /*@{*/
21922 /*! @brief Read current value of the SPI_CTAR_ASC field. */
21923 #define SPI_RD_CTAR_ASC(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_ASC_MASK) >> SPI_CTAR_ASC_SHIFT)
21924 #define SPI_BRD_CTAR_ASC(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_ASC_SHIFT, SPI_CTAR_ASC_WIDTH))
21925 
21926 /*! @brief Set the ASC field to a new value. */
21927 #define SPI_WR_CTAR_ASC(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_ASC_MASK, SPI_CTAR_ASC(value)))
21928 #define SPI_BWR_CTAR_ASC(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(value) << SPI_CTAR_ASC_SHIFT), SPI_CTAR_ASC_SHIFT, SPI_CTAR_ASC_WIDTH))
21929 /*@}*/
21930 
21931 /*!
21932  * @name Register SPI_CTAR, field CSSCK[15:12] (RW)
21933  *
21934  * Selects the scaler value for the PCS to SCK delay. This field is used only in
21935  * master mode. The PCS to SCK Delay is the delay between the assertion of PCS
21936  * and the first edge of the SCK. The delay is a multiple of the protocol clock
21937  * period, and it is computed according to the following equation: t CSC = (1/fP )
21938  * x PCSSCK x CSSCK. The following table lists the delay scaler values. Delay
21939  * Scaler Encoding Field Value Delay Scaler Value 0000 2 0001 4 0010 8 0011 16 0100
21940  * 32 0101 64 0110 128 0111 256 1000 512 1001 1024 1010 2048 1011 4096 1100 8192
21941  * 1101 16384 1110 32768 1111 65536 Refer PCS to SCK Delay (tCSC ) for more
21942  * details.
21943  */
21944 /*@{*/
21945 /*! @brief Read current value of the SPI_CTAR_CSSCK field. */
21946 #define SPI_RD_CTAR_CSSCK(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CSSCK_MASK) >> SPI_CTAR_CSSCK_SHIFT)
21947 #define SPI_BRD_CTAR_CSSCK(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_CSSCK_SHIFT, SPI_CTAR_CSSCK_WIDTH))
21948 
21949 /*! @brief Set the CSSCK field to a new value. */
21950 #define SPI_WR_CTAR_CSSCK(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CSSCK_MASK, SPI_CTAR_CSSCK(value)))
21951 #define SPI_BWR_CTAR_CSSCK(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(value) << SPI_CTAR_CSSCK_SHIFT), SPI_CTAR_CSSCK_SHIFT, SPI_CTAR_CSSCK_WIDTH))
21952 /*@}*/
21953 
21954 /*!
21955  * @name Register SPI_CTAR, field PBR[17:16] (RW)
21956  *
21957  * Selects the prescaler value for the baud rate. This field is used only in
21958  * master mode. The baud rate is the frequency of the SCK. The protocol clock is
21959  * divided by the prescaler value before the baud rate selection takes place. See
21960  * the BR field description for details on how to compute the baud rate.
21961  *
21962  * Values:
21963  * - 0b00 - Baud Rate Prescaler value is 2.
21964  * - 0b01 - Baud Rate Prescaler value is 3.
21965  * - 0b10 - Baud Rate Prescaler value is 5.
21966  * - 0b11 - Baud Rate Prescaler value is 7.
21967  */
21968 /*@{*/
21969 /*! @brief Read current value of the SPI_CTAR_PBR field. */
21970 #define SPI_RD_CTAR_PBR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PBR_MASK) >> SPI_CTAR_PBR_SHIFT)
21971 #define SPI_BRD_CTAR_PBR(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_PBR_SHIFT, SPI_CTAR_PBR_WIDTH))
21972 
21973 /*! @brief Set the PBR field to a new value. */
21974 #define SPI_WR_CTAR_PBR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PBR_MASK, SPI_CTAR_PBR(value)))
21975 #define SPI_BWR_CTAR_PBR(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(value) << SPI_CTAR_PBR_SHIFT), SPI_CTAR_PBR_SHIFT, SPI_CTAR_PBR_WIDTH))
21976 /*@}*/
21977 
21978 /*!
21979  * @name Register SPI_CTAR, field PDT[19:18] (RW)
21980  *
21981  * Selects the prescaler value for the delay between the negation of the PCS
21982  * signal at the end of a frame and the assertion of PCS at the beginning of the
21983  * next frame. The PDT field is only used in master mode. See the DT field
21984  * description for details on how to compute the Delay after Transfer. Refer Delay after
21985  * Transfer (tDT ) for more details.
21986  *
21987  * Values:
21988  * - 0b00 - Delay after Transfer Prescaler value is 1.
21989  * - 0b01 - Delay after Transfer Prescaler value is 3.
21990  * - 0b10 - Delay after Transfer Prescaler value is 5.
21991  * - 0b11 - Delay after Transfer Prescaler value is 7.
21992  */
21993 /*@{*/
21994 /*! @brief Read current value of the SPI_CTAR_PDT field. */
21995 #define SPI_RD_CTAR_PDT(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PDT_MASK) >> SPI_CTAR_PDT_SHIFT)
21996 #define SPI_BRD_CTAR_PDT(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_PDT_SHIFT, SPI_CTAR_PDT_WIDTH))
21997 
21998 /*! @brief Set the PDT field to a new value. */
21999 #define SPI_WR_CTAR_PDT(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PDT_MASK, SPI_CTAR_PDT(value)))
22000 #define SPI_BWR_CTAR_PDT(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(value) << SPI_CTAR_PDT_SHIFT), SPI_CTAR_PDT_SHIFT, SPI_CTAR_PDT_WIDTH))
22001 /*@}*/
22002 
22003 /*!
22004  * @name Register SPI_CTAR, field PASC[21:20] (RW)
22005  *
22006  * Selects the prescaler value for the delay between the last edge of SCK and
22007  * the negation of PCS. See the ASC field description for information on how to
22008  * compute the After SCK Delay. Refer After SCK Delay (tASC ) for more details.
22009  *
22010  * Values:
22011  * - 0b00 - Delay after Transfer Prescaler value is 1.
22012  * - 0b01 - Delay after Transfer Prescaler value is 3.
22013  * - 0b10 - Delay after Transfer Prescaler value is 5.
22014  * - 0b11 - Delay after Transfer Prescaler value is 7.
22015  */
22016 /*@{*/
22017 /*! @brief Read current value of the SPI_CTAR_PASC field. */
22018 #define SPI_RD_CTAR_PASC(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PASC_MASK) >> SPI_CTAR_PASC_SHIFT)
22019 #define SPI_BRD_CTAR_PASC(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_PASC_SHIFT, SPI_CTAR_PASC_WIDTH))
22020 
22021 /*! @brief Set the PASC field to a new value. */
22022 #define SPI_WR_CTAR_PASC(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PASC_MASK, SPI_CTAR_PASC(value)))
22023 #define SPI_BWR_CTAR_PASC(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(value) << SPI_CTAR_PASC_SHIFT), SPI_CTAR_PASC_SHIFT, SPI_CTAR_PASC_WIDTH))
22024 /*@}*/
22025 
22026 /*!
22027  * @name Register SPI_CTAR, field PCSSCK[23:22] (RW)
22028  *
22029  * Selects the prescaler value for the delay between assertion of PCS and the
22030  * first edge of the SCK. See the CSSCK field description for information on how to
22031  * compute the PCS to SCK Delay. Refer PCS to SCK Delay (tCSC ) for more details.
22032  *
22033  * Values:
22034  * - 0b00 - PCS to SCK Prescaler value is 1.
22035  * - 0b01 - PCS to SCK Prescaler value is 3.
22036  * - 0b10 - PCS to SCK Prescaler value is 5.
22037  * - 0b11 - PCS to SCK Prescaler value is 7.
22038  */
22039 /*@{*/
22040 /*! @brief Read current value of the SPI_CTAR_PCSSCK field. */
22041 #define SPI_RD_CTAR_PCSSCK(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_PCSSCK_MASK) >> SPI_CTAR_PCSSCK_SHIFT)
22042 #define SPI_BRD_CTAR_PCSSCK(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_PCSSCK_SHIFT, SPI_CTAR_PCSSCK_WIDTH))
22043 
22044 /*! @brief Set the PCSSCK field to a new value. */
22045 #define SPI_WR_CTAR_PCSSCK(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_PCSSCK_MASK, SPI_CTAR_PCSSCK(value)))
22046 #define SPI_BWR_CTAR_PCSSCK(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(value) << SPI_CTAR_PCSSCK_SHIFT), SPI_CTAR_PCSSCK_SHIFT, SPI_CTAR_PCSSCK_WIDTH))
22047 /*@}*/
22048 
22049 /*!
22050  * @name Register SPI_CTAR, field LSBFE[24] (RW)
22051  *
22052  * Specifies whether the LSB or MSB of the frame is transferred first.
22053  *
22054  * Values:
22055  * - 0b0 - Data is transferred MSB first.
22056  * - 0b1 - Data is transferred LSB first.
22057  */
22058 /*@{*/
22059 /*! @brief Read current value of the SPI_CTAR_LSBFE field. */
22060 #define SPI_RD_CTAR_LSBFE(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_LSBFE_MASK) >> SPI_CTAR_LSBFE_SHIFT)
22061 #define SPI_BRD_CTAR_LSBFE(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_LSBFE_SHIFT, SPI_CTAR_LSBFE_WIDTH))
22062 
22063 /*! @brief Set the LSBFE field to a new value. */
22064 #define SPI_WR_CTAR_LSBFE(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_LSBFE_MASK, SPI_CTAR_LSBFE(value)))
22065 #define SPI_BWR_CTAR_LSBFE(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(value) << SPI_CTAR_LSBFE_SHIFT), SPI_CTAR_LSBFE_SHIFT, SPI_CTAR_LSBFE_WIDTH))
22066 /*@}*/
22067 
22068 /*!
22069  * @name Register SPI_CTAR, field CPHA[25] (RW)
22070  *
22071  * Selects which edge of SCK causes data to change and which edge causes data to
22072  * be captured. This bit is used in both master and slave mode. For successful
22073  * communication between serial devices, the devices must have identical clock
22074  * phase settings. In Continuous SCK mode, the bit value is ignored and the
22075  * transfers are done as if the CPHA bit is set to 1.
22076  *
22077  * Values:
22078  * - 0b0 - Data is captured on the leading edge of SCK and changed on the
22079  *     following edge.
22080  * - 0b1 - Data is changed on the leading edge of SCK and captured on the
22081  *     following edge.
22082  */
22083 /*@{*/
22084 /*! @brief Read current value of the SPI_CTAR_CPHA field. */
22085 #define SPI_RD_CTAR_CPHA(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CPHA_MASK) >> SPI_CTAR_CPHA_SHIFT)
22086 #define SPI_BRD_CTAR_CPHA(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPHA_SHIFT, SPI_CTAR_CPHA_WIDTH))
22087 
22088 /*! @brief Set the CPHA field to a new value. */
22089 #define SPI_WR_CTAR_CPHA(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CPHA_MASK, SPI_CTAR_CPHA(value)))
22090 #define SPI_BWR_CTAR_CPHA(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(value) << SPI_CTAR_CPHA_SHIFT), SPI_CTAR_CPHA_SHIFT, SPI_CTAR_CPHA_WIDTH))
22091 /*@}*/
22092 
22093 /*!
22094  * @name Register SPI_CTAR, field CPOL[26] (RW)
22095  *
22096  * Selects the inactive state of the Serial Communications Clock (SCK). This bit
22097  * is used in both master and slave mode. For successful communication between
22098  * serial devices, the devices must have identical clock polarities. When the
22099  * Continuous Selection Format is selected, switching between clock polarities
22100  * without stopping the module can cause errors in the transfer due to the peripheral
22101  * device interpreting the switch of clock polarity as a valid clock edge. In case
22102  * of Continuous SCK mode, when the module goes in low power mode(disabled),
22103  * inactive state of SCK is not guaranted.
22104  *
22105  * Values:
22106  * - 0b0 - The inactive state value of SCK is low.
22107  * - 0b1 - The inactive state value of SCK is high.
22108  */
22109 /*@{*/
22110 /*! @brief Read current value of the SPI_CTAR_CPOL field. */
22111 #define SPI_RD_CTAR_CPOL(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_CPOL_MASK) >> SPI_CTAR_CPOL_SHIFT)
22112 #define SPI_BRD_CTAR_CPOL(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_CPOL_SHIFT, SPI_CTAR_CPOL_WIDTH))
22113 
22114 /*! @brief Set the CPOL field to a new value. */
22115 #define SPI_WR_CTAR_CPOL(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_CPOL_MASK, SPI_CTAR_CPOL(value)))
22116 #define SPI_BWR_CTAR_CPOL(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(value) << SPI_CTAR_CPOL_SHIFT), SPI_CTAR_CPOL_SHIFT, SPI_CTAR_CPOL_WIDTH))
22117 /*@}*/
22118 
22119 /*!
22120  * @name Register SPI_CTAR, field FMSZ[30:27] (RW)
22121  *
22122  * The number of bits transferred per frame is equal to the FMSZ value plus 1.
22123  * Regardless of the transmission mode, the minimum valid frame size value is 4.
22124  */
22125 /*@{*/
22126 /*! @brief Read current value of the SPI_CTAR_FMSZ field. */
22127 #define SPI_RD_CTAR_FMSZ(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_FMSZ_MASK) >> SPI_CTAR_FMSZ_SHIFT)
22128 #define SPI_BRD_CTAR_FMSZ(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_FMSZ_SHIFT, SPI_CTAR_FMSZ_WIDTH))
22129 
22130 /*! @brief Set the FMSZ field to a new value. */
22131 #define SPI_WR_CTAR_FMSZ(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_FMSZ_MASK, SPI_CTAR_FMSZ(value)))
22132 #define SPI_BWR_CTAR_FMSZ(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(value) << SPI_CTAR_FMSZ_SHIFT), SPI_CTAR_FMSZ_SHIFT, SPI_CTAR_FMSZ_WIDTH))
22133 /*@}*/
22134 
22135 /*!
22136  * @name Register SPI_CTAR, field DBR[31] (RW)
22137  *
22138  * Doubles the effective baud rate of the Serial Communications Clock (SCK).
22139  * This field is used only in master mode. It effectively halves the Baud Rate
22140  * division ratio, supporting faster frequencies, and odd division ratios for the
22141  * Serial Communications Clock (SCK). When the DBR bit is set, the duty cycle of the
22142  * Serial Communications Clock (SCK) depends on the value in the Baud Rate
22143  * Prescaler and the Clock Phase bit as listed in the following table. See the BR field
22144  * description for details on how to compute the baud rate. SPI SCK Duty Cycle
22145  * DBR CPHA PBR SCK Duty Cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10
22146  * 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43
22147  *
22148  * Values:
22149  * - 0b0 - The baud rate is computed normally with a 50/50 duty cycle.
22150  * - 0b1 - The baud rate is doubled with the duty cycle depending on the Baud
22151  *     Rate Prescaler.
22152  */
22153 /*@{*/
22154 /*! @brief Read current value of the SPI_CTAR_DBR field. */
22155 #define SPI_RD_CTAR_DBR(base, index) ((SPI_CTAR_REG(base, index) & SPI_CTAR_DBR_MASK) >> SPI_CTAR_DBR_SHIFT)
22156 #define SPI_BRD_CTAR_DBR(base, index) (BME_UBFX32(&SPI_CTAR_REG(base, index), SPI_CTAR_DBR_SHIFT, SPI_CTAR_DBR_WIDTH))
22157 
22158 /*! @brief Set the DBR field to a new value. */
22159 #define SPI_WR_CTAR_DBR(base, index, value) (SPI_RMW_CTAR(base, index, SPI_CTAR_DBR_MASK, SPI_CTAR_DBR(value)))
22160 #define SPI_BWR_CTAR_DBR(base, index, value) (BME_BFI32(&SPI_CTAR_REG(base, index), ((uint32_t)(value) << SPI_CTAR_DBR_SHIFT), SPI_CTAR_DBR_SHIFT, SPI_CTAR_DBR_WIDTH))
22161 /*@}*/
22162 
22163 /*******************************************************************************
22164  * SPI_SR - Status Register
22165  ******************************************************************************/
22166 
22167 /*!
22168  * @brief SPI_SR - Status Register (RW)
22169  *
22170  * Reset value: 0x02000000U
22171  *
22172  * SR contains status and flag bits. The bits reflect the status of the module
22173  * and indicate the occurrence of events that can generate interrupt or DMA
22174  * requests. Software can clear flag bits in the SR by writing a 1 to them. Writing a 0
22175  * to a flag bit has no effect. This register may not be writable in Module
22176  * Disable mode due to the use of power saving mechanisms.
22177  */
22178 /*!
22179  * @name Constants and macros for entire SPI_SR register
22180  */
22181 /*@{*/
22182 #define SPI_RD_SR(base)          (SPI_SR_REG(base))
22183 #define SPI_WR_SR(base, value)   (SPI_SR_REG(base) = (value))
22184 #define SPI_RMW_SR(base, mask, value) (SPI_WR_SR(base, (SPI_RD_SR(base) & ~(mask)) | (value)))
22185 #define SPI_SET_SR(base, value)  (BME_OR32(&SPI_SR_REG(base), (uint32_t)(value)))
22186 #define SPI_CLR_SR(base, value)  (BME_AND32(&SPI_SR_REG(base), (uint32_t)(~(value))))
22187 #define SPI_TOG_SR(base, value)  (BME_XOR32(&SPI_SR_REG(base), (uint32_t)(value)))
22188 /*@}*/
22189 
22190 /*
22191  * Constants & macros for individual SPI_SR bitfields
22192  */
22193 
22194 /*!
22195  * @name Register SPI_SR, field POPNXTPTR[3:0] (RO)
22196  *
22197  * Contains a pointer to the RX FIFO entry to be returned when the POPR is read.
22198  * The POPNXTPTR is updated when the POPR is read.
22199  */
22200 /*@{*/
22201 /*! @brief Read current value of the SPI_SR_POPNXTPTR field. */
22202 #define SPI_RD_SR_POPNXTPTR(base) ((SPI_SR_REG(base) & SPI_SR_POPNXTPTR_MASK) >> SPI_SR_POPNXTPTR_SHIFT)
22203 #define SPI_BRD_SR_POPNXTPTR(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_POPNXTPTR_SHIFT, SPI_SR_POPNXTPTR_WIDTH))
22204 /*@}*/
22205 
22206 /*!
22207  * @name Register SPI_SR, field RXCTR[7:4] (RO)
22208  *
22209  * Indicates the number of entries in the RX FIFO. The RXCTR is decremented
22210  * every time the POPR is read. The RXCTR is incremented every time data is
22211  * transferred from the shift register to the RX FIFO.
22212  */
22213 /*@{*/
22214 /*! @brief Read current value of the SPI_SR_RXCTR field. */
22215 #define SPI_RD_SR_RXCTR(base) ((SPI_SR_REG(base) & SPI_SR_RXCTR_MASK) >> SPI_SR_RXCTR_SHIFT)
22216 #define SPI_BRD_SR_RXCTR(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_RXCTR_SHIFT, SPI_SR_RXCTR_WIDTH))
22217 /*@}*/
22218 
22219 /*!
22220  * @name Register SPI_SR, field TXNXTPTR[11:8] (RO)
22221  *
22222  * Indicates which TX FIFO entry is transmitted during the next transfer. The
22223  * TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to
22224  * the shift register.
22225  */
22226 /*@{*/
22227 /*! @brief Read current value of the SPI_SR_TXNXTPTR field. */
22228 #define SPI_RD_SR_TXNXTPTR(base) ((SPI_SR_REG(base) & SPI_SR_TXNXTPTR_MASK) >> SPI_SR_TXNXTPTR_SHIFT)
22229 #define SPI_BRD_SR_TXNXTPTR(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_TXNXTPTR_SHIFT, SPI_SR_TXNXTPTR_WIDTH))
22230 /*@}*/
22231 
22232 /*!
22233  * @name Register SPI_SR, field TXCTR[15:12] (RO)
22234  *
22235  * Indicates the number of valid entries in the TX FIFO. The TXCTR is
22236  * incremented every time the PUSHR is written. The TXCTR is decremented every time an SPI
22237  * command is executed and the SPI data is transferred to the shift register.
22238  */
22239 /*@{*/
22240 /*! @brief Read current value of the SPI_SR_TXCTR field. */
22241 #define SPI_RD_SR_TXCTR(base) ((SPI_SR_REG(base) & SPI_SR_TXCTR_MASK) >> SPI_SR_TXCTR_SHIFT)
22242 #define SPI_BRD_SR_TXCTR(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_TXCTR_SHIFT, SPI_SR_TXCTR_WIDTH))
22243 /*@}*/
22244 
22245 /*!
22246  * @name Register SPI_SR, field RFDF[17] (W1C)
22247  *
22248  * Provides a method for the module to request that entries be removed from the
22249  * RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be
22250  * cleared by writing 1 to it or by acknowledgement from the DMA controller when
22251  * the RX FIFO is empty.
22252  *
22253  * Values:
22254  * - 0b0 - RX FIFO is empty.
22255  * - 0b1 - RX FIFO is not empty.
22256  */
22257 /*@{*/
22258 /*! @brief Read current value of the SPI_SR_RFDF field. */
22259 #define SPI_RD_SR_RFDF(base) ((SPI_SR_REG(base) & SPI_SR_RFDF_MASK) >> SPI_SR_RFDF_SHIFT)
22260 #define SPI_BRD_SR_RFDF(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_RFDF_SHIFT, SPI_SR_RFDF_WIDTH))
22261 
22262 /*! @brief Set the RFDF field to a new value. */
22263 #define SPI_WR_SR_RFDF(base, value) (SPI_RMW_SR(base, (SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_RFDF(value)))
22264 #define SPI_BWR_SR_RFDF(base, value) (BME_BFI32(&SPI_SR_REG(base), ((uint32_t)(value) << SPI_SR_RFDF_SHIFT), SPI_SR_RFDF_SHIFT, SPI_SR_RFDF_WIDTH))
22265 /*@}*/
22266 
22267 /*!
22268  * @name Register SPI_SR, field RFOF[19] (W1C)
22269  *
22270  * Indicates an overflow condition in the RX FIFO. The field is set when the RX
22271  * FIFO and shift register are full and a transfer is initiated. The bit remains
22272  * set until it is cleared by writing a 1 to it.
22273  *
22274  * Values:
22275  * - 0b0 - No Rx FIFO overflow.
22276  * - 0b1 - Rx FIFO overflow has occurred.
22277  */
22278 /*@{*/
22279 /*! @brief Read current value of the SPI_SR_RFOF field. */
22280 #define SPI_RD_SR_RFOF(base) ((SPI_SR_REG(base) & SPI_SR_RFOF_MASK) >> SPI_SR_RFOF_SHIFT)
22281 #define SPI_BRD_SR_RFOF(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_RFOF_SHIFT, SPI_SR_RFOF_WIDTH))
22282 
22283 /*! @brief Set the RFOF field to a new value. */
22284 #define SPI_WR_SR_RFOF(base, value) (SPI_RMW_SR(base, (SPI_SR_RFOF_MASK | SPI_SR_RFDF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_RFOF(value)))
22285 #define SPI_BWR_SR_RFOF(base, value) (BME_BFI32(&SPI_SR_REG(base), ((uint32_t)(value) << SPI_SR_RFOF_SHIFT), SPI_SR_RFOF_SHIFT, SPI_SR_RFOF_WIDTH))
22286 /*@}*/
22287 
22288 /*!
22289  * @name Register SPI_SR, field TFFF[25] (W1C)
22290  *
22291  * Provides a method for the module to request more entries to be added to the
22292  * TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be
22293  * cleared by writing 1 to it or by acknowledgement from the DMA controller to
22294  * the TX FIFO full request.
22295  *
22296  * Values:
22297  * - 0b0 - TX FIFO is full.
22298  * - 0b1 - TX FIFO is not full.
22299  */
22300 /*@{*/
22301 /*! @brief Read current value of the SPI_SR_TFFF field. */
22302 #define SPI_RD_SR_TFFF(base) ((SPI_SR_REG(base) & SPI_SR_TFFF_MASK) >> SPI_SR_TFFF_SHIFT)
22303 #define SPI_BRD_SR_TFFF(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_TFFF_SHIFT, SPI_SR_TFFF_WIDTH))
22304 
22305 /*! @brief Set the TFFF field to a new value. */
22306 #define SPI_WR_SR_TFFF(base, value) (SPI_RMW_SR(base, (SPI_SR_TFFF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_TFFF(value)))
22307 #define SPI_BWR_SR_TFFF(base, value) (BME_BFI32(&SPI_SR_REG(base), ((uint32_t)(value) << SPI_SR_TFFF_SHIFT), SPI_SR_TFFF_SHIFT, SPI_SR_TFFF_WIDTH))
22308 /*@}*/
22309 
22310 /*!
22311  * @name Register SPI_SR, field TFUF[27] (W1C)
22312  *
22313  * Indicates an underflow condition in the TX FIFO. The transmit underflow
22314  * condition is detected only for SPI blocks operating in Slave mode and SPI
22315  * configuration. TFUF is set when the TX FIFO of the module operating in SPI Slave mode
22316  * is empty and an external SPI master initiates a transfer. The TFUF bit remains
22317  * set until cleared by writing 1 to it.
22318  *
22319  * Values:
22320  * - 0b0 - No TX FIFO underflow.
22321  * - 0b1 - TX FIFO underflow has occurred.
22322  */
22323 /*@{*/
22324 /*! @brief Read current value of the SPI_SR_TFUF field. */
22325 #define SPI_RD_SR_TFUF(base) ((SPI_SR_REG(base) & SPI_SR_TFUF_MASK) >> SPI_SR_TFUF_SHIFT)
22326 #define SPI_BRD_SR_TFUF(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_TFUF_SHIFT, SPI_SR_TFUF_WIDTH))
22327 
22328 /*! @brief Set the TFUF field to a new value. */
22329 #define SPI_WR_SR_TFUF(base, value) (SPI_RMW_SR(base, (SPI_SR_TFUF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_TFUF(value)))
22330 #define SPI_BWR_SR_TFUF(base, value) (BME_BFI32(&SPI_SR_REG(base), ((uint32_t)(value) << SPI_SR_TFUF_SHIFT), SPI_SR_TFUF_SHIFT, SPI_SR_TFUF_WIDTH))
22331 /*@}*/
22332 
22333 /*!
22334  * @name Register SPI_SR, field EOQF[28] (W1C)
22335  *
22336  * Indicates that the last entry in a queue has been transmitted when the module
22337  * is in Master mode. The EOQF bit is set when the TX FIFO entry has the EOQ bit
22338  * set in the command halfword and the end of the transfer is reached. The EOQF
22339  * bit remains set until cleared by writing a 1 to it. When the EOQF bit is set,
22340  * the TXRXS bit is automatically cleared.
22341  *
22342  * Values:
22343  * - 0b0 - EOQ is not set in the executing command.
22344  * - 0b1 - EOQ is set in the executing SPI command.
22345  */
22346 /*@{*/
22347 /*! @brief Read current value of the SPI_SR_EOQF field. */
22348 #define SPI_RD_SR_EOQF(base) ((SPI_SR_REG(base) & SPI_SR_EOQF_MASK) >> SPI_SR_EOQF_SHIFT)
22349 #define SPI_BRD_SR_EOQF(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_EOQF_SHIFT, SPI_SR_EOQF_WIDTH))
22350 
22351 /*! @brief Set the EOQF field to a new value. */
22352 #define SPI_WR_SR_EOQF(base, value) (SPI_RMW_SR(base, (SPI_SR_EOQF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TXRXS_MASK | SPI_SR_TCF_MASK), SPI_SR_EOQF(value)))
22353 #define SPI_BWR_SR_EOQF(base, value) (BME_BFI32(&SPI_SR_REG(base), ((uint32_t)(value) << SPI_SR_EOQF_SHIFT), SPI_SR_EOQF_SHIFT, SPI_SR_EOQF_WIDTH))
22354 /*@}*/
22355 
22356 /*!
22357  * @name Register SPI_SR, field TXRXS[30] (W1C)
22358  *
22359  * Reflects the run status of the module.
22360  *
22361  * Values:
22362  * - 0b0 - Transmit and receive operations are disabled (The module is in
22363  *     Stopped state).
22364  * - 0b1 - Transmit and receive operations are enabled (The module is in Running
22365  *     state).
22366  */
22367 /*@{*/
22368 /*! @brief Read current value of the SPI_SR_TXRXS field. */
22369 #define SPI_RD_SR_TXRXS(base) ((SPI_SR_REG(base) & SPI_SR_TXRXS_MASK) >> SPI_SR_TXRXS_SHIFT)
22370 #define SPI_BRD_SR_TXRXS(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_TXRXS_SHIFT, SPI_SR_TXRXS_WIDTH))
22371 
22372 /*! @brief Set the TXRXS field to a new value. */
22373 #define SPI_WR_SR_TXRXS(base, value) (SPI_RMW_SR(base, (SPI_SR_TXRXS_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TCF_MASK), SPI_SR_TXRXS(value)))
22374 #define SPI_BWR_SR_TXRXS(base, value) (BME_BFI32(&SPI_SR_REG(base), ((uint32_t)(value) << SPI_SR_TXRXS_SHIFT), SPI_SR_TXRXS_SHIFT, SPI_SR_TXRXS_WIDTH))
22375 /*@}*/
22376 
22377 /*!
22378  * @name Register SPI_SR, field TCF[31] (W1C)
22379  *
22380  * Indicates that all bits in a frame have been shifted out. TCF remains set
22381  * until it is cleared by writing a 1 to it.
22382  *
22383  * Values:
22384  * - 0b0 - Transfer not complete.
22385  * - 0b1 - Transfer complete.
22386  */
22387 /*@{*/
22388 /*! @brief Read current value of the SPI_SR_TCF field. */
22389 #define SPI_RD_SR_TCF(base)  ((SPI_SR_REG(base) & SPI_SR_TCF_MASK) >> SPI_SR_TCF_SHIFT)
22390 #define SPI_BRD_SR_TCF(base) (BME_UBFX32(&SPI_SR_REG(base), SPI_SR_TCF_SHIFT, SPI_SR_TCF_WIDTH))
22391 
22392 /*! @brief Set the TCF field to a new value. */
22393 #define SPI_WR_SR_TCF(base, value) (SPI_RMW_SR(base, (SPI_SR_TCF_MASK | SPI_SR_RFDF_MASK | SPI_SR_RFOF_MASK | SPI_SR_TFFF_MASK | SPI_SR_TFUF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TXRXS_MASK), SPI_SR_TCF(value)))
22394 #define SPI_BWR_SR_TCF(base, value) (BME_BFI32(&SPI_SR_REG(base), ((uint32_t)(value) << SPI_SR_TCF_SHIFT), SPI_SR_TCF_SHIFT, SPI_SR_TCF_WIDTH))
22395 /*@}*/
22396 
22397 /*******************************************************************************
22398  * SPI_RSER - DMA/Interrupt Request Select and Enable Register
22399  ******************************************************************************/
22400 
22401 /*!
22402  * @brief SPI_RSER - DMA/Interrupt Request Select and Enable Register (RW)
22403  *
22404  * Reset value: 0x00000000U
22405  *
22406  * RSER controls DMA and interrupt requests. Do not write to the RSER while the
22407  * module is in the Running state.
22408  */
22409 /*!
22410  * @name Constants and macros for entire SPI_RSER register
22411  */
22412 /*@{*/
22413 #define SPI_RD_RSER(base)        (SPI_RSER_REG(base))
22414 #define SPI_WR_RSER(base, value) (SPI_RSER_REG(base) = (value))
22415 #define SPI_RMW_RSER(base, mask, value) (SPI_WR_RSER(base, (SPI_RD_RSER(base) & ~(mask)) | (value)))
22416 #define SPI_SET_RSER(base, value) (BME_OR32(&SPI_RSER_REG(base), (uint32_t)(value)))
22417 #define SPI_CLR_RSER(base, value) (BME_AND32(&SPI_RSER_REG(base), (uint32_t)(~(value))))
22418 #define SPI_TOG_RSER(base, value) (BME_XOR32(&SPI_RSER_REG(base), (uint32_t)(value)))
22419 /*@}*/
22420 
22421 /*
22422  * Constants & macros for individual SPI_RSER bitfields
22423  */
22424 
22425 /*!
22426  * @name Register SPI_RSER, field RFDF_DIRS[16] (RW)
22427  *
22428  * Selects between generating a DMA request or an interrupt request. When the
22429  * RFDF flag bit in the SR is set, and the RFDF_RE bit in the RSER is set, the
22430  * RFDF_DIRS bit selects between generating an interrupt request or a DMA request.
22431  *
22432  * Values:
22433  * - 0b0 - Interrupt request.
22434  * - 0b1 - DMA request.
22435  */
22436 /*@{*/
22437 /*! @brief Read current value of the SPI_RSER_RFDF_DIRS field. */
22438 #define SPI_RD_RSER_RFDF_DIRS(base) ((SPI_RSER_REG(base) & SPI_RSER_RFDF_DIRS_MASK) >> SPI_RSER_RFDF_DIRS_SHIFT)
22439 #define SPI_BRD_RSER_RFDF_DIRS(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_RFDF_DIRS_SHIFT, SPI_RSER_RFDF_DIRS_WIDTH))
22440 
22441 /*! @brief Set the RFDF_DIRS field to a new value. */
22442 #define SPI_WR_RSER_RFDF_DIRS(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFDF_DIRS_MASK, SPI_RSER_RFDF_DIRS(value)))
22443 #define SPI_BWR_RSER_RFDF_DIRS(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << SPI_RSER_RFDF_DIRS_SHIFT), SPI_RSER_RFDF_DIRS_SHIFT, SPI_RSER_RFDF_DIRS_WIDTH))
22444 /*@}*/
22445 
22446 /*!
22447  * @name Register SPI_RSER, field RFDF_RE[17] (RW)
22448  *
22449  * Enables the RFDF flag in the SR to generate a request. The RFDF_DIRS bit
22450  * selects between generating an interrupt request or a DMA request.
22451  *
22452  * Values:
22453  * - 0b0 - RFDF interrupt or DMA requests are disabled.
22454  * - 0b1 - RFDF interrupt or DMA requests are enabled.
22455  */
22456 /*@{*/
22457 /*! @brief Read current value of the SPI_RSER_RFDF_RE field. */
22458 #define SPI_RD_RSER_RFDF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_RFDF_RE_MASK) >> SPI_RSER_RFDF_RE_SHIFT)
22459 #define SPI_BRD_RSER_RFDF_RE(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_RFDF_RE_SHIFT, SPI_RSER_RFDF_RE_WIDTH))
22460 
22461 /*! @brief Set the RFDF_RE field to a new value. */
22462 #define SPI_WR_RSER_RFDF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFDF_RE_MASK, SPI_RSER_RFDF_RE(value)))
22463 #define SPI_BWR_RSER_RFDF_RE(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << SPI_RSER_RFDF_RE_SHIFT), SPI_RSER_RFDF_RE_SHIFT, SPI_RSER_RFDF_RE_WIDTH))
22464 /*@}*/
22465 
22466 /*!
22467  * @name Register SPI_RSER, field RFOF_RE[19] (RW)
22468  *
22469  * Enables the RFOF flag in the SR to generate an interrupt request.
22470  *
22471  * Values:
22472  * - 0b0 - RFOF interrupt requests are disabled.
22473  * - 0b1 - RFOF interrupt requests are enabled.
22474  */
22475 /*@{*/
22476 /*! @brief Read current value of the SPI_RSER_RFOF_RE field. */
22477 #define SPI_RD_RSER_RFOF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_RFOF_RE_MASK) >> SPI_RSER_RFOF_RE_SHIFT)
22478 #define SPI_BRD_RSER_RFOF_RE(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_RFOF_RE_SHIFT, SPI_RSER_RFOF_RE_WIDTH))
22479 
22480 /*! @brief Set the RFOF_RE field to a new value. */
22481 #define SPI_WR_RSER_RFOF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_RFOF_RE_MASK, SPI_RSER_RFOF_RE(value)))
22482 #define SPI_BWR_RSER_RFOF_RE(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << SPI_RSER_RFOF_RE_SHIFT), SPI_RSER_RFOF_RE_SHIFT, SPI_RSER_RFOF_RE_WIDTH))
22483 /*@}*/
22484 
22485 /*!
22486  * @name Register SPI_RSER, field TFFF_DIRS[24] (RW)
22487  *
22488  * Selects between generating a DMA request or an interrupt request. When
22489  * SR[TFFF] and RSER[TFFF_RE] are set, this field selects between generating an
22490  * interrupt request or a DMA request.
22491  *
22492  * Values:
22493  * - 0b0 - TFFF flag generates interrupt requests.
22494  * - 0b1 - TFFF flag generates DMA requests.
22495  */
22496 /*@{*/
22497 /*! @brief Read current value of the SPI_RSER_TFFF_DIRS field. */
22498 #define SPI_RD_RSER_TFFF_DIRS(base) ((SPI_RSER_REG(base) & SPI_RSER_TFFF_DIRS_MASK) >> SPI_RSER_TFFF_DIRS_SHIFT)
22499 #define SPI_BRD_RSER_TFFF_DIRS(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_TFFF_DIRS_SHIFT, SPI_RSER_TFFF_DIRS_WIDTH))
22500 
22501 /*! @brief Set the TFFF_DIRS field to a new value. */
22502 #define SPI_WR_RSER_TFFF_DIRS(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFFF_DIRS_MASK, SPI_RSER_TFFF_DIRS(value)))
22503 #define SPI_BWR_RSER_TFFF_DIRS(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << SPI_RSER_TFFF_DIRS_SHIFT), SPI_RSER_TFFF_DIRS_SHIFT, SPI_RSER_TFFF_DIRS_WIDTH))
22504 /*@}*/
22505 
22506 /*!
22507  * @name Register SPI_RSER, field TFFF_RE[25] (RW)
22508  *
22509  * Enables the TFFF flag in the SR to generate a request. The TFFF_DIRS bit
22510  * selects between generating an interrupt request or a DMA request.
22511  *
22512  * Values:
22513  * - 0b0 - TFFF interrupts or DMA requests are disabled.
22514  * - 0b1 - TFFF interrupts or DMA requests are enabled.
22515  */
22516 /*@{*/
22517 /*! @brief Read current value of the SPI_RSER_TFFF_RE field. */
22518 #define SPI_RD_RSER_TFFF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TFFF_RE_MASK) >> SPI_RSER_TFFF_RE_SHIFT)
22519 #define SPI_BRD_RSER_TFFF_RE(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_TFFF_RE_SHIFT, SPI_RSER_TFFF_RE_WIDTH))
22520 
22521 /*! @brief Set the TFFF_RE field to a new value. */
22522 #define SPI_WR_RSER_TFFF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFFF_RE_MASK, SPI_RSER_TFFF_RE(value)))
22523 #define SPI_BWR_RSER_TFFF_RE(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << SPI_RSER_TFFF_RE_SHIFT), SPI_RSER_TFFF_RE_SHIFT, SPI_RSER_TFFF_RE_WIDTH))
22524 /*@}*/
22525 
22526 /*!
22527  * @name Register SPI_RSER, field TFUF_RE[27] (RW)
22528  *
22529  * Enables the TFUF flag in the SR to generate an interrupt request.
22530  *
22531  * Values:
22532  * - 0b0 - TFUF interrupt requests are disabled.
22533  * - 0b1 - TFUF interrupt requests are enabled.
22534  */
22535 /*@{*/
22536 /*! @brief Read current value of the SPI_RSER_TFUF_RE field. */
22537 #define SPI_RD_RSER_TFUF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TFUF_RE_MASK) >> SPI_RSER_TFUF_RE_SHIFT)
22538 #define SPI_BRD_RSER_TFUF_RE(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_TFUF_RE_SHIFT, SPI_RSER_TFUF_RE_WIDTH))
22539 
22540 /*! @brief Set the TFUF_RE field to a new value. */
22541 #define SPI_WR_RSER_TFUF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TFUF_RE_MASK, SPI_RSER_TFUF_RE(value)))
22542 #define SPI_BWR_RSER_TFUF_RE(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << SPI_RSER_TFUF_RE_SHIFT), SPI_RSER_TFUF_RE_SHIFT, SPI_RSER_TFUF_RE_WIDTH))
22543 /*@}*/
22544 
22545 /*!
22546  * @name Register SPI_RSER, field EOQF_RE[28] (RW)
22547  *
22548  * Enables the EOQF flag in the SR to generate an interrupt request.
22549  *
22550  * Values:
22551  * - 0b0 - EOQF interrupt requests are disabled.
22552  * - 0b1 - EOQF interrupt requests are enabled.
22553  */
22554 /*@{*/
22555 /*! @brief Read current value of the SPI_RSER_EOQF_RE field. */
22556 #define SPI_RD_RSER_EOQF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_EOQF_RE_MASK) >> SPI_RSER_EOQF_RE_SHIFT)
22557 #define SPI_BRD_RSER_EOQF_RE(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_EOQF_RE_SHIFT, SPI_RSER_EOQF_RE_WIDTH))
22558 
22559 /*! @brief Set the EOQF_RE field to a new value. */
22560 #define SPI_WR_RSER_EOQF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_EOQF_RE_MASK, SPI_RSER_EOQF_RE(value)))
22561 #define SPI_BWR_RSER_EOQF_RE(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << SPI_RSER_EOQF_RE_SHIFT), SPI_RSER_EOQF_RE_SHIFT, SPI_RSER_EOQF_RE_WIDTH))
22562 /*@}*/
22563 
22564 /*!
22565  * @name Register SPI_RSER, field TCF_RE[31] (RW)
22566  *
22567  * Enables TCF flag in the SR to generate an interrupt request.
22568  *
22569  * Values:
22570  * - 0b0 - TCF interrupt requests are disabled.
22571  * - 0b1 - TCF interrupt requests are enabled.
22572  */
22573 /*@{*/
22574 /*! @brief Read current value of the SPI_RSER_TCF_RE field. */
22575 #define SPI_RD_RSER_TCF_RE(base) ((SPI_RSER_REG(base) & SPI_RSER_TCF_RE_MASK) >> SPI_RSER_TCF_RE_SHIFT)
22576 #define SPI_BRD_RSER_TCF_RE(base) (BME_UBFX32(&SPI_RSER_REG(base), SPI_RSER_TCF_RE_SHIFT, SPI_RSER_TCF_RE_WIDTH))
22577 
22578 /*! @brief Set the TCF_RE field to a new value. */
22579 #define SPI_WR_RSER_TCF_RE(base, value) (SPI_RMW_RSER(base, SPI_RSER_TCF_RE_MASK, SPI_RSER_TCF_RE(value)))
22580 #define SPI_BWR_RSER_TCF_RE(base, value) (BME_BFI32(&SPI_RSER_REG(base), ((uint32_t)(value) << SPI_RSER_TCF_RE_SHIFT), SPI_RSER_TCF_RE_SHIFT, SPI_RSER_TCF_RE_WIDTH))
22581 /*@}*/
22582 
22583 /*******************************************************************************
22584  * SPI_PUSHR - PUSH TX FIFO Register In Master Mode
22585  ******************************************************************************/
22586 
22587 /*!
22588  * @brief SPI_PUSHR - PUSH TX FIFO Register In Master Mode (RW)
22589  *
22590  * Reset value: 0x00000000U
22591  *
22592  * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
22593  * transfers all 32 bits to the TX FIFO. In Master mode, the register transfers
22594  * 16 bits of data and 16 bits of command information. In Slave mode, all 32 bits
22595  * can be used as data, supporting up to 32-bit frame operation. A read access
22596  * of PUSHR returns the topmost TX FIFO entry. When the module is disabled,
22597  * writing to this register does not update the FIFO. Therefore, any reads performed
22598  * while the module is disabled return the last PUSHR write performed while the
22599  * module was still enabled.
22600  */
22601 /*!
22602  * @name Constants and macros for entire SPI_PUSHR register
22603  */
22604 /*@{*/
22605 #define SPI_RD_PUSHR(base)       (SPI_PUSHR_REG(base))
22606 #define SPI_WR_PUSHR(base, value) (SPI_PUSHR_REG(base) = (value))
22607 #define SPI_RMW_PUSHR(base, mask, value) (SPI_WR_PUSHR(base, (SPI_RD_PUSHR(base) & ~(mask)) | (value)))
22608 #define SPI_SET_PUSHR(base, value) (BME_OR32(&SPI_PUSHR_REG(base), (uint32_t)(value)))
22609 #define SPI_CLR_PUSHR(base, value) (BME_AND32(&SPI_PUSHR_REG(base), (uint32_t)(~(value))))
22610 #define SPI_TOG_PUSHR(base, value) (BME_XOR32(&SPI_PUSHR_REG(base), (uint32_t)(value)))
22611 /*@}*/
22612 
22613 /*
22614  * Constants & macros for individual SPI_PUSHR bitfields
22615  */
22616 
22617 /*!
22618  * @name Register SPI_PUSHR, field TXDATA[15:0] (RW)
22619  *
22620  * Holds SPI data to be transferred according to the associated SPI command.
22621  */
22622 /*@{*/
22623 /*! @brief Read current value of the SPI_PUSHR_TXDATA field. */
22624 #define SPI_RD_PUSHR_TXDATA(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_TXDATA_MASK) >> SPI_PUSHR_TXDATA_SHIFT)
22625 #define SPI_BRD_PUSHR_TXDATA(base) (BME_UBFX32(&SPI_PUSHR_REG(base), SPI_PUSHR_TXDATA_SHIFT, SPI_PUSHR_TXDATA_WIDTH))
22626 
22627 /*! @brief Set the TXDATA field to a new value. */
22628 #define SPI_WR_PUSHR_TXDATA(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_TXDATA_MASK, SPI_PUSHR_TXDATA(value)))
22629 #define SPI_BWR_PUSHR_TXDATA(base, value) (BME_BFI32(&SPI_PUSHR_REG(base), ((uint32_t)(value) << SPI_PUSHR_TXDATA_SHIFT), SPI_PUSHR_TXDATA_SHIFT, SPI_PUSHR_TXDATA_WIDTH))
22630 /*@}*/
22631 
22632 /*!
22633  * @name Register SPI_PUSHR, field PCS[19:16] (RW)
22634  *
22635  * Select which PCS signals are to be asserted for the transfer. Refer to the
22636  * chip-specific SPI information for the number of PCS signals used in this MCU.
22637  *
22638  * Values:
22639  * - 0b0000 - Negate the PCS[x] signal
22640  * - 0b0001 - Assert the PCS[x] signal.
22641  */
22642 /*@{*/
22643 /*! @brief Read current value of the SPI_PUSHR_PCS field. */
22644 #define SPI_RD_PUSHR_PCS(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_PCS_MASK) >> SPI_PUSHR_PCS_SHIFT)
22645 #define SPI_BRD_PUSHR_PCS(base) (BME_UBFX32(&SPI_PUSHR_REG(base), SPI_PUSHR_PCS_SHIFT, SPI_PUSHR_PCS_WIDTH))
22646 
22647 /*! @brief Set the PCS field to a new value. */
22648 #define SPI_WR_PUSHR_PCS(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_PCS_MASK, SPI_PUSHR_PCS(value)))
22649 #define SPI_BWR_PUSHR_PCS(base, value) (BME_BFI32(&SPI_PUSHR_REG(base), ((uint32_t)(value) << SPI_PUSHR_PCS_SHIFT), SPI_PUSHR_PCS_SHIFT, SPI_PUSHR_PCS_WIDTH))
22650 /*@}*/
22651 
22652 /*!
22653  * @name Register SPI_PUSHR, field CTCNT[26] (RW)
22654  *
22655  * Clears the TCNT field in the TCR register. The TCNT field is cleared before
22656  * the module starts transmitting the current SPI frame.
22657  *
22658  * Values:
22659  * - 0b0 - Do not clear the TCR[TCNT] field.
22660  * - 0b1 - Clear the TCR[TCNT] field.
22661  */
22662 /*@{*/
22663 /*! @brief Read current value of the SPI_PUSHR_CTCNT field. */
22664 #define SPI_RD_PUSHR_CTCNT(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CTCNT_MASK) >> SPI_PUSHR_CTCNT_SHIFT)
22665 #define SPI_BRD_PUSHR_CTCNT(base) (BME_UBFX32(&SPI_PUSHR_REG(base), SPI_PUSHR_CTCNT_SHIFT, SPI_PUSHR_CTCNT_WIDTH))
22666 
22667 /*! @brief Set the CTCNT field to a new value. */
22668 #define SPI_WR_PUSHR_CTCNT(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CTCNT_MASK, SPI_PUSHR_CTCNT(value)))
22669 #define SPI_BWR_PUSHR_CTCNT(base, value) (BME_BFI32(&SPI_PUSHR_REG(base), ((uint32_t)(value) << SPI_PUSHR_CTCNT_SHIFT), SPI_PUSHR_CTCNT_SHIFT, SPI_PUSHR_CTCNT_WIDTH))
22670 /*@}*/
22671 
22672 /*!
22673  * @name Register SPI_PUSHR, field EOQ[27] (RW)
22674  *
22675  * Host software uses this bit to signal to the module that the current SPI
22676  * transfer is the last in a queue. At the end of the transfer, the EOQF bit in the
22677  * SR is set.
22678  *
22679  * Values:
22680  * - 0b0 - The SPI data is not the last data to transfer.
22681  * - 0b1 - The SPI data is the last data to transfer.
22682  */
22683 /*@{*/
22684 /*! @brief Read current value of the SPI_PUSHR_EOQ field. */
22685 #define SPI_RD_PUSHR_EOQ(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_EOQ_MASK) >> SPI_PUSHR_EOQ_SHIFT)
22686 #define SPI_BRD_PUSHR_EOQ(base) (BME_UBFX32(&SPI_PUSHR_REG(base), SPI_PUSHR_EOQ_SHIFT, SPI_PUSHR_EOQ_WIDTH))
22687 
22688 /*! @brief Set the EOQ field to a new value. */
22689 #define SPI_WR_PUSHR_EOQ(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_EOQ_MASK, SPI_PUSHR_EOQ(value)))
22690 #define SPI_BWR_PUSHR_EOQ(base, value) (BME_BFI32(&SPI_PUSHR_REG(base), ((uint32_t)(value) << SPI_PUSHR_EOQ_SHIFT), SPI_PUSHR_EOQ_SHIFT, SPI_PUSHR_EOQ_WIDTH))
22691 /*@}*/
22692 
22693 /*!
22694  * @name Register SPI_PUSHR, field CTAS[30:28] (RW)
22695  *
22696  * Selects which CTAR to use in master mode to specify the transfer attributes
22697  * for the associated SPI frame. In SPI Slave mode, CTAR0 is used. See the chip
22698  * configuration details to determine how many CTARs this device has. You should
22699  * not program a value in this field for a register that is not present.
22700  *
22701  * Values:
22702  * - 0b000 - CTAR0
22703  * - 0b001 - CTAR1
22704  * - 0b010 - Reserved
22705  * - 0b011 - Reserved
22706  * - 0b100 - Reserved
22707  * - 0b101 - Reserved
22708  * - 0b110 - Reserved
22709  * - 0b111 - Reserved
22710  */
22711 /*@{*/
22712 /*! @brief Read current value of the SPI_PUSHR_CTAS field. */
22713 #define SPI_RD_PUSHR_CTAS(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CTAS_MASK) >> SPI_PUSHR_CTAS_SHIFT)
22714 #define SPI_BRD_PUSHR_CTAS(base) (BME_UBFX32(&SPI_PUSHR_REG(base), SPI_PUSHR_CTAS_SHIFT, SPI_PUSHR_CTAS_WIDTH))
22715 
22716 /*! @brief Set the CTAS field to a new value. */
22717 #define SPI_WR_PUSHR_CTAS(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CTAS_MASK, SPI_PUSHR_CTAS(value)))
22718 #define SPI_BWR_PUSHR_CTAS(base, value) (BME_BFI32(&SPI_PUSHR_REG(base), ((uint32_t)(value) << SPI_PUSHR_CTAS_SHIFT), SPI_PUSHR_CTAS_SHIFT, SPI_PUSHR_CTAS_WIDTH))
22719 /*@}*/
22720 
22721 /*!
22722  * @name Register SPI_PUSHR, field CONT[31] (RW)
22723  *
22724  * Selects a continuous selection format. The bit is used in SPI Master mode.
22725  * The bit enables the selected PCS signals to remain asserted between transfers.
22726  *
22727  * Values:
22728  * - 0b0 - Return PCSn signals to their inactive state between transfers.
22729  * - 0b1 - Keep PCSn signals asserted between transfers.
22730  */
22731 /*@{*/
22732 /*! @brief Read current value of the SPI_PUSHR_CONT field. */
22733 #define SPI_RD_PUSHR_CONT(base) ((SPI_PUSHR_REG(base) & SPI_PUSHR_CONT_MASK) >> SPI_PUSHR_CONT_SHIFT)
22734 #define SPI_BRD_PUSHR_CONT(base) (BME_UBFX32(&SPI_PUSHR_REG(base), SPI_PUSHR_CONT_SHIFT, SPI_PUSHR_CONT_WIDTH))
22735 
22736 /*! @brief Set the CONT field to a new value. */
22737 #define SPI_WR_PUSHR_CONT(base, value) (SPI_RMW_PUSHR(base, SPI_PUSHR_CONT_MASK, SPI_PUSHR_CONT(value)))
22738 #define SPI_BWR_PUSHR_CONT(base, value) (BME_BFI32(&SPI_PUSHR_REG(base), ((uint32_t)(value) << SPI_PUSHR_CONT_SHIFT), SPI_PUSHR_CONT_SHIFT, SPI_PUSHR_CONT_WIDTH))
22739 /*@}*/
22740 
22741 /*******************************************************************************
22742  * SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode
22743  ******************************************************************************/
22744 
22745 /*!
22746  * @brief SPI_PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode (RW)
22747  *
22748  * Reset value: 0x00000000U
22749  *
22750  * Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access
22751  * to PUSHR transfers all 32 bits to the TX FIFO. In master mode, the register
22752  * transfers 16 bits of data and 16 bits of command information to the TX FIFO. In
22753  * slave mode, all 32 register bits can be used as data, supporting up to 32-bit
22754  * SPI Frame operation.
22755  */
22756 /*!
22757  * @name Constants and macros for entire SPI_PUSHR_SLAVE register
22758  */
22759 /*@{*/
22760 #define SPI_RD_PUSHR_SLAVE(base) (SPI_PUSHR_SLAVE_REG(base))
22761 #define SPI_WR_PUSHR_SLAVE(base, value) (SPI_PUSHR_SLAVE_REG(base) = (value))
22762 #define SPI_RMW_PUSHR_SLAVE(base, mask, value) (SPI_WR_PUSHR_SLAVE(base, (SPI_RD_PUSHR_SLAVE(base) & ~(mask)) | (value)))
22763 #define SPI_SET_PUSHR_SLAVE(base, value) (BME_OR32(&SPI_PUSHR_SLAVE_REG(base), (uint32_t)(value)))
22764 #define SPI_CLR_PUSHR_SLAVE(base, value) (BME_AND32(&SPI_PUSHR_SLAVE_REG(base), (uint32_t)(~(value))))
22765 #define SPI_TOG_PUSHR_SLAVE(base, value) (BME_XOR32(&SPI_PUSHR_SLAVE_REG(base), (uint32_t)(value)))
22766 /*@}*/
22767 
22768 /*******************************************************************************
22769  * SPI_POPR - POP RX FIFO Register
22770  ******************************************************************************/
22771 
22772 /*!
22773  * @brief SPI_POPR - POP RX FIFO Register (RO)
22774  *
22775  * Reset value: 0x00000000U
22776  *
22777  * POPR is used to read the RX FIFO. Eight- or sixteen-bit read accesses to the
22778  * POPR have the same effect on the RX FIFO as 32-bit read accesses. A write to
22779  * this register will generate a Transfer Error.
22780  */
22781 /*!
22782  * @name Constants and macros for entire SPI_POPR register
22783  */
22784 /*@{*/
22785 #define SPI_RD_POPR(base)        (SPI_POPR_REG(base))
22786 /*@}*/
22787 
22788 /*******************************************************************************
22789  * SPI_TXFR0 - Transmit FIFO Registers
22790  ******************************************************************************/
22791 
22792 /*!
22793  * @brief SPI_TXFR0 - Transmit FIFO Registers (RO)
22794  *
22795  * Reset value: 0x00000000U
22796  *
22797  * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
22798  * Each register is an entry in the TX FIFO. The registers are read-only and
22799  * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
22800  * FIFO. The number of registers used to implement the TX FIFO is
22801  * device-specific. If a four-entry TX FIFO is implemented, TXFR0-TXFR3 are accessible.
22802  */
22803 /*!
22804  * @name Constants and macros for entire SPI_TXFR0 register
22805  */
22806 /*@{*/
22807 #define SPI_RD_TXFR0(base)       (SPI_TXFR0_REG(base))
22808 /*@}*/
22809 
22810 /*
22811  * Constants & macros for individual SPI_TXFR0 bitfields
22812  */
22813 
22814 /*!
22815  * @name Register SPI_TXFR0, field TXDATA[15:0] (RO)
22816  *
22817  * Contains the SPI data to be shifted out.
22818  */
22819 /*@{*/
22820 /*! @brief Read current value of the SPI_TXFR0_TXDATA field. */
22821 #define SPI_RD_TXFR0_TXDATA(base) ((SPI_TXFR0_REG(base) & SPI_TXFR0_TXDATA_MASK) >> SPI_TXFR0_TXDATA_SHIFT)
22822 #define SPI_BRD_TXFR0_TXDATA(base) (BME_UBFX32(&SPI_TXFR0_REG(base), SPI_TXFR0_TXDATA_SHIFT, SPI_TXFR0_TXDATA_WIDTH))
22823 /*@}*/
22824 
22825 /*!
22826  * @name Register SPI_TXFR0, field TXCMD_TXDATA[31:16] (RO)
22827  *
22828  * In Master mode the TXCMD field contains the command that sets the transfer
22829  * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
22830  * the SPI data to be shifted out.
22831  */
22832 /*@{*/
22833 /*! @brief Read current value of the SPI_TXFR0_TXCMD_TXDATA field. */
22834 #define SPI_RD_TXFR0_TXCMD_TXDATA(base) ((SPI_TXFR0_REG(base) & SPI_TXFR0_TXCMD_TXDATA_MASK) >> SPI_TXFR0_TXCMD_TXDATA_SHIFT)
22835 #define SPI_BRD_TXFR0_TXCMD_TXDATA(base) (BME_UBFX32(&SPI_TXFR0_REG(base), SPI_TXFR0_TXCMD_TXDATA_SHIFT, SPI_TXFR0_TXCMD_TXDATA_WIDTH))
22836 /*@}*/
22837 
22838 /*******************************************************************************
22839  * SPI_TXFR1 - Transmit FIFO Registers
22840  ******************************************************************************/
22841 
22842 /*!
22843  * @brief SPI_TXFR1 - Transmit FIFO Registers (RO)
22844  *
22845  * Reset value: 0x00000000U
22846  *
22847  * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
22848  * Each register is an entry in the TX FIFO. The registers are read-only and
22849  * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
22850  * FIFO. The number of registers used to implement the TX FIFO is
22851  * device-specific. If a four-entry TX FIFO is implemented, TXFR0-TXFR3 are accessible.
22852  */
22853 /*!
22854  * @name Constants and macros for entire SPI_TXFR1 register
22855  */
22856 /*@{*/
22857 #define SPI_RD_TXFR1(base)       (SPI_TXFR1_REG(base))
22858 /*@}*/
22859 
22860 /*
22861  * Constants & macros for individual SPI_TXFR1 bitfields
22862  */
22863 
22864 /*!
22865  * @name Register SPI_TXFR1, field TXDATA[15:0] (RO)
22866  *
22867  * Contains the SPI data to be shifted out.
22868  */
22869 /*@{*/
22870 /*! @brief Read current value of the SPI_TXFR1_TXDATA field. */
22871 #define SPI_RD_TXFR1_TXDATA(base) ((SPI_TXFR1_REG(base) & SPI_TXFR1_TXDATA_MASK) >> SPI_TXFR1_TXDATA_SHIFT)
22872 #define SPI_BRD_TXFR1_TXDATA(base) (BME_UBFX32(&SPI_TXFR1_REG(base), SPI_TXFR1_TXDATA_SHIFT, SPI_TXFR1_TXDATA_WIDTH))
22873 /*@}*/
22874 
22875 /*!
22876  * @name Register SPI_TXFR1, field TXCMD_TXDATA[31:16] (RO)
22877  *
22878  * In Master mode the TXCMD field contains the command that sets the transfer
22879  * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
22880  * the SPI data to be shifted out.
22881  */
22882 /*@{*/
22883 /*! @brief Read current value of the SPI_TXFR1_TXCMD_TXDATA field. */
22884 #define SPI_RD_TXFR1_TXCMD_TXDATA(base) ((SPI_TXFR1_REG(base) & SPI_TXFR1_TXCMD_TXDATA_MASK) >> SPI_TXFR1_TXCMD_TXDATA_SHIFT)
22885 #define SPI_BRD_TXFR1_TXCMD_TXDATA(base) (BME_UBFX32(&SPI_TXFR1_REG(base), SPI_TXFR1_TXCMD_TXDATA_SHIFT, SPI_TXFR1_TXCMD_TXDATA_WIDTH))
22886 /*@}*/
22887 
22888 /*******************************************************************************
22889  * SPI_TXFR2 - Transmit FIFO Registers
22890  ******************************************************************************/
22891 
22892 /*!
22893  * @brief SPI_TXFR2 - Transmit FIFO Registers (RO)
22894  *
22895  * Reset value: 0x00000000U
22896  *
22897  * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
22898  * Each register is an entry in the TX FIFO. The registers are read-only and
22899  * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
22900  * FIFO. The number of registers used to implement the TX FIFO is
22901  * device-specific. If a four-entry TX FIFO is implemented, TXFR0-TXFR3 are accessible.
22902  */
22903 /*!
22904  * @name Constants and macros for entire SPI_TXFR2 register
22905  */
22906 /*@{*/
22907 #define SPI_RD_TXFR2(base)       (SPI_TXFR2_REG(base))
22908 /*@}*/
22909 
22910 /*
22911  * Constants & macros for individual SPI_TXFR2 bitfields
22912  */
22913 
22914 /*!
22915  * @name Register SPI_TXFR2, field TXDATA[15:0] (RO)
22916  *
22917  * Contains the SPI data to be shifted out.
22918  */
22919 /*@{*/
22920 /*! @brief Read current value of the SPI_TXFR2_TXDATA field. */
22921 #define SPI_RD_TXFR2_TXDATA(base) ((SPI_TXFR2_REG(base) & SPI_TXFR2_TXDATA_MASK) >> SPI_TXFR2_TXDATA_SHIFT)
22922 #define SPI_BRD_TXFR2_TXDATA(base) (BME_UBFX32(&SPI_TXFR2_REG(base), SPI_TXFR2_TXDATA_SHIFT, SPI_TXFR2_TXDATA_WIDTH))
22923 /*@}*/
22924 
22925 /*!
22926  * @name Register SPI_TXFR2, field TXCMD_TXDATA[31:16] (RO)
22927  *
22928  * In Master mode the TXCMD field contains the command that sets the transfer
22929  * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
22930  * the SPI data to be shifted out.
22931  */
22932 /*@{*/
22933 /*! @brief Read current value of the SPI_TXFR2_TXCMD_TXDATA field. */
22934 #define SPI_RD_TXFR2_TXCMD_TXDATA(base) ((SPI_TXFR2_REG(base) & SPI_TXFR2_TXCMD_TXDATA_MASK) >> SPI_TXFR2_TXCMD_TXDATA_SHIFT)
22935 #define SPI_BRD_TXFR2_TXCMD_TXDATA(base) (BME_UBFX32(&SPI_TXFR2_REG(base), SPI_TXFR2_TXCMD_TXDATA_SHIFT, SPI_TXFR2_TXCMD_TXDATA_WIDTH))
22936 /*@}*/
22937 
22938 /*******************************************************************************
22939  * SPI_TXFR3 - Transmit FIFO Registers
22940  ******************************************************************************/
22941 
22942 /*!
22943  * @brief SPI_TXFR3 - Transmit FIFO Registers (RO)
22944  *
22945  * Reset value: 0x00000000U
22946  *
22947  * TXFRn registers provide visibility into the TX FIFO for debugging purposes.
22948  * Each register is an entry in the TX FIFO. The registers are read-only and
22949  * cannot be modified. Reading the TXFRx registers does not alter the state of the TX
22950  * FIFO. The number of registers used to implement the TX FIFO is
22951  * device-specific. If a four-entry TX FIFO is implemented, TXFR0-TXFR3 are accessible.
22952  */
22953 /*!
22954  * @name Constants and macros for entire SPI_TXFR3 register
22955  */
22956 /*@{*/
22957 #define SPI_RD_TXFR3(base)       (SPI_TXFR3_REG(base))
22958 /*@}*/
22959 
22960 /*
22961  * Constants & macros for individual SPI_TXFR3 bitfields
22962  */
22963 
22964 /*!
22965  * @name Register SPI_TXFR3, field TXDATA[15:0] (RO)
22966  *
22967  * Contains the SPI data to be shifted out.
22968  */
22969 /*@{*/
22970 /*! @brief Read current value of the SPI_TXFR3_TXDATA field. */
22971 #define SPI_RD_TXFR3_TXDATA(base) ((SPI_TXFR3_REG(base) & SPI_TXFR3_TXDATA_MASK) >> SPI_TXFR3_TXDATA_SHIFT)
22972 #define SPI_BRD_TXFR3_TXDATA(base) (BME_UBFX32(&SPI_TXFR3_REG(base), SPI_TXFR3_TXDATA_SHIFT, SPI_TXFR3_TXDATA_WIDTH))
22973 /*@}*/
22974 
22975 /*!
22976  * @name Register SPI_TXFR3, field TXCMD_TXDATA[31:16] (RO)
22977  *
22978  * In Master mode the TXCMD field contains the command that sets the transfer
22979  * attributes for the SPI data. In Slave mode, the TXDATA contains 16 MSB bits of
22980  * the SPI data to be shifted out.
22981  */
22982 /*@{*/
22983 /*! @brief Read current value of the SPI_TXFR3_TXCMD_TXDATA field. */
22984 #define SPI_RD_TXFR3_TXCMD_TXDATA(base) ((SPI_TXFR3_REG(base) & SPI_TXFR3_TXCMD_TXDATA_MASK) >> SPI_TXFR3_TXCMD_TXDATA_SHIFT)
22985 #define SPI_BRD_TXFR3_TXCMD_TXDATA(base) (BME_UBFX32(&SPI_TXFR3_REG(base), SPI_TXFR3_TXCMD_TXDATA_SHIFT, SPI_TXFR3_TXCMD_TXDATA_WIDTH))
22986 /*@}*/
22987 
22988 /*******************************************************************************
22989  * SPI_RXFR0 - Receive FIFO Registers
22990  ******************************************************************************/
22991 
22992 /*!
22993  * @brief SPI_RXFR0 - Receive FIFO Registers (RO)
22994  *
22995  * Reset value: 0x00000000U
22996  *
22997  * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
22998  * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
22999  * RXFRx registers does not alter the state of the RX FIFO. The number of
23000  * registers used to implement the RX FIFO is device-specific. For example, if a
23001  * four-entry RX FIFO is implemented, RXFR0-RXFR3 are used.
23002  */
23003 /*!
23004  * @name Constants and macros for entire SPI_RXFR0 register
23005  */
23006 /*@{*/
23007 #define SPI_RD_RXFR0(base)       (SPI_RXFR0_REG(base))
23008 /*@}*/
23009 
23010 /*******************************************************************************
23011  * SPI_RXFR1 - Receive FIFO Registers
23012  ******************************************************************************/
23013 
23014 /*!
23015  * @brief SPI_RXFR1 - Receive FIFO Registers (RO)
23016  *
23017  * Reset value: 0x00000000U
23018  *
23019  * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
23020  * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
23021  * RXFRx registers does not alter the state of the RX FIFO. The number of
23022  * registers used to implement the RX FIFO is device-specific. For example, if a
23023  * four-entry RX FIFO is implemented, RXFR0-RXFR3 are used.
23024  */
23025 /*!
23026  * @name Constants and macros for entire SPI_RXFR1 register
23027  */
23028 /*@{*/
23029 #define SPI_RD_RXFR1(base)       (SPI_RXFR1_REG(base))
23030 /*@}*/
23031 
23032 /*******************************************************************************
23033  * SPI_RXFR2 - Receive FIFO Registers
23034  ******************************************************************************/
23035 
23036 /*!
23037  * @brief SPI_RXFR2 - Receive FIFO Registers (RO)
23038  *
23039  * Reset value: 0x00000000U
23040  *
23041  * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
23042  * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
23043  * RXFRx registers does not alter the state of the RX FIFO. The number of
23044  * registers used to implement the RX FIFO is device-specific. For example, if a
23045  * four-entry RX FIFO is implemented, RXFR0-RXFR3 are used.
23046  */
23047 /*!
23048  * @name Constants and macros for entire SPI_RXFR2 register
23049  */
23050 /*@{*/
23051 #define SPI_RD_RXFR2(base)       (SPI_RXFR2_REG(base))
23052 /*@}*/
23053 
23054 /*******************************************************************************
23055  * SPI_RXFR3 - Receive FIFO Registers
23056  ******************************************************************************/
23057 
23058 /*!
23059  * @brief SPI_RXFR3 - Receive FIFO Registers (RO)
23060  *
23061  * Reset value: 0x00000000U
23062  *
23063  * RXFRn provide visibility into the RX FIFO for debugging purposes. Each
23064  * register is an entry in the RX FIFO. The RXFR registers are read-only. Reading the
23065  * RXFRx registers does not alter the state of the RX FIFO. The number of
23066  * registers used to implement the RX FIFO is device-specific. For example, if a
23067  * four-entry RX FIFO is implemented, RXFR0-RXFR3 are used.
23068  */
23069 /*!
23070  * @name Constants and macros for entire SPI_RXFR3 register
23071  */
23072 /*@{*/
23073 #define SPI_RD_RXFR3(base)       (SPI_RXFR3_REG(base))
23074 /*@}*/
23075 
23076 /*
23077  * MKW40Z4 TPM
23078  *
23079  * Timer/PWM Module
23080  *
23081  * Registers defined in this header file:
23082  * - TPM_SC - Status and Control
23083  * - TPM_CNT - Counter
23084  * - TPM_MOD - Modulo
23085  * - TPM_CnSC - Channel (n) Status and Control
23086  * - TPM_CnV - Channel (n) Value
23087  * - TPM_STATUS - Capture and Compare Status
23088  * - TPM_COMBINE - Combine Channel Register
23089  * - TPM_FILTER - Filter Control
23090  * - TPM_QDCTRL - Quadrature Decoder Control and Status
23091  * - TPM_CONF - Configuration
23092  */
23093 
23094 #define TPM_INSTANCE_COUNT (3U) /*!< Number of instances of the TPM module. */
23095 #define TPM0_IDX (0U) /*!< Instance number for TPM0. */
23096 #define TPM1_IDX (1U) /*!< Instance number for TPM1. */
23097 #define TPM2_IDX (2U) /*!< Instance number for TPM2. */
23098 
23099 /*******************************************************************************
23100  * TPM_SC - Status and Control
23101  ******************************************************************************/
23102 
23103 /*!
23104  * @brief TPM_SC - Status and Control (RW)
23105  *
23106  * Reset value: 0x00000000U
23107  *
23108  * SC contains the overflow status flag and control bits used to configure the
23109  * interrupt enable, module configuration and prescaler factor. These controls
23110  * relate to all channels within this module.
23111  */
23112 /*!
23113  * @name Constants and macros for entire TPM_SC register
23114  */
23115 /*@{*/
23116 #define TPM_RD_SC(base)          (TPM_SC_REG(base))
23117 #define TPM_WR_SC(base, value)   (TPM_SC_REG(base) = (value))
23118 #define TPM_RMW_SC(base, mask, value) (TPM_WR_SC(base, (TPM_RD_SC(base) & ~(mask)) | (value)))
23119 #define TPM_SET_SC(base, value)  (BME_OR32(&TPM_SC_REG(base), (uint32_t)(value)))
23120 #define TPM_CLR_SC(base, value)  (BME_AND32(&TPM_SC_REG(base), (uint32_t)(~(value))))
23121 #define TPM_TOG_SC(base, value)  (BME_XOR32(&TPM_SC_REG(base), (uint32_t)(value)))
23122 /*@}*/
23123 
23124 /*
23125  * Constants & macros for individual TPM_SC bitfields
23126  */
23127 
23128 /*!
23129  * @name Register TPM_SC, field PS[2:0] (RW)
23130  *
23131  * Selects one of 8 division factors for the clock mode selected by CMOD. This
23132  * field is write protected. It can be written only when the counter is disabled.
23133  *
23134  * Values:
23135  * - 0b000 - Divide by 1
23136  * - 0b001 - Divide by 2
23137  * - 0b010 - Divide by 4
23138  * - 0b011 - Divide by 8
23139  * - 0b100 - Divide by 16
23140  * - 0b101 - Divide by 32
23141  * - 0b110 - Divide by 64
23142  * - 0b111 - Divide by 128
23143  */
23144 /*@{*/
23145 /*! @brief Read current value of the TPM_SC_PS field. */
23146 #define TPM_RD_SC_PS(base)   ((TPM_SC_REG(base) & TPM_SC_PS_MASK) >> TPM_SC_PS_SHIFT)
23147 #define TPM_BRD_SC_PS(base)  (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_PS_SHIFT, TPM_SC_PS_WIDTH))
23148 
23149 /*! @brief Set the PS field to a new value. */
23150 #define TPM_WR_SC_PS(base, value) (TPM_RMW_SC(base, (TPM_SC_PS_MASK | TPM_SC_TOF_MASK), TPM_SC_PS(value)))
23151 #define TPM_BWR_SC_PS(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_PS_SHIFT), TPM_SC_PS_SHIFT, TPM_SC_PS_WIDTH))
23152 /*@}*/
23153 
23154 /*!
23155  * @name Register TPM_SC, field CMOD[4:3] (RW)
23156  *
23157  * Selects the TPM counter clock modes. When disabling the counter, this field
23158  * remain set until acknolwedged in the TPM clock domain.
23159  *
23160  * Values:
23161  * - 0b00 - TPM counter is disabled
23162  * - 0b01 - TPM counter increments on every TPM counter clock
23163  * - 0b10 - TPM counter increments on rising edge of TPM_EXTCLK synchronized to
23164  *     the TPM counter clock
23165  * - 0b11 - Reserved.
23166  */
23167 /*@{*/
23168 /*! @brief Read current value of the TPM_SC_CMOD field. */
23169 #define TPM_RD_SC_CMOD(base) ((TPM_SC_REG(base) & TPM_SC_CMOD_MASK) >> TPM_SC_CMOD_SHIFT)
23170 #define TPM_BRD_SC_CMOD(base) (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_CMOD_SHIFT, TPM_SC_CMOD_WIDTH))
23171 
23172 /*! @brief Set the CMOD field to a new value. */
23173 #define TPM_WR_SC_CMOD(base, value) (TPM_RMW_SC(base, (TPM_SC_CMOD_MASK | TPM_SC_TOF_MASK), TPM_SC_CMOD(value)))
23174 #define TPM_BWR_SC_CMOD(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_CMOD_SHIFT), TPM_SC_CMOD_SHIFT, TPM_SC_CMOD_WIDTH))
23175 /*@}*/
23176 
23177 /*!
23178  * @name Register TPM_SC, field CPWMS[5] (RW)
23179  *
23180  * Selects CPWM mode. This mode configures the TPM to operate in up-down
23181  * counting mode. This field is write protected. It can be written only when the counter
23182  * is disabled.
23183  *
23184  * Values:
23185  * - 0b0 - TPM counter operates in up counting mode.
23186  * - 0b1 - TPM counter operates in up-down counting mode.
23187  */
23188 /*@{*/
23189 /*! @brief Read current value of the TPM_SC_CPWMS field. */
23190 #define TPM_RD_SC_CPWMS(base) ((TPM_SC_REG(base) & TPM_SC_CPWMS_MASK) >> TPM_SC_CPWMS_SHIFT)
23191 #define TPM_BRD_SC_CPWMS(base) (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_CPWMS_SHIFT, TPM_SC_CPWMS_WIDTH))
23192 
23193 /*! @brief Set the CPWMS field to a new value. */
23194 #define TPM_WR_SC_CPWMS(base, value) (TPM_RMW_SC(base, (TPM_SC_CPWMS_MASK | TPM_SC_TOF_MASK), TPM_SC_CPWMS(value)))
23195 #define TPM_BWR_SC_CPWMS(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_CPWMS_SHIFT), TPM_SC_CPWMS_SHIFT, TPM_SC_CPWMS_WIDTH))
23196 /*@}*/
23197 
23198 /*!
23199  * @name Register TPM_SC, field TOIE[6] (RW)
23200  *
23201  * Enables TPM overflow interrupts.
23202  *
23203  * Values:
23204  * - 0b0 - Disable TOF interrupts. Use software polling or DMA request.
23205  * - 0b1 - Enable TOF interrupts. An interrupt is generated when TOF equals one.
23206  */
23207 /*@{*/
23208 /*! @brief Read current value of the TPM_SC_TOIE field. */
23209 #define TPM_RD_SC_TOIE(base) ((TPM_SC_REG(base) & TPM_SC_TOIE_MASK) >> TPM_SC_TOIE_SHIFT)
23210 #define TPM_BRD_SC_TOIE(base) (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_TOIE_SHIFT, TPM_SC_TOIE_WIDTH))
23211 
23212 /*! @brief Set the TOIE field to a new value. */
23213 #define TPM_WR_SC_TOIE(base, value) (TPM_RMW_SC(base, (TPM_SC_TOIE_MASK | TPM_SC_TOF_MASK), TPM_SC_TOIE(value)))
23214 #define TPM_BWR_SC_TOIE(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_TOIE_SHIFT), TPM_SC_TOIE_SHIFT, TPM_SC_TOIE_WIDTH))
23215 /*@}*/
23216 
23217 /*!
23218  * @name Register TPM_SC, field TOF[7] (W1C)
23219  *
23220  * Set by hardware when the TPM counter equals the value in the MOD register and
23221  * increments. Writing a 1 to TOF clears it. Writing a 0 to TOF has no effect.
23222  * If another TPM overflow occurs between the flag setting and the flag clearing,
23223  * the write operation has no effect; therefore, TOF remains set indicating
23224  * another overflow has occurred. In this case a TOF interrupt request is not lost due
23225  * to a delay in clearing the previous TOF.
23226  *
23227  * Values:
23228  * - 0b0 - TPM counter has not overflowed.
23229  * - 0b1 - TPM counter has overflowed.
23230  */
23231 /*@{*/
23232 /*! @brief Read current value of the TPM_SC_TOF field. */
23233 #define TPM_RD_SC_TOF(base)  ((TPM_SC_REG(base) & TPM_SC_TOF_MASK) >> TPM_SC_TOF_SHIFT)
23234 #define TPM_BRD_SC_TOF(base) (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_TOF_SHIFT, TPM_SC_TOF_WIDTH))
23235 
23236 /*! @brief Set the TOF field to a new value. */
23237 #define TPM_WR_SC_TOF(base, value) (TPM_RMW_SC(base, TPM_SC_TOF_MASK, TPM_SC_TOF(value)))
23238 #define TPM_BWR_SC_TOF(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_TOF_SHIFT), TPM_SC_TOF_SHIFT, TPM_SC_TOF_WIDTH))
23239 /*@}*/
23240 
23241 /*!
23242  * @name Register TPM_SC, field DMA[8] (RW)
23243  *
23244  * Enables DMA transfers for the overflow flag.
23245  *
23246  * Values:
23247  * - 0b0 - Disables DMA transfers.
23248  * - 0b1 - Enables DMA transfers.
23249  */
23250 /*@{*/
23251 /*! @brief Read current value of the TPM_SC_DMA field. */
23252 #define TPM_RD_SC_DMA(base)  ((TPM_SC_REG(base) & TPM_SC_DMA_MASK) >> TPM_SC_DMA_SHIFT)
23253 #define TPM_BRD_SC_DMA(base) (BME_UBFX32(&TPM_SC_REG(base), TPM_SC_DMA_SHIFT, TPM_SC_DMA_WIDTH))
23254 
23255 /*! @brief Set the DMA field to a new value. */
23256 #define TPM_WR_SC_DMA(base, value) (TPM_RMW_SC(base, (TPM_SC_DMA_MASK | TPM_SC_TOF_MASK), TPM_SC_DMA(value)))
23257 #define TPM_BWR_SC_DMA(base, value) (BME_BFI32(&TPM_SC_REG(base), ((uint32_t)(value) << TPM_SC_DMA_SHIFT), TPM_SC_DMA_SHIFT, TPM_SC_DMA_WIDTH))
23258 /*@}*/
23259 
23260 /*******************************************************************************
23261  * TPM_CNT - Counter
23262  ******************************************************************************/
23263 
23264 /*!
23265  * @brief TPM_CNT - Counter (RW)
23266  *
23267  * Reset value: 0x00000000U
23268  *
23269  * The CNT register contains the TPM counter value. Reset clears the CNT
23270  * register. Writing any value to COUNT also clears the counter. When debug is active,
23271  * the TPM counter does not increment unless configured otherwise. Reading the CNT
23272  * register adds two wait states to the register access due to synchronization
23273  * delays.
23274  */
23275 /*!
23276  * @name Constants and macros for entire TPM_CNT register
23277  */
23278 /*@{*/
23279 #define TPM_RD_CNT(base)         (TPM_CNT_REG(base))
23280 #define TPM_WR_CNT(base, value)  (TPM_CNT_REG(base) = (value))
23281 #define TPM_RMW_CNT(base, mask, value) (TPM_WR_CNT(base, (TPM_RD_CNT(base) & ~(mask)) | (value)))
23282 #define TPM_SET_CNT(base, value) (BME_OR32(&TPM_CNT_REG(base), (uint32_t)(value)))
23283 #define TPM_CLR_CNT(base, value) (BME_AND32(&TPM_CNT_REG(base), (uint32_t)(~(value))))
23284 #define TPM_TOG_CNT(base, value) (BME_XOR32(&TPM_CNT_REG(base), (uint32_t)(value)))
23285 /*@}*/
23286 
23287 /*
23288  * Constants & macros for individual TPM_CNT bitfields
23289  */
23290 
23291 /*!
23292  * @name Register TPM_CNT, field COUNT[15:0] (RW)
23293  */
23294 /*@{*/
23295 /*! @brief Read current value of the TPM_CNT_COUNT field. */
23296 #define TPM_RD_CNT_COUNT(base) ((TPM_CNT_REG(base) & TPM_CNT_COUNT_MASK) >> TPM_CNT_COUNT_SHIFT)
23297 #define TPM_BRD_CNT_COUNT(base) (BME_UBFX32(&TPM_CNT_REG(base), TPM_CNT_COUNT_SHIFT, TPM_CNT_COUNT_WIDTH))
23298 
23299 /*! @brief Set the COUNT field to a new value. */
23300 #define TPM_WR_CNT_COUNT(base, value) (TPM_RMW_CNT(base, TPM_CNT_COUNT_MASK, TPM_CNT_COUNT(value)))
23301 #define TPM_BWR_CNT_COUNT(base, value) (BME_BFI32(&TPM_CNT_REG(base), ((uint32_t)(value) << TPM_CNT_COUNT_SHIFT), TPM_CNT_COUNT_SHIFT, TPM_CNT_COUNT_WIDTH))
23302 /*@}*/
23303 
23304 /*******************************************************************************
23305  * TPM_MOD - Modulo
23306  ******************************************************************************/
23307 
23308 /*!
23309  * @brief TPM_MOD - Modulo (RW)
23310  *
23311  * Reset value: 0x0000FFFFU
23312  *
23313  * The Modulo register contains the modulo value for the TPM counter. When the
23314  * TPM counter reaches the modulo value and increments, the overflow flag (TOF) is
23315  * set and the next value of TPM counter depends on the selected counting method
23316  * (see CounterThe TPM has a 16-bit counter that is used by the channels either
23317  * for input or output modes. ). Writing to the MOD register latches the value
23318  * into a buffer. The MOD register is updated with the value of its write buffer
23319  * according to MOD Register Update . Additional writes to the MOD write buffer are
23320  * ignored until the register has been updated. It is recommended to initialize
23321  * the TPM counter (write to CNT) before writing to the MOD register to avoid
23322  * confusion about when the first counter overflow will occur.
23323  */
23324 /*!
23325  * @name Constants and macros for entire TPM_MOD register
23326  */
23327 /*@{*/
23328 #define TPM_RD_MOD(base)         (TPM_MOD_REG(base))
23329 #define TPM_WR_MOD(base, value)  (TPM_MOD_REG(base) = (value))
23330 #define TPM_RMW_MOD(base, mask, value) (TPM_WR_MOD(base, (TPM_RD_MOD(base) & ~(mask)) | (value)))
23331 #define TPM_SET_MOD(base, value) (BME_OR32(&TPM_MOD_REG(base), (uint32_t)(value)))
23332 #define TPM_CLR_MOD(base, value) (BME_AND32(&TPM_MOD_REG(base), (uint32_t)(~(value))))
23333 #define TPM_TOG_MOD(base, value) (BME_XOR32(&TPM_MOD_REG(base), (uint32_t)(value)))
23334 /*@}*/
23335 
23336 /*
23337  * Constants & macros for individual TPM_MOD bitfields
23338  */
23339 
23340 /*!
23341  * @name Register TPM_MOD, field MOD[15:0] (RW)
23342  *
23343  * This field must be written with single 16-bit or 32-bit access.
23344  */
23345 /*@{*/
23346 /*! @brief Read current value of the TPM_MOD_MOD field. */
23347 #define TPM_RD_MOD_MOD(base) ((TPM_MOD_REG(base) & TPM_MOD_MOD_MASK) >> TPM_MOD_MOD_SHIFT)
23348 #define TPM_BRD_MOD_MOD(base) (BME_UBFX32(&TPM_MOD_REG(base), TPM_MOD_MOD_SHIFT, TPM_MOD_MOD_WIDTH))
23349 
23350 /*! @brief Set the MOD field to a new value. */
23351 #define TPM_WR_MOD_MOD(base, value) (TPM_RMW_MOD(base, TPM_MOD_MOD_MASK, TPM_MOD_MOD(value)))
23352 #define TPM_BWR_MOD_MOD(base, value) (BME_BFI32(&TPM_MOD_REG(base), ((uint32_t)(value) << TPM_MOD_MOD_SHIFT), TPM_MOD_MOD_SHIFT, TPM_MOD_MOD_WIDTH))
23353 /*@}*/
23354 
23355 /*******************************************************************************
23356  * TPM_CnSC - Channel (n) Status and Control
23357  ******************************************************************************/
23358 
23359 /*!
23360  * @brief TPM_CnSC - Channel (n) Status and Control (RW)
23361  *
23362  * Reset value: 0x00000000U
23363  *
23364  * CnSC contains the channel-interrupt-status flag and control bits used to
23365  * configure the interrupt enable, channel configuration, and pin function. When
23366  * switching from one channel mode to a different channel mode, the channel must
23367  * first be disabled and this must be acknowledged in the TPM counter clock domain.
23368  * Mode, Edge, and Level Selection CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration
23369  * X 00 00 None Channel disabled X 01 00 Software compare Pin not used for TPM 0
23370  * 00 01 Input capture Capture on Rising Edge Only 10 Capture on Falling Edge
23371  * Only 11 Capture on Rising or Falling Edge 01 01 Output compare Toggle Output on
23372  * match 10 Clear Output on match 11 Set Output on match 10 10 Edge-aligned PWM
23373  * High-true pulses (clear Output on match, set Output on reload) X1 Low-true
23374  * pulses (set Output on match, clear Output on reload) 11 10 Output compare Pulse
23375  * Output low on match 01 Pulse Output high on match 1 10 10 Center-aligned PWM
23376  * High-true pulses (clear Output on match-up, set Output on match-down) 01 Low-true
23377  * pulses (set Output on match-up, clear Output on match-down)
23378  */
23379 /*!
23380  * @name Constants and macros for entire TPM_CnSC register
23381  */
23382 /*@{*/
23383 #define TPM_RD_CnSC(base, index) (TPM_CnSC_REG(base, index))
23384 #define TPM_WR_CnSC(base, index, value) (TPM_CnSC_REG(base, index) = (value))
23385 #define TPM_RMW_CnSC(base, index, mask, value) (TPM_WR_CnSC(base, index, (TPM_RD_CnSC(base, index) & ~(mask)) | (value)))
23386 #define TPM_SET_CnSC(base, index, value) (BME_OR32(&TPM_CnSC_REG(base, index), (uint32_t)(value)))
23387 #define TPM_CLR_CnSC(base, index, value) (BME_AND32(&TPM_CnSC_REG(base, index), (uint32_t)(~(value))))
23388 #define TPM_TOG_CnSC(base, index, value) (BME_XOR32(&TPM_CnSC_REG(base, index), (uint32_t)(value)))
23389 /*@}*/
23390 
23391 /*
23392  * Constants & macros for individual TPM_CnSC bitfields
23393  */
23394 
23395 /*!
23396  * @name Register TPM_CnSC, field DMA[0] (RW)
23397  *
23398  * Enables DMA transfers for the channel.
23399  *
23400  * Values:
23401  * - 0b0 - Disable DMA transfers.
23402  * - 0b1 - Enable DMA transfers.
23403  */
23404 /*@{*/
23405 /*! @brief Read current value of the TPM_CnSC_DMA field. */
23406 #define TPM_RD_CnSC_DMA(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_DMA_MASK) >> TPM_CnSC_DMA_SHIFT)
23407 #define TPM_BRD_CnSC_DMA(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_DMA_SHIFT, TPM_CnSC_DMA_WIDTH))
23408 
23409 /*! @brief Set the DMA field to a new value. */
23410 #define TPM_WR_CnSC_DMA(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_DMA_MASK | TPM_CnSC_CHF_MASK), TPM_CnSC_DMA(value)))
23411 #define TPM_BWR_CnSC_DMA(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(value) << TPM_CnSC_DMA_SHIFT), TPM_CnSC_DMA_SHIFT, TPM_CnSC_DMA_WIDTH))
23412 /*@}*/
23413 
23414 /*!
23415  * @name Register TPM_CnSC, field ELSA[2] (RW)
23416  *
23417  * The functionality of ELSB and ELSA depends on the channel mode. When a
23418  * channel is disabled, this field will not change state until acknowledged in the TPM
23419  * counter clock domain.
23420  */
23421 /*@{*/
23422 /*! @brief Read current value of the TPM_CnSC_ELSA field. */
23423 #define TPM_RD_CnSC_ELSA(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_ELSA_MASK) >> TPM_CnSC_ELSA_SHIFT)
23424 #define TPM_BRD_CnSC_ELSA(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_ELSA_SHIFT, TPM_CnSC_ELSA_WIDTH))
23425 
23426 /*! @brief Set the ELSA field to a new value. */
23427 #define TPM_WR_CnSC_ELSA(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_ELSA_MASK | TPM_CnSC_CHF_MASK), TPM_CnSC_ELSA(value)))
23428 #define TPM_BWR_CnSC_ELSA(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(value) << TPM_CnSC_ELSA_SHIFT), TPM_CnSC_ELSA_SHIFT, TPM_CnSC_ELSA_WIDTH))
23429 /*@}*/
23430 
23431 /*!
23432  * @name Register TPM_CnSC, field ELSB[3] (RW)
23433  *
23434  * The functionality of ELSB and ELSA depends on the channel mode. When a
23435  * channel is disabled, this field will not change state until acknowledged in the TPM
23436  * counter clock domain.
23437  */
23438 /*@{*/
23439 /*! @brief Read current value of the TPM_CnSC_ELSB field. */
23440 #define TPM_RD_CnSC_ELSB(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_ELSB_MASK) >> TPM_CnSC_ELSB_SHIFT)
23441 #define TPM_BRD_CnSC_ELSB(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_ELSB_SHIFT, TPM_CnSC_ELSB_WIDTH))
23442 
23443 /*! @brief Set the ELSB field to a new value. */
23444 #define TPM_WR_CnSC_ELSB(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_ELSB_MASK | TPM_CnSC_CHF_MASK), TPM_CnSC_ELSB(value)))
23445 #define TPM_BWR_CnSC_ELSB(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(value) << TPM_CnSC_ELSB_SHIFT), TPM_CnSC_ELSB_SHIFT, TPM_CnSC_ELSB_WIDTH))
23446 /*@}*/
23447 
23448 /*!
23449  * @name Register TPM_CnSC, field MSA[4] (RW)
23450  *
23451  * Used for further selections in the channel logic. Its functionality is
23452  * dependent on the channel mode. When a channel is disabled, this field will not
23453  * change state until acknowledged in the TPM counter clock domain.
23454  */
23455 /*@{*/
23456 /*! @brief Read current value of the TPM_CnSC_MSA field. */
23457 #define TPM_RD_CnSC_MSA(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_MSA_MASK) >> TPM_CnSC_MSA_SHIFT)
23458 #define TPM_BRD_CnSC_MSA(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_MSA_SHIFT, TPM_CnSC_MSA_WIDTH))
23459 
23460 /*! @brief Set the MSA field to a new value. */
23461 #define TPM_WR_CnSC_MSA(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_MSA_MASK | TPM_CnSC_CHF_MASK), TPM_CnSC_MSA(value)))
23462 #define TPM_BWR_CnSC_MSA(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(value) << TPM_CnSC_MSA_SHIFT), TPM_CnSC_MSA_SHIFT, TPM_CnSC_MSA_WIDTH))
23463 /*@}*/
23464 
23465 /*!
23466  * @name Register TPM_CnSC, field MSB[5] (RW)
23467  *
23468  * Used for further selections in the channel logic. Its functionality is
23469  * dependent on the channel mode. When a channel is disabled, this field will not
23470  * change state until acknowledged in the TPM counter clock domain.
23471  */
23472 /*@{*/
23473 /*! @brief Read current value of the TPM_CnSC_MSB field. */
23474 #define TPM_RD_CnSC_MSB(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_MSB_MASK) >> TPM_CnSC_MSB_SHIFT)
23475 #define TPM_BRD_CnSC_MSB(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_MSB_SHIFT, TPM_CnSC_MSB_WIDTH))
23476 
23477 /*! @brief Set the MSB field to a new value. */
23478 #define TPM_WR_CnSC_MSB(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_MSB_MASK | TPM_CnSC_CHF_MASK), TPM_CnSC_MSB(value)))
23479 #define TPM_BWR_CnSC_MSB(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(value) << TPM_CnSC_MSB_SHIFT), TPM_CnSC_MSB_SHIFT, TPM_CnSC_MSB_WIDTH))
23480 /*@}*/
23481 
23482 /*!
23483  * @name Register TPM_CnSC, field CHIE[6] (RW)
23484  *
23485  * Enables channel interrupts.
23486  *
23487  * Values:
23488  * - 0b0 - Disable channel interrupts.
23489  * - 0b1 - Enable channel interrupts.
23490  */
23491 /*@{*/
23492 /*! @brief Read current value of the TPM_CnSC_CHIE field. */
23493 #define TPM_RD_CnSC_CHIE(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_CHIE_MASK) >> TPM_CnSC_CHIE_SHIFT)
23494 #define TPM_BRD_CnSC_CHIE(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_CHIE_SHIFT, TPM_CnSC_CHIE_WIDTH))
23495 
23496 /*! @brief Set the CHIE field to a new value. */
23497 #define TPM_WR_CnSC_CHIE(base, index, value) (TPM_RMW_CnSC(base, index, (TPM_CnSC_CHIE_MASK | TPM_CnSC_CHF_MASK), TPM_CnSC_CHIE(value)))
23498 #define TPM_BWR_CnSC_CHIE(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(value) << TPM_CnSC_CHIE_SHIFT), TPM_CnSC_CHIE_SHIFT, TPM_CnSC_CHIE_WIDTH))
23499 /*@}*/
23500 
23501 /*!
23502  * @name Register TPM_CnSC, field CHF[7] (W1C)
23503  *
23504  * Set by hardware when an event occurs on the channel. CHF is cleared by
23505  * writing a 1 to the CHF bit. Writing a 0 to CHF has no effect. If another event
23506  * occurs between the CHF sets and the write operation, the write operation has no
23507  * effect; therefore, CHF remains set indicating another event has occurred. In this
23508  * case a CHF interrupt request is not lost due to the delay in clearing the
23509  * previous CHF.
23510  *
23511  * Values:
23512  * - 0b0 - No channel event has occurred.
23513  * - 0b1 - A channel event has occurred.
23514  */
23515 /*@{*/
23516 /*! @brief Read current value of the TPM_CnSC_CHF field. */
23517 #define TPM_RD_CnSC_CHF(base, index) ((TPM_CnSC_REG(base, index) & TPM_CnSC_CHF_MASK) >> TPM_CnSC_CHF_SHIFT)
23518 #define TPM_BRD_CnSC_CHF(base, index) (BME_UBFX32(&TPM_CnSC_REG(base, index), TPM_CnSC_CHF_SHIFT, TPM_CnSC_CHF_WIDTH))
23519 
23520 /*! @brief Set the CHF field to a new value. */
23521 #define TPM_WR_CnSC_CHF(base, index, value) (TPM_RMW_CnSC(base, index, TPM_CnSC_CHF_MASK, TPM_CnSC_CHF(value)))
23522 #define TPM_BWR_CnSC_CHF(base, index, value) (BME_BFI32(&TPM_CnSC_REG(base, index), ((uint32_t)(value) << TPM_CnSC_CHF_SHIFT), TPM_CnSC_CHF_SHIFT, TPM_CnSC_CHF_WIDTH))
23523 /*@}*/
23524 
23525 /*******************************************************************************
23526  * TPM_CnV - Channel (n) Value
23527  ******************************************************************************/
23528 
23529 /*!
23530  * @brief TPM_CnV - Channel (n) Value (RW)
23531  *
23532  * Reset value: 0x00000000U
23533  *
23534  * These registers contain the captured TPM counter value for the input modes or
23535  * the match value for the output modes. In input capture mode, any write to a
23536  * CnV register is ignored. In compare modes, writing to a CnV register latches
23537  * the value into a buffer. A CnV register is updated with the value of its write
23538  * buffer according to CnV Register Update . Additional writes to the CnV write
23539  * buffer are ignored until the register has been updated.
23540  */
23541 /*!
23542  * @name Constants and macros for entire TPM_CnV register
23543  */
23544 /*@{*/
23545 #define TPM_RD_CnV(base, index)  (TPM_CnV_REG(base, index))
23546 #define TPM_WR_CnV(base, index, value) (TPM_CnV_REG(base, index) = (value))
23547 #define TPM_RMW_CnV(base, index, mask, value) (TPM_WR_CnV(base, index, (TPM_RD_CnV(base, index) & ~(mask)) | (value)))
23548 #define TPM_SET_CnV(base, index, value) (BME_OR32(&TPM_CnV_REG(base, index), (uint32_t)(value)))
23549 #define TPM_CLR_CnV(base, index, value) (BME_AND32(&TPM_CnV_REG(base, index), (uint32_t)(~(value))))
23550 #define TPM_TOG_CnV(base, index, value) (BME_XOR32(&TPM_CnV_REG(base, index), (uint32_t)(value)))
23551 /*@}*/
23552 
23553 /*
23554  * Constants & macros for individual TPM_CnV bitfields
23555  */
23556 
23557 /*!
23558  * @name Register TPM_CnV, field VAL[15:0] (RW)
23559  *
23560  * Captured TPM counter value of the input modes or the match value for the
23561  * output modes. This field must be written with single 16-bit or 32-bit access.
23562  */
23563 /*@{*/
23564 /*! @brief Read current value of the TPM_CnV_VAL field. */
23565 #define TPM_RD_CnV_VAL(base, index) ((TPM_CnV_REG(base, index) & TPM_CnV_VAL_MASK) >> TPM_CnV_VAL_SHIFT)
23566 #define TPM_BRD_CnV_VAL(base, index) (BME_UBFX32(&TPM_CnV_REG(base, index), TPM_CnV_VAL_SHIFT, TPM_CnV_VAL_WIDTH))
23567 
23568 /*! @brief Set the VAL field to a new value. */
23569 #define TPM_WR_CnV_VAL(base, index, value) (TPM_RMW_CnV(base, index, TPM_CnV_VAL_MASK, TPM_CnV_VAL(value)))
23570 #define TPM_BWR_CnV_VAL(base, index, value) (BME_BFI32(&TPM_CnV_REG(base, index), ((uint32_t)(value) << TPM_CnV_VAL_SHIFT), TPM_CnV_VAL_SHIFT, TPM_CnV_VAL_WIDTH))
23571 /*@}*/
23572 
23573 /*******************************************************************************
23574  * TPM_STATUS - Capture and Compare Status
23575  ******************************************************************************/
23576 
23577 /*!
23578  * @brief TPM_STATUS - Capture and Compare Status (RW)
23579  *
23580  * Reset value: 0x00000000U
23581  *
23582  * The STATUS register contains a copy of the status flag, CnSC[CHnF] for each
23583  * TPM channel, as well as SC[TOF], for software convenience. Each CHnF bit in
23584  * STATUS is a mirror of CHnF bit in CnSC. All CHnF bits can be checked using only
23585  * one read of STATUS. All CHnF bits can be cleared by writing all ones to STATUS.
23586  * Hardware sets the individual channel flags when an event occurs on the
23587  * channel. Writing a 1 to CHF clears it. Writing a 0 to CHF has no effect. If another
23588  * event occurs between the flag setting and the write operation, the write
23589  * operation has no effect; therefore, CHF remains set indicating another event has
23590  * occurred. In this case a CHF interrupt request is not lost due to the clearing
23591  * sequence for a previous CHF.
23592  */
23593 /*!
23594  * @name Constants and macros for entire TPM_STATUS register
23595  */
23596 /*@{*/
23597 #define TPM_RD_STATUS(base)      (TPM_STATUS_REG(base))
23598 #define TPM_WR_STATUS(base, value) (TPM_STATUS_REG(base) = (value))
23599 #define TPM_RMW_STATUS(base, mask, value) (TPM_WR_STATUS(base, (TPM_RD_STATUS(base) & ~(mask)) | (value)))
23600 #define TPM_SET_STATUS(base, value) (BME_OR32(&TPM_STATUS_REG(base), (uint32_t)(value)))
23601 #define TPM_CLR_STATUS(base, value) (BME_AND32(&TPM_STATUS_REG(base), (uint32_t)(~(value))))
23602 #define TPM_TOG_STATUS(base, value) (BME_XOR32(&TPM_STATUS_REG(base), (uint32_t)(value)))
23603 /*@}*/
23604 
23605 /*
23606  * Constants & macros for individual TPM_STATUS bitfields
23607  */
23608 
23609 /*!
23610  * @name Register TPM_STATUS, field CH0F[0] (W1C)
23611  *
23612  * See the register description.
23613  *
23614  * Values:
23615  * - 0b0 - No channel event has occurred.
23616  * - 0b1 - A channel event has occurred.
23617  */
23618 /*@{*/
23619 /*! @brief Read current value of the TPM_STATUS_CH0F field. */
23620 #define TPM_RD_STATUS_CH0F(base) ((TPM_STATUS_REG(base) & TPM_STATUS_CH0F_MASK) >> TPM_STATUS_CH0F_SHIFT)
23621 #define TPM_BRD_STATUS_CH0F(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_CH0F_SHIFT, TPM_STATUS_CH0F_WIDTH))
23622 
23623 /*! @brief Set the CH0F field to a new value. */
23624 #define TPM_WR_STATUS_CH0F(base, value) (TPM_RMW_STATUS(base, (TPM_STATUS_CH0F_MASK | TPM_STATUS_CH1F_MASK | TPM_STATUS_CH2F_MASK | TPM_STATUS_CH3F_MASK | TPM_STATUS_TOF_MASK), TPM_STATUS_CH0F(value)))
23625 #define TPM_BWR_STATUS_CH0F(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TPM_STATUS_CH0F_SHIFT), TPM_STATUS_CH0F_SHIFT, TPM_STATUS_CH0F_WIDTH))
23626 /*@}*/
23627 
23628 /*!
23629  * @name Register TPM_STATUS, field CH1F[1] (W1C)
23630  *
23631  * See the register description.
23632  *
23633  * Values:
23634  * - 0b0 - No channel event has occurred.
23635  * - 0b1 - A channel event has occurred.
23636  */
23637 /*@{*/
23638 /*! @brief Read current value of the TPM_STATUS_CH1F field. */
23639 #define TPM_RD_STATUS_CH1F(base) ((TPM_STATUS_REG(base) & TPM_STATUS_CH1F_MASK) >> TPM_STATUS_CH1F_SHIFT)
23640 #define TPM_BRD_STATUS_CH1F(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_CH1F_SHIFT, TPM_STATUS_CH1F_WIDTH))
23641 
23642 /*! @brief Set the CH1F field to a new value. */
23643 #define TPM_WR_STATUS_CH1F(base, value) (TPM_RMW_STATUS(base, (TPM_STATUS_CH1F_MASK | TPM_STATUS_CH0F_MASK | TPM_STATUS_CH2F_MASK | TPM_STATUS_CH3F_MASK | TPM_STATUS_TOF_MASK), TPM_STATUS_CH1F(value)))
23644 #define TPM_BWR_STATUS_CH1F(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TPM_STATUS_CH1F_SHIFT), TPM_STATUS_CH1F_SHIFT, TPM_STATUS_CH1F_WIDTH))
23645 /*@}*/
23646 
23647 /*!
23648  * @name Register TPM_STATUS, field CH2F[2] (W1C)
23649  *
23650  * See the register description.
23651  *
23652  * Values:
23653  * - 0b0 - No channel event has occurred.
23654  * - 0b1 - A channel event has occurred.
23655  */
23656 /*@{*/
23657 /*! @brief Read current value of the TPM_STATUS_CH2F field. */
23658 #define TPM_RD_STATUS_CH2F(base) ((TPM_STATUS_REG(base) & TPM_STATUS_CH2F_MASK) >> TPM_STATUS_CH2F_SHIFT)
23659 #define TPM_BRD_STATUS_CH2F(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_CH2F_SHIFT, TPM_STATUS_CH2F_WIDTH))
23660 
23661 /*! @brief Set the CH2F field to a new value. */
23662 #define TPM_WR_STATUS_CH2F(base, value) (TPM_RMW_STATUS(base, (TPM_STATUS_CH2F_MASK | TPM_STATUS_CH0F_MASK | TPM_STATUS_CH1F_MASK | TPM_STATUS_CH3F_MASK | TPM_STATUS_TOF_MASK), TPM_STATUS_CH2F(value)))
23663 #define TPM_BWR_STATUS_CH2F(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TPM_STATUS_CH2F_SHIFT), TPM_STATUS_CH2F_SHIFT, TPM_STATUS_CH2F_WIDTH))
23664 /*@}*/
23665 
23666 /*!
23667  * @name Register TPM_STATUS, field CH3F[3] (W1C)
23668  *
23669  * See the register description.
23670  *
23671  * Values:
23672  * - 0b0 - No channel event has occurred.
23673  * - 0b1 - A channel event has occurred.
23674  */
23675 /*@{*/
23676 /*! @brief Read current value of the TPM_STATUS_CH3F field. */
23677 #define TPM_RD_STATUS_CH3F(base) ((TPM_STATUS_REG(base) & TPM_STATUS_CH3F_MASK) >> TPM_STATUS_CH3F_SHIFT)
23678 #define TPM_BRD_STATUS_CH3F(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_CH3F_SHIFT, TPM_STATUS_CH3F_WIDTH))
23679 
23680 /*! @brief Set the CH3F field to a new value. */
23681 #define TPM_WR_STATUS_CH3F(base, value) (TPM_RMW_STATUS(base, (TPM_STATUS_CH3F_MASK | TPM_STATUS_CH0F_MASK | TPM_STATUS_CH1F_MASK | TPM_STATUS_CH2F_MASK | TPM_STATUS_TOF_MASK), TPM_STATUS_CH3F(value)))
23682 #define TPM_BWR_STATUS_CH3F(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TPM_STATUS_CH3F_SHIFT), TPM_STATUS_CH3F_SHIFT, TPM_STATUS_CH3F_WIDTH))
23683 /*@}*/
23684 
23685 /*!
23686  * @name Register TPM_STATUS, field TOF[8] (W1C)
23687  *
23688  * See register description
23689  *
23690  * Values:
23691  * - 0b0 - TPM counter has not overflowed.
23692  * - 0b1 - TPM counter has overflowed.
23693  */
23694 /*@{*/
23695 /*! @brief Read current value of the TPM_STATUS_TOF field. */
23696 #define TPM_RD_STATUS_TOF(base) ((TPM_STATUS_REG(base) & TPM_STATUS_TOF_MASK) >> TPM_STATUS_TOF_SHIFT)
23697 #define TPM_BRD_STATUS_TOF(base) (BME_UBFX32(&TPM_STATUS_REG(base), TPM_STATUS_TOF_SHIFT, TPM_STATUS_TOF_WIDTH))
23698 
23699 /*! @brief Set the TOF field to a new value. */
23700 #define TPM_WR_STATUS_TOF(base, value) (TPM_RMW_STATUS(base, (TPM_STATUS_TOF_MASK | TPM_STATUS_CH0F_MASK | TPM_STATUS_CH1F_MASK | TPM_STATUS_CH2F_MASK | TPM_STATUS_CH3F_MASK), TPM_STATUS_TOF(value)))
23701 #define TPM_BWR_STATUS_TOF(base, value) (BME_BFI32(&TPM_STATUS_REG(base), ((uint32_t)(value) << TPM_STATUS_TOF_SHIFT), TPM_STATUS_TOF_SHIFT, TPM_STATUS_TOF_WIDTH))
23702 /*@}*/
23703 
23704 /*******************************************************************************
23705  * TPM_COMBINE - Combine Channel Register
23706  ******************************************************************************/
23707 
23708 /*!
23709  * @brief TPM_COMBINE - Combine Channel Register (RW)
23710  *
23711  * Reset value: 0x00000000U
23712  *
23713  * This register contains the control bits used to configure the combine channel
23714  * modes for each pair of channels (n) and (n+1), where n is all the even
23715  * numbered channels.
23716  */
23717 /*!
23718  * @name Constants and macros for entire TPM_COMBINE register
23719  */
23720 /*@{*/
23721 #define TPM_RD_COMBINE(base)     (TPM_COMBINE_REG(base))
23722 #define TPM_WR_COMBINE(base, value) (TPM_COMBINE_REG(base) = (value))
23723 #define TPM_RMW_COMBINE(base, mask, value) (TPM_WR_COMBINE(base, (TPM_RD_COMBINE(base) & ~(mask)) | (value)))
23724 #define TPM_SET_COMBINE(base, value) (BME_OR32(&TPM_COMBINE_REG(base), (uint32_t)(value)))
23725 #define TPM_CLR_COMBINE(base, value) (BME_AND32(&TPM_COMBINE_REG(base), (uint32_t)(~(value))))
23726 #define TPM_TOG_COMBINE(base, value) (BME_XOR32(&TPM_COMBINE_REG(base), (uint32_t)(value)))
23727 /*@}*/
23728 
23729 /*
23730  * Constants & macros for individual TPM_COMBINE bitfields
23731  */
23732 
23733 /*!
23734  * @name Register TPM_COMBINE, field COMBINE0[0] (RW)
23735  *
23736  * Enables the combine feature for channels 0 and 1. In input capture mode, the
23737  * combined channels use the even channel input. In software compare modes, the
23738  * even channel match asserts the output trigger and the odd channel match negates
23739  * the output trigger. In PWM modes, the even channel match is used for the 1st
23740  * compare and odd channel match for the 2nd compare.
23741  *
23742  * Values:
23743  * - 0b0 - Channels 0 and 1 are independent.
23744  * - 0b1 - Channels 0 and 1 are combined.
23745  */
23746 /*@{*/
23747 /*! @brief Read current value of the TPM_COMBINE_COMBINE0 field. */
23748 #define TPM_RD_COMBINE_COMBINE0(base) ((TPM_COMBINE_REG(base) & TPM_COMBINE_COMBINE0_MASK) >> TPM_COMBINE_COMBINE0_SHIFT)
23749 #define TPM_BRD_COMBINE_COMBINE0(base) (BME_UBFX32(&TPM_COMBINE_REG(base), TPM_COMBINE_COMBINE0_SHIFT, TPM_COMBINE_COMBINE0_WIDTH))
23750 
23751 /*! @brief Set the COMBINE0 field to a new value. */
23752 #define TPM_WR_COMBINE_COMBINE0(base, value) (TPM_RMW_COMBINE(base, TPM_COMBINE_COMBINE0_MASK, TPM_COMBINE_COMBINE0(value)))
23753 #define TPM_BWR_COMBINE_COMBINE0(base, value) (BME_BFI32(&TPM_COMBINE_REG(base), ((uint32_t)(value) << TPM_COMBINE_COMBINE0_SHIFT), TPM_COMBINE_COMBINE0_SHIFT, TPM_COMBINE_COMBINE0_WIDTH))
23754 /*@}*/
23755 
23756 /*!
23757  * @name Register TPM_COMBINE, field COMSWAP0[1] (RW)
23758  *
23759  * When set in combine mode, the even channel is used for the input capture and
23760  * 1st compare, the odd channel is used for the 2nd compare.
23761  *
23762  * Values:
23763  * - 0b0 - Even channel is used for input capture and 1st compare.
23764  * - 0b1 - Odd channel is used for input capture and 1st compare.
23765  */
23766 /*@{*/
23767 /*! @brief Read current value of the TPM_COMBINE_COMSWAP0 field. */
23768 #define TPM_RD_COMBINE_COMSWAP0(base) ((TPM_COMBINE_REG(base) & TPM_COMBINE_COMSWAP0_MASK) >> TPM_COMBINE_COMSWAP0_SHIFT)
23769 #define TPM_BRD_COMBINE_COMSWAP0(base) (BME_UBFX32(&TPM_COMBINE_REG(base), TPM_COMBINE_COMSWAP0_SHIFT, TPM_COMBINE_COMSWAP0_WIDTH))
23770 
23771 /*! @brief Set the COMSWAP0 field to a new value. */
23772 #define TPM_WR_COMBINE_COMSWAP0(base, value) (TPM_RMW_COMBINE(base, TPM_COMBINE_COMSWAP0_MASK, TPM_COMBINE_COMSWAP0(value)))
23773 #define TPM_BWR_COMBINE_COMSWAP0(base, value) (BME_BFI32(&TPM_COMBINE_REG(base), ((uint32_t)(value) << TPM_COMBINE_COMSWAP0_SHIFT), TPM_COMBINE_COMSWAP0_SHIFT, TPM_COMBINE_COMSWAP0_WIDTH))
23774 /*@}*/
23775 
23776 /*!
23777  * @name Register TPM_COMBINE, field COMBINE1[8] (RW)
23778  *
23779  * Enables the combine feature for channels 2 and 3. In input capture mode, the
23780  * combined channels use the even channel input. In software compare modes, the
23781  * even channel match asserts the output trigger and the odd channel match negates
23782  * the output trigger. In PWM modes, the even channel match is used for the 1st
23783  * compare and odd channel match for the 2nd compare.
23784  *
23785  * Values:
23786  * - 0b0 - Channels 2 and 3 are independent.
23787  * - 0b1 - Channels 2 and 3 are combined.
23788  */
23789 /*@{*/
23790 /*! @brief Read current value of the TPM_COMBINE_COMBINE1 field. */
23791 #define TPM_RD_COMBINE_COMBINE1(base) ((TPM_COMBINE_REG(base) & TPM_COMBINE_COMBINE1_MASK) >> TPM_COMBINE_COMBINE1_SHIFT)
23792 #define TPM_BRD_COMBINE_COMBINE1(base) (BME_UBFX32(&TPM_COMBINE_REG(base), TPM_COMBINE_COMBINE1_SHIFT, TPM_COMBINE_COMBINE1_WIDTH))
23793 
23794 /*! @brief Set the COMBINE1 field to a new value. */
23795 #define TPM_WR_COMBINE_COMBINE1(base, value) (TPM_RMW_COMBINE(base, TPM_COMBINE_COMBINE1_MASK, TPM_COMBINE_COMBINE1(value)))
23796 #define TPM_BWR_COMBINE_COMBINE1(base, value) (BME_BFI32(&TPM_COMBINE_REG(base), ((uint32_t)(value) << TPM_COMBINE_COMBINE1_SHIFT), TPM_COMBINE_COMBINE1_SHIFT, TPM_COMBINE_COMBINE1_WIDTH))
23797 /*@}*/
23798 
23799 /*!
23800  * @name Register TPM_COMBINE, field COMSWAP1[9] (RW)
23801  *
23802  * When set in combine mode, the odd channel is used for the input capture and
23803  * 1st compare, the even channel is used for the 2nd compare.
23804  *
23805  * Values:
23806  * - 0b0 - Even channel is used for input capture and 1st compare.
23807  * - 0b1 - Odd channel is used for input capture and 1st compare.
23808  */
23809 /*@{*/
23810 /*! @brief Read current value of the TPM_COMBINE_COMSWAP1 field. */
23811 #define TPM_RD_COMBINE_COMSWAP1(base) ((TPM_COMBINE_REG(base) & TPM_COMBINE_COMSWAP1_MASK) >> TPM_COMBINE_COMSWAP1_SHIFT)
23812 #define TPM_BRD_COMBINE_COMSWAP1(base) (BME_UBFX32(&TPM_COMBINE_REG(base), TPM_COMBINE_COMSWAP1_SHIFT, TPM_COMBINE_COMSWAP1_WIDTH))
23813 
23814 /*! @brief Set the COMSWAP1 field to a new value. */
23815 #define TPM_WR_COMBINE_COMSWAP1(base, value) (TPM_RMW_COMBINE(base, TPM_COMBINE_COMSWAP1_MASK, TPM_COMBINE_COMSWAP1(value)))
23816 #define TPM_BWR_COMBINE_COMSWAP1(base, value) (BME_BFI32(&TPM_COMBINE_REG(base), ((uint32_t)(value) << TPM_COMBINE_COMSWAP1_SHIFT), TPM_COMBINE_COMSWAP1_SHIFT, TPM_COMBINE_COMSWAP1_WIDTH))
23817 /*@}*/
23818 
23819 /*******************************************************************************
23820  * TPM_FILTER - Filter Control
23821  ******************************************************************************/
23822 
23823 /*!
23824  * @brief TPM_FILTER - Filter Control (RW)
23825  *
23826  * Reset value: 0x00000000U
23827  *
23828  * This register selects the filter value of the channel inputs, and an
23829  * additional output delay value for the channel outputs. In PWM combine modes, the
23830  * filter can effectively implements deadtime insertion.
23831  */
23832 /*!
23833  * @name Constants and macros for entire TPM_FILTER register
23834  */
23835 /*@{*/
23836 #define TPM_RD_FILTER(base)      (TPM_FILTER_REG(base))
23837 #define TPM_WR_FILTER(base, value) (TPM_FILTER_REG(base) = (value))
23838 #define TPM_RMW_FILTER(base, mask, value) (TPM_WR_FILTER(base, (TPM_RD_FILTER(base) & ~(mask)) | (value)))
23839 #define TPM_SET_FILTER(base, value) (BME_OR32(&TPM_FILTER_REG(base), (uint32_t)(value)))
23840 #define TPM_CLR_FILTER(base, value) (BME_AND32(&TPM_FILTER_REG(base), (uint32_t)(~(value))))
23841 #define TPM_TOG_FILTER(base, value) (BME_XOR32(&TPM_FILTER_REG(base), (uint32_t)(value)))
23842 /*@}*/
23843 
23844 /*
23845  * Constants & macros for individual TPM_FILTER bitfields
23846  */
23847 
23848 /*!
23849  * @name Register TPM_FILTER, field CH0FVAL[3:0] (RW)
23850  *
23851  * Selects the filter value for the channel input and the delay value for the
23852  * channel output. The filter/delay is disabled when the value is zero, otherwise
23853  * the filter/delay is configured as (CH0FVAL * 4) clock cycles.
23854  */
23855 /*@{*/
23856 /*! @brief Read current value of the TPM_FILTER_CH0FVAL field. */
23857 #define TPM_RD_FILTER_CH0FVAL(base) ((TPM_FILTER_REG(base) & TPM_FILTER_CH0FVAL_MASK) >> TPM_FILTER_CH0FVAL_SHIFT)
23858 #define TPM_BRD_FILTER_CH0FVAL(base) (BME_UBFX32(&TPM_FILTER_REG(base), TPM_FILTER_CH0FVAL_SHIFT, TPM_FILTER_CH0FVAL_WIDTH))
23859 
23860 /*! @brief Set the CH0FVAL field to a new value. */
23861 #define TPM_WR_FILTER_CH0FVAL(base, value) (TPM_RMW_FILTER(base, TPM_FILTER_CH0FVAL_MASK, TPM_FILTER_CH0FVAL(value)))
23862 #define TPM_BWR_FILTER_CH0FVAL(base, value) (BME_BFI32(&TPM_FILTER_REG(base), ((uint32_t)(value) << TPM_FILTER_CH0FVAL_SHIFT), TPM_FILTER_CH0FVAL_SHIFT, TPM_FILTER_CH0FVAL_WIDTH))
23863 /*@}*/
23864 
23865 /*!
23866  * @name Register TPM_FILTER, field CH1FVAL[7:4] (RW)
23867  *
23868  * Selects the filter value for the channel input and the delay value for the
23869  * channel output. The filter/delay is disabled when the value is zero, otherwise
23870  * the filter/delay is configured as (CH1FVAL * 4) clock cycles.
23871  */
23872 /*@{*/
23873 /*! @brief Read current value of the TPM_FILTER_CH1FVAL field. */
23874 #define TPM_RD_FILTER_CH1FVAL(base) ((TPM_FILTER_REG(base) & TPM_FILTER_CH1FVAL_MASK) >> TPM_FILTER_CH1FVAL_SHIFT)
23875 #define TPM_BRD_FILTER_CH1FVAL(base) (BME_UBFX32(&TPM_FILTER_REG(base), TPM_FILTER_CH1FVAL_SHIFT, TPM_FILTER_CH1FVAL_WIDTH))
23876 
23877 /*! @brief Set the CH1FVAL field to a new value. */
23878 #define TPM_WR_FILTER_CH1FVAL(base, value) (TPM_RMW_FILTER(base, TPM_FILTER_CH1FVAL_MASK, TPM_FILTER_CH1FVAL(value)))
23879 #define TPM_BWR_FILTER_CH1FVAL(base, value) (BME_BFI32(&TPM_FILTER_REG(base), ((uint32_t)(value) << TPM_FILTER_CH1FVAL_SHIFT), TPM_FILTER_CH1FVAL_SHIFT, TPM_FILTER_CH1FVAL_WIDTH))
23880 /*@}*/
23881 
23882 /*!
23883  * @name Register TPM_FILTER, field CH2FVAL[11:8] (RW)
23884  *
23885  * Selects the filter value for the channel input and the delay value for the
23886  * channel output. The filter/delay is disabled when the value is zero, otherwise
23887  * the filter/delay is configured as (CH2FVAL * 4) clock cycles.
23888  */
23889 /*@{*/
23890 /*! @brief Read current value of the TPM_FILTER_CH2FVAL field. */
23891 #define TPM_RD_FILTER_CH2FVAL(base) ((TPM_FILTER_REG(base) & TPM_FILTER_CH2FVAL_MASK) >> TPM_FILTER_CH2FVAL_SHIFT)
23892 #define TPM_BRD_FILTER_CH2FVAL(base) (BME_UBFX32(&TPM_FILTER_REG(base), TPM_FILTER_CH2FVAL_SHIFT, TPM_FILTER_CH2FVAL_WIDTH))
23893 
23894 /*! @brief Set the CH2FVAL field to a new value. */
23895 #define TPM_WR_FILTER_CH2FVAL(base, value) (TPM_RMW_FILTER(base, TPM_FILTER_CH2FVAL_MASK, TPM_FILTER_CH2FVAL(value)))
23896 #define TPM_BWR_FILTER_CH2FVAL(base, value) (BME_BFI32(&TPM_FILTER_REG(base), ((uint32_t)(value) << TPM_FILTER_CH2FVAL_SHIFT), TPM_FILTER_CH2FVAL_SHIFT, TPM_FILTER_CH2FVAL_WIDTH))
23897 /*@}*/
23898 
23899 /*!
23900  * @name Register TPM_FILTER, field CH3FVAL[15:12] (RW)
23901  *
23902  * Selects the filter value for the channel input and the delay value for the
23903  * channel output. The filter/delay is disabled when the value is zero, otherwise
23904  * the filter/delay is configured as (CH3FVAL * 4) clock cycles.
23905  */
23906 /*@{*/
23907 /*! @brief Read current value of the TPM_FILTER_CH3FVAL field. */
23908 #define TPM_RD_FILTER_CH3FVAL(base) ((TPM_FILTER_REG(base) & TPM_FILTER_CH3FVAL_MASK) >> TPM_FILTER_CH3FVAL_SHIFT)
23909 #define TPM_BRD_FILTER_CH3FVAL(base) (BME_UBFX32(&TPM_FILTER_REG(base), TPM_FILTER_CH3FVAL_SHIFT, TPM_FILTER_CH3FVAL_WIDTH))
23910 
23911 /*! @brief Set the CH3FVAL field to a new value. */
23912 #define TPM_WR_FILTER_CH3FVAL(base, value) (TPM_RMW_FILTER(base, TPM_FILTER_CH3FVAL_MASK, TPM_FILTER_CH3FVAL(value)))
23913 #define TPM_BWR_FILTER_CH3FVAL(base, value) (BME_BFI32(&TPM_FILTER_REG(base), ((uint32_t)(value) << TPM_FILTER_CH3FVAL_SHIFT), TPM_FILTER_CH3FVAL_SHIFT, TPM_FILTER_CH3FVAL_WIDTH))
23914 /*@}*/
23915 
23916 /*******************************************************************************
23917  * TPM_QDCTRL - Quadrature Decoder Control and Status
23918  ******************************************************************************/
23919 
23920 /*!
23921  * @brief TPM_QDCTRL - Quadrature Decoder Control and Status (RW)
23922  *
23923  * Reset value: 0x00000000U
23924  *
23925  * This register has the control and status bits for the quadrature decoder mode.
23926  */
23927 /*!
23928  * @name Constants and macros for entire TPM_QDCTRL register
23929  */
23930 /*@{*/
23931 #define TPM_RD_QDCTRL(base)      (TPM_QDCTRL_REG(base))
23932 #define TPM_WR_QDCTRL(base, value) (TPM_QDCTRL_REG(base) = (value))
23933 #define TPM_RMW_QDCTRL(base, mask, value) (TPM_WR_QDCTRL(base, (TPM_RD_QDCTRL(base) & ~(mask)) | (value)))
23934 #define TPM_SET_QDCTRL(base, value) (BME_OR32(&TPM_QDCTRL_REG(base), (uint32_t)(value)))
23935 #define TPM_CLR_QDCTRL(base, value) (BME_AND32(&TPM_QDCTRL_REG(base), (uint32_t)(~(value))))
23936 #define TPM_TOG_QDCTRL(base, value) (BME_XOR32(&TPM_QDCTRL_REG(base), (uint32_t)(value)))
23937 /*@}*/
23938 
23939 /*
23940  * Constants & macros for individual TPM_QDCTRL bitfields
23941  */
23942 
23943 /*!
23944  * @name Register TPM_QDCTRL, field QUADEN[0] (RW)
23945  *
23946  * Enables the quadrature decoder mode. In this mode, the channel 0 and channel
23947  * 1 inputs control the TPM counter direction and can only be used for software
23948  * compare. The quadrature decoder mode has precedence over the other modes.
23949  *
23950  * Values:
23951  * - 0b0 - Quadrature decoder mode is disabled.
23952  * - 0b1 - Quadrature decoder mode is enabled.
23953  */
23954 /*@{*/
23955 /*! @brief Read current value of the TPM_QDCTRL_QUADEN field. */
23956 #define TPM_RD_QDCTRL_QUADEN(base) ((TPM_QDCTRL_REG(base) & TPM_QDCTRL_QUADEN_MASK) >> TPM_QDCTRL_QUADEN_SHIFT)
23957 #define TPM_BRD_QDCTRL_QUADEN(base) (BME_UBFX32(&TPM_QDCTRL_REG(base), TPM_QDCTRL_QUADEN_SHIFT, TPM_QDCTRL_QUADEN_WIDTH))
23958 
23959 /*! @brief Set the QUADEN field to a new value. */
23960 #define TPM_WR_QDCTRL_QUADEN(base, value) (TPM_RMW_QDCTRL(base, TPM_QDCTRL_QUADEN_MASK, TPM_QDCTRL_QUADEN(value)))
23961 #define TPM_BWR_QDCTRL_QUADEN(base, value) (BME_BFI32(&TPM_QDCTRL_REG(base), ((uint32_t)(value) << TPM_QDCTRL_QUADEN_SHIFT), TPM_QDCTRL_QUADEN_SHIFT, TPM_QDCTRL_QUADEN_WIDTH))
23962 /*@}*/
23963 
23964 /*!
23965  * @name Register TPM_QDCTRL, field TOFDIR[1] (RO)
23966  *
23967  * Indicates if the TOF bit was set on the top or the bottom of counting.
23968  *
23969  * Values:
23970  * - 0b0 - TOF bit was set on the bottom of counting. There was an FTM counter
23971  *     decrement and FTM counter changes from its minimum value (zero) to its
23972  *     maximum value (MOD register).
23973  * - 0b1 - TOF bit was set on the top of counting. There was an FTM counter
23974  *     increment and FTM counter changes from its maximum value (MOD register) to its
23975  *     minimum value (zero).
23976  */
23977 /*@{*/
23978 /*! @brief Read current value of the TPM_QDCTRL_TOFDIR field. */
23979 #define TPM_RD_QDCTRL_TOFDIR(base) ((TPM_QDCTRL_REG(base) & TPM_QDCTRL_TOFDIR_MASK) >> TPM_QDCTRL_TOFDIR_SHIFT)
23980 #define TPM_BRD_QDCTRL_TOFDIR(base) (BME_UBFX32(&TPM_QDCTRL_REG(base), TPM_QDCTRL_TOFDIR_SHIFT, TPM_QDCTRL_TOFDIR_WIDTH))
23981 /*@}*/
23982 
23983 /*!
23984  * @name Register TPM_QDCTRL, field QUADIR[2] (RO)
23985  *
23986  * Indicates the counting direction.
23987  *
23988  * Values:
23989  * - 0b0 - Counter direction is decreasing (counter decrement).
23990  * - 0b1 - Counter direction is increasing (counter increment).
23991  */
23992 /*@{*/
23993 /*! @brief Read current value of the TPM_QDCTRL_QUADIR field. */
23994 #define TPM_RD_QDCTRL_QUADIR(base) ((TPM_QDCTRL_REG(base) & TPM_QDCTRL_QUADIR_MASK) >> TPM_QDCTRL_QUADIR_SHIFT)
23995 #define TPM_BRD_QDCTRL_QUADIR(base) (BME_UBFX32(&TPM_QDCTRL_REG(base), TPM_QDCTRL_QUADIR_SHIFT, TPM_QDCTRL_QUADIR_WIDTH))
23996 /*@}*/
23997 
23998 /*!
23999  * @name Register TPM_QDCTRL, field QUADMODE[3] (RW)
24000  *
24001  * Selects the encoding mode used in the quadrature decoder mode.
24002  *
24003  * Values:
24004  * - 0b0 - Phase encoding mode.
24005  * - 0b1 - Count and direction encoding mode.
24006  */
24007 /*@{*/
24008 /*! @brief Read current value of the TPM_QDCTRL_QUADMODE field. */
24009 #define TPM_RD_QDCTRL_QUADMODE(base) ((TPM_QDCTRL_REG(base) & TPM_QDCTRL_QUADMODE_MASK) >> TPM_QDCTRL_QUADMODE_SHIFT)
24010 #define TPM_BRD_QDCTRL_QUADMODE(base) (BME_UBFX32(&TPM_QDCTRL_REG(base), TPM_QDCTRL_QUADMODE_SHIFT, TPM_QDCTRL_QUADMODE_WIDTH))
24011 
24012 /*! @brief Set the QUADMODE field to a new value. */
24013 #define TPM_WR_QDCTRL_QUADMODE(base, value) (TPM_RMW_QDCTRL(base, TPM_QDCTRL_QUADMODE_MASK, TPM_QDCTRL_QUADMODE(value)))
24014 #define TPM_BWR_QDCTRL_QUADMODE(base, value) (BME_BFI32(&TPM_QDCTRL_REG(base), ((uint32_t)(value) << TPM_QDCTRL_QUADMODE_SHIFT), TPM_QDCTRL_QUADMODE_SHIFT, TPM_QDCTRL_QUADMODE_WIDTH))
24015 /*@}*/
24016 
24017 /*******************************************************************************
24018  * TPM_CONF - Configuration
24019  ******************************************************************************/
24020 
24021 /*!
24022  * @brief TPM_CONF - Configuration (RW)
24023  *
24024  * Reset value: 0x00000000U
24025  *
24026  * This register selects the behavior in debug and wait modes and the use of an
24027  * external global time base.
24028  */
24029 /*!
24030  * @name Constants and macros for entire TPM_CONF register
24031  */
24032 /*@{*/
24033 #define TPM_RD_CONF(base)        (TPM_CONF_REG(base))
24034 #define TPM_WR_CONF(base, value) (TPM_CONF_REG(base) = (value))
24035 #define TPM_RMW_CONF(base, mask, value) (TPM_WR_CONF(base, (TPM_RD_CONF(base) & ~(mask)) | (value)))
24036 #define TPM_SET_CONF(base, value) (BME_OR32(&TPM_CONF_REG(base), (uint32_t)(value)))
24037 #define TPM_CLR_CONF(base, value) (BME_AND32(&TPM_CONF_REG(base), (uint32_t)(~(value))))
24038 #define TPM_TOG_CONF(base, value) (BME_XOR32(&TPM_CONF_REG(base), (uint32_t)(value)))
24039 /*@}*/
24040 
24041 /*
24042  * Constants & macros for individual TPM_CONF bitfields
24043  */
24044 
24045 /*!
24046  * @name Register TPM_CONF, field DOZEEN[5] (RW)
24047  *
24048  * Configures the TPM behavior in wait mode.
24049  *
24050  * Values:
24051  * - 0b0 - Internal TPM counter continues in Doze mode.
24052  * - 0b1 - Internal TPM counter is paused and does not increment during Doze
24053  *     mode. Trigger inputs and input capture events are also ignored.
24054  */
24055 /*@{*/
24056 /*! @brief Read current value of the TPM_CONF_DOZEEN field. */
24057 #define TPM_RD_CONF_DOZEEN(base) ((TPM_CONF_REG(base) & TPM_CONF_DOZEEN_MASK) >> TPM_CONF_DOZEEN_SHIFT)
24058 #define TPM_BRD_CONF_DOZEEN(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_DOZEEN_SHIFT, TPM_CONF_DOZEEN_WIDTH))
24059 
24060 /*! @brief Set the DOZEEN field to a new value. */
24061 #define TPM_WR_CONF_DOZEEN(base, value) (TPM_RMW_CONF(base, TPM_CONF_DOZEEN_MASK, TPM_CONF_DOZEEN(value)))
24062 #define TPM_BWR_CONF_DOZEEN(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CONF_DOZEEN_SHIFT), TPM_CONF_DOZEEN_SHIFT, TPM_CONF_DOZEEN_WIDTH))
24063 /*@}*/
24064 
24065 /*!
24066  * @name Register TPM_CONF, field DBGMODE[7:6] (RW)
24067  *
24068  * Configures the TPM behavior in debug mode. All other configurations are
24069  * reserved.
24070  *
24071  * Values:
24072  * - 0b00 - TPM counter is paused and does not increment during debug mode.
24073  *     Trigger inputs and input capture events are also ignored.
24074  * - 0b11 - TPM counter continues in debug mode.
24075  */
24076 /*@{*/
24077 /*! @brief Read current value of the TPM_CONF_DBGMODE field. */
24078 #define TPM_RD_CONF_DBGMODE(base) ((TPM_CONF_REG(base) & TPM_CONF_DBGMODE_MASK) >> TPM_CONF_DBGMODE_SHIFT)
24079 #define TPM_BRD_CONF_DBGMODE(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_DBGMODE_SHIFT, TPM_CONF_DBGMODE_WIDTH))
24080 
24081 /*! @brief Set the DBGMODE field to a new value. */
24082 #define TPM_WR_CONF_DBGMODE(base, value) (TPM_RMW_CONF(base, TPM_CONF_DBGMODE_MASK, TPM_CONF_DBGMODE(value)))
24083 #define TPM_BWR_CONF_DBGMODE(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CONF_DBGMODE_SHIFT), TPM_CONF_DBGMODE_SHIFT, TPM_CONF_DBGMODE_WIDTH))
24084 /*@}*/
24085 
24086 /*!
24087  * @name Register TPM_CONF, field GTBEEN[9] (RW)
24088  *
24089  * Configures the TPM to use an externally generated global time base counter.
24090  * When an externally generated timebase is used, the internal TPM counter is not
24091  * used by the channels but can be used to generate a periodic interruptor DMA
24092  * request using the Modulo register and timer overflow flag.
24093  *
24094  * Values:
24095  * - 0b0 - All channels use the internally generated TPM counter as their
24096  *     timebase
24097  * - 0b1 - All channels use an externally generated global timebase as their
24098  *     timebase
24099  */
24100 /*@{*/
24101 /*! @brief Read current value of the TPM_CONF_GTBEEN field. */
24102 #define TPM_RD_CONF_GTBEEN(base) ((TPM_CONF_REG(base) & TPM_CONF_GTBEEN_MASK) >> TPM_CONF_GTBEEN_SHIFT)
24103 #define TPM_BRD_CONF_GTBEEN(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_GTBEEN_SHIFT, TPM_CONF_GTBEEN_WIDTH))
24104 
24105 /*! @brief Set the GTBEEN field to a new value. */
24106 #define TPM_WR_CONF_GTBEEN(base, value) (TPM_RMW_CONF(base, TPM_CONF_GTBEEN_MASK, TPM_CONF_GTBEEN(value)))
24107 #define TPM_BWR_CONF_GTBEEN(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CONF_GTBEEN_SHIFT), TPM_CONF_GTBEEN_SHIFT, TPM_CONF_GTBEEN_WIDTH))
24108 /*@}*/
24109 
24110 /*!
24111  * @name Register TPM_CONF, field CSOT[16] (RW)
24112  *
24113  * When set, the TPM counter will not start incrementing after it is enabled
24114  * until a rising edge on the selected trigger input is detected. If the TPM counter
24115  * is stopped due to an overflow, a rising edge on the selected trigger input
24116  * will also cause the TPM counter to start incrementing again. The trigger input
24117  * is ignored if the TPM counter is paused during debug mode or doze mode. This
24118  * field should only be changed when the TPM counter is disabled.
24119  *
24120  * Values:
24121  * - 0b0 - TPM counter starts to increment immediately, once it is enabled.
24122  * - 0b1 - TPM counter only starts to increment when it a rising edge on the
24123  *     selected input trigger is detected, after it has been enabled or after it has
24124  *     stopped due to overflow.
24125  */
24126 /*@{*/
24127 /*! @brief Read current value of the TPM_CONF_CSOT field. */
24128 #define TPM_RD_CONF_CSOT(base) ((TPM_CONF_REG(base) & TPM_CONF_CSOT_MASK) >> TPM_CONF_CSOT_SHIFT)
24129 #define TPM_BRD_CONF_CSOT(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_CSOT_SHIFT, TPM_CONF_CSOT_WIDTH))
24130 
24131 /*! @brief Set the CSOT field to a new value. */
24132 #define TPM_WR_CONF_CSOT(base, value) (TPM_RMW_CONF(base, TPM_CONF_CSOT_MASK, TPM_CONF_CSOT(value)))
24133 #define TPM_BWR_CONF_CSOT(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CONF_CSOT_SHIFT), TPM_CONF_CSOT_SHIFT, TPM_CONF_CSOT_WIDTH))
24134 /*@}*/
24135 
24136 /*!
24137  * @name Register TPM_CONF, field CSOO[17] (RW)
24138  *
24139  * When set, the TPM counter will stop incrementing once the counter equals the
24140  * MOD value and incremented (this also sets the TOF). Reloading the counter with
24141  * 0 due to writing to the counter register or due to a trigger input does not
24142  * cause the counter to stop incrementing. Once the counter has stopped
24143  * incrementing, the counter will not start incrementing unless it is disabled and then
24144  * enabled again, or a rising edge on the selected trigger input is detected when
24145  * CSOT set. This field should only be changed when the TPM counter is disabled.
24146  *
24147  * Values:
24148  * - 0b0 - TPM counter continues incrementing or decrementing after overflow
24149  * - 0b1 - TPM counter stops incrementing or decrementing after overflow.
24150  */
24151 /*@{*/
24152 /*! @brief Read current value of the TPM_CONF_CSOO field. */
24153 #define TPM_RD_CONF_CSOO(base) ((TPM_CONF_REG(base) & TPM_CONF_CSOO_MASK) >> TPM_CONF_CSOO_SHIFT)
24154 #define TPM_BRD_CONF_CSOO(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_CSOO_SHIFT, TPM_CONF_CSOO_WIDTH))
24155 
24156 /*! @brief Set the CSOO field to a new value. */
24157 #define TPM_WR_CONF_CSOO(base, value) (TPM_RMW_CONF(base, TPM_CONF_CSOO_MASK, TPM_CONF_CSOO(value)))
24158 #define TPM_BWR_CONF_CSOO(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CONF_CSOO_SHIFT), TPM_CONF_CSOO_SHIFT, TPM_CONF_CSOO_WIDTH))
24159 /*@}*/
24160 
24161 /*!
24162  * @name Register TPM_CONF, field CROT[18] (RW)
24163  *
24164  * When set, the TPM counter will reload with 0 (and initialize PWM outputs to
24165  * their default value) when a rising edge is detected on the selected trigger
24166  * input. The trigger input is ignored if the TPM counter is paused during debug
24167  * mode or doze mode. This field should only be changed when the TPM counter is
24168  * disabled.
24169  *
24170  * Values:
24171  * - 0b0 - Counter is not reloaded due to a rising edge on the selected input
24172  *     trigger
24173  * - 0b1 - Counter is reloaded when a rising edge is detected on the selected
24174  *     input trigger
24175  */
24176 /*@{*/
24177 /*! @brief Read current value of the TPM_CONF_CROT field. */
24178 #define TPM_RD_CONF_CROT(base) ((TPM_CONF_REG(base) & TPM_CONF_CROT_MASK) >> TPM_CONF_CROT_SHIFT)
24179 #define TPM_BRD_CONF_CROT(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_CROT_SHIFT, TPM_CONF_CROT_WIDTH))
24180 
24181 /*! @brief Set the CROT field to a new value. */
24182 #define TPM_WR_CONF_CROT(base, value) (TPM_RMW_CONF(base, TPM_CONF_CROT_MASK, TPM_CONF_CROT(value)))
24183 #define TPM_BWR_CONF_CROT(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CONF_CROT_SHIFT), TPM_CONF_CROT_SHIFT, TPM_CONF_CROT_WIDTH))
24184 /*@}*/
24185 
24186 /*!
24187  * @name Register TPM_CONF, field TRGSEL[27:24] (RW)
24188  *
24189  * Selects the input trigger to use for starting the counter and/or reloading
24190  * the counter. This field should only be changed when the TPM counter is disabled.
24191  * See Chip configuration section for available options.
24192  */
24193 /*@{*/
24194 /*! @brief Read current value of the TPM_CONF_TRGSEL field. */
24195 #define TPM_RD_CONF_TRGSEL(base) ((TPM_CONF_REG(base) & TPM_CONF_TRGSEL_MASK) >> TPM_CONF_TRGSEL_SHIFT)
24196 #define TPM_BRD_CONF_TRGSEL(base) (BME_UBFX32(&TPM_CONF_REG(base), TPM_CONF_TRGSEL_SHIFT, TPM_CONF_TRGSEL_WIDTH))
24197 
24198 /*! @brief Set the TRGSEL field to a new value. */
24199 #define TPM_WR_CONF_TRGSEL(base, value) (TPM_RMW_CONF(base, TPM_CONF_TRGSEL_MASK, TPM_CONF_TRGSEL(value)))
24200 #define TPM_BWR_CONF_TRGSEL(base, value) (BME_BFI32(&TPM_CONF_REG(base), ((uint32_t)(value) << TPM_CONF_TRGSEL_SHIFT), TPM_CONF_TRGSEL_SHIFT, TPM_CONF_TRGSEL_WIDTH))
24201 /*@}*/
24202 
24203 /*
24204  * MKW40Z4 TRNG
24205  *
24206  * RNG
24207  *
24208  * Registers defined in this header file:
24209  * - TRNG_MCTL - RNG Miscellaneous Control Register
24210  * - TRNG_SCMISC - RNG Statistical Check Miscellaneous Register
24211  * - TRNG_PKRRNG - RNG Poker Range Register
24212  * - TRNG_PKRMAX - RNG Poker Maximum Limit Register
24213  * - TRNG_PKRSQ - RNG Poker Square Calculation Result Register
24214  * - TRNG_SDCTL - RNG Seed Control Register
24215  * - TRNG_SBLIM - RNG Sparse Bit Limit Register
24216  * - TRNG_TOTSAM - RNG Total Samples Register
24217  * - TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register
24218  * - TRNG_FRQCNT - RNG Frequency Count Register
24219  * - TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register
24220  * - TRNG_SCMC - RNG Statistical Check Monobit Count Register
24221  * - TRNG_SCML - RNG Statistical Check Monobit Limit Register
24222  * - TRNG_SCR1C - RNG Statistical Check Run Length 1 Count Register
24223  * - TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register
24224  * - TRNG_SCR2C - RNG Statistical Check Run Length 2 Count Register
24225  * - TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register
24226  * - TRNG_SCR3C - RNG Statistical Check Run Length 3 Count Register
24227  * - TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register
24228  * - TRNG_SCR4C - RNG Statistical Check Run Length 4 Count Register
24229  * - TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register
24230  * - TRNG_SCR5C - RNG Statistical Check Run Length 5 Count Register
24231  * - TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register
24232  * - TRNG_SCR6PC - RNG Statistical Check Run Length 6+ Count Register
24233  * - TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register
24234  * - TRNG_STATUS - RNG Status Register
24235  * - TRNG_ENT - RNG TRNG Entropy Read Register
24236  * - TRNG_PKRCNT10 - RNG Statistical Check Poker Count 1 and 0 Register
24237  * - TRNG_PKRCNT32 - RNG Statistical Check Poker Count 3 and 2 Register
24238  * - TRNG_PKRCNT54 - RNG Statistical Check Poker Count 5 and 4 Register
24239  * - TRNG_PKRCNT76 - RNG Statistical Check Poker Count 7 and 6 Register
24240  * - TRNG_PKRCNT98 - RNG Statistical Check Poker Count 9 and 8 Register
24241  * - TRNG_PKRCNTBA - RNG Statistical Check Poker Count B and A Register
24242  * - TRNG_PKRCNTDC - RNG Statistical Check Poker Count D and C Register
24243  * - TRNG_PKRCNTFE - RNG Statistical Check Poker Count F and E Register
24244  * - TRNG_SEC_CFG - RNG Security Configuration Register
24245  * - TRNG_INT_CTRL - RNG Interrupt Control Register
24246  * - TRNG_INT_MASK - RNG Mask Register
24247  * - TRNG_INT_STATUS - RNG Interrupt Status Register
24248  * - TRNG_VID1 - RNG Version ID Register (MS)
24249  * - TRNG_VID2 - RNG Version ID Register (LS)
24250  */
24251 
24252 #define TRNG_INSTANCE_COUNT (1U) /*!< Number of instances of the TRNG module. */
24253 #define TRNG0_IDX (0U) /*!< Instance number for TRNG0. */
24254 
24255 /*******************************************************************************
24256  * TRNG_MCTL - RNG Miscellaneous Control Register
24257  ******************************************************************************/
24258 
24259 /*!
24260  * @brief TRNG_MCTL - RNG Miscellaneous Control Register (RW)
24261  *
24262  * Reset value: 0x00012001U
24263  *
24264  * This register is intended to be used for programming, configuring and testing
24265  * the RNG. It is the main register to read/write, in order to enable Entropy
24266  * generation, to stop entropy generation and to block access to entropy registers.
24267  * This is done via the special TRNG_ACC and PRGM bits below. The RNG
24268  * Miscellaneous Control Register is a read/write register used to control the RNG's True
24269  * Random Number Generator (TRNG) access, operation and test. Note that in many
24270  * cases two RNG registers share the same address, and a particular register at the
24271  * shared address is selected based upon the value in the PRGM field of the MCTL
24272  * register.
24273  */
24274 /*!
24275  * @name Constants and macros for entire TRNG_MCTL register
24276  */
24277 /*@{*/
24278 #define TRNG_RD_MCTL(base)       (TRNG_MCTL_REG(base))
24279 #define TRNG_WR_MCTL(base, value) (TRNG_MCTL_REG(base) = (value))
24280 #define TRNG_RMW_MCTL(base, mask, value) (TRNG_WR_MCTL(base, (TRNG_RD_MCTL(base) & ~(mask)) | (value)))
24281 #define TRNG_SET_MCTL(base, value) (BME_OR32(&TRNG_MCTL_REG(base), (uint32_t)(value)))
24282 #define TRNG_CLR_MCTL(base, value) (BME_AND32(&TRNG_MCTL_REG(base), (uint32_t)(~(value))))
24283 #define TRNG_TOG_MCTL(base, value) (BME_XOR32(&TRNG_MCTL_REG(base), (uint32_t)(value)))
24284 /*@}*/
24285 
24286 /*
24287  * Constants & macros for individual TRNG_MCTL bitfields
24288  */
24289 
24290 /*!
24291  * @name Register TRNG_MCTL, field SAMP_MODE[1:0] (RW)
24292  *
24293  * Sample Mode. Determines the method of sampling the ring oscillator while
24294  * generating the Entropy value:This field is writable only if PRGM bit is 1, or PRGM
24295  * bit is being written to 1 simultaneously with writing this field. This field
24296  * is cleared to 01 by writing the RST_DEF bit to 1.
24297  *
24298  * Values:
24299  * - 0b00 - use Von Neumann data into both Entropy shifter and Statistical
24300  *     Checker
24301  * - 0b01 - use raw data into both Entropy shifter and Statistical Checker
24302  * - 0b10 - use Von Neumann data into Entropy shifter. Use raw data into
24303  *     Statistical Checker
24304  * - 0b11 - reserved.
24305  */
24306 /*@{*/
24307 /*! @brief Read current value of the TRNG_MCTL_SAMP_MODE field. */
24308 #define TRNG_RD_MCTL_SAMP_MODE(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_SAMP_MODE_MASK) >> TRNG_MCTL_SAMP_MODE_SHIFT)
24309 #define TRNG_BRD_MCTL_SAMP_MODE(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_SAMP_MODE_SHIFT, TRNG_MCTL_SAMP_MODE_WIDTH))
24310 
24311 /*! @brief Set the SAMP_MODE field to a new value. */
24312 #define TRNG_WR_MCTL_SAMP_MODE(base, value) (TRNG_RMW_MCTL(base, (TRNG_MCTL_SAMP_MODE_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_SAMP_MODE(value)))
24313 #define TRNG_BWR_MCTL_SAMP_MODE(base, value) (BME_BFI32(&TRNG_MCTL_REG(base), ((uint32_t)(value) << TRNG_MCTL_SAMP_MODE_SHIFT), TRNG_MCTL_SAMP_MODE_SHIFT, TRNG_MCTL_SAMP_MODE_WIDTH))
24314 /*@}*/
24315 
24316 /*!
24317  * @name Register TRNG_MCTL, field OSC_DIV[3:2] (RW)
24318  *
24319  * Oscillator Divide. Determines the amount of dividing done to the ring
24320  * oscillator before it is used by the TRNG.This field is writable only if PRGM bit is
24321  * 1, or PRGM bit is being written to 1 simultaneously to writing this field. This
24322  * field is cleared to 00 by writing the RST_DEF bit to 1.
24323  *
24324  * Values:
24325  * - 0b00 - use ring oscillator with no divide
24326  * - 0b01 - use ring oscillator divided-by-2
24327  * - 0b10 - use ring oscillator divided-by-4
24328  * - 0b11 - use ring oscillator divided-by-8
24329  */
24330 /*@{*/
24331 /*! @brief Read current value of the TRNG_MCTL_OSC_DIV field. */
24332 #define TRNG_RD_MCTL_OSC_DIV(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_OSC_DIV_MASK) >> TRNG_MCTL_OSC_DIV_SHIFT)
24333 #define TRNG_BRD_MCTL_OSC_DIV(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_OSC_DIV_SHIFT, TRNG_MCTL_OSC_DIV_WIDTH))
24334 
24335 /*! @brief Set the OSC_DIV field to a new value. */
24336 #define TRNG_WR_MCTL_OSC_DIV(base, value) (TRNG_RMW_MCTL(base, (TRNG_MCTL_OSC_DIV_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_OSC_DIV(value)))
24337 #define TRNG_BWR_MCTL_OSC_DIV(base, value) (BME_BFI32(&TRNG_MCTL_REG(base), ((uint32_t)(value) << TRNG_MCTL_OSC_DIV_SHIFT), TRNG_MCTL_OSC_DIV_SHIFT, TRNG_MCTL_OSC_DIV_WIDTH))
24338 /*@}*/
24339 
24340 /*!
24341  * @name Register TRNG_MCTL, field UNUSED[4] (RW)
24342  *
24343  * This bit is unused but write-able. Must be left as zero.
24344  */
24345 /*@{*/
24346 /*! @brief Read current value of the TRNG_MCTL_UNUSED field. */
24347 #define TRNG_RD_MCTL_UNUSED(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_UNUSED_MASK) >> TRNG_MCTL_UNUSED_SHIFT)
24348 #define TRNG_BRD_MCTL_UNUSED(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_UNUSED_SHIFT, TRNG_MCTL_UNUSED_WIDTH))
24349 
24350 /*! @brief Set the UNUSED field to a new value. */
24351 #define TRNG_WR_MCTL_UNUSED(base, value) (TRNG_RMW_MCTL(base, (TRNG_MCTL_UNUSED_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_UNUSED(value)))
24352 #define TRNG_BWR_MCTL_UNUSED(base, value) (BME_BFI32(&TRNG_MCTL_REG(base), ((uint32_t)(value) << TRNG_MCTL_UNUSED_SHIFT), TRNG_MCTL_UNUSED_SHIFT, TRNG_MCTL_UNUSED_WIDTH))
24353 /*@}*/
24354 
24355 /*!
24356  * @name Register TRNG_MCTL, field TRNG_ACC[5] (RW)
24357  *
24358  * TRNG Access Mode. If this bit is set to 1, the TRNG will generate an Entropy
24359  * value that can be read via the ENT0-ENT15 registers. The Entropy value may be
24360  * read once the ENT VAL bit is asserted. Also see ENTa register descriptions
24361  * (For a = 0 to 15).
24362  */
24363 /*@{*/
24364 /*! @brief Read current value of the TRNG_MCTL_TRNG_ACC field. */
24365 #define TRNG_RD_MCTL_TRNG_ACC(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TRNG_ACC_MASK) >> TRNG_MCTL_TRNG_ACC_SHIFT)
24366 #define TRNG_BRD_MCTL_TRNG_ACC(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_TRNG_ACC_SHIFT, TRNG_MCTL_TRNG_ACC_WIDTH))
24367 
24368 /*! @brief Set the TRNG_ACC field to a new value. */
24369 #define TRNG_WR_MCTL_TRNG_ACC(base, value) (TRNG_RMW_MCTL(base, (TRNG_MCTL_TRNG_ACC_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_TRNG_ACC(value)))
24370 #define TRNG_BWR_MCTL_TRNG_ACC(base, value) (BME_BFI32(&TRNG_MCTL_REG(base), ((uint32_t)(value) << TRNG_MCTL_TRNG_ACC_SHIFT), TRNG_MCTL_TRNG_ACC_SHIFT, TRNG_MCTL_TRNG_ACC_WIDTH))
24371 /*@}*/
24372 
24373 /*!
24374  * @name Register TRNG_MCTL, field RST_DEF[6] (WO)
24375  *
24376  * Reset Defaults. Writing a 1 to this bit clears various TRNG registers, and
24377  * bits within registers, to their default state. This bit is writable only if PRGM
24378  * bit is 1, or PRGM bit is being written to 1 simultaneously to writing this
24379  * bit. Reading this bit always produces a 0.
24380  */
24381 /*@{*/
24382 /*! @brief Set the RST_DEF field to a new value. */
24383 #define TRNG_WR_MCTL_RST_DEF(base, value) (TRNG_RMW_MCTL(base, (TRNG_MCTL_RST_DEF_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_RST_DEF(value)))
24384 #define TRNG_BWR_MCTL_RST_DEF(base, value) (TRNG_WR_MCTL_RST_DEF(base, value))
24385 /*@}*/
24386 
24387 /*!
24388  * @name Register TRNG_MCTL, field FOR_SCLK[7] (RW)
24389  *
24390  * Force System Clock. If set, the system clock is used to operate the TRNG,
24391  * instead of the ring oscillator. This is for test use only, and indeterminate
24392  * results may occur. This bit is writable only if PRGM bit is 1, or PRGM bit is
24393  * being written to 1 simultaneously to writing this bit. This bit is cleared by
24394  * writing the RST_DEF bit to 1.
24395  */
24396 /*@{*/
24397 /*! @brief Read current value of the TRNG_MCTL_FOR_SCLK field. */
24398 #define TRNG_RD_MCTL_FOR_SCLK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_FOR_SCLK_MASK) >> TRNG_MCTL_FOR_SCLK_SHIFT)
24399 #define TRNG_BRD_MCTL_FOR_SCLK(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_FOR_SCLK_SHIFT, TRNG_MCTL_FOR_SCLK_WIDTH))
24400 
24401 /*! @brief Set the FOR_SCLK field to a new value. */
24402 #define TRNG_WR_MCTL_FOR_SCLK(base, value) (TRNG_RMW_MCTL(base, (TRNG_MCTL_FOR_SCLK_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_FOR_SCLK(value)))
24403 #define TRNG_BWR_MCTL_FOR_SCLK(base, value) (BME_BFI32(&TRNG_MCTL_REG(base), ((uint32_t)(value) << TRNG_MCTL_FOR_SCLK_SHIFT), TRNG_MCTL_FOR_SCLK_SHIFT, TRNG_MCTL_FOR_SCLK_WIDTH))
24404 /*@}*/
24405 
24406 /*!
24407  * @name Register TRNG_MCTL, field FCT_FAIL[8] (RO)
24408  *
24409  * Read only: Frequency Count Fail. The frequency counter has detected a
24410  * failure. This may be due to improper programming of the FRQMAX and/or FRQMIN
24411  * registers, or a hardware failure in the ring oscillator. This error may be cleared by
24412  * writing a 1 to the ERR bit.
24413  */
24414 /*@{*/
24415 /*! @brief Read current value of the TRNG_MCTL_FCT_FAIL field. */
24416 #define TRNG_RD_MCTL_FCT_FAIL(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_FCT_FAIL_MASK) >> TRNG_MCTL_FCT_FAIL_SHIFT)
24417 #define TRNG_BRD_MCTL_FCT_FAIL(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_FCT_FAIL_SHIFT, TRNG_MCTL_FCT_FAIL_WIDTH))
24418 /*@}*/
24419 
24420 /*!
24421  * @name Register TRNG_MCTL, field FCT_VAL[9] (RO)
24422  *
24423  * Read only: Frequency Count Valid. Indicates that a valid frequency count may
24424  * be read from FRQCNT.
24425  */
24426 /*@{*/
24427 /*! @brief Read current value of the TRNG_MCTL_FCT_VAL field. */
24428 #define TRNG_RD_MCTL_FCT_VAL(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_FCT_VAL_MASK) >> TRNG_MCTL_FCT_VAL_SHIFT)
24429 #define TRNG_BRD_MCTL_FCT_VAL(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_FCT_VAL_SHIFT, TRNG_MCTL_FCT_VAL_WIDTH))
24430 /*@}*/
24431 
24432 /*!
24433  * @name Register TRNG_MCTL, field ENT_VAL[10] (RO)
24434  *
24435  * Read only: Entropy Valid. Will assert only if TRNG ACC bit is set, and then
24436  * after an entropy value is generated. Will be cleared when ENT15 is read. (ENT0
24437  * through ENT14 should be read before reading ENT15).
24438  */
24439 /*@{*/
24440 /*! @brief Read current value of the TRNG_MCTL_ENT_VAL field. */
24441 #define TRNG_RD_MCTL_ENT_VAL(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ENT_VAL_MASK) >> TRNG_MCTL_ENT_VAL_SHIFT)
24442 #define TRNG_BRD_MCTL_ENT_VAL(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_ENT_VAL_SHIFT, TRNG_MCTL_ENT_VAL_WIDTH))
24443 /*@}*/
24444 
24445 /*!
24446  * @name Register TRNG_MCTL, field TST_OUT[11] (RO)
24447  *
24448  * Read only: Test point inside ring oscillator.
24449  */
24450 /*@{*/
24451 /*! @brief Read current value of the TRNG_MCTL_TST_OUT field. */
24452 #define TRNG_RD_MCTL_TST_OUT(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TST_OUT_MASK) >> TRNG_MCTL_TST_OUT_SHIFT)
24453 #define TRNG_BRD_MCTL_TST_OUT(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_TST_OUT_SHIFT, TRNG_MCTL_TST_OUT_WIDTH))
24454 /*@}*/
24455 
24456 /*!
24457  * @name Register TRNG_MCTL, field ERR[12] (W1C)
24458  *
24459  * Read: Error status. 1 = error detected. 0 = no error.Write: Write 1 to clear
24460  * errors. Writing 0 has no effect.
24461  */
24462 /*@{*/
24463 /*! @brief Read current value of the TRNG_MCTL_ERR field. */
24464 #define TRNG_RD_MCTL_ERR(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_ERR_MASK) >> TRNG_MCTL_ERR_SHIFT)
24465 #define TRNG_BRD_MCTL_ERR(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_ERR_SHIFT, TRNG_MCTL_ERR_WIDTH))
24466 
24467 /*! @brief Set the ERR field to a new value. */
24468 #define TRNG_WR_MCTL_ERR(base, value) (TRNG_RMW_MCTL(base, TRNG_MCTL_ERR_MASK, TRNG_MCTL_ERR(value)))
24469 #define TRNG_BWR_MCTL_ERR(base, value) (BME_BFI32(&TRNG_MCTL_REG(base), ((uint32_t)(value) << TRNG_MCTL_ERR_SHIFT), TRNG_MCTL_ERR_SHIFT, TRNG_MCTL_ERR_WIDTH))
24470 /*@}*/
24471 
24472 /*!
24473  * @name Register TRNG_MCTL, field TSTOP_OK[13] (RO)
24474  *
24475  * TRNG_OK_TO_STOP. Software should check that this bit is a 1 before
24476  * transitioning RNG to low power mode (RNG clock stopped). RNG turns on the TRNG
24477  * free-running ring oscillator whenever new entropy is being generated and turns off the
24478  * ring oscillator when entropy generation is complete. If the RNG clock is
24479  * stopped while the TRNG ring oscillator is running, the oscillator will continue
24480  * running even though the RNG clock is stopped. TSTOP_OK is asserted when the TRNG
24481  * ring oscillator is not running. and therefore it is ok to stop the RNG clock.
24482  */
24483 /*@{*/
24484 /*! @brief Read current value of the TRNG_MCTL_TSTOP_OK field. */
24485 #define TRNG_RD_MCTL_TSTOP_OK(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_TSTOP_OK_MASK) >> TRNG_MCTL_TSTOP_OK_SHIFT)
24486 #define TRNG_BRD_MCTL_TSTOP_OK(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_TSTOP_OK_SHIFT, TRNG_MCTL_TSTOP_OK_WIDTH))
24487 /*@}*/
24488 
24489 /*!
24490  * @name Register TRNG_MCTL, field PRGM[16] (RW)
24491  *
24492  * Programming Mode Select. When this bit is 1, the TRNG is in Program Mode,
24493  * otherwise it is in Run Mode. No Entropy value will be generated while the TRNG is
24494  * in Program Mode. Note that different RNG registers are accessible at the same
24495  * address depending on whether PRGM is set to 1 or 0. This is noted in the RNG
24496  * register descriptions.
24497  */
24498 /*@{*/
24499 /*! @brief Read current value of the TRNG_MCTL_PRGM field. */
24500 #define TRNG_RD_MCTL_PRGM(base) ((TRNG_MCTL_REG(base) & TRNG_MCTL_PRGM_MASK) >> TRNG_MCTL_PRGM_SHIFT)
24501 #define TRNG_BRD_MCTL_PRGM(base) (BME_UBFX32(&TRNG_MCTL_REG(base), TRNG_MCTL_PRGM_SHIFT, TRNG_MCTL_PRGM_WIDTH))
24502 
24503 /*! @brief Set the PRGM field to a new value. */
24504 #define TRNG_WR_MCTL_PRGM(base, value) (TRNG_RMW_MCTL(base, (TRNG_MCTL_PRGM_MASK | TRNG_MCTL_ERR_MASK), TRNG_MCTL_PRGM(value)))
24505 #define TRNG_BWR_MCTL_PRGM(base, value) (BME_BFI32(&TRNG_MCTL_REG(base), ((uint32_t)(value) << TRNG_MCTL_PRGM_SHIFT), TRNG_MCTL_PRGM_SHIFT, TRNG_MCTL_PRGM_WIDTH))
24506 /*@}*/
24507 
24508 /*******************************************************************************
24509  * TRNG_SCMISC - RNG Statistical Check Miscellaneous Register
24510  ******************************************************************************/
24511 
24512 /*!
24513  * @brief TRNG_SCMISC - RNG Statistical Check Miscellaneous Register (RW)
24514  *
24515  * Reset value: 0x0001001FU
24516  *
24517  * The RNG Statistical Check Miscellaneous Register contains the Long Run
24518  * Maximum Limit value and the Retry Count value. This register is accessible only when
24519  * the MCTL[PRGM] bit is 1, otherwise this register will read zeroes, and cannot
24520  * be written.
24521  */
24522 /*!
24523  * @name Constants and macros for entire TRNG_SCMISC register
24524  */
24525 /*@{*/
24526 #define TRNG_RD_SCMISC(base)     (TRNG_SCMISC_REG(base))
24527 #define TRNG_WR_SCMISC(base, value) (TRNG_SCMISC_REG(base) = (value))
24528 #define TRNG_RMW_SCMISC(base, mask, value) (TRNG_WR_SCMISC(base, (TRNG_RD_SCMISC(base) & ~(mask)) | (value)))
24529 #define TRNG_SET_SCMISC(base, value) (BME_OR32(&TRNG_SCMISC_REG(base), (uint32_t)(value)))
24530 #define TRNG_CLR_SCMISC(base, value) (BME_AND32(&TRNG_SCMISC_REG(base), (uint32_t)(~(value))))
24531 #define TRNG_TOG_SCMISC(base, value) (BME_XOR32(&TRNG_SCMISC_REG(base), (uint32_t)(value)))
24532 /*@}*/
24533 
24534 /*
24535  * Constants & macros for individual TRNG_SCMISC bitfields
24536  */
24537 
24538 /*!
24539  * @name Register TRNG_SCMISC, field LRUN_MAX[7:0] (RW)
24540  *
24541  * LONG RUN MAX LIMIT. This value is the largest allowable number of consecutive
24542  * samples of all 1, or all 0, that is allowed during the Entropy generation.
24543  * This field is writable only if MCTL[PRGM] bit is 1. This field will read zeroes
24544  * if MCTL[PRGM] = 0. This field is cleared to 22h by writing the MCTL[RST_DEF]
24545  * bit to 1.
24546  */
24547 /*@{*/
24548 /*! @brief Read current value of the TRNG_SCMISC_LRUN_MAX field. */
24549 #define TRNG_RD_SCMISC_LRUN_MAX(base) ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_LRUN_MAX_MASK) >> TRNG_SCMISC_LRUN_MAX_SHIFT)
24550 #define TRNG_BRD_SCMISC_LRUN_MAX(base) (BME_UBFX32(&TRNG_SCMISC_REG(base), TRNG_SCMISC_LRUN_MAX_SHIFT, TRNG_SCMISC_LRUN_MAX_WIDTH))
24551 
24552 /*! @brief Set the LRUN_MAX field to a new value. */
24553 #define TRNG_WR_SCMISC_LRUN_MAX(base, value) (TRNG_RMW_SCMISC(base, TRNG_SCMISC_LRUN_MAX_MASK, TRNG_SCMISC_LRUN_MAX(value)))
24554 #define TRNG_BWR_SCMISC_LRUN_MAX(base, value) (BME_BFI32(&TRNG_SCMISC_REG(base), ((uint32_t)(value) << TRNG_SCMISC_LRUN_MAX_SHIFT), TRNG_SCMISC_LRUN_MAX_SHIFT, TRNG_SCMISC_LRUN_MAX_WIDTH))
24555 /*@}*/
24556 
24557 /*!
24558  * @name Register TRNG_SCMISC, field RTY_CT[19:16] (RW)
24559  *
24560  * RETRY COUNT. If a statistical check fails during the TRNG Entropy Generation,
24561  * the RTY_CT value indicates the number of times a retry should occur before
24562  * generating an error. This field is writable only if MCTL[PRGM] bit is 1. This
24563  * field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 1h by writing
24564  * the MCTL[RST_DEF] bit to 1.
24565  */
24566 /*@{*/
24567 /*! @brief Read current value of the TRNG_SCMISC_RTY_CT field. */
24568 #define TRNG_RD_SCMISC_RTY_CT(base) ((TRNG_SCMISC_REG(base) & TRNG_SCMISC_RTY_CT_MASK) >> TRNG_SCMISC_RTY_CT_SHIFT)
24569 #define TRNG_BRD_SCMISC_RTY_CT(base) (BME_UBFX32(&TRNG_SCMISC_REG(base), TRNG_SCMISC_RTY_CT_SHIFT, TRNG_SCMISC_RTY_CT_WIDTH))
24570 
24571 /*! @brief Set the RTY_CT field to a new value. */
24572 #define TRNG_WR_SCMISC_RTY_CT(base, value) (TRNG_RMW_SCMISC(base, TRNG_SCMISC_RTY_CT_MASK, TRNG_SCMISC_RTY_CT(value)))
24573 #define TRNG_BWR_SCMISC_RTY_CT(base, value) (BME_BFI32(&TRNG_SCMISC_REG(base), ((uint32_t)(value) << TRNG_SCMISC_RTY_CT_SHIFT), TRNG_SCMISC_RTY_CT_SHIFT, TRNG_SCMISC_RTY_CT_WIDTH))
24574 /*@}*/
24575 
24576 /*******************************************************************************
24577  * TRNG_PKRRNG - RNG Poker Range Register
24578  ******************************************************************************/
24579 
24580 /*!
24581  * @brief TRNG_PKRRNG - RNG Poker Range Register (RW)
24582  *
24583  * Reset value: 0x000009A3U
24584  *
24585  * The RNG Poker Range Register defines the difference between the TRNG Poker
24586  * Maximum Limit and the minimum limit. These limits are used during the TRNG
24587  * Statistical Check Poker Test.
24588  */
24589 /*!
24590  * @name Constants and macros for entire TRNG_PKRRNG register
24591  */
24592 /*@{*/
24593 #define TRNG_RD_PKRRNG(base)     (TRNG_PKRRNG_REG(base))
24594 #define TRNG_WR_PKRRNG(base, value) (TRNG_PKRRNG_REG(base) = (value))
24595 #define TRNG_RMW_PKRRNG(base, mask, value) (TRNG_WR_PKRRNG(base, (TRNG_RD_PKRRNG(base) & ~(mask)) | (value)))
24596 #define TRNG_SET_PKRRNG(base, value) (BME_OR32(&TRNG_PKRRNG_REG(base), (uint32_t)(value)))
24597 #define TRNG_CLR_PKRRNG(base, value) (BME_AND32(&TRNG_PKRRNG_REG(base), (uint32_t)(~(value))))
24598 #define TRNG_TOG_PKRRNG(base, value) (BME_XOR32(&TRNG_PKRRNG_REG(base), (uint32_t)(value)))
24599 /*@}*/
24600 
24601 /*
24602  * Constants & macros for individual TRNG_PKRRNG bitfields
24603  */
24604 
24605 /*!
24606  * @name Register TRNG_PKRRNG, field PKR_RNG[15:0] (RW)
24607  *
24608  * Poker Range. During the TRNG Statistical Checks, a "Poker Test" is run which
24609  * requires a maximum and minimum limit. The maximum is programmed in the
24610  * RTPKRMAX[PKR_MAX] register, and the minimum is derived by subtracting the PKR_RNG
24611  * value from the programmed maximum value. This field is writable only if
24612  * MCTL[PRGM] bit is 1. This field will read zeroes if MCTL[PRGM] = 0. This field is
24613  * cleared to 09A3h (decimal 2467) by writing the MCTL[RST_DEF] bit to 1. Note that
24614  * the minimum allowable Poker result is PKR_MAX - PKR_RNG + 1.
24615  */
24616 /*@{*/
24617 /*! @brief Read current value of the TRNG_PKRRNG_PKR_RNG field. */
24618 #define TRNG_RD_PKRRNG_PKR_RNG(base) ((TRNG_PKRRNG_REG(base) & TRNG_PKRRNG_PKR_RNG_MASK) >> TRNG_PKRRNG_PKR_RNG_SHIFT)
24619 #define TRNG_BRD_PKRRNG_PKR_RNG(base) (BME_UBFX32(&TRNG_PKRRNG_REG(base), TRNG_PKRRNG_PKR_RNG_SHIFT, TRNG_PKRRNG_PKR_RNG_WIDTH))
24620 
24621 /*! @brief Set the PKR_RNG field to a new value. */
24622 #define TRNG_WR_PKRRNG_PKR_RNG(base, value) (TRNG_RMW_PKRRNG(base, TRNG_PKRRNG_PKR_RNG_MASK, TRNG_PKRRNG_PKR_RNG(value)))
24623 #define TRNG_BWR_PKRRNG_PKR_RNG(base, value) (BME_BFI32(&TRNG_PKRRNG_REG(base), ((uint32_t)(value) << TRNG_PKRRNG_PKR_RNG_SHIFT), TRNG_PKRRNG_PKR_RNG_SHIFT, TRNG_PKRRNG_PKR_RNG_WIDTH))
24624 /*@}*/
24625 
24626 /*******************************************************************************
24627  * TRNG_PKRMAX - RNG Poker Maximum Limit Register
24628  ******************************************************************************/
24629 
24630 /*!
24631  * @brief TRNG_PKRMAX - RNG Poker Maximum Limit Register (RW)
24632  *
24633  * Reset value: 0x00006920U
24634  *
24635  * The RNG Poker Maximum Limit Register defines Maximum Limit allowable during
24636  * the TRNG Statistical Check Poker Test. Note that this offset (0xBASE_060C) is
24637  * used as PKRMAX only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is used
24638  * as the PKRSQ readback register.
24639  */
24640 /*!
24641  * @name Constants and macros for entire TRNG_PKRMAX register
24642  */
24643 /*@{*/
24644 #define TRNG_RD_PKRMAX(base)     (TRNG_PKRMAX_REG(base))
24645 #define TRNG_WR_PKRMAX(base, value) (TRNG_PKRMAX_REG(base) = (value))
24646 #define TRNG_RMW_PKRMAX(base, mask, value) (TRNG_WR_PKRMAX(base, (TRNG_RD_PKRMAX(base) & ~(mask)) | (value)))
24647 #define TRNG_SET_PKRMAX(base, value) (BME_OR32(&TRNG_PKRMAX_REG(base), (uint32_t)(value)))
24648 #define TRNG_CLR_PKRMAX(base, value) (BME_AND32(&TRNG_PKRMAX_REG(base), (uint32_t)(~(value))))
24649 #define TRNG_TOG_PKRMAX(base, value) (BME_XOR32(&TRNG_PKRMAX_REG(base), (uint32_t)(value)))
24650 /*@}*/
24651 
24652 /*
24653  * Constants & macros for individual TRNG_PKRMAX bitfields
24654  */
24655 
24656 /*!
24657  * @name Register TRNG_PKRMAX, field PKR_MAX[23:0] (RW)
24658  *
24659  * Poker Maximum Limit. During the TRNG Statistical Checks, a "Poker Test" is
24660  * run which requires a maximum and minimum limit. The maximum allowable result is
24661  * programmed in the PKRMAX[PKR_MAX] register. This field is writable only if
24662  * MCTL[PRGM] bit is 1. This register is cleared to 006920h (decimal 26912) by
24663  * writing the MCTL[RST_DEF] bit to 1. Note that the PKRMAX and PKRRNG registers
24664  * combined are used to define the minimum allowable Poker result, which is PKR_MAX -
24665  * PKR_RNG + 1. Note that if MCTL[PRGM] bit is 0, this register address is used
24666  * to read the Poker Test Square Calculation result in register PKRSQ, as defined
24667  * in the following section.
24668  */
24669 /*@{*/
24670 /*! @brief Read current value of the TRNG_PKRMAX_PKR_MAX field. */
24671 #define TRNG_RD_PKRMAX_PKR_MAX(base) ((TRNG_PKRMAX_REG(base) & TRNG_PKRMAX_PKR_MAX_MASK) >> TRNG_PKRMAX_PKR_MAX_SHIFT)
24672 #define TRNG_BRD_PKRMAX_PKR_MAX(base) (TRNG_RD_PKRMAX_PKR_MAX(base))
24673 
24674 /*! @brief Set the PKR_MAX field to a new value. */
24675 #define TRNG_WR_PKRMAX_PKR_MAX(base, value) (TRNG_RMW_PKRMAX(base, TRNG_PKRMAX_PKR_MAX_MASK, TRNG_PKRMAX_PKR_MAX(value)))
24676 #define TRNG_BWR_PKRMAX_PKR_MAX(base, value) (TRNG_WR_PKRMAX_PKR_MAX(base, value))
24677 /*@}*/
24678 
24679 /*******************************************************************************
24680  * TRNG_PKRSQ - RNG Poker Square Calculation Result Register
24681  ******************************************************************************/
24682 
24683 /*!
24684  * @brief TRNG_PKRSQ - RNG Poker Square Calculation Result Register (RO)
24685  *
24686  * Reset value: 0x00000000U
24687  *
24688  * The RNG Poker Square Calculation Result Register is a read-only register used
24689  * to read the result of the TRNG Statistical Check Poker Test's Square
24690  * Calculation. This test starts with the PKRMAX value and decreases towards a final
24691  * result, which is read here. For the Poker Test to pass, this final result must be
24692  * less than the programmed PKRRNG value. Note that this offset (0xBASE_060C) is
24693  * used as PKRMAX if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is used as
24694  * PKRSQ readback register, as described here.
24695  */
24696 /*!
24697  * @name Constants and macros for entire TRNG_PKRSQ register
24698  */
24699 /*@{*/
24700 #define TRNG_RD_PKRSQ(base)      (TRNG_PKRSQ_REG(base))
24701 /*@}*/
24702 
24703 /*
24704  * Constants & macros for individual TRNG_PKRSQ bitfields
24705  */
24706 
24707 /*!
24708  * @name Register TRNG_PKRSQ, field PKR_SQ[23:0] (RO)
24709  *
24710  * Poker Square Calculation Result. During the TRNG Statistical Checks, a "Poker
24711  * Test" is run which starts with the value PKRMAX[PKR_MAX]. This value
24712  * decreases according to a "sum of squares" algorithm, and must remain greater than
24713  * zero, but less than the PKRRNG[PKR_RNG] limit. The resulting value may be read
24714  * through this register, if MCTL[PRGM] bit is 0. Note that if MCTL[PRGM] bit is 1,
24715  * this register address is used to access the Poker Test Maximum Limit in
24716  * register PKRMAX, as defined in the previous section.
24717  */
24718 /*@{*/
24719 /*! @brief Read current value of the TRNG_PKRSQ_PKR_SQ field. */
24720 #define TRNG_RD_PKRSQ_PKR_SQ(base) ((TRNG_PKRSQ_REG(base) & TRNG_PKRSQ_PKR_SQ_MASK) >> TRNG_PKRSQ_PKR_SQ_SHIFT)
24721 #define TRNG_BRD_PKRSQ_PKR_SQ(base) (TRNG_RD_PKRSQ_PKR_SQ(base))
24722 /*@}*/
24723 
24724 /*******************************************************************************
24725  * TRNG_SDCTL - RNG Seed Control Register
24726  ******************************************************************************/
24727 
24728 /*!
24729  * @brief TRNG_SDCTL - RNG Seed Control Register (RW)
24730  *
24731  * Reset value: 0x0C8009C4U
24732  *
24733  * The RNG Seed Control Register contains two fields. One field defines the
24734  * length (in system clocks) of each Entropy sample (ENT_DLY), and the other field
24735  * indicates the number of samples that will taken during each TRNG Entropy
24736  * generation (SAMP_SIZE).
24737  */
24738 /*!
24739  * @name Constants and macros for entire TRNG_SDCTL register
24740  */
24741 /*@{*/
24742 #define TRNG_RD_SDCTL(base)      (TRNG_SDCTL_REG(base))
24743 #define TRNG_WR_SDCTL(base, value) (TRNG_SDCTL_REG(base) = (value))
24744 #define TRNG_RMW_SDCTL(base, mask, value) (TRNG_WR_SDCTL(base, (TRNG_RD_SDCTL(base) & ~(mask)) | (value)))
24745 #define TRNG_SET_SDCTL(base, value) (BME_OR32(&TRNG_SDCTL_REG(base), (uint32_t)(value)))
24746 #define TRNG_CLR_SDCTL(base, value) (BME_AND32(&TRNG_SDCTL_REG(base), (uint32_t)(~(value))))
24747 #define TRNG_TOG_SDCTL(base, value) (BME_XOR32(&TRNG_SDCTL_REG(base), (uint32_t)(value)))
24748 /*@}*/
24749 
24750 /*
24751  * Constants & macros for individual TRNG_SDCTL bitfields
24752  */
24753 
24754 /*!
24755  * @name Register TRNG_SDCTL, field SAMP_SIZE[15:0] (RW)
24756  *
24757  * Sample Size. Defines the total number of Entropy samples that will be taken
24758  * during Entropy generation. This field is writable only if MCTL[PRGM] bit is 1.
24759  * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 09C4h
24760  * (decimal 2500) by writing the MCTL[RST_DEF] bit to 1.
24761  */
24762 /*@{*/
24763 /*! @brief Read current value of the TRNG_SDCTL_SAMP_SIZE field. */
24764 #define TRNG_RD_SDCTL_SAMP_SIZE(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_SAMP_SIZE_MASK) >> TRNG_SDCTL_SAMP_SIZE_SHIFT)
24765 #define TRNG_BRD_SDCTL_SAMP_SIZE(base) (BME_UBFX32(&TRNG_SDCTL_REG(base), TRNG_SDCTL_SAMP_SIZE_SHIFT, TRNG_SDCTL_SAMP_SIZE_WIDTH))
24766 
24767 /*! @brief Set the SAMP_SIZE field to a new value. */
24768 #define TRNG_WR_SDCTL_SAMP_SIZE(base, value) (TRNG_RMW_SDCTL(base, TRNG_SDCTL_SAMP_SIZE_MASK, TRNG_SDCTL_SAMP_SIZE(value)))
24769 #define TRNG_BWR_SDCTL_SAMP_SIZE(base, value) (BME_BFI32(&TRNG_SDCTL_REG(base), ((uint32_t)(value) << TRNG_SDCTL_SAMP_SIZE_SHIFT), TRNG_SDCTL_SAMP_SIZE_SHIFT, TRNG_SDCTL_SAMP_SIZE_WIDTH))
24770 /*@}*/
24771 
24772 /*!
24773  * @name Register TRNG_SDCTL, field ENT_DLY[31:16] (RW)
24774  *
24775  * Entropy Delay. Defines the length (in system clocks) of each Entropy sample
24776  * taken. This field is writable only if MCTL[PRGM] bit is 1. This field will read
24777  * zeroes if MCTL[PRGM] = 0. This field is cleared to 0C80h (decimal 3200) by
24778  * writing the MCTL[RST_DEF] bit to 1.
24779  */
24780 /*@{*/
24781 /*! @brief Read current value of the TRNG_SDCTL_ENT_DLY field. */
24782 #define TRNG_RD_SDCTL_ENT_DLY(base) ((TRNG_SDCTL_REG(base) & TRNG_SDCTL_ENT_DLY_MASK) >> TRNG_SDCTL_ENT_DLY_SHIFT)
24783 #define TRNG_BRD_SDCTL_ENT_DLY(base) (BME_UBFX32(&TRNG_SDCTL_REG(base), TRNG_SDCTL_ENT_DLY_SHIFT, TRNG_SDCTL_ENT_DLY_WIDTH))
24784 
24785 /*! @brief Set the ENT_DLY field to a new value. */
24786 #define TRNG_WR_SDCTL_ENT_DLY(base, value) (TRNG_RMW_SDCTL(base, TRNG_SDCTL_ENT_DLY_MASK, TRNG_SDCTL_ENT_DLY(value)))
24787 #define TRNG_BWR_SDCTL_ENT_DLY(base, value) (BME_BFI32(&TRNG_SDCTL_REG(base), ((uint32_t)(value) << TRNG_SDCTL_ENT_DLY_SHIFT), TRNG_SDCTL_ENT_DLY_SHIFT, TRNG_SDCTL_ENT_DLY_WIDTH))
24788 /*@}*/
24789 
24790 /*******************************************************************************
24791  * TRNG_SBLIM - RNG Sparse Bit Limit Register
24792  ******************************************************************************/
24793 
24794 /*!
24795  * @brief TRNG_SBLIM - RNG Sparse Bit Limit Register (RW)
24796  *
24797  * Reset value: 0x0000003FU
24798  *
24799  * The RNG Sparse Bit Limit Register is used when Von Neumann sampling is
24800  * selected during Entropy Generation. It defines the maximum number of consecutive Von
24801  * Neumann samples which may be discarded before an error is generated. Note
24802  * that this address (0xBASE_0614) is used as SBLIM only if MCTL[PRGM] is 1. If
24803  * MCTL[PRGM] is 0, this address is used as TOTSAM readback register.
24804  */
24805 /*!
24806  * @name Constants and macros for entire TRNG_SBLIM register
24807  */
24808 /*@{*/
24809 #define TRNG_RD_SBLIM(base)      (TRNG_SBLIM_REG(base))
24810 #define TRNG_WR_SBLIM(base, value) (TRNG_SBLIM_REG(base) = (value))
24811 #define TRNG_RMW_SBLIM(base, mask, value) (TRNG_WR_SBLIM(base, (TRNG_RD_SBLIM(base) & ~(mask)) | (value)))
24812 #define TRNG_SET_SBLIM(base, value) (BME_OR32(&TRNG_SBLIM_REG(base), (uint32_t)(value)))
24813 #define TRNG_CLR_SBLIM(base, value) (BME_AND32(&TRNG_SBLIM_REG(base), (uint32_t)(~(value))))
24814 #define TRNG_TOG_SBLIM(base, value) (BME_XOR32(&TRNG_SBLIM_REG(base), (uint32_t)(value)))
24815 /*@}*/
24816 
24817 /*
24818  * Constants & macros for individual TRNG_SBLIM bitfields
24819  */
24820 
24821 /*!
24822  * @name Register TRNG_SBLIM, field SB_LIM[9:0] (RW)
24823  *
24824  * Sparse Bit Limit. During Von Neumann sampling (if enabled by MCTL[SAMP_MODE],
24825  * samples are discarded if two consecutive raw samples are both 0 or both 1. If
24826  * this discarding occurs for a long period of time, it indicates that there is
24827  * insufficient Entropy. The Sparse Bit Limit defines the maximum number of
24828  * consecutive samples that may be discarded before an error is generated. This field
24829  * is writable only if MCTL[PRGM] bit is 1. This register is cleared to 03hF by
24830  * writing the MCTL[RST_DEF] bit to 1. Note that if MCTL[PRGM] bit is 0, this
24831  * register address is used to read the Total Samples count in register TOTSAM, as
24832  * defined in the following section.
24833  */
24834 /*@{*/
24835 /*! @brief Read current value of the TRNG_SBLIM_SB_LIM field. */
24836 #define TRNG_RD_SBLIM_SB_LIM(base) ((TRNG_SBLIM_REG(base) & TRNG_SBLIM_SB_LIM_MASK) >> TRNG_SBLIM_SB_LIM_SHIFT)
24837 #define TRNG_BRD_SBLIM_SB_LIM(base) (BME_UBFX32(&TRNG_SBLIM_REG(base), TRNG_SBLIM_SB_LIM_SHIFT, TRNG_SBLIM_SB_LIM_WIDTH))
24838 
24839 /*! @brief Set the SB_LIM field to a new value. */
24840 #define TRNG_WR_SBLIM_SB_LIM(base, value) (TRNG_RMW_SBLIM(base, TRNG_SBLIM_SB_LIM_MASK, TRNG_SBLIM_SB_LIM(value)))
24841 #define TRNG_BWR_SBLIM_SB_LIM(base, value) (BME_BFI32(&TRNG_SBLIM_REG(base), ((uint32_t)(value) << TRNG_SBLIM_SB_LIM_SHIFT), TRNG_SBLIM_SB_LIM_SHIFT, TRNG_SBLIM_SB_LIM_WIDTH))
24842 /*@}*/
24843 
24844 /*******************************************************************************
24845  * TRNG_TOTSAM - RNG Total Samples Register
24846  ******************************************************************************/
24847 
24848 /*!
24849  * @brief TRNG_TOTSAM - RNG Total Samples Register (RO)
24850  *
24851  * Reset value: 0x00000000U
24852  *
24853  * The RNG Total Samples Register is a read-only register used to read the total
24854  * number of samples taken during Entropy generation. It is used to give an
24855  * indication of how often a sample is actually used during Von Neumann sampling.
24856  * Note that this offset (0xBASE_0614) is used as SBLIM if MCTL[PRGM] is 1. If
24857  * MCTL[PRGM] is 0, this offset is used as TOTSAM readback register, as described here.
24858  */
24859 /*!
24860  * @name Constants and macros for entire TRNG_TOTSAM register
24861  */
24862 /*@{*/
24863 #define TRNG_RD_TOTSAM(base)     (TRNG_TOTSAM_REG(base))
24864 /*@}*/
24865 
24866 /*
24867  * Constants & macros for individual TRNG_TOTSAM bitfields
24868  */
24869 
24870 /*!
24871  * @name Register TRNG_TOTSAM, field TOT_SAM[19:0] (RO)
24872  *
24873  * Total Samples. During Entropy generation, the total number of raw samples is
24874  * counted. This count is useful in determining how often a sample is used during
24875  * Von Neumann sampling. The count may be read through this register, if
24876  * MCTL[PRGM] bit is 0. Note that if MCTL[PRGM] bit is 1, this register address is used
24877  * to access the Sparse Bit Limit in register SBLIM, as defined in the previous
24878  * section.
24879  */
24880 /*@{*/
24881 /*! @brief Read current value of the TRNG_TOTSAM_TOT_SAM field. */
24882 #define TRNG_RD_TOTSAM_TOT_SAM(base) ((TRNG_TOTSAM_REG(base) & TRNG_TOTSAM_TOT_SAM_MASK) >> TRNG_TOTSAM_TOT_SAM_SHIFT)
24883 #define TRNG_BRD_TOTSAM_TOT_SAM(base) (TRNG_RD_TOTSAM_TOT_SAM(base))
24884 /*@}*/
24885 
24886 /*******************************************************************************
24887  * TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register
24888  ******************************************************************************/
24889 
24890 /*!
24891  * @brief TRNG_FRQMIN - RNG Frequency Count Minimum Limit Register (RW)
24892  *
24893  * Reset value: 0x00000640U
24894  *
24895  * The RNG Frequency Count Minimum Limit Register defines the minimum allowable
24896  * count taken by the Entropy sample counter during each Entropy sample. During
24897  * any sample period, if the count is less than this programmed minimum, a
24898  * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated.
24899  */
24900 /*!
24901  * @name Constants and macros for entire TRNG_FRQMIN register
24902  */
24903 /*@{*/
24904 #define TRNG_RD_FRQMIN(base)     (TRNG_FRQMIN_REG(base))
24905 #define TRNG_WR_FRQMIN(base, value) (TRNG_FRQMIN_REG(base) = (value))
24906 #define TRNG_RMW_FRQMIN(base, mask, value) (TRNG_WR_FRQMIN(base, (TRNG_RD_FRQMIN(base) & ~(mask)) | (value)))
24907 #define TRNG_SET_FRQMIN(base, value) (BME_OR32(&TRNG_FRQMIN_REG(base), (uint32_t)(value)))
24908 #define TRNG_CLR_FRQMIN(base, value) (BME_AND32(&TRNG_FRQMIN_REG(base), (uint32_t)(~(value))))
24909 #define TRNG_TOG_FRQMIN(base, value) (BME_XOR32(&TRNG_FRQMIN_REG(base), (uint32_t)(value)))
24910 /*@}*/
24911 
24912 /*
24913  * Constants & macros for individual TRNG_FRQMIN bitfields
24914  */
24915 
24916 /*!
24917  * @name Register TRNG_FRQMIN, field FRQ_MIN[21:0] (RW)
24918  *
24919  * Frequency Count Minimum Limit. Defines the minimum allowable count taken
24920  * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1.
24921  * This field will read zeroes if MCTL[PRGM] = 0. This field is cleared to 0000h64
24922  * by writing the MCTL[RST_DEF] bit to 1.
24923  */
24924 /*@{*/
24925 /*! @brief Read current value of the TRNG_FRQMIN_FRQ_MIN field. */
24926 #define TRNG_RD_FRQMIN_FRQ_MIN(base) ((TRNG_FRQMIN_REG(base) & TRNG_FRQMIN_FRQ_MIN_MASK) >> TRNG_FRQMIN_FRQ_MIN_SHIFT)
24927 #define TRNG_BRD_FRQMIN_FRQ_MIN(base) (TRNG_RD_FRQMIN_FRQ_MIN(base))
24928 
24929 /*! @brief Set the FRQ_MIN field to a new value. */
24930 #define TRNG_WR_FRQMIN_FRQ_MIN(base, value) (TRNG_RMW_FRQMIN(base, TRNG_FRQMIN_FRQ_MIN_MASK, TRNG_FRQMIN_FRQ_MIN(value)))
24931 #define TRNG_BWR_FRQMIN_FRQ_MIN(base, value) (TRNG_WR_FRQMIN_FRQ_MIN(base, value))
24932 /*@}*/
24933 
24934 /*******************************************************************************
24935  * TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register
24936  ******************************************************************************/
24937 
24938 /*!
24939  * @brief TRNG_FRQMAX - RNG Frequency Count Maximum Limit Register (RW)
24940  *
24941  * Reset value: 0x00006400U
24942  *
24943  * The RNG Frequency Count Maximum Limit Register defines the maximum allowable
24944  * count taken by the Entropy sample counter during each Entropy sample. During
24945  * any sample period, if the count is greater than this programmed maximum, a
24946  * Frequency Count Fail is flagged in MCTL[FCT_FAIL] and an error is generated. Note
24947  * that this address (061C) is used as FRQMAX only if MCTL[PRGM] is 1. If
24948  * MCTL[PRGM] is 0, this address is used as FRQCNT readback register.
24949  */
24950 /*!
24951  * @name Constants and macros for entire TRNG_FRQMAX register
24952  */
24953 /*@{*/
24954 #define TRNG_RD_FRQMAX(base)     (TRNG_FRQMAX_REG(base))
24955 #define TRNG_WR_FRQMAX(base, value) (TRNG_FRQMAX_REG(base) = (value))
24956 #define TRNG_RMW_FRQMAX(base, mask, value) (TRNG_WR_FRQMAX(base, (TRNG_RD_FRQMAX(base) & ~(mask)) | (value)))
24957 #define TRNG_SET_FRQMAX(base, value) (BME_OR32(&TRNG_FRQMAX_REG(base), (uint32_t)(value)))
24958 #define TRNG_CLR_FRQMAX(base, value) (BME_AND32(&TRNG_FRQMAX_REG(base), (uint32_t)(~(value))))
24959 #define TRNG_TOG_FRQMAX(base, value) (BME_XOR32(&TRNG_FRQMAX_REG(base), (uint32_t)(value)))
24960 /*@}*/
24961 
24962 /*
24963  * Constants & macros for individual TRNG_FRQMAX bitfields
24964  */
24965 
24966 /*!
24967  * @name Register TRNG_FRQMAX, field FRQ_MAX[21:0] (RW)
24968  *
24969  * Frequency Counter Maximum Limit. Defines the maximum allowable count taken
24970  * during each entropy sample. This field is writable only if MCTL[PRGM] bit is 1.
24971  * This register is cleared to 000640h by writing the MCTL[RST_DEF] bit to 1.
24972  * Note that if MCTL[PRGM] bit is 0, this register address is used to read the
24973  * Frequency Count result in register FRQCNT, as defined in the following section.
24974  */
24975 /*@{*/
24976 /*! @brief Read current value of the TRNG_FRQMAX_FRQ_MAX field. */
24977 #define TRNG_RD_FRQMAX_FRQ_MAX(base) ((TRNG_FRQMAX_REG(base) & TRNG_FRQMAX_FRQ_MAX_MASK) >> TRNG_FRQMAX_FRQ_MAX_SHIFT)
24978 #define TRNG_BRD_FRQMAX_FRQ_MAX(base) (TRNG_RD_FRQMAX_FRQ_MAX(base))
24979 
24980 /*! @brief Set the FRQ_MAX field to a new value. */
24981 #define TRNG_WR_FRQMAX_FRQ_MAX(base, value) (TRNG_RMW_FRQMAX(base, TRNG_FRQMAX_FRQ_MAX_MASK, TRNG_FRQMAX_FRQ_MAX(value)))
24982 #define TRNG_BWR_FRQMAX_FRQ_MAX(base, value) (TRNG_WR_FRQMAX_FRQ_MAX(base, value))
24983 /*@}*/
24984 
24985 /*******************************************************************************
24986  * TRNG_FRQCNT - RNG Frequency Count Register
24987  ******************************************************************************/
24988 
24989 /*!
24990  * @brief TRNG_FRQCNT - RNG Frequency Count Register (RO)
24991  *
24992  * Reset value: 0x00000000U
24993  *
24994  * The RNG Frequency Count Register is a read-only register used to read the
24995  * frequency counter within the TRNG entropy generator. It will read all zeroes
24996  * unless MCTL[TRNG_ACC] = 1. Note that this offset (0xBASE_061C) is used as FRQMAX
24997  * if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is used as FRQCNT readback
24998  * register, as described here.
24999  */
25000 /*!
25001  * @name Constants and macros for entire TRNG_FRQCNT register
25002  */
25003 /*@{*/
25004 #define TRNG_RD_FRQCNT(base)     (TRNG_FRQCNT_REG(base))
25005 /*@}*/
25006 
25007 /*
25008  * Constants & macros for individual TRNG_FRQCNT bitfields
25009  */
25010 
25011 /*!
25012  * @name Register TRNG_FRQCNT, field FRQ_CT[21:0] (RO)
25013  *
25014  * Frequency Count. If MCTL[TRNG_ACC] = 1, reads a sample frequency count taken
25015  * during entropy generation. Requires MCTL[PRGM] = 0. Note that if MCTL[PRGM]
25016  * bit is 1, this register address is used to access the Poker Test Maximum Limit
25017  * in register PKRMAX, as defined in the previous section.
25018  */
25019 /*@{*/
25020 /*! @brief Read current value of the TRNG_FRQCNT_FRQ_CT field. */
25021 #define TRNG_RD_FRQCNT_FRQ_CT(base) ((TRNG_FRQCNT_REG(base) & TRNG_FRQCNT_FRQ_CT_MASK) >> TRNG_FRQCNT_FRQ_CT_SHIFT)
25022 #define TRNG_BRD_FRQCNT_FRQ_CT(base) (TRNG_RD_FRQCNT_FRQ_CT(base))
25023 /*@}*/
25024 
25025 /*******************************************************************************
25026  * TRNG_SCMC - RNG Statistical Check Monobit Count Register
25027  ******************************************************************************/
25028 
25029 /*!
25030  * @brief TRNG_SCMC - RNG Statistical Check Monobit Count Register (RO)
25031  *
25032  * Reset value: 0x00000000U
25033  *
25034  * The RNG Statistical Check Monobit Count Register is a read-only register used
25035  * to read the final monobit count after entropy generation. This counter starts
25036  * with the value in SCML[MONO_MAX], and is decremented each time a one is
25037  * sampled. Note that this offset (0xBASE_0620) is used as SCML if MCTL[PRGM] is 1. If
25038  * MCTL[PRGM] is 0, this offset is used as SCMC readback register, as described
25039  * here.
25040  */
25041 /*!
25042  * @name Constants and macros for entire TRNG_SCMC register
25043  */
25044 /*@{*/
25045 #define TRNG_RD_SCMC(base)       (TRNG_SCMC_REG(base))
25046 /*@}*/
25047 
25048 /*
25049  * Constants & macros for individual TRNG_SCMC bitfields
25050  */
25051 
25052 /*!
25053  * @name Register TRNG_SCMC, field MONO_CT[15:0] (RO)
25054  *
25055  * Monobit Count. Reads the final Monobit count after entropy generation.
25056  * Requires MCTL[PRGM] = 0. Note that if MCTL[PRGM] bit is 1, this register address is
25057  * used to access the Statistical Check Monobit Limit in register SCML, as
25058  * defined in the previous section.
25059  */
25060 /*@{*/
25061 /*! @brief Read current value of the TRNG_SCMC_MONO_CT field. */
25062 #define TRNG_RD_SCMC_MONO_CT(base) ((TRNG_SCMC_REG(base) & TRNG_SCMC_MONO_CT_MASK) >> TRNG_SCMC_MONO_CT_SHIFT)
25063 #define TRNG_BRD_SCMC_MONO_CT(base) (BME_UBFX32(&TRNG_SCMC_REG(base), TRNG_SCMC_MONO_CT_SHIFT, TRNG_SCMC_MONO_CT_WIDTH))
25064 /*@}*/
25065 
25066 /*******************************************************************************
25067  * TRNG_SCML - RNG Statistical Check Monobit Limit Register
25068  ******************************************************************************/
25069 
25070 /*!
25071  * @brief TRNG_SCML - RNG Statistical Check Monobit Limit Register (RW)
25072  *
25073  * Reset value: 0x010C0568U
25074  *
25075  * The RNG Statistical Check Monobit Limit Register defines the allowable
25076  * maximum and minimum number of ones/zero detected during entropy generation. To pass
25077  * the test, the number of ones/zeroes generated must be less than the programmed
25078  * maximum value, and the number of ones/zeroes generated must be greater than
25079  * (maximum - range). If this test fails, the Retry Counter in SCMISC will be
25080  * decremented, and a retry will occur if the Retry Count has not reached zero. If
25081  * the Retry Count has reached zero, an error will be generated. Note that this
25082  * offset (0xBASE_0620) is used as SCML only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0,
25083  * this offset is used as SCMC readback register.
25084  */
25085 /*!
25086  * @name Constants and macros for entire TRNG_SCML register
25087  */
25088 /*@{*/
25089 #define TRNG_RD_SCML(base)       (TRNG_SCML_REG(base))
25090 #define TRNG_WR_SCML(base, value) (TRNG_SCML_REG(base) = (value))
25091 #define TRNG_RMW_SCML(base, mask, value) (TRNG_WR_SCML(base, (TRNG_RD_SCML(base) & ~(mask)) | (value)))
25092 #define TRNG_SET_SCML(base, value) (BME_OR32(&TRNG_SCML_REG(base), (uint32_t)(value)))
25093 #define TRNG_CLR_SCML(base, value) (BME_AND32(&TRNG_SCML_REG(base), (uint32_t)(~(value))))
25094 #define TRNG_TOG_SCML(base, value) (BME_XOR32(&TRNG_SCML_REG(base), (uint32_t)(value)))
25095 /*@}*/
25096 
25097 /*
25098  * Constants & macros for individual TRNG_SCML bitfields
25099  */
25100 
25101 /*!
25102  * @name Register TRNG_SCML, field MONO_MAX[15:0] (RW)
25103  *
25104  * Monobit Maximum Limit. Defines the maximum allowable count taken during
25105  * entropy generation. The number of ones/zeroes detected during entropy generation
25106  * must be less than MONO_MAX, else a retry or error will occur. This register is
25107  * cleared to 00056Bh (decimal 1387) by writing the MCTL[RST_DEF] bit to 1.
25108  */
25109 /*@{*/
25110 /*! @brief Read current value of the TRNG_SCML_MONO_MAX field. */
25111 #define TRNG_RD_SCML_MONO_MAX(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_MAX_MASK) >> TRNG_SCML_MONO_MAX_SHIFT)
25112 #define TRNG_BRD_SCML_MONO_MAX(base) (BME_UBFX32(&TRNG_SCML_REG(base), TRNG_SCML_MONO_MAX_SHIFT, TRNG_SCML_MONO_MAX_WIDTH))
25113 
25114 /*! @brief Set the MONO_MAX field to a new value. */
25115 #define TRNG_WR_SCML_MONO_MAX(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_MAX_MASK, TRNG_SCML_MONO_MAX(value)))
25116 #define TRNG_BWR_SCML_MONO_MAX(base, value) (BME_BFI32(&TRNG_SCML_REG(base), ((uint32_t)(value) << TRNG_SCML_MONO_MAX_SHIFT), TRNG_SCML_MONO_MAX_SHIFT, TRNG_SCML_MONO_MAX_WIDTH))
25117 /*@}*/
25118 
25119 /*!
25120  * @name Register TRNG_SCML, field MONO_RNG[31:16] (RW)
25121  *
25122  * Monobit Range. The number of ones/zeroes detected during entropy generation
25123  * must be greater than MONO_MAX - MONO_RNG, else a retry or error will occur.
25124  * This register is cleared to 000112h (decimal 274) by writing the MCTL[RST_DEF]
25125  * bit to 1.
25126  */
25127 /*@{*/
25128 /*! @brief Read current value of the TRNG_SCML_MONO_RNG field. */
25129 #define TRNG_RD_SCML_MONO_RNG(base) ((TRNG_SCML_REG(base) & TRNG_SCML_MONO_RNG_MASK) >> TRNG_SCML_MONO_RNG_SHIFT)
25130 #define TRNG_BRD_SCML_MONO_RNG(base) (BME_UBFX32(&TRNG_SCML_REG(base), TRNG_SCML_MONO_RNG_SHIFT, TRNG_SCML_MONO_RNG_WIDTH))
25131 
25132 /*! @brief Set the MONO_RNG field to a new value. */
25133 #define TRNG_WR_SCML_MONO_RNG(base, value) (TRNG_RMW_SCML(base, TRNG_SCML_MONO_RNG_MASK, TRNG_SCML_MONO_RNG(value)))
25134 #define TRNG_BWR_SCML_MONO_RNG(base, value) (BME_BFI32(&TRNG_SCML_REG(base), ((uint32_t)(value) << TRNG_SCML_MONO_RNG_SHIFT), TRNG_SCML_MONO_RNG_SHIFT, TRNG_SCML_MONO_RNG_WIDTH))
25135 /*@}*/
25136 
25137 /*******************************************************************************
25138  * TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register
25139  ******************************************************************************/
25140 
25141 /*!
25142  * @brief TRNG_SCR1L - RNG Statistical Check Run Length 1 Limit Register (RW)
25143  *
25144  * Reset value: 0x00B20195U
25145  *
25146  * The RNG Statistical Check Run Length 1 Limit Register defines the allowable
25147  * maximum and minimum number of runs of length 1 detected during entropy
25148  * generation. To pass the test, the number of runs of length 1 (for samples of both 0
25149  * and 1) must be less than the programmed maximum value, and the number of runs of
25150  * length 1 must be greater than (maximum - range). If this test fails, the
25151  * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
25152  * Count has not reached zero. If the Retry Count has reached zero, an error will
25153  * be generated. Note that this address (0xBASE_0624) is used as SCR1L only if
25154  * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR1C readback
25155  * register.
25156  */
25157 /*!
25158  * @name Constants and macros for entire TRNG_SCR1L register
25159  */
25160 /*@{*/
25161 #define TRNG_RD_SCR1L(base)      (TRNG_SCR1L_REG(base))
25162 #define TRNG_WR_SCR1L(base, value) (TRNG_SCR1L_REG(base) = (value))
25163 #define TRNG_RMW_SCR1L(base, mask, value) (TRNG_WR_SCR1L(base, (TRNG_RD_SCR1L(base) & ~(mask)) | (value)))
25164 #define TRNG_SET_SCR1L(base, value) (BME_OR32(&TRNG_SCR1L_REG(base), (uint32_t)(value)))
25165 #define TRNG_CLR_SCR1L(base, value) (BME_AND32(&TRNG_SCR1L_REG(base), (uint32_t)(~(value))))
25166 #define TRNG_TOG_SCR1L(base, value) (BME_XOR32(&TRNG_SCR1L_REG(base), (uint32_t)(value)))
25167 /*@}*/
25168 
25169 /*
25170  * Constants & macros for individual TRNG_SCR1L bitfields
25171  */
25172 
25173 /*!
25174  * @name Register TRNG_SCR1L, field RUN1_MAX[14:0] (RW)
25175  *
25176  * Run Length 1 Maximum Limit. Defines the maximum allowable runs of length 1
25177  * (for both 0 and 1) detected during entropy generation. The number of runs of
25178  * length 1 detected during entropy generation must be less than RUN1_MAX, else a
25179  * retry or error will occur. This register is cleared to 01E5h (decimal 485) by
25180  * writing the MCTL[RST_DEF] bit to 1.
25181  */
25182 /*@{*/
25183 /*! @brief Read current value of the TRNG_SCR1L_RUN1_MAX field. */
25184 #define TRNG_RD_SCR1L_RUN1_MAX(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_MAX_MASK) >> TRNG_SCR1L_RUN1_MAX_SHIFT)
25185 #define TRNG_BRD_SCR1L_RUN1_MAX(base) (BME_UBFX32(&TRNG_SCR1L_REG(base), TRNG_SCR1L_RUN1_MAX_SHIFT, TRNG_SCR1L_RUN1_MAX_WIDTH))
25186 
25187 /*! @brief Set the RUN1_MAX field to a new value. */
25188 #define TRNG_WR_SCR1L_RUN1_MAX(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_MAX_MASK, TRNG_SCR1L_RUN1_MAX(value)))
25189 #define TRNG_BWR_SCR1L_RUN1_MAX(base, value) (BME_BFI32(&TRNG_SCR1L_REG(base), ((uint32_t)(value) << TRNG_SCR1L_RUN1_MAX_SHIFT), TRNG_SCR1L_RUN1_MAX_SHIFT, TRNG_SCR1L_RUN1_MAX_WIDTH))
25190 /*@}*/
25191 
25192 /*!
25193  * @name Register TRNG_SCR1L, field RUN1_RNG[30:16] (RW)
25194  *
25195  * Run Length 1 Range. The number of runs of length 1 (for both 0 and 1)
25196  * detected during entropy generation must be greater than RUN1_MAX - RUN1_RNG, else a
25197  * retry or error will occur. This register is cleared to 0102h (decimal 258) by
25198  * writing the MCTL[RST_DEF] bit to 1.
25199  */
25200 /*@{*/
25201 /*! @brief Read current value of the TRNG_SCR1L_RUN1_RNG field. */
25202 #define TRNG_RD_SCR1L_RUN1_RNG(base) ((TRNG_SCR1L_REG(base) & TRNG_SCR1L_RUN1_RNG_MASK) >> TRNG_SCR1L_RUN1_RNG_SHIFT)
25203 #define TRNG_BRD_SCR1L_RUN1_RNG(base) (BME_UBFX32(&TRNG_SCR1L_REG(base), TRNG_SCR1L_RUN1_RNG_SHIFT, TRNG_SCR1L_RUN1_RNG_WIDTH))
25204 
25205 /*! @brief Set the RUN1_RNG field to a new value. */
25206 #define TRNG_WR_SCR1L_RUN1_RNG(base, value) (TRNG_RMW_SCR1L(base, TRNG_SCR1L_RUN1_RNG_MASK, TRNG_SCR1L_RUN1_RNG(value)))
25207 #define TRNG_BWR_SCR1L_RUN1_RNG(base, value) (BME_BFI32(&TRNG_SCR1L_REG(base), ((uint32_t)(value) << TRNG_SCR1L_RUN1_RNG_SHIFT), TRNG_SCR1L_RUN1_RNG_SHIFT, TRNG_SCR1L_RUN1_RNG_WIDTH))
25208 /*@}*/
25209 
25210 /*******************************************************************************
25211  * TRNG_SCR1C - RNG Statistical Check Run Length 1 Count Register
25212  ******************************************************************************/
25213 
25214 /*!
25215  * @brief TRNG_SCR1C - RNG Statistical Check Run Length 1 Count Register (RO)
25216  *
25217  * Reset value: 0x00000000U
25218  *
25219  * The RNG Statistical Check Run Length 1 Counters Register is a read-only
25220  * register used to read the final Run Length 1 counts after entropy generation. These
25221  * counters start with the value in SCR1L[RUN1_MAX]. The R1_1_CT decrements each
25222  * time a single one is sampled (preceded by a zero and followed by a zero). The
25223  * R1_0_CT decrements each time a single zero is sampled (preceded by a one and
25224  * followed by a one). Note that this offset (0xBASE_0624) is used as SCR1L if
25225  * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is used as SCR1C readback
25226  * register, as described here.
25227  */
25228 /*!
25229  * @name Constants and macros for entire TRNG_SCR1C register
25230  */
25231 /*@{*/
25232 #define TRNG_RD_SCR1C(base)      (TRNG_SCR1C_REG(base))
25233 /*@}*/
25234 
25235 /*
25236  * Constants & macros for individual TRNG_SCR1C bitfields
25237  */
25238 
25239 /*!
25240  * @name Register TRNG_SCR1C, field R1_0_CT[14:0] (RO)
25241  *
25242  * Runs of Zero, Length 1 Count. Reads the final Runs of Zeroes, length 1 count
25243  * after entropy generation. Requires MCTL[PRGM] = 0.
25244  */
25245 /*@{*/
25246 /*! @brief Read current value of the TRNG_SCR1C_R1_0_CT field. */
25247 #define TRNG_RD_SCR1C_R1_0_CT(base) ((TRNG_SCR1C_REG(base) & TRNG_SCR1C_R1_0_CT_MASK) >> TRNG_SCR1C_R1_0_CT_SHIFT)
25248 #define TRNG_BRD_SCR1C_R1_0_CT(base) (BME_UBFX32(&TRNG_SCR1C_REG(base), TRNG_SCR1C_R1_0_CT_SHIFT, TRNG_SCR1C_R1_0_CT_WIDTH))
25249 /*@}*/
25250 
25251 /*!
25252  * @name Register TRNG_SCR1C, field R1_1_CT[30:16] (RO)
25253  *
25254  * Runs of One, Length 1 Count. Reads the final Runs of Ones, length 1 count
25255  * after entropy generation. Requires MCTL[PRGM] = 0.
25256  */
25257 /*@{*/
25258 /*! @brief Read current value of the TRNG_SCR1C_R1_1_CT field. */
25259 #define TRNG_RD_SCR1C_R1_1_CT(base) ((TRNG_SCR1C_REG(base) & TRNG_SCR1C_R1_1_CT_MASK) >> TRNG_SCR1C_R1_1_CT_SHIFT)
25260 #define TRNG_BRD_SCR1C_R1_1_CT(base) (BME_UBFX32(&TRNG_SCR1C_REG(base), TRNG_SCR1C_R1_1_CT_SHIFT, TRNG_SCR1C_R1_1_CT_WIDTH))
25261 /*@}*/
25262 
25263 /*******************************************************************************
25264  * TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register
25265  ******************************************************************************/
25266 
25267 /*!
25268  * @brief TRNG_SCR2L - RNG Statistical Check Run Length 2 Limit Register (RW)
25269  *
25270  * Reset value: 0x007A00DCU
25271  *
25272  * The RNG Statistical Check Run Length 2 Limit Register defines the allowable
25273  * maximum and minimum number of runs of length 2 detected during entropy
25274  * generation. To pass the test, the number of runs of length 2 (for samples of both 0
25275  * and 1) must be less than the programmed maximum value, and the number of runs of
25276  * length 2 must be greater than (maximum - range). If this test fails, the
25277  * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
25278  * Count has not reached zero. If the Retry Count has reached zero, an error will
25279  * be generated. Note that this address (0xBASE_0628) is used as SCR2L only if
25280  * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR2C readback
25281  * register.
25282  */
25283 /*!
25284  * @name Constants and macros for entire TRNG_SCR2L register
25285  */
25286 /*@{*/
25287 #define TRNG_RD_SCR2L(base)      (TRNG_SCR2L_REG(base))
25288 #define TRNG_WR_SCR2L(base, value) (TRNG_SCR2L_REG(base) = (value))
25289 #define TRNG_RMW_SCR2L(base, mask, value) (TRNG_WR_SCR2L(base, (TRNG_RD_SCR2L(base) & ~(mask)) | (value)))
25290 #define TRNG_SET_SCR2L(base, value) (BME_OR32(&TRNG_SCR2L_REG(base), (uint32_t)(value)))
25291 #define TRNG_CLR_SCR2L(base, value) (BME_AND32(&TRNG_SCR2L_REG(base), (uint32_t)(~(value))))
25292 #define TRNG_TOG_SCR2L(base, value) (BME_XOR32(&TRNG_SCR2L_REG(base), (uint32_t)(value)))
25293 /*@}*/
25294 
25295 /*
25296  * Constants & macros for individual TRNG_SCR2L bitfields
25297  */
25298 
25299 /*!
25300  * @name Register TRNG_SCR2L, field RUN2_MAX[13:0] (RW)
25301  *
25302  * Run Length 2 Maximum Limit. Defines the maximum allowable runs of length 2
25303  * (for both 0 and 1) detected during entropy generation. The number of runs of
25304  * length 2 detected during entropy generation must be less than RUN2_MAX, else a
25305  * retry or error will occur. This register is cleared to 00DCh (decimal 220) by
25306  * writing the MCTL[RST_DEF] bit to 1.
25307  */
25308 /*@{*/
25309 /*! @brief Read current value of the TRNG_SCR2L_RUN2_MAX field. */
25310 #define TRNG_RD_SCR2L_RUN2_MAX(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_MAX_MASK) >> TRNG_SCR2L_RUN2_MAX_SHIFT)
25311 #define TRNG_BRD_SCR2L_RUN2_MAX(base) (BME_UBFX32(&TRNG_SCR2L_REG(base), TRNG_SCR2L_RUN2_MAX_SHIFT, TRNG_SCR2L_RUN2_MAX_WIDTH))
25312 
25313 /*! @brief Set the RUN2_MAX field to a new value. */
25314 #define TRNG_WR_SCR2L_RUN2_MAX(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_MAX_MASK, TRNG_SCR2L_RUN2_MAX(value)))
25315 #define TRNG_BWR_SCR2L_RUN2_MAX(base, value) (BME_BFI32(&TRNG_SCR2L_REG(base), ((uint32_t)(value) << TRNG_SCR2L_RUN2_MAX_SHIFT), TRNG_SCR2L_RUN2_MAX_SHIFT, TRNG_SCR2L_RUN2_MAX_WIDTH))
25316 /*@}*/
25317 
25318 /*!
25319  * @name Register TRNG_SCR2L, field RUN2_RNG[29:16] (RW)
25320  *
25321  * Run Length 2 Range. The number of runs of length 2 (for both 0 and 1)
25322  * detected during entropy generation must be greater than RUN2_MAX - RUN2_RNG, else a
25323  * retry or error will occur. This register is cleared to 007Ah (decimal 122) by
25324  * writing the MCTL[RST_DEF] bit to 1.
25325  */
25326 /*@{*/
25327 /*! @brief Read current value of the TRNG_SCR2L_RUN2_RNG field. */
25328 #define TRNG_RD_SCR2L_RUN2_RNG(base) ((TRNG_SCR2L_REG(base) & TRNG_SCR2L_RUN2_RNG_MASK) >> TRNG_SCR2L_RUN2_RNG_SHIFT)
25329 #define TRNG_BRD_SCR2L_RUN2_RNG(base) (BME_UBFX32(&TRNG_SCR2L_REG(base), TRNG_SCR2L_RUN2_RNG_SHIFT, TRNG_SCR2L_RUN2_RNG_WIDTH))
25330 
25331 /*! @brief Set the RUN2_RNG field to a new value. */
25332 #define TRNG_WR_SCR2L_RUN2_RNG(base, value) (TRNG_RMW_SCR2L(base, TRNG_SCR2L_RUN2_RNG_MASK, TRNG_SCR2L_RUN2_RNG(value)))
25333 #define TRNG_BWR_SCR2L_RUN2_RNG(base, value) (BME_BFI32(&TRNG_SCR2L_REG(base), ((uint32_t)(value) << TRNG_SCR2L_RUN2_RNG_SHIFT), TRNG_SCR2L_RUN2_RNG_SHIFT, TRNG_SCR2L_RUN2_RNG_WIDTH))
25334 /*@}*/
25335 
25336 /*******************************************************************************
25337  * TRNG_SCR2C - RNG Statistical Check Run Length 2 Count Register
25338  ******************************************************************************/
25339 
25340 /*!
25341  * @brief TRNG_SCR2C - RNG Statistical Check Run Length 2 Count Register (RO)
25342  *
25343  * Reset value: 0x00000000U
25344  *
25345  * The RNG Statistical Check Run Length 2 Counters Register is a read-only
25346  * register used to read the final Run Length 2 counts after entropy generation. These
25347  * counters start with the value in SCR2L[RUN2_MAX]. The R2_1_CT decrements each
25348  * time two consecutive ones are sampled (preceded by a zero and followed by a
25349  * zero). The R2_0_CT decrements each time two consecutive zeroes are sampled
25350  * (preceded by a one and followed by a one). Note that this offset (0xBASE_0628) is
25351  * used as SCR2L if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is used as
25352  * SCR2C readback register, as described here.
25353  */
25354 /*!
25355  * @name Constants and macros for entire TRNG_SCR2C register
25356  */
25357 /*@{*/
25358 #define TRNG_RD_SCR2C(base)      (TRNG_SCR2C_REG(base))
25359 /*@}*/
25360 
25361 /*
25362  * Constants & macros for individual TRNG_SCR2C bitfields
25363  */
25364 
25365 /*!
25366  * @name Register TRNG_SCR2C, field R2_0_CT[13:0] (RO)
25367  *
25368  * Runs of Zero, Length 2 Count. Reads the final Runs of Zeroes, length 2 count
25369  * after entropy generation. Requires MCTL[PRGM] = 0.
25370  */
25371 /*@{*/
25372 /*! @brief Read current value of the TRNG_SCR2C_R2_0_CT field. */
25373 #define TRNG_RD_SCR2C_R2_0_CT(base) ((TRNG_SCR2C_REG(base) & TRNG_SCR2C_R2_0_CT_MASK) >> TRNG_SCR2C_R2_0_CT_SHIFT)
25374 #define TRNG_BRD_SCR2C_R2_0_CT(base) (BME_UBFX32(&TRNG_SCR2C_REG(base), TRNG_SCR2C_R2_0_CT_SHIFT, TRNG_SCR2C_R2_0_CT_WIDTH))
25375 /*@}*/
25376 
25377 /*!
25378  * @name Register TRNG_SCR2C, field R2_1_CT[29:16] (RO)
25379  *
25380  * Runs of One, Length 2 Count. Reads the final Runs of Ones, length 2 count
25381  * after entropy generation. Requires MCTL[PRGM] = 0.
25382  */
25383 /*@{*/
25384 /*! @brief Read current value of the TRNG_SCR2C_R2_1_CT field. */
25385 #define TRNG_RD_SCR2C_R2_1_CT(base) ((TRNG_SCR2C_REG(base) & TRNG_SCR2C_R2_1_CT_MASK) >> TRNG_SCR2C_R2_1_CT_SHIFT)
25386 #define TRNG_BRD_SCR2C_R2_1_CT(base) (BME_UBFX32(&TRNG_SCR2C_REG(base), TRNG_SCR2C_R2_1_CT_SHIFT, TRNG_SCR2C_R2_1_CT_WIDTH))
25387 /*@}*/
25388 
25389 /*******************************************************************************
25390  * TRNG_SCR3C - RNG Statistical Check Run Length 3 Count Register
25391  ******************************************************************************/
25392 
25393 /*!
25394  * @brief TRNG_SCR3C - RNG Statistical Check Run Length 3 Count Register (RO)
25395  *
25396  * Reset value: 0x00000000U
25397  *
25398  * The RNG Statistical Check Run Length 3 Counters Register is a read-only
25399  * register used to read the final Run Length 3 counts after entropy generation. These
25400  * counters start with the value in SCR3L[RUN3_MAX]. The R3_1_CT decrements each
25401  * time three consecutive ones are sampled (preceded by a zero and followed by a
25402  * zero). The R3_0_CT decrements each time three consecutive zeroes are sampled
25403  * (preceded by a one and followed by a one). Note that this offset (0xBASE_062C)
25404  * is used as SCR3L if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is used
25405  * as SCR3C readback register, as described here.
25406  */
25407 /*!
25408  * @name Constants and macros for entire TRNG_SCR3C register
25409  */
25410 /*@{*/
25411 #define TRNG_RD_SCR3C(base)      (TRNG_SCR3C_REG(base))
25412 /*@}*/
25413 
25414 /*
25415  * Constants & macros for individual TRNG_SCR3C bitfields
25416  */
25417 
25418 /*!
25419  * @name Register TRNG_SCR3C, field R3_0_CT[12:0] (RO)
25420  *
25421  * Runs of Zeroes, Length 3 Count. Reads the final Runs of Zeroes, length 3
25422  * count after entropy generation. Requires MCTL[PRGM] = 0.
25423  */
25424 /*@{*/
25425 /*! @brief Read current value of the TRNG_SCR3C_R3_0_CT field. */
25426 #define TRNG_RD_SCR3C_R3_0_CT(base) ((TRNG_SCR3C_REG(base) & TRNG_SCR3C_R3_0_CT_MASK) >> TRNG_SCR3C_R3_0_CT_SHIFT)
25427 #define TRNG_BRD_SCR3C_R3_0_CT(base) (BME_UBFX32(&TRNG_SCR3C_REG(base), TRNG_SCR3C_R3_0_CT_SHIFT, TRNG_SCR3C_R3_0_CT_WIDTH))
25428 /*@}*/
25429 
25430 /*!
25431  * @name Register TRNG_SCR3C, field R3_1_CT[28:16] (RO)
25432  *
25433  * Runs of Ones, Length 3 Count. Reads the final Runs of Ones, length 3 count
25434  * after entropy generation. Requires MCTL[PRGM] = 0.
25435  */
25436 /*@{*/
25437 /*! @brief Read current value of the TRNG_SCR3C_R3_1_CT field. */
25438 #define TRNG_RD_SCR3C_R3_1_CT(base) ((TRNG_SCR3C_REG(base) & TRNG_SCR3C_R3_1_CT_MASK) >> TRNG_SCR3C_R3_1_CT_SHIFT)
25439 #define TRNG_BRD_SCR3C_R3_1_CT(base) (BME_UBFX32(&TRNG_SCR3C_REG(base), TRNG_SCR3C_R3_1_CT_SHIFT, TRNG_SCR3C_R3_1_CT_WIDTH))
25440 /*@}*/
25441 
25442 /*******************************************************************************
25443  * TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register
25444  ******************************************************************************/
25445 
25446 /*!
25447  * @brief TRNG_SCR3L - RNG Statistical Check Run Length 3 Limit Register (RW)
25448  *
25449  * Reset value: 0x0058007DU
25450  *
25451  * The RNG Statistical Check Run Length 3 Limit Register defines the allowable
25452  * maximum and minimum number of runs of length 3 detected during entropy
25453  * generation. To pass the test, the number of runs of length 3 (for samples of both 0
25454  * and 1) must be less than the programmed maximum value, and the number of runs of
25455  * length 3 must be greater than (maximum - range). If this test fails, the
25456  * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
25457  * Count has not reached zero. If the Retry Count has reached zero, an error will
25458  * be generated. Note that this address (0xBASE_062C) is used as SCR3L only if
25459  * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR3C readback
25460  * register.
25461  */
25462 /*!
25463  * @name Constants and macros for entire TRNG_SCR3L register
25464  */
25465 /*@{*/
25466 #define TRNG_RD_SCR3L(base)      (TRNG_SCR3L_REG(base))
25467 #define TRNG_WR_SCR3L(base, value) (TRNG_SCR3L_REG(base) = (value))
25468 #define TRNG_RMW_SCR3L(base, mask, value) (TRNG_WR_SCR3L(base, (TRNG_RD_SCR3L(base) & ~(mask)) | (value)))
25469 #define TRNG_SET_SCR3L(base, value) (BME_OR32(&TRNG_SCR3L_REG(base), (uint32_t)(value)))
25470 #define TRNG_CLR_SCR3L(base, value) (BME_AND32(&TRNG_SCR3L_REG(base), (uint32_t)(~(value))))
25471 #define TRNG_TOG_SCR3L(base, value) (BME_XOR32(&TRNG_SCR3L_REG(base), (uint32_t)(value)))
25472 /*@}*/
25473 
25474 /*
25475  * Constants & macros for individual TRNG_SCR3L bitfields
25476  */
25477 
25478 /*!
25479  * @name Register TRNG_SCR3L, field RUN3_MAX[12:0] (RW)
25480  *
25481  * Run Length 3 Maximum Limit. Defines the maximum allowable runs of length 3
25482  * (for both 0 and 1) detected during entropy generation. The number of runs of
25483  * length 3 detected during entropy generation must be less than RUN3_MAX, else a
25484  * retry or error will occur. This register is cleared to 007Dh (decimal 125) by
25485  * writing the MCTL[RST_DEF] bit to 1.
25486  */
25487 /*@{*/
25488 /*! @brief Read current value of the TRNG_SCR3L_RUN3_MAX field. */
25489 #define TRNG_RD_SCR3L_RUN3_MAX(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_MAX_MASK) >> TRNG_SCR3L_RUN3_MAX_SHIFT)
25490 #define TRNG_BRD_SCR3L_RUN3_MAX(base) (BME_UBFX32(&TRNG_SCR3L_REG(base), TRNG_SCR3L_RUN3_MAX_SHIFT, TRNG_SCR3L_RUN3_MAX_WIDTH))
25491 
25492 /*! @brief Set the RUN3_MAX field to a new value. */
25493 #define TRNG_WR_SCR3L_RUN3_MAX(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_MAX_MASK, TRNG_SCR3L_RUN3_MAX(value)))
25494 #define TRNG_BWR_SCR3L_RUN3_MAX(base, value) (BME_BFI32(&TRNG_SCR3L_REG(base), ((uint32_t)(value) << TRNG_SCR3L_RUN3_MAX_SHIFT), TRNG_SCR3L_RUN3_MAX_SHIFT, TRNG_SCR3L_RUN3_MAX_WIDTH))
25495 /*@}*/
25496 
25497 /*!
25498  * @name Register TRNG_SCR3L, field RUN3_RNG[28:16] (RW)
25499  *
25500  * Run Length 3 Range. The number of runs of length 3 (for both 0 and 1)
25501  * detected during entropy generation must be greater than RUN3_MAX - RUN3_RNG, else a
25502  * retry or error will occur. This register is cleared to 0058h (decimal 88) by
25503  * writing the MCTL[RST_DEF] bit to 1.
25504  */
25505 /*@{*/
25506 /*! @brief Read current value of the TRNG_SCR3L_RUN3_RNG field. */
25507 #define TRNG_RD_SCR3L_RUN3_RNG(base) ((TRNG_SCR3L_REG(base) & TRNG_SCR3L_RUN3_RNG_MASK) >> TRNG_SCR3L_RUN3_RNG_SHIFT)
25508 #define TRNG_BRD_SCR3L_RUN3_RNG(base) (BME_UBFX32(&TRNG_SCR3L_REG(base), TRNG_SCR3L_RUN3_RNG_SHIFT, TRNG_SCR3L_RUN3_RNG_WIDTH))
25509 
25510 /*! @brief Set the RUN3_RNG field to a new value. */
25511 #define TRNG_WR_SCR3L_RUN3_RNG(base, value) (TRNG_RMW_SCR3L(base, TRNG_SCR3L_RUN3_RNG_MASK, TRNG_SCR3L_RUN3_RNG(value)))
25512 #define TRNG_BWR_SCR3L_RUN3_RNG(base, value) (BME_BFI32(&TRNG_SCR3L_REG(base), ((uint32_t)(value) << TRNG_SCR3L_RUN3_RNG_SHIFT), TRNG_SCR3L_RUN3_RNG_SHIFT, TRNG_SCR3L_RUN3_RNG_WIDTH))
25513 /*@}*/
25514 
25515 /*******************************************************************************
25516  * TRNG_SCR4C - RNG Statistical Check Run Length 4 Count Register
25517  ******************************************************************************/
25518 
25519 /*!
25520  * @brief TRNG_SCR4C - RNG Statistical Check Run Length 4 Count Register (RO)
25521  *
25522  * Reset value: 0x00000000U
25523  *
25524  * The RNG Statistical Check Run Length 4 Counters Register is a read-only
25525  * register used to read the final Run Length 4 counts after entropy generation. These
25526  * counters start with the value in SCR4L[RUN4_MAX]. The R4_1_CT decrements each
25527  * time four consecutive ones are sampled (preceded by a zero and followed by a
25528  * zero). The R4_0_CT decrements each time four consecutive zeroes are sampled
25529  * (preceded by a one and followed by a one). Note that this offset (0xBASE_0630)
25530  * is used as SCR4L if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is used as
25531  * SCR4C readback register, as described here.
25532  */
25533 /*!
25534  * @name Constants and macros for entire TRNG_SCR4C register
25535  */
25536 /*@{*/
25537 #define TRNG_RD_SCR4C(base)      (TRNG_SCR4C_REG(base))
25538 /*@}*/
25539 
25540 /*
25541  * Constants & macros for individual TRNG_SCR4C bitfields
25542  */
25543 
25544 /*!
25545  * @name Register TRNG_SCR4C, field R4_0_CT[11:0] (RO)
25546  *
25547  * Runs of Zero, Length 4 Count. Reads the final Runs of Ones, length 4 count
25548  * after entropy generation. Requires MCTL[PRGM] = 0.
25549  */
25550 /*@{*/
25551 /*! @brief Read current value of the TRNG_SCR4C_R4_0_CT field. */
25552 #define TRNG_RD_SCR4C_R4_0_CT(base) ((TRNG_SCR4C_REG(base) & TRNG_SCR4C_R4_0_CT_MASK) >> TRNG_SCR4C_R4_0_CT_SHIFT)
25553 #define TRNG_BRD_SCR4C_R4_0_CT(base) (BME_UBFX32(&TRNG_SCR4C_REG(base), TRNG_SCR4C_R4_0_CT_SHIFT, TRNG_SCR4C_R4_0_CT_WIDTH))
25554 /*@}*/
25555 
25556 /*!
25557  * @name Register TRNG_SCR4C, field R4_1_CT[27:16] (RO)
25558  *
25559  * Runs of One, Length 4 Count. Reads the final Runs of Ones, length 4 count
25560  * after entropy generation. Requires MCTL[PRGM] = 0.
25561  */
25562 /*@{*/
25563 /*! @brief Read current value of the TRNG_SCR4C_R4_1_CT field. */
25564 #define TRNG_RD_SCR4C_R4_1_CT(base) ((TRNG_SCR4C_REG(base) & TRNG_SCR4C_R4_1_CT_MASK) >> TRNG_SCR4C_R4_1_CT_SHIFT)
25565 #define TRNG_BRD_SCR4C_R4_1_CT(base) (BME_UBFX32(&TRNG_SCR4C_REG(base), TRNG_SCR4C_R4_1_CT_SHIFT, TRNG_SCR4C_R4_1_CT_WIDTH))
25566 /*@}*/
25567 
25568 /*******************************************************************************
25569  * TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register
25570  ******************************************************************************/
25571 
25572 /*!
25573  * @brief TRNG_SCR4L - RNG Statistical Check Run Length 4 Limit Register (RW)
25574  *
25575  * Reset value: 0x0040004BU
25576  *
25577  * The RNG Statistical Check Run Length 4 Limit Register defines the allowable
25578  * maximum and minimum number of runs of length 4 detected during entropy
25579  * generation. To pass the test, the number of runs of length 4 (for samples of both 0
25580  * and 1) must be less than the programmed maximum value, and the number of runs of
25581  * length 4 must be greater than (maximum - range). If this test fails, the
25582  * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
25583  * Count has not reached zero. If the Retry Count has reached zero, an error will
25584  * be generated. Note that this address (0xBASE_0630) is used as SCR4L only if
25585  * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR4C readback
25586  * register.
25587  */
25588 /*!
25589  * @name Constants and macros for entire TRNG_SCR4L register
25590  */
25591 /*@{*/
25592 #define TRNG_RD_SCR4L(base)      (TRNG_SCR4L_REG(base))
25593 #define TRNG_WR_SCR4L(base, value) (TRNG_SCR4L_REG(base) = (value))
25594 #define TRNG_RMW_SCR4L(base, mask, value) (TRNG_WR_SCR4L(base, (TRNG_RD_SCR4L(base) & ~(mask)) | (value)))
25595 #define TRNG_SET_SCR4L(base, value) (BME_OR32(&TRNG_SCR4L_REG(base), (uint32_t)(value)))
25596 #define TRNG_CLR_SCR4L(base, value) (BME_AND32(&TRNG_SCR4L_REG(base), (uint32_t)(~(value))))
25597 #define TRNG_TOG_SCR4L(base, value) (BME_XOR32(&TRNG_SCR4L_REG(base), (uint32_t)(value)))
25598 /*@}*/
25599 
25600 /*
25601  * Constants & macros for individual TRNG_SCR4L bitfields
25602  */
25603 
25604 /*!
25605  * @name Register TRNG_SCR4L, field RUN4_MAX[11:0] (RW)
25606  *
25607  * Run Length 4 Maximum Limit. Defines the maximum allowable runs of length 4
25608  * (for both 0 and 1) detected during entropy generation. The number of runs of
25609  * length 4 detected during entropy generation must be less than RUN4_MAX, else a
25610  * retry or error will occur. This register is cleared to 004Bh (decimal 75) by
25611  * writing the MCTL[RST_DEF] bit to 1.
25612  */
25613 /*@{*/
25614 /*! @brief Read current value of the TRNG_SCR4L_RUN4_MAX field. */
25615 #define TRNG_RD_SCR4L_RUN4_MAX(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_MAX_MASK) >> TRNG_SCR4L_RUN4_MAX_SHIFT)
25616 #define TRNG_BRD_SCR4L_RUN4_MAX(base) (BME_UBFX32(&TRNG_SCR4L_REG(base), TRNG_SCR4L_RUN4_MAX_SHIFT, TRNG_SCR4L_RUN4_MAX_WIDTH))
25617 
25618 /*! @brief Set the RUN4_MAX field to a new value. */
25619 #define TRNG_WR_SCR4L_RUN4_MAX(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_MAX_MASK, TRNG_SCR4L_RUN4_MAX(value)))
25620 #define TRNG_BWR_SCR4L_RUN4_MAX(base, value) (BME_BFI32(&TRNG_SCR4L_REG(base), ((uint32_t)(value) << TRNG_SCR4L_RUN4_MAX_SHIFT), TRNG_SCR4L_RUN4_MAX_SHIFT, TRNG_SCR4L_RUN4_MAX_WIDTH))
25621 /*@}*/
25622 
25623 /*!
25624  * @name Register TRNG_SCR4L, field RUN4_RNG[27:16] (RW)
25625  *
25626  * Run Length 4 Range. The number of runs of length 4 (for both 0 and 1)
25627  * detected during entropy generation must be greater than RUN4_MAX - RUN4_RNG, else a
25628  * retry or error will occur. This register is cleared to 0040h (decimal 64) by
25629  * writing the MCTL[RST_DEF] bit to 1.
25630  */
25631 /*@{*/
25632 /*! @brief Read current value of the TRNG_SCR4L_RUN4_RNG field. */
25633 #define TRNG_RD_SCR4L_RUN4_RNG(base) ((TRNG_SCR4L_REG(base) & TRNG_SCR4L_RUN4_RNG_MASK) >> TRNG_SCR4L_RUN4_RNG_SHIFT)
25634 #define TRNG_BRD_SCR4L_RUN4_RNG(base) (BME_UBFX32(&TRNG_SCR4L_REG(base), TRNG_SCR4L_RUN4_RNG_SHIFT, TRNG_SCR4L_RUN4_RNG_WIDTH))
25635 
25636 /*! @brief Set the RUN4_RNG field to a new value. */
25637 #define TRNG_WR_SCR4L_RUN4_RNG(base, value) (TRNG_RMW_SCR4L(base, TRNG_SCR4L_RUN4_RNG_MASK, TRNG_SCR4L_RUN4_RNG(value)))
25638 #define TRNG_BWR_SCR4L_RUN4_RNG(base, value) (BME_BFI32(&TRNG_SCR4L_REG(base), ((uint32_t)(value) << TRNG_SCR4L_RUN4_RNG_SHIFT), TRNG_SCR4L_RUN4_RNG_SHIFT, TRNG_SCR4L_RUN4_RNG_WIDTH))
25639 /*@}*/
25640 
25641 /*******************************************************************************
25642  * TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register
25643  ******************************************************************************/
25644 
25645 /*!
25646  * @brief TRNG_SCR5L - RNG Statistical Check Run Length 5 Limit Register (RW)
25647  *
25648  * Reset value: 0x002E002FU
25649  *
25650  * The RNG Statistical Check Run Length 5 Limit Register defines the allowable
25651  * maximum and minimum number of runs of length 5 detected during entropy
25652  * generation. To pass the test, the number of runs of length 5 (for samples of both 0
25653  * and 1) must be less than the programmed maximum value, and the number of runs of
25654  * length 5 must be greater than (maximum - range). If this test fails, the
25655  * Retry Counter in SCMISC will be decremented, and a retry will occur if the Retry
25656  * Count has not reached zero. If the Retry Count has reached zero, an error will
25657  * be generated. Note that this address (0xBASE_0634) is used as SCR5L only if
25658  * MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this address is used as SCR5C readback
25659  * register.
25660  */
25661 /*!
25662  * @name Constants and macros for entire TRNG_SCR5L register
25663  */
25664 /*@{*/
25665 #define TRNG_RD_SCR5L(base)      (TRNG_SCR5L_REG(base))
25666 #define TRNG_WR_SCR5L(base, value) (TRNG_SCR5L_REG(base) = (value))
25667 #define TRNG_RMW_SCR5L(base, mask, value) (TRNG_WR_SCR5L(base, (TRNG_RD_SCR5L(base) & ~(mask)) | (value)))
25668 #define TRNG_SET_SCR5L(base, value) (BME_OR32(&TRNG_SCR5L_REG(base), (uint32_t)(value)))
25669 #define TRNG_CLR_SCR5L(base, value) (BME_AND32(&TRNG_SCR5L_REG(base), (uint32_t)(~(value))))
25670 #define TRNG_TOG_SCR5L(base, value) (BME_XOR32(&TRNG_SCR5L_REG(base), (uint32_t)(value)))
25671 /*@}*/
25672 
25673 /*
25674  * Constants & macros for individual TRNG_SCR5L bitfields
25675  */
25676 
25677 /*!
25678  * @name Register TRNG_SCR5L, field RUN5_MAX[10:0] (RW)
25679  *
25680  * Run Length 5 Maximum Limit. Defines the maximum allowable runs of length 5
25681  * (for both 0 and 1) detected during entropy generation. The number of runs of
25682  * length 5 detected during entropy generation must be less than RUN5_MAX, else a
25683  * retry or error will occur. This register is cleared to 002Fh (decimal 47) by
25684  * writing the MCTL[RST_DEF] bit to 1.
25685  */
25686 /*@{*/
25687 /*! @brief Read current value of the TRNG_SCR5L_RUN5_MAX field. */
25688 #define TRNG_RD_SCR5L_RUN5_MAX(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_MAX_MASK) >> TRNG_SCR5L_RUN5_MAX_SHIFT)
25689 #define TRNG_BRD_SCR5L_RUN5_MAX(base) (BME_UBFX32(&TRNG_SCR5L_REG(base), TRNG_SCR5L_RUN5_MAX_SHIFT, TRNG_SCR5L_RUN5_MAX_WIDTH))
25690 
25691 /*! @brief Set the RUN5_MAX field to a new value. */
25692 #define TRNG_WR_SCR5L_RUN5_MAX(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_MAX_MASK, TRNG_SCR5L_RUN5_MAX(value)))
25693 #define TRNG_BWR_SCR5L_RUN5_MAX(base, value) (BME_BFI32(&TRNG_SCR5L_REG(base), ((uint32_t)(value) << TRNG_SCR5L_RUN5_MAX_SHIFT), TRNG_SCR5L_RUN5_MAX_SHIFT, TRNG_SCR5L_RUN5_MAX_WIDTH))
25694 /*@}*/
25695 
25696 /*!
25697  * @name Register TRNG_SCR5L, field RUN5_RNG[26:16] (RW)
25698  *
25699  * Run Length 5 Range. The number of runs of length 5 (for both 0 and 1)
25700  * detected during entropy generation must be greater than RUN5_MAX - RUN5_RNG, else a
25701  * retry or error will occur. This register is cleared to 002Eh (decimal 46) by
25702  * writing the MCTL[RST_DEF] bit to 1.
25703  */
25704 /*@{*/
25705 /*! @brief Read current value of the TRNG_SCR5L_RUN5_RNG field. */
25706 #define TRNG_RD_SCR5L_RUN5_RNG(base) ((TRNG_SCR5L_REG(base) & TRNG_SCR5L_RUN5_RNG_MASK) >> TRNG_SCR5L_RUN5_RNG_SHIFT)
25707 #define TRNG_BRD_SCR5L_RUN5_RNG(base) (BME_UBFX32(&TRNG_SCR5L_REG(base), TRNG_SCR5L_RUN5_RNG_SHIFT, TRNG_SCR5L_RUN5_RNG_WIDTH))
25708 
25709 /*! @brief Set the RUN5_RNG field to a new value. */
25710 #define TRNG_WR_SCR5L_RUN5_RNG(base, value) (TRNG_RMW_SCR5L(base, TRNG_SCR5L_RUN5_RNG_MASK, TRNG_SCR5L_RUN5_RNG(value)))
25711 #define TRNG_BWR_SCR5L_RUN5_RNG(base, value) (BME_BFI32(&TRNG_SCR5L_REG(base), ((uint32_t)(value) << TRNG_SCR5L_RUN5_RNG_SHIFT), TRNG_SCR5L_RUN5_RNG_SHIFT, TRNG_SCR5L_RUN5_RNG_WIDTH))
25712 /*@}*/
25713 
25714 /*******************************************************************************
25715  * TRNG_SCR5C - RNG Statistical Check Run Length 5 Count Register
25716  ******************************************************************************/
25717 
25718 /*!
25719  * @brief TRNG_SCR5C - RNG Statistical Check Run Length 5 Count Register (RO)
25720  *
25721  * Reset value: 0x00000000U
25722  *
25723  * The RNG Statistical Check Run Length 5 Counters Register is a read-only
25724  * register used to read the final Run Length 5 counts after entropy generation. These
25725  * counters start with the value in SCR5L[RUN5_MAX]. The R5_1_CT decrements each
25726  * time five consecutive ones are sampled (preceded by a zero and followed by a
25727  * zero). The R5_0_CT decrements each time five consecutive zeroes are sampled
25728  * (preceded by a one and followed by a one). Note that this offset (0xBASE_0634)
25729  * is used as SCR5L if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is used as
25730  * SCR5C readback register, as described here.
25731  */
25732 /*!
25733  * @name Constants and macros for entire TRNG_SCR5C register
25734  */
25735 /*@{*/
25736 #define TRNG_RD_SCR5C(base)      (TRNG_SCR5C_REG(base))
25737 /*@}*/
25738 
25739 /*
25740  * Constants & macros for individual TRNG_SCR5C bitfields
25741  */
25742 
25743 /*!
25744  * @name Register TRNG_SCR5C, field R5_0_CT[10:0] (RO)
25745  *
25746  * Runs of Zero, Length 5 Count. Reads the final Runs of Ones, length 5 count
25747  * after entropy generation. Requires MCTL[PRGM] = 0.
25748  */
25749 /*@{*/
25750 /*! @brief Read current value of the TRNG_SCR5C_R5_0_CT field. */
25751 #define TRNG_RD_SCR5C_R5_0_CT(base) ((TRNG_SCR5C_REG(base) & TRNG_SCR5C_R5_0_CT_MASK) >> TRNG_SCR5C_R5_0_CT_SHIFT)
25752 #define TRNG_BRD_SCR5C_R5_0_CT(base) (BME_UBFX32(&TRNG_SCR5C_REG(base), TRNG_SCR5C_R5_0_CT_SHIFT, TRNG_SCR5C_R5_0_CT_WIDTH))
25753 /*@}*/
25754 
25755 /*!
25756  * @name Register TRNG_SCR5C, field R5_1_CT[26:16] (RO)
25757  *
25758  * Runs of One, Length 5 Count. Reads the final Runs of Ones, length 5 count
25759  * after entropy generation. Requires MCTL[PRGM] = 0.
25760  */
25761 /*@{*/
25762 /*! @brief Read current value of the TRNG_SCR5C_R5_1_CT field. */
25763 #define TRNG_RD_SCR5C_R5_1_CT(base) ((TRNG_SCR5C_REG(base) & TRNG_SCR5C_R5_1_CT_MASK) >> TRNG_SCR5C_R5_1_CT_SHIFT)
25764 #define TRNG_BRD_SCR5C_R5_1_CT(base) (BME_UBFX32(&TRNG_SCR5C_REG(base), TRNG_SCR5C_R5_1_CT_SHIFT, TRNG_SCR5C_R5_1_CT_WIDTH))
25765 /*@}*/
25766 
25767 /*******************************************************************************
25768  * TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register
25769  ******************************************************************************/
25770 
25771 /*!
25772  * @brief TRNG_SCR6PL - RNG Statistical Check Run Length 6+ Limit Register (RW)
25773  *
25774  * Reset value: 0x002E002FU
25775  *
25776  * The RNG Statistical Check Run Length 6+ Limit Register defines the allowable
25777  * maximum and minimum number of runs of length 6 or more detected during entropy
25778  * generation. To pass the test, the number of runs of length 6 or more (for
25779  * samples of both 0 and 1) must be less than the programmed maximum value, and the
25780  * number of runs of length 6 or more must be greater than (maximum - range). If
25781  * this test fails, the Retry Counter in SCMISC will be decremented, and a retry
25782  * will occur if the Retry Count has not reached zero. If the Retry Count has
25783  * reached zero, an error will be generated. Note that this offset (0xBASE_0638) is
25784  * used as SCR6PL only if MCTL[PRGM] is 1. If MCTL[PRGM] is 0, this offset is
25785  * used as SCR6PC readback register.
25786  */
25787 /*!
25788  * @name Constants and macros for entire TRNG_SCR6PL register
25789  */
25790 /*@{*/
25791 #define TRNG_RD_SCR6PL(base)     (TRNG_SCR6PL_REG(base))
25792 #define TRNG_WR_SCR6PL(base, value) (TRNG_SCR6PL_REG(base) = (value))
25793 #define TRNG_RMW_SCR6PL(base, mask, value) (TRNG_WR_SCR6PL(base, (TRNG_RD_SCR6PL(base) & ~(mask)) | (value)))
25794 #define TRNG_SET_SCR6PL(base, value) (BME_OR32(&TRNG_SCR6PL_REG(base), (uint32_t)(value)))
25795 #define TRNG_CLR_SCR6PL(base, value) (BME_AND32(&TRNG_SCR6PL_REG(base), (uint32_t)(~(value))))
25796 #define TRNG_TOG_SCR6PL(base, value) (BME_XOR32(&TRNG_SCR6PL_REG(base), (uint32_t)(value)))
25797 /*@}*/
25798 
25799 /*
25800  * Constants & macros for individual TRNG_SCR6PL bitfields
25801  */
25802 
25803 /*!
25804  * @name Register TRNG_SCR6PL, field RUN6P_MAX[10:0] (RW)
25805  *
25806  * Run Length 6+ Maximum Limit. Defines the maximum allowable runs of length 6
25807  * or more (for both 0 and 1) detected during entropy generation. The number of
25808  * runs of length 6 or more detected during entropy generation must be less than
25809  * RUN6P_MAX, else a retry or error will occur. This register is cleared to 002Fh
25810  * (decimal 47) by writing the MCTL[RST_DEF] bit to 1.
25811  */
25812 /*@{*/
25813 /*! @brief Read current value of the TRNG_SCR6PL_RUN6P_MAX field. */
25814 #define TRNG_RD_SCR6PL_RUN6P_MAX(base) ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_MAX_MASK) >> TRNG_SCR6PL_RUN6P_MAX_SHIFT)
25815 #define TRNG_BRD_SCR6PL_RUN6P_MAX(base) (BME_UBFX32(&TRNG_SCR6PL_REG(base), TRNG_SCR6PL_RUN6P_MAX_SHIFT, TRNG_SCR6PL_RUN6P_MAX_WIDTH))
25816 
25817 /*! @brief Set the RUN6P_MAX field to a new value. */
25818 #define TRNG_WR_SCR6PL_RUN6P_MAX(base, value) (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_MAX_MASK, TRNG_SCR6PL_RUN6P_MAX(value)))
25819 #define TRNG_BWR_SCR6PL_RUN6P_MAX(base, value) (BME_BFI32(&TRNG_SCR6PL_REG(base), ((uint32_t)(value) << TRNG_SCR6PL_RUN6P_MAX_SHIFT), TRNG_SCR6PL_RUN6P_MAX_SHIFT, TRNG_SCR6PL_RUN6P_MAX_WIDTH))
25820 /*@}*/
25821 
25822 /*!
25823  * @name Register TRNG_SCR6PL, field RUN6P_RNG[26:16] (RW)
25824  *
25825  * Run Length 6+ Range. The number of runs of length 6 or more (for both 0 and
25826  * 1) detected during entropy generation must be greater than RUN6P_MAX -
25827  * RUN6P_RNG, else a retry or error will occur. This register is cleared to 002Eh
25828  * (decimal 46) by writing the MCTL[RST_DEF] bit to 1.
25829  */
25830 /*@{*/
25831 /*! @brief Read current value of the TRNG_SCR6PL_RUN6P_RNG field. */
25832 #define TRNG_RD_SCR6PL_RUN6P_RNG(base) ((TRNG_SCR6PL_REG(base) & TRNG_SCR6PL_RUN6P_RNG_MASK) >> TRNG_SCR6PL_RUN6P_RNG_SHIFT)
25833 #define TRNG_BRD_SCR6PL_RUN6P_RNG(base) (BME_UBFX32(&TRNG_SCR6PL_REG(base), TRNG_SCR6PL_RUN6P_RNG_SHIFT, TRNG_SCR6PL_RUN6P_RNG_WIDTH))
25834 
25835 /*! @brief Set the RUN6P_RNG field to a new value. */
25836 #define TRNG_WR_SCR6PL_RUN6P_RNG(base, value) (TRNG_RMW_SCR6PL(base, TRNG_SCR6PL_RUN6P_RNG_MASK, TRNG_SCR6PL_RUN6P_RNG(value)))
25837 #define TRNG_BWR_SCR6PL_RUN6P_RNG(base, value) (BME_BFI32(&TRNG_SCR6PL_REG(base), ((uint32_t)(value) << TRNG_SCR6PL_RUN6P_RNG_SHIFT), TRNG_SCR6PL_RUN6P_RNG_SHIFT, TRNG_SCR6PL_RUN6P_RNG_WIDTH))
25838 /*@}*/
25839 
25840 /*******************************************************************************
25841  * TRNG_SCR6PC - RNG Statistical Check Run Length 6+ Count Register
25842  ******************************************************************************/
25843 
25844 /*!
25845  * @brief TRNG_SCR6PC - RNG Statistical Check Run Length 6+ Count Register (RO)
25846  *
25847  * Reset value: 0x00000000U
25848  *
25849  * The RNG Statistical Check Run Length 6+ Counters Register is a read-only
25850  * register used to read the final Run Length 6+ counts after entropy generation.
25851  * These counters start with the value in SCR6PL[RUN6P_MAX]. The R6P_1_CT decrements
25852  * each time six or more consecutive ones are sampled (preceded by a zero and
25853  * followed by a zero). The R6P_0_CT decrements each time six or more consecutive
25854  * zeroes are sampled (preceded by a one and followed by a one). Note that this
25855  * offset (0xBASE_0638) is used as SCR6PL if MCTL[PRGM] is 1. If MCTL[PRGM] is 0,
25856  * this offset is used as SCR6PC readback register, as described here.
25857  */
25858 /*!
25859  * @name Constants and macros for entire TRNG_SCR6PC register
25860  */
25861 /*@{*/
25862 #define TRNG_RD_SCR6PC(base)     (TRNG_SCR6PC_REG(base))
25863 /*@}*/
25864 
25865 /*
25866  * Constants & macros for individual TRNG_SCR6PC bitfields
25867  */
25868 
25869 /*!
25870  * @name Register TRNG_SCR6PC, field R6P_0_CT[10:0] (RO)
25871  *
25872  * Runs of Zero, Length 6+ Count. Reads the final Runs of Ones, length 6+ count
25873  * after entropy generation. Requires MCTL[PRGM] = 0.
25874  */
25875 /*@{*/
25876 /*! @brief Read current value of the TRNG_SCR6PC_R6P_0_CT field. */
25877 #define TRNG_RD_SCR6PC_R6P_0_CT(base) ((TRNG_SCR6PC_REG(base) & TRNG_SCR6PC_R6P_0_CT_MASK) >> TRNG_SCR6PC_R6P_0_CT_SHIFT)
25878 #define TRNG_BRD_SCR6PC_R6P_0_CT(base) (BME_UBFX32(&TRNG_SCR6PC_REG(base), TRNG_SCR6PC_R6P_0_CT_SHIFT, TRNG_SCR6PC_R6P_0_CT_WIDTH))
25879 /*@}*/
25880 
25881 /*!
25882  * @name Register TRNG_SCR6PC, field R6P_1_CT[26:16] (RO)
25883  *
25884  * Runs of One, Length 6+ Count. Reads the final Runs of Ones, length 6+ count
25885  * after entropy generation. Requires MCTL[PRGM] = 0.
25886  */
25887 /*@{*/
25888 /*! @brief Read current value of the TRNG_SCR6PC_R6P_1_CT field. */
25889 #define TRNG_RD_SCR6PC_R6P_1_CT(base) ((TRNG_SCR6PC_REG(base) & TRNG_SCR6PC_R6P_1_CT_MASK) >> TRNG_SCR6PC_R6P_1_CT_SHIFT)
25890 #define TRNG_BRD_SCR6PC_R6P_1_CT(base) (BME_UBFX32(&TRNG_SCR6PC_REG(base), TRNG_SCR6PC_R6P_1_CT_SHIFT, TRNG_SCR6PC_R6P_1_CT_WIDTH))
25891 /*@}*/
25892 
25893 /*******************************************************************************
25894  * TRNG_STATUS - RNG Status Register
25895  ******************************************************************************/
25896 
25897 /*!
25898  * @brief TRNG_STATUS - RNG Status Register (RO)
25899  *
25900  * Reset value: 0x00000000U
25901  *
25902  * Various statistical tests are run as a normal part of the TRNG's entropy
25903  * generation process. The least-significant 16 bits of the STATUS register reflect
25904  * the result of each of these tests. The status of these bits will be valid when
25905  * the TRNG has finished its entropy generation process. Software can determine
25906  * when this occurs by polling the ENT_VAL bit in the RNG Miscellaneous Control
25907  * Register. Note that there is a very small probability that a statistical test
25908  * will fail even though the TRNG is operating properly. If this happens the TRNG
25909  * will automatically retry the entire entropy generation process, including
25910  * running all the statistical tests. The value in RETRY_CT is decremented each time
25911  * an entropy generation retry occurs. If a statistical check fails when the retry
25912  * count is nonzero, a retry is initiated. But if a statistical check fails when
25913  * the retry count is zero, an error is generated by the RNG. By default
25914  * RETRY_CT is initialized to 1, but software can increase the retry count by writing to
25915  * the RTY_CT field in the SCMISC register. All 0s will be returned if this
25916  * register address is read while the RNG is in Program Mode (see PRGM field in MCTL
25917  * register. If this register is read while the RNG is in Run Mode the value
25918  * returned will be formatted as follows.
25919  */
25920 /*!
25921  * @name Constants and macros for entire TRNG_STATUS register
25922  */
25923 /*@{*/
25924 #define TRNG_RD_STATUS(base)     (TRNG_STATUS_REG(base))
25925 /*@}*/
25926 
25927 /*
25928  * Constants & macros for individual TRNG_STATUS bitfields
25929  */
25930 
25931 /*!
25932  * @name Register TRNG_STATUS, field TF1BR0[0] (RO)
25933  *
25934  * Test Fail, 1-Bit Run, Sampling 0s. If TF1BR0=1, the 1-Bit Run, Sampling 0s
25935  * Test has failed.
25936  */
25937 /*@{*/
25938 /*! @brief Read current value of the TRNG_STATUS_TF1BR0 field. */
25939 #define TRNG_RD_STATUS_TF1BR0(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF1BR0_MASK) >> TRNG_STATUS_TF1BR0_SHIFT)
25940 #define TRNG_BRD_STATUS_TF1BR0(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF1BR0_SHIFT, TRNG_STATUS_TF1BR0_WIDTH))
25941 /*@}*/
25942 
25943 /*!
25944  * @name Register TRNG_STATUS, field TF1BR1[1] (RO)
25945  *
25946  * Test Fail, 1-Bit Run, Sampling 1s. If TF1BR1=1, the 1-Bit Run, Sampling 1s
25947  * Test has failed.
25948  */
25949 /*@{*/
25950 /*! @brief Read current value of the TRNG_STATUS_TF1BR1 field. */
25951 #define TRNG_RD_STATUS_TF1BR1(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF1BR1_MASK) >> TRNG_STATUS_TF1BR1_SHIFT)
25952 #define TRNG_BRD_STATUS_TF1BR1(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF1BR1_SHIFT, TRNG_STATUS_TF1BR1_WIDTH))
25953 /*@}*/
25954 
25955 /*!
25956  * @name Register TRNG_STATUS, field TF2BR0[2] (RO)
25957  *
25958  * Test Fail, 2-Bit Run, Sampling 0s. If TF2BR0=1, the 2-Bit Run, Sampling 0s
25959  * Test has failed.
25960  */
25961 /*@{*/
25962 /*! @brief Read current value of the TRNG_STATUS_TF2BR0 field. */
25963 #define TRNG_RD_STATUS_TF2BR0(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF2BR0_MASK) >> TRNG_STATUS_TF2BR0_SHIFT)
25964 #define TRNG_BRD_STATUS_TF2BR0(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF2BR0_SHIFT, TRNG_STATUS_TF2BR0_WIDTH))
25965 /*@}*/
25966 
25967 /*!
25968  * @name Register TRNG_STATUS, field TF2BR1[3] (RO)
25969  *
25970  * Test Fail, 2-Bit Run, Sampling 1s. If TF2BR1=1, the 2-Bit Run, Sampling 1s
25971  * Test has failed.
25972  */
25973 /*@{*/
25974 /*! @brief Read current value of the TRNG_STATUS_TF2BR1 field. */
25975 #define TRNG_RD_STATUS_TF2BR1(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF2BR1_MASK) >> TRNG_STATUS_TF2BR1_SHIFT)
25976 #define TRNG_BRD_STATUS_TF2BR1(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF2BR1_SHIFT, TRNG_STATUS_TF2BR1_WIDTH))
25977 /*@}*/
25978 
25979 /*!
25980  * @name Register TRNG_STATUS, field TF3BR0[4] (RO)
25981  *
25982  * Test Fail, 3-Bit Run, Sampling 0s. If TF3BR0=1, the 3-Bit Run, Sampling 0s
25983  * Test has failed.
25984  */
25985 /*@{*/
25986 /*! @brief Read current value of the TRNG_STATUS_TF3BR0 field. */
25987 #define TRNG_RD_STATUS_TF3BR0(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF3BR0_MASK) >> TRNG_STATUS_TF3BR0_SHIFT)
25988 #define TRNG_BRD_STATUS_TF3BR0(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF3BR0_SHIFT, TRNG_STATUS_TF3BR0_WIDTH))
25989 /*@}*/
25990 
25991 /*!
25992  * @name Register TRNG_STATUS, field TF3BR1[5] (RO)
25993  *
25994  * Test Fail, 3-Bit Run, Sampling 1s. If TF3BR1=1, the 3-Bit Run, Sampling 1s
25995  * Test has failed.
25996  */
25997 /*@{*/
25998 /*! @brief Read current value of the TRNG_STATUS_TF3BR1 field. */
25999 #define TRNG_RD_STATUS_TF3BR1(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF3BR1_MASK) >> TRNG_STATUS_TF3BR1_SHIFT)
26000 #define TRNG_BRD_STATUS_TF3BR1(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF3BR1_SHIFT, TRNG_STATUS_TF3BR1_WIDTH))
26001 /*@}*/
26002 
26003 /*!
26004  * @name Register TRNG_STATUS, field TF4BR0[6] (RO)
26005  *
26006  * Test Fail, 4-Bit Run, Sampling 0s. If TF4BR0=1, the 4-Bit Run, Sampling 0s
26007  * Test has failed.
26008  */
26009 /*@{*/
26010 /*! @brief Read current value of the TRNG_STATUS_TF4BR0 field. */
26011 #define TRNG_RD_STATUS_TF4BR0(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF4BR0_MASK) >> TRNG_STATUS_TF4BR0_SHIFT)
26012 #define TRNG_BRD_STATUS_TF4BR0(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF4BR0_SHIFT, TRNG_STATUS_TF4BR0_WIDTH))
26013 /*@}*/
26014 
26015 /*!
26016  * @name Register TRNG_STATUS, field TF4BR1[7] (RO)
26017  *
26018  * Test Fail, 4-Bit Run, Sampling 1s. If TF4BR1=1, the 4-Bit Run, Sampling 1s
26019  * Test has failed.
26020  */
26021 /*@{*/
26022 /*! @brief Read current value of the TRNG_STATUS_TF4BR1 field. */
26023 #define TRNG_RD_STATUS_TF4BR1(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF4BR1_MASK) >> TRNG_STATUS_TF4BR1_SHIFT)
26024 #define TRNG_BRD_STATUS_TF4BR1(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF4BR1_SHIFT, TRNG_STATUS_TF4BR1_WIDTH))
26025 /*@}*/
26026 
26027 /*!
26028  * @name Register TRNG_STATUS, field TF5BR0[8] (RO)
26029  *
26030  * Test Fail, 5-Bit Run, Sampling 0s. If TF5BR0=1, the 5-Bit Run, Sampling 0s
26031  * Test has failed.
26032  */
26033 /*@{*/
26034 /*! @brief Read current value of the TRNG_STATUS_TF5BR0 field. */
26035 #define TRNG_RD_STATUS_TF5BR0(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF5BR0_MASK) >> TRNG_STATUS_TF5BR0_SHIFT)
26036 #define TRNG_BRD_STATUS_TF5BR0(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF5BR0_SHIFT, TRNG_STATUS_TF5BR0_WIDTH))
26037 /*@}*/
26038 
26039 /*!
26040  * @name Register TRNG_STATUS, field TF5BR1[9] (RO)
26041  *
26042  * Test Fail, 5-Bit Run, Sampling 1s. If TF5BR1=1, the 5-Bit Run, Sampling 1s
26043  * Test has failed.
26044  */
26045 /*@{*/
26046 /*! @brief Read current value of the TRNG_STATUS_TF5BR1 field. */
26047 #define TRNG_RD_STATUS_TF5BR1(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF5BR1_MASK) >> TRNG_STATUS_TF5BR1_SHIFT)
26048 #define TRNG_BRD_STATUS_TF5BR1(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF5BR1_SHIFT, TRNG_STATUS_TF5BR1_WIDTH))
26049 /*@}*/
26050 
26051 /*!
26052  * @name Register TRNG_STATUS, field TF6PBR0[10] (RO)
26053  *
26054  * Test Fail, 6 Plus Bit Run, Sampling 0s. If TF6PBR0=1, the 6 Plus Bit Run,
26055  * Sampling 0s Test has failed.
26056  */
26057 /*@{*/
26058 /*! @brief Read current value of the TRNG_STATUS_TF6PBR0 field. */
26059 #define TRNG_RD_STATUS_TF6PBR0(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF6PBR0_MASK) >> TRNG_STATUS_TF6PBR0_SHIFT)
26060 #define TRNG_BRD_STATUS_TF6PBR0(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF6PBR0_SHIFT, TRNG_STATUS_TF6PBR0_WIDTH))
26061 /*@}*/
26062 
26063 /*!
26064  * @name Register TRNG_STATUS, field TF6PBR1[11] (RO)
26065  *
26066  * Test Fail, 6 Plus Bit Run, Sampling 1s. If TF6PBR1=1, the 6 Plus Bit Run,
26067  * Sampling 1s Test has failed.
26068  */
26069 /*@{*/
26070 /*! @brief Read current value of the TRNG_STATUS_TF6PBR1 field. */
26071 #define TRNG_RD_STATUS_TF6PBR1(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TF6PBR1_MASK) >> TRNG_STATUS_TF6PBR1_SHIFT)
26072 #define TRNG_BRD_STATUS_TF6PBR1(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TF6PBR1_SHIFT, TRNG_STATUS_TF6PBR1_WIDTH))
26073 /*@}*/
26074 
26075 /*!
26076  * @name Register TRNG_STATUS, field TFSB[12] (RO)
26077  *
26078  * Test Fail, Sparse Bit. If TFSB=1, the Sparse Bit Test has failed.
26079  */
26080 /*@{*/
26081 /*! @brief Read current value of the TRNG_STATUS_TFSB field. */
26082 #define TRNG_RD_STATUS_TFSB(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TFSB_MASK) >> TRNG_STATUS_TFSB_SHIFT)
26083 #define TRNG_BRD_STATUS_TFSB(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TFSB_SHIFT, TRNG_STATUS_TFSB_WIDTH))
26084 /*@}*/
26085 
26086 /*!
26087  * @name Register TRNG_STATUS, field TFLR[13] (RO)
26088  *
26089  * Test Fail, Long Run. If TFLR=1, the Long Run Test has failed.
26090  */
26091 /*@{*/
26092 /*! @brief Read current value of the TRNG_STATUS_TFLR field. */
26093 #define TRNG_RD_STATUS_TFLR(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TFLR_MASK) >> TRNG_STATUS_TFLR_SHIFT)
26094 #define TRNG_BRD_STATUS_TFLR(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TFLR_SHIFT, TRNG_STATUS_TFLR_WIDTH))
26095 /*@}*/
26096 
26097 /*!
26098  * @name Register TRNG_STATUS, field TFP[14] (RO)
26099  *
26100  * Test Fail, Poker. If TFP=1, the Poker Test has failed.
26101  */
26102 /*@{*/
26103 /*! @brief Read current value of the TRNG_STATUS_TFP field. */
26104 #define TRNG_RD_STATUS_TFP(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TFP_MASK) >> TRNG_STATUS_TFP_SHIFT)
26105 #define TRNG_BRD_STATUS_TFP(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TFP_SHIFT, TRNG_STATUS_TFP_WIDTH))
26106 /*@}*/
26107 
26108 /*!
26109  * @name Register TRNG_STATUS, field TFMB[15] (RO)
26110  *
26111  * Test Fail, Mono Bit. If TFMB=1, the Mono Bit Test has failed.
26112  */
26113 /*@{*/
26114 /*! @brief Read current value of the TRNG_STATUS_TFMB field. */
26115 #define TRNG_RD_STATUS_TFMB(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_TFMB_MASK) >> TRNG_STATUS_TFMB_SHIFT)
26116 #define TRNG_BRD_STATUS_TFMB(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_TFMB_SHIFT, TRNG_STATUS_TFMB_WIDTH))
26117 /*@}*/
26118 
26119 /*!
26120  * @name Register TRNG_STATUS, field RETRY_CT[19:16] (RO)
26121  *
26122  * RETRY COUNT. This represents the current number of entropy generation retries
26123  * left before a statistical text failure will cause the RNG to generate an
26124  * error condition.
26125  */
26126 /*@{*/
26127 /*! @brief Read current value of the TRNG_STATUS_RETRY_CT field. */
26128 #define TRNG_RD_STATUS_RETRY_CT(base) ((TRNG_STATUS_REG(base) & TRNG_STATUS_RETRY_CT_MASK) >> TRNG_STATUS_RETRY_CT_SHIFT)
26129 #define TRNG_BRD_STATUS_RETRY_CT(base) (BME_UBFX32(&TRNG_STATUS_REG(base), TRNG_STATUS_RETRY_CT_SHIFT, TRNG_STATUS_RETRY_CT_WIDTH))
26130 /*@}*/
26131 
26132 /*******************************************************************************
26133  * TRNG_ENT - RNG TRNG Entropy Read Register
26134  ******************************************************************************/
26135 
26136 /*!
26137  * @brief TRNG_ENT - RNG TRNG Entropy Read Register (RO)
26138  *
26139  * Reset value: 0x00000000U
26140  *
26141  * The RNG TRNG can be programmed to generate an entropy value that is readable
26142  * via the SkyBlue bus. To do this, set the MCTL[TRNG_ACC] bit to 1. Once the
26143  * entropy value has been generated, the MCTL[ENT_VAL] bit will be set to 1. At this
26144  * point, ENT0 through ENT15 may be read to retrieve the 512-bit entropy value.
26145  * Note that once ENT15 is read, the entropy value will be cleared and a new
26146  * value will begin generation, so it is important that ENT15 be read last. These
26147  * registers are readable only when MCTL[PRGM] = 0 (Run Mode), MCTL[TRNG_ACC] = 1
26148  * (TRNG access mode) and MCTL[ENT_VAL] = 1, otherwise zeroes will be read.
26149  */
26150 /*!
26151  * @name Constants and macros for entire TRNG_ENT register
26152  */
26153 /*@{*/
26154 #define TRNG_RD_ENT(base, index) (TRNG_ENT_REG(base, index))
26155 /*@}*/
26156 
26157 /*******************************************************************************
26158  * TRNG_PKRCNT10 - RNG Statistical Check Poker Count 1 and 0 Register
26159  ******************************************************************************/
26160 
26161 /*!
26162  * @brief TRNG_PKRCNT10 - RNG Statistical Check Poker Count 1 and 0 Register (RO)
26163  *
26164  * Reset value: 0x00000000U
26165  *
26166  * The RNG Statistical Check Poker Count 1 and 0 Register is a read-only
26167  * register used to read the final Poker test counts of 1h and 0h patterns. The Poker 0h
26168  * Count increments each time a nibble of sample data is found to be 0h. The
26169  * Poker 1h Count increments each time a nibble of sample data is found to be 1h.
26170  * Note that this register is readable only if MCTL[PRGM] is 0, otherwise zeroes
26171  * will be read.
26172  */
26173 /*!
26174  * @name Constants and macros for entire TRNG_PKRCNT10 register
26175  */
26176 /*@{*/
26177 #define TRNG_RD_PKRCNT10(base)   (TRNG_PKRCNT10_REG(base))
26178 /*@}*/
26179 
26180 /*
26181  * Constants & macros for individual TRNG_PKRCNT10 bitfields
26182  */
26183 
26184 /*!
26185  * @name Register TRNG_PKRCNT10, field PKR_0_CT[15:0] (RO)
26186  *
26187  * Poker 0h Count. Total number of nibbles of sample data which were found to be
26188  * 0h. Requires MCTL[PRGM] = 0.
26189  */
26190 /*@{*/
26191 /*! @brief Read current value of the TRNG_PKRCNT10_PKR_0_CT field. */
26192 #define TRNG_RD_PKRCNT10_PKR_0_CT(base) ((TRNG_PKRCNT10_REG(base) & TRNG_PKRCNT10_PKR_0_CT_MASK) >> TRNG_PKRCNT10_PKR_0_CT_SHIFT)
26193 #define TRNG_BRD_PKRCNT10_PKR_0_CT(base) (BME_UBFX32(&TRNG_PKRCNT10_REG(base), TRNG_PKRCNT10_PKR_0_CT_SHIFT, TRNG_PKRCNT10_PKR_0_CT_WIDTH))
26194 /*@}*/
26195 
26196 /*!
26197  * @name Register TRNG_PKRCNT10, field PKR_1_CT[31:16] (RO)
26198  *
26199  * Poker 1h Count. Total number of nibbles of sample data which were found to be
26200  * 1h. Requires MCTL[PRGM] = 0.
26201  */
26202 /*@{*/
26203 /*! @brief Read current value of the TRNG_PKRCNT10_PKR_1_CT field. */
26204 #define TRNG_RD_PKRCNT10_PKR_1_CT(base) ((TRNG_PKRCNT10_REG(base) & TRNG_PKRCNT10_PKR_1_CT_MASK) >> TRNG_PKRCNT10_PKR_1_CT_SHIFT)
26205 #define TRNG_BRD_PKRCNT10_PKR_1_CT(base) (BME_UBFX32(&TRNG_PKRCNT10_REG(base), TRNG_PKRCNT10_PKR_1_CT_SHIFT, TRNG_PKRCNT10_PKR_1_CT_WIDTH))
26206 /*@}*/
26207 
26208 /*******************************************************************************
26209  * TRNG_PKRCNT32 - RNG Statistical Check Poker Count 3 and 2 Register
26210  ******************************************************************************/
26211 
26212 /*!
26213  * @brief TRNG_PKRCNT32 - RNG Statistical Check Poker Count 3 and 2 Register (RO)
26214  *
26215  * Reset value: 0x00000000U
26216  *
26217  * The RNG Statistical Check Poker Count 3 and 2 Register is a read-only
26218  * register used to read the final Poker test counts of 3h and 2h patterns. The Poker 2h
26219  * Count increments each time a nibble of sample data is found to be 2h. The
26220  * Poker 3h Count increments each time a nibble of sample data is found to be 3h.
26221  * Note that this register is readable only if MCTL[PRGM] is 0, otherwise zeroes
26222  * will be read.
26223  */
26224 /*!
26225  * @name Constants and macros for entire TRNG_PKRCNT32 register
26226  */
26227 /*@{*/
26228 #define TRNG_RD_PKRCNT32(base)   (TRNG_PKRCNT32_REG(base))
26229 /*@}*/
26230 
26231 /*
26232  * Constants & macros for individual TRNG_PKRCNT32 bitfields
26233  */
26234 
26235 /*!
26236  * @name Register TRNG_PKRCNT32, field PKR_2_CT[15:0] (RO)
26237  *
26238  * Poker 2h Count. Total number of nibbles of sample data which were found to be
26239  * 2h. Requires MCTL[PRGM] = 0.
26240  */
26241 /*@{*/
26242 /*! @brief Read current value of the TRNG_PKRCNT32_PKR_2_CT field. */
26243 #define TRNG_RD_PKRCNT32_PKR_2_CT(base) ((TRNG_PKRCNT32_REG(base) & TRNG_PKRCNT32_PKR_2_CT_MASK) >> TRNG_PKRCNT32_PKR_2_CT_SHIFT)
26244 #define TRNG_BRD_PKRCNT32_PKR_2_CT(base) (BME_UBFX32(&TRNG_PKRCNT32_REG(base), TRNG_PKRCNT32_PKR_2_CT_SHIFT, TRNG_PKRCNT32_PKR_2_CT_WIDTH))
26245 /*@}*/
26246 
26247 /*!
26248  * @name Register TRNG_PKRCNT32, field PKR_3_CT[31:16] (RO)
26249  *
26250  * Poker 3h Count. Total number of nibbles of sample data which were found to be
26251  * 3h. Requires MCTL[PRGM] = 0.
26252  */
26253 /*@{*/
26254 /*! @brief Read current value of the TRNG_PKRCNT32_PKR_3_CT field. */
26255 #define TRNG_RD_PKRCNT32_PKR_3_CT(base) ((TRNG_PKRCNT32_REG(base) & TRNG_PKRCNT32_PKR_3_CT_MASK) >> TRNG_PKRCNT32_PKR_3_CT_SHIFT)
26256 #define TRNG_BRD_PKRCNT32_PKR_3_CT(base) (BME_UBFX32(&TRNG_PKRCNT32_REG(base), TRNG_PKRCNT32_PKR_3_CT_SHIFT, TRNG_PKRCNT32_PKR_3_CT_WIDTH))
26257 /*@}*/
26258 
26259 /*******************************************************************************
26260  * TRNG_PKRCNT54 - RNG Statistical Check Poker Count 5 and 4 Register
26261  ******************************************************************************/
26262 
26263 /*!
26264  * @brief TRNG_PKRCNT54 - RNG Statistical Check Poker Count 5 and 4 Register (RO)
26265  *
26266  * Reset value: 0x00000000U
26267  *
26268  * The RNG Statistical Check Poker Count 5 and 4 Register is a read-only
26269  * register used to read the final Poker test counts of 5h and 4h patterns. The Poker 4h
26270  * Count increments each time a nibble of sample data is found to be 4h. The
26271  * Poker 5h Count increments each time a nibble of sample data is found to be 5h.
26272  * Note that this register is readable only if MCTL[PRGM] is 0, otherwise zeroes
26273  * will be read.
26274  */
26275 /*!
26276  * @name Constants and macros for entire TRNG_PKRCNT54 register
26277  */
26278 /*@{*/
26279 #define TRNG_RD_PKRCNT54(base)   (TRNG_PKRCNT54_REG(base))
26280 /*@}*/
26281 
26282 /*
26283  * Constants & macros for individual TRNG_PKRCNT54 bitfields
26284  */
26285 
26286 /*!
26287  * @name Register TRNG_PKRCNT54, field PKR_4_CT[15:0] (RO)
26288  *
26289  * Poker 4h Count. Total number of nibbles of sample data which were found to be
26290  * 4h. Requires MCTL[PRGM] = 0.
26291  */
26292 /*@{*/
26293 /*! @brief Read current value of the TRNG_PKRCNT54_PKR_4_CT field. */
26294 #define TRNG_RD_PKRCNT54_PKR_4_CT(base) ((TRNG_PKRCNT54_REG(base) & TRNG_PKRCNT54_PKR_4_CT_MASK) >> TRNG_PKRCNT54_PKR_4_CT_SHIFT)
26295 #define TRNG_BRD_PKRCNT54_PKR_4_CT(base) (BME_UBFX32(&TRNG_PKRCNT54_REG(base), TRNG_PKRCNT54_PKR_4_CT_SHIFT, TRNG_PKRCNT54_PKR_4_CT_WIDTH))
26296 /*@}*/
26297 
26298 /*!
26299  * @name Register TRNG_PKRCNT54, field PKR_5_CT[31:16] (RO)
26300  *
26301  * Poker 5h Count. Total number of nibbles of sample data which were found to be
26302  * 5h. Requires MCTL[PRGM] = 0.
26303  */
26304 /*@{*/
26305 /*! @brief Read current value of the TRNG_PKRCNT54_PKR_5_CT field. */
26306 #define TRNG_RD_PKRCNT54_PKR_5_CT(base) ((TRNG_PKRCNT54_REG(base) & TRNG_PKRCNT54_PKR_5_CT_MASK) >> TRNG_PKRCNT54_PKR_5_CT_SHIFT)
26307 #define TRNG_BRD_PKRCNT54_PKR_5_CT(base) (BME_UBFX32(&TRNG_PKRCNT54_REG(base), TRNG_PKRCNT54_PKR_5_CT_SHIFT, TRNG_PKRCNT54_PKR_5_CT_WIDTH))
26308 /*@}*/
26309 
26310 /*******************************************************************************
26311  * TRNG_PKRCNT76 - RNG Statistical Check Poker Count 7 and 6 Register
26312  ******************************************************************************/
26313 
26314 /*!
26315  * @brief TRNG_PKRCNT76 - RNG Statistical Check Poker Count 7 and 6 Register (RO)
26316  *
26317  * Reset value: 0x00000000U
26318  *
26319  * The RNG Statistical Check Poker Count 7 and 6 Register is a read-only
26320  * register used to read the final Poker test counts of 7h and 6h patterns. The Poker 6h
26321  * Count increments each time a nibble of sample data is found to be 6h. The
26322  * Poker 7h Count increments each time a nibble of sample data is found to be 7h.
26323  * Note that this register is readable only if MCTL[PRGM] is 0, otherwise zeroes
26324  * will be read.
26325  */
26326 /*!
26327  * @name Constants and macros for entire TRNG_PKRCNT76 register
26328  */
26329 /*@{*/
26330 #define TRNG_RD_PKRCNT76(base)   (TRNG_PKRCNT76_REG(base))
26331 /*@}*/
26332 
26333 /*
26334  * Constants & macros for individual TRNG_PKRCNT76 bitfields
26335  */
26336 
26337 /*!
26338  * @name Register TRNG_PKRCNT76, field PKR_6_CT[15:0] (RO)
26339  *
26340  * Poker 6h Count. Total number of nibbles of sample data which were found to be
26341  * 6h. Requires MCTL[PRGM] = 0.
26342  */
26343 /*@{*/
26344 /*! @brief Read current value of the TRNG_PKRCNT76_PKR_6_CT field. */
26345 #define TRNG_RD_PKRCNT76_PKR_6_CT(base) ((TRNG_PKRCNT76_REG(base) & TRNG_PKRCNT76_PKR_6_CT_MASK) >> TRNG_PKRCNT76_PKR_6_CT_SHIFT)
26346 #define TRNG_BRD_PKRCNT76_PKR_6_CT(base) (BME_UBFX32(&TRNG_PKRCNT76_REG(base), TRNG_PKRCNT76_PKR_6_CT_SHIFT, TRNG_PKRCNT76_PKR_6_CT_WIDTH))
26347 /*@}*/
26348 
26349 /*!
26350  * @name Register TRNG_PKRCNT76, field PKR_7_CT[31:16] (RO)
26351  *
26352  * Poker 7h Count. Total number of nibbles of sample data which were found to be
26353  * 7h. Requires MCTL[PRGM] = 0.
26354  */
26355 /*@{*/
26356 /*! @brief Read current value of the TRNG_PKRCNT76_PKR_7_CT field. */
26357 #define TRNG_RD_PKRCNT76_PKR_7_CT(base) ((TRNG_PKRCNT76_REG(base) & TRNG_PKRCNT76_PKR_7_CT_MASK) >> TRNG_PKRCNT76_PKR_7_CT_SHIFT)
26358 #define TRNG_BRD_PKRCNT76_PKR_7_CT(base) (BME_UBFX32(&TRNG_PKRCNT76_REG(base), TRNG_PKRCNT76_PKR_7_CT_SHIFT, TRNG_PKRCNT76_PKR_7_CT_WIDTH))
26359 /*@}*/
26360 
26361 /*******************************************************************************
26362  * TRNG_PKRCNT98 - RNG Statistical Check Poker Count 9 and 8 Register
26363  ******************************************************************************/
26364 
26365 /*!
26366  * @brief TRNG_PKRCNT98 - RNG Statistical Check Poker Count 9 and 8 Register (RO)
26367  *
26368  * Reset value: 0x00000000U
26369  *
26370  * The RNG Statistical Check Poker Count 9 and 8 Register is a read-only
26371  * register used to read the final Poker test counts of 9h and 8h patterns. The Poker 8h
26372  * Count increments each time a nibble of sample data is found to be 8h. The
26373  * Poker 9h Count increments each time a nibble of sample data is found to be 9h.
26374  * Note that this register is readable only if MCTL[PRGM] is 0, otherwise zeroes
26375  * will be read.
26376  */
26377 /*!
26378  * @name Constants and macros for entire TRNG_PKRCNT98 register
26379  */
26380 /*@{*/
26381 #define TRNG_RD_PKRCNT98(base)   (TRNG_PKRCNT98_REG(base))
26382 /*@}*/
26383 
26384 /*
26385  * Constants & macros for individual TRNG_PKRCNT98 bitfields
26386  */
26387 
26388 /*!
26389  * @name Register TRNG_PKRCNT98, field PKR_8_CT[15:0] (RO)
26390  *
26391  * Poker 8h Count. Total number of nibbles of sample data which were found to be
26392  * 8h. Requires MCTL[PRGM] = 0.
26393  */
26394 /*@{*/
26395 /*! @brief Read current value of the TRNG_PKRCNT98_PKR_8_CT field. */
26396 #define TRNG_RD_PKRCNT98_PKR_8_CT(base) ((TRNG_PKRCNT98_REG(base) & TRNG_PKRCNT98_PKR_8_CT_MASK) >> TRNG_PKRCNT98_PKR_8_CT_SHIFT)
26397 #define TRNG_BRD_PKRCNT98_PKR_8_CT(base) (BME_UBFX32(&TRNG_PKRCNT98_REG(base), TRNG_PKRCNT98_PKR_8_CT_SHIFT, TRNG_PKRCNT98_PKR_8_CT_WIDTH))
26398 /*@}*/
26399 
26400 /*!
26401  * @name Register TRNG_PKRCNT98, field PKR_9_CT[31:16] (RO)
26402  *
26403  * Poker 9h Count. Total number of nibbles of sample data which were found to be
26404  * 9h. Requires MCTL[PRGM] = 0.
26405  */
26406 /*@{*/
26407 /*! @brief Read current value of the TRNG_PKRCNT98_PKR_9_CT field. */
26408 #define TRNG_RD_PKRCNT98_PKR_9_CT(base) ((TRNG_PKRCNT98_REG(base) & TRNG_PKRCNT98_PKR_9_CT_MASK) >> TRNG_PKRCNT98_PKR_9_CT_SHIFT)
26409 #define TRNG_BRD_PKRCNT98_PKR_9_CT(base) (BME_UBFX32(&TRNG_PKRCNT98_REG(base), TRNG_PKRCNT98_PKR_9_CT_SHIFT, TRNG_PKRCNT98_PKR_9_CT_WIDTH))
26410 /*@}*/
26411 
26412 /*******************************************************************************
26413  * TRNG_PKRCNTBA - RNG Statistical Check Poker Count B and A Register
26414  ******************************************************************************/
26415 
26416 /*!
26417  * @brief TRNG_PKRCNTBA - RNG Statistical Check Poker Count B and A Register (RO)
26418  *
26419  * Reset value: 0x00000000U
26420  *
26421  * The RNG Statistical Check Poker Count B and A Register is a read-only
26422  * register used to read the final Poker test counts of Bh and Ah patterns. The Poker Ah
26423  * Count increments each time a nibble of sample data is found to be Ah. The
26424  * Poker Bh Count increments each time a nibble of sample data is found to be Bh.
26425  * Note that this register is readable only if MCTL[PRGM] is 0, otherwise zeroes
26426  * will be read.
26427  */
26428 /*!
26429  * @name Constants and macros for entire TRNG_PKRCNTBA register
26430  */
26431 /*@{*/
26432 #define TRNG_RD_PKRCNTBA(base)   (TRNG_PKRCNTBA_REG(base))
26433 /*@}*/
26434 
26435 /*
26436  * Constants & macros for individual TRNG_PKRCNTBA bitfields
26437  */
26438 
26439 /*!
26440  * @name Register TRNG_PKRCNTBA, field PKR_A_CT[15:0] (RO)
26441  *
26442  * Poker Ah Count. Total number of nibbles of sample data which were found to be
26443  * Ah. Requires MCTL[PRGM] = 0.
26444  */
26445 /*@{*/
26446 /*! @brief Read current value of the TRNG_PKRCNTBA_PKR_A_CT field. */
26447 #define TRNG_RD_PKRCNTBA_PKR_A_CT(base) ((TRNG_PKRCNTBA_REG(base) & TRNG_PKRCNTBA_PKR_A_CT_MASK) >> TRNG_PKRCNTBA_PKR_A_CT_SHIFT)
26448 #define TRNG_BRD_PKRCNTBA_PKR_A_CT(base) (BME_UBFX32(&TRNG_PKRCNTBA_REG(base), TRNG_PKRCNTBA_PKR_A_CT_SHIFT, TRNG_PKRCNTBA_PKR_A_CT_WIDTH))
26449 /*@}*/
26450 
26451 /*!
26452  * @name Register TRNG_PKRCNTBA, field PKR_B_CT[31:16] (RO)
26453  *
26454  * Poker Bh Count. Total number of nibbles of sample data which were found to be
26455  * Bh. Requires MCTL[PRGM] = 0.
26456  */
26457 /*@{*/
26458 /*! @brief Read current value of the TRNG_PKRCNTBA_PKR_B_CT field. */
26459 #define TRNG_RD_PKRCNTBA_PKR_B_CT(base) ((TRNG_PKRCNTBA_REG(base) & TRNG_PKRCNTBA_PKR_B_CT_MASK) >> TRNG_PKRCNTBA_PKR_B_CT_SHIFT)
26460 #define TRNG_BRD_PKRCNTBA_PKR_B_CT(base) (BME_UBFX32(&TRNG_PKRCNTBA_REG(base), TRNG_PKRCNTBA_PKR_B_CT_SHIFT, TRNG_PKRCNTBA_PKR_B_CT_WIDTH))
26461 /*@}*/
26462 
26463 /*******************************************************************************
26464  * TRNG_PKRCNTDC - RNG Statistical Check Poker Count D and C Register
26465  ******************************************************************************/
26466 
26467 /*!
26468  * @brief TRNG_PKRCNTDC - RNG Statistical Check Poker Count D and C Register (RO)
26469  *
26470  * Reset value: 0x00000000U
26471  *
26472  * The RNG Statistical Check Poker Count D and C Register is a read-only
26473  * register used to read the final Poker test counts of Dh and Ch patterns. The Poker Ch
26474  * Count increments each time a nibble of sample data is found to be Ch. The
26475  * Poker Dh Count increments each time a nibble of sample data is found to be Dh.
26476  * Note that this register is readable only if MCTL[PRGM] is 0, otherwise zeroes
26477  * will be read.
26478  */
26479 /*!
26480  * @name Constants and macros for entire TRNG_PKRCNTDC register
26481  */
26482 /*@{*/
26483 #define TRNG_RD_PKRCNTDC(base)   (TRNG_PKRCNTDC_REG(base))
26484 /*@}*/
26485 
26486 /*
26487  * Constants & macros for individual TRNG_PKRCNTDC bitfields
26488  */
26489 
26490 /*!
26491  * @name Register TRNG_PKRCNTDC, field PKR_C_CT[15:0] (RO)
26492  *
26493  * Poker Ch Count. Total number of nibbles of sample data which were found to be
26494  * Ch. Requires MCTL[PRGM] = 0.
26495  */
26496 /*@{*/
26497 /*! @brief Read current value of the TRNG_PKRCNTDC_PKR_C_CT field. */
26498 #define TRNG_RD_PKRCNTDC_PKR_C_CT(base) ((TRNG_PKRCNTDC_REG(base) & TRNG_PKRCNTDC_PKR_C_CT_MASK) >> TRNG_PKRCNTDC_PKR_C_CT_SHIFT)
26499 #define TRNG_BRD_PKRCNTDC_PKR_C_CT(base) (BME_UBFX32(&TRNG_PKRCNTDC_REG(base), TRNG_PKRCNTDC_PKR_C_CT_SHIFT, TRNG_PKRCNTDC_PKR_C_CT_WIDTH))
26500 /*@}*/
26501 
26502 /*!
26503  * @name Register TRNG_PKRCNTDC, field PKR_D_CT[31:16] (RO)
26504  *
26505  * Poker Dh Count. Total number of nibbles of sample data which were found to be
26506  * Dh. Requires MCTL[PRGM] = 0.
26507  */
26508 /*@{*/
26509 /*! @brief Read current value of the TRNG_PKRCNTDC_PKR_D_CT field. */
26510 #define TRNG_RD_PKRCNTDC_PKR_D_CT(base) ((TRNG_PKRCNTDC_REG(base) & TRNG_PKRCNTDC_PKR_D_CT_MASK) >> TRNG_PKRCNTDC_PKR_D_CT_SHIFT)
26511 #define TRNG_BRD_PKRCNTDC_PKR_D_CT(base) (BME_UBFX32(&TRNG_PKRCNTDC_REG(base), TRNG_PKRCNTDC_PKR_D_CT_SHIFT, TRNG_PKRCNTDC_PKR_D_CT_WIDTH))
26512 /*@}*/
26513 
26514 /*******************************************************************************
26515  * TRNG_PKRCNTFE - RNG Statistical Check Poker Count F and E Register
26516  ******************************************************************************/
26517 
26518 /*!
26519  * @brief TRNG_PKRCNTFE - RNG Statistical Check Poker Count F and E Register (RO)
26520  *
26521  * Reset value: 0x00000000U
26522  *
26523  * The RNG Statistical Check Poker Count F and E Register is a read-only
26524  * register used to read the final Poker test counts of Fh and Eh patterns. The Poker Eh
26525  * Count increments each time a nibble of sample data is found to be Eh. The
26526  * Poker Fh Count increments each time a nibble of sample data is found to be Fh.
26527  * Note that this register is readable only if MCTL[PRGM] is 0, otherwise zeroes
26528  * will be read.
26529  */
26530 /*!
26531  * @name Constants and macros for entire TRNG_PKRCNTFE register
26532  */
26533 /*@{*/
26534 #define TRNG_RD_PKRCNTFE(base)   (TRNG_PKRCNTFE_REG(base))
26535 /*@}*/
26536 
26537 /*
26538  * Constants & macros for individual TRNG_PKRCNTFE bitfields
26539  */
26540 
26541 /*!
26542  * @name Register TRNG_PKRCNTFE, field PKR_E_CT[15:0] (RO)
26543  *
26544  * Poker Eh Count. Total number of nibbles of sample data which were found to be
26545  * Eh. Requires MCTL[PRGM] = 0.
26546  */
26547 /*@{*/
26548 /*! @brief Read current value of the TRNG_PKRCNTFE_PKR_E_CT field. */
26549 #define TRNG_RD_PKRCNTFE_PKR_E_CT(base) ((TRNG_PKRCNTFE_REG(base) & TRNG_PKRCNTFE_PKR_E_CT_MASK) >> TRNG_PKRCNTFE_PKR_E_CT_SHIFT)
26550 #define TRNG_BRD_PKRCNTFE_PKR_E_CT(base) (BME_UBFX32(&TRNG_PKRCNTFE_REG(base), TRNG_PKRCNTFE_PKR_E_CT_SHIFT, TRNG_PKRCNTFE_PKR_E_CT_WIDTH))
26551 /*@}*/
26552 
26553 /*!
26554  * @name Register TRNG_PKRCNTFE, field PKR_F_CT[31:16] (RO)
26555  *
26556  * Poker Fh Count. Total number of nibbles of sample data which were found to be
26557  * Fh. Requires MCTL[PRGM] = 0.
26558  */
26559 /*@{*/
26560 /*! @brief Read current value of the TRNG_PKRCNTFE_PKR_F_CT field. */
26561 #define TRNG_RD_PKRCNTFE_PKR_F_CT(base) ((TRNG_PKRCNTFE_REG(base) & TRNG_PKRCNTFE_PKR_F_CT_MASK) >> TRNG_PKRCNTFE_PKR_F_CT_SHIFT)
26562 #define TRNG_BRD_PKRCNTFE_PKR_F_CT(base) (BME_UBFX32(&TRNG_PKRCNTFE_REG(base), TRNG_PKRCNTFE_PKR_F_CT_SHIFT, TRNG_PKRCNTFE_PKR_F_CT_WIDTH))
26563 /*@}*/
26564 
26565 /*******************************************************************************
26566  * TRNG_SEC_CFG - RNG Security Configuration Register
26567  ******************************************************************************/
26568 
26569 /*!
26570  * @brief TRNG_SEC_CFG - RNG Security Configuration Register (RW)
26571  *
26572  * Reset value: 0x00000000U
26573  *
26574  * The RNG Security Configuration Register is a read/write register used to
26575  * control the test mode, programmability and state modes of the RNG. Many bits are
26576  * place holders for this version. More configurability will be added here. Clears
26577  * on asynchronous reset. For SA-TRNG releases before 2014/July/01, offsets 0xA0
26578  * to 0xAC used to be 0xB0 to 0xBC respectively. So, update newer tests that use
26579  * these registers, if hard coded.
26580  */
26581 /*!
26582  * @name Constants and macros for entire TRNG_SEC_CFG register
26583  */
26584 /*@{*/
26585 #define TRNG_RD_SEC_CFG(base)    (TRNG_SEC_CFG_REG(base))
26586 #define TRNG_WR_SEC_CFG(base, value) (TRNG_SEC_CFG_REG(base) = (value))
26587 #define TRNG_RMW_SEC_CFG(base, mask, value) (TRNG_WR_SEC_CFG(base, (TRNG_RD_SEC_CFG(base) & ~(mask)) | (value)))
26588 #define TRNG_SET_SEC_CFG(base, value) (BME_OR32(&TRNG_SEC_CFG_REG(base), (uint32_t)(value)))
26589 #define TRNG_CLR_SEC_CFG(base, value) (BME_AND32(&TRNG_SEC_CFG_REG(base), (uint32_t)(~(value))))
26590 #define TRNG_TOG_SEC_CFG(base, value) (BME_XOR32(&TRNG_SEC_CFG_REG(base), (uint32_t)(value)))
26591 /*@}*/
26592 
26593 /*
26594  * Constants & macros for individual TRNG_SEC_CFG bitfields
26595  */
26596 
26597 /*!
26598  * @name Register TRNG_SEC_CFG, field SH0[0] (RW)
26599  *
26600  * Reserved. DRNG specific, not applicable to this version.
26601  *
26602  * Values:
26603  * - 0b0 - See DRNG version.
26604  * - 0b1 - See DRNG version.
26605  */
26606 /*@{*/
26607 /*! @brief Read current value of the TRNG_SEC_CFG_SH0 field. */
26608 #define TRNG_RD_SEC_CFG_SH0(base) ((TRNG_SEC_CFG_REG(base) & TRNG_SEC_CFG_SH0_MASK) >> TRNG_SEC_CFG_SH0_SHIFT)
26609 #define TRNG_BRD_SEC_CFG_SH0(base) (BME_UBFX32(&TRNG_SEC_CFG_REG(base), TRNG_SEC_CFG_SH0_SHIFT, TRNG_SEC_CFG_SH0_WIDTH))
26610 
26611 /*! @brief Set the SH0 field to a new value. */
26612 #define TRNG_WR_SEC_CFG_SH0(base, value) (TRNG_RMW_SEC_CFG(base, TRNG_SEC_CFG_SH0_MASK, TRNG_SEC_CFG_SH0(value)))
26613 #define TRNG_BWR_SEC_CFG_SH0(base, value) (BME_BFI32(&TRNG_SEC_CFG_REG(base), ((uint32_t)(value) << TRNG_SEC_CFG_SH0_SHIFT), TRNG_SEC_CFG_SH0_SHIFT, TRNG_SEC_CFG_SH0_WIDTH))
26614 /*@}*/
26615 
26616 /*!
26617  * @name Register TRNG_SEC_CFG, field NO_PRGM[1] (RW)
26618  *
26619  * If set the TRNG registers cannot be programmed. That is, regardless of the
26620  * TRNG access mode in the SA-TRNG Miscellaneous Control Register.
26621  *
26622  * Values:
26623  * - 0b0 - Programability of registers controlled only by the RNG Miscellaneous
26624  *     Control Register's access mode bit.
26625  * - 0b1 - Overides RNG Miscellaneous Control Register access mode and prevents
26626  *     TRNG register programming.
26627  */
26628 /*@{*/
26629 /*! @brief Read current value of the TRNG_SEC_CFG_NO_PRGM field. */
26630 #define TRNG_RD_SEC_CFG_NO_PRGM(base) ((TRNG_SEC_CFG_REG(base) & TRNG_SEC_CFG_NO_PRGM_MASK) >> TRNG_SEC_CFG_NO_PRGM_SHIFT)
26631 #define TRNG_BRD_SEC_CFG_NO_PRGM(base) (BME_UBFX32(&TRNG_SEC_CFG_REG(base), TRNG_SEC_CFG_NO_PRGM_SHIFT, TRNG_SEC_CFG_NO_PRGM_WIDTH))
26632 
26633 /*! @brief Set the NO_PRGM field to a new value. */
26634 #define TRNG_WR_SEC_CFG_NO_PRGM(base, value) (TRNG_RMW_SEC_CFG(base, TRNG_SEC_CFG_NO_PRGM_MASK, TRNG_SEC_CFG_NO_PRGM(value)))
26635 #define TRNG_BWR_SEC_CFG_NO_PRGM(base, value) (BME_BFI32(&TRNG_SEC_CFG_REG(base), ((uint32_t)(value) << TRNG_SEC_CFG_NO_PRGM_SHIFT), TRNG_SEC_CFG_NO_PRGM_SHIFT, TRNG_SEC_CFG_NO_PRGM_WIDTH))
26636 /*@}*/
26637 
26638 /*!
26639  * @name Register TRNG_SEC_CFG, field SK_VAL[2] (RW)
26640  *
26641  * Reserved. DRNG-specific, not applicable to this version.
26642  *
26643  * Values:
26644  * - 0b0 - See DRNG version.
26645  * - 0b1 - See DRNG version.
26646  */
26647 /*@{*/
26648 /*! @brief Read current value of the TRNG_SEC_CFG_SK_VAL field. */
26649 #define TRNG_RD_SEC_CFG_SK_VAL(base) ((TRNG_SEC_CFG_REG(base) & TRNG_SEC_CFG_SK_VAL_MASK) >> TRNG_SEC_CFG_SK_VAL_SHIFT)
26650 #define TRNG_BRD_SEC_CFG_SK_VAL(base) (BME_UBFX32(&TRNG_SEC_CFG_REG(base), TRNG_SEC_CFG_SK_VAL_SHIFT, TRNG_SEC_CFG_SK_VAL_WIDTH))
26651 
26652 /*! @brief Set the SK_VAL field to a new value. */
26653 #define TRNG_WR_SEC_CFG_SK_VAL(base, value) (TRNG_RMW_SEC_CFG(base, TRNG_SEC_CFG_SK_VAL_MASK, TRNG_SEC_CFG_SK_VAL(value)))
26654 #define TRNG_BWR_SEC_CFG_SK_VAL(base, value) (BME_BFI32(&TRNG_SEC_CFG_REG(base), ((uint32_t)(value) << TRNG_SEC_CFG_SK_VAL_SHIFT), TRNG_SEC_CFG_SK_VAL_SHIFT, TRNG_SEC_CFG_SK_VAL_WIDTH))
26655 /*@}*/
26656 
26657 /*******************************************************************************
26658  * TRNG_INT_CTRL - RNG Interrupt Control Register
26659  ******************************************************************************/
26660 
26661 /*!
26662  * @brief TRNG_INT_CTRL - RNG Interrupt Control Register (RW)
26663  *
26664  * Reset value: 0xFFFFFFFFU
26665  *
26666  * The RNG Interrupt Control Register is a read/write register used to control
26667  * the status for the (currently) three important interrupts that are generated by
26668  * the TRNG. See INT_STATUS register description above. Each interrupt can be
26669  * cleared by de-asserting the corresponding bit in the INT_CTRL register. Only a
26670  * new interrupt will reassert the corresponding bit in the status register. Even
26671  * if the interrupt is cleared or masked, interrupt status information can be
26672  * read from the MCTL register.
26673  */
26674 /*!
26675  * @name Constants and macros for entire TRNG_INT_CTRL register
26676  */
26677 /*@{*/
26678 #define TRNG_RD_INT_CTRL(base)   (TRNG_INT_CTRL_REG(base))
26679 #define TRNG_WR_INT_CTRL(base, value) (TRNG_INT_CTRL_REG(base) = (value))
26680 #define TRNG_RMW_INT_CTRL(base, mask, value) (TRNG_WR_INT_CTRL(base, (TRNG_RD_INT_CTRL(base) & ~(mask)) | (value)))
26681 #define TRNG_SET_INT_CTRL(base, value) (BME_OR32(&TRNG_INT_CTRL_REG(base), (uint32_t)(value)))
26682 #define TRNG_CLR_INT_CTRL(base, value) (BME_AND32(&TRNG_INT_CTRL_REG(base), (uint32_t)(~(value))))
26683 #define TRNG_TOG_INT_CTRL(base, value) (BME_XOR32(&TRNG_INT_CTRL_REG(base), (uint32_t)(value)))
26684 /*@}*/
26685 
26686 /*
26687  * Constants & macros for individual TRNG_INT_CTRL bitfields
26688  */
26689 
26690 /*!
26691  * @name Register TRNG_INT_CTRL, field HW_ERR[0] (RW)
26692  *
26693  * Bit position that can be cleared if corresponding bit of INT_STATUS has been
26694  * asserted.
26695  *
26696  * Values:
26697  * - 0b0 - Corresponding bit of INT_STATUS cleared.
26698  * - 0b1 - Corresponding bit of INT_STATUS active.
26699  */
26700 /*@{*/
26701 /*! @brief Read current value of the TRNG_INT_CTRL_HW_ERR field. */
26702 #define TRNG_RD_INT_CTRL_HW_ERR(base) ((TRNG_INT_CTRL_REG(base) & TRNG_INT_CTRL_HW_ERR_MASK) >> TRNG_INT_CTRL_HW_ERR_SHIFT)
26703 #define TRNG_BRD_INT_CTRL_HW_ERR(base) (BME_UBFX32(&TRNG_INT_CTRL_REG(base), TRNG_INT_CTRL_HW_ERR_SHIFT, TRNG_INT_CTRL_HW_ERR_WIDTH))
26704 
26705 /*! @brief Set the HW_ERR field to a new value. */
26706 #define TRNG_WR_INT_CTRL_HW_ERR(base, value) (TRNG_RMW_INT_CTRL(base, TRNG_INT_CTRL_HW_ERR_MASK, TRNG_INT_CTRL_HW_ERR(value)))
26707 #define TRNG_BWR_INT_CTRL_HW_ERR(base, value) (BME_BFI32(&TRNG_INT_CTRL_REG(base), ((uint32_t)(value) << TRNG_INT_CTRL_HW_ERR_SHIFT), TRNG_INT_CTRL_HW_ERR_SHIFT, TRNG_INT_CTRL_HW_ERR_WIDTH))
26708 /*@}*/
26709 
26710 /*!
26711  * @name Register TRNG_INT_CTRL, field ENT_VAL[1] (RW)
26712  *
26713  * Same behavior as bit 0 above.
26714  *
26715  * Values:
26716  * - 0b0 - Same behavior as bit 0 above.
26717  * - 0b1 - Same behavior as bit 0 above.
26718  */
26719 /*@{*/
26720 /*! @brief Read current value of the TRNG_INT_CTRL_ENT_VAL field. */
26721 #define TRNG_RD_INT_CTRL_ENT_VAL(base) ((TRNG_INT_CTRL_REG(base) & TRNG_INT_CTRL_ENT_VAL_MASK) >> TRNG_INT_CTRL_ENT_VAL_SHIFT)
26722 #define TRNG_BRD_INT_CTRL_ENT_VAL(base) (BME_UBFX32(&TRNG_INT_CTRL_REG(base), TRNG_INT_CTRL_ENT_VAL_SHIFT, TRNG_INT_CTRL_ENT_VAL_WIDTH))
26723 
26724 /*! @brief Set the ENT_VAL field to a new value. */
26725 #define TRNG_WR_INT_CTRL_ENT_VAL(base, value) (TRNG_RMW_INT_CTRL(base, TRNG_INT_CTRL_ENT_VAL_MASK, TRNG_INT_CTRL_ENT_VAL(value)))
26726 #define TRNG_BWR_INT_CTRL_ENT_VAL(base, value) (BME_BFI32(&TRNG_INT_CTRL_REG(base), ((uint32_t)(value) << TRNG_INT_CTRL_ENT_VAL_SHIFT), TRNG_INT_CTRL_ENT_VAL_SHIFT, TRNG_INT_CTRL_ENT_VAL_WIDTH))
26727 /*@}*/
26728 
26729 /*!
26730  * @name Register TRNG_INT_CTRL, field FRQ_CT_FAIL[2] (RW)
26731  *
26732  * Same behavior as bit 0 above.
26733  *
26734  * Values:
26735  * - 0b0 - Same behavior as bit 0 above.
26736  * - 0b1 - Same behavior as bit 0 above.
26737  */
26738 /*@{*/
26739 /*! @brief Read current value of the TRNG_INT_CTRL_FRQ_CT_FAIL field. */
26740 #define TRNG_RD_INT_CTRL_FRQ_CT_FAIL(base) ((TRNG_INT_CTRL_REG(base) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK) >> TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)
26741 #define TRNG_BRD_INT_CTRL_FRQ_CT_FAIL(base) (BME_UBFX32(&TRNG_INT_CTRL_REG(base), TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT, TRNG_INT_CTRL_FRQ_CT_FAIL_WIDTH))
26742 
26743 /*! @brief Set the FRQ_CT_FAIL field to a new value. */
26744 #define TRNG_WR_INT_CTRL_FRQ_CT_FAIL(base, value) (TRNG_RMW_INT_CTRL(base, TRNG_INT_CTRL_FRQ_CT_FAIL_MASK, TRNG_INT_CTRL_FRQ_CT_FAIL(value)))
26745 #define TRNG_BWR_INT_CTRL_FRQ_CT_FAIL(base, value) (BME_BFI32(&TRNG_INT_CTRL_REG(base), ((uint32_t)(value) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT), TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT, TRNG_INT_CTRL_FRQ_CT_FAIL_WIDTH))
26746 /*@}*/
26747 
26748 /*!
26749  * @name Register TRNG_INT_CTRL, field UNUSED[31:3] (RW)
26750  *
26751  * Reserved but writeable.
26752  */
26753 /*@{*/
26754 /*! @brief Read current value of the TRNG_INT_CTRL_UNUSED field. */
26755 #define TRNG_RD_INT_CTRL_UNUSED(base) ((TRNG_INT_CTRL_REG(base) & TRNG_INT_CTRL_UNUSED_MASK) >> TRNG_INT_CTRL_UNUSED_SHIFT)
26756 #define TRNG_BRD_INT_CTRL_UNUSED(base) (TRNG_RD_INT_CTRL_UNUSED(base))
26757 
26758 /*! @brief Set the UNUSED field to a new value. */
26759 #define TRNG_WR_INT_CTRL_UNUSED(base, value) (TRNG_RMW_INT_CTRL(base, TRNG_INT_CTRL_UNUSED_MASK, TRNG_INT_CTRL_UNUSED(value)))
26760 #define TRNG_BWR_INT_CTRL_UNUSED(base, value) (TRNG_WR_INT_CTRL_UNUSED(base, value))
26761 /*@}*/
26762 
26763 /*******************************************************************************
26764  * TRNG_INT_MASK - RNG Mask Register
26765  ******************************************************************************/
26766 
26767 /*!
26768  * @brief TRNG_INT_MASK - RNG Mask Register (RW)
26769  *
26770  * Reset value: 0x00000000U
26771  *
26772  * The RNG Interrupt Mask Register is a read/write register used to disable/mask
26773  * the status reporting of the (currently) three important interrupts that are
26774  * generated by the TRNG. See INT_STATUS register description above. Each
26775  * interrupt can be masked/disabled by de-asserting the corresponding bit in the INT_MASK
26776  * register. Only setting this bit high will re-enable the interrupt in the
26777  * status register. Even if the interrupt is cleared or masked, interrupt status
26778  * information can be read from the MCTL register.
26779  */
26780 /*!
26781  * @name Constants and macros for entire TRNG_INT_MASK register
26782  */
26783 /*@{*/
26784 #define TRNG_RD_INT_MASK(base)   (TRNG_INT_MASK_REG(base))
26785 #define TRNG_WR_INT_MASK(base, value) (TRNG_INT_MASK_REG(base) = (value))
26786 #define TRNG_RMW_INT_MASK(base, mask, value) (TRNG_WR_INT_MASK(base, (TRNG_RD_INT_MASK(base) & ~(mask)) | (value)))
26787 #define TRNG_SET_INT_MASK(base, value) (BME_OR32(&TRNG_INT_MASK_REG(base), (uint32_t)(value)))
26788 #define TRNG_CLR_INT_MASK(base, value) (BME_AND32(&TRNG_INT_MASK_REG(base), (uint32_t)(~(value))))
26789 #define TRNG_TOG_INT_MASK(base, value) (BME_XOR32(&TRNG_INT_MASK_REG(base), (uint32_t)(value)))
26790 /*@}*/
26791 
26792 /*
26793  * Constants & macros for individual TRNG_INT_MASK bitfields
26794  */
26795 
26796 /*!
26797  * @name Register TRNG_INT_MASK, field HW_ERR[0] (RW)
26798  *
26799  * Bit position that can be cleared if corresponding bit of INT_STATUS has been
26800  * asserted.
26801  *
26802  * Values:
26803  * - 0b0 - Corresponding interrupt of INT_STATUS is masked.
26804  * - 0b1 - Corresponding bit of INT_STATUS is active.
26805  */
26806 /*@{*/
26807 /*! @brief Read current value of the TRNG_INT_MASK_HW_ERR field. */
26808 #define TRNG_RD_INT_MASK_HW_ERR(base) ((TRNG_INT_MASK_REG(base) & TRNG_INT_MASK_HW_ERR_MASK) >> TRNG_INT_MASK_HW_ERR_SHIFT)
26809 #define TRNG_BRD_INT_MASK_HW_ERR(base) (BME_UBFX32(&TRNG_INT_MASK_REG(base), TRNG_INT_MASK_HW_ERR_SHIFT, TRNG_INT_MASK_HW_ERR_WIDTH))
26810 
26811 /*! @brief Set the HW_ERR field to a new value. */
26812 #define TRNG_WR_INT_MASK_HW_ERR(base, value) (TRNG_RMW_INT_MASK(base, TRNG_INT_MASK_HW_ERR_MASK, TRNG_INT_MASK_HW_ERR(value)))
26813 #define TRNG_BWR_INT_MASK_HW_ERR(base, value) (BME_BFI32(&TRNG_INT_MASK_REG(base), ((uint32_t)(value) << TRNG_INT_MASK_HW_ERR_SHIFT), TRNG_INT_MASK_HW_ERR_SHIFT, TRNG_INT_MASK_HW_ERR_WIDTH))
26814 /*@}*/
26815 
26816 /*!
26817  * @name Register TRNG_INT_MASK, field ENT_VAL[1] (RW)
26818  *
26819  * Same behavior as bit 0 above.
26820  *
26821  * Values:
26822  * - 0b0 - Same behavior as bit 0 above.
26823  * - 0b1 - Same behavior as bit 0 above.
26824  */
26825 /*@{*/
26826 /*! @brief Read current value of the TRNG_INT_MASK_ENT_VAL field. */
26827 #define TRNG_RD_INT_MASK_ENT_VAL(base) ((TRNG_INT_MASK_REG(base) & TRNG_INT_MASK_ENT_VAL_MASK) >> TRNG_INT_MASK_ENT_VAL_SHIFT)
26828 #define TRNG_BRD_INT_MASK_ENT_VAL(base) (BME_UBFX32(&TRNG_INT_MASK_REG(base), TRNG_INT_MASK_ENT_VAL_SHIFT, TRNG_INT_MASK_ENT_VAL_WIDTH))
26829 
26830 /*! @brief Set the ENT_VAL field to a new value. */
26831 #define TRNG_WR_INT_MASK_ENT_VAL(base, value) (TRNG_RMW_INT_MASK(base, TRNG_INT_MASK_ENT_VAL_MASK, TRNG_INT_MASK_ENT_VAL(value)))
26832 #define TRNG_BWR_INT_MASK_ENT_VAL(base, value) (BME_BFI32(&TRNG_INT_MASK_REG(base), ((uint32_t)(value) << TRNG_INT_MASK_ENT_VAL_SHIFT), TRNG_INT_MASK_ENT_VAL_SHIFT, TRNG_INT_MASK_ENT_VAL_WIDTH))
26833 /*@}*/
26834 
26835 /*!
26836  * @name Register TRNG_INT_MASK, field FRQ_CT_FAIL[2] (RW)
26837  *
26838  * Same behavior as bit 0 above.
26839  *
26840  * Values:
26841  * - 0b0 - Same behavior as bit 0 above.
26842  * - 0b1 - Same behavior as bit 0 above.
26843  */
26844 /*@{*/
26845 /*! @brief Read current value of the TRNG_INT_MASK_FRQ_CT_FAIL field. */
26846 #define TRNG_RD_INT_MASK_FRQ_CT_FAIL(base) ((TRNG_INT_MASK_REG(base) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK) >> TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)
26847 #define TRNG_BRD_INT_MASK_FRQ_CT_FAIL(base) (BME_UBFX32(&TRNG_INT_MASK_REG(base), TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT, TRNG_INT_MASK_FRQ_CT_FAIL_WIDTH))
26848 
26849 /*! @brief Set the FRQ_CT_FAIL field to a new value. */
26850 #define TRNG_WR_INT_MASK_FRQ_CT_FAIL(base, value) (TRNG_RMW_INT_MASK(base, TRNG_INT_MASK_FRQ_CT_FAIL_MASK, TRNG_INT_MASK_FRQ_CT_FAIL(value)))
26851 #define TRNG_BWR_INT_MASK_FRQ_CT_FAIL(base, value) (BME_BFI32(&TRNG_INT_MASK_REG(base), ((uint32_t)(value) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT), TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT, TRNG_INT_MASK_FRQ_CT_FAIL_WIDTH))
26852 /*@}*/
26853 
26854 /*******************************************************************************
26855  * TRNG_INT_STATUS - RNG Interrupt Status Register
26856  ******************************************************************************/
26857 
26858 /*!
26859  * @brief TRNG_INT_STATUS - RNG Interrupt Status Register (RW)
26860  *
26861  * Reset value: 0x00000000U
26862  *
26863  * The RNG Interrupt Status Register is a read register used to control and
26864  * provide status for the (currently) three important interrupts that are generated
26865  * by the TRNG. The ipi_rng_int_b interrupt signals that RNG has either generated
26866  * a Frequency Count Fail, Entropy Valid or Error Interrupt. The cause of the
26867  * interrupt can be decoded by checking the least significant bits of the INT_STATUS
26868  * register. Each interrupt can be temporarily cleared by de-asserting the
26869  * corresponding bit in the INT_CTRL register. To mask the interrupts, clear the
26870  * corresponding bits in the INT_MASK register. The description of each of the 3
26871  * interrupts is defined in the Block Guide under the MCTL register description. Even
26872  * if the interrupt is cleared or masked, interrupt status information can be
26873  * read from the MCTL register.
26874  */
26875 /*!
26876  * @name Constants and macros for entire TRNG_INT_STATUS register
26877  */
26878 /*@{*/
26879 #define TRNG_RD_INT_STATUS(base) (TRNG_INT_STATUS_REG(base))
26880 #define TRNG_WR_INT_STATUS(base, value) (TRNG_INT_STATUS_REG(base) = (value))
26881 #define TRNG_RMW_INT_STATUS(base, mask, value) (TRNG_WR_INT_STATUS(base, (TRNG_RD_INT_STATUS(base) & ~(mask)) | (value)))
26882 #define TRNG_SET_INT_STATUS(base, value) (BME_OR32(&TRNG_INT_STATUS_REG(base), (uint32_t)(value)))
26883 #define TRNG_CLR_INT_STATUS(base, value) (BME_AND32(&TRNG_INT_STATUS_REG(base), (uint32_t)(~(value))))
26884 #define TRNG_TOG_INT_STATUS(base, value) (BME_XOR32(&TRNG_INT_STATUS_REG(base), (uint32_t)(value)))
26885 /*@}*/
26886 
26887 /*
26888  * Constants & macros for individual TRNG_INT_STATUS bitfields
26889  */
26890 
26891 /*!
26892  * @name Register TRNG_INT_STATUS, field HW_ERR[0] (RO)
26893  *
26894  * Read: Error status. 1 = error detected. 0 = no error. Any HW error in the
26895  * TRNG will trigger this interrupt.
26896  *
26897  * Values:
26898  * - 0b0 - no error
26899  * - 0b1 - error detected.
26900  */
26901 /*@{*/
26902 /*! @brief Read current value of the TRNG_INT_STATUS_HW_ERR field. */
26903 #define TRNG_RD_INT_STATUS_HW_ERR(base) ((TRNG_INT_STATUS_REG(base) & TRNG_INT_STATUS_HW_ERR_MASK) >> TRNG_INT_STATUS_HW_ERR_SHIFT)
26904 #define TRNG_BRD_INT_STATUS_HW_ERR(base) (BME_UBFX32(&TRNG_INT_STATUS_REG(base), TRNG_INT_STATUS_HW_ERR_SHIFT, TRNG_INT_STATUS_HW_ERR_WIDTH))
26905 /*@}*/
26906 
26907 /*!
26908  * @name Register TRNG_INT_STATUS, field ENT_VAL[1] (RO)
26909  *
26910  * Read only: Entropy Valid. Will assert only if TRNG ACC bit is set, and then
26911  * after an entropy value is generated. Will be cleared when ENT15 is read. (ENT0
26912  * through ENT14 should be read before reading ENT15).
26913  *
26914  * Values:
26915  * - 0b0 - Busy generation entropy. Any value read is invalid.
26916  * - 0b1 - TRNG can be stopped and entropy is valid if read.
26917  */
26918 /*@{*/
26919 /*! @brief Read current value of the TRNG_INT_STATUS_ENT_VAL field. */
26920 #define TRNG_RD_INT_STATUS_ENT_VAL(base) ((TRNG_INT_STATUS_REG(base) & TRNG_INT_STATUS_ENT_VAL_MASK) >> TRNG_INT_STATUS_ENT_VAL_SHIFT)
26921 #define TRNG_BRD_INT_STATUS_ENT_VAL(base) (BME_UBFX32(&TRNG_INT_STATUS_REG(base), TRNG_INT_STATUS_ENT_VAL_SHIFT, TRNG_INT_STATUS_ENT_VAL_WIDTH))
26922 /*@}*/
26923 
26924 /*!
26925  * @name Register TRNG_INT_STATUS, field FRQ_CT_FAIL[2] (RW)
26926  *
26927  * Read only: Frequency Count Fail. The frequency counter has detected a
26928  * failure. This may be due to improper programming of the FRQMAX and/or FRQMIN
26929  * registers, or a hardware failure in the ring oscillator.
26930  *
26931  * Values:
26932  * - 0b0 - No hardware nor self test frequency errors.
26933  * - 0b1 - The frequency counter has detected a failure.
26934  */
26935 /*@{*/
26936 /*! @brief Read current value of the TRNG_INT_STATUS_FRQ_CT_FAIL field. */
26937 #define TRNG_RD_INT_STATUS_FRQ_CT_FAIL(base) ((TRNG_INT_STATUS_REG(base) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK) >> TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)
26938 #define TRNG_BRD_INT_STATUS_FRQ_CT_FAIL(base) (BME_UBFX32(&TRNG_INT_STATUS_REG(base), TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT, TRNG_INT_STATUS_FRQ_CT_FAIL_WIDTH))
26939 
26940 /*! @brief Set the FRQ_CT_FAIL field to a new value. */
26941 #define TRNG_WR_INT_STATUS_FRQ_CT_FAIL(base, value) (TRNG_RMW_INT_STATUS(base, TRNG_INT_STATUS_FRQ_CT_FAIL_MASK, TRNG_INT_STATUS_FRQ_CT_FAIL(value)))
26942 #define TRNG_BWR_INT_STATUS_FRQ_CT_FAIL(base, value) (BME_BFI32(&TRNG_INT_STATUS_REG(base), ((uint32_t)(value) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT), TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT, TRNG_INT_STATUS_FRQ_CT_FAIL_WIDTH))
26943 /*@}*/
26944 
26945 /*******************************************************************************
26946  * TRNG_VID1 - RNG Version ID Register (MS)
26947  ******************************************************************************/
26948 
26949 /*!
26950  * @brief TRNG_VID1 - RNG Version ID Register (MS) (RO)
26951  *
26952  * Reset value: 0x00300100U
26953  *
26954  * The RNG Version ID Register is a read only register used to identify the
26955  * version of the TRNG in use. This register as well as VID2 should both be read to
26956  * verify the expected version.
26957  */
26958 /*!
26959  * @name Constants and macros for entire TRNG_VID1 register
26960  */
26961 /*@{*/
26962 #define TRNG_RD_VID1(base)       (TRNG_VID1_REG(base))
26963 /*@}*/
26964 
26965 /*
26966  * Constants & macros for individual TRNG_VID1 bitfields
26967  */
26968 
26969 /*!
26970  * @name Register TRNG_VID1, field RNG_MIN_REV[7:0] (RO)
26971  *
26972  * Shows the Freescale IP's Minor revision of the TRNG.
26973  *
26974  * Values:
26975  * - 0b00000000 - Minor revision number for TRNG.
26976  */
26977 /*@{*/
26978 /*! @brief Read current value of the TRNG_VID1_RNG_MIN_REV field. */
26979 #define TRNG_RD_VID1_RNG_MIN_REV(base) ((TRNG_VID1_REG(base) & TRNG_VID1_RNG_MIN_REV_MASK) >> TRNG_VID1_RNG_MIN_REV_SHIFT)
26980 #define TRNG_BRD_VID1_RNG_MIN_REV(base) (BME_UBFX32(&TRNG_VID1_REG(base), TRNG_VID1_RNG_MIN_REV_SHIFT, TRNG_VID1_RNG_MIN_REV_WIDTH))
26981 /*@}*/
26982 
26983 /*!
26984  * @name Register TRNG_VID1, field RNG_MAJ_REV[15:8] (RO)
26985  *
26986  * Shows the Freescale IP's Major revision of the TRNG.
26987  *
26988  * Values:
26989  * - 0b00000001 - Major revision number for TRNG.
26990  */
26991 /*@{*/
26992 /*! @brief Read current value of the TRNG_VID1_RNG_MAJ_REV field. */
26993 #define TRNG_RD_VID1_RNG_MAJ_REV(base) ((TRNG_VID1_REG(base) & TRNG_VID1_RNG_MAJ_REV_MASK) >> TRNG_VID1_RNG_MAJ_REV_SHIFT)
26994 #define TRNG_BRD_VID1_RNG_MAJ_REV(base) (BME_UBFX32(&TRNG_VID1_REG(base), TRNG_VID1_RNG_MAJ_REV_SHIFT, TRNG_VID1_RNG_MAJ_REV_WIDTH))
26995 /*@}*/
26996 
26997 /*!
26998  * @name Register TRNG_VID1, field RNG_IP_ID[31:16] (RO)
26999  *
27000  * Shows the Freescale IP ID.
27001  */
27002 /*@{*/
27003 /*! @brief Read current value of the TRNG_VID1_RNG_IP_ID field. */
27004 #define TRNG_RD_VID1_RNG_IP_ID(base) ((TRNG_VID1_REG(base) & TRNG_VID1_RNG_IP_ID_MASK) >> TRNG_VID1_RNG_IP_ID_SHIFT)
27005 #define TRNG_BRD_VID1_RNG_IP_ID(base) (BME_UBFX32(&TRNG_VID1_REG(base), TRNG_VID1_RNG_IP_ID_SHIFT, TRNG_VID1_RNG_IP_ID_WIDTH))
27006 /*@}*/
27007 
27008 /*******************************************************************************
27009  * TRNG_VID2 - RNG Version ID Register (LS)
27010  ******************************************************************************/
27011 
27012 /*!
27013  * @brief TRNG_VID2 - RNG Version ID Register (LS) (RO)
27014  *
27015  * Reset value: 0x00000000U
27016  *
27017  * The RNG Version ID Register LSB is a read only register used to identify the
27018  * architecture of the TRNG in use. This register as well as VID1 should both be
27019  * read to verify the expected version.
27020  */
27021 /*!
27022  * @name Constants and macros for entire TRNG_VID2 register
27023  */
27024 /*@{*/
27025 #define TRNG_RD_VID2(base)       (TRNG_VID2_REG(base))
27026 /*@}*/
27027 
27028 /*
27029  * Constants & macros for individual TRNG_VID2 bitfields
27030  */
27031 
27032 /*!
27033  * @name Register TRNG_VID2, field RNG_CONFIG_OPT[7:0] (RO)
27034  *
27035  * Shows the Freescale IP's Configuaration options for the TRNG.
27036  *
27037  * Values:
27038  * - 0b00000000 - TRNG_CONFIG_OPT for TRNG.
27039  */
27040 /*@{*/
27041 /*! @brief Read current value of the TRNG_VID2_RNG_CONFIG_OPT field. */
27042 #define TRNG_RD_VID2_RNG_CONFIG_OPT(base) ((TRNG_VID2_REG(base) & TRNG_VID2_RNG_CONFIG_OPT_MASK) >> TRNG_VID2_RNG_CONFIG_OPT_SHIFT)
27043 #define TRNG_BRD_VID2_RNG_CONFIG_OPT(base) (BME_UBFX32(&TRNG_VID2_REG(base), TRNG_VID2_RNG_CONFIG_OPT_SHIFT, TRNG_VID2_RNG_CONFIG_OPT_WIDTH))
27044 /*@}*/
27045 
27046 /*!
27047  * @name Register TRNG_VID2, field RNG_ECO_REV[15:8] (RO)
27048  *
27049  * Shows the Freescale IP's ECO revision of the TRNG.
27050  *
27051  * Values:
27052  * - 0b00000000 - TRNG_ECO_REV for TRNG.
27053  */
27054 /*@{*/
27055 /*! @brief Read current value of the TRNG_VID2_RNG_ECO_REV field. */
27056 #define TRNG_RD_VID2_RNG_ECO_REV(base) ((TRNG_VID2_REG(base) & TRNG_VID2_RNG_ECO_REV_MASK) >> TRNG_VID2_RNG_ECO_REV_SHIFT)
27057 #define TRNG_BRD_VID2_RNG_ECO_REV(base) (BME_UBFX32(&TRNG_VID2_REG(base), TRNG_VID2_RNG_ECO_REV_SHIFT, TRNG_VID2_RNG_ECO_REV_WIDTH))
27058 /*@}*/
27059 
27060 /*!
27061  * @name Register TRNG_VID2, field RNG_INTG_OPT[23:16] (RO)
27062  *
27063  * Shows the Freescale integration options for the TRNG.
27064  *
27065  * Values:
27066  * - 0b00000000 - INTG_OPT for TRNG.
27067  */
27068 /*@{*/
27069 /*! @brief Read current value of the TRNG_VID2_RNG_INTG_OPT field. */
27070 #define TRNG_RD_VID2_RNG_INTG_OPT(base) ((TRNG_VID2_REG(base) & TRNG_VID2_RNG_INTG_OPT_MASK) >> TRNG_VID2_RNG_INTG_OPT_SHIFT)
27071 #define TRNG_BRD_VID2_RNG_INTG_OPT(base) (BME_UBFX32(&TRNG_VID2_REG(base), TRNG_VID2_RNG_INTG_OPT_SHIFT, TRNG_VID2_RNG_INTG_OPT_WIDTH))
27072 /*@}*/
27073 
27074 /*!
27075  * @name Register TRNG_VID2, field RNG_ERA[31:24] (RO)
27076  *
27077  * Shows the Freescale compile options for the TRNG.
27078  *
27079  * Values:
27080  * - 0b00000000 - COMPILE_OPT for TRNG.
27081  */
27082 /*@{*/
27083 /*! @brief Read current value of the TRNG_VID2_RNG_ERA field. */
27084 #define TRNG_RD_VID2_RNG_ERA(base) ((TRNG_VID2_REG(base) & TRNG_VID2_RNG_ERA_MASK) >> TRNG_VID2_RNG_ERA_SHIFT)
27085 #define TRNG_BRD_VID2_RNG_ERA(base) (BME_UBFX32(&TRNG_VID2_REG(base), TRNG_VID2_RNG_ERA_SHIFT, TRNG_VID2_RNG_ERA_WIDTH))
27086 /*@}*/
27087 
27088 /*
27089  * MKW40Z4 TSI
27090  *
27091  * Touch sense input
27092  *
27093  * Registers defined in this header file:
27094  * - TSI_GENCS - TSI General Control and Status Register
27095  * - TSI_DATA - TSI DATA Register
27096  * - TSI_TSHD - TSI Threshold Register
27097  */
27098 
27099 #define TSI_INSTANCE_COUNT (1U) /*!< Number of instances of the TSI module. */
27100 #define TSI0_IDX (0U) /*!< Instance number for TSI0. */
27101 
27102 /*******************************************************************************
27103  * TSI_GENCS - TSI General Control and Status Register
27104  ******************************************************************************/
27105 
27106 /*!
27107  * @brief TSI_GENCS - TSI General Control and Status Register (RW)
27108  *
27109  * Reset value: 0x00000000U
27110  *
27111  * This control register provides various control and configuration information
27112  * for the TSI module. When TSI is working, the configuration bits (GENCS[TSIEN],
27113  * GENCS[TSIIEN], and GENCS[STM]) must not be changed. The EOSF flag is kept
27114  * until the software acknowledge it.
27115  */
27116 /*!
27117  * @name Constants and macros for entire TSI_GENCS register
27118  */
27119 /*@{*/
27120 #define TSI_RD_GENCS(base)       (TSI_GENCS_REG(base))
27121 #define TSI_WR_GENCS(base, value) (TSI_GENCS_REG(base) = (value))
27122 #define TSI_RMW_GENCS(base, mask, value) (TSI_WR_GENCS(base, (TSI_RD_GENCS(base) & ~(mask)) | (value)))
27123 #define TSI_SET_GENCS(base, value) (BME_OR32(&TSI_GENCS_REG(base), (uint32_t)(value)))
27124 #define TSI_CLR_GENCS(base, value) (BME_AND32(&TSI_GENCS_REG(base), (uint32_t)(~(value))))
27125 #define TSI_TOG_GENCS(base, value) (BME_XOR32(&TSI_GENCS_REG(base), (uint32_t)(value)))
27126 /*@}*/
27127 
27128 /*
27129  * Constants & macros for individual TSI_GENCS bitfields
27130  */
27131 
27132 /*!
27133  * @name Register TSI_GENCS, field CURSW[1] (RW)
27134  *
27135  * This bit specifies if the current sources of electrode oscillator and
27136  * reference oscillator are swapped.
27137  *
27138  * Values:
27139  * - 0b0 - The current source pair are not swapped.
27140  * - 0b1 - The current source pair are swapped.
27141  */
27142 /*@{*/
27143 /*! @brief Read current value of the TSI_GENCS_CURSW field. */
27144 #define TSI_RD_GENCS_CURSW(base) ((TSI_GENCS_REG(base) & TSI_GENCS_CURSW_MASK) >> TSI_GENCS_CURSW_SHIFT)
27145 #define TSI_BRD_GENCS_CURSW(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_CURSW_SHIFT, TSI_GENCS_CURSW_WIDTH))
27146 
27147 /*! @brief Set the CURSW field to a new value. */
27148 #define TSI_WR_GENCS_CURSW(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_CURSW_MASK | TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK), TSI_GENCS_CURSW(value)))
27149 #define TSI_BWR_GENCS_CURSW(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_GENCS_CURSW_SHIFT), TSI_GENCS_CURSW_SHIFT, TSI_GENCS_CURSW_WIDTH))
27150 /*@}*/
27151 
27152 /*!
27153  * @name Register TSI_GENCS, field EOSF[2] (W1C)
27154  *
27155  * This flag is set when all active electrodes are finished scanning after a
27156  * scan trigger. Write "1" , when this flag is set, to clear it.
27157  *
27158  * Values:
27159  * - 0b0 - Scan not complete.
27160  * - 0b1 - Scan complete.
27161  */
27162 /*@{*/
27163 /*! @brief Read current value of the TSI_GENCS_EOSF field. */
27164 #define TSI_RD_GENCS_EOSF(base) ((TSI_GENCS_REG(base) & TSI_GENCS_EOSF_MASK) >> TSI_GENCS_EOSF_SHIFT)
27165 #define TSI_BRD_GENCS_EOSF(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_EOSF_SHIFT, TSI_GENCS_EOSF_WIDTH))
27166 
27167 /*! @brief Set the EOSF field to a new value. */
27168 #define TSI_WR_GENCS_EOSF(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK), TSI_GENCS_EOSF(value)))
27169 #define TSI_BWR_GENCS_EOSF(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_GENCS_EOSF_SHIFT), TSI_GENCS_EOSF_SHIFT, TSI_GENCS_EOSF_WIDTH))
27170 /*@}*/
27171 
27172 /*!
27173  * @name Register TSI_GENCS, field SCNIP[3] (RO)
27174  *
27175  * This read-only bit indicates if scan is in progress. This bit will get
27176  * asserted after the analog bias circuit is stable after a trigger and it changes
27177  * automatically by the TSI.
27178  *
27179  * Values:
27180  * - 0b0 - No scan in progress.
27181  * - 0b1 - Scan in progress.
27182  */
27183 /*@{*/
27184 /*! @brief Read current value of the TSI_GENCS_SCNIP field. */
27185 #define TSI_RD_GENCS_SCNIP(base) ((TSI_GENCS_REG(base) & TSI_GENCS_SCNIP_MASK) >> TSI_GENCS_SCNIP_SHIFT)
27186 #define TSI_BRD_GENCS_SCNIP(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_SCNIP_SHIFT, TSI_GENCS_SCNIP_WIDTH))
27187 /*@}*/
27188 
27189 /*!
27190  * @name Register TSI_GENCS, field STM[4] (RW)
27191  *
27192  * This bit specifies the trigger mode. User is allowed to change this bit when
27193  * TSI is not working in progress.
27194  *
27195  * Values:
27196  * - 0b0 - Software trigger scan.
27197  * - 0b1 - Hardware trigger scan.
27198  */
27199 /*@{*/
27200 /*! @brief Read current value of the TSI_GENCS_STM field. */
27201 #define TSI_RD_GENCS_STM(base) ((TSI_GENCS_REG(base) & TSI_GENCS_STM_MASK) >> TSI_GENCS_STM_SHIFT)
27202 #define TSI_BRD_GENCS_STM(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_STM_SHIFT, TSI_GENCS_STM_WIDTH))
27203 
27204 /*! @brief Set the STM field to a new value. */
27205 #define TSI_WR_GENCS_STM(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_STM_MASK | TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK), TSI_GENCS_STM(value)))
27206 #define TSI_BWR_GENCS_STM(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_GENCS_STM_SHIFT), TSI_GENCS_STM_SHIFT, TSI_GENCS_STM_WIDTH))
27207 /*@}*/
27208 
27209 /*!
27210  * @name Register TSI_GENCS, field STPE[5] (RW)
27211  *
27212  * This bit enables TSI module function in low power modes (stop, VLPS, LLS and
27213  * VLLS{3,2,1}).
27214  *
27215  * Values:
27216  * - 0b0 - TSI is disabled when MCU goes into low power mode.
27217  * - 0b1 - Allows TSI to continue running in all low power modes.
27218  */
27219 /*@{*/
27220 /*! @brief Read current value of the TSI_GENCS_STPE field. */
27221 #define TSI_RD_GENCS_STPE(base) ((TSI_GENCS_REG(base) & TSI_GENCS_STPE_MASK) >> TSI_GENCS_STPE_SHIFT)
27222 #define TSI_BRD_GENCS_STPE(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_STPE_SHIFT, TSI_GENCS_STPE_WIDTH))
27223 
27224 /*! @brief Set the STPE field to a new value. */
27225 #define TSI_WR_GENCS_STPE(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_STPE_MASK | TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK), TSI_GENCS_STPE(value)))
27226 #define TSI_BWR_GENCS_STPE(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_GENCS_STPE_SHIFT), TSI_GENCS_STPE_SHIFT, TSI_GENCS_STPE_WIDTH))
27227 /*@}*/
27228 
27229 /*!
27230  * @name Register TSI_GENCS, field TSIIEN[6] (RW)
27231  *
27232  * This bit enables TSI module interrupt request to CPU when the scan completes.
27233  * The interrupt will wake MCU from low power mode if this interrupt is enabled.
27234  *
27235  * Values:
27236  * - 0b0 - TSI interrupt is disabled.
27237  * - 0b1 - TSI interrupt is enabled.
27238  */
27239 /*@{*/
27240 /*! @brief Read current value of the TSI_GENCS_TSIIEN field. */
27241 #define TSI_RD_GENCS_TSIIEN(base) ((TSI_GENCS_REG(base) & TSI_GENCS_TSIIEN_MASK) >> TSI_GENCS_TSIIEN_SHIFT)
27242 #define TSI_BRD_GENCS_TSIIEN(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_TSIIEN_SHIFT, TSI_GENCS_TSIIEN_WIDTH))
27243 
27244 /*! @brief Set the TSIIEN field to a new value. */
27245 #define TSI_WR_GENCS_TSIIEN(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_TSIIEN_MASK | TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK), TSI_GENCS_TSIIEN(value)))
27246 #define TSI_BWR_GENCS_TSIIEN(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_GENCS_TSIIEN_SHIFT), TSI_GENCS_TSIIEN_SHIFT, TSI_GENCS_TSIIEN_WIDTH))
27247 /*@}*/
27248 
27249 /*!
27250  * @name Register TSI_GENCS, field TSIEN[7] (RW)
27251  *
27252  * This bit enables TSI module.
27253  *
27254  * Values:
27255  * - 0b0 - TSI module disabled.
27256  * - 0b1 - TSI module enabled.
27257  */
27258 /*@{*/
27259 /*! @brief Read current value of the TSI_GENCS_TSIEN field. */
27260 #define TSI_RD_GENCS_TSIEN(base) ((TSI_GENCS_REG(base) & TSI_GENCS_TSIEN_MASK) >> TSI_GENCS_TSIEN_SHIFT)
27261 #define TSI_BRD_GENCS_TSIEN(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_TSIEN_SHIFT, TSI_GENCS_TSIEN_WIDTH))
27262 
27263 /*! @brief Set the TSIEN field to a new value. */
27264 #define TSI_WR_GENCS_TSIEN(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_TSIEN_MASK | TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK), TSI_GENCS_TSIEN(value)))
27265 #define TSI_BWR_GENCS_TSIEN(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_GENCS_TSIEN_SHIFT), TSI_GENCS_TSIEN_SHIFT, TSI_GENCS_TSIEN_WIDTH))
27266 /*@}*/
27267 
27268 /*!
27269  * @name Register TSI_GENCS, field NSCN[12:8] (RW)
27270  *
27271  * These bits indicate the scan number for each electrode. The scan number is
27272  * equal to NSCN + 1, which allows the scan time ranges from 1 to 32. By default,
27273  * NSCN is configured as 0, which asserts the TSI scans once on the selected
27274  * eletrode channel.
27275  *
27276  * Values:
27277  * - 0b00000 - Once per electrode
27278  * - 0b00001 - Twice per electrode
27279  * - 0b00010 - 3 times per electrode
27280  * - 0b00011 - 4 times per electrode
27281  * - 0b00100 - 5 times per electrode
27282  * - 0b00101 - 6 times per electrode
27283  * - 0b00110 - 7 times per electrode
27284  * - 0b00111 - 8 times per electrode
27285  * - 0b01000 - 9 times per electrode
27286  * - 0b01001 - 10 times per electrode
27287  * - 0b01010 - 11 times per electrode
27288  * - 0b01011 - 12 times per electrode
27289  * - 0b01100 - 13 times per electrode
27290  * - 0b01101 - 14 times per electrode
27291  * - 0b01110 - 15 times per electrode
27292  * - 0b01111 - 16 times per electrode
27293  * - 0b10000 - 17 times per electrode
27294  * - 0b10001 - 18 times per electrode
27295  * - 0b10010 - 19 times per electrode
27296  * - 0b10011 - 20 times per electrode
27297  * - 0b10100 - 21 times per electrode
27298  * - 0b10101 - 22 times per electrode
27299  * - 0b10110 - 23 times per electrode
27300  * - 0b10111 - 24 times per electrode
27301  * - 0b11000 - 25 times per electrode
27302  * - 0b11001 - 26 times per electrode
27303  * - 0b11010 - 27 times per electrode
27304  * - 0b11011 - 28 times per electrode
27305  * - 0b11100 - 29 times per electrode
27306  * - 0b11101 - 30 times per electrode
27307  * - 0b11110 - 31 times per electrode
27308  * - 0b11111 - 32 times per electrode
27309  */
27310 /*@{*/
27311 /*! @brief Read current value of the TSI_GENCS_NSCN field. */
27312 #define TSI_RD_GENCS_NSCN(base) ((TSI_GENCS_REG(base) & TSI_GENCS_NSCN_MASK) >> TSI_GENCS_NSCN_SHIFT)
27313 #define TSI_BRD_GENCS_NSCN(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_NSCN_SHIFT, TSI_GENCS_NSCN_WIDTH))
27314 
27315 /*! @brief Set the NSCN field to a new value. */
27316 #define TSI_WR_GENCS_NSCN(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_NSCN_MASK | TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK), TSI_GENCS_NSCN(value)))
27317 #define TSI_BWR_GENCS_NSCN(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_GENCS_NSCN_SHIFT), TSI_GENCS_NSCN_SHIFT, TSI_GENCS_NSCN_WIDTH))
27318 /*@}*/
27319 
27320 /*!
27321  * @name Register TSI_GENCS, field PS[15:13] (RW)
27322  *
27323  * These bits indicate the prescaler of the output of electrode oscillator.
27324  *
27325  * Values:
27326  * - 0b000 - Electrode Oscillator Frequency divided by 1
27327  * - 0b001 - Electrode Oscillator Frequency divided by 2
27328  * - 0b010 - Electrode Oscillator Frequency divided by 4
27329  * - 0b011 - Electrode Oscillator Frequency divided by 8
27330  * - 0b100 - Electrode Oscillator Frequency divided by 16
27331  * - 0b101 - Electrode Oscillator Frequency divided by 32
27332  * - 0b110 - Electrode Oscillator Frequency divided by 64
27333  * - 0b111 - Electrode Oscillator Frequency divided by 128
27334  */
27335 /*@{*/
27336 /*! @brief Read current value of the TSI_GENCS_PS field. */
27337 #define TSI_RD_GENCS_PS(base) ((TSI_GENCS_REG(base) & TSI_GENCS_PS_MASK) >> TSI_GENCS_PS_SHIFT)
27338 #define TSI_BRD_GENCS_PS(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_PS_SHIFT, TSI_GENCS_PS_WIDTH))
27339 
27340 /*! @brief Set the PS field to a new value. */
27341 #define TSI_WR_GENCS_PS(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_PS_MASK | TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK), TSI_GENCS_PS(value)))
27342 #define TSI_BWR_GENCS_PS(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_GENCS_PS_SHIFT), TSI_GENCS_PS_SHIFT, TSI_GENCS_PS_WIDTH))
27343 /*@}*/
27344 
27345 /*!
27346  * @name Register TSI_GENCS, field EXTCHRG[18:16] (RW)
27347  *
27348  * These bits indicate the electrode oscillator charge and discharge current
27349  * value.
27350  *
27351  * Values:
27352  * - 0b000 - 500 nA.
27353  * - 0b001 - 1 uA.
27354  * - 0b010 - 2 uA.
27355  * - 0b011 - 4 uA.
27356  * - 0b100 - 8 uA.
27357  * - 0b101 - 16 uA.
27358  * - 0b110 - 32 uA.
27359  * - 0b111 - 64 uA.
27360  */
27361 /*@{*/
27362 /*! @brief Read current value of the TSI_GENCS_EXTCHRG field. */
27363 #define TSI_RD_GENCS_EXTCHRG(base) ((TSI_GENCS_REG(base) & TSI_GENCS_EXTCHRG_MASK) >> TSI_GENCS_EXTCHRG_SHIFT)
27364 #define TSI_BRD_GENCS_EXTCHRG(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_EXTCHRG_SHIFT, TSI_GENCS_EXTCHRG_WIDTH))
27365 
27366 /*! @brief Set the EXTCHRG field to a new value. */
27367 #define TSI_WR_GENCS_EXTCHRG(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_EXTCHRG_MASK | TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK), TSI_GENCS_EXTCHRG(value)))
27368 #define TSI_BWR_GENCS_EXTCHRG(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_GENCS_EXTCHRG_SHIFT), TSI_GENCS_EXTCHRG_SHIFT, TSI_GENCS_EXTCHRG_WIDTH))
27369 /*@}*/
27370 
27371 /*!
27372  * @name Register TSI_GENCS, field DVOLT[20:19] (RW)
27373  *
27374  * These bits indicate the oscillator's voltage rails as below.
27375  *
27376  * Values:
27377  * - 0b00 - DV = 1.026 V; VP = 1.328 V; Vm = 0.302 V.
27378  * - 0b01 - DV = 0.592 V; VP = 1.111 V; Vm = 0.519 V.
27379  * - 0b10 - DV = 0.342 V; VP = 0.986 V; Vm = 0.644 V.
27380  * - 0b11 - DV = 0.197 V; VP = 0.914 V; Vm = 0.716 V.
27381  */
27382 /*@{*/
27383 /*! @brief Read current value of the TSI_GENCS_DVOLT field. */
27384 #define TSI_RD_GENCS_DVOLT(base) ((TSI_GENCS_REG(base) & TSI_GENCS_DVOLT_MASK) >> TSI_GENCS_DVOLT_SHIFT)
27385 #define TSI_BRD_GENCS_DVOLT(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_DVOLT_SHIFT, TSI_GENCS_DVOLT_WIDTH))
27386 
27387 /*! @brief Set the DVOLT field to a new value. */
27388 #define TSI_WR_GENCS_DVOLT(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_DVOLT_MASK | TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK), TSI_GENCS_DVOLT(value)))
27389 #define TSI_BWR_GENCS_DVOLT(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_GENCS_DVOLT_SHIFT), TSI_GENCS_DVOLT_SHIFT, TSI_GENCS_DVOLT_WIDTH))
27390 /*@}*/
27391 
27392 /*!
27393  * @name Register TSI_GENCS, field REFCHRG[23:21] (RW)
27394  *
27395  * These bits indicate the reference oscillator charge and discharge current
27396  * value.
27397  *
27398  * Values:
27399  * - 0b000 - 500 nA.
27400  * - 0b001 - 1 uA.
27401  * - 0b010 - 2 uA.
27402  * - 0b011 - 4 uA.
27403  * - 0b100 - 8 uA.
27404  * - 0b101 - 16 uA.
27405  * - 0b110 - 32 uA.
27406  * - 0b111 - 64 uA.
27407  */
27408 /*@{*/
27409 /*! @brief Read current value of the TSI_GENCS_REFCHRG field. */
27410 #define TSI_RD_GENCS_REFCHRG(base) ((TSI_GENCS_REG(base) & TSI_GENCS_REFCHRG_MASK) >> TSI_GENCS_REFCHRG_SHIFT)
27411 #define TSI_BRD_GENCS_REFCHRG(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_REFCHRG_SHIFT, TSI_GENCS_REFCHRG_WIDTH))
27412 
27413 /*! @brief Set the REFCHRG field to a new value. */
27414 #define TSI_WR_GENCS_REFCHRG(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_REFCHRG_MASK | TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK), TSI_GENCS_REFCHRG(value)))
27415 #define TSI_BWR_GENCS_REFCHRG(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_GENCS_REFCHRG_SHIFT), TSI_GENCS_REFCHRG_SHIFT, TSI_GENCS_REFCHRG_WIDTH))
27416 /*@}*/
27417 
27418 /*!
27419  * @name Register TSI_GENCS, field MODE[27:24] (RW)
27420  *
27421  * Set up TSI analog modes, especially, setting MODE[3:2] to not 2'b00 will
27422  * configure TSI to noise detection modes. MODE[1:0] take no effect on TSI operation
27423  * mode and should always write to 2'b00 for setting up. When reading this field
27424  * will return the analog status. Refer to chapter "Noise detection mode" for
27425  * details.
27426  *
27427  * Values:
27428  * - 0b0000 - Set TSI in capacitive sensing(non-noise detection) mode.
27429  * - 0b0100 - Set TSI analog to work in single threshold noise detection mode
27430  *     and the frequency limitation circuit is disabled.
27431  * - 0b1000 - Set TSI analog to work in single threshold noise detection mode
27432  *     and the frequency limitation circuit is enabled to work in higher
27433  *     frequencies operations.
27434  * - 0b1100 - Set TSI analog to work in automatic noise detection mode.
27435  */
27436 /*@{*/
27437 /*! @brief Read current value of the TSI_GENCS_MODE field. */
27438 #define TSI_RD_GENCS_MODE(base) ((TSI_GENCS_REG(base) & TSI_GENCS_MODE_MASK) >> TSI_GENCS_MODE_SHIFT)
27439 #define TSI_BRD_GENCS_MODE(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_MODE_SHIFT, TSI_GENCS_MODE_WIDTH))
27440 
27441 /*! @brief Set the MODE field to a new value. */
27442 #define TSI_WR_GENCS_MODE(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_MODE_MASK | TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK), TSI_GENCS_MODE(value)))
27443 #define TSI_BWR_GENCS_MODE(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_GENCS_MODE_SHIFT), TSI_GENCS_MODE_SHIFT, TSI_GENCS_MODE_WIDTH))
27444 /*@}*/
27445 
27446 /*!
27447  * @name Register TSI_GENCS, field ESOR[28] (RW)
27448  *
27449  * This bit is used to select out-of-range or end-of-scan event to generate an
27450  * interrupt.
27451  *
27452  * Values:
27453  * - 0b0 - Out-of-range interrupt is allowed.
27454  * - 0b1 - End-of-scan interrupt is allowed.
27455  */
27456 /*@{*/
27457 /*! @brief Read current value of the TSI_GENCS_ESOR field. */
27458 #define TSI_RD_GENCS_ESOR(base) ((TSI_GENCS_REG(base) & TSI_GENCS_ESOR_MASK) >> TSI_GENCS_ESOR_SHIFT)
27459 #define TSI_BRD_GENCS_ESOR(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_ESOR_SHIFT, TSI_GENCS_ESOR_WIDTH))
27460 
27461 /*! @brief Set the ESOR field to a new value. */
27462 #define TSI_WR_GENCS_ESOR(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_ESOR_MASK | TSI_GENCS_EOSF_MASK | TSI_GENCS_OUTRGF_MASK), TSI_GENCS_ESOR(value)))
27463 #define TSI_BWR_GENCS_ESOR(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_GENCS_ESOR_SHIFT), TSI_GENCS_ESOR_SHIFT, TSI_GENCS_ESOR_WIDTH))
27464 /*@}*/
27465 
27466 /*!
27467  * @name Register TSI_GENCS, field OUTRGF[31] (W1C)
27468  *
27469  * This flag is set if the result register of the enabled electrode is out of
27470  * the range defined by the TSI_THRESHOLD register. This flag is set only when TSI
27471  * is configured in non-noise detection mode. It can be read once the CPU wakes.
27472  * Write "1" , when this flag is set, to clear it.
27473  */
27474 /*@{*/
27475 /*! @brief Read current value of the TSI_GENCS_OUTRGF field. */
27476 #define TSI_RD_GENCS_OUTRGF(base) ((TSI_GENCS_REG(base) & TSI_GENCS_OUTRGF_MASK) >> TSI_GENCS_OUTRGF_SHIFT)
27477 #define TSI_BRD_GENCS_OUTRGF(base) (BME_UBFX32(&TSI_GENCS_REG(base), TSI_GENCS_OUTRGF_SHIFT, TSI_GENCS_OUTRGF_WIDTH))
27478 
27479 /*! @brief Set the OUTRGF field to a new value. */
27480 #define TSI_WR_GENCS_OUTRGF(base, value) (TSI_RMW_GENCS(base, (TSI_GENCS_OUTRGF_MASK | TSI_GENCS_EOSF_MASK), TSI_GENCS_OUTRGF(value)))
27481 #define TSI_BWR_GENCS_OUTRGF(base, value) (BME_BFI32(&TSI_GENCS_REG(base), ((uint32_t)(value) << TSI_GENCS_OUTRGF_SHIFT), TSI_GENCS_OUTRGF_SHIFT, TSI_GENCS_OUTRGF_WIDTH))
27482 /*@}*/
27483 
27484 /*******************************************************************************
27485  * TSI_DATA - TSI DATA Register
27486  ******************************************************************************/
27487 
27488 /*!
27489  * @brief TSI_DATA - TSI DATA Register (RW)
27490  *
27491  * Reset value: 0x00000000U
27492  */
27493 /*!
27494  * @name Constants and macros for entire TSI_DATA register
27495  */
27496 /*@{*/
27497 #define TSI_RD_DATA(base)        (TSI_DATA_REG(base))
27498 #define TSI_WR_DATA(base, value) (TSI_DATA_REG(base) = (value))
27499 #define TSI_RMW_DATA(base, mask, value) (TSI_WR_DATA(base, (TSI_RD_DATA(base) & ~(mask)) | (value)))
27500 #define TSI_SET_DATA(base, value) (BME_OR32(&TSI_DATA_REG(base), (uint32_t)(value)))
27501 #define TSI_CLR_DATA(base, value) (BME_AND32(&TSI_DATA_REG(base), (uint32_t)(~(value))))
27502 #define TSI_TOG_DATA(base, value) (BME_XOR32(&TSI_DATA_REG(base), (uint32_t)(value)))
27503 /*@}*/
27504 
27505 /*
27506  * Constants & macros for individual TSI_DATA bitfields
27507  */
27508 
27509 /*!
27510  * @name Register TSI_DATA, field TSICNT[15:0] (RO)
27511  *
27512  * These read-only bits record the accumulated scan counter value ticked by the
27513  * reference oscillator.
27514  */
27515 /*@{*/
27516 /*! @brief Read current value of the TSI_DATA_TSICNT field. */
27517 #define TSI_RD_DATA_TSICNT(base) ((TSI_DATA_REG(base) & TSI_DATA_TSICNT_MASK) >> TSI_DATA_TSICNT_SHIFT)
27518 #define TSI_BRD_DATA_TSICNT(base) (BME_UBFX32(&TSI_DATA_REG(base), TSI_DATA_TSICNT_SHIFT, TSI_DATA_TSICNT_WIDTH))
27519 /*@}*/
27520 
27521 /*!
27522  * @name Register TSI_DATA, field SWTS[22] (WORZ)
27523  *
27524  * This write-only bit is a software start trigger. When STM bit is clear, write
27525  * "1" to this bit will start a scan. The electrode channel to be scanned is
27526  * determinated by TSI_DATA[TSICH] bits.
27527  *
27528  * Values:
27529  * - 0b0 - No effect.
27530  * - 0b1 - Start a scan to determine which channel is specified by
27531  *     TSI_DATA[TSICH].
27532  */
27533 /*@{*/
27534 /*! @brief Set the SWTS field to a new value. */
27535 #define TSI_WR_DATA_SWTS(base, value) (TSI_RMW_DATA(base, TSI_DATA_SWTS_MASK, TSI_DATA_SWTS(value)))
27536 #define TSI_BWR_DATA_SWTS(base, value) (BME_BFI32(&TSI_DATA_REG(base), ((uint32_t)(value) << TSI_DATA_SWTS_SHIFT), TSI_DATA_SWTS_SHIFT, TSI_DATA_SWTS_WIDTH))
27537 /*@}*/
27538 
27539 /*!
27540  * @name Register TSI_DATA, field DMAEN[23] (RW)
27541  *
27542  * This bit is used together with the TSI interrupt enable bits(TSIIE, ESOR) to
27543  * generate a DMA transfer request instead of an interrupt.
27544  *
27545  * Values:
27546  * - 0b0 - Interrupt is selected when the interrupt enable bit is set and the
27547  *     corresponding TSI events assert.
27548  * - 0b1 - DMA transfer request is selected when the interrupt enable bit is set
27549  *     and the corresponding TSI events assert.
27550  */
27551 /*@{*/
27552 /*! @brief Read current value of the TSI_DATA_DMAEN field. */
27553 #define TSI_RD_DATA_DMAEN(base) ((TSI_DATA_REG(base) & TSI_DATA_DMAEN_MASK) >> TSI_DATA_DMAEN_SHIFT)
27554 #define TSI_BRD_DATA_DMAEN(base) (BME_UBFX32(&TSI_DATA_REG(base), TSI_DATA_DMAEN_SHIFT, TSI_DATA_DMAEN_WIDTH))
27555 
27556 /*! @brief Set the DMAEN field to a new value. */
27557 #define TSI_WR_DATA_DMAEN(base, value) (TSI_RMW_DATA(base, TSI_DATA_DMAEN_MASK, TSI_DATA_DMAEN(value)))
27558 #define TSI_BWR_DATA_DMAEN(base, value) (BME_BFI32(&TSI_DATA_REG(base), ((uint32_t)(value) << TSI_DATA_DMAEN_SHIFT), TSI_DATA_DMAEN_SHIFT, TSI_DATA_DMAEN_WIDTH))
27559 /*@}*/
27560 
27561 /*!
27562  * @name Register TSI_DATA, field TSICH[31:28] (RW)
27563  *
27564  * These bits specify current channel to be measured. In hardware trigger mode
27565  * (TSI_GENCS[STM] = 1), the scan will not start until the hardware trigger
27566  * occurs. In software trigger mode (TSI_GENCS[STM] = 0), the scan starts immediately
27567  * when TSI_DATA[SWTS] bit is written by 1.
27568  *
27569  * Values:
27570  * - 0b0000 - Channel 0.
27571  * - 0b0001 - Channel 1.
27572  * - 0b0010 - Channel 2.
27573  * - 0b0011 - Channel 3.
27574  * - 0b0100 - Channel 4.
27575  * - 0b0101 - Channel 5.
27576  * - 0b0110 - Channel 6.
27577  * - 0b0111 - Channel 7.
27578  * - 0b1000 - Channel 8.
27579  * - 0b1001 - Channel 9.
27580  * - 0b1010 - Channel 10.
27581  * - 0b1011 - Channel 11.
27582  * - 0b1100 - Channel 12.
27583  * - 0b1101 - Channel 13.
27584  * - 0b1110 - Channel 14.
27585  * - 0b1111 - Channel 15.
27586  */
27587 /*@{*/
27588 /*! @brief Read current value of the TSI_DATA_TSICH field. */
27589 #define TSI_RD_DATA_TSICH(base) ((TSI_DATA_REG(base) & TSI_DATA_TSICH_MASK) >> TSI_DATA_TSICH_SHIFT)
27590 #define TSI_BRD_DATA_TSICH(base) (BME_UBFX32(&TSI_DATA_REG(base), TSI_DATA_TSICH_SHIFT, TSI_DATA_TSICH_WIDTH))
27591 
27592 /*! @brief Set the TSICH field to a new value. */
27593 #define TSI_WR_DATA_TSICH(base, value) (TSI_RMW_DATA(base, TSI_DATA_TSICH_MASK, TSI_DATA_TSICH(value)))
27594 #define TSI_BWR_DATA_TSICH(base, value) (BME_BFI32(&TSI_DATA_REG(base), ((uint32_t)(value) << TSI_DATA_TSICH_SHIFT), TSI_DATA_TSICH_SHIFT, TSI_DATA_TSICH_WIDTH))
27595 /*@}*/
27596 
27597 /*******************************************************************************
27598  * TSI_TSHD - TSI Threshold Register
27599  ******************************************************************************/
27600 
27601 /*!
27602  * @brief TSI_TSHD - TSI Threshold Register (RW)
27603  *
27604  * Reset value: 0x00000000U
27605  */
27606 /*!
27607  * @name Constants and macros for entire TSI_TSHD register
27608  */
27609 /*@{*/
27610 #define TSI_RD_TSHD(base)        (TSI_TSHD_REG(base))
27611 #define TSI_WR_TSHD(base, value) (TSI_TSHD_REG(base) = (value))
27612 #define TSI_RMW_TSHD(base, mask, value) (TSI_WR_TSHD(base, (TSI_RD_TSHD(base) & ~(mask)) | (value)))
27613 #define TSI_SET_TSHD(base, value) (BME_OR32(&TSI_TSHD_REG(base), (uint32_t)(value)))
27614 #define TSI_CLR_TSHD(base, value) (BME_AND32(&TSI_TSHD_REG(base), (uint32_t)(~(value))))
27615 #define TSI_TOG_TSHD(base, value) (BME_XOR32(&TSI_TSHD_REG(base), (uint32_t)(value)))
27616 /*@}*/
27617 
27618 /*
27619  * Constants & macros for individual TSI_TSHD bitfields
27620  */
27621 
27622 /*!
27623  * @name Register TSI_TSHD, field THRESL[15:0] (RW)
27624  *
27625  * This half-word specifies the low threshold of the wakeup channel.
27626  */
27627 /*@{*/
27628 /*! @brief Read current value of the TSI_TSHD_THRESL field. */
27629 #define TSI_RD_TSHD_THRESL(base) ((TSI_TSHD_REG(base) & TSI_TSHD_THRESL_MASK) >> TSI_TSHD_THRESL_SHIFT)
27630 #define TSI_BRD_TSHD_THRESL(base) (BME_UBFX32(&TSI_TSHD_REG(base), TSI_TSHD_THRESL_SHIFT, TSI_TSHD_THRESL_WIDTH))
27631 
27632 /*! @brief Set the THRESL field to a new value. */
27633 #define TSI_WR_TSHD_THRESL(base, value) (TSI_RMW_TSHD(base, TSI_TSHD_THRESL_MASK, TSI_TSHD_THRESL(value)))
27634 #define TSI_BWR_TSHD_THRESL(base, value) (BME_BFI32(&TSI_TSHD_REG(base), ((uint32_t)(value) << TSI_TSHD_THRESL_SHIFT), TSI_TSHD_THRESL_SHIFT, TSI_TSHD_THRESL_WIDTH))
27635 /*@}*/
27636 
27637 /*!
27638  * @name Register TSI_TSHD, field THRESH[31:16] (RW)
27639  *
27640  * This half-word specifies the high threshold of the wakeup channel.
27641  */
27642 /*@{*/
27643 /*! @brief Read current value of the TSI_TSHD_THRESH field. */
27644 #define TSI_RD_TSHD_THRESH(base) ((TSI_TSHD_REG(base) & TSI_TSHD_THRESH_MASK) >> TSI_TSHD_THRESH_SHIFT)
27645 #define TSI_BRD_TSHD_THRESH(base) (BME_UBFX32(&TSI_TSHD_REG(base), TSI_TSHD_THRESH_SHIFT, TSI_TSHD_THRESH_WIDTH))
27646 
27647 /*! @brief Set the THRESH field to a new value. */
27648 #define TSI_WR_TSHD_THRESH(base, value) (TSI_RMW_TSHD(base, TSI_TSHD_THRESH_MASK, TSI_TSHD_THRESH(value)))
27649 #define TSI_BWR_TSHD_THRESH(base, value) (BME_BFI32(&TSI_TSHD_REG(base), ((uint32_t)(value) << TSI_TSHD_THRESH_SHIFT), TSI_TSHD_THRESH_SHIFT, TSI_TSHD_THRESH_WIDTH))
27650 /*@}*/
27651 
27652 /*
27653  * MKW40Z4 XCVR
27654  *
27655  * Apache 1.0 Transceiver
27656  *
27657  * Registers defined in this header file:
27658  * - XCVR_RX_DIG_CTRL - RX Digital Control
27659  * - XCVR_AGC_CTRL_0 - AGC Control 0
27660  * - XCVR_AGC_CTRL_1 - AGC Control 1
27661  * - XCVR_AGC_CTRL_2 - AGC Control 2
27662  * - XCVR_AGC_CTRL_3 - AGC Control 3
27663  * - XCVR_AGC_STAT - AGC Status
27664  * - XCVR_RSSI_CTRL_0 - RSSI Control 0
27665  * - XCVR_RSSI_CTRL_1 - RSSI Control 1
27666  * - XCVR_DCOC_CTRL_0 - DCOC Control 0
27667  * - XCVR_DCOC_CTRL_1 - DCOC Control 1
27668  * - XCVR_DCOC_CTRL_2 - DCOC Control 2
27669  * - XCVR_DCOC_CTRL_3 - DCOC Control 3
27670  * - XCVR_DCOC_CTRL_4 - DCOC Control 4
27671  * - XCVR_DCOC_CAL_GAIN - DCOC Calibration Gain
27672  * - XCVR_DCOC_STAT - DCOC Status
27673  * - XCVR_DCOC_DC_EST - DCOC DC Estimate
27674  * - XCVR_DCOC_CAL_RCP - DCOC Calibration Reciprocals
27675  * - XCVR_IQMC_CTRL - IQMC Control
27676  * - XCVR_IQMC_CAL - IQMC Calibration
27677  * - XCVR_TCA_AGC_VAL_3_0 - TCA AGC Step Values 3..0
27678  * - XCVR_TCA_AGC_VAL_7_4 - TCA AGC Step Values 7..4
27679  * - XCVR_TCA_AGC_VAL_8 - TCA AGC Step Values 8
27680  * - XCVR_BBF_RES_TUNE_VAL_7_0 - BBF Resistor Tune Values 7..0
27681  * - XCVR_BBF_RES_TUNE_VAL_10_8 - BBF Resistor Tune Values 10..8
27682  * - XCVR_TCA_AGC_LIN_VAL_2_0 - TCA AGC Linear Gain Values 2..0
27683  * - XCVR_TCA_AGC_LIN_VAL_5_3 - TCA AGC Linear Gain Values 5..3
27684  * - XCVR_TCA_AGC_LIN_VAL_8_6 - TCA AGC Linear Gain Values 8..6
27685  * - XCVR_BBF_RES_TUNE_LIN_VAL_3_0 - BBF Resistor Tune Values 3..0
27686  * - XCVR_BBF_RES_TUNE_LIN_VAL_7_4 - BBF Resistor Tune Values 7..4
27687  * - XCVR_BBF_RES_TUNE_LIN_VAL_10_8 - BBF Resistor Tune Values 10..8
27688  * - XCVR_AGC_GAIN_TBL_03_00 - AGC Gain Tables Step 03..00
27689  * - XCVR_AGC_GAIN_TBL_07_04 - AGC Gain Tables Step 07..04
27690  * - XCVR_AGC_GAIN_TBL_11_08 - AGC Gain Tables Step 11..08
27691  * - XCVR_AGC_GAIN_TBL_15_12 - AGC Gain Tables Step 15..12
27692  * - XCVR_AGC_GAIN_TBL_19_16 - AGC Gain Tables Step 19..16
27693  * - XCVR_AGC_GAIN_TBL_23_20 - AGC Gain Tables Step 23..20
27694  * - XCVR_AGC_GAIN_TBL_26_24 - AGC Gain Tables Step 26..24
27695  * - XCVR_DCOC_OFFSET_ - DCOC Offset
27696  * - XCVR_DCOC_TZA_STEP_ - DCOC TZA DC step
27697  * - XCVR_DCOC_CAL_ALPHA - DCOC Calibration Alpha
27698  * - XCVR_DCOC_CAL_BETA - DCOC Calibration Beta
27699  * - XCVR_DCOC_CAL_GAMMA - DCOC Calibration Gamma
27700  * - XCVR_DCOC_CAL_IIR - DCOC Calibration IIR
27701  * - XCVR_DCOC_CAL - DCOC Calibration Result
27702  * - XCVR_RX_CHF_COEF - Receive Channel Filter Coefficient
27703  * - XCVR_TX_DIG_CTRL - TX Digital Control
27704  * - XCVR_TX_DATA_PAD_PAT - TX Data Padding Pattern
27705  * - XCVR_TX_GFSK_MOD_CTRL - TX GFSK Modulation Control
27706  * - XCVR_TX_GFSK_COEFF2 - TX GFSK Filter Coefficients 2
27707  * - XCVR_TX_GFSK_COEFF1 - TX GFSK Filter Coefficients 1
27708  * - XCVR_TX_FSK_MOD_SCALE - TX FSK Modulation Scale
27709  * - XCVR_TX_DFT_MOD_PAT - TX DFT Modulation Pattern
27710  * - XCVR_TX_DFT_TONE_0_1 - TX DFT Tones 0 and 1
27711  * - XCVR_TX_DFT_TONE_2_3 - TX DFT Tones 2 and 3
27712  * - XCVR_PLL_MOD_OVRD - PLL Modulation Overrides
27713  * - XCVR_PLL_CHAN_MAP - PLL Channel Mapping
27714  * - XCVR_PLL_LOCK_DETECT - PLL Lock Detect
27715  * - XCVR_PLL_HP_MOD_CTRL - PLL High Port Modulation Control
27716  * - XCVR_PLL_HPM_CAL_CTRL - PLL HPM Calibration Control
27717  * - XCVR_PLL_LD_HPM_CAL1 - PLL Cycle Slip Lock Detect Configuration and HPM Calibration 1
27718  * - XCVR_PLL_LD_HPM_CAL2 - PLL Cycle Slip Lock Detect Configuration and HPM Calibration 2
27719  * - XCVR_PLL_HPM_SDM_FRACTION - PLL HPM SDM Fraction
27720  * - XCVR_PLL_LP_MOD_CTRL - PLL Low Port Modulation Control
27721  * - XCVR_PLL_LP_SDM_CTRL1 - PLL Low Port SDM Control 1
27722  * - XCVR_PLL_LP_SDM_CTRL2 - PLL Low Port SDM Control 2
27723  * - XCVR_PLL_LP_SDM_CTRL3 - PLL Low Port SDM Control 3
27724  * - XCVR_PLL_LP_SDM_NUM - PLL Low Port SDM Numerator Applied
27725  * - XCVR_PLL_LP_SDM_DENOM - PLL Low Port SDM Denominator Applied
27726  * - XCVR_PLL_DELAY_MATCH - PLL Delay Matching
27727  * - XCVR_PLL_CTUNE_CTRL - PLL Coarse Tune Control
27728  * - XCVR_PLL_CTUNE_CNT6 - PLL Coarse Tune Count 6
27729  * - XCVR_PLL_CTUNE_CNT5_4 - PLL Coarse Tune Counts 5 and 4
27730  * - XCVR_PLL_CTUNE_CNT3_2 - PLL Coarse Tune Counts 3 and 2
27731  * - XCVR_PLL_CTUNE_CNT1_0 - PLL Coarse Tune Counts 1 and 0
27732  * - XCVR_PLL_CTUNE_RESULTS - PLL Coarse Tune Results
27733  * - XCVR_CTRL - Transceiver Control
27734  * - XCVR_STATUS - Transceiver Status
27735  * - XCVR_SOFT_RESET - Soft Reset
27736  * - XCVR_OVERWRITE_VER - Overwrite Version
27737  * - XCVR_DMA_CTRL - DMA Control
27738  * - XCVR_DMA_DATA - DMA Data
27739  * - XCVR_DTEST_CTRL - Digital Test Control
27740  * - XCVR_PB_CTRL - Packet Buffer Control Register
27741  * - XCVR_TSM_CTRL - Transceiver Sequence Manager Control
27742  * - XCVR_END_OF_SEQ - End of Sequence Control
27743  * - XCVR_TSM_OVRD0 - TSM Override 0
27744  * - XCVR_TSM_OVRD1 - TSM Override 1
27745  * - XCVR_TSM_OVRD2 - TSM Override 2
27746  * - XCVR_TSM_OVRD3 - TSM Override 3
27747  * - XCVR_PA_POWER - PA Power
27748  * - XCVR_PA_BIAS_TBL0 - PA Bias Table 0
27749  * - XCVR_PA_BIAS_TBL1 - PA Bias Table 1
27750  * - XCVR_RECYCLE_COUNT - Recycle Count Register
27751  * - XCVR_TSM_TIMING00 - TSM_TIMING00
27752  * - XCVR_TSM_TIMING01 - TSM_TIMING01
27753  * - XCVR_TSM_TIMING02 - TSM_TIMING02
27754  * - XCVR_TSM_TIMING03 - TSM_TIMING03
27755  * - XCVR_TSM_TIMING04 - TSM_TIMING04
27756  * - XCVR_TSM_TIMING05 - TSM_TIMING05
27757  * - XCVR_TSM_TIMING06 - TSM_TIMING06
27758  * - XCVR_TSM_TIMING07 - TSM_TIMING07
27759  * - XCVR_TSM_TIMING08 - TSM_TIMING08
27760  * - XCVR_TSM_TIMING09 - TSM_TIMING09
27761  * - XCVR_TSM_TIMING10 - TSM_TIMING10
27762  * - XCVR_TSM_TIMING11 - TSM_TIMING11
27763  * - XCVR_TSM_TIMING12 - TSM_TIMING12
27764  * - XCVR_TSM_TIMING13 - TSM_TIMING13
27765  * - XCVR_TSM_TIMING14 - TSM_TIMING14
27766  * - XCVR_TSM_TIMING15 - TSM_TIMING15
27767  * - XCVR_TSM_TIMING16 - TSM_TIMING16
27768  * - XCVR_TSM_TIMING17 - TSM_TIMING17
27769  * - XCVR_TSM_TIMING18 - TSM_TIMING18
27770  * - XCVR_TSM_TIMING19 - TSM_TIMING19
27771  * - XCVR_TSM_TIMING20 - TSM_TIMING20
27772  * - XCVR_TSM_TIMING21 - TSM_TIMING21
27773  * - XCVR_TSM_TIMING22 - TSM_TIMING22
27774  * - XCVR_TSM_TIMING23 - TSM_TIMING23
27775  * - XCVR_TSM_TIMING24 - TSM_TIMING24
27776  * - XCVR_TSM_TIMING25 - TSM_TIMING25
27777  * - XCVR_TSM_TIMING26 - TSM_TIMING26
27778  * - XCVR_TSM_TIMING27 - TSM_TIMING27
27779  * - XCVR_TSM_TIMING28 - TSM_TIMING28
27780  * - XCVR_TSM_TIMING29 - TSM_TIMING29
27781  * - XCVR_TSM_TIMING30 - TSM_TIMING30
27782  * - XCVR_TSM_TIMING31 - TSM_TIMING31
27783  * - XCVR_TSM_TIMING32 - TSM_TIMING32
27784  * - XCVR_TSM_TIMING33 - TSM_TIMING33
27785  * - XCVR_TSM_TIMING34 - TSM_TIMING34
27786  * - XCVR_TSM_TIMING35 - TSM_TIMING35
27787  * - XCVR_TSM_TIMING36 - TSM_TIMING36
27788  * - XCVR_TSM_TIMING37 - TSM_TIMING37
27789  * - XCVR_TSM_TIMING38 - TSM_TIMING38
27790  * - XCVR_TSM_TIMING39 - TSM_TIMING39
27791  * - XCVR_TSM_TIMING40 - TSM_TIMING40
27792  * - XCVR_TSM_TIMING41 - TSM_TIMING41
27793  * - XCVR_TSM_TIMING42 - TSM_TIMING42
27794  * - XCVR_TSM_TIMING43 - TSM_TIMING43
27795  * - XCVR_CORR_CTRL - CORR_CTRL
27796  * - XCVR_PN_TYPE - PN_TYPE
27797  * - XCVR_PN_CODE - PN_CODE
27798  * - XCVR_SYNC_CTRL - Sync Control
27799  * - XCVR_SNF_THR - SNF_THR
27800  * - XCVR_FAD_THR - FAD_THR
27801  * - XCVR_ZBDEM_AFC - ZBDEM_AFC
27802  * - XCVR_LPPS_CTRL - LPPS Control Register
27803  * - XCVR_ADC_CTRL - ADC Control
27804  * - XCVR_ADC_TUNE - ADC Tuning
27805  * - XCVR_ADC_ADJ - ADC Adjustment
27806  * - XCVR_ADC_REGS - ADC Regulators
27807  * - XCVR_ADC_TRIMS - ADC Regulator Trims
27808  * - XCVR_ADC_TEST_CTRL - ADC Test Control
27809  * - XCVR_BBF_CTRL - Baseband Filter Control
27810  * - XCVR_RX_ANA_CTRL - RX Analog Control
27811  * - XCVR_XTAL_CTRL - Crystal Oscillator Control Register 1
27812  * - XCVR_XTAL_CTRL2 - Crystal Oscillator Control Register 2
27813  * - XCVR_BGAP_CTRL - Bandgap Control
27814  * - XCVR_PLL_CTRL - PLL Control Register
27815  * - XCVR_PLL_CTRL2 - PLL Control Register 2
27816  * - XCVR_PLL_TEST_CTRL - PLL Test Control
27817  * - XCVR_QGEN_CTRL - QGEN Control
27818  * - XCVR_TCA_CTRL - TCA Control
27819  * - XCVR_TZA_CTRL - TZA Control
27820  * - XCVR_TX_ANA_CTRL - TX Analog Control
27821  * - XCVR_ANA_SPARE - Analog Spare
27822  */
27823 
27824 #define XCVR_INSTANCE_COUNT (1U) /*!< Number of instances of the XCVR module. */
27825 #define XCVR_IDX (0U) /*!< Instance number for XCVR. */
27826 
27827 /*******************************************************************************
27828  * XCVR_RX_DIG_CTRL - RX Digital Control
27829  ******************************************************************************/
27830 
27831 /*!
27832  * @brief XCVR_RX_DIG_CTRL - RX Digital Control (RW)
27833  *
27834  * Reset value: 0x00000000U
27835  */
27836 /*!
27837  * @name Constants and macros for entire XCVR_RX_DIG_CTRL register
27838  */
27839 /*@{*/
27840 #define XCVR_RD_RX_DIG_CTRL(base) (XCVR_RX_DIG_CTRL_REG(base))
27841 #define XCVR_WR_RX_DIG_CTRL(base, value) (XCVR_RX_DIG_CTRL_REG(base) = (value))
27842 #define XCVR_RMW_RX_DIG_CTRL(base, mask, value) (XCVR_WR_RX_DIG_CTRL(base, (XCVR_RD_RX_DIG_CTRL(base) & ~(mask)) | (value)))
27843 #define XCVR_SET_RX_DIG_CTRL(base, value) (BME_OR32(&XCVR_RX_DIG_CTRL_REG(base), (uint32_t)(value)))
27844 #define XCVR_CLR_RX_DIG_CTRL(base, value) (BME_AND32(&XCVR_RX_DIG_CTRL_REG(base), (uint32_t)(~(value))))
27845 #define XCVR_TOG_RX_DIG_CTRL(base, value) (BME_XOR32(&XCVR_RX_DIG_CTRL_REG(base), (uint32_t)(value)))
27846 /*@}*/
27847 
27848 /*
27849  * Constants & macros for individual XCVR_RX_DIG_CTRL bitfields
27850  */
27851 
27852 /*!
27853  * @name Register XCVR_RX_DIG_CTRL, field RX_ADC_NEGEDGE[0] (RW)
27854  *
27855  * Selects which edge of the clock the ADC data is registered.
27856  *
27857  * Values:
27858  * - 0b0 - Register ADC data on positive edge of clock
27859  * - 0b1 - Register ADC data on negative edge of clock
27860  */
27861 /*@{*/
27862 /*! @brief Read current value of the XCVR_RX_DIG_CTRL_RX_ADC_NEGEDGE field. */
27863 #define XCVR_RD_RX_DIG_CTRL_RX_ADC_NEGEDGE(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL_RX_ADC_NEGEDGE_MASK) >> XCVR_RX_DIG_CTRL_RX_ADC_NEGEDGE_SHIFT)
27864 #define XCVR_BRD_RX_DIG_CTRL_RX_ADC_NEGEDGE(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DIG_CTRL_RX_ADC_NEGEDGE_SHIFT, XCVR_RX_DIG_CTRL_RX_ADC_NEGEDGE_WIDTH))
27865 
27866 /*! @brief Set the RX_ADC_NEGEDGE field to a new value. */
27867 #define XCVR_WR_RX_DIG_CTRL_RX_ADC_NEGEDGE(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_CTRL_RX_ADC_NEGEDGE_MASK, XCVR_RX_DIG_CTRL_RX_ADC_NEGEDGE(value)))
27868 #define XCVR_BWR_RX_DIG_CTRL_RX_ADC_NEGEDGE(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((uint32_t)(value) << XCVR_RX_DIG_CTRL_RX_ADC_NEGEDGE_SHIFT), XCVR_RX_DIG_CTRL_RX_ADC_NEGEDGE_SHIFT, XCVR_RX_DIG_CTRL_RX_ADC_NEGEDGE_WIDTH))
27869 /*@}*/
27870 
27871 /*!
27872  * @name Register XCVR_RX_DIG_CTRL, field RX_CH_FILT_BYPASS[1] (RW)
27873  *
27874  * Selects whether to disable and bypass channel filter.
27875  *
27876  * Values:
27877  * - 0b0 - Channel filter is enabled.
27878  * - 0b1 - Disable and bypass channel filter.
27879  */
27880 /*@{*/
27881 /*! @brief Read current value of the XCVR_RX_DIG_CTRL_RX_CH_FILT_BYPASS field. */
27882 #define XCVR_RD_RX_DIG_CTRL_RX_CH_FILT_BYPASS(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL_RX_CH_FILT_BYPASS_MASK) >> XCVR_RX_DIG_CTRL_RX_CH_FILT_BYPASS_SHIFT)
27883 #define XCVR_BRD_RX_DIG_CTRL_RX_CH_FILT_BYPASS(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DIG_CTRL_RX_CH_FILT_BYPASS_SHIFT, XCVR_RX_DIG_CTRL_RX_CH_FILT_BYPASS_WIDTH))
27884 
27885 /*! @brief Set the RX_CH_FILT_BYPASS field to a new value. */
27886 #define XCVR_WR_RX_DIG_CTRL_RX_CH_FILT_BYPASS(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_CTRL_RX_CH_FILT_BYPASS_MASK, XCVR_RX_DIG_CTRL_RX_CH_FILT_BYPASS(value)))
27887 #define XCVR_BWR_RX_DIG_CTRL_RX_CH_FILT_BYPASS(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((uint32_t)(value) << XCVR_RX_DIG_CTRL_RX_CH_FILT_BYPASS_SHIFT), XCVR_RX_DIG_CTRL_RX_CH_FILT_BYPASS_SHIFT, XCVR_RX_DIG_CTRL_RX_CH_FILT_BYPASS_WIDTH))
27888 /*@}*/
27889 
27890 /*!
27891  * @name Register XCVR_RX_DIG_CTRL, field RX_ADC_RAW_EN[2] (RW)
27892  *
27893  * Values:
27894  * - 0b0 - Normal operation.
27895  * - 0b1 - The decimation filter's 12bit output consists of two unfiltered 5-bit
27896  *     ADC samples. This is for test purposes only to observe ADC output via
27897  *     XCVR DMA or DTEST.
27898  */
27899 /*@{*/
27900 /*! @brief Read current value of the XCVR_RX_DIG_CTRL_RX_ADC_RAW_EN field. */
27901 #define XCVR_RD_RX_DIG_CTRL_RX_ADC_RAW_EN(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL_RX_ADC_RAW_EN_MASK) >> XCVR_RX_DIG_CTRL_RX_ADC_RAW_EN_SHIFT)
27902 #define XCVR_BRD_RX_DIG_CTRL_RX_ADC_RAW_EN(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DIG_CTRL_RX_ADC_RAW_EN_SHIFT, XCVR_RX_DIG_CTRL_RX_ADC_RAW_EN_WIDTH))
27903 
27904 /*! @brief Set the RX_ADC_RAW_EN field to a new value. */
27905 #define XCVR_WR_RX_DIG_CTRL_RX_ADC_RAW_EN(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_CTRL_RX_ADC_RAW_EN_MASK, XCVR_RX_DIG_CTRL_RX_ADC_RAW_EN(value)))
27906 #define XCVR_BWR_RX_DIG_CTRL_RX_ADC_RAW_EN(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((uint32_t)(value) << XCVR_RX_DIG_CTRL_RX_ADC_RAW_EN_SHIFT), XCVR_RX_DIG_CTRL_RX_ADC_RAW_EN_SHIFT, XCVR_RX_DIG_CTRL_RX_ADC_RAW_EN_WIDTH))
27907 /*@}*/
27908 
27909 /*!
27910  * @name Register XCVR_RX_DIG_CTRL, field RX_DEC_FILT_OSR[6:4] (RW)
27911  *
27912  * All undocumented values are Reserved.
27913  *
27914  * Values:
27915  * - 0b000 - OSR 2
27916  * - 0b001 - OSR 4
27917  */
27918 /*@{*/
27919 /*! @brief Read current value of the XCVR_RX_DIG_CTRL_RX_DEC_FILT_OSR field. */
27920 #define XCVR_RD_RX_DIG_CTRL_RX_DEC_FILT_OSR(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL_RX_DEC_FILT_OSR_MASK) >> XCVR_RX_DIG_CTRL_RX_DEC_FILT_OSR_SHIFT)
27921 #define XCVR_BRD_RX_DIG_CTRL_RX_DEC_FILT_OSR(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DIG_CTRL_RX_DEC_FILT_OSR_SHIFT, XCVR_RX_DIG_CTRL_RX_DEC_FILT_OSR_WIDTH))
27922 
27923 /*! @brief Set the RX_DEC_FILT_OSR field to a new value. */
27924 #define XCVR_WR_RX_DIG_CTRL_RX_DEC_FILT_OSR(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_CTRL_RX_DEC_FILT_OSR_MASK, XCVR_RX_DIG_CTRL_RX_DEC_FILT_OSR(value)))
27925 #define XCVR_BWR_RX_DIG_CTRL_RX_DEC_FILT_OSR(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((uint32_t)(value) << XCVR_RX_DIG_CTRL_RX_DEC_FILT_OSR_SHIFT), XCVR_RX_DIG_CTRL_RX_DEC_FILT_OSR_SHIFT, XCVR_RX_DIG_CTRL_RX_DEC_FILT_OSR_WIDTH))
27926 /*@}*/
27927 
27928 /*!
27929  * @name Register XCVR_RX_DIG_CTRL, field RX_INTERP_EN[8] (RW)
27930  *
27931  * Values:
27932  * - 0b0 - Interpolator is disabled.
27933  * - 0b1 - Interpolator is enabled.
27934  */
27935 /*@{*/
27936 /*! @brief Read current value of the XCVR_RX_DIG_CTRL_RX_INTERP_EN field. */
27937 #define XCVR_RD_RX_DIG_CTRL_RX_INTERP_EN(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL_RX_INTERP_EN_MASK) >> XCVR_RX_DIG_CTRL_RX_INTERP_EN_SHIFT)
27938 #define XCVR_BRD_RX_DIG_CTRL_RX_INTERP_EN(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DIG_CTRL_RX_INTERP_EN_SHIFT, XCVR_RX_DIG_CTRL_RX_INTERP_EN_WIDTH))
27939 
27940 /*! @brief Set the RX_INTERP_EN field to a new value. */
27941 #define XCVR_WR_RX_DIG_CTRL_RX_INTERP_EN(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_CTRL_RX_INTERP_EN_MASK, XCVR_RX_DIG_CTRL_RX_INTERP_EN(value)))
27942 #define XCVR_BWR_RX_DIG_CTRL_RX_INTERP_EN(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((uint32_t)(value) << XCVR_RX_DIG_CTRL_RX_INTERP_EN_SHIFT), XCVR_RX_DIG_CTRL_RX_INTERP_EN_SHIFT, XCVR_RX_DIG_CTRL_RX_INTERP_EN_WIDTH))
27943 /*@}*/
27944 
27945 /*!
27946  * @name Register XCVR_RX_DIG_CTRL, field RX_NORM_EN[9] (RW)
27947  *
27948  * Values:
27949  * - 0b0 - Normalizer is disabled.
27950  * - 0b1 - Normalizer is enabled.
27951  */
27952 /*@{*/
27953 /*! @brief Read current value of the XCVR_RX_DIG_CTRL_RX_NORM_EN field. */
27954 #define XCVR_RD_RX_DIG_CTRL_RX_NORM_EN(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL_RX_NORM_EN_MASK) >> XCVR_RX_DIG_CTRL_RX_NORM_EN_SHIFT)
27955 #define XCVR_BRD_RX_DIG_CTRL_RX_NORM_EN(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DIG_CTRL_RX_NORM_EN_SHIFT, XCVR_RX_DIG_CTRL_RX_NORM_EN_WIDTH))
27956 
27957 /*! @brief Set the RX_NORM_EN field to a new value. */
27958 #define XCVR_WR_RX_DIG_CTRL_RX_NORM_EN(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_CTRL_RX_NORM_EN_MASK, XCVR_RX_DIG_CTRL_RX_NORM_EN(value)))
27959 #define XCVR_BWR_RX_DIG_CTRL_RX_NORM_EN(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((uint32_t)(value) << XCVR_RX_DIG_CTRL_RX_NORM_EN_SHIFT), XCVR_RX_DIG_CTRL_RX_NORM_EN_SHIFT, XCVR_RX_DIG_CTRL_RX_NORM_EN_WIDTH))
27960 /*@}*/
27961 
27962 /*!
27963  * @name Register XCVR_RX_DIG_CTRL, field RX_RSSI_EN[10] (RW)
27964  *
27965  * Values:
27966  * - 0b0 - RSSI measurement is disabled.
27967  * - 0b1 - RSSI measurement is enabled.
27968  */
27969 /*@{*/
27970 /*! @brief Read current value of the XCVR_RX_DIG_CTRL_RX_RSSI_EN field. */
27971 #define XCVR_RD_RX_DIG_CTRL_RX_RSSI_EN(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL_RX_RSSI_EN_MASK) >> XCVR_RX_DIG_CTRL_RX_RSSI_EN_SHIFT)
27972 #define XCVR_BRD_RX_DIG_CTRL_RX_RSSI_EN(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DIG_CTRL_RX_RSSI_EN_SHIFT, XCVR_RX_DIG_CTRL_RX_RSSI_EN_WIDTH))
27973 
27974 /*! @brief Set the RX_RSSI_EN field to a new value. */
27975 #define XCVR_WR_RX_DIG_CTRL_RX_RSSI_EN(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_CTRL_RX_RSSI_EN_MASK, XCVR_RX_DIG_CTRL_RX_RSSI_EN(value)))
27976 #define XCVR_BWR_RX_DIG_CTRL_RX_RSSI_EN(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((uint32_t)(value) << XCVR_RX_DIG_CTRL_RX_RSSI_EN_SHIFT), XCVR_RX_DIG_CTRL_RX_RSSI_EN_SHIFT, XCVR_RX_DIG_CTRL_RX_RSSI_EN_WIDTH))
27977 /*@}*/
27978 
27979 /*!
27980  * @name Register XCVR_RX_DIG_CTRL, field RX_AGC_EN[11] (RW)
27981  *
27982  * Does NOT affect user gains (user gain programming has priority).
27983  *
27984  * Values:
27985  * - 0b0 - AGC is disabled.
27986  * - 0b1 - AGC is enabled.
27987  */
27988 /*@{*/
27989 /*! @brief Read current value of the XCVR_RX_DIG_CTRL_RX_AGC_EN field. */
27990 #define XCVR_RD_RX_DIG_CTRL_RX_AGC_EN(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL_RX_AGC_EN_MASK) >> XCVR_RX_DIG_CTRL_RX_AGC_EN_SHIFT)
27991 #define XCVR_BRD_RX_DIG_CTRL_RX_AGC_EN(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DIG_CTRL_RX_AGC_EN_SHIFT, XCVR_RX_DIG_CTRL_RX_AGC_EN_WIDTH))
27992 
27993 /*! @brief Set the RX_AGC_EN field to a new value. */
27994 #define XCVR_WR_RX_DIG_CTRL_RX_AGC_EN(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_CTRL_RX_AGC_EN_MASK, XCVR_RX_DIG_CTRL_RX_AGC_EN(value)))
27995 #define XCVR_BWR_RX_DIG_CTRL_RX_AGC_EN(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((uint32_t)(value) << XCVR_RX_DIG_CTRL_RX_AGC_EN_SHIFT), XCVR_RX_DIG_CTRL_RX_AGC_EN_SHIFT, XCVR_RX_DIG_CTRL_RX_AGC_EN_WIDTH))
27996 /*@}*/
27997 
27998 /*!
27999  * @name Register XCVR_RX_DIG_CTRL, field RX_DCOC_EN[12] (RW)
28000  *
28001  * Enables DCO calculation and application of corrections.
28002  *
28003  * Values:
28004  * - 0b0 - DCOC is disabled.
28005  * - 0b1 - DCOC is enabled.
28006  */
28007 /*@{*/
28008 /*! @brief Read current value of the XCVR_RX_DIG_CTRL_RX_DCOC_EN field. */
28009 #define XCVR_RD_RX_DIG_CTRL_RX_DCOC_EN(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL_RX_DCOC_EN_MASK) >> XCVR_RX_DIG_CTRL_RX_DCOC_EN_SHIFT)
28010 #define XCVR_BRD_RX_DIG_CTRL_RX_DCOC_EN(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DIG_CTRL_RX_DCOC_EN_SHIFT, XCVR_RX_DIG_CTRL_RX_DCOC_EN_WIDTH))
28011 
28012 /*! @brief Set the RX_DCOC_EN field to a new value. */
28013 #define XCVR_WR_RX_DIG_CTRL_RX_DCOC_EN(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_CTRL_RX_DCOC_EN_MASK, XCVR_RX_DIG_CTRL_RX_DCOC_EN(value)))
28014 #define XCVR_BWR_RX_DIG_CTRL_RX_DCOC_EN(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((uint32_t)(value) << XCVR_RX_DIG_CTRL_RX_DCOC_EN_SHIFT), XCVR_RX_DIG_CTRL_RX_DCOC_EN_SHIFT, XCVR_RX_DIG_CTRL_RX_DCOC_EN_WIDTH))
28015 /*@}*/
28016 
28017 /*!
28018  * @name Register XCVR_RX_DIG_CTRL, field RX_DCOC_CAL_EN[13] (RW)
28019  *
28020  * Enable DCOC warm-up calibration in receiver.
28021  *
28022  * Values:
28023  * - 0b0 - DCOC calibration is disabled.
28024  * - 0b1 - DCOC calibration is enabled.
28025  */
28026 /*@{*/
28027 /*! @brief Read current value of the XCVR_RX_DIG_CTRL_RX_DCOC_CAL_EN field. */
28028 #define XCVR_RD_RX_DIG_CTRL_RX_DCOC_CAL_EN(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK) >> XCVR_RX_DIG_CTRL_RX_DCOC_CAL_EN_SHIFT)
28029 #define XCVR_BRD_RX_DIG_CTRL_RX_DCOC_CAL_EN(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DIG_CTRL_RX_DCOC_CAL_EN_SHIFT, XCVR_RX_DIG_CTRL_RX_DCOC_CAL_EN_WIDTH))
28030 
28031 /*! @brief Set the RX_DCOC_CAL_EN field to a new value. */
28032 #define XCVR_WR_RX_DIG_CTRL_RX_DCOC_CAL_EN(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_CTRL_RX_DCOC_CAL_EN_MASK, XCVR_RX_DIG_CTRL_RX_DCOC_CAL_EN(value)))
28033 #define XCVR_BWR_RX_DIG_CTRL_RX_DCOC_CAL_EN(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((uint32_t)(value) << XCVR_RX_DIG_CTRL_RX_DCOC_CAL_EN_SHIFT), XCVR_RX_DIG_CTRL_RX_DCOC_CAL_EN_SHIFT, XCVR_RX_DIG_CTRL_RX_DCOC_CAL_EN_WIDTH))
28034 /*@}*/
28035 
28036 /*!
28037  * @name Register XCVR_RX_DIG_CTRL, field RX_IQ_SWAP[14] (RW)
28038  *
28039  * Enable swap of I/Q channels (does not affect ADC raw mode).
28040  *
28041  * Values:
28042  * - 0b0 - IQ swap is disabled.
28043  * - 0b1 - IQ swap is enabled.
28044  */
28045 /*@{*/
28046 /*! @brief Read current value of the XCVR_RX_DIG_CTRL_RX_IQ_SWAP field. */
28047 #define XCVR_RD_RX_DIG_CTRL_RX_IQ_SWAP(base) ((XCVR_RX_DIG_CTRL_REG(base) & XCVR_RX_DIG_CTRL_RX_IQ_SWAP_MASK) >> XCVR_RX_DIG_CTRL_RX_IQ_SWAP_SHIFT)
28048 #define XCVR_BRD_RX_DIG_CTRL_RX_IQ_SWAP(base) (BME_UBFX32(&XCVR_RX_DIG_CTRL_REG(base), XCVR_RX_DIG_CTRL_RX_IQ_SWAP_SHIFT, XCVR_RX_DIG_CTRL_RX_IQ_SWAP_WIDTH))
28049 
28050 /*! @brief Set the RX_IQ_SWAP field to a new value. */
28051 #define XCVR_WR_RX_DIG_CTRL_RX_IQ_SWAP(base, value) (XCVR_RMW_RX_DIG_CTRL(base, XCVR_RX_DIG_CTRL_RX_IQ_SWAP_MASK, XCVR_RX_DIG_CTRL_RX_IQ_SWAP(value)))
28052 #define XCVR_BWR_RX_DIG_CTRL_RX_IQ_SWAP(base, value) (BME_BFI32(&XCVR_RX_DIG_CTRL_REG(base), ((uint32_t)(value) << XCVR_RX_DIG_CTRL_RX_IQ_SWAP_SHIFT), XCVR_RX_DIG_CTRL_RX_IQ_SWAP_SHIFT, XCVR_RX_DIG_CTRL_RX_IQ_SWAP_WIDTH))
28053 /*@}*/
28054 
28055 /*******************************************************************************
28056  * XCVR_AGC_CTRL_0 - AGC Control 0
28057  ******************************************************************************/
28058 
28059 /*!
28060  * @brief XCVR_AGC_CTRL_0 - AGC Control 0 (RW)
28061  *
28062  * Reset value: 0x00000000U
28063  */
28064 /*!
28065  * @name Constants and macros for entire XCVR_AGC_CTRL_0 register
28066  */
28067 /*@{*/
28068 #define XCVR_RD_AGC_CTRL_0(base) (XCVR_AGC_CTRL_0_REG(base))
28069 #define XCVR_WR_AGC_CTRL_0(base, value) (XCVR_AGC_CTRL_0_REG(base) = (value))
28070 #define XCVR_RMW_AGC_CTRL_0(base, mask, value) (XCVR_WR_AGC_CTRL_0(base, (XCVR_RD_AGC_CTRL_0(base) & ~(mask)) | (value)))
28071 #define XCVR_SET_AGC_CTRL_0(base, value) (BME_OR32(&XCVR_AGC_CTRL_0_REG(base), (uint32_t)(value)))
28072 #define XCVR_CLR_AGC_CTRL_0(base, value) (BME_AND32(&XCVR_AGC_CTRL_0_REG(base), (uint32_t)(~(value))))
28073 #define XCVR_TOG_AGC_CTRL_0(base, value) (BME_XOR32(&XCVR_AGC_CTRL_0_REG(base), (uint32_t)(value)))
28074 /*@}*/
28075 
28076 /*
28077  * Constants & macros for individual XCVR_AGC_CTRL_0 bitfields
28078  */
28079 
28080 /*!
28081  * @name Register XCVR_AGC_CTRL_0, field SLOW_AGC_EN[0] (RW)
28082  *
28083  * Allow AGC to enter into slow mode.
28084  */
28085 /*@{*/
28086 /*! @brief Read current value of the XCVR_AGC_CTRL_0_SLOW_AGC_EN field. */
28087 #define XCVR_RD_AGC_CTRL_0_SLOW_AGC_EN(base) ((XCVR_AGC_CTRL_0_REG(base) & XCVR_AGC_CTRL_0_SLOW_AGC_EN_MASK) >> XCVR_AGC_CTRL_0_SLOW_AGC_EN_SHIFT)
28088 #define XCVR_BRD_AGC_CTRL_0_SLOW_AGC_EN(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_CTRL_0_SLOW_AGC_EN_SHIFT, XCVR_AGC_CTRL_0_SLOW_AGC_EN_WIDTH))
28089 
28090 /*! @brief Set the SLOW_AGC_EN field to a new value. */
28091 #define XCVR_WR_AGC_CTRL_0_SLOW_AGC_EN(base, value) (XCVR_RMW_AGC_CTRL_0(base, XCVR_AGC_CTRL_0_SLOW_AGC_EN_MASK, XCVR_AGC_CTRL_0_SLOW_AGC_EN(value)))
28092 #define XCVR_BWR_AGC_CTRL_0_SLOW_AGC_EN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_0_SLOW_AGC_EN_SHIFT), XCVR_AGC_CTRL_0_SLOW_AGC_EN_SHIFT, XCVR_AGC_CTRL_0_SLOW_AGC_EN_WIDTH))
28093 /*@}*/
28094 
28095 /*!
28096  * @name Register XCVR_AGC_CTRL_0, field SLOW_AGC_SRC[2:1] (RW)
28097  *
28098  * Select trigger source for entering slow AGC.
28099  *
28100  * Values:
28101  * - 0b00 - BTLE Preamble Detect
28102  * - 0b01 - Zigbee Preamble Detect
28103  */
28104 /*@{*/
28105 /*! @brief Read current value of the XCVR_AGC_CTRL_0_SLOW_AGC_SRC field. */
28106 #define XCVR_RD_AGC_CTRL_0_SLOW_AGC_SRC(base) ((XCVR_AGC_CTRL_0_REG(base) & XCVR_AGC_CTRL_0_SLOW_AGC_SRC_MASK) >> XCVR_AGC_CTRL_0_SLOW_AGC_SRC_SHIFT)
28107 #define XCVR_BRD_AGC_CTRL_0_SLOW_AGC_SRC(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_CTRL_0_SLOW_AGC_SRC_SHIFT, XCVR_AGC_CTRL_0_SLOW_AGC_SRC_WIDTH))
28108 
28109 /*! @brief Set the SLOW_AGC_SRC field to a new value. */
28110 #define XCVR_WR_AGC_CTRL_0_SLOW_AGC_SRC(base, value) (XCVR_RMW_AGC_CTRL_0(base, XCVR_AGC_CTRL_0_SLOW_AGC_SRC_MASK, XCVR_AGC_CTRL_0_SLOW_AGC_SRC(value)))
28111 #define XCVR_BWR_AGC_CTRL_0_SLOW_AGC_SRC(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_0_SLOW_AGC_SRC_SHIFT), XCVR_AGC_CTRL_0_SLOW_AGC_SRC_SHIFT, XCVR_AGC_CTRL_0_SLOW_AGC_SRC_WIDTH))
28112 /*@}*/
28113 
28114 /*!
28115  * @name Register XCVR_AGC_CTRL_0, field AGC_FREEZE_EN[3] (RW)
28116  *
28117  * Allow AGC to freeze. AGC can still go to hold mode if timer expires (same as
28118  * fast expire) from slow mode.
28119  */
28120 /*@{*/
28121 /*! @brief Read current value of the XCVR_AGC_CTRL_0_AGC_FREEZE_EN field. */
28122 #define XCVR_RD_AGC_CTRL_0_AGC_FREEZE_EN(base) ((XCVR_AGC_CTRL_0_REG(base) & XCVR_AGC_CTRL_0_AGC_FREEZE_EN_MASK) >> XCVR_AGC_CTRL_0_AGC_FREEZE_EN_SHIFT)
28123 #define XCVR_BRD_AGC_CTRL_0_AGC_FREEZE_EN(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_CTRL_0_AGC_FREEZE_EN_SHIFT, XCVR_AGC_CTRL_0_AGC_FREEZE_EN_WIDTH))
28124 
28125 /*! @brief Set the AGC_FREEZE_EN field to a new value. */
28126 #define XCVR_WR_AGC_CTRL_0_AGC_FREEZE_EN(base, value) (XCVR_RMW_AGC_CTRL_0(base, XCVR_AGC_CTRL_0_AGC_FREEZE_EN_MASK, XCVR_AGC_CTRL_0_AGC_FREEZE_EN(value)))
28127 #define XCVR_BWR_AGC_CTRL_0_AGC_FREEZE_EN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_0_AGC_FREEZE_EN_SHIFT), XCVR_AGC_CTRL_0_AGC_FREEZE_EN_SHIFT, XCVR_AGC_CTRL_0_AGC_FREEZE_EN_WIDTH))
28128 /*@}*/
28129 
28130 /*!
28131  * @name Register XCVR_AGC_CTRL_0, field FREEZE_AGC_SRC[5:4] (RW)
28132  *
28133  * Select trigger source for entering freeze AGC.
28134  *
28135  * Values:
28136  * - 0b00 - BTLE Preamble Detect
28137  * - 0b01 - Zigbee Preamble Detect
28138  */
28139 /*@{*/
28140 /*! @brief Read current value of the XCVR_AGC_CTRL_0_FREEZE_AGC_SRC field. */
28141 #define XCVR_RD_AGC_CTRL_0_FREEZE_AGC_SRC(base) ((XCVR_AGC_CTRL_0_REG(base) & XCVR_AGC_CTRL_0_FREEZE_AGC_SRC_MASK) >> XCVR_AGC_CTRL_0_FREEZE_AGC_SRC_SHIFT)
28142 #define XCVR_BRD_AGC_CTRL_0_FREEZE_AGC_SRC(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_CTRL_0_FREEZE_AGC_SRC_SHIFT, XCVR_AGC_CTRL_0_FREEZE_AGC_SRC_WIDTH))
28143 
28144 /*! @brief Set the FREEZE_AGC_SRC field to a new value. */
28145 #define XCVR_WR_AGC_CTRL_0_FREEZE_AGC_SRC(base, value) (XCVR_RMW_AGC_CTRL_0(base, XCVR_AGC_CTRL_0_FREEZE_AGC_SRC_MASK, XCVR_AGC_CTRL_0_FREEZE_AGC_SRC(value)))
28146 #define XCVR_BWR_AGC_CTRL_0_FREEZE_AGC_SRC(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_0_FREEZE_AGC_SRC_SHIFT), XCVR_AGC_CTRL_0_FREEZE_AGC_SRC_SHIFT, XCVR_AGC_CTRL_0_FREEZE_AGC_SRC_WIDTH))
28147 /*@}*/
28148 
28149 /*!
28150  * @name Register XCVR_AGC_CTRL_0, field AGC_UP_EN[6] (RW)
28151  *
28152  * Allow AGC to take upward steps in slow mode.
28153  */
28154 /*@{*/
28155 /*! @brief Read current value of the XCVR_AGC_CTRL_0_AGC_UP_EN field. */
28156 #define XCVR_RD_AGC_CTRL_0_AGC_UP_EN(base) ((XCVR_AGC_CTRL_0_REG(base) & XCVR_AGC_CTRL_0_AGC_UP_EN_MASK) >> XCVR_AGC_CTRL_0_AGC_UP_EN_SHIFT)
28157 #define XCVR_BRD_AGC_CTRL_0_AGC_UP_EN(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_CTRL_0_AGC_UP_EN_SHIFT, XCVR_AGC_CTRL_0_AGC_UP_EN_WIDTH))
28158 
28159 /*! @brief Set the AGC_UP_EN field to a new value. */
28160 #define XCVR_WR_AGC_CTRL_0_AGC_UP_EN(base, value) (XCVR_RMW_AGC_CTRL_0(base, XCVR_AGC_CTRL_0_AGC_UP_EN_MASK, XCVR_AGC_CTRL_0_AGC_UP_EN(value)))
28161 #define XCVR_BWR_AGC_CTRL_0_AGC_UP_EN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_0_AGC_UP_EN_SHIFT), XCVR_AGC_CTRL_0_AGC_UP_EN_SHIFT, XCVR_AGC_CTRL_0_AGC_UP_EN_WIDTH))
28162 /*@}*/
28163 
28164 /*!
28165  * @name Register XCVR_AGC_CTRL_0, field AGC_UP_SRC[7] (RW)
28166  *
28167  * Criterion to use for upward AGC steps.
28168  *
28169  * Values:
28170  * - 0b0 - PDET LO
28171  * - 0b1 - RSSI
28172  */
28173 /*@{*/
28174 /*! @brief Read current value of the XCVR_AGC_CTRL_0_AGC_UP_SRC field. */
28175 #define XCVR_RD_AGC_CTRL_0_AGC_UP_SRC(base) ((XCVR_AGC_CTRL_0_REG(base) & XCVR_AGC_CTRL_0_AGC_UP_SRC_MASK) >> XCVR_AGC_CTRL_0_AGC_UP_SRC_SHIFT)
28176 #define XCVR_BRD_AGC_CTRL_0_AGC_UP_SRC(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_CTRL_0_AGC_UP_SRC_SHIFT, XCVR_AGC_CTRL_0_AGC_UP_SRC_WIDTH))
28177 
28178 /*! @brief Set the AGC_UP_SRC field to a new value. */
28179 #define XCVR_WR_AGC_CTRL_0_AGC_UP_SRC(base, value) (XCVR_RMW_AGC_CTRL_0(base, XCVR_AGC_CTRL_0_AGC_UP_SRC_MASK, XCVR_AGC_CTRL_0_AGC_UP_SRC(value)))
28180 #define XCVR_BWR_AGC_CTRL_0_AGC_UP_SRC(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_0_AGC_UP_SRC_SHIFT), XCVR_AGC_CTRL_0_AGC_UP_SRC_SHIFT, XCVR_AGC_CTRL_0_AGC_UP_SRC_WIDTH))
28181 /*@}*/
28182 
28183 /*!
28184  * @name Register XCVR_AGC_CTRL_0, field AGC_DOWN_BBF_STEP_SZ[11:8] (RW)
28185  *
28186  * Number of table steps for downward step (BBF) in AGC fast.
28187  */
28188 /*@{*/
28189 /*! @brief Read current value of the XCVR_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ field. */
28190 #define XCVR_RD_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ(base) ((XCVR_AGC_CTRL_0_REG(base) & XCVR_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ_MASK) >> XCVR_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ_SHIFT)
28191 #define XCVR_BRD_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ_SHIFT, XCVR_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ_WIDTH))
28192 
28193 /*! @brief Set the AGC_DOWN_BBF_STEP_SZ field to a new value. */
28194 #define XCVR_WR_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ(base, value) (XCVR_RMW_AGC_CTRL_0(base, XCVR_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ_MASK, XCVR_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ(value)))
28195 #define XCVR_BWR_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ_SHIFT), XCVR_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ_SHIFT, XCVR_AGC_CTRL_0_AGC_DOWN_BBF_STEP_SZ_WIDTH))
28196 /*@}*/
28197 
28198 /*!
28199  * @name Register XCVR_AGC_CTRL_0, field AGC_DOWN_TZA_STEP_SZ[15:12] (RW)
28200  *
28201  * Number of table steps for downward step (TZA) in AGC fast.
28202  */
28203 /*@{*/
28204 /*! @brief Read current value of the XCVR_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ field. */
28205 #define XCVR_RD_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ(base) ((XCVR_AGC_CTRL_0_REG(base) & XCVR_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ_MASK) >> XCVR_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ_SHIFT)
28206 #define XCVR_BRD_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ_SHIFT, XCVR_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ_WIDTH))
28207 
28208 /*! @brief Set the AGC_DOWN_TZA_STEP_SZ field to a new value. */
28209 #define XCVR_WR_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ(base, value) (XCVR_RMW_AGC_CTRL_0(base, XCVR_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ_MASK, XCVR_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ(value)))
28210 #define XCVR_BWR_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ_SHIFT), XCVR_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ_SHIFT, XCVR_AGC_CTRL_0_AGC_DOWN_TZA_STEP_SZ_WIDTH))
28211 /*@}*/
28212 
28213 /*!
28214  * @name Register XCVR_AGC_CTRL_0, field AGC_UP_RSSI_THRESH[23:16] (RW)
28215  *
28216  * ADC RSSI threshold to take upward step (AGC slow).
28217  */
28218 /*@{*/
28219 /*! @brief Read current value of the XCVR_AGC_CTRL_0_AGC_UP_RSSI_THRESH field. */
28220 #define XCVR_RD_AGC_CTRL_0_AGC_UP_RSSI_THRESH(base) ((XCVR_AGC_CTRL_0_REG(base) & XCVR_AGC_CTRL_0_AGC_UP_RSSI_THRESH_MASK) >> XCVR_AGC_CTRL_0_AGC_UP_RSSI_THRESH_SHIFT)
28221 #define XCVR_BRD_AGC_CTRL_0_AGC_UP_RSSI_THRESH(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_CTRL_0_AGC_UP_RSSI_THRESH_SHIFT, XCVR_AGC_CTRL_0_AGC_UP_RSSI_THRESH_WIDTH))
28222 
28223 /*! @brief Set the AGC_UP_RSSI_THRESH field to a new value. */
28224 #define XCVR_WR_AGC_CTRL_0_AGC_UP_RSSI_THRESH(base, value) (XCVR_RMW_AGC_CTRL_0(base, XCVR_AGC_CTRL_0_AGC_UP_RSSI_THRESH_MASK, XCVR_AGC_CTRL_0_AGC_UP_RSSI_THRESH(value)))
28225 #define XCVR_BWR_AGC_CTRL_0_AGC_UP_RSSI_THRESH(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_0_AGC_UP_RSSI_THRESH_SHIFT), XCVR_AGC_CTRL_0_AGC_UP_RSSI_THRESH_SHIFT, XCVR_AGC_CTRL_0_AGC_UP_RSSI_THRESH_WIDTH))
28226 /*@}*/
28227 
28228 /*!
28229  * @name Register XCVR_AGC_CTRL_0, field AGC_DOWN_RSSI_THRESH[31:24] (RW)
28230  *
28231  * ADC RSSI threshold to take downward step (AGC slow).
28232  */
28233 /*@{*/
28234 /*! @brief Read current value of the XCVR_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH field. */
28235 #define XCVR_RD_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(base) ((XCVR_AGC_CTRL_0_REG(base) & XCVR_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_MASK) >> XCVR_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_SHIFT)
28236 #define XCVR_BRD_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(base) (BME_UBFX32(&XCVR_AGC_CTRL_0_REG(base), XCVR_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_SHIFT, XCVR_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_WIDTH))
28237 
28238 /*! @brief Set the AGC_DOWN_RSSI_THRESH field to a new value. */
28239 #define XCVR_WR_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(base, value) (XCVR_RMW_AGC_CTRL_0(base, XCVR_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_MASK, XCVR_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(value)))
28240 #define XCVR_BWR_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH(base, value) (BME_BFI32(&XCVR_AGC_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_SHIFT), XCVR_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_SHIFT, XCVR_AGC_CTRL_0_AGC_DOWN_RSSI_THRESH_WIDTH))
28241 /*@}*/
28242 
28243 /*******************************************************************************
28244  * XCVR_AGC_CTRL_1 - AGC Control 1
28245  ******************************************************************************/
28246 
28247 /*!
28248  * @brief XCVR_AGC_CTRL_1 - AGC Control 1 (RW)
28249  *
28250  * Reset value: 0x00000000U
28251  */
28252 /*!
28253  * @name Constants and macros for entire XCVR_AGC_CTRL_1 register
28254  */
28255 /*@{*/
28256 #define XCVR_RD_AGC_CTRL_1(base) (XCVR_AGC_CTRL_1_REG(base))
28257 #define XCVR_WR_AGC_CTRL_1(base, value) (XCVR_AGC_CTRL_1_REG(base) = (value))
28258 #define XCVR_RMW_AGC_CTRL_1(base, mask, value) (XCVR_WR_AGC_CTRL_1(base, (XCVR_RD_AGC_CTRL_1(base) & ~(mask)) | (value)))
28259 #define XCVR_SET_AGC_CTRL_1(base, value) (BME_OR32(&XCVR_AGC_CTRL_1_REG(base), (uint32_t)(value)))
28260 #define XCVR_CLR_AGC_CTRL_1(base, value) (BME_AND32(&XCVR_AGC_CTRL_1_REG(base), (uint32_t)(~(value))))
28261 #define XCVR_TOG_AGC_CTRL_1(base, value) (BME_XOR32(&XCVR_AGC_CTRL_1_REG(base), (uint32_t)(value)))
28262 /*@}*/
28263 
28264 /*
28265  * Constants & macros for individual XCVR_AGC_CTRL_1 bitfields
28266  */
28267 
28268 /*!
28269  * @name Register XCVR_AGC_CTRL_1, field BBF_ALT_CODE[3:0] (RW)
28270  *
28271  * Alternate BBF gain code selected when bbf_gain_xx=0xF. Also used as initial
28272  * gain value before DCOC cal is performed.
28273  */
28274 /*@{*/
28275 /*! @brief Read current value of the XCVR_AGC_CTRL_1_BBF_ALT_CODE field. */
28276 #define XCVR_RD_AGC_CTRL_1_BBF_ALT_CODE(base) ((XCVR_AGC_CTRL_1_REG(base) & XCVR_AGC_CTRL_1_BBF_ALT_CODE_MASK) >> XCVR_AGC_CTRL_1_BBF_ALT_CODE_SHIFT)
28277 #define XCVR_BRD_AGC_CTRL_1_BBF_ALT_CODE(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC_CTRL_1_BBF_ALT_CODE_SHIFT, XCVR_AGC_CTRL_1_BBF_ALT_CODE_WIDTH))
28278 
28279 /*! @brief Set the BBF_ALT_CODE field to a new value. */
28280 #define XCVR_WR_AGC_CTRL_1_BBF_ALT_CODE(base, value) (XCVR_RMW_AGC_CTRL_1(base, XCVR_AGC_CTRL_1_BBF_ALT_CODE_MASK, XCVR_AGC_CTRL_1_BBF_ALT_CODE(value)))
28281 #define XCVR_BWR_AGC_CTRL_1_BBF_ALT_CODE(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_1_BBF_ALT_CODE_SHIFT), XCVR_AGC_CTRL_1_BBF_ALT_CODE_SHIFT, XCVR_AGC_CTRL_1_BBF_ALT_CODE_WIDTH))
28282 /*@}*/
28283 
28284 /*!
28285  * @name Register XCVR_AGC_CTRL_1, field LNM_ALT_CODE[11:4] (RW)
28286  *
28287  * Alternate LNM gain code selected when lnm_gain_xx=F. Also used as initial
28288  * gain value before DCOC cal is performed.
28289  */
28290 /*@{*/
28291 /*! @brief Read current value of the XCVR_AGC_CTRL_1_LNM_ALT_CODE field. */
28292 #define XCVR_RD_AGC_CTRL_1_LNM_ALT_CODE(base) ((XCVR_AGC_CTRL_1_REG(base) & XCVR_AGC_CTRL_1_LNM_ALT_CODE_MASK) >> XCVR_AGC_CTRL_1_LNM_ALT_CODE_SHIFT)
28293 #define XCVR_BRD_AGC_CTRL_1_LNM_ALT_CODE(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC_CTRL_1_LNM_ALT_CODE_SHIFT, XCVR_AGC_CTRL_1_LNM_ALT_CODE_WIDTH))
28294 
28295 /*! @brief Set the LNM_ALT_CODE field to a new value. */
28296 #define XCVR_WR_AGC_CTRL_1_LNM_ALT_CODE(base, value) (XCVR_RMW_AGC_CTRL_1(base, XCVR_AGC_CTRL_1_LNM_ALT_CODE_MASK, XCVR_AGC_CTRL_1_LNM_ALT_CODE(value)))
28297 #define XCVR_BWR_AGC_CTRL_1_LNM_ALT_CODE(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_1_LNM_ALT_CODE_SHIFT), XCVR_AGC_CTRL_1_LNM_ALT_CODE_SHIFT, XCVR_AGC_CTRL_1_LNM_ALT_CODE_WIDTH))
28298 /*@}*/
28299 
28300 /*!
28301  * @name Register XCVR_AGC_CTRL_1, field LNM_USER_GAIN[15:12] (RW)
28302  *
28303  * user defined lnm gain index if user_lnm_gain_en =1
28304  */
28305 /*@{*/
28306 /*! @brief Read current value of the XCVR_AGC_CTRL_1_LNM_USER_GAIN field. */
28307 #define XCVR_RD_AGC_CTRL_1_LNM_USER_GAIN(base) ((XCVR_AGC_CTRL_1_REG(base) & XCVR_AGC_CTRL_1_LNM_USER_GAIN_MASK) >> XCVR_AGC_CTRL_1_LNM_USER_GAIN_SHIFT)
28308 #define XCVR_BRD_AGC_CTRL_1_LNM_USER_GAIN(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC_CTRL_1_LNM_USER_GAIN_SHIFT, XCVR_AGC_CTRL_1_LNM_USER_GAIN_WIDTH))
28309 
28310 /*! @brief Set the LNM_USER_GAIN field to a new value. */
28311 #define XCVR_WR_AGC_CTRL_1_LNM_USER_GAIN(base, value) (XCVR_RMW_AGC_CTRL_1(base, XCVR_AGC_CTRL_1_LNM_USER_GAIN_MASK, XCVR_AGC_CTRL_1_LNM_USER_GAIN(value)))
28312 #define XCVR_BWR_AGC_CTRL_1_LNM_USER_GAIN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_1_LNM_USER_GAIN_SHIFT), XCVR_AGC_CTRL_1_LNM_USER_GAIN_SHIFT, XCVR_AGC_CTRL_1_LNM_USER_GAIN_WIDTH))
28313 /*@}*/
28314 
28315 /*!
28316  * @name Register XCVR_AGC_CTRL_1, field BBF_USER_GAIN[19:16] (RW)
28317  *
28318  * User defined BBF gain index if user_bbf_gain_en =1
28319  */
28320 /*@{*/
28321 /*! @brief Read current value of the XCVR_AGC_CTRL_1_BBF_USER_GAIN field. */
28322 #define XCVR_RD_AGC_CTRL_1_BBF_USER_GAIN(base) ((XCVR_AGC_CTRL_1_REG(base) & XCVR_AGC_CTRL_1_BBF_USER_GAIN_MASK) >> XCVR_AGC_CTRL_1_BBF_USER_GAIN_SHIFT)
28323 #define XCVR_BRD_AGC_CTRL_1_BBF_USER_GAIN(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC_CTRL_1_BBF_USER_GAIN_SHIFT, XCVR_AGC_CTRL_1_BBF_USER_GAIN_WIDTH))
28324 
28325 /*! @brief Set the BBF_USER_GAIN field to a new value. */
28326 #define XCVR_WR_AGC_CTRL_1_BBF_USER_GAIN(base, value) (XCVR_RMW_AGC_CTRL_1(base, XCVR_AGC_CTRL_1_BBF_USER_GAIN_MASK, XCVR_AGC_CTRL_1_BBF_USER_GAIN(value)))
28327 #define XCVR_BWR_AGC_CTRL_1_BBF_USER_GAIN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_1_BBF_USER_GAIN_SHIFT), XCVR_AGC_CTRL_1_BBF_USER_GAIN_SHIFT, XCVR_AGC_CTRL_1_BBF_USER_GAIN_WIDTH))
28328 /*@}*/
28329 
28330 /*!
28331  * @name Register XCVR_AGC_CTRL_1, field USER_LNM_GAIN_EN[20] (RW)
28332  *
28333  * Enable user defined LNM gain (no AGC).
28334  */
28335 /*@{*/
28336 /*! @brief Read current value of the XCVR_AGC_CTRL_1_USER_LNM_GAIN_EN field. */
28337 #define XCVR_RD_AGC_CTRL_1_USER_LNM_GAIN_EN(base) ((XCVR_AGC_CTRL_1_REG(base) & XCVR_AGC_CTRL_1_USER_LNM_GAIN_EN_MASK) >> XCVR_AGC_CTRL_1_USER_LNM_GAIN_EN_SHIFT)
28338 #define XCVR_BRD_AGC_CTRL_1_USER_LNM_GAIN_EN(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC_CTRL_1_USER_LNM_GAIN_EN_SHIFT, XCVR_AGC_CTRL_1_USER_LNM_GAIN_EN_WIDTH))
28339 
28340 /*! @brief Set the USER_LNM_GAIN_EN field to a new value. */
28341 #define XCVR_WR_AGC_CTRL_1_USER_LNM_GAIN_EN(base, value) (XCVR_RMW_AGC_CTRL_1(base, XCVR_AGC_CTRL_1_USER_LNM_GAIN_EN_MASK, XCVR_AGC_CTRL_1_USER_LNM_GAIN_EN(value)))
28342 #define XCVR_BWR_AGC_CTRL_1_USER_LNM_GAIN_EN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_1_USER_LNM_GAIN_EN_SHIFT), XCVR_AGC_CTRL_1_USER_LNM_GAIN_EN_SHIFT, XCVR_AGC_CTRL_1_USER_LNM_GAIN_EN_WIDTH))
28343 /*@}*/
28344 
28345 /*!
28346  * @name Register XCVR_AGC_CTRL_1, field USER_BBF_GAIN_EN[21] (RW)
28347  *
28348  * Enable user defined BBF gain (no AGC).
28349  */
28350 /*@{*/
28351 /*! @brief Read current value of the XCVR_AGC_CTRL_1_USER_BBF_GAIN_EN field. */
28352 #define XCVR_RD_AGC_CTRL_1_USER_BBF_GAIN_EN(base) ((XCVR_AGC_CTRL_1_REG(base) & XCVR_AGC_CTRL_1_USER_BBF_GAIN_EN_MASK) >> XCVR_AGC_CTRL_1_USER_BBF_GAIN_EN_SHIFT)
28353 #define XCVR_BRD_AGC_CTRL_1_USER_BBF_GAIN_EN(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC_CTRL_1_USER_BBF_GAIN_EN_SHIFT, XCVR_AGC_CTRL_1_USER_BBF_GAIN_EN_WIDTH))
28354 
28355 /*! @brief Set the USER_BBF_GAIN_EN field to a new value. */
28356 #define XCVR_WR_AGC_CTRL_1_USER_BBF_GAIN_EN(base, value) (XCVR_RMW_AGC_CTRL_1(base, XCVR_AGC_CTRL_1_USER_BBF_GAIN_EN_MASK, XCVR_AGC_CTRL_1_USER_BBF_GAIN_EN(value)))
28357 #define XCVR_BWR_AGC_CTRL_1_USER_BBF_GAIN_EN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_1_USER_BBF_GAIN_EN_SHIFT), XCVR_AGC_CTRL_1_USER_BBF_GAIN_EN_SHIFT, XCVR_AGC_CTRL_1_USER_BBF_GAIN_EN_WIDTH))
28358 /*@}*/
28359 
28360 /*!
28361  * @name Register XCVR_AGC_CTRL_1, field PRESLOW_EN[22] (RW)
28362  *
28363  * Enablepre-slow state.
28364  *
28365  * Values:
28366  * - 0b0 - Pre-slow is disabled.
28367  * - 0b1 - Pre-slow is enabled.
28368  */
28369 /*@{*/
28370 /*! @brief Read current value of the XCVR_AGC_CTRL_1_PRESLOW_EN field. */
28371 #define XCVR_RD_AGC_CTRL_1_PRESLOW_EN(base) ((XCVR_AGC_CTRL_1_REG(base) & XCVR_AGC_CTRL_1_PRESLOW_EN_MASK) >> XCVR_AGC_CTRL_1_PRESLOW_EN_SHIFT)
28372 #define XCVR_BRD_AGC_CTRL_1_PRESLOW_EN(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC_CTRL_1_PRESLOW_EN_SHIFT, XCVR_AGC_CTRL_1_PRESLOW_EN_WIDTH))
28373 
28374 /*! @brief Set the PRESLOW_EN field to a new value. */
28375 #define XCVR_WR_AGC_CTRL_1_PRESLOW_EN(base, value) (XCVR_RMW_AGC_CTRL_1(base, XCVR_AGC_CTRL_1_PRESLOW_EN_MASK, XCVR_AGC_CTRL_1_PRESLOW_EN(value)))
28376 #define XCVR_BWR_AGC_CTRL_1_PRESLOW_EN(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_1_PRESLOW_EN_SHIFT), XCVR_AGC_CTRL_1_PRESLOW_EN_SHIFT, XCVR_AGC_CTRL_1_PRESLOW_EN_WIDTH))
28377 /*@}*/
28378 
28379 /*!
28380  * @name Register XCVR_AGC_CTRL_1, field TZA_GAIN_SETTLE_TIME[31:24] (RW)
28381  *
28382  * Number of clocks to assert TZA peak detector reset (for automatic control).
28383  */
28384 /*@{*/
28385 /*! @brief Read current value of the XCVR_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME field. */
28386 #define XCVR_RD_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME(base) ((XCVR_AGC_CTRL_1_REG(base) & XCVR_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME_MASK) >> XCVR_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME_SHIFT)
28387 #define XCVR_BRD_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME(base) (BME_UBFX32(&XCVR_AGC_CTRL_1_REG(base), XCVR_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME_SHIFT, XCVR_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME_WIDTH))
28388 
28389 /*! @brief Set the TZA_GAIN_SETTLE_TIME field to a new value. */
28390 #define XCVR_WR_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME(base, value) (XCVR_RMW_AGC_CTRL_1(base, XCVR_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME_MASK, XCVR_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME(value)))
28391 #define XCVR_BWR_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME(base, value) (BME_BFI32(&XCVR_AGC_CTRL_1_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME_SHIFT), XCVR_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME_SHIFT, XCVR_AGC_CTRL_1_TZA_GAIN_SETTLE_TIME_WIDTH))
28392 /*@}*/
28393 
28394 /*******************************************************************************
28395  * XCVR_AGC_CTRL_2 - AGC Control 2
28396  ******************************************************************************/
28397 
28398 /*!
28399  * @brief XCVR_AGC_CTRL_2 - AGC Control 2 (RW)
28400  *
28401  * Reset value: 0x00000000U
28402  */
28403 /*!
28404  * @name Constants and macros for entire XCVR_AGC_CTRL_2 register
28405  */
28406 /*@{*/
28407 #define XCVR_RD_AGC_CTRL_2(base) (XCVR_AGC_CTRL_2_REG(base))
28408 #define XCVR_WR_AGC_CTRL_2(base, value) (XCVR_AGC_CTRL_2_REG(base) = (value))
28409 #define XCVR_RMW_AGC_CTRL_2(base, mask, value) (XCVR_WR_AGC_CTRL_2(base, (XCVR_RD_AGC_CTRL_2(base) & ~(mask)) | (value)))
28410 #define XCVR_SET_AGC_CTRL_2(base, value) (BME_OR32(&XCVR_AGC_CTRL_2_REG(base), (uint32_t)(value)))
28411 #define XCVR_CLR_AGC_CTRL_2(base, value) (BME_AND32(&XCVR_AGC_CTRL_2_REG(base), (uint32_t)(~(value))))
28412 #define XCVR_TOG_AGC_CTRL_2(base, value) (BME_XOR32(&XCVR_AGC_CTRL_2_REG(base), (uint32_t)(value)))
28413 /*@}*/
28414 
28415 /*
28416  * Constants & macros for individual XCVR_AGC_CTRL_2 bitfields
28417  */
28418 
28419 /*!
28420  * @name Register XCVR_AGC_CTRL_2, field BBF_PDET_RST[0] (RW)
28421  *
28422  * BBF peak detector reset, manual control.
28423  */
28424 /*@{*/
28425 /*! @brief Read current value of the XCVR_AGC_CTRL_2_BBF_PDET_RST field. */
28426 #define XCVR_RD_AGC_CTRL_2_BBF_PDET_RST(base) ((XCVR_AGC_CTRL_2_REG(base) & XCVR_AGC_CTRL_2_BBF_PDET_RST_MASK) >> XCVR_AGC_CTRL_2_BBF_PDET_RST_SHIFT)
28427 #define XCVR_BRD_AGC_CTRL_2_BBF_PDET_RST(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_AGC_CTRL_2_BBF_PDET_RST_SHIFT, XCVR_AGC_CTRL_2_BBF_PDET_RST_WIDTH))
28428 
28429 /*! @brief Set the BBF_PDET_RST field to a new value. */
28430 #define XCVR_WR_AGC_CTRL_2_BBF_PDET_RST(base, value) (XCVR_RMW_AGC_CTRL_2(base, XCVR_AGC_CTRL_2_BBF_PDET_RST_MASK, XCVR_AGC_CTRL_2_BBF_PDET_RST(value)))
28431 #define XCVR_BWR_AGC_CTRL_2_BBF_PDET_RST(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_2_BBF_PDET_RST_SHIFT), XCVR_AGC_CTRL_2_BBF_PDET_RST_SHIFT, XCVR_AGC_CTRL_2_BBF_PDET_RST_WIDTH))
28432 /*@}*/
28433 
28434 /*!
28435  * @name Register XCVR_AGC_CTRL_2, field TZA_PDET_RST[1] (RW)
28436  *
28437  * TZA peak detector reset, manual control.
28438  */
28439 /*@{*/
28440 /*! @brief Read current value of the XCVR_AGC_CTRL_2_TZA_PDET_RST field. */
28441 #define XCVR_RD_AGC_CTRL_2_TZA_PDET_RST(base) ((XCVR_AGC_CTRL_2_REG(base) & XCVR_AGC_CTRL_2_TZA_PDET_RST_MASK) >> XCVR_AGC_CTRL_2_TZA_PDET_RST_SHIFT)
28442 #define XCVR_BRD_AGC_CTRL_2_TZA_PDET_RST(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_AGC_CTRL_2_TZA_PDET_RST_SHIFT, XCVR_AGC_CTRL_2_TZA_PDET_RST_WIDTH))
28443 
28444 /*! @brief Set the TZA_PDET_RST field to a new value. */
28445 #define XCVR_WR_AGC_CTRL_2_TZA_PDET_RST(base, value) (XCVR_RMW_AGC_CTRL_2(base, XCVR_AGC_CTRL_2_TZA_PDET_RST_MASK, XCVR_AGC_CTRL_2_TZA_PDET_RST(value)))
28446 #define XCVR_BWR_AGC_CTRL_2_TZA_PDET_RST(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_2_TZA_PDET_RST_SHIFT), XCVR_AGC_CTRL_2_TZA_PDET_RST_SHIFT, XCVR_AGC_CTRL_2_TZA_PDET_RST_WIDTH))
28447 /*@}*/
28448 
28449 /*!
28450  * @name Register XCVR_AGC_CTRL_2, field BBF_GAIN_SETTLE_TIME[11:4] (RW)
28451  *
28452  * Number of clocks to assert BBF peak detector reset (for automatic control).
28453  */
28454 /*@{*/
28455 /*! @brief Read current value of the XCVR_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME field. */
28456 #define XCVR_RD_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME(base) ((XCVR_AGC_CTRL_2_REG(base) & XCVR_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME_MASK) >> XCVR_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME_SHIFT)
28457 #define XCVR_BRD_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME_SHIFT, XCVR_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME_WIDTH))
28458 
28459 /*! @brief Set the BBF_GAIN_SETTLE_TIME field to a new value. */
28460 #define XCVR_WR_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME(base, value) (XCVR_RMW_AGC_CTRL_2(base, XCVR_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME_MASK, XCVR_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME(value)))
28461 #define XCVR_BWR_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME_SHIFT), XCVR_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME_SHIFT, XCVR_AGC_CTRL_2_BBF_GAIN_SETTLE_TIME_WIDTH))
28462 /*@}*/
28463 
28464 /*!
28465  * @name Register XCVR_AGC_CTRL_2, field BBF_PDET_THRESH_LO[14:12] (RW)
28466  *
28467  * BBF peak detect LO threshold.
28468  *
28469  * Values:
28470  * - 0b000 - 0.6V
28471  * - 0b001 - 0.675V
28472  * - 0b010 - 0.75V
28473  * - 0b011 - 0.825V
28474  * - 0b100 - 0.9V
28475  * - 0b101 - 0.975V
28476  * - 0b110 - 1.05V
28477  * - 0b111 - 1.125V
28478  */
28479 /*@{*/
28480 /*! @brief Read current value of the XCVR_AGC_CTRL_2_BBF_PDET_THRESH_LO field. */
28481 #define XCVR_RD_AGC_CTRL_2_BBF_PDET_THRESH_LO(base) ((XCVR_AGC_CTRL_2_REG(base) & XCVR_AGC_CTRL_2_BBF_PDET_THRESH_LO_MASK) >> XCVR_AGC_CTRL_2_BBF_PDET_THRESH_LO_SHIFT)
28482 #define XCVR_BRD_AGC_CTRL_2_BBF_PDET_THRESH_LO(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_AGC_CTRL_2_BBF_PDET_THRESH_LO_SHIFT, XCVR_AGC_CTRL_2_BBF_PDET_THRESH_LO_WIDTH))
28483 
28484 /*! @brief Set the BBF_PDET_THRESH_LO field to a new value. */
28485 #define XCVR_WR_AGC_CTRL_2_BBF_PDET_THRESH_LO(base, value) (XCVR_RMW_AGC_CTRL_2(base, XCVR_AGC_CTRL_2_BBF_PDET_THRESH_LO_MASK, XCVR_AGC_CTRL_2_BBF_PDET_THRESH_LO(value)))
28486 #define XCVR_BWR_AGC_CTRL_2_BBF_PDET_THRESH_LO(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_2_BBF_PDET_THRESH_LO_SHIFT), XCVR_AGC_CTRL_2_BBF_PDET_THRESH_LO_SHIFT, XCVR_AGC_CTRL_2_BBF_PDET_THRESH_LO_WIDTH))
28487 /*@}*/
28488 
28489 /*!
28490  * @name Register XCVR_AGC_CTRL_2, field BBF_PDET_THRESH_HI[17:15] (RW)
28491  *
28492  * BBF peak detect HI threshold.
28493  *
28494  * Values:
28495  * - 0b000 - 0.6V
28496  * - 0b001 - 0.675V
28497  * - 0b010 - 0.75V
28498  * - 0b011 - 0.825V
28499  * - 0b100 - 0.9V
28500  * - 0b101 - 0.975V
28501  * - 0b110 - 1.05V
28502  * - 0b111 - 1.125V
28503  */
28504 /*@{*/
28505 /*! @brief Read current value of the XCVR_AGC_CTRL_2_BBF_PDET_THRESH_HI field. */
28506 #define XCVR_RD_AGC_CTRL_2_BBF_PDET_THRESH_HI(base) ((XCVR_AGC_CTRL_2_REG(base) & XCVR_AGC_CTRL_2_BBF_PDET_THRESH_HI_MASK) >> XCVR_AGC_CTRL_2_BBF_PDET_THRESH_HI_SHIFT)
28507 #define XCVR_BRD_AGC_CTRL_2_BBF_PDET_THRESH_HI(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_AGC_CTRL_2_BBF_PDET_THRESH_HI_SHIFT, XCVR_AGC_CTRL_2_BBF_PDET_THRESH_HI_WIDTH))
28508 
28509 /*! @brief Set the BBF_PDET_THRESH_HI field to a new value. */
28510 #define XCVR_WR_AGC_CTRL_2_BBF_PDET_THRESH_HI(base, value) (XCVR_RMW_AGC_CTRL_2(base, XCVR_AGC_CTRL_2_BBF_PDET_THRESH_HI_MASK, XCVR_AGC_CTRL_2_BBF_PDET_THRESH_HI(value)))
28511 #define XCVR_BWR_AGC_CTRL_2_BBF_PDET_THRESH_HI(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_2_BBF_PDET_THRESH_HI_SHIFT), XCVR_AGC_CTRL_2_BBF_PDET_THRESH_HI_SHIFT, XCVR_AGC_CTRL_2_BBF_PDET_THRESH_HI_WIDTH))
28512 /*@}*/
28513 
28514 /*!
28515  * @name Register XCVR_AGC_CTRL_2, field TZA_PDET_THRESH_LO[20:18] (RW)
28516  *
28517  * TZA peak detect LO threshold.
28518  *
28519  * Values:
28520  * - 0b000 - 0.6V
28521  * - 0b001 - 0.675V
28522  * - 0b010 - 0.75V
28523  * - 0b011 - 0.825V
28524  * - 0b100 - 0.9V
28525  * - 0b101 - 0.975V
28526  * - 0b110 - 1.05V
28527  * - 0b111 - 1.125V
28528  */
28529 /*@{*/
28530 /*! @brief Read current value of the XCVR_AGC_CTRL_2_TZA_PDET_THRESH_LO field. */
28531 #define XCVR_RD_AGC_CTRL_2_TZA_PDET_THRESH_LO(base) ((XCVR_AGC_CTRL_2_REG(base) & XCVR_AGC_CTRL_2_TZA_PDET_THRESH_LO_MASK) >> XCVR_AGC_CTRL_2_TZA_PDET_THRESH_LO_SHIFT)
28532 #define XCVR_BRD_AGC_CTRL_2_TZA_PDET_THRESH_LO(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_AGC_CTRL_2_TZA_PDET_THRESH_LO_SHIFT, XCVR_AGC_CTRL_2_TZA_PDET_THRESH_LO_WIDTH))
28533 
28534 /*! @brief Set the TZA_PDET_THRESH_LO field to a new value. */
28535 #define XCVR_WR_AGC_CTRL_2_TZA_PDET_THRESH_LO(base, value) (XCVR_RMW_AGC_CTRL_2(base, XCVR_AGC_CTRL_2_TZA_PDET_THRESH_LO_MASK, XCVR_AGC_CTRL_2_TZA_PDET_THRESH_LO(value)))
28536 #define XCVR_BWR_AGC_CTRL_2_TZA_PDET_THRESH_LO(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_2_TZA_PDET_THRESH_LO_SHIFT), XCVR_AGC_CTRL_2_TZA_PDET_THRESH_LO_SHIFT, XCVR_AGC_CTRL_2_TZA_PDET_THRESH_LO_WIDTH))
28537 /*@}*/
28538 
28539 /*!
28540  * @name Register XCVR_AGC_CTRL_2, field TZA_PDET_THRESH_HI[23:21] (RW)
28541  *
28542  * TZA peak detect HI threshold.
28543  *
28544  * Values:
28545  * - 0b000 - 0.6V
28546  * - 0b001 - 0.675V
28547  * - 0b010 - 0.75V
28548  * - 0b011 - 0.825V
28549  * - 0b100 - 0.9V
28550  * - 0b101 - 0.975V
28551  * - 0b110 - 1.05V
28552  * - 0b111 - 1.125V
28553  */
28554 /*@{*/
28555 /*! @brief Read current value of the XCVR_AGC_CTRL_2_TZA_PDET_THRESH_HI field. */
28556 #define XCVR_RD_AGC_CTRL_2_TZA_PDET_THRESH_HI(base) ((XCVR_AGC_CTRL_2_REG(base) & XCVR_AGC_CTRL_2_TZA_PDET_THRESH_HI_MASK) >> XCVR_AGC_CTRL_2_TZA_PDET_THRESH_HI_SHIFT)
28557 #define XCVR_BRD_AGC_CTRL_2_TZA_PDET_THRESH_HI(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_AGC_CTRL_2_TZA_PDET_THRESH_HI_SHIFT, XCVR_AGC_CTRL_2_TZA_PDET_THRESH_HI_WIDTH))
28558 
28559 /*! @brief Set the TZA_PDET_THRESH_HI field to a new value. */
28560 #define XCVR_WR_AGC_CTRL_2_TZA_PDET_THRESH_HI(base, value) (XCVR_RMW_AGC_CTRL_2(base, XCVR_AGC_CTRL_2_TZA_PDET_THRESH_HI_MASK, XCVR_AGC_CTRL_2_TZA_PDET_THRESH_HI(value)))
28561 #define XCVR_BWR_AGC_CTRL_2_TZA_PDET_THRESH_HI(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_2_TZA_PDET_THRESH_HI_SHIFT), XCVR_AGC_CTRL_2_TZA_PDET_THRESH_HI_SHIFT, XCVR_AGC_CTRL_2_TZA_PDET_THRESH_HI_WIDTH))
28562 /*@}*/
28563 
28564 /*!
28565  * @name Register XCVR_AGC_CTRL_2, field AGC_FAST_EXPIRE[29:24] (RW)
28566  *
28567  * Expire time (uS) for fast AGC (1-63uS).
28568  */
28569 /*@{*/
28570 /*! @brief Read current value of the XCVR_AGC_CTRL_2_AGC_FAST_EXPIRE field. */
28571 #define XCVR_RD_AGC_CTRL_2_AGC_FAST_EXPIRE(base) ((XCVR_AGC_CTRL_2_REG(base) & XCVR_AGC_CTRL_2_AGC_FAST_EXPIRE_MASK) >> XCVR_AGC_CTRL_2_AGC_FAST_EXPIRE_SHIFT)
28572 #define XCVR_BRD_AGC_CTRL_2_AGC_FAST_EXPIRE(base) (BME_UBFX32(&XCVR_AGC_CTRL_2_REG(base), XCVR_AGC_CTRL_2_AGC_FAST_EXPIRE_SHIFT, XCVR_AGC_CTRL_2_AGC_FAST_EXPIRE_WIDTH))
28573 
28574 /*! @brief Set the AGC_FAST_EXPIRE field to a new value. */
28575 #define XCVR_WR_AGC_CTRL_2_AGC_FAST_EXPIRE(base, value) (XCVR_RMW_AGC_CTRL_2(base, XCVR_AGC_CTRL_2_AGC_FAST_EXPIRE_MASK, XCVR_AGC_CTRL_2_AGC_FAST_EXPIRE(value)))
28576 #define XCVR_BWR_AGC_CTRL_2_AGC_FAST_EXPIRE(base, value) (BME_BFI32(&XCVR_AGC_CTRL_2_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_2_AGC_FAST_EXPIRE_SHIFT), XCVR_AGC_CTRL_2_AGC_FAST_EXPIRE_SHIFT, XCVR_AGC_CTRL_2_AGC_FAST_EXPIRE_WIDTH))
28577 /*@}*/
28578 
28579 /*******************************************************************************
28580  * XCVR_AGC_CTRL_3 - AGC Control 3
28581  ******************************************************************************/
28582 
28583 /*!
28584  * @brief XCVR_AGC_CTRL_3 - AGC Control 3 (RW)
28585  *
28586  * Reset value: 0x00000000U
28587  */
28588 /*!
28589  * @name Constants and macros for entire XCVR_AGC_CTRL_3 register
28590  */
28591 /*@{*/
28592 #define XCVR_RD_AGC_CTRL_3(base) (XCVR_AGC_CTRL_3_REG(base))
28593 #define XCVR_WR_AGC_CTRL_3(base, value) (XCVR_AGC_CTRL_3_REG(base) = (value))
28594 #define XCVR_RMW_AGC_CTRL_3(base, mask, value) (XCVR_WR_AGC_CTRL_3(base, (XCVR_RD_AGC_CTRL_3(base) & ~(mask)) | (value)))
28595 #define XCVR_SET_AGC_CTRL_3(base, value) (BME_OR32(&XCVR_AGC_CTRL_3_REG(base), (uint32_t)(value)))
28596 #define XCVR_CLR_AGC_CTRL_3(base, value) (BME_AND32(&XCVR_AGC_CTRL_3_REG(base), (uint32_t)(~(value))))
28597 #define XCVR_TOG_AGC_CTRL_3(base, value) (BME_XOR32(&XCVR_AGC_CTRL_3_REG(base), (uint32_t)(value)))
28598 /*@}*/
28599 
28600 /*
28601  * Constants & macros for individual XCVR_AGC_CTRL_3 bitfields
28602  */
28603 
28604 /*!
28605  * @name Register XCVR_AGC_CTRL_3, field AGC_UNFREEZE_TIME[12:0] (RW)
28606  *
28607  * Time (uS) for AGC to unfreeze (1-8191uS).
28608  */
28609 /*@{*/
28610 /*! @brief Read current value of the XCVR_AGC_CTRL_3_AGC_UNFREEZE_TIME field. */
28611 #define XCVR_RD_AGC_CTRL_3_AGC_UNFREEZE_TIME(base) ((XCVR_AGC_CTRL_3_REG(base) & XCVR_AGC_CTRL_3_AGC_UNFREEZE_TIME_MASK) >> XCVR_AGC_CTRL_3_AGC_UNFREEZE_TIME_SHIFT)
28612 #define XCVR_BRD_AGC_CTRL_3_AGC_UNFREEZE_TIME(base) (BME_UBFX32(&XCVR_AGC_CTRL_3_REG(base), XCVR_AGC_CTRL_3_AGC_UNFREEZE_TIME_SHIFT, XCVR_AGC_CTRL_3_AGC_UNFREEZE_TIME_WIDTH))
28613 
28614 /*! @brief Set the AGC_UNFREEZE_TIME field to a new value. */
28615 #define XCVR_WR_AGC_CTRL_3_AGC_UNFREEZE_TIME(base, value) (XCVR_RMW_AGC_CTRL_3(base, XCVR_AGC_CTRL_3_AGC_UNFREEZE_TIME_MASK, XCVR_AGC_CTRL_3_AGC_UNFREEZE_TIME(value)))
28616 #define XCVR_BWR_AGC_CTRL_3_AGC_UNFREEZE_TIME(base, value) (BME_BFI32(&XCVR_AGC_CTRL_3_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_3_AGC_UNFREEZE_TIME_SHIFT), XCVR_AGC_CTRL_3_AGC_UNFREEZE_TIME_SHIFT, XCVR_AGC_CTRL_3_AGC_UNFREEZE_TIME_WIDTH))
28617 /*@}*/
28618 
28619 /*!
28620  * @name Register XCVR_AGC_CTRL_3, field AGC_PDET_LO_DLY[15:13] (RW)
28621  *
28622  * Time (uS) to wait for pdet low to assert (1-7uS).
28623  */
28624 /*@{*/
28625 /*! @brief Read current value of the XCVR_AGC_CTRL_3_AGC_PDET_LO_DLY field. */
28626 #define XCVR_RD_AGC_CTRL_3_AGC_PDET_LO_DLY(base) ((XCVR_AGC_CTRL_3_REG(base) & XCVR_AGC_CTRL_3_AGC_PDET_LO_DLY_MASK) >> XCVR_AGC_CTRL_3_AGC_PDET_LO_DLY_SHIFT)
28627 #define XCVR_BRD_AGC_CTRL_3_AGC_PDET_LO_DLY(base) (BME_UBFX32(&XCVR_AGC_CTRL_3_REG(base), XCVR_AGC_CTRL_3_AGC_PDET_LO_DLY_SHIFT, XCVR_AGC_CTRL_3_AGC_PDET_LO_DLY_WIDTH))
28628 
28629 /*! @brief Set the AGC_PDET_LO_DLY field to a new value. */
28630 #define XCVR_WR_AGC_CTRL_3_AGC_PDET_LO_DLY(base, value) (XCVR_RMW_AGC_CTRL_3(base, XCVR_AGC_CTRL_3_AGC_PDET_LO_DLY_MASK, XCVR_AGC_CTRL_3_AGC_PDET_LO_DLY(value)))
28631 #define XCVR_BWR_AGC_CTRL_3_AGC_PDET_LO_DLY(base, value) (BME_BFI32(&XCVR_AGC_CTRL_3_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_3_AGC_PDET_LO_DLY_SHIFT), XCVR_AGC_CTRL_3_AGC_PDET_LO_DLY_SHIFT, XCVR_AGC_CTRL_3_AGC_PDET_LO_DLY_WIDTH))
28632 /*@}*/
28633 
28634 /*!
28635  * @name Register XCVR_AGC_CTRL_3, field AGC_RSSI_DELT_H2S[22:16] (RW)
28636  *
28637  * RSSI delta that causes hold to slow transition.
28638  */
28639 /*@{*/
28640 /*! @brief Read current value of the XCVR_AGC_CTRL_3_AGC_RSSI_DELT_H2S field. */
28641 #define XCVR_RD_AGC_CTRL_3_AGC_RSSI_DELT_H2S(base) ((XCVR_AGC_CTRL_3_REG(base) & XCVR_AGC_CTRL_3_AGC_RSSI_DELT_H2S_MASK) >> XCVR_AGC_CTRL_3_AGC_RSSI_DELT_H2S_SHIFT)
28642 #define XCVR_BRD_AGC_CTRL_3_AGC_RSSI_DELT_H2S(base) (BME_UBFX32(&XCVR_AGC_CTRL_3_REG(base), XCVR_AGC_CTRL_3_AGC_RSSI_DELT_H2S_SHIFT, XCVR_AGC_CTRL_3_AGC_RSSI_DELT_H2S_WIDTH))
28643 
28644 /*! @brief Set the AGC_RSSI_DELT_H2S field to a new value. */
28645 #define XCVR_WR_AGC_CTRL_3_AGC_RSSI_DELT_H2S(base, value) (XCVR_RMW_AGC_CTRL_3(base, XCVR_AGC_CTRL_3_AGC_RSSI_DELT_H2S_MASK, XCVR_AGC_CTRL_3_AGC_RSSI_DELT_H2S(value)))
28646 #define XCVR_BWR_AGC_CTRL_3_AGC_RSSI_DELT_H2S(base, value) (BME_BFI32(&XCVR_AGC_CTRL_3_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_3_AGC_RSSI_DELT_H2S_SHIFT), XCVR_AGC_CTRL_3_AGC_RSSI_DELT_H2S_SHIFT, XCVR_AGC_CTRL_3_AGC_RSSI_DELT_H2S_WIDTH))
28647 /*@}*/
28648 
28649 /*!
28650  * @name Register XCVR_AGC_CTRL_3, field AGC_H2S_STEP_SZ[27:23] (RW)
28651  *
28652  * Step size for hold to slow jump.
28653  */
28654 /*@{*/
28655 /*! @brief Read current value of the XCVR_AGC_CTRL_3_AGC_H2S_STEP_SZ field. */
28656 #define XCVR_RD_AGC_CTRL_3_AGC_H2S_STEP_SZ(base) ((XCVR_AGC_CTRL_3_REG(base) & XCVR_AGC_CTRL_3_AGC_H2S_STEP_SZ_MASK) >> XCVR_AGC_CTRL_3_AGC_H2S_STEP_SZ_SHIFT)
28657 #define XCVR_BRD_AGC_CTRL_3_AGC_H2S_STEP_SZ(base) (BME_UBFX32(&XCVR_AGC_CTRL_3_REG(base), XCVR_AGC_CTRL_3_AGC_H2S_STEP_SZ_SHIFT, XCVR_AGC_CTRL_3_AGC_H2S_STEP_SZ_WIDTH))
28658 
28659 /*! @brief Set the AGC_H2S_STEP_SZ field to a new value. */
28660 #define XCVR_WR_AGC_CTRL_3_AGC_H2S_STEP_SZ(base, value) (XCVR_RMW_AGC_CTRL_3(base, XCVR_AGC_CTRL_3_AGC_H2S_STEP_SZ_MASK, XCVR_AGC_CTRL_3_AGC_H2S_STEP_SZ(value)))
28661 #define XCVR_BWR_AGC_CTRL_3_AGC_H2S_STEP_SZ(base, value) (BME_BFI32(&XCVR_AGC_CTRL_3_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_3_AGC_H2S_STEP_SZ_SHIFT), XCVR_AGC_CTRL_3_AGC_H2S_STEP_SZ_SHIFT, XCVR_AGC_CTRL_3_AGC_H2S_STEP_SZ_WIDTH))
28662 /*@}*/
28663 
28664 /*!
28665  * @name Register XCVR_AGC_CTRL_3, field AGC_UP_STEP_SZ[31:28] (RW)
28666  *
28667  * Number of table steps for upward step
28668  */
28669 /*@{*/
28670 /*! @brief Read current value of the XCVR_AGC_CTRL_3_AGC_UP_STEP_SZ field. */
28671 #define XCVR_RD_AGC_CTRL_3_AGC_UP_STEP_SZ(base) ((XCVR_AGC_CTRL_3_REG(base) & XCVR_AGC_CTRL_3_AGC_UP_STEP_SZ_MASK) >> XCVR_AGC_CTRL_3_AGC_UP_STEP_SZ_SHIFT)
28672 #define XCVR_BRD_AGC_CTRL_3_AGC_UP_STEP_SZ(base) (BME_UBFX32(&XCVR_AGC_CTRL_3_REG(base), XCVR_AGC_CTRL_3_AGC_UP_STEP_SZ_SHIFT, XCVR_AGC_CTRL_3_AGC_UP_STEP_SZ_WIDTH))
28673 
28674 /*! @brief Set the AGC_UP_STEP_SZ field to a new value. */
28675 #define XCVR_WR_AGC_CTRL_3_AGC_UP_STEP_SZ(base, value) (XCVR_RMW_AGC_CTRL_3(base, XCVR_AGC_CTRL_3_AGC_UP_STEP_SZ_MASK, XCVR_AGC_CTRL_3_AGC_UP_STEP_SZ(value)))
28676 #define XCVR_BWR_AGC_CTRL_3_AGC_UP_STEP_SZ(base, value) (BME_BFI32(&XCVR_AGC_CTRL_3_REG(base), ((uint32_t)(value) << XCVR_AGC_CTRL_3_AGC_UP_STEP_SZ_SHIFT), XCVR_AGC_CTRL_3_AGC_UP_STEP_SZ_SHIFT, XCVR_AGC_CTRL_3_AGC_UP_STEP_SZ_WIDTH))
28677 /*@}*/
28678 
28679 /*******************************************************************************
28680  * XCVR_AGC_STAT - AGC Status
28681  ******************************************************************************/
28682 
28683 /*!
28684  * @brief XCVR_AGC_STAT - AGC Status (RO)
28685  *
28686  * Reset value: 0x00000000U
28687  */
28688 /*!
28689  * @name Constants and macros for entire XCVR_AGC_STAT register
28690  */
28691 /*@{*/
28692 #define XCVR_RD_AGC_STAT(base)   (XCVR_AGC_STAT_REG(base))
28693 /*@}*/
28694 
28695 /*
28696  * Constants & macros for individual XCVR_AGC_STAT bitfields
28697  */
28698 
28699 /*!
28700  * @name Register XCVR_AGC_STAT, field BBF_PDET_LO_STAT[0] (RO)
28701  *
28702  * Status of BBF peak detector LO flag (1=set)
28703  */
28704 /*@{*/
28705 /*! @brief Read current value of the XCVR_AGC_STAT_BBF_PDET_LO_STAT field. */
28706 #define XCVR_RD_AGC_STAT_BBF_PDET_LO_STAT(base) ((XCVR_AGC_STAT_REG(base) & XCVR_AGC_STAT_BBF_PDET_LO_STAT_MASK) >> XCVR_AGC_STAT_BBF_PDET_LO_STAT_SHIFT)
28707 #define XCVR_BRD_AGC_STAT_BBF_PDET_LO_STAT(base) (BME_UBFX32(&XCVR_AGC_STAT_REG(base), XCVR_AGC_STAT_BBF_PDET_LO_STAT_SHIFT, XCVR_AGC_STAT_BBF_PDET_LO_STAT_WIDTH))
28708 /*@}*/
28709 
28710 /*!
28711  * @name Register XCVR_AGC_STAT, field BBF_PDET_HI_STAT[1] (RO)
28712  *
28713  * Status of BBF peak detector HI flag (1=set)
28714  */
28715 /*@{*/
28716 /*! @brief Read current value of the XCVR_AGC_STAT_BBF_PDET_HI_STAT field. */
28717 #define XCVR_RD_AGC_STAT_BBF_PDET_HI_STAT(base) ((XCVR_AGC_STAT_REG(base) & XCVR_AGC_STAT_BBF_PDET_HI_STAT_MASK) >> XCVR_AGC_STAT_BBF_PDET_HI_STAT_SHIFT)
28718 #define XCVR_BRD_AGC_STAT_BBF_PDET_HI_STAT(base) (BME_UBFX32(&XCVR_AGC_STAT_REG(base), XCVR_AGC_STAT_BBF_PDET_HI_STAT_SHIFT, XCVR_AGC_STAT_BBF_PDET_HI_STAT_WIDTH))
28719 /*@}*/
28720 
28721 /*!
28722  * @name Register XCVR_AGC_STAT, field TZA_PDET_LO_STAT[2] (RO)
28723  *
28724  * Status of TZA peak detector LO flag (1=set)
28725  */
28726 /*@{*/
28727 /*! @brief Read current value of the XCVR_AGC_STAT_TZA_PDET_LO_STAT field. */
28728 #define XCVR_RD_AGC_STAT_TZA_PDET_LO_STAT(base) ((XCVR_AGC_STAT_REG(base) & XCVR_AGC_STAT_TZA_PDET_LO_STAT_MASK) >> XCVR_AGC_STAT_TZA_PDET_LO_STAT_SHIFT)
28729 #define XCVR_BRD_AGC_STAT_TZA_PDET_LO_STAT(base) (BME_UBFX32(&XCVR_AGC_STAT_REG(base), XCVR_AGC_STAT_TZA_PDET_LO_STAT_SHIFT, XCVR_AGC_STAT_TZA_PDET_LO_STAT_WIDTH))
28730 /*@}*/
28731 
28732 /*!
28733  * @name Register XCVR_AGC_STAT, field TZA_PDET_HI_STAT[3] (RO)
28734  *
28735  * Status of TZA peak detector HI flag (1=set)
28736  */
28737 /*@{*/
28738 /*! @brief Read current value of the XCVR_AGC_STAT_TZA_PDET_HI_STAT field. */
28739 #define XCVR_RD_AGC_STAT_TZA_PDET_HI_STAT(base) ((XCVR_AGC_STAT_REG(base) & XCVR_AGC_STAT_TZA_PDET_HI_STAT_MASK) >> XCVR_AGC_STAT_TZA_PDET_HI_STAT_SHIFT)
28740 #define XCVR_BRD_AGC_STAT_TZA_PDET_HI_STAT(base) (BME_UBFX32(&XCVR_AGC_STAT_REG(base), XCVR_AGC_STAT_TZA_PDET_HI_STAT_SHIFT, XCVR_AGC_STAT_TZA_PDET_HI_STAT_WIDTH))
28741 /*@}*/
28742 
28743 /*!
28744  * @name Register XCVR_AGC_STAT, field CURR_AGC_IDX[8:4] (RO)
28745  *
28746  * Current AGC gain table index
28747  */
28748 /*@{*/
28749 /*! @brief Read current value of the XCVR_AGC_STAT_CURR_AGC_IDX field. */
28750 #define XCVR_RD_AGC_STAT_CURR_AGC_IDX(base) ((XCVR_AGC_STAT_REG(base) & XCVR_AGC_STAT_CURR_AGC_IDX_MASK) >> XCVR_AGC_STAT_CURR_AGC_IDX_SHIFT)
28751 #define XCVR_BRD_AGC_STAT_CURR_AGC_IDX(base) (BME_UBFX32(&XCVR_AGC_STAT_REG(base), XCVR_AGC_STAT_CURR_AGC_IDX_SHIFT, XCVR_AGC_STAT_CURR_AGC_IDX_WIDTH))
28752 /*@}*/
28753 
28754 /*!
28755  * @name Register XCVR_AGC_STAT, field AGC_FROZEN[9] (RO)
28756  *
28757  * Status of AGC freeze.
28758  *
28759  * Values:
28760  * - 0b0 - AGC is not frozen.
28761  * - 0b1 - AGC is frozen.
28762  */
28763 /*@{*/
28764 /*! @brief Read current value of the XCVR_AGC_STAT_AGC_FROZEN field. */
28765 #define XCVR_RD_AGC_STAT_AGC_FROZEN(base) ((XCVR_AGC_STAT_REG(base) & XCVR_AGC_STAT_AGC_FROZEN_MASK) >> XCVR_AGC_STAT_AGC_FROZEN_SHIFT)
28766 #define XCVR_BRD_AGC_STAT_AGC_FROZEN(base) (BME_UBFX32(&XCVR_AGC_STAT_REG(base), XCVR_AGC_STAT_AGC_FROZEN_SHIFT, XCVR_AGC_STAT_AGC_FROZEN_WIDTH))
28767 /*@}*/
28768 
28769 /*!
28770  * @name Register XCVR_AGC_STAT, field RSSI_ADC_RAW[23:16] (RO)
28771  *
28772  * Reading of ADC rssi (before adjustments)
28773  */
28774 /*@{*/
28775 /*! @brief Read current value of the XCVR_AGC_STAT_RSSI_ADC_RAW field. */
28776 #define XCVR_RD_AGC_STAT_RSSI_ADC_RAW(base) ((XCVR_AGC_STAT_REG(base) & XCVR_AGC_STAT_RSSI_ADC_RAW_MASK) >> XCVR_AGC_STAT_RSSI_ADC_RAW_SHIFT)
28777 #define XCVR_BRD_AGC_STAT_RSSI_ADC_RAW(base) (BME_UBFX32(&XCVR_AGC_STAT_REG(base), XCVR_AGC_STAT_RSSI_ADC_RAW_SHIFT, XCVR_AGC_STAT_RSSI_ADC_RAW_WIDTH))
28778 /*@}*/
28779 
28780 /*******************************************************************************
28781  * XCVR_RSSI_CTRL_0 - RSSI Control 0
28782  ******************************************************************************/
28783 
28784 /*!
28785  * @brief XCVR_RSSI_CTRL_0 - RSSI Control 0 (RW)
28786  *
28787  * Reset value: 0x00000000U
28788  */
28789 /*!
28790  * @name Constants and macros for entire XCVR_RSSI_CTRL_0 register
28791  */
28792 /*@{*/
28793 #define XCVR_RD_RSSI_CTRL_0(base) (XCVR_RSSI_CTRL_0_REG(base))
28794 #define XCVR_WR_RSSI_CTRL_0(base, value) (XCVR_RSSI_CTRL_0_REG(base) = (value))
28795 #define XCVR_RMW_RSSI_CTRL_0(base, mask, value) (XCVR_WR_RSSI_CTRL_0(base, (XCVR_RD_RSSI_CTRL_0(base) & ~(mask)) | (value)))
28796 #define XCVR_SET_RSSI_CTRL_0(base, value) (BME_OR32(&XCVR_RSSI_CTRL_0_REG(base), (uint32_t)(value)))
28797 #define XCVR_CLR_RSSI_CTRL_0(base, value) (BME_AND32(&XCVR_RSSI_CTRL_0_REG(base), (uint32_t)(~(value))))
28798 #define XCVR_TOG_RSSI_CTRL_0(base, value) (BME_XOR32(&XCVR_RSSI_CTRL_0_REG(base), (uint32_t)(value)))
28799 /*@}*/
28800 
28801 /*
28802  * Constants & macros for individual XCVR_RSSI_CTRL_0 bitfields
28803  */
28804 
28805 /*!
28806  * @name Register XCVR_RSSI_CTRL_0, field RSSI_USE_VALS[0] (RW)
28807  *
28808  * Enable use of TCA and BBF gain values programmed in registers for calculation.
28809  */
28810 /*@{*/
28811 /*! @brief Read current value of the XCVR_RSSI_CTRL_0_RSSI_USE_VALS field. */
28812 #define XCVR_RD_RSSI_CTRL_0_RSSI_USE_VALS(base) ((XCVR_RSSI_CTRL_0_REG(base) & XCVR_RSSI_CTRL_0_RSSI_USE_VALS_MASK) >> XCVR_RSSI_CTRL_0_RSSI_USE_VALS_SHIFT)
28813 #define XCVR_BRD_RSSI_CTRL_0_RSSI_USE_VALS(base) (BME_UBFX32(&XCVR_RSSI_CTRL_0_REG(base), XCVR_RSSI_CTRL_0_RSSI_USE_VALS_SHIFT, XCVR_RSSI_CTRL_0_RSSI_USE_VALS_WIDTH))
28814 
28815 /*! @brief Set the RSSI_USE_VALS field to a new value. */
28816 #define XCVR_WR_RSSI_CTRL_0_RSSI_USE_VALS(base, value) (XCVR_RMW_RSSI_CTRL_0(base, XCVR_RSSI_CTRL_0_RSSI_USE_VALS_MASK, XCVR_RSSI_CTRL_0_RSSI_USE_VALS(value)))
28817 #define XCVR_BWR_RSSI_CTRL_0_RSSI_USE_VALS(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_RSSI_CTRL_0_RSSI_USE_VALS_SHIFT), XCVR_RSSI_CTRL_0_RSSI_USE_VALS_SHIFT, XCVR_RSSI_CTRL_0_RSSI_USE_VALS_WIDTH))
28818 /*@}*/
28819 
28820 /*!
28821  * @name Register XCVR_RSSI_CTRL_0, field RSSI_HOLD_SRC[2:1] (RW)
28822  *
28823  * Select trigger source for entering freezing RSSI measurement.
28824  *
28825  * Values:
28826  * - 0b00 - BTLE Preamble Detect
28827  * - 0b01 - Zigbee Preamble Detect
28828  */
28829 /*@{*/
28830 /*! @brief Read current value of the XCVR_RSSI_CTRL_0_RSSI_HOLD_SRC field. */
28831 #define XCVR_RD_RSSI_CTRL_0_RSSI_HOLD_SRC(base) ((XCVR_RSSI_CTRL_0_REG(base) & XCVR_RSSI_CTRL_0_RSSI_HOLD_SRC_MASK) >> XCVR_RSSI_CTRL_0_RSSI_HOLD_SRC_SHIFT)
28832 #define XCVR_BRD_RSSI_CTRL_0_RSSI_HOLD_SRC(base) (BME_UBFX32(&XCVR_RSSI_CTRL_0_REG(base), XCVR_RSSI_CTRL_0_RSSI_HOLD_SRC_SHIFT, XCVR_RSSI_CTRL_0_RSSI_HOLD_SRC_WIDTH))
28833 
28834 /*! @brief Set the RSSI_HOLD_SRC field to a new value. */
28835 #define XCVR_WR_RSSI_CTRL_0_RSSI_HOLD_SRC(base, value) (XCVR_RMW_RSSI_CTRL_0(base, XCVR_RSSI_CTRL_0_RSSI_HOLD_SRC_MASK, XCVR_RSSI_CTRL_0_RSSI_HOLD_SRC(value)))
28836 #define XCVR_BWR_RSSI_CTRL_0_RSSI_HOLD_SRC(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_RSSI_CTRL_0_RSSI_HOLD_SRC_SHIFT), XCVR_RSSI_CTRL_0_RSSI_HOLD_SRC_SHIFT, XCVR_RSSI_CTRL_0_RSSI_HOLD_SRC_WIDTH))
28837 /*@}*/
28838 
28839 /*!
28840  * @name Register XCVR_RSSI_CTRL_0, field RSSI_HOLD_EN[3] (RW)
28841  *
28842  * Enable RSSI to freeze after hold criterion met. RSSI will still be briefly
28843  * held when a gain change occurs.
28844  */
28845 /*@{*/
28846 /*! @brief Read current value of the XCVR_RSSI_CTRL_0_RSSI_HOLD_EN field. */
28847 #define XCVR_RD_RSSI_CTRL_0_RSSI_HOLD_EN(base) ((XCVR_RSSI_CTRL_0_REG(base) & XCVR_RSSI_CTRL_0_RSSI_HOLD_EN_MASK) >> XCVR_RSSI_CTRL_0_RSSI_HOLD_EN_SHIFT)
28848 #define XCVR_BRD_RSSI_CTRL_0_RSSI_HOLD_EN(base) (BME_UBFX32(&XCVR_RSSI_CTRL_0_REG(base), XCVR_RSSI_CTRL_0_RSSI_HOLD_EN_SHIFT, XCVR_RSSI_CTRL_0_RSSI_HOLD_EN_WIDTH))
28849 
28850 /*! @brief Set the RSSI_HOLD_EN field to a new value. */
28851 #define XCVR_WR_RSSI_CTRL_0_RSSI_HOLD_EN(base, value) (XCVR_RMW_RSSI_CTRL_0(base, XCVR_RSSI_CTRL_0_RSSI_HOLD_EN_MASK, XCVR_RSSI_CTRL_0_RSSI_HOLD_EN(value)))
28852 #define XCVR_BWR_RSSI_CTRL_0_RSSI_HOLD_EN(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_RSSI_CTRL_0_RSSI_HOLD_EN_SHIFT), XCVR_RSSI_CTRL_0_RSSI_HOLD_EN_SHIFT, XCVR_RSSI_CTRL_0_RSSI_HOLD_EN_WIDTH))
28853 /*@}*/
28854 
28855 /*!
28856  * @name Register XCVR_RSSI_CTRL_0, field RSSI_DEC_EN[4] (RW)
28857  *
28858  * Enable RSSI 4x decimation stage.
28859  */
28860 /*@{*/
28861 /*! @brief Read current value of the XCVR_RSSI_CTRL_0_RSSI_DEC_EN field. */
28862 #define XCVR_RD_RSSI_CTRL_0_RSSI_DEC_EN(base) ((XCVR_RSSI_CTRL_0_REG(base) & XCVR_RSSI_CTRL_0_RSSI_DEC_EN_MASK) >> XCVR_RSSI_CTRL_0_RSSI_DEC_EN_SHIFT)
28863 #define XCVR_BRD_RSSI_CTRL_0_RSSI_DEC_EN(base) (BME_UBFX32(&XCVR_RSSI_CTRL_0_REG(base), XCVR_RSSI_CTRL_0_RSSI_DEC_EN_SHIFT, XCVR_RSSI_CTRL_0_RSSI_DEC_EN_WIDTH))
28864 
28865 /*! @brief Set the RSSI_DEC_EN field to a new value. */
28866 #define XCVR_WR_RSSI_CTRL_0_RSSI_DEC_EN(base, value) (XCVR_RMW_RSSI_CTRL_0(base, XCVR_RSSI_CTRL_0_RSSI_DEC_EN_MASK, XCVR_RSSI_CTRL_0_RSSI_DEC_EN(value)))
28867 #define XCVR_BWR_RSSI_CTRL_0_RSSI_DEC_EN(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_RSSI_CTRL_0_RSSI_DEC_EN_SHIFT), XCVR_RSSI_CTRL_0_RSSI_DEC_EN_SHIFT, XCVR_RSSI_CTRL_0_RSSI_DEC_EN_WIDTH))
28868 /*@}*/
28869 
28870 /*!
28871  * @name Register XCVR_RSSI_CTRL_0, field RSSI_IIR_CW_WEIGHT[6:5] (RW)
28872  *
28873  * IIR filter weight for RSSI filtering of a CW input.
28874  *
28875  * Values:
28876  * - 0b00 - Bypass
28877  * - 0b01 - 1/8
28878  */
28879 /*@{*/
28880 /*! @brief Read current value of the XCVR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT field. */
28881 #define XCVR_RD_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(base) ((XCVR_RSSI_CTRL_0_REG(base) & XCVR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK) >> XCVR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_SHIFT)
28882 #define XCVR_BRD_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(base) (BME_UBFX32(&XCVR_RSSI_CTRL_0_REG(base), XCVR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_SHIFT, XCVR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_WIDTH))
28883 
28884 /*! @brief Set the RSSI_IIR_CW_WEIGHT field to a new value. */
28885 #define XCVR_WR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(base, value) (XCVR_RMW_RSSI_CTRL_0(base, XCVR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_MASK, XCVR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(value)))
28886 #define XCVR_BWR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_SHIFT), XCVR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_SHIFT, XCVR_RSSI_CTRL_0_RSSI_IIR_CW_WEIGHT_WIDTH))
28887 /*@}*/
28888 
28889 /*!
28890  * @name Register XCVR_RSSI_CTRL_0, field RSSI_IIR_WEIGHT[19:16] (RW)
28891  *
28892  * IIR filter weight for RSSI filtering.
28893  *
28894  * Values:
28895  * - 0b0000 - Bypass
28896  * - 0b0001 - 1/2
28897  */
28898 /*@{*/
28899 /*! @brief Read current value of the XCVR_RSSI_CTRL_0_RSSI_IIR_WEIGHT field. */
28900 #define XCVR_RD_RSSI_CTRL_0_RSSI_IIR_WEIGHT(base) ((XCVR_RSSI_CTRL_0_REG(base) & XCVR_RSSI_CTRL_0_RSSI_IIR_WEIGHT_MASK) >> XCVR_RSSI_CTRL_0_RSSI_IIR_WEIGHT_SHIFT)
28901 #define XCVR_BRD_RSSI_CTRL_0_RSSI_IIR_WEIGHT(base) (BME_UBFX32(&XCVR_RSSI_CTRL_0_REG(base), XCVR_RSSI_CTRL_0_RSSI_IIR_WEIGHT_SHIFT, XCVR_RSSI_CTRL_0_RSSI_IIR_WEIGHT_WIDTH))
28902 
28903 /*! @brief Set the RSSI_IIR_WEIGHT field to a new value. */
28904 #define XCVR_WR_RSSI_CTRL_0_RSSI_IIR_WEIGHT(base, value) (XCVR_RMW_RSSI_CTRL_0(base, XCVR_RSSI_CTRL_0_RSSI_IIR_WEIGHT_MASK, XCVR_RSSI_CTRL_0_RSSI_IIR_WEIGHT(value)))
28905 #define XCVR_BWR_RSSI_CTRL_0_RSSI_IIR_WEIGHT(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_RSSI_CTRL_0_RSSI_IIR_WEIGHT_SHIFT), XCVR_RSSI_CTRL_0_RSSI_IIR_WEIGHT_SHIFT, XCVR_RSSI_CTRL_0_RSSI_IIR_WEIGHT_WIDTH))
28906 /*@}*/
28907 
28908 /*!
28909  * @name Register XCVR_RSSI_CTRL_0, field RSSI_ADJ[31:24] (RW)
28910  *
28911  * RSSI calculation adjustment (8-bit signed 1/4 dB).
28912  */
28913 /*@{*/
28914 /*! @brief Read current value of the XCVR_RSSI_CTRL_0_RSSI_ADJ field. */
28915 #define XCVR_RD_RSSI_CTRL_0_RSSI_ADJ(base) ((XCVR_RSSI_CTRL_0_REG(base) & XCVR_RSSI_CTRL_0_RSSI_ADJ_MASK) >> XCVR_RSSI_CTRL_0_RSSI_ADJ_SHIFT)
28916 #define XCVR_BRD_RSSI_CTRL_0_RSSI_ADJ(base) (BME_UBFX32(&XCVR_RSSI_CTRL_0_REG(base), XCVR_RSSI_CTRL_0_RSSI_ADJ_SHIFT, XCVR_RSSI_CTRL_0_RSSI_ADJ_WIDTH))
28917 
28918 /*! @brief Set the RSSI_ADJ field to a new value. */
28919 #define XCVR_WR_RSSI_CTRL_0_RSSI_ADJ(base, value) (XCVR_RMW_RSSI_CTRL_0(base, XCVR_RSSI_CTRL_0_RSSI_ADJ_MASK, XCVR_RSSI_CTRL_0_RSSI_ADJ(value)))
28920 #define XCVR_BWR_RSSI_CTRL_0_RSSI_ADJ(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_RSSI_CTRL_0_RSSI_ADJ_SHIFT), XCVR_RSSI_CTRL_0_RSSI_ADJ_SHIFT, XCVR_RSSI_CTRL_0_RSSI_ADJ_WIDTH))
28921 /*@}*/
28922 
28923 /*******************************************************************************
28924  * XCVR_RSSI_CTRL_1 - RSSI Control 1
28925  ******************************************************************************/
28926 
28927 /*!
28928  * @brief XCVR_RSSI_CTRL_1 - RSSI Control 1 (RW)
28929  *
28930  * Reset value: 0x00000000U
28931  */
28932 /*!
28933  * @name Constants and macros for entire XCVR_RSSI_CTRL_1 register
28934  */
28935 /*@{*/
28936 #define XCVR_RD_RSSI_CTRL_1(base) (XCVR_RSSI_CTRL_1_REG(base))
28937 #define XCVR_WR_RSSI_CTRL_1(base, value) (XCVR_RSSI_CTRL_1_REG(base) = (value))
28938 #define XCVR_RMW_RSSI_CTRL_1(base, mask, value) (XCVR_WR_RSSI_CTRL_1(base, (XCVR_RD_RSSI_CTRL_1(base) & ~(mask)) | (value)))
28939 #define XCVR_SET_RSSI_CTRL_1(base, value) (BME_OR32(&XCVR_RSSI_CTRL_1_REG(base), (uint32_t)(value)))
28940 #define XCVR_CLR_RSSI_CTRL_1(base, value) (BME_AND32(&XCVR_RSSI_CTRL_1_REG(base), (uint32_t)(~(value))))
28941 #define XCVR_TOG_RSSI_CTRL_1(base, value) (BME_XOR32(&XCVR_RSSI_CTRL_1_REG(base), (uint32_t)(value)))
28942 /*@}*/
28943 
28944 /*
28945  * Constants & macros for individual XCVR_RSSI_CTRL_1 bitfields
28946  */
28947 
28948 /*!
28949  * @name Register XCVR_RSSI_CTRL_1, field RSSI_ED_THRESH0[7:0] (RW)
28950  *
28951  * Threshold for setting energy detect 0 to scanner.
28952  */
28953 /*@{*/
28954 /*! @brief Read current value of the XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0 field. */
28955 #define XCVR_RD_RSSI_CTRL_1_RSSI_ED_THRESH0(base) ((XCVR_RSSI_CTRL_1_REG(base) & XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_MASK) >> XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_SHIFT)
28956 #define XCVR_BRD_RSSI_CTRL_1_RSSI_ED_THRESH0(base) (BME_UBFX32(&XCVR_RSSI_CTRL_1_REG(base), XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_SHIFT, XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_WIDTH))
28957 
28958 /*! @brief Set the RSSI_ED_THRESH0 field to a new value. */
28959 #define XCVR_WR_RSSI_CTRL_1_RSSI_ED_THRESH0(base, value) (XCVR_RMW_RSSI_CTRL_1(base, XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_MASK, XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0(value)))
28960 #define XCVR_BWR_RSSI_CTRL_1_RSSI_ED_THRESH0(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_1_REG(base), ((uint32_t)(value) << XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_SHIFT), XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_SHIFT, XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_WIDTH))
28961 /*@}*/
28962 
28963 /*!
28964  * @name Register XCVR_RSSI_CTRL_1, field RSSI_ED_THRESH1[15:8] (RW)
28965  *
28966  * Threshold for setting energy detect 1 to scanner.
28967  */
28968 /*@{*/
28969 /*! @brief Read current value of the XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1 field. */
28970 #define XCVR_RD_RSSI_CTRL_1_RSSI_ED_THRESH1(base) ((XCVR_RSSI_CTRL_1_REG(base) & XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_MASK) >> XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_SHIFT)
28971 #define XCVR_BRD_RSSI_CTRL_1_RSSI_ED_THRESH1(base) (BME_UBFX32(&XCVR_RSSI_CTRL_1_REG(base), XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_SHIFT, XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_WIDTH))
28972 
28973 /*! @brief Set the RSSI_ED_THRESH1 field to a new value. */
28974 #define XCVR_WR_RSSI_CTRL_1_RSSI_ED_THRESH1(base, value) (XCVR_RMW_RSSI_CTRL_1(base, XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_MASK, XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1(value)))
28975 #define XCVR_BWR_RSSI_CTRL_1_RSSI_ED_THRESH1(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_1_REG(base), ((uint32_t)(value) << XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_SHIFT), XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_SHIFT, XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_WIDTH))
28976 /*@}*/
28977 
28978 /*!
28979  * @name Register XCVR_RSSI_CTRL_1, field RSSI_ED_THRESH0_H[19:16] (RW)
28980  *
28981  * ED hysteresis window size.
28982  */
28983 /*@{*/
28984 /*! @brief Read current value of the XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_H field. */
28985 #define XCVR_RD_RSSI_CTRL_1_RSSI_ED_THRESH0_H(base) ((XCVR_RSSI_CTRL_1_REG(base) & XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_H_MASK) >> XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_H_SHIFT)
28986 #define XCVR_BRD_RSSI_CTRL_1_RSSI_ED_THRESH0_H(base) (BME_UBFX32(&XCVR_RSSI_CTRL_1_REG(base), XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_H_SHIFT, XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_H_WIDTH))
28987 
28988 /*! @brief Set the RSSI_ED_THRESH0_H field to a new value. */
28989 #define XCVR_WR_RSSI_CTRL_1_RSSI_ED_THRESH0_H(base, value) (XCVR_RMW_RSSI_CTRL_1(base, XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_H_MASK, XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_H(value)))
28990 #define XCVR_BWR_RSSI_CTRL_1_RSSI_ED_THRESH0_H(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_1_REG(base), ((uint32_t)(value) << XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_H_SHIFT), XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_H_SHIFT, XCVR_RSSI_CTRL_1_RSSI_ED_THRESH0_H_WIDTH))
28991 /*@}*/
28992 
28993 /*!
28994  * @name Register XCVR_RSSI_CTRL_1, field RSSI_ED_THRESH1_H[23:20] (RW)
28995  *
28996  * ED hysteresis window size.
28997  */
28998 /*@{*/
28999 /*! @brief Read current value of the XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_H field. */
29000 #define XCVR_RD_RSSI_CTRL_1_RSSI_ED_THRESH1_H(base) ((XCVR_RSSI_CTRL_1_REG(base) & XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_H_MASK) >> XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_H_SHIFT)
29001 #define XCVR_BRD_RSSI_CTRL_1_RSSI_ED_THRESH1_H(base) (BME_UBFX32(&XCVR_RSSI_CTRL_1_REG(base), XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_H_SHIFT, XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_H_WIDTH))
29002 
29003 /*! @brief Set the RSSI_ED_THRESH1_H field to a new value. */
29004 #define XCVR_WR_RSSI_CTRL_1_RSSI_ED_THRESH1_H(base, value) (XCVR_RMW_RSSI_CTRL_1(base, XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_H_MASK, XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_H(value)))
29005 #define XCVR_BWR_RSSI_CTRL_1_RSSI_ED_THRESH1_H(base, value) (BME_BFI32(&XCVR_RSSI_CTRL_1_REG(base), ((uint32_t)(value) << XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_H_SHIFT), XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_H_SHIFT, XCVR_RSSI_CTRL_1_RSSI_ED_THRESH1_H_WIDTH))
29006 /*@}*/
29007 
29008 /*!
29009  * @name Register XCVR_RSSI_CTRL_1, field RSSI_OUT[31:24] (RO)
29010  *
29011  * RSSI output (8-bit signed).
29012  */
29013 /*@{*/
29014 /*! @brief Read current value of the XCVR_RSSI_CTRL_1_RSSI_OUT field. */
29015 #define XCVR_RD_RSSI_CTRL_1_RSSI_OUT(base) ((XCVR_RSSI_CTRL_1_REG(base) & XCVR_RSSI_CTRL_1_RSSI_OUT_MASK) >> XCVR_RSSI_CTRL_1_RSSI_OUT_SHIFT)
29016 #define XCVR_BRD_RSSI_CTRL_1_RSSI_OUT(base) (BME_UBFX32(&XCVR_RSSI_CTRL_1_REG(base), XCVR_RSSI_CTRL_1_RSSI_OUT_SHIFT, XCVR_RSSI_CTRL_1_RSSI_OUT_WIDTH))
29017 /*@}*/
29018 
29019 /*******************************************************************************
29020  * XCVR_DCOC_CTRL_0 - DCOC Control 0
29021  ******************************************************************************/
29022 
29023 /*!
29024  * @brief XCVR_DCOC_CTRL_0 - DCOC Control 0 (RW)
29025  *
29026  * Reset value: 0x00000000U
29027  */
29028 /*!
29029  * @name Constants and macros for entire XCVR_DCOC_CTRL_0 register
29030  */
29031 /*@{*/
29032 #define XCVR_RD_DCOC_CTRL_0(base) (XCVR_DCOC_CTRL_0_REG(base))
29033 #define XCVR_WR_DCOC_CTRL_0(base, value) (XCVR_DCOC_CTRL_0_REG(base) = (value))
29034 #define XCVR_RMW_DCOC_CTRL_0(base, mask, value) (XCVR_WR_DCOC_CTRL_0(base, (XCVR_RD_DCOC_CTRL_0(base) & ~(mask)) | (value)))
29035 #define XCVR_SET_DCOC_CTRL_0(base, value) (BME_OR32(&XCVR_DCOC_CTRL_0_REG(base), (uint32_t)(value)))
29036 #define XCVR_CLR_DCOC_CTRL_0(base, value) (BME_AND32(&XCVR_DCOC_CTRL_0_REG(base), (uint32_t)(~(value))))
29037 #define XCVR_TOG_DCOC_CTRL_0(base, value) (BME_XOR32(&XCVR_DCOC_CTRL_0_REG(base), (uint32_t)(value)))
29038 /*@}*/
29039 
29040 /*
29041  * Constants & macros for individual XCVR_DCOC_CTRL_0 bitfields
29042  */
29043 
29044 /*!
29045  * @name Register XCVR_DCOC_CTRL_0, field DCOC_MAN[1] (RW)
29046  *
29047  * If the manual override bit is set, it forces the DCOC to use the DAC and
29048  * digital correction values from registers XCVR_DCOC_CTRL_3 and XCVR_DCOC_CTRL_4,
29049  * respectively.
29050  */
29051 /*@{*/
29052 /*! @brief Read current value of the XCVR_DCOC_CTRL_0_DCOC_MAN field. */
29053 #define XCVR_RD_DCOC_CTRL_0_DCOC_MAN(base) ((XCVR_DCOC_CTRL_0_REG(base) & XCVR_DCOC_CTRL_0_DCOC_MAN_MASK) >> XCVR_DCOC_CTRL_0_DCOC_MAN_SHIFT)
29054 #define XCVR_BRD_DCOC_CTRL_0_DCOC_MAN(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCVR_DCOC_CTRL_0_DCOC_MAN_SHIFT, XCVR_DCOC_CTRL_0_DCOC_MAN_WIDTH))
29055 
29056 /*! @brief Set the DCOC_MAN field to a new value. */
29057 #define XCVR_WR_DCOC_CTRL_0_DCOC_MAN(base, value) (XCVR_RMW_DCOC_CTRL_0(base, XCVR_DCOC_CTRL_0_DCOC_MAN_MASK, XCVR_DCOC_CTRL_0_DCOC_MAN(value)))
29058 #define XCVR_BWR_DCOC_CTRL_0_DCOC_MAN(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_DCOC_CTRL_0_DCOC_MAN_SHIFT), XCVR_DCOC_CTRL_0_DCOC_MAN_SHIFT, XCVR_DCOC_CTRL_0_DCOC_MAN_WIDTH))
29059 /*@}*/
29060 
29061 /*!
29062  * @name Register XCVR_DCOC_CTRL_0, field DCOC_TRACK_EN[3] (RW)
29063  *
29064  * Enables the DCOC tracking estimator to correct the DC offset. Can be used
29065  * with or without DCOC calibration (RX_DCOC_CAL_EN).
29066  */
29067 /*@{*/
29068 /*! @brief Read current value of the XCVR_DCOC_CTRL_0_DCOC_TRACK_EN field. */
29069 #define XCVR_RD_DCOC_CTRL_0_DCOC_TRACK_EN(base) ((XCVR_DCOC_CTRL_0_REG(base) & XCVR_DCOC_CTRL_0_DCOC_TRACK_EN_MASK) >> XCVR_DCOC_CTRL_0_DCOC_TRACK_EN_SHIFT)
29070 #define XCVR_BRD_DCOC_CTRL_0_DCOC_TRACK_EN(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCVR_DCOC_CTRL_0_DCOC_TRACK_EN_SHIFT, XCVR_DCOC_CTRL_0_DCOC_TRACK_EN_WIDTH))
29071 
29072 /*! @brief Set the DCOC_TRACK_EN field to a new value. */
29073 #define XCVR_WR_DCOC_CTRL_0_DCOC_TRACK_EN(base, value) (XCVR_RMW_DCOC_CTRL_0(base, XCVR_DCOC_CTRL_0_DCOC_TRACK_EN_MASK, XCVR_DCOC_CTRL_0_DCOC_TRACK_EN(value)))
29074 #define XCVR_BWR_DCOC_CTRL_0_DCOC_TRACK_EN(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_DCOC_CTRL_0_DCOC_TRACK_EN_SHIFT), XCVR_DCOC_CTRL_0_DCOC_TRACK_EN_SHIFT, XCVR_DCOC_CTRL_0_DCOC_TRACK_EN_WIDTH))
29075 /*@}*/
29076 
29077 /*!
29078  * @name Register XCVR_DCOC_CTRL_0, field DCOC_CORRECT_EN[4] (RW)
29079  *
29080  * Enables the DCOC to use the TZA and BBA DACs to correct the DC offset.
29081  */
29082 /*@{*/
29083 /*! @brief Read current value of the XCVR_DCOC_CTRL_0_DCOC_CORRECT_EN field. */
29084 #define XCVR_RD_DCOC_CTRL_0_DCOC_CORRECT_EN(base) ((XCVR_DCOC_CTRL_0_REG(base) & XCVR_DCOC_CTRL_0_DCOC_CORRECT_EN_MASK) >> XCVR_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT)
29085 #define XCVR_BRD_DCOC_CTRL_0_DCOC_CORRECT_EN(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCVR_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT, XCVR_DCOC_CTRL_0_DCOC_CORRECT_EN_WIDTH))
29086 
29087 /*! @brief Set the DCOC_CORRECT_EN field to a new value. */
29088 #define XCVR_WR_DCOC_CTRL_0_DCOC_CORRECT_EN(base, value) (XCVR_RMW_DCOC_CTRL_0(base, XCVR_DCOC_CTRL_0_DCOC_CORRECT_EN_MASK, XCVR_DCOC_CTRL_0_DCOC_CORRECT_EN(value)))
29089 #define XCVR_BWR_DCOC_CTRL_0_DCOC_CORRECT_EN(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT), XCVR_DCOC_CTRL_0_DCOC_CORRECT_EN_SHIFT, XCVR_DCOC_CTRL_0_DCOC_CORRECT_EN_WIDTH))
29090 /*@}*/
29091 
29092 /*!
29093  * @name Register XCVR_DCOC_CTRL_0, field DCOC_SIGN_SCALE_IDX[6:5] (RW)
29094  *
29095  * DCOC Sign Scaling. Sign()-based scaling factor used in the DCOC tracking
29096  * estimator. Used when DCOC_TRACK_EN=1.
29097  *
29098  * Values:
29099  * - 0b00 - 1/4
29100  * - 0b01 - 1/8
29101  * - 0b10 - 1/16
29102  * - 0b11 - 1/32
29103  */
29104 /*@{*/
29105 /*! @brief Read current value of the XCVR_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX field. */
29106 #define XCVR_RD_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX(base) ((XCVR_DCOC_CTRL_0_REG(base) & XCVR_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX_MASK) >> XCVR_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX_SHIFT)
29107 #define XCVR_BRD_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCVR_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX_SHIFT, XCVR_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX_WIDTH))
29108 
29109 /*! @brief Set the DCOC_SIGN_SCALE_IDX field to a new value. */
29110 #define XCVR_WR_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX(base, value) (XCVR_RMW_DCOC_CTRL_0(base, XCVR_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX_MASK, XCVR_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX(value)))
29111 #define XCVR_BWR_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX_SHIFT), XCVR_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX_SHIFT, XCVR_DCOC_CTRL_0_DCOC_SIGN_SCALE_IDX_WIDTH))
29112 /*@}*/
29113 
29114 /*!
29115  * @name Register XCVR_DCOC_CTRL_0, field DCOC_ALPHAC_SCALE_IDX[9:8] (RW)
29116  *
29117  * DCOC Alpha-C Scaling. I/Q center stepsize used in the DCOC tracking
29118  * estimator. Used when DCOC_TRACK_EN=1.
29119  *
29120  * Values:
29121  * - 0b00 - 1/2
29122  * - 0b01 - 1/4
29123  * - 0b10 - 1/8
29124  * - 0b11 - 1/16
29125  */
29126 /*@{*/
29127 /*! @brief Read current value of the XCVR_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX field. */
29128 #define XCVR_RD_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX(base) ((XCVR_DCOC_CTRL_0_REG(base) & XCVR_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX_MASK) >> XCVR_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX_SHIFT)
29129 #define XCVR_BRD_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCVR_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX_SHIFT, XCVR_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX_WIDTH))
29130 
29131 /*! @brief Set the DCOC_ALPHAC_SCALE_IDX field to a new value. */
29132 #define XCVR_WR_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX(base, value) (XCVR_RMW_DCOC_CTRL_0(base, XCVR_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX_MASK, XCVR_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX(value)))
29133 #define XCVR_BWR_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX_SHIFT), XCVR_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX_SHIFT, XCVR_DCOC_CTRL_0_DCOC_ALPHAC_SCALE_IDX_WIDTH))
29134 /*@}*/
29135 
29136 /*!
29137  * @name Register XCVR_DCOC_CTRL_0, field DCOC_ALPHA_RADIUS_IDX[14:12] (RW)
29138  *
29139  * DCOC Alpha-R Scaling. Radius stepsize used in the DCOC tracking estimator.
29140  * Used when DCOC_TRACK_EN=1.
29141  *
29142  * Values:
29143  * - 0b000 - 1
29144  * - 0b001 - 1/2
29145  * - 0b010 - 1/4
29146  * - 0b011 - 1/8
29147  * - 0b100 - 1/16
29148  * - 0b101 - 1/32
29149  * - 0b110 - 1/64
29150  * - 0b111 - Reserved
29151  */
29152 /*@{*/
29153 /*! @brief Read current value of the XCVR_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX field. */
29154 #define XCVR_RD_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX(base) ((XCVR_DCOC_CTRL_0_REG(base) & XCVR_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX_MASK) >> XCVR_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX_SHIFT)
29155 #define XCVR_BRD_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCVR_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX_SHIFT, XCVR_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX_WIDTH))
29156 
29157 /*! @brief Set the DCOC_ALPHA_RADIUS_IDX field to a new value. */
29158 #define XCVR_WR_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX(base, value) (XCVR_RMW_DCOC_CTRL_0(base, XCVR_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX_MASK, XCVR_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX(value)))
29159 #define XCVR_BWR_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX_SHIFT), XCVR_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX_SHIFT, XCVR_DCOC_CTRL_0_DCOC_ALPHA_RADIUS_IDX_WIDTH))
29160 /*@}*/
29161 
29162 /*!
29163  * @name Register XCVR_DCOC_CTRL_0, field DCOC_CAL_DURATION[19:15] (RW)
29164  *
29165  * Duration (in uS) of a calibration (1-31uS). A value of 0 should never be used.
29166  */
29167 /*@{*/
29168 /*! @brief Read current value of the XCVR_DCOC_CTRL_0_DCOC_CAL_DURATION field. */
29169 #define XCVR_RD_DCOC_CTRL_0_DCOC_CAL_DURATION(base) ((XCVR_DCOC_CTRL_0_REG(base) & XCVR_DCOC_CTRL_0_DCOC_CAL_DURATION_MASK) >> XCVR_DCOC_CTRL_0_DCOC_CAL_DURATION_SHIFT)
29170 #define XCVR_BRD_DCOC_CTRL_0_DCOC_CAL_DURATION(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCVR_DCOC_CTRL_0_DCOC_CAL_DURATION_SHIFT, XCVR_DCOC_CTRL_0_DCOC_CAL_DURATION_WIDTH))
29171 
29172 /*! @brief Set the DCOC_CAL_DURATION field to a new value. */
29173 #define XCVR_WR_DCOC_CTRL_0_DCOC_CAL_DURATION(base, value) (XCVR_RMW_DCOC_CTRL_0(base, XCVR_DCOC_CTRL_0_DCOC_CAL_DURATION_MASK, XCVR_DCOC_CTRL_0_DCOC_CAL_DURATION(value)))
29174 #define XCVR_BWR_DCOC_CTRL_0_DCOC_CAL_DURATION(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_DCOC_CTRL_0_DCOC_CAL_DURATION_SHIFT), XCVR_DCOC_CTRL_0_DCOC_CAL_DURATION_SHIFT, XCVR_DCOC_CTRL_0_DCOC_CAL_DURATION_WIDTH))
29175 /*@}*/
29176 
29177 /*!
29178  * @name Register XCVR_DCOC_CTRL_0, field DCOC_CORR_DLY[24:20] (RW)
29179  *
29180  * Wait time (in uS) between corrections (1-31uS). A value of 0 should never be
29181  * used.
29182  */
29183 /*@{*/
29184 /*! @brief Read current value of the XCVR_DCOC_CTRL_0_DCOC_CORR_DLY field. */
29185 #define XCVR_RD_DCOC_CTRL_0_DCOC_CORR_DLY(base) ((XCVR_DCOC_CTRL_0_REG(base) & XCVR_DCOC_CTRL_0_DCOC_CORR_DLY_MASK) >> XCVR_DCOC_CTRL_0_DCOC_CORR_DLY_SHIFT)
29186 #define XCVR_BRD_DCOC_CTRL_0_DCOC_CORR_DLY(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCVR_DCOC_CTRL_0_DCOC_CORR_DLY_SHIFT, XCVR_DCOC_CTRL_0_DCOC_CORR_DLY_WIDTH))
29187 
29188 /*! @brief Set the DCOC_CORR_DLY field to a new value. */
29189 #define XCVR_WR_DCOC_CTRL_0_DCOC_CORR_DLY(base, value) (XCVR_RMW_DCOC_CTRL_0(base, XCVR_DCOC_CTRL_0_DCOC_CORR_DLY_MASK, XCVR_DCOC_CTRL_0_DCOC_CORR_DLY(value)))
29190 #define XCVR_BWR_DCOC_CTRL_0_DCOC_CORR_DLY(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_DCOC_CTRL_0_DCOC_CORR_DLY_SHIFT), XCVR_DCOC_CTRL_0_DCOC_CORR_DLY_SHIFT, XCVR_DCOC_CTRL_0_DCOC_CORR_DLY_WIDTH))
29191 /*@}*/
29192 
29193 /*!
29194  * @name Register XCVR_DCOC_CTRL_0, field DCOC_CORR_HOLD_TIME[31:25] (RW)
29195  *
29196  * Delay (in uS) from last gain change to freezing DC correction (1-127uS,
29197  * 127=never freeze). A value of 0 should never be used.
29198  */
29199 /*@{*/
29200 /*! @brief Read current value of the XCVR_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME field. */
29201 #define XCVR_RD_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(base) ((XCVR_DCOC_CTRL_0_REG(base) & XCVR_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_MASK) >> XCVR_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_SHIFT)
29202 #define XCVR_BRD_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(base) (BME_UBFX32(&XCVR_DCOC_CTRL_0_REG(base), XCVR_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_SHIFT, XCVR_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_WIDTH))
29203 
29204 /*! @brief Set the DCOC_CORR_HOLD_TIME field to a new value. */
29205 #define XCVR_WR_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(base, value) (XCVR_RMW_DCOC_CTRL_0(base, XCVR_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_MASK, XCVR_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(value)))
29206 #define XCVR_BWR_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_0_REG(base), ((uint32_t)(value) << XCVR_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_SHIFT), XCVR_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_SHIFT, XCVR_DCOC_CTRL_0_DCOC_CORR_HOLD_TIME_WIDTH))
29207 /*@}*/
29208 
29209 /*******************************************************************************
29210  * XCVR_DCOC_CTRL_1 - DCOC Control 1
29211  ******************************************************************************/
29212 
29213 /*!
29214  * @brief XCVR_DCOC_CTRL_1 - DCOC Control 1 (RW)
29215  *
29216  * Reset value: 0x00000000U
29217  */
29218 /*!
29219  * @name Constants and macros for entire XCVR_DCOC_CTRL_1 register
29220  */
29221 /*@{*/
29222 #define XCVR_RD_DCOC_CTRL_1(base) (XCVR_DCOC_CTRL_1_REG(base))
29223 #define XCVR_WR_DCOC_CTRL_1(base, value) (XCVR_DCOC_CTRL_1_REG(base) = (value))
29224 #define XCVR_RMW_DCOC_CTRL_1(base, mask, value) (XCVR_WR_DCOC_CTRL_1(base, (XCVR_RD_DCOC_CTRL_1(base) & ~(mask)) | (value)))
29225 #define XCVR_SET_DCOC_CTRL_1(base, value) (BME_OR32(&XCVR_DCOC_CTRL_1_REG(base), (uint32_t)(value)))
29226 #define XCVR_CLR_DCOC_CTRL_1(base, value) (BME_AND32(&XCVR_DCOC_CTRL_1_REG(base), (uint32_t)(~(value))))
29227 #define XCVR_TOG_DCOC_CTRL_1(base, value) (BME_XOR32(&XCVR_DCOC_CTRL_1_REG(base), (uint32_t)(value)))
29228 /*@}*/
29229 
29230 /*
29231  * Constants & macros for individual XCVR_DCOC_CTRL_1 bitfields
29232  */
29233 
29234 /*!
29235  * @name Register XCVR_DCOC_CTRL_1, field BBF_DCOC_STEP[8:0] (RW)
29236  *
29237  * DCOC BBF Step Size (format: 6.3). The nominal value for this is the DAC
29238  * resolution (1.2/2^6= 18.7mV) times AGC gain of -1.7dB ( 10^(-1.7/20)=0.822) times
29239  * an AGC mV to quantization scaling factor (2^11/1000 = 2.048), which is 31.57.
29240  * This value is stored in the register with 3 fractional bits, so use
29241  * round(31.57*2^3) = 253 decimal.
29242  */
29243 /*@{*/
29244 /*! @brief Read current value of the XCVR_DCOC_CTRL_1_BBF_DCOC_STEP field. */
29245 #define XCVR_RD_DCOC_CTRL_1_BBF_DCOC_STEP(base) ((XCVR_DCOC_CTRL_1_REG(base) & XCVR_DCOC_CTRL_1_BBF_DCOC_STEP_MASK) >> XCVR_DCOC_CTRL_1_BBF_DCOC_STEP_SHIFT)
29246 #define XCVR_BRD_DCOC_CTRL_1_BBF_DCOC_STEP(base) (BME_UBFX32(&XCVR_DCOC_CTRL_1_REG(base), XCVR_DCOC_CTRL_1_BBF_DCOC_STEP_SHIFT, XCVR_DCOC_CTRL_1_BBF_DCOC_STEP_WIDTH))
29247 
29248 /*! @brief Set the BBF_DCOC_STEP field to a new value. */
29249 #define XCVR_WR_DCOC_CTRL_1_BBF_DCOC_STEP(base, value) (XCVR_RMW_DCOC_CTRL_1(base, XCVR_DCOC_CTRL_1_BBF_DCOC_STEP_MASK, XCVR_DCOC_CTRL_1_BBF_DCOC_STEP(value)))
29250 #define XCVR_BWR_DCOC_CTRL_1_BBF_DCOC_STEP(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_1_REG(base), ((uint32_t)(value) << XCVR_DCOC_CTRL_1_BBF_DCOC_STEP_SHIFT), XCVR_DCOC_CTRL_1_BBF_DCOC_STEP_SHIFT, XCVR_DCOC_CTRL_1_BBF_DCOC_STEP_WIDTH))
29251 /*@}*/
29252 
29253 /*!
29254  * @name Register XCVR_DCOC_CTRL_1, field TRACK_FROM_ZERO[24] (RW)
29255  *
29256  * Selects whether the tracking estimator resets its DC estimate on every AGC
29257  * gain change to zero or uses the current I/Q sample.
29258  *
29259  * Values:
29260  * - 0b0 - Track from current I/Q sample.
29261  * - 0b1 - Track from zero.
29262  */
29263 /*@{*/
29264 /*! @brief Read current value of the XCVR_DCOC_CTRL_1_TRACK_FROM_ZERO field. */
29265 #define XCVR_RD_DCOC_CTRL_1_TRACK_FROM_ZERO(base) ((XCVR_DCOC_CTRL_1_REG(base) & XCVR_DCOC_CTRL_1_TRACK_FROM_ZERO_MASK) >> XCVR_DCOC_CTRL_1_TRACK_FROM_ZERO_SHIFT)
29266 #define XCVR_BRD_DCOC_CTRL_1_TRACK_FROM_ZERO(base) (BME_UBFX32(&XCVR_DCOC_CTRL_1_REG(base), XCVR_DCOC_CTRL_1_TRACK_FROM_ZERO_SHIFT, XCVR_DCOC_CTRL_1_TRACK_FROM_ZERO_WIDTH))
29267 
29268 /*! @brief Set the TRACK_FROM_ZERO field to a new value. */
29269 #define XCVR_WR_DCOC_CTRL_1_TRACK_FROM_ZERO(base, value) (XCVR_RMW_DCOC_CTRL_1(base, XCVR_DCOC_CTRL_1_TRACK_FROM_ZERO_MASK, XCVR_DCOC_CTRL_1_TRACK_FROM_ZERO(value)))
29270 #define XCVR_BWR_DCOC_CTRL_1_TRACK_FROM_ZERO(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_1_REG(base), ((uint32_t)(value) << XCVR_DCOC_CTRL_1_TRACK_FROM_ZERO_SHIFT), XCVR_DCOC_CTRL_1_TRACK_FROM_ZERO_SHIFT, XCVR_DCOC_CTRL_1_TRACK_FROM_ZERO_WIDTH))
29271 /*@}*/
29272 
29273 /*!
29274  * @name Register XCVR_DCOC_CTRL_1, field BBA_CORR_POL[25] (RW)
29275  *
29276  * Selects polarity of BBA corrections.
29277  *
29278  * Values:
29279  * - 0b0 - Normal polarity.
29280  * - 0b1 - Negative polarity. This should be set if the ADC output is inverted,
29281  *     or if the BBA DACs were implemented with negative polarity.
29282  */
29283 /*@{*/
29284 /*! @brief Read current value of the XCVR_DCOC_CTRL_1_BBA_CORR_POL field. */
29285 #define XCVR_RD_DCOC_CTRL_1_BBA_CORR_POL(base) ((XCVR_DCOC_CTRL_1_REG(base) & XCVR_DCOC_CTRL_1_BBA_CORR_POL_MASK) >> XCVR_DCOC_CTRL_1_BBA_CORR_POL_SHIFT)
29286 #define XCVR_BRD_DCOC_CTRL_1_BBA_CORR_POL(base) (BME_UBFX32(&XCVR_DCOC_CTRL_1_REG(base), XCVR_DCOC_CTRL_1_BBA_CORR_POL_SHIFT, XCVR_DCOC_CTRL_1_BBA_CORR_POL_WIDTH))
29287 
29288 /*! @brief Set the BBA_CORR_POL field to a new value. */
29289 #define XCVR_WR_DCOC_CTRL_1_BBA_CORR_POL(base, value) (XCVR_RMW_DCOC_CTRL_1(base, XCVR_DCOC_CTRL_1_BBA_CORR_POL_MASK, XCVR_DCOC_CTRL_1_BBA_CORR_POL(value)))
29290 #define XCVR_BWR_DCOC_CTRL_1_BBA_CORR_POL(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_1_REG(base), ((uint32_t)(value) << XCVR_DCOC_CTRL_1_BBA_CORR_POL_SHIFT), XCVR_DCOC_CTRL_1_BBA_CORR_POL_SHIFT, XCVR_DCOC_CTRL_1_BBA_CORR_POL_WIDTH))
29291 /*@}*/
29292 
29293 /*!
29294  * @name Register XCVR_DCOC_CTRL_1, field TZA_CORR_POL[26] (RW)
29295  *
29296  * Selects polarity of TZA corrections.
29297  *
29298  * Values:
29299  * - 0b0 - Normal polarity.
29300  * - 0b1 - Negative polarity. This should be set if the ADC output is inverted,
29301  *     or if the TZA DACs were implemented with negative polarity.
29302  */
29303 /*@{*/
29304 /*! @brief Read current value of the XCVR_DCOC_CTRL_1_TZA_CORR_POL field. */
29305 #define XCVR_RD_DCOC_CTRL_1_TZA_CORR_POL(base) ((XCVR_DCOC_CTRL_1_REG(base) & XCVR_DCOC_CTRL_1_TZA_CORR_POL_MASK) >> XCVR_DCOC_CTRL_1_TZA_CORR_POL_SHIFT)
29306 #define XCVR_BRD_DCOC_CTRL_1_TZA_CORR_POL(base) (BME_UBFX32(&XCVR_DCOC_CTRL_1_REG(base), XCVR_DCOC_CTRL_1_TZA_CORR_POL_SHIFT, XCVR_DCOC_CTRL_1_TZA_CORR_POL_WIDTH))
29307 
29308 /*! @brief Set the TZA_CORR_POL field to a new value. */
29309 #define XCVR_WR_DCOC_CTRL_1_TZA_CORR_POL(base, value) (XCVR_RMW_DCOC_CTRL_1(base, XCVR_DCOC_CTRL_1_TZA_CORR_POL_MASK, XCVR_DCOC_CTRL_1_TZA_CORR_POL(value)))
29310 #define XCVR_BWR_DCOC_CTRL_1_TZA_CORR_POL(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_1_REG(base), ((uint32_t)(value) << XCVR_DCOC_CTRL_1_TZA_CORR_POL_SHIFT), XCVR_DCOC_CTRL_1_TZA_CORR_POL_SHIFT, XCVR_DCOC_CTRL_1_TZA_CORR_POL_WIDTH))
29311 /*@}*/
29312 
29313 /*******************************************************************************
29314  * XCVR_DCOC_CTRL_2 - DCOC Control 2
29315  ******************************************************************************/
29316 
29317 /*!
29318  * @brief XCVR_DCOC_CTRL_2 - DCOC Control 2 (RW)
29319  *
29320  * Reset value: 0x00000000U
29321  */
29322 /*!
29323  * @name Constants and macros for entire XCVR_DCOC_CTRL_2 register
29324  */
29325 /*@{*/
29326 #define XCVR_RD_DCOC_CTRL_2(base) (XCVR_DCOC_CTRL_2_REG(base))
29327 #define XCVR_WR_DCOC_CTRL_2(base, value) (XCVR_DCOC_CTRL_2_REG(base) = (value))
29328 #define XCVR_RMW_DCOC_CTRL_2(base, mask, value) (XCVR_WR_DCOC_CTRL_2(base, (XCVR_RD_DCOC_CTRL_2(base) & ~(mask)) | (value)))
29329 #define XCVR_SET_DCOC_CTRL_2(base, value) (BME_OR32(&XCVR_DCOC_CTRL_2_REG(base), (uint32_t)(value)))
29330 #define XCVR_CLR_DCOC_CTRL_2(base, value) (BME_AND32(&XCVR_DCOC_CTRL_2_REG(base), (uint32_t)(~(value))))
29331 #define XCVR_TOG_DCOC_CTRL_2(base, value) (BME_XOR32(&XCVR_DCOC_CTRL_2_REG(base), (uint32_t)(value)))
29332 /*@}*/
29333 
29334 /*
29335  * Constants & macros for individual XCVR_DCOC_CTRL_2 bitfields
29336  */
29337 
29338 /*!
29339  * @name Register XCVR_DCOC_CTRL_2, field BBF_DCOC_STEP_RECIP[12:0] (RW)
29340  *
29341  * DCOC BBF Reciprocal of Step Size (format: .[00]13). This the reciprocal of
29342  * the BBF DCOC STEP value programmed in the XCVR_DCOC_CTRL_1 register. It's
29343  * nominal value is 1.0/31.57. This value is stored as a 15 bit fraction (though only
29344  * 13 bits are programmed), so use round(1.0/31.57*2^15) = 1038decimal.
29345  */
29346 /*@{*/
29347 /*! @brief Read current value of the XCVR_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP field. */
29348 #define XCVR_RD_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP(base) ((XCVR_DCOC_CTRL_2_REG(base) & XCVR_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP_MASK) >> XCVR_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP_SHIFT)
29349 #define XCVR_BRD_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP(base) (BME_UBFX32(&XCVR_DCOC_CTRL_2_REG(base), XCVR_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP_SHIFT, XCVR_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP_WIDTH))
29350 
29351 /*! @brief Set the BBF_DCOC_STEP_RECIP field to a new value. */
29352 #define XCVR_WR_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP(base, value) (XCVR_RMW_DCOC_CTRL_2(base, XCVR_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP_MASK, XCVR_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP(value)))
29353 #define XCVR_BWR_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_2_REG(base), ((uint32_t)(value) << XCVR_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP_SHIFT), XCVR_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP_SHIFT, XCVR_DCOC_CTRL_2_BBF_DCOC_STEP_RECIP_WIDTH))
29354 /*@}*/
29355 
29356 /*******************************************************************************
29357  * XCVR_DCOC_CTRL_3 - DCOC Control 3
29358  ******************************************************************************/
29359 
29360 /*!
29361  * @brief XCVR_DCOC_CTRL_3 - DCOC Control 3 (RW)
29362  *
29363  * Reset value: 0x00000000U
29364  */
29365 /*!
29366  * @name Constants and macros for entire XCVR_DCOC_CTRL_3 register
29367  */
29368 /*@{*/
29369 #define XCVR_RD_DCOC_CTRL_3(base) (XCVR_DCOC_CTRL_3_REG(base))
29370 #define XCVR_WR_DCOC_CTRL_3(base, value) (XCVR_DCOC_CTRL_3_REG(base) = (value))
29371 #define XCVR_RMW_DCOC_CTRL_3(base, mask, value) (XCVR_WR_DCOC_CTRL_3(base, (XCVR_RD_DCOC_CTRL_3(base) & ~(mask)) | (value)))
29372 #define XCVR_SET_DCOC_CTRL_3(base, value) (BME_OR32(&XCVR_DCOC_CTRL_3_REG(base), (uint32_t)(value)))
29373 #define XCVR_CLR_DCOC_CTRL_3(base, value) (BME_AND32(&XCVR_DCOC_CTRL_3_REG(base), (uint32_t)(~(value))))
29374 #define XCVR_TOG_DCOC_CTRL_3(base, value) (BME_XOR32(&XCVR_DCOC_CTRL_3_REG(base), (uint32_t)(value)))
29375 /*@}*/
29376 
29377 /*
29378  * Constants & macros for individual XCVR_DCOC_CTRL_3 bitfields
29379  */
29380 
29381 /*!
29382  * @name Register XCVR_DCOC_CTRL_3, field BBF_DCOC_INIT_I[5:0] (RW)
29383  *
29384  * Manual override value for DCOC BBF I channel DAC. Used when DCOC_MAN=1.
29385  */
29386 /*@{*/
29387 /*! @brief Read current value of the XCVR_DCOC_CTRL_3_BBF_DCOC_INIT_I field. */
29388 #define XCVR_RD_DCOC_CTRL_3_BBF_DCOC_INIT_I(base) ((XCVR_DCOC_CTRL_3_REG(base) & XCVR_DCOC_CTRL_3_BBF_DCOC_INIT_I_MASK) >> XCVR_DCOC_CTRL_3_BBF_DCOC_INIT_I_SHIFT)
29389 #define XCVR_BRD_DCOC_CTRL_3_BBF_DCOC_INIT_I(base) (BME_UBFX32(&XCVR_DCOC_CTRL_3_REG(base), XCVR_DCOC_CTRL_3_BBF_DCOC_INIT_I_SHIFT, XCVR_DCOC_CTRL_3_BBF_DCOC_INIT_I_WIDTH))
29390 
29391 /*! @brief Set the BBF_DCOC_INIT_I field to a new value. */
29392 #define XCVR_WR_DCOC_CTRL_3_BBF_DCOC_INIT_I(base, value) (XCVR_RMW_DCOC_CTRL_3(base, XCVR_DCOC_CTRL_3_BBF_DCOC_INIT_I_MASK, XCVR_DCOC_CTRL_3_BBF_DCOC_INIT_I(value)))
29393 #define XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_I(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_3_REG(base), ((uint32_t)(value) << XCVR_DCOC_CTRL_3_BBF_DCOC_INIT_I_SHIFT), XCVR_DCOC_CTRL_3_BBF_DCOC_INIT_I_SHIFT, XCVR_DCOC_CTRL_3_BBF_DCOC_INIT_I_WIDTH))
29394 /*@}*/
29395 
29396 /*!
29397  * @name Register XCVR_DCOC_CTRL_3, field BBF_DCOC_INIT_Q[13:8] (RW)
29398  *
29399  * Manual override value for DCOC BBF Q channel DAC. Used when DCOC_MAN=1.
29400  */
29401 /*@{*/
29402 /*! @brief Read current value of the XCVR_DCOC_CTRL_3_BBF_DCOC_INIT_Q field. */
29403 #define XCVR_RD_DCOC_CTRL_3_BBF_DCOC_INIT_Q(base) ((XCVR_DCOC_CTRL_3_REG(base) & XCVR_DCOC_CTRL_3_BBF_DCOC_INIT_Q_MASK) >> XCVR_DCOC_CTRL_3_BBF_DCOC_INIT_Q_SHIFT)
29404 #define XCVR_BRD_DCOC_CTRL_3_BBF_DCOC_INIT_Q(base) (BME_UBFX32(&XCVR_DCOC_CTRL_3_REG(base), XCVR_DCOC_CTRL_3_BBF_DCOC_INIT_Q_SHIFT, XCVR_DCOC_CTRL_3_BBF_DCOC_INIT_Q_WIDTH))
29405 
29406 /*! @brief Set the BBF_DCOC_INIT_Q field to a new value. */
29407 #define XCVR_WR_DCOC_CTRL_3_BBF_DCOC_INIT_Q(base, value) (XCVR_RMW_DCOC_CTRL_3(base, XCVR_DCOC_CTRL_3_BBF_DCOC_INIT_Q_MASK, XCVR_DCOC_CTRL_3_BBF_DCOC_INIT_Q(value)))
29408 #define XCVR_BWR_DCOC_CTRL_3_BBF_DCOC_INIT_Q(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_3_REG(base), ((uint32_t)(value) << XCVR_DCOC_CTRL_3_BBF_DCOC_INIT_Q_SHIFT), XCVR_DCOC_CTRL_3_BBF_DCOC_INIT_Q_SHIFT, XCVR_DCOC_CTRL_3_BBF_DCOC_INIT_Q_WIDTH))
29409 /*@}*/
29410 
29411 /*!
29412  * @name Register XCVR_DCOC_CTRL_3, field TZA_DCOC_INIT_I[23:16] (RW)
29413  *
29414  * Manual override value for DCOC TZA I channel DAC. Used when DCOC_MAN=1.
29415  */
29416 /*@{*/
29417 /*! @brief Read current value of the XCVR_DCOC_CTRL_3_TZA_DCOC_INIT_I field. */
29418 #define XCVR_RD_DCOC_CTRL_3_TZA_DCOC_INIT_I(base) ((XCVR_DCOC_CTRL_3_REG(base) & XCVR_DCOC_CTRL_3_TZA_DCOC_INIT_I_MASK) >> XCVR_DCOC_CTRL_3_TZA_DCOC_INIT_I_SHIFT)
29419 #define XCVR_BRD_DCOC_CTRL_3_TZA_DCOC_INIT_I(base) (BME_UBFX32(&XCVR_DCOC_CTRL_3_REG(base), XCVR_DCOC_CTRL_3_TZA_DCOC_INIT_I_SHIFT, XCVR_DCOC_CTRL_3_TZA_DCOC_INIT_I_WIDTH))
29420 
29421 /*! @brief Set the TZA_DCOC_INIT_I field to a new value. */
29422 #define XCVR_WR_DCOC_CTRL_3_TZA_DCOC_INIT_I(base, value) (XCVR_RMW_DCOC_CTRL_3(base, XCVR_DCOC_CTRL_3_TZA_DCOC_INIT_I_MASK, XCVR_DCOC_CTRL_3_TZA_DCOC_INIT_I(value)))
29423 #define XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_I(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_3_REG(base), ((uint32_t)(value) << XCVR_DCOC_CTRL_3_TZA_DCOC_INIT_I_SHIFT), XCVR_DCOC_CTRL_3_TZA_DCOC_INIT_I_SHIFT, XCVR_DCOC_CTRL_3_TZA_DCOC_INIT_I_WIDTH))
29424 /*@}*/
29425 
29426 /*!
29427  * @name Register XCVR_DCOC_CTRL_3, field TZA_DCOC_INIT_Q[31:24] (RW)
29428  *
29429  * Manual override value for DCOC TZA Q channel DAC. Used when DCOC_MAN=1.
29430  */
29431 /*@{*/
29432 /*! @brief Read current value of the XCVR_DCOC_CTRL_3_TZA_DCOC_INIT_Q field. */
29433 #define XCVR_RD_DCOC_CTRL_3_TZA_DCOC_INIT_Q(base) ((XCVR_DCOC_CTRL_3_REG(base) & XCVR_DCOC_CTRL_3_TZA_DCOC_INIT_Q_MASK) >> XCVR_DCOC_CTRL_3_TZA_DCOC_INIT_Q_SHIFT)
29434 #define XCVR_BRD_DCOC_CTRL_3_TZA_DCOC_INIT_Q(base) (BME_UBFX32(&XCVR_DCOC_CTRL_3_REG(base), XCVR_DCOC_CTRL_3_TZA_DCOC_INIT_Q_SHIFT, XCVR_DCOC_CTRL_3_TZA_DCOC_INIT_Q_WIDTH))
29435 
29436 /*! @brief Set the TZA_DCOC_INIT_Q field to a new value. */
29437 #define XCVR_WR_DCOC_CTRL_3_TZA_DCOC_INIT_Q(base, value) (XCVR_RMW_DCOC_CTRL_3(base, XCVR_DCOC_CTRL_3_TZA_DCOC_INIT_Q_MASK, XCVR_DCOC_CTRL_3_TZA_DCOC_INIT_Q(value)))
29438 #define XCVR_BWR_DCOC_CTRL_3_TZA_DCOC_INIT_Q(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_3_REG(base), ((uint32_t)(value) << XCVR_DCOC_CTRL_3_TZA_DCOC_INIT_Q_SHIFT), XCVR_DCOC_CTRL_3_TZA_DCOC_INIT_Q_SHIFT, XCVR_DCOC_CTRL_3_TZA_DCOC_INIT_Q_WIDTH))
29439 /*@}*/
29440 
29441 /*******************************************************************************
29442  * XCVR_DCOC_CTRL_4 - DCOC Control 4
29443  ******************************************************************************/
29444 
29445 /*!
29446  * @brief XCVR_DCOC_CTRL_4 - DCOC Control 4 (RW)
29447  *
29448  * Reset value: 0x00000000U
29449  */
29450 /*!
29451  * @name Constants and macros for entire XCVR_DCOC_CTRL_4 register
29452  */
29453 /*@{*/
29454 #define XCVR_RD_DCOC_CTRL_4(base) (XCVR_DCOC_CTRL_4_REG(base))
29455 #define XCVR_WR_DCOC_CTRL_4(base, value) (XCVR_DCOC_CTRL_4_REG(base) = (value))
29456 #define XCVR_RMW_DCOC_CTRL_4(base, mask, value) (XCVR_WR_DCOC_CTRL_4(base, (XCVR_RD_DCOC_CTRL_4(base) & ~(mask)) | (value)))
29457 #define XCVR_SET_DCOC_CTRL_4(base, value) (BME_OR32(&XCVR_DCOC_CTRL_4_REG(base), (uint32_t)(value)))
29458 #define XCVR_CLR_DCOC_CTRL_4(base, value) (BME_AND32(&XCVR_DCOC_CTRL_4_REG(base), (uint32_t)(~(value))))
29459 #define XCVR_TOG_DCOC_CTRL_4(base, value) (BME_XOR32(&XCVR_DCOC_CTRL_4_REG(base), (uint32_t)(value)))
29460 /*@}*/
29461 
29462 /*
29463  * Constants & macros for individual XCVR_DCOC_CTRL_4 bitfields
29464  */
29465 
29466 /*!
29467  * @name Register XCVR_DCOC_CTRL_4, field DIG_DCOC_INIT_I[11:0] (RW)
29468  *
29469  * Manual override for DCOC DIG I channel correction. Value to be subtracted
29470  * from downsampled I channel. Used when DCOC_MAN=1.
29471  */
29472 /*@{*/
29473 /*! @brief Read current value of the XCVR_DCOC_CTRL_4_DIG_DCOC_INIT_I field. */
29474 #define XCVR_RD_DCOC_CTRL_4_DIG_DCOC_INIT_I(base) ((XCVR_DCOC_CTRL_4_REG(base) & XCVR_DCOC_CTRL_4_DIG_DCOC_INIT_I_MASK) >> XCVR_DCOC_CTRL_4_DIG_DCOC_INIT_I_SHIFT)
29475 #define XCVR_BRD_DCOC_CTRL_4_DIG_DCOC_INIT_I(base) (BME_UBFX32(&XCVR_DCOC_CTRL_4_REG(base), XCVR_DCOC_CTRL_4_DIG_DCOC_INIT_I_SHIFT, XCVR_DCOC_CTRL_4_DIG_DCOC_INIT_I_WIDTH))
29476 
29477 /*! @brief Set the DIG_DCOC_INIT_I field to a new value. */
29478 #define XCVR_WR_DCOC_CTRL_4_DIG_DCOC_INIT_I(base, value) (XCVR_RMW_DCOC_CTRL_4(base, XCVR_DCOC_CTRL_4_DIG_DCOC_INIT_I_MASK, XCVR_DCOC_CTRL_4_DIG_DCOC_INIT_I(value)))
29479 #define XCVR_BWR_DCOC_CTRL_4_DIG_DCOC_INIT_I(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_4_REG(base), ((uint32_t)(value) << XCVR_DCOC_CTRL_4_DIG_DCOC_INIT_I_SHIFT), XCVR_DCOC_CTRL_4_DIG_DCOC_INIT_I_SHIFT, XCVR_DCOC_CTRL_4_DIG_DCOC_INIT_I_WIDTH))
29480 /*@}*/
29481 
29482 /*!
29483  * @name Register XCVR_DCOC_CTRL_4, field DIG_DCOC_INIT_Q[27:16] (RW)
29484  *
29485  * Manual override for DCOC DIG Q channel correction. Value to be subtracted
29486  * from downsampled Q channel. Used when DCOC_MAN=1.
29487  */
29488 /*@{*/
29489 /*! @brief Read current value of the XCVR_DCOC_CTRL_4_DIG_DCOC_INIT_Q field. */
29490 #define XCVR_RD_DCOC_CTRL_4_DIG_DCOC_INIT_Q(base) ((XCVR_DCOC_CTRL_4_REG(base) & XCVR_DCOC_CTRL_4_DIG_DCOC_INIT_Q_MASK) >> XCVR_DCOC_CTRL_4_DIG_DCOC_INIT_Q_SHIFT)
29491 #define XCVR_BRD_DCOC_CTRL_4_DIG_DCOC_INIT_Q(base) (BME_UBFX32(&XCVR_DCOC_CTRL_4_REG(base), XCVR_DCOC_CTRL_4_DIG_DCOC_INIT_Q_SHIFT, XCVR_DCOC_CTRL_4_DIG_DCOC_INIT_Q_WIDTH))
29492 
29493 /*! @brief Set the DIG_DCOC_INIT_Q field to a new value. */
29494 #define XCVR_WR_DCOC_CTRL_4_DIG_DCOC_INIT_Q(base, value) (XCVR_RMW_DCOC_CTRL_4(base, XCVR_DCOC_CTRL_4_DIG_DCOC_INIT_Q_MASK, XCVR_DCOC_CTRL_4_DIG_DCOC_INIT_Q(value)))
29495 #define XCVR_BWR_DCOC_CTRL_4_DIG_DCOC_INIT_Q(base, value) (BME_BFI32(&XCVR_DCOC_CTRL_4_REG(base), ((uint32_t)(value) << XCVR_DCOC_CTRL_4_DIG_DCOC_INIT_Q_SHIFT), XCVR_DCOC_CTRL_4_DIG_DCOC_INIT_Q_SHIFT, XCVR_DCOC_CTRL_4_DIG_DCOC_INIT_Q_WIDTH))
29496 /*@}*/
29497 
29498 /*******************************************************************************
29499  * XCVR_DCOC_CAL_GAIN - DCOC Calibration Gain
29500  ******************************************************************************/
29501 
29502 /*!
29503  * @brief XCVR_DCOC_CAL_GAIN - DCOC Calibration Gain (RW)
29504  *
29505  * Reset value: 0x00000000U
29506  */
29507 /*!
29508  * @name Constants and macros for entire XCVR_DCOC_CAL_GAIN register
29509  */
29510 /*@{*/
29511 #define XCVR_RD_DCOC_CAL_GAIN(base) (XCVR_DCOC_CAL_GAIN_REG(base))
29512 #define XCVR_WR_DCOC_CAL_GAIN(base, value) (XCVR_DCOC_CAL_GAIN_REG(base) = (value))
29513 #define XCVR_RMW_DCOC_CAL_GAIN(base, mask, value) (XCVR_WR_DCOC_CAL_GAIN(base, (XCVR_RD_DCOC_CAL_GAIN(base) & ~(mask)) | (value)))
29514 #define XCVR_SET_DCOC_CAL_GAIN(base, value) (BME_OR32(&XCVR_DCOC_CAL_GAIN_REG(base), (uint32_t)(value)))
29515 #define XCVR_CLR_DCOC_CAL_GAIN(base, value) (BME_AND32(&XCVR_DCOC_CAL_GAIN_REG(base), (uint32_t)(~(value))))
29516 #define XCVR_TOG_DCOC_CAL_GAIN(base, value) (BME_XOR32(&XCVR_DCOC_CAL_GAIN_REG(base), (uint32_t)(value)))
29517 /*@}*/
29518 
29519 /*
29520  * Constants & macros for individual XCVR_DCOC_CAL_GAIN bitfields
29521  */
29522 
29523 /*!
29524  * @name Register XCVR_DCOC_CAL_GAIN, field DCOC_BBF_CAL_GAIN1[11:8] (RW)
29525  *
29526  * The BBF gain index used for the 1st DCOC calibration point. Used when
29527  * RX_DCOC_CAL_EN=1.
29528  */
29529 /*@{*/
29530 /*! @brief Read current value of the XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1 field. */
29531 #define XCVR_RD_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1(base) ((XCVR_DCOC_CAL_GAIN_REG(base) & XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1_MASK) >> XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1_SHIFT)
29532 #define XCVR_BRD_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAIN_REG(base), XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1_SHIFT, XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1_WIDTH))
29533 
29534 /*! @brief Set the DCOC_BBF_CAL_GAIN1 field to a new value. */
29535 #define XCVR_WR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1(base, value) (XCVR_RMW_DCOC_CAL_GAIN(base, XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1_MASK, XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1(value)))
29536 #define XCVR_BWR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1(base, value) (BME_BFI32(&XCVR_DCOC_CAL_GAIN_REG(base), ((uint32_t)(value) << XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1_SHIFT), XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1_SHIFT, XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN1_WIDTH))
29537 /*@}*/
29538 
29539 /*!
29540  * @name Register XCVR_DCOC_CAL_GAIN, field DCOC_TZA_CAL_GAIN1[15:12] (RW)
29541  *
29542  * The LNM gain index used for the 1st DCOC calibration point. Used when
29543  * RX_DCOC_CAL_EN=1.
29544  */
29545 /*@{*/
29546 /*! @brief Read current value of the XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1 field. */
29547 #define XCVR_RD_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1(base) ((XCVR_DCOC_CAL_GAIN_REG(base) & XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1_MASK) >> XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1_SHIFT)
29548 #define XCVR_BRD_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAIN_REG(base), XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1_SHIFT, XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1_WIDTH))
29549 
29550 /*! @brief Set the DCOC_TZA_CAL_GAIN1 field to a new value. */
29551 #define XCVR_WR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1(base, value) (XCVR_RMW_DCOC_CAL_GAIN(base, XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1_MASK, XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1(value)))
29552 #define XCVR_BWR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1(base, value) (BME_BFI32(&XCVR_DCOC_CAL_GAIN_REG(base), ((uint32_t)(value) << XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1_SHIFT), XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1_SHIFT, XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN1_WIDTH))
29553 /*@}*/
29554 
29555 /*!
29556  * @name Register XCVR_DCOC_CAL_GAIN, field DCOC_BBF_CAL_GAIN2[19:16] (RW)
29557  *
29558  * The BBF gain index used for the 2nd DCOC calibration point. Used when
29559  * RX_DCOC_CAL_EN=1.
29560  */
29561 /*@{*/
29562 /*! @brief Read current value of the XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2 field. */
29563 #define XCVR_RD_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2(base) ((XCVR_DCOC_CAL_GAIN_REG(base) & XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2_MASK) >> XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2_SHIFT)
29564 #define XCVR_BRD_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAIN_REG(base), XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2_SHIFT, XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2_WIDTH))
29565 
29566 /*! @brief Set the DCOC_BBF_CAL_GAIN2 field to a new value. */
29567 #define XCVR_WR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2(base, value) (XCVR_RMW_DCOC_CAL_GAIN(base, XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2_MASK, XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2(value)))
29568 #define XCVR_BWR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2(base, value) (BME_BFI32(&XCVR_DCOC_CAL_GAIN_REG(base), ((uint32_t)(value) << XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2_SHIFT), XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2_SHIFT, XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN2_WIDTH))
29569 /*@}*/
29570 
29571 /*!
29572  * @name Register XCVR_DCOC_CAL_GAIN, field DCOC_TZA_CAL_GAIN2[23:20] (RW)
29573  *
29574  * The LNM gain index used for the 2nd DCOC calibration point. Used when
29575  * RX_DCOC_CAL_EN=1.
29576  */
29577 /*@{*/
29578 /*! @brief Read current value of the XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2 field. */
29579 #define XCVR_RD_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2(base) ((XCVR_DCOC_CAL_GAIN_REG(base) & XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2_MASK) >> XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2_SHIFT)
29580 #define XCVR_BRD_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAIN_REG(base), XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2_SHIFT, XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2_WIDTH))
29581 
29582 /*! @brief Set the DCOC_TZA_CAL_GAIN2 field to a new value. */
29583 #define XCVR_WR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2(base, value) (XCVR_RMW_DCOC_CAL_GAIN(base, XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2_MASK, XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2(value)))
29584 #define XCVR_BWR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2(base, value) (BME_BFI32(&XCVR_DCOC_CAL_GAIN_REG(base), ((uint32_t)(value) << XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2_SHIFT), XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2_SHIFT, XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN2_WIDTH))
29585 /*@}*/
29586 
29587 /*!
29588  * @name Register XCVR_DCOC_CAL_GAIN, field DCOC_BBF_CAL_GAIN3[27:24] (RW)
29589  *
29590  * The BBF gain index used for the 3rd DCOC calibration point. Used when
29591  * RX_DCOC_CAL_EN=1.
29592  */
29593 /*@{*/
29594 /*! @brief Read current value of the XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3 field. */
29595 #define XCVR_RD_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3(base) ((XCVR_DCOC_CAL_GAIN_REG(base) & XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3_MASK) >> XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3_SHIFT)
29596 #define XCVR_BRD_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAIN_REG(base), XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3_SHIFT, XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3_WIDTH))
29597 
29598 /*! @brief Set the DCOC_BBF_CAL_GAIN3 field to a new value. */
29599 #define XCVR_WR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3(base, value) (XCVR_RMW_DCOC_CAL_GAIN(base, XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3_MASK, XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3(value)))
29600 #define XCVR_BWR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3(base, value) (BME_BFI32(&XCVR_DCOC_CAL_GAIN_REG(base), ((uint32_t)(value) << XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3_SHIFT), XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3_SHIFT, XCVR_DCOC_CAL_GAIN_DCOC_BBF_CAL_GAIN3_WIDTH))
29601 /*@}*/
29602 
29603 /*!
29604  * @name Register XCVR_DCOC_CAL_GAIN, field DCOC_TZA_CAL_GAIN3[31:28] (RW)
29605  *
29606  * The LNM gain index used for the 3rd DCOC calibration point. Used when
29607  * RX_DCOC_CAL_EN=1.
29608  */
29609 /*@{*/
29610 /*! @brief Read current value of the XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3 field. */
29611 #define XCVR_RD_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3(base) ((XCVR_DCOC_CAL_GAIN_REG(base) & XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3_MASK) >> XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3_SHIFT)
29612 #define XCVR_BRD_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAIN_REG(base), XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3_SHIFT, XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3_WIDTH))
29613 
29614 /*! @brief Set the DCOC_TZA_CAL_GAIN3 field to a new value. */
29615 #define XCVR_WR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3(base, value) (XCVR_RMW_DCOC_CAL_GAIN(base, XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3_MASK, XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3(value)))
29616 #define XCVR_BWR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3(base, value) (BME_BFI32(&XCVR_DCOC_CAL_GAIN_REG(base), ((uint32_t)(value) << XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3_SHIFT), XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3_SHIFT, XCVR_DCOC_CAL_GAIN_DCOC_TZA_CAL_GAIN3_WIDTH))
29617 /*@}*/
29618 
29619 /*******************************************************************************
29620  * XCVR_DCOC_STAT - DCOC Status
29621  ******************************************************************************/
29622 
29623 /*!
29624  * @brief XCVR_DCOC_STAT - DCOC Status (RO)
29625  *
29626  * Reset value: 0x80802020U
29627  */
29628 /*!
29629  * @name Constants and macros for entire XCVR_DCOC_STAT register
29630  */
29631 /*@{*/
29632 #define XCVR_RD_DCOC_STAT(base)  (XCVR_DCOC_STAT_REG(base))
29633 /*@}*/
29634 
29635 /*
29636  * Constants & macros for individual XCVR_DCOC_STAT bitfields
29637  */
29638 
29639 /*!
29640  * @name Register XCVR_DCOC_STAT, field BBF_DCOC_I[5:0] (RO)
29641  *
29642  * Current BBF DAC setting for I channel. Note that the BBF DACs have a bias of
29643  * 0x20; 0x0 represents the most negative DC offset, 0x20 represents a DC offset
29644  * of 0, and 0x3F represents the most postiive DC offset. This is provided for
29645  * debug and characterization purposes only.
29646  */
29647 /*@{*/
29648 /*! @brief Read current value of the XCVR_DCOC_STAT_BBF_DCOC_I field. */
29649 #define XCVR_RD_DCOC_STAT_BBF_DCOC_I(base) ((XCVR_DCOC_STAT_REG(base) & XCVR_DCOC_STAT_BBF_DCOC_I_MASK) >> XCVR_DCOC_STAT_BBF_DCOC_I_SHIFT)
29650 #define XCVR_BRD_DCOC_STAT_BBF_DCOC_I(base) (BME_UBFX32(&XCVR_DCOC_STAT_REG(base), XCVR_DCOC_STAT_BBF_DCOC_I_SHIFT, XCVR_DCOC_STAT_BBF_DCOC_I_WIDTH))
29651 /*@}*/
29652 
29653 /*!
29654  * @name Register XCVR_DCOC_STAT, field BBF_DCOC_Q[13:8] (RO)
29655  *
29656  * Current BBF DAC setting for Q channel. Note that the BBF DACs have a bias of
29657  * 0x20; 0x0 represents the most negative DC offset, 0x20 represents a DC offset
29658  * of 0, and 0x3F represents the most postiive DC offset. This is provided for
29659  * debug and characterization purposes only.
29660  */
29661 /*@{*/
29662 /*! @brief Read current value of the XCVR_DCOC_STAT_BBF_DCOC_Q field. */
29663 #define XCVR_RD_DCOC_STAT_BBF_DCOC_Q(base) ((XCVR_DCOC_STAT_REG(base) & XCVR_DCOC_STAT_BBF_DCOC_Q_MASK) >> XCVR_DCOC_STAT_BBF_DCOC_Q_SHIFT)
29664 #define XCVR_BRD_DCOC_STAT_BBF_DCOC_Q(base) (BME_UBFX32(&XCVR_DCOC_STAT_REG(base), XCVR_DCOC_STAT_BBF_DCOC_Q_SHIFT, XCVR_DCOC_STAT_BBF_DCOC_Q_WIDTH))
29665 /*@}*/
29666 
29667 /*!
29668  * @name Register XCVR_DCOC_STAT, field TZA_DCOC_I[23:16] (RO)
29669  *
29670  * Current TZA DAC setting for I channel. Note that the TZA DACs have a bias of
29671  * 0x80; 0x0 represents the most negative DC offset, 0x80 represents a DC offset
29672  * of 0, and 0xFF represents the most postiive DC offset. This is provided for
29673  * debug and characterization purposes only.
29674  */
29675 /*@{*/
29676 /*! @brief Read current value of the XCVR_DCOC_STAT_TZA_DCOC_I field. */
29677 #define XCVR_RD_DCOC_STAT_TZA_DCOC_I(base) ((XCVR_DCOC_STAT_REG(base) & XCVR_DCOC_STAT_TZA_DCOC_I_MASK) >> XCVR_DCOC_STAT_TZA_DCOC_I_SHIFT)
29678 #define XCVR_BRD_DCOC_STAT_TZA_DCOC_I(base) (BME_UBFX32(&XCVR_DCOC_STAT_REG(base), XCVR_DCOC_STAT_TZA_DCOC_I_SHIFT, XCVR_DCOC_STAT_TZA_DCOC_I_WIDTH))
29679 /*@}*/
29680 
29681 /*!
29682  * @name Register XCVR_DCOC_STAT, field TZA_DCOC_Q[31:24] (RO)
29683  *
29684  * Current TZA DAC setting for Q channel. Note that the TZA DACs have a bias of
29685  * 0x80; 0x0 represents the most negative DC offset, 0x80 represents a DC offset
29686  * of 0, and 0xFF represents the most postiive DC offset. This is provided for
29687  * debug and characterization purposes only.
29688  */
29689 /*@{*/
29690 /*! @brief Read current value of the XCVR_DCOC_STAT_TZA_DCOC_Q field. */
29691 #define XCVR_RD_DCOC_STAT_TZA_DCOC_Q(base) ((XCVR_DCOC_STAT_REG(base) & XCVR_DCOC_STAT_TZA_DCOC_Q_MASK) >> XCVR_DCOC_STAT_TZA_DCOC_Q_SHIFT)
29692 #define XCVR_BRD_DCOC_STAT_TZA_DCOC_Q(base) (BME_UBFX32(&XCVR_DCOC_STAT_REG(base), XCVR_DCOC_STAT_TZA_DCOC_Q_SHIFT, XCVR_DCOC_STAT_TZA_DCOC_Q_WIDTH))
29693 /*@}*/
29694 
29695 /*******************************************************************************
29696  * XCVR_DCOC_DC_EST - DCOC DC Estimate
29697  ******************************************************************************/
29698 
29699 /*!
29700  * @brief XCVR_DCOC_DC_EST - DCOC DC Estimate (RO)
29701  *
29702  * Reset value: 0x00000000U
29703  */
29704 /*!
29705  * @name Constants and macros for entire XCVR_DCOC_DC_EST register
29706  */
29707 /*@{*/
29708 #define XCVR_RD_DCOC_DC_EST(base) (XCVR_DCOC_DC_EST_REG(base))
29709 /*@}*/
29710 
29711 /*
29712  * Constants & macros for individual XCVR_DCOC_DC_EST bitfields
29713  */
29714 
29715 /*!
29716  * @name Register XCVR_DCOC_DC_EST, field DC_EST_I[11:0] (RO)
29717  *
29718  * Reflects the current DCOC DC tracking estimate for I channel. Used when
29719  * DCOC_TRACK_EN=1. This is provided for debug and characterization purposes only.
29720  */
29721 /*@{*/
29722 /*! @brief Read current value of the XCVR_DCOC_DC_EST_DC_EST_I field. */
29723 #define XCVR_RD_DCOC_DC_EST_DC_EST_I(base) ((XCVR_DCOC_DC_EST_REG(base) & XCVR_DCOC_DC_EST_DC_EST_I_MASK) >> XCVR_DCOC_DC_EST_DC_EST_I_SHIFT)
29724 #define XCVR_BRD_DCOC_DC_EST_DC_EST_I(base) (BME_UBFX32(&XCVR_DCOC_DC_EST_REG(base), XCVR_DCOC_DC_EST_DC_EST_I_SHIFT, XCVR_DCOC_DC_EST_DC_EST_I_WIDTH))
29725 /*@}*/
29726 
29727 /*!
29728  * @name Register XCVR_DCOC_DC_EST, field DC_EST_Q[27:16] (RO)
29729  *
29730  * Reflects the current DCOC DC tracking estimate for Q channel. Used when
29731  * DCOC_TRACK_EN=1. This is provided for debug and characterization purposes only.
29732  */
29733 /*@{*/
29734 /*! @brief Read current value of the XCVR_DCOC_DC_EST_DC_EST_Q field. */
29735 #define XCVR_RD_DCOC_DC_EST_DC_EST_Q(base) ((XCVR_DCOC_DC_EST_REG(base) & XCVR_DCOC_DC_EST_DC_EST_Q_MASK) >> XCVR_DCOC_DC_EST_DC_EST_Q_SHIFT)
29736 #define XCVR_BRD_DCOC_DC_EST_DC_EST_Q(base) (BME_UBFX32(&XCVR_DCOC_DC_EST_REG(base), XCVR_DCOC_DC_EST_DC_EST_Q_SHIFT, XCVR_DCOC_DC_EST_DC_EST_Q_WIDTH))
29737 /*@}*/
29738 
29739 /*******************************************************************************
29740  * XCVR_DCOC_CAL_RCP - DCOC Calibration Reciprocals
29741  ******************************************************************************/
29742 
29743 /*!
29744  * @brief XCVR_DCOC_CAL_RCP - DCOC Calibration Reciprocals (RW)
29745  *
29746  * Reset value: 0x00000000U
29747  */
29748 /*!
29749  * @name Constants and macros for entire XCVR_DCOC_CAL_RCP register
29750  */
29751 /*@{*/
29752 #define XCVR_RD_DCOC_CAL_RCP(base) (XCVR_DCOC_CAL_RCP_REG(base))
29753 #define XCVR_WR_DCOC_CAL_RCP(base, value) (XCVR_DCOC_CAL_RCP_REG(base) = (value))
29754 #define XCVR_RMW_DCOC_CAL_RCP(base, mask, value) (XCVR_WR_DCOC_CAL_RCP(base, (XCVR_RD_DCOC_CAL_RCP(base) & ~(mask)) | (value)))
29755 #define XCVR_SET_DCOC_CAL_RCP(base, value) (BME_OR32(&XCVR_DCOC_CAL_RCP_REG(base), (uint32_t)(value)))
29756 #define XCVR_CLR_DCOC_CAL_RCP(base, value) (BME_AND32(&XCVR_DCOC_CAL_RCP_REG(base), (uint32_t)(~(value))))
29757 #define XCVR_TOG_DCOC_CAL_RCP(base, value) (BME_XOR32(&XCVR_DCOC_CAL_RCP_REG(base), (uint32_t)(value)))
29758 /*@}*/
29759 
29760 /*
29761  * Constants & macros for individual XCVR_DCOC_CAL_RCP bitfields
29762  */
29763 
29764 /*!
29765  * @name Register XCVR_DCOC_CAL_RCP, field DCOC_TMP_CALC_RECIP[9:0] (RW)
29766  *
29767  * DCOC_tmp calculation reciprocal (format: .10). This is used in DCDC
29768  * calibration calculation. It is defined as 1.0/(GB_HI - GB_LO) This is stored with 10
29769  * fractional bits, so program the value round([1.0/(GB_HI - GB_LO)]*2^10).
29770  */
29771 /*@{*/
29772 /*! @brief Read current value of the XCVR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP field. */
29773 #define XCVR_RD_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(base) ((XCVR_DCOC_CAL_RCP_REG(base) & XCVR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_MASK) >> XCVR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_SHIFT)
29774 #define XCVR_BRD_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(base) (BME_UBFX32(&XCVR_DCOC_CAL_RCP_REG(base), XCVR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_SHIFT, XCVR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_WIDTH))
29775 
29776 /*! @brief Set the DCOC_TMP_CALC_RECIP field to a new value. */
29777 #define XCVR_WR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(base, value) (XCVR_RMW_DCOC_CAL_RCP(base, XCVR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_MASK, XCVR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(value)))
29778 #define XCVR_BWR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP(base, value) (BME_BFI32(&XCVR_DCOC_CAL_RCP_REG(base), ((uint32_t)(value) << XCVR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_SHIFT), XCVR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_SHIFT, XCVR_DCOC_CAL_RCP_DCOC_TMP_CALC_RECIP_WIDTH))
29779 /*@}*/
29780 
29781 /*!
29782  * @name Register XCVR_DCOC_CAL_RCP, field ALPHA_CALC_RECIP[20:10] (RW)
29783  *
29784  * DCOC Alpha calculation reciprocal (format: .11). This is used in DCOC
29785  * calibration calculation of the alpha DC component. It is defined as: 1.0/((GL_HI -
29786  * GL_LO)*GB_LO) This is stored as with 11 fractional bits, so program the value
29787  * round([1.0/((GL_HI - GL_LO)*GB_LO)]*2^11).
29788  */
29789 /*@{*/
29790 /*! @brief Read current value of the XCVR_DCOC_CAL_RCP_ALPHA_CALC_RECIP field. */
29791 #define XCVR_RD_DCOC_CAL_RCP_ALPHA_CALC_RECIP(base) ((XCVR_DCOC_CAL_RCP_REG(base) & XCVR_DCOC_CAL_RCP_ALPHA_CALC_RECIP_MASK) >> XCVR_DCOC_CAL_RCP_ALPHA_CALC_RECIP_SHIFT)
29792 #define XCVR_BRD_DCOC_CAL_RCP_ALPHA_CALC_RECIP(base) (BME_UBFX32(&XCVR_DCOC_CAL_RCP_REG(base), XCVR_DCOC_CAL_RCP_ALPHA_CALC_RECIP_SHIFT, XCVR_DCOC_CAL_RCP_ALPHA_CALC_RECIP_WIDTH))
29793 
29794 /*! @brief Set the ALPHA_CALC_RECIP field to a new value. */
29795 #define XCVR_WR_DCOC_CAL_RCP_ALPHA_CALC_RECIP(base, value) (XCVR_RMW_DCOC_CAL_RCP(base, XCVR_DCOC_CAL_RCP_ALPHA_CALC_RECIP_MASK, XCVR_DCOC_CAL_RCP_ALPHA_CALC_RECIP(value)))
29796 #define XCVR_BWR_DCOC_CAL_RCP_ALPHA_CALC_RECIP(base, value) (BME_BFI32(&XCVR_DCOC_CAL_RCP_REG(base), ((uint32_t)(value) << XCVR_DCOC_CAL_RCP_ALPHA_CALC_RECIP_SHIFT), XCVR_DCOC_CAL_RCP_ALPHA_CALC_RECIP_SHIFT, XCVR_DCOC_CAL_RCP_ALPHA_CALC_RECIP_WIDTH))
29797 /*@}*/
29798 
29799 /*******************************************************************************
29800  * XCVR_IQMC_CTRL - IQMC Control
29801  ******************************************************************************/
29802 
29803 /*!
29804  * @brief XCVR_IQMC_CTRL - IQMC Control (RW)
29805  *
29806  * Reset value: 0x00008000U
29807  */
29808 /*!
29809  * @name Constants and macros for entire XCVR_IQMC_CTRL register
29810  */
29811 /*@{*/
29812 #define XCVR_RD_IQMC_CTRL(base)  (XCVR_IQMC_CTRL_REG(base))
29813 #define XCVR_WR_IQMC_CTRL(base, value) (XCVR_IQMC_CTRL_REG(base) = (value))
29814 #define XCVR_RMW_IQMC_CTRL(base, mask, value) (XCVR_WR_IQMC_CTRL(base, (XCVR_RD_IQMC_CTRL(base) & ~(mask)) | (value)))
29815 #define XCVR_SET_IQMC_CTRL(base, value) (BME_OR32(&XCVR_IQMC_CTRL_REG(base), (uint32_t)(value)))
29816 #define XCVR_CLR_IQMC_CTRL(base, value) (BME_AND32(&XCVR_IQMC_CTRL_REG(base), (uint32_t)(~(value))))
29817 #define XCVR_TOG_IQMC_CTRL(base, value) (BME_XOR32(&XCVR_IQMC_CTRL_REG(base), (uint32_t)(value)))
29818 /*@}*/
29819 
29820 /*
29821  * Constants & macros for individual XCVR_IQMC_CTRL bitfields
29822  */
29823 
29824 /*!
29825  * @name Register XCVR_IQMC_CTRL, field IQMC_CAL_EN[0] (RW)
29826  *
29827  * Enables IQ mismatch calibration.
29828  */
29829 /*@{*/
29830 /*! @brief Read current value of the XCVR_IQMC_CTRL_IQMC_CAL_EN field. */
29831 #define XCVR_RD_IQMC_CTRL_IQMC_CAL_EN(base) ((XCVR_IQMC_CTRL_REG(base) & XCVR_IQMC_CTRL_IQMC_CAL_EN_MASK) >> XCVR_IQMC_CTRL_IQMC_CAL_EN_SHIFT)
29832 #define XCVR_BRD_IQMC_CTRL_IQMC_CAL_EN(base) (BME_UBFX32(&XCVR_IQMC_CTRL_REG(base), XCVR_IQMC_CTRL_IQMC_CAL_EN_SHIFT, XCVR_IQMC_CTRL_IQMC_CAL_EN_WIDTH))
29833 
29834 /*! @brief Set the IQMC_CAL_EN field to a new value. */
29835 #define XCVR_WR_IQMC_CTRL_IQMC_CAL_EN(base, value) (XCVR_RMW_IQMC_CTRL(base, XCVR_IQMC_CTRL_IQMC_CAL_EN_MASK, XCVR_IQMC_CTRL_IQMC_CAL_EN(value)))
29836 #define XCVR_BWR_IQMC_CTRL_IQMC_CAL_EN(base, value) (BME_BFI32(&XCVR_IQMC_CTRL_REG(base), ((uint32_t)(value) << XCVR_IQMC_CTRL_IQMC_CAL_EN_SHIFT), XCVR_IQMC_CTRL_IQMC_CAL_EN_SHIFT, XCVR_IQMC_CTRL_IQMC_CAL_EN_WIDTH))
29837 /*@}*/
29838 
29839 /*!
29840  * @name Register XCVR_IQMC_CTRL, field IQMC_NUM_ITER[15:8] (RW)
29841  *
29842  * Number of iterations for IQ Mismatch Calibration.
29843  */
29844 /*@{*/
29845 /*! @brief Read current value of the XCVR_IQMC_CTRL_IQMC_NUM_ITER field. */
29846 #define XCVR_RD_IQMC_CTRL_IQMC_NUM_ITER(base) ((XCVR_IQMC_CTRL_REG(base) & XCVR_IQMC_CTRL_IQMC_NUM_ITER_MASK) >> XCVR_IQMC_CTRL_IQMC_NUM_ITER_SHIFT)
29847 #define XCVR_BRD_IQMC_CTRL_IQMC_NUM_ITER(base) (BME_UBFX32(&XCVR_IQMC_CTRL_REG(base), XCVR_IQMC_CTRL_IQMC_NUM_ITER_SHIFT, XCVR_IQMC_CTRL_IQMC_NUM_ITER_WIDTH))
29848 
29849 /*! @brief Set the IQMC_NUM_ITER field to a new value. */
29850 #define XCVR_WR_IQMC_CTRL_IQMC_NUM_ITER(base, value) (XCVR_RMW_IQMC_CTRL(base, XCVR_IQMC_CTRL_IQMC_NUM_ITER_MASK, XCVR_IQMC_CTRL_IQMC_NUM_ITER(value)))
29851 #define XCVR_BWR_IQMC_CTRL_IQMC_NUM_ITER(base, value) (BME_BFI32(&XCVR_IQMC_CTRL_REG(base), ((uint32_t)(value) << XCVR_IQMC_CTRL_IQMC_NUM_ITER_SHIFT), XCVR_IQMC_CTRL_IQMC_NUM_ITER_SHIFT, XCVR_IQMC_CTRL_IQMC_NUM_ITER_WIDTH))
29852 /*@}*/
29853 
29854 /*******************************************************************************
29855  * XCVR_IQMC_CAL - IQMC Calibration
29856  ******************************************************************************/
29857 
29858 /*!
29859  * @brief XCVR_IQMC_CAL - IQMC Calibration (RW)
29860  *
29861  * Reset value: 0x00000400U
29862  */
29863 /*!
29864  * @name Constants and macros for entire XCVR_IQMC_CAL register
29865  */
29866 /*@{*/
29867 #define XCVR_RD_IQMC_CAL(base)   (XCVR_IQMC_CAL_REG(base))
29868 #define XCVR_WR_IQMC_CAL(base, value) (XCVR_IQMC_CAL_REG(base) = (value))
29869 #define XCVR_RMW_IQMC_CAL(base, mask, value) (XCVR_WR_IQMC_CAL(base, (XCVR_RD_IQMC_CAL(base) & ~(mask)) | (value)))
29870 #define XCVR_SET_IQMC_CAL(base, value) (BME_OR32(&XCVR_IQMC_CAL_REG(base), (uint32_t)(value)))
29871 #define XCVR_CLR_IQMC_CAL(base, value) (BME_AND32(&XCVR_IQMC_CAL_REG(base), (uint32_t)(~(value))))
29872 #define XCVR_TOG_IQMC_CAL(base, value) (BME_XOR32(&XCVR_IQMC_CAL_REG(base), (uint32_t)(value)))
29873 /*@}*/
29874 
29875 /*
29876  * Constants & macros for individual XCVR_IQMC_CAL bitfields
29877  */
29878 
29879 /*!
29880  * @name Register XCVR_IQMC_CAL, field IQMC_GAIN_ADJ[10:0] (RW)
29881  *
29882  * I/Q mismatch correction gain coefficient.
29883  */
29884 /*@{*/
29885 /*! @brief Read current value of the XCVR_IQMC_CAL_IQMC_GAIN_ADJ field. */
29886 #define XCVR_RD_IQMC_CAL_IQMC_GAIN_ADJ(base) ((XCVR_IQMC_CAL_REG(base) & XCVR_IQMC_CAL_IQMC_GAIN_ADJ_MASK) >> XCVR_IQMC_CAL_IQMC_GAIN_ADJ_SHIFT)
29887 #define XCVR_BRD_IQMC_CAL_IQMC_GAIN_ADJ(base) (BME_UBFX32(&XCVR_IQMC_CAL_REG(base), XCVR_IQMC_CAL_IQMC_GAIN_ADJ_SHIFT, XCVR_IQMC_CAL_IQMC_GAIN_ADJ_WIDTH))
29888 
29889 /*! @brief Set the IQMC_GAIN_ADJ field to a new value. */
29890 #define XCVR_WR_IQMC_CAL_IQMC_GAIN_ADJ(base, value) (XCVR_RMW_IQMC_CAL(base, XCVR_IQMC_CAL_IQMC_GAIN_ADJ_MASK, XCVR_IQMC_CAL_IQMC_GAIN_ADJ(value)))
29891 #define XCVR_BWR_IQMC_CAL_IQMC_GAIN_ADJ(base, value) (BME_BFI32(&XCVR_IQMC_CAL_REG(base), ((uint32_t)(value) << XCVR_IQMC_CAL_IQMC_GAIN_ADJ_SHIFT), XCVR_IQMC_CAL_IQMC_GAIN_ADJ_SHIFT, XCVR_IQMC_CAL_IQMC_GAIN_ADJ_WIDTH))
29892 /*@}*/
29893 
29894 /*!
29895  * @name Register XCVR_IQMC_CAL, field IQMC_PHASE_ADJ[27:16] (RW)
29896  *
29897  * I/Q mismatch correction phase coefficient.
29898  */
29899 /*@{*/
29900 /*! @brief Read current value of the XCVR_IQMC_CAL_IQMC_PHASE_ADJ field. */
29901 #define XCVR_RD_IQMC_CAL_IQMC_PHASE_ADJ(base) ((XCVR_IQMC_CAL_REG(base) & XCVR_IQMC_CAL_IQMC_PHASE_ADJ_MASK) >> XCVR_IQMC_CAL_IQMC_PHASE_ADJ_SHIFT)
29902 #define XCVR_BRD_IQMC_CAL_IQMC_PHASE_ADJ(base) (BME_UBFX32(&XCVR_IQMC_CAL_REG(base), XCVR_IQMC_CAL_IQMC_PHASE_ADJ_SHIFT, XCVR_IQMC_CAL_IQMC_PHASE_ADJ_WIDTH))
29903 
29904 /*! @brief Set the IQMC_PHASE_ADJ field to a new value. */
29905 #define XCVR_WR_IQMC_CAL_IQMC_PHASE_ADJ(base, value) (XCVR_RMW_IQMC_CAL(base, XCVR_IQMC_CAL_IQMC_PHASE_ADJ_MASK, XCVR_IQMC_CAL_IQMC_PHASE_ADJ(value)))
29906 #define XCVR_BWR_IQMC_CAL_IQMC_PHASE_ADJ(base, value) (BME_BFI32(&XCVR_IQMC_CAL_REG(base), ((uint32_t)(value) << XCVR_IQMC_CAL_IQMC_PHASE_ADJ_SHIFT), XCVR_IQMC_CAL_IQMC_PHASE_ADJ_SHIFT, XCVR_IQMC_CAL_IQMC_PHASE_ADJ_WIDTH))
29907 /*@}*/
29908 
29909 /*******************************************************************************
29910  * XCVR_TCA_AGC_VAL_3_0 - TCA AGC Step Values 3..0
29911  ******************************************************************************/
29912 
29913 /*!
29914  * @brief XCVR_TCA_AGC_VAL_3_0 - TCA AGC Step Values 3..0 (RW)
29915  *
29916  * Reset value: 0x3C242C14U
29917  */
29918 /*!
29919  * @name Constants and macros for entire XCVR_TCA_AGC_VAL_3_0 register
29920  */
29921 /*@{*/
29922 #define XCVR_RD_TCA_AGC_VAL_3_0(base) (XCVR_TCA_AGC_VAL_3_0_REG(base))
29923 #define XCVR_WR_TCA_AGC_VAL_3_0(base, value) (XCVR_TCA_AGC_VAL_3_0_REG(base) = (value))
29924 #define XCVR_RMW_TCA_AGC_VAL_3_0(base, mask, value) (XCVR_WR_TCA_AGC_VAL_3_0(base, (XCVR_RD_TCA_AGC_VAL_3_0(base) & ~(mask)) | (value)))
29925 #define XCVR_SET_TCA_AGC_VAL_3_0(base, value) (BME_OR32(&XCVR_TCA_AGC_VAL_3_0_REG(base), (uint32_t)(value)))
29926 #define XCVR_CLR_TCA_AGC_VAL_3_0(base, value) (BME_AND32(&XCVR_TCA_AGC_VAL_3_0_REG(base), (uint32_t)(~(value))))
29927 #define XCVR_TOG_TCA_AGC_VAL_3_0(base, value) (BME_XOR32(&XCVR_TCA_AGC_VAL_3_0_REG(base), (uint32_t)(value)))
29928 /*@}*/
29929 
29930 /*
29931  * Constants & macros for individual XCVR_TCA_AGC_VAL_3_0 bitfields
29932  */
29933 
29934 /*!
29935  * @name Register XCVR_TCA_AGC_VAL_3_0, field TCA_AGC_VAL_0[7:0] (RW)
29936  *
29937  * 4(x+8) value of TCA_AGC step 0, for RSSI calculation.
29938  */
29939 /*@{*/
29940 /*! @brief Read current value of the XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0 field. */
29941 #define XCVR_RD_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0(base) ((XCVR_TCA_AGC_VAL_3_0_REG(base) & XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0_MASK) >> XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0_SHIFT)
29942 #define XCVR_BRD_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_3_0_REG(base), XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0_SHIFT, XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0_WIDTH))
29943 
29944 /*! @brief Set the TCA_AGC_VAL_0 field to a new value. */
29945 #define XCVR_WR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0(base, value) (XCVR_RMW_TCA_AGC_VAL_3_0(base, XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0_MASK, XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0(value)))
29946 #define XCVR_BWR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_3_0_REG(base), ((uint32_t)(value) << XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0_SHIFT), XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0_SHIFT, XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_0_WIDTH))
29947 /*@}*/
29948 
29949 /*!
29950  * @name Register XCVR_TCA_AGC_VAL_3_0, field TCA_AGC_VAL_1[15:8] (RW)
29951  *
29952  * 4(x+8) value of TCA_AGC step 1, for RSSI calculation.
29953  */
29954 /*@{*/
29955 /*! @brief Read current value of the XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1 field. */
29956 #define XCVR_RD_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1(base) ((XCVR_TCA_AGC_VAL_3_0_REG(base) & XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1_MASK) >> XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1_SHIFT)
29957 #define XCVR_BRD_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_3_0_REG(base), XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1_SHIFT, XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1_WIDTH))
29958 
29959 /*! @brief Set the TCA_AGC_VAL_1 field to a new value. */
29960 #define XCVR_WR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1(base, value) (XCVR_RMW_TCA_AGC_VAL_3_0(base, XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1_MASK, XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1(value)))
29961 #define XCVR_BWR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_3_0_REG(base), ((uint32_t)(value) << XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1_SHIFT), XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1_SHIFT, XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_1_WIDTH))
29962 /*@}*/
29963 
29964 /*!
29965  * @name Register XCVR_TCA_AGC_VAL_3_0, field TCA_AGC_VAL_2[23:16] (RW)
29966  *
29967  * 4x value of TCA_AGC step 2, for RSSI calculation.
29968  */
29969 /*@{*/
29970 /*! @brief Read current value of the XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2 field. */
29971 #define XCVR_RD_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2(base) ((XCVR_TCA_AGC_VAL_3_0_REG(base) & XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2_MASK) >> XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2_SHIFT)
29972 #define XCVR_BRD_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_3_0_REG(base), XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2_SHIFT, XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2_WIDTH))
29973 
29974 /*! @brief Set the TCA_AGC_VAL_2 field to a new value. */
29975 #define XCVR_WR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2(base, value) (XCVR_RMW_TCA_AGC_VAL_3_0(base, XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2_MASK, XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2(value)))
29976 #define XCVR_BWR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_3_0_REG(base), ((uint32_t)(value) << XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2_SHIFT), XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2_SHIFT, XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_2_WIDTH))
29977 /*@}*/
29978 
29979 /*!
29980  * @name Register XCVR_TCA_AGC_VAL_3_0, field TCA_AGC_VAL_3[31:24] (RW)
29981  *
29982  * 4x value of TCA_AGC step 3, for RSSI calculation.
29983  */
29984 /*@{*/
29985 /*! @brief Read current value of the XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3 field. */
29986 #define XCVR_RD_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3(base) ((XCVR_TCA_AGC_VAL_3_0_REG(base) & XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3_MASK) >> XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3_SHIFT)
29987 #define XCVR_BRD_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_3_0_REG(base), XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3_SHIFT, XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3_WIDTH))
29988 
29989 /*! @brief Set the TCA_AGC_VAL_3 field to a new value. */
29990 #define XCVR_WR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3(base, value) (XCVR_RMW_TCA_AGC_VAL_3_0(base, XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3_MASK, XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3(value)))
29991 #define XCVR_BWR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_3_0_REG(base), ((uint32_t)(value) << XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3_SHIFT), XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3_SHIFT, XCVR_TCA_AGC_VAL_3_0_TCA_AGC_VAL_3_WIDTH))
29992 /*@}*/
29993 
29994 /*******************************************************************************
29995  * XCVR_TCA_AGC_VAL_7_4 - TCA AGC Step Values 7..4
29996  ******************************************************************************/
29997 
29998 /*!
29999  * @brief XCVR_TCA_AGC_VAL_7_4 - TCA AGC Step Values 7..4 (RW)
30000  *
30001  * Reset value: 0x9C846C54U
30002  */
30003 /*!
30004  * @name Constants and macros for entire XCVR_TCA_AGC_VAL_7_4 register
30005  */
30006 /*@{*/
30007 #define XCVR_RD_TCA_AGC_VAL_7_4(base) (XCVR_TCA_AGC_VAL_7_4_REG(base))
30008 #define XCVR_WR_TCA_AGC_VAL_7_4(base, value) (XCVR_TCA_AGC_VAL_7_4_REG(base) = (value))
30009 #define XCVR_RMW_TCA_AGC_VAL_7_4(base, mask, value) (XCVR_WR_TCA_AGC_VAL_7_4(base, (XCVR_RD_TCA_AGC_VAL_7_4(base) & ~(mask)) | (value)))
30010 #define XCVR_SET_TCA_AGC_VAL_7_4(base, value) (BME_OR32(&XCVR_TCA_AGC_VAL_7_4_REG(base), (uint32_t)(value)))
30011 #define XCVR_CLR_TCA_AGC_VAL_7_4(base, value) (BME_AND32(&XCVR_TCA_AGC_VAL_7_4_REG(base), (uint32_t)(~(value))))
30012 #define XCVR_TOG_TCA_AGC_VAL_7_4(base, value) (BME_XOR32(&XCVR_TCA_AGC_VAL_7_4_REG(base), (uint32_t)(value)))
30013 /*@}*/
30014 
30015 /*
30016  * Constants & macros for individual XCVR_TCA_AGC_VAL_7_4 bitfields
30017  */
30018 
30019 /*!
30020  * @name Register XCVR_TCA_AGC_VAL_7_4, field TCA_AGC_VAL_4[7:0] (RW)
30021  *
30022  * 4x value of TCA_AGC step 4, for RSSI calculation.
30023  */
30024 /*@{*/
30025 /*! @brief Read current value of the XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4 field. */
30026 #define XCVR_RD_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4(base) ((XCVR_TCA_AGC_VAL_7_4_REG(base) & XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4_MASK) >> XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4_SHIFT)
30027 #define XCVR_BRD_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_7_4_REG(base), XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4_SHIFT, XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4_WIDTH))
30028 
30029 /*! @brief Set the TCA_AGC_VAL_4 field to a new value. */
30030 #define XCVR_WR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4(base, value) (XCVR_RMW_TCA_AGC_VAL_7_4(base, XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4_MASK, XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4(value)))
30031 #define XCVR_BWR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_7_4_REG(base), ((uint32_t)(value) << XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4_SHIFT), XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4_SHIFT, XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_4_WIDTH))
30032 /*@}*/
30033 
30034 /*!
30035  * @name Register XCVR_TCA_AGC_VAL_7_4, field TCA_AGC_VAL_5[15:8] (RW)
30036  *
30037  * 4x value of TCA_AGC step 5, for RSSI calculation.
30038  */
30039 /*@{*/
30040 /*! @brief Read current value of the XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5 field. */
30041 #define XCVR_RD_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5(base) ((XCVR_TCA_AGC_VAL_7_4_REG(base) & XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5_MASK) >> XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5_SHIFT)
30042 #define XCVR_BRD_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_7_4_REG(base), XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5_SHIFT, XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5_WIDTH))
30043 
30044 /*! @brief Set the TCA_AGC_VAL_5 field to a new value. */
30045 #define XCVR_WR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5(base, value) (XCVR_RMW_TCA_AGC_VAL_7_4(base, XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5_MASK, XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5(value)))
30046 #define XCVR_BWR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_7_4_REG(base), ((uint32_t)(value) << XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5_SHIFT), XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5_SHIFT, XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_5_WIDTH))
30047 /*@}*/
30048 
30049 /*!
30050  * @name Register XCVR_TCA_AGC_VAL_7_4, field TCA_AGC_VAL_6[23:16] (RW)
30051  *
30052  * 4x value of TCA_AGC step 6, for RSSI calculation.
30053  */
30054 /*@{*/
30055 /*! @brief Read current value of the XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6 field. */
30056 #define XCVR_RD_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6(base) ((XCVR_TCA_AGC_VAL_7_4_REG(base) & XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6_MASK) >> XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6_SHIFT)
30057 #define XCVR_BRD_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_7_4_REG(base), XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6_SHIFT, XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6_WIDTH))
30058 
30059 /*! @brief Set the TCA_AGC_VAL_6 field to a new value. */
30060 #define XCVR_WR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6(base, value) (XCVR_RMW_TCA_AGC_VAL_7_4(base, XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6_MASK, XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6(value)))
30061 #define XCVR_BWR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_7_4_REG(base), ((uint32_t)(value) << XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6_SHIFT), XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6_SHIFT, XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_6_WIDTH))
30062 /*@}*/
30063 
30064 /*!
30065  * @name Register XCVR_TCA_AGC_VAL_7_4, field TCA_AGC_VAL_7[31:24] (RW)
30066  *
30067  * 4x value of TCA_AGC step 7, for RSSI calculation.
30068  */
30069 /*@{*/
30070 /*! @brief Read current value of the XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7 field. */
30071 #define XCVR_RD_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7(base) ((XCVR_TCA_AGC_VAL_7_4_REG(base) & XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7_MASK) >> XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7_SHIFT)
30072 #define XCVR_BRD_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_7_4_REG(base), XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7_SHIFT, XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7_WIDTH))
30073 
30074 /*! @brief Set the TCA_AGC_VAL_7 field to a new value. */
30075 #define XCVR_WR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7(base, value) (XCVR_RMW_TCA_AGC_VAL_7_4(base, XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7_MASK, XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7(value)))
30076 #define XCVR_BWR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_7_4_REG(base), ((uint32_t)(value) << XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7_SHIFT), XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7_SHIFT, XCVR_TCA_AGC_VAL_7_4_TCA_AGC_VAL_7_WIDTH))
30077 /*@}*/
30078 
30079 /*******************************************************************************
30080  * XCVR_TCA_AGC_VAL_8 - TCA AGC Step Values 8
30081  ******************************************************************************/
30082 
30083 /*!
30084  * @brief XCVR_TCA_AGC_VAL_8 - TCA AGC Step Values 8 (RW)
30085  *
30086  * Reset value: 0x000000B4U
30087  */
30088 /*!
30089  * @name Constants and macros for entire XCVR_TCA_AGC_VAL_8 register
30090  */
30091 /*@{*/
30092 #define XCVR_RD_TCA_AGC_VAL_8(base) (XCVR_TCA_AGC_VAL_8_REG(base))
30093 #define XCVR_WR_TCA_AGC_VAL_8(base, value) (XCVR_TCA_AGC_VAL_8_REG(base) = (value))
30094 #define XCVR_RMW_TCA_AGC_VAL_8(base, mask, value) (XCVR_WR_TCA_AGC_VAL_8(base, (XCVR_RD_TCA_AGC_VAL_8(base) & ~(mask)) | (value)))
30095 #define XCVR_SET_TCA_AGC_VAL_8(base, value) (BME_OR32(&XCVR_TCA_AGC_VAL_8_REG(base), (uint32_t)(value)))
30096 #define XCVR_CLR_TCA_AGC_VAL_8(base, value) (BME_AND32(&XCVR_TCA_AGC_VAL_8_REG(base), (uint32_t)(~(value))))
30097 #define XCVR_TOG_TCA_AGC_VAL_8(base, value) (BME_XOR32(&XCVR_TCA_AGC_VAL_8_REG(base), (uint32_t)(value)))
30098 /*@}*/
30099 
30100 /*
30101  * Constants & macros for individual XCVR_TCA_AGC_VAL_8 bitfields
30102  */
30103 
30104 /*!
30105  * @name Register XCVR_TCA_AGC_VAL_8, field TCA_AGC_VAL_8[7:0] (RW)
30106  *
30107  * 4x value of TCA_AGC step 8, for RSSI calculation.
30108  */
30109 /*@{*/
30110 /*! @brief Read current value of the XCVR_TCA_AGC_VAL_8_TCA_AGC_VAL_8 field. */
30111 #define XCVR_RD_TCA_AGC_VAL_8_TCA_AGC_VAL_8(base) ((XCVR_TCA_AGC_VAL_8_REG(base) & XCVR_TCA_AGC_VAL_8_TCA_AGC_VAL_8_MASK) >> XCVR_TCA_AGC_VAL_8_TCA_AGC_VAL_8_SHIFT)
30112 #define XCVR_BRD_TCA_AGC_VAL_8_TCA_AGC_VAL_8(base) (BME_UBFX32(&XCVR_TCA_AGC_VAL_8_REG(base), XCVR_TCA_AGC_VAL_8_TCA_AGC_VAL_8_SHIFT, XCVR_TCA_AGC_VAL_8_TCA_AGC_VAL_8_WIDTH))
30113 
30114 /*! @brief Set the TCA_AGC_VAL_8 field to a new value. */
30115 #define XCVR_WR_TCA_AGC_VAL_8_TCA_AGC_VAL_8(base, value) (XCVR_RMW_TCA_AGC_VAL_8(base, XCVR_TCA_AGC_VAL_8_TCA_AGC_VAL_8_MASK, XCVR_TCA_AGC_VAL_8_TCA_AGC_VAL_8(value)))
30116 #define XCVR_BWR_TCA_AGC_VAL_8_TCA_AGC_VAL_8(base, value) (BME_BFI32(&XCVR_TCA_AGC_VAL_8_REG(base), ((uint32_t)(value) << XCVR_TCA_AGC_VAL_8_TCA_AGC_VAL_8_SHIFT), XCVR_TCA_AGC_VAL_8_TCA_AGC_VAL_8_SHIFT, XCVR_TCA_AGC_VAL_8_TCA_AGC_VAL_8_WIDTH))
30117 /*@}*/
30118 
30119 /*******************************************************************************
30120  * XCVR_BBF_RES_TUNE_VAL_7_0 - BBF Resistor Tune Values 7..0
30121  ******************************************************************************/
30122 
30123 /*!
30124  * @brief XCVR_BBF_RES_TUNE_VAL_7_0 - BBF Resistor Tune Values 7..0 (RW)
30125  *
30126  * Reset value: 0x00000000U
30127  */
30128 /*!
30129  * @name Constants and macros for entire XCVR_BBF_RES_TUNE_VAL_7_0 register
30130  */
30131 /*@{*/
30132 #define XCVR_RD_BBF_RES_TUNE_VAL_7_0(base) (XCVR_BBF_RES_TUNE_VAL_7_0_REG(base))
30133 #define XCVR_WR_BBF_RES_TUNE_VAL_7_0(base, value) (XCVR_BBF_RES_TUNE_VAL_7_0_REG(base) = (value))
30134 #define XCVR_RMW_BBF_RES_TUNE_VAL_7_0(base, mask, value) (XCVR_WR_BBF_RES_TUNE_VAL_7_0(base, (XCVR_RD_BBF_RES_TUNE_VAL_7_0(base) & ~(mask)) | (value)))
30135 #define XCVR_SET_BBF_RES_TUNE_VAL_7_0(base, value) (BME_OR32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base), (uint32_t)(value)))
30136 #define XCVR_CLR_BBF_RES_TUNE_VAL_7_0(base, value) (BME_AND32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base), (uint32_t)(~(value))))
30137 #define XCVR_TOG_BBF_RES_TUNE_VAL_7_0(base, value) (BME_XOR32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base), (uint32_t)(value)))
30138 /*@}*/
30139 
30140 /*
30141  * Constants & macros for individual XCVR_BBF_RES_TUNE_VAL_7_0 bitfields
30142  */
30143 
30144 /*!
30145  * @name Register XCVR_BBF_RES_TUNE_VAL_7_0, field BBF_RES_TUNE_VAL_0[3:0] (RW)
30146  *
30147  * Signed, 2x offset value of bbf_res_tune step 0 agc delta.
30148  */
30149 /*@{*/
30150 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0 field. */
30151 #define XCVR_RD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0(base) ((XCVR_BBF_RES_TUNE_VAL_7_0_REG(base) & XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0_MASK) >> XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0_SHIFT)
30152 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base), XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0_SHIFT, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0_WIDTH))
30153 
30154 /*! @brief Set the BBF_RES_TUNE_VAL_0 field to a new value. */
30155 #define XCVR_WR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_7_0(base, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0_MASK, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0(value)))
30156 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0_SHIFT), XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0_SHIFT, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_0_WIDTH))
30157 /*@}*/
30158 
30159 /*!
30160  * @name Register XCVR_BBF_RES_TUNE_VAL_7_0, field BBF_RES_TUNE_VAL_1[7:4] (RW)
30161  *
30162  * Signed, 2x offset value of bbf_res_tune step 1 agc delta.
30163  */
30164 /*@{*/
30165 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1 field. */
30166 #define XCVR_RD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1(base) ((XCVR_BBF_RES_TUNE_VAL_7_0_REG(base) & XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1_MASK) >> XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1_SHIFT)
30167 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base), XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1_SHIFT, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1_WIDTH))
30168 
30169 /*! @brief Set the BBF_RES_TUNE_VAL_1 field to a new value. */
30170 #define XCVR_WR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_7_0(base, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1_MASK, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1(value)))
30171 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1_SHIFT), XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1_SHIFT, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_1_WIDTH))
30172 /*@}*/
30173 
30174 /*!
30175  * @name Register XCVR_BBF_RES_TUNE_VAL_7_0, field BBF_RES_TUNE_VAL_2[11:8] (RW)
30176  *
30177  * Signed, 2x offset value of bbf_res_tune step 2 agc delta.
30178  */
30179 /*@{*/
30180 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2 field. */
30181 #define XCVR_RD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2(base) ((XCVR_BBF_RES_TUNE_VAL_7_0_REG(base) & XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2_MASK) >> XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2_SHIFT)
30182 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base), XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2_SHIFT, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2_WIDTH))
30183 
30184 /*! @brief Set the BBF_RES_TUNE_VAL_2 field to a new value. */
30185 #define XCVR_WR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_7_0(base, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2_MASK, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2(value)))
30186 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2_SHIFT), XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2_SHIFT, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_2_WIDTH))
30187 /*@}*/
30188 
30189 /*!
30190  * @name Register XCVR_BBF_RES_TUNE_VAL_7_0, field BBF_RES_TUNE_VAL_3[15:12] (RW)
30191  *
30192  * Signed, 2x offset value of bbf_res_tune step 3 agc delta.
30193  */
30194 /*@{*/
30195 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3 field. */
30196 #define XCVR_RD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3(base) ((XCVR_BBF_RES_TUNE_VAL_7_0_REG(base) & XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3_MASK) >> XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3_SHIFT)
30197 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base), XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3_SHIFT, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3_WIDTH))
30198 
30199 /*! @brief Set the BBF_RES_TUNE_VAL_3 field to a new value. */
30200 #define XCVR_WR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_7_0(base, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3_MASK, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3(value)))
30201 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3_SHIFT), XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3_SHIFT, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_3_WIDTH))
30202 /*@}*/
30203 
30204 /*!
30205  * @name Register XCVR_BBF_RES_TUNE_VAL_7_0, field BBF_RES_TUNE_VAL_4[19:16] (RW)
30206  *
30207  * Signed, 2x offset value of bbf_res_tune step 4 agc delta.
30208  */
30209 /*@{*/
30210 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4 field. */
30211 #define XCVR_RD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4(base) ((XCVR_BBF_RES_TUNE_VAL_7_0_REG(base) & XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4_MASK) >> XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4_SHIFT)
30212 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base), XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4_SHIFT, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4_WIDTH))
30213 
30214 /*! @brief Set the BBF_RES_TUNE_VAL_4 field to a new value. */
30215 #define XCVR_WR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_7_0(base, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4_MASK, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4(value)))
30216 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4_SHIFT), XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4_SHIFT, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_4_WIDTH))
30217 /*@}*/
30218 
30219 /*!
30220  * @name Register XCVR_BBF_RES_TUNE_VAL_7_0, field BBF_RES_TUNE_VAL_5[23:20] (RW)
30221  *
30222  * Signed, 2x offset value of bbf_res_tune step 5 agc delta.
30223  */
30224 /*@{*/
30225 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5 field. */
30226 #define XCVR_RD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5(base) ((XCVR_BBF_RES_TUNE_VAL_7_0_REG(base) & XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5_MASK) >> XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5_SHIFT)
30227 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base), XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5_SHIFT, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5_WIDTH))
30228 
30229 /*! @brief Set the BBF_RES_TUNE_VAL_5 field to a new value. */
30230 #define XCVR_WR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_7_0(base, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5_MASK, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5(value)))
30231 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5_SHIFT), XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5_SHIFT, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_5_WIDTH))
30232 /*@}*/
30233 
30234 /*!
30235  * @name Register XCVR_BBF_RES_TUNE_VAL_7_0, field BBF_RES_TUNE_VAL_6[27:24] (RW)
30236  *
30237  * Signed, 2x offset value of bbf_res_tune step 6 agc delta.
30238  */
30239 /*@{*/
30240 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6 field. */
30241 #define XCVR_RD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6(base) ((XCVR_BBF_RES_TUNE_VAL_7_0_REG(base) & XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6_MASK) >> XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6_SHIFT)
30242 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base), XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6_SHIFT, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6_WIDTH))
30243 
30244 /*! @brief Set the BBF_RES_TUNE_VAL_6 field to a new value. */
30245 #define XCVR_WR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_7_0(base, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6_MASK, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6(value)))
30246 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6_SHIFT), XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6_SHIFT, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_6_WIDTH))
30247 /*@}*/
30248 
30249 /*!
30250  * @name Register XCVR_BBF_RES_TUNE_VAL_7_0, field BBF_RES_TUNE_VAL_7[31:28] (RW)
30251  *
30252  * Signed, 2x offset value of bbf_res_tune step 7 agc delta.
30253  */
30254 /*@{*/
30255 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7 field. */
30256 #define XCVR_RD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7(base) ((XCVR_BBF_RES_TUNE_VAL_7_0_REG(base) & XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7_MASK) >> XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7_SHIFT)
30257 #define XCVR_BRD_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base), XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7_SHIFT, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7_WIDTH))
30258 
30259 /*! @brief Set the BBF_RES_TUNE_VAL_7 field to a new value. */
30260 #define XCVR_WR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_7_0(base, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7_MASK, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7(value)))
30261 #define XCVR_BWR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_VAL_7_0_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7_SHIFT), XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7_SHIFT, XCVR_BBF_RES_TUNE_VAL_7_0_BBF_RES_TUNE_VAL_7_WIDTH))
30262 /*@}*/
30263 
30264 /*******************************************************************************
30265  * XCVR_BBF_RES_TUNE_VAL_10_8 - BBF Resistor Tune Values 10..8
30266  ******************************************************************************/
30267 
30268 /*!
30269  * @brief XCVR_BBF_RES_TUNE_VAL_10_8 - BBF Resistor Tune Values 10..8 (RW)
30270  *
30271  * Reset value: 0x00000000U
30272  */
30273 /*!
30274  * @name Constants and macros for entire XCVR_BBF_RES_TUNE_VAL_10_8 register
30275  */
30276 /*@{*/
30277 #define XCVR_RD_BBF_RES_TUNE_VAL_10_8(base) (XCVR_BBF_RES_TUNE_VAL_10_8_REG(base))
30278 #define XCVR_WR_BBF_RES_TUNE_VAL_10_8(base, value) (XCVR_BBF_RES_TUNE_VAL_10_8_REG(base) = (value))
30279 #define XCVR_RMW_BBF_RES_TUNE_VAL_10_8(base, mask, value) (XCVR_WR_BBF_RES_TUNE_VAL_10_8(base, (XCVR_RD_BBF_RES_TUNE_VAL_10_8(base) & ~(mask)) | (value)))
30280 #define XCVR_SET_BBF_RES_TUNE_VAL_10_8(base, value) (BME_OR32(&XCVR_BBF_RES_TUNE_VAL_10_8_REG(base), (uint32_t)(value)))
30281 #define XCVR_CLR_BBF_RES_TUNE_VAL_10_8(base, value) (BME_AND32(&XCVR_BBF_RES_TUNE_VAL_10_8_REG(base), (uint32_t)(~(value))))
30282 #define XCVR_TOG_BBF_RES_TUNE_VAL_10_8(base, value) (BME_XOR32(&XCVR_BBF_RES_TUNE_VAL_10_8_REG(base), (uint32_t)(value)))
30283 /*@}*/
30284 
30285 /*
30286  * Constants & macros for individual XCVR_BBF_RES_TUNE_VAL_10_8 bitfields
30287  */
30288 
30289 /*!
30290  * @name Register XCVR_BBF_RES_TUNE_VAL_10_8, field BBF_RES_TUNE_VAL_8[3:0] (RW)
30291  *
30292  * Signed, 2x offset value of bbf_res_tune step 8 agc delta.
30293  */
30294 /*@{*/
30295 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8 field. */
30296 #define XCVR_RD_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8(base) ((XCVR_BBF_RES_TUNE_VAL_10_8_REG(base) & XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8_MASK) >> XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8_SHIFT)
30297 #define XCVR_BRD_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_10_8_REG(base), XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8_SHIFT, XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8_WIDTH))
30298 
30299 /*! @brief Set the BBF_RES_TUNE_VAL_8 field to a new value. */
30300 #define XCVR_WR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_10_8(base, XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8_MASK, XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8(value)))
30301 #define XCVR_BWR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_VAL_10_8_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8_SHIFT), XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8_SHIFT, XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_8_WIDTH))
30302 /*@}*/
30303 
30304 /*!
30305  * @name Register XCVR_BBF_RES_TUNE_VAL_10_8, field BBF_RES_TUNE_VAL_9[7:4] (RW)
30306  *
30307  * Signed, 2x offset value of bbf_res_tune step 9 agc delta.
30308  */
30309 /*@{*/
30310 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9 field. */
30311 #define XCVR_RD_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9(base) ((XCVR_BBF_RES_TUNE_VAL_10_8_REG(base) & XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9_MASK) >> XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9_SHIFT)
30312 #define XCVR_BRD_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_10_8_REG(base), XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9_SHIFT, XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9_WIDTH))
30313 
30314 /*! @brief Set the BBF_RES_TUNE_VAL_9 field to a new value. */
30315 #define XCVR_WR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_10_8(base, XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9_MASK, XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9(value)))
30316 #define XCVR_BWR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_VAL_10_8_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9_SHIFT), XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9_SHIFT, XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_9_WIDTH))
30317 /*@}*/
30318 
30319 /*!
30320  * @name Register XCVR_BBF_RES_TUNE_VAL_10_8, field BBF_RES_TUNE_VAL_10[11:8] (RW)
30321  *
30322  * Signed, 2x offset value of bbf_res_tune step 10 agc delta.
30323  */
30324 /*@{*/
30325 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10 field. */
30326 #define XCVR_RD_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10(base) ((XCVR_BBF_RES_TUNE_VAL_10_8_REG(base) & XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10_MASK) >> XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10_SHIFT)
30327 #define XCVR_BRD_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_VAL_10_8_REG(base), XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10_SHIFT, XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10_WIDTH))
30328 
30329 /*! @brief Set the BBF_RES_TUNE_VAL_10 field to a new value. */
30330 #define XCVR_WR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10(base, value) (XCVR_RMW_BBF_RES_TUNE_VAL_10_8(base, XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10_MASK, XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10(value)))
30331 #define XCVR_BWR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_VAL_10_8_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10_SHIFT), XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10_SHIFT, XCVR_BBF_RES_TUNE_VAL_10_8_BBF_RES_TUNE_VAL_10_WIDTH))
30332 /*@}*/
30333 
30334 /*******************************************************************************
30335  * XCVR_TCA_AGC_LIN_VAL_2_0 - TCA AGC Linear Gain Values 2..0
30336  ******************************************************************************/
30337 
30338 /*!
30339  * @brief XCVR_TCA_AGC_LIN_VAL_2_0 - TCA AGC Linear Gain Values 2..0 (RW)
30340  *
30341  * Reset value: 0x00000000U
30342  */
30343 /*!
30344  * @name Constants and macros for entire XCVR_TCA_AGC_LIN_VAL_2_0 register
30345  */
30346 /*@{*/
30347 #define XCVR_RD_TCA_AGC_LIN_VAL_2_0(base) (XCVR_TCA_AGC_LIN_VAL_2_0_REG(base))
30348 #define XCVR_WR_TCA_AGC_LIN_VAL_2_0(base, value) (XCVR_TCA_AGC_LIN_VAL_2_0_REG(base) = (value))
30349 #define XCVR_RMW_TCA_AGC_LIN_VAL_2_0(base, mask, value) (XCVR_WR_TCA_AGC_LIN_VAL_2_0(base, (XCVR_RD_TCA_AGC_LIN_VAL_2_0(base) & ~(mask)) | (value)))
30350 #define XCVR_SET_TCA_AGC_LIN_VAL_2_0(base, value) (BME_OR32(&XCVR_TCA_AGC_LIN_VAL_2_0_REG(base), (uint32_t)(value)))
30351 #define XCVR_CLR_TCA_AGC_LIN_VAL_2_0(base, value) (BME_AND32(&XCVR_TCA_AGC_LIN_VAL_2_0_REG(base), (uint32_t)(~(value))))
30352 #define XCVR_TOG_TCA_AGC_LIN_VAL_2_0(base, value) (BME_XOR32(&XCVR_TCA_AGC_LIN_VAL_2_0_REG(base), (uint32_t)(value)))
30353 /*@}*/
30354 
30355 /*
30356  * Constants & macros for individual XCVR_TCA_AGC_LIN_VAL_2_0 bitfields
30357  */
30358 
30359 /*!
30360  * @name Register XCVR_TCA_AGC_LIN_VAL_2_0, field TCA_AGC_LIN_VAL_0[9:0] (RW)
30361  *
30362  * Linear gain (8.2).
30363  */
30364 /*@{*/
30365 /*! @brief Read current value of the XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0 field. */
30366 #define XCVR_RD_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0(base) ((XCVR_TCA_AGC_LIN_VAL_2_0_REG(base) & XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0_MASK) >> XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0_SHIFT)
30367 #define XCVR_BRD_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_2_0_REG(base), XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0_SHIFT, XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0_WIDTH))
30368 
30369 /*! @brief Set the TCA_AGC_LIN_VAL_0 field to a new value. */
30370 #define XCVR_WR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0(base, value) (XCVR_RMW_TCA_AGC_LIN_VAL_2_0(base, XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0_MASK, XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0(value)))
30371 #define XCVR_BWR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VAL_2_0_REG(base), ((uint32_t)(value) << XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0_SHIFT), XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0_SHIFT, XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_0_WIDTH))
30372 /*@}*/
30373 
30374 /*!
30375  * @name Register XCVR_TCA_AGC_LIN_VAL_2_0, field TCA_AGC_LIN_VAL_1[19:10] (RW)
30376  *
30377  * LNM linear gain value for index 1, e.g. nominal value is 10^(3/20). Stored
30378  * with 2 fractional bits, e.g. round([10^(3/20)]*2^2) = 6decimal
30379  */
30380 /*@{*/
30381 /*! @brief Read current value of the XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1 field. */
30382 #define XCVR_RD_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1(base) ((XCVR_TCA_AGC_LIN_VAL_2_0_REG(base) & XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1_MASK) >> XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1_SHIFT)
30383 #define XCVR_BRD_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_2_0_REG(base), XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1_SHIFT, XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1_WIDTH))
30384 
30385 /*! @brief Set the TCA_AGC_LIN_VAL_1 field to a new value. */
30386 #define XCVR_WR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1(base, value) (XCVR_RMW_TCA_AGC_LIN_VAL_2_0(base, XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1_MASK, XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1(value)))
30387 #define XCVR_BWR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VAL_2_0_REG(base), ((uint32_t)(value) << XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1_SHIFT), XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1_SHIFT, XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_1_WIDTH))
30388 /*@}*/
30389 
30390 /*!
30391  * @name Register XCVR_TCA_AGC_LIN_VAL_2_0, field TCA_AGC_LIN_VAL_2[29:20] (RW)
30392  *
30393  * LNM linear gain value for index 2, e.g. nominal value is 10^(9/20). Stored
30394  * with 2 fractional bits, e.g. round([10^(9/20)]*2^2) = 11decimal
30395  */
30396 /*@{*/
30397 /*! @brief Read current value of the XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2 field. */
30398 #define XCVR_RD_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2(base) ((XCVR_TCA_AGC_LIN_VAL_2_0_REG(base) & XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2_MASK) >> XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2_SHIFT)
30399 #define XCVR_BRD_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_2_0_REG(base), XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2_SHIFT, XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2_WIDTH))
30400 
30401 /*! @brief Set the TCA_AGC_LIN_VAL_2 field to a new value. */
30402 #define XCVR_WR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2(base, value) (XCVR_RMW_TCA_AGC_LIN_VAL_2_0(base, XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2_MASK, XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2(value)))
30403 #define XCVR_BWR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VAL_2_0_REG(base), ((uint32_t)(value) << XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2_SHIFT), XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2_SHIFT, XCVR_TCA_AGC_LIN_VAL_2_0_TCA_AGC_LIN_VAL_2_WIDTH))
30404 /*@}*/
30405 
30406 /*******************************************************************************
30407  * XCVR_TCA_AGC_LIN_VAL_5_3 - TCA AGC Linear Gain Values 5..3
30408  ******************************************************************************/
30409 
30410 /*!
30411  * @brief XCVR_TCA_AGC_LIN_VAL_5_3 - TCA AGC Linear Gain Values 5..3 (RW)
30412  *
30413  * Reset value: 0x00000000U
30414  */
30415 /*!
30416  * @name Constants and macros for entire XCVR_TCA_AGC_LIN_VAL_5_3 register
30417  */
30418 /*@{*/
30419 #define XCVR_RD_TCA_AGC_LIN_VAL_5_3(base) (XCVR_TCA_AGC_LIN_VAL_5_3_REG(base))
30420 #define XCVR_WR_TCA_AGC_LIN_VAL_5_3(base, value) (XCVR_TCA_AGC_LIN_VAL_5_3_REG(base) = (value))
30421 #define XCVR_RMW_TCA_AGC_LIN_VAL_5_3(base, mask, value) (XCVR_WR_TCA_AGC_LIN_VAL_5_3(base, (XCVR_RD_TCA_AGC_LIN_VAL_5_3(base) & ~(mask)) | (value)))
30422 #define XCVR_SET_TCA_AGC_LIN_VAL_5_3(base, value) (BME_OR32(&XCVR_TCA_AGC_LIN_VAL_5_3_REG(base), (uint32_t)(value)))
30423 #define XCVR_CLR_TCA_AGC_LIN_VAL_5_3(base, value) (BME_AND32(&XCVR_TCA_AGC_LIN_VAL_5_3_REG(base), (uint32_t)(~(value))))
30424 #define XCVR_TOG_TCA_AGC_LIN_VAL_5_3(base, value) (BME_XOR32(&XCVR_TCA_AGC_LIN_VAL_5_3_REG(base), (uint32_t)(value)))
30425 /*@}*/
30426 
30427 /*
30428  * Constants & macros for individual XCVR_TCA_AGC_LIN_VAL_5_3 bitfields
30429  */
30430 
30431 /*!
30432  * @name Register XCVR_TCA_AGC_LIN_VAL_5_3, field TCA_AGC_LIN_VAL_3[9:0] (RW)
30433  *
30434  * LNM linear gain value for index 3, e.g. nominal value is 10^(15/20). Stored
30435  * with 2 fractional bits, e.g. round([10^(15/20)]*2^2) = 22decimal
30436  */
30437 /*@{*/
30438 /*! @brief Read current value of the XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3 field. */
30439 #define XCVR_RD_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3(base) ((XCVR_TCA_AGC_LIN_VAL_5_3_REG(base) & XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3_MASK) >> XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3_SHIFT)
30440 #define XCVR_BRD_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_5_3_REG(base), XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3_SHIFT, XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3_WIDTH))
30441 
30442 /*! @brief Set the TCA_AGC_LIN_VAL_3 field to a new value. */
30443 #define XCVR_WR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3(base, value) (XCVR_RMW_TCA_AGC_LIN_VAL_5_3(base, XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3_MASK, XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3(value)))
30444 #define XCVR_BWR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VAL_5_3_REG(base), ((uint32_t)(value) << XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3_SHIFT), XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3_SHIFT, XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_3_WIDTH))
30445 /*@}*/
30446 
30447 /*!
30448  * @name Register XCVR_TCA_AGC_LIN_VAL_5_3, field TCA_AGC_LIN_VAL_4[19:10] (RW)
30449  *
30450  * LNM linear gain value for index 4, e.g. nominal value is 10^(21/20). Stored
30451  * with 2 fractional bits, e.g. round([10^(21/20)]*2^2) = 45decimal
30452  */
30453 /*@{*/
30454 /*! @brief Read current value of the XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4 field. */
30455 #define XCVR_RD_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4(base) ((XCVR_TCA_AGC_LIN_VAL_5_3_REG(base) & XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4_MASK) >> XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4_SHIFT)
30456 #define XCVR_BRD_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_5_3_REG(base), XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4_SHIFT, XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4_WIDTH))
30457 
30458 /*! @brief Set the TCA_AGC_LIN_VAL_4 field to a new value. */
30459 #define XCVR_WR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4(base, value) (XCVR_RMW_TCA_AGC_LIN_VAL_5_3(base, XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4_MASK, XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4(value)))
30460 #define XCVR_BWR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VAL_5_3_REG(base), ((uint32_t)(value) << XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4_SHIFT), XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4_SHIFT, XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_4_WIDTH))
30461 /*@}*/
30462 
30463 /*!
30464  * @name Register XCVR_TCA_AGC_LIN_VAL_5_3, field TCA_AGC_LIN_VAL_5[29:20] (RW)
30465  *
30466  * LNM linear gain value for index 5, e.g. nominal value is 10^(27/20). Stored
30467  * with 2 fractional bits, e.g. round([10^(27/20)]*2^2) = 90decimal
30468  */
30469 /*@{*/
30470 /*! @brief Read current value of the XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5 field. */
30471 #define XCVR_RD_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5(base) ((XCVR_TCA_AGC_LIN_VAL_5_3_REG(base) & XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5_MASK) >> XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5_SHIFT)
30472 #define XCVR_BRD_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_5_3_REG(base), XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5_SHIFT, XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5_WIDTH))
30473 
30474 /*! @brief Set the TCA_AGC_LIN_VAL_5 field to a new value. */
30475 #define XCVR_WR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5(base, value) (XCVR_RMW_TCA_AGC_LIN_VAL_5_3(base, XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5_MASK, XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5(value)))
30476 #define XCVR_BWR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VAL_5_3_REG(base), ((uint32_t)(value) << XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5_SHIFT), XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5_SHIFT, XCVR_TCA_AGC_LIN_VAL_5_3_TCA_AGC_LIN_VAL_5_WIDTH))
30477 /*@}*/
30478 
30479 /*******************************************************************************
30480  * XCVR_TCA_AGC_LIN_VAL_8_6 - TCA AGC Linear Gain Values 8..6
30481  ******************************************************************************/
30482 
30483 /*!
30484  * @brief XCVR_TCA_AGC_LIN_VAL_8_6 - TCA AGC Linear Gain Values 8..6 (RW)
30485  *
30486  * Reset value: 0x00000000U
30487  */
30488 /*!
30489  * @name Constants and macros for entire XCVR_TCA_AGC_LIN_VAL_8_6 register
30490  */
30491 /*@{*/
30492 #define XCVR_RD_TCA_AGC_LIN_VAL_8_6(base) (XCVR_TCA_AGC_LIN_VAL_8_6_REG(base))
30493 #define XCVR_WR_TCA_AGC_LIN_VAL_8_6(base, value) (XCVR_TCA_AGC_LIN_VAL_8_6_REG(base) = (value))
30494 #define XCVR_RMW_TCA_AGC_LIN_VAL_8_6(base, mask, value) (XCVR_WR_TCA_AGC_LIN_VAL_8_6(base, (XCVR_RD_TCA_AGC_LIN_VAL_8_6(base) & ~(mask)) | (value)))
30495 #define XCVR_SET_TCA_AGC_LIN_VAL_8_6(base, value) (BME_OR32(&XCVR_TCA_AGC_LIN_VAL_8_6_REG(base), (uint32_t)(value)))
30496 #define XCVR_CLR_TCA_AGC_LIN_VAL_8_6(base, value) (BME_AND32(&XCVR_TCA_AGC_LIN_VAL_8_6_REG(base), (uint32_t)(~(value))))
30497 #define XCVR_TOG_TCA_AGC_LIN_VAL_8_6(base, value) (BME_XOR32(&XCVR_TCA_AGC_LIN_VAL_8_6_REG(base), (uint32_t)(value)))
30498 /*@}*/
30499 
30500 /*
30501  * Constants & macros for individual XCVR_TCA_AGC_LIN_VAL_8_6 bitfields
30502  */
30503 
30504 /*!
30505  * @name Register XCVR_TCA_AGC_LIN_VAL_8_6, field TCA_AGC_LIN_VAL_6[9:0] (RW)
30506  *
30507  * LNM linear gain value for index 6, e.g. nominal value is 10^(33/20). Stored
30508  * with 2 fractional bits, e.g. round([10^(33/20)]*2^2) = 179decimal
30509  */
30510 /*@{*/
30511 /*! @brief Read current value of the XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6 field. */
30512 #define XCVR_RD_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6(base) ((XCVR_TCA_AGC_LIN_VAL_8_6_REG(base) & XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6_MASK) >> XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6_SHIFT)
30513 #define XCVR_BRD_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_8_6_REG(base), XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6_SHIFT, XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6_WIDTH))
30514 
30515 /*! @brief Set the TCA_AGC_LIN_VAL_6 field to a new value. */
30516 #define XCVR_WR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6(base, value) (XCVR_RMW_TCA_AGC_LIN_VAL_8_6(base, XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6_MASK, XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6(value)))
30517 #define XCVR_BWR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VAL_8_6_REG(base), ((uint32_t)(value) << XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6_SHIFT), XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6_SHIFT, XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_6_WIDTH))
30518 /*@}*/
30519 
30520 /*!
30521  * @name Register XCVR_TCA_AGC_LIN_VAL_8_6, field TCA_AGC_LIN_VAL_7[19:10] (RW)
30522  *
30523  * LNM linear gain value for index 7, e.g. nominal value is 10^(39/20). Stored
30524  * with 2 fractional bits, e.g. round([10^(39/20)]*2^2) = 357decimal
30525  */
30526 /*@{*/
30527 /*! @brief Read current value of the XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7 field. */
30528 #define XCVR_RD_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7(base) ((XCVR_TCA_AGC_LIN_VAL_8_6_REG(base) & XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7_MASK) >> XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7_SHIFT)
30529 #define XCVR_BRD_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_8_6_REG(base), XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7_SHIFT, XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7_WIDTH))
30530 
30531 /*! @brief Set the TCA_AGC_LIN_VAL_7 field to a new value. */
30532 #define XCVR_WR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7(base, value) (XCVR_RMW_TCA_AGC_LIN_VAL_8_6(base, XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7_MASK, XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7(value)))
30533 #define XCVR_BWR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VAL_8_6_REG(base), ((uint32_t)(value) << XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7_SHIFT), XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7_SHIFT, XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_7_WIDTH))
30534 /*@}*/
30535 
30536 /*!
30537  * @name Register XCVR_TCA_AGC_LIN_VAL_8_6, field TCA_AGC_LIN_VAL_8[29:20] (RW)
30538  *
30539  * LNM linear gain value for index 8, e.g. nominal value is 10^(45/20). Stored
30540  * with 2 fractional bits, e.g. round([10^(45/20)]*2^2) = 711decimal
30541  */
30542 /*@{*/
30543 /*! @brief Read current value of the XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8 field. */
30544 #define XCVR_RD_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8(base) ((XCVR_TCA_AGC_LIN_VAL_8_6_REG(base) & XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8_MASK) >> XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8_SHIFT)
30545 #define XCVR_BRD_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8(base) (BME_UBFX32(&XCVR_TCA_AGC_LIN_VAL_8_6_REG(base), XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8_SHIFT, XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8_WIDTH))
30546 
30547 /*! @brief Set the TCA_AGC_LIN_VAL_8 field to a new value. */
30548 #define XCVR_WR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8(base, value) (XCVR_RMW_TCA_AGC_LIN_VAL_8_6(base, XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8_MASK, XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8(value)))
30549 #define XCVR_BWR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8(base, value) (BME_BFI32(&XCVR_TCA_AGC_LIN_VAL_8_6_REG(base), ((uint32_t)(value) << XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8_SHIFT), XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8_SHIFT, XCVR_TCA_AGC_LIN_VAL_8_6_TCA_AGC_LIN_VAL_8_WIDTH))
30550 /*@}*/
30551 
30552 /*******************************************************************************
30553  * XCVR_BBF_RES_TUNE_LIN_VAL_3_0 - BBF Resistor Tune Values 3..0
30554  ******************************************************************************/
30555 
30556 /*!
30557  * @brief XCVR_BBF_RES_TUNE_LIN_VAL_3_0 - BBF Resistor Tune Values 3..0 (RW)
30558  *
30559  * Reset value: 0x00000000U
30560  */
30561 /*!
30562  * @name Constants and macros for entire XCVR_BBF_RES_TUNE_LIN_VAL_3_0 register
30563  */
30564 /*@{*/
30565 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_3_0(base) (XCVR_BBF_RES_TUNE_LIN_VAL_3_0_REG(base))
30566 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_3_0(base, value) (XCVR_BBF_RES_TUNE_LIN_VAL_3_0_REG(base) = (value))
30567 #define XCVR_RMW_BBF_RES_TUNE_LIN_VAL_3_0(base, mask, value) (XCVR_WR_BBF_RES_TUNE_LIN_VAL_3_0(base, (XCVR_RD_BBF_RES_TUNE_LIN_VAL_3_0(base) & ~(mask)) | (value)))
30568 #define XCVR_SET_BBF_RES_TUNE_LIN_VAL_3_0(base, value) (BME_OR32(&XCVR_BBF_RES_TUNE_LIN_VAL_3_0_REG(base), (uint32_t)(value)))
30569 #define XCVR_CLR_BBF_RES_TUNE_LIN_VAL_3_0(base, value) (BME_AND32(&XCVR_BBF_RES_TUNE_LIN_VAL_3_0_REG(base), (uint32_t)(~(value))))
30570 #define XCVR_TOG_BBF_RES_TUNE_LIN_VAL_3_0(base, value) (BME_XOR32(&XCVR_BBF_RES_TUNE_LIN_VAL_3_0_REG(base), (uint32_t)(value)))
30571 /*@}*/
30572 
30573 /*
30574  * Constants & macros for individual XCVR_BBF_RES_TUNE_LIN_VAL_3_0 bitfields
30575  */
30576 
30577 /*!
30578  * @name Register XCVR_BBF_RES_TUNE_LIN_VAL_3_0, field BBF_RES_TUNE_LIN_VAL_0[7:0] (RW)
30579  *
30580  * BBF linear gain value for index 0 (format: 5.3). Nominal value is 10^(0/20).
30581  * Stored with 3 fractional bits, e.g. round([10^(0/20)]*2^3) = 8decimal
30582  */
30583 /*@{*/
30584 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0 field. */
30585 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0(base) ((XCVR_BBF_RES_TUNE_LIN_VAL_3_0_REG(base) & XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0_MASK) >> XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0_SHIFT)
30586 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_LIN_VAL_3_0_REG(base), XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0_WIDTH))
30587 
30588 /*! @brief Set the BBF_RES_TUNE_LIN_VAL_0 field to a new value. */
30589 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0(base, value) (XCVR_RMW_BBF_RES_TUNE_LIN_VAL_3_0(base, XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0_MASK, XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0(value)))
30590 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_LIN_VAL_3_0_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0_SHIFT), XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_0_WIDTH))
30591 /*@}*/
30592 
30593 /*!
30594  * @name Register XCVR_BBF_RES_TUNE_LIN_VAL_3_0, field BBF_RES_TUNE_LIN_VAL_1[15:8] (RW)
30595  *
30596  * BBF linear gain value for index 1 (format: 5.3). Nominal value is 10^(3/20).
30597  * Stored with 3 fractional bits, e.g. round([10^(3/20)]*2^3) = 11decimal
30598  */
30599 /*@{*/
30600 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1 field. */
30601 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1(base) ((XCVR_BBF_RES_TUNE_LIN_VAL_3_0_REG(base) & XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1_MASK) >> XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1_SHIFT)
30602 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_LIN_VAL_3_0_REG(base), XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1_WIDTH))
30603 
30604 /*! @brief Set the BBF_RES_TUNE_LIN_VAL_1 field to a new value. */
30605 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1(base, value) (XCVR_RMW_BBF_RES_TUNE_LIN_VAL_3_0(base, XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1_MASK, XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1(value)))
30606 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_LIN_VAL_3_0_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1_SHIFT), XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_1_WIDTH))
30607 /*@}*/
30608 
30609 /*!
30610  * @name Register XCVR_BBF_RES_TUNE_LIN_VAL_3_0, field BBF_RES_TUNE_LIN_VAL_2[23:16] (RW)
30611  *
30612  * BBF linear gain value for index 2 (format: 5.3). Nominal value is 10^(6/20).
30613  * Stored with 3 fractional bits, e.g. round([10^(6/20)]*2^3) = 16decimal
30614  */
30615 /*@{*/
30616 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2 field. */
30617 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2(base) ((XCVR_BBF_RES_TUNE_LIN_VAL_3_0_REG(base) & XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2_MASK) >> XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2_SHIFT)
30618 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_LIN_VAL_3_0_REG(base), XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2_WIDTH))
30619 
30620 /*! @brief Set the BBF_RES_TUNE_LIN_VAL_2 field to a new value. */
30621 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2(base, value) (XCVR_RMW_BBF_RES_TUNE_LIN_VAL_3_0(base, XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2_MASK, XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2(value)))
30622 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_LIN_VAL_3_0_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2_SHIFT), XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_2_WIDTH))
30623 /*@}*/
30624 
30625 /*!
30626  * @name Register XCVR_BBF_RES_TUNE_LIN_VAL_3_0, field BBF_RES_TUNE_LIN_VAL_3[31:24] (RW)
30627  *
30628  * BBF linear gain value for index 3 (format: 5.3). Nominal value is 10^(9/20).
30629  * Stored with 3 fractional bits, e.g. round([10^(9/20)]*2^3) = 23decimal
30630  */
30631 /*@{*/
30632 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3 field. */
30633 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3(base) ((XCVR_BBF_RES_TUNE_LIN_VAL_3_0_REG(base) & XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3_MASK) >> XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3_SHIFT)
30634 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_LIN_VAL_3_0_REG(base), XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3_WIDTH))
30635 
30636 /*! @brief Set the BBF_RES_TUNE_LIN_VAL_3 field to a new value. */
30637 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3(base, value) (XCVR_RMW_BBF_RES_TUNE_LIN_VAL_3_0(base, XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3_MASK, XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3(value)))
30638 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_LIN_VAL_3_0_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3_SHIFT), XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_3_0_BBF_RES_TUNE_LIN_VAL_3_WIDTH))
30639 /*@}*/
30640 
30641 /*******************************************************************************
30642  * XCVR_BBF_RES_TUNE_LIN_VAL_7_4 - BBF Resistor Tune Values 7..4
30643  ******************************************************************************/
30644 
30645 /*!
30646  * @brief XCVR_BBF_RES_TUNE_LIN_VAL_7_4 - BBF Resistor Tune Values 7..4 (RW)
30647  *
30648  * Reset value: 0x00000000U
30649  */
30650 /*!
30651  * @name Constants and macros for entire XCVR_BBF_RES_TUNE_LIN_VAL_7_4 register
30652  */
30653 /*@{*/
30654 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_7_4(base) (XCVR_BBF_RES_TUNE_LIN_VAL_7_4_REG(base))
30655 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_7_4(base, value) (XCVR_BBF_RES_TUNE_LIN_VAL_7_4_REG(base) = (value))
30656 #define XCVR_RMW_BBF_RES_TUNE_LIN_VAL_7_4(base, mask, value) (XCVR_WR_BBF_RES_TUNE_LIN_VAL_7_4(base, (XCVR_RD_BBF_RES_TUNE_LIN_VAL_7_4(base) & ~(mask)) | (value)))
30657 #define XCVR_SET_BBF_RES_TUNE_LIN_VAL_7_4(base, value) (BME_OR32(&XCVR_BBF_RES_TUNE_LIN_VAL_7_4_REG(base), (uint32_t)(value)))
30658 #define XCVR_CLR_BBF_RES_TUNE_LIN_VAL_7_4(base, value) (BME_AND32(&XCVR_BBF_RES_TUNE_LIN_VAL_7_4_REG(base), (uint32_t)(~(value))))
30659 #define XCVR_TOG_BBF_RES_TUNE_LIN_VAL_7_4(base, value) (BME_XOR32(&XCVR_BBF_RES_TUNE_LIN_VAL_7_4_REG(base), (uint32_t)(value)))
30660 /*@}*/
30661 
30662 /*
30663  * Constants & macros for individual XCVR_BBF_RES_TUNE_LIN_VAL_7_4 bitfields
30664  */
30665 
30666 /*!
30667  * @name Register XCVR_BBF_RES_TUNE_LIN_VAL_7_4, field BBF_RES_TUNE_LIN_VAL_4[7:0] (RW)
30668  *
30669  * BBF linear gain value for index 4 (format: 5.3). Nominal value is 10^(12/20).
30670  * Stored with 3 fractional bits, e.g. round([10^(12/20)]*2^3) = 32decimal
30671  */
30672 /*@{*/
30673 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4 field. */
30674 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4(base) ((XCVR_BBF_RES_TUNE_LIN_VAL_7_4_REG(base) & XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4_MASK) >> XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4_SHIFT)
30675 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_LIN_VAL_7_4_REG(base), XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4_WIDTH))
30676 
30677 /*! @brief Set the BBF_RES_TUNE_LIN_VAL_4 field to a new value. */
30678 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4(base, value) (XCVR_RMW_BBF_RES_TUNE_LIN_VAL_7_4(base, XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4_MASK, XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4(value)))
30679 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_LIN_VAL_7_4_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4_SHIFT), XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_4_WIDTH))
30680 /*@}*/
30681 
30682 /*!
30683  * @name Register XCVR_BBF_RES_TUNE_LIN_VAL_7_4, field BBF_RES_TUNE_LIN_VAL_5[15:8] (RW)
30684  *
30685  * BBF linear gain value for index 5 (format: 5.3). Nominal value is 10^(15/20).
30686  * Stored with 3 fractional bits, e.g. round([10^(15/20)]*2^3) = 45decimal
30687  */
30688 /*@{*/
30689 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5 field. */
30690 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5(base) ((XCVR_BBF_RES_TUNE_LIN_VAL_7_4_REG(base) & XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5_MASK) >> XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5_SHIFT)
30691 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_LIN_VAL_7_4_REG(base), XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5_WIDTH))
30692 
30693 /*! @brief Set the BBF_RES_TUNE_LIN_VAL_5 field to a new value. */
30694 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5(base, value) (XCVR_RMW_BBF_RES_TUNE_LIN_VAL_7_4(base, XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5_MASK, XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5(value)))
30695 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_LIN_VAL_7_4_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5_SHIFT), XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_5_WIDTH))
30696 /*@}*/
30697 
30698 /*!
30699  * @name Register XCVR_BBF_RES_TUNE_LIN_VAL_7_4, field BBF_RES_TUNE_LIN_VAL_6[23:16] (RW)
30700  *
30701  * BBF linear gain value for index 6 (format: 5.3). Nominal value is 10^(18/20).
30702  * Stored with 3 fractional bits, e.g. round([10^(18/20)]*2^3) = 64decimal
30703  */
30704 /*@{*/
30705 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6 field. */
30706 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6(base) ((XCVR_BBF_RES_TUNE_LIN_VAL_7_4_REG(base) & XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6_MASK) >> XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6_SHIFT)
30707 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_LIN_VAL_7_4_REG(base), XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6_WIDTH))
30708 
30709 /*! @brief Set the BBF_RES_TUNE_LIN_VAL_6 field to a new value. */
30710 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6(base, value) (XCVR_RMW_BBF_RES_TUNE_LIN_VAL_7_4(base, XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6_MASK, XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6(value)))
30711 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_LIN_VAL_7_4_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6_SHIFT), XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_6_WIDTH))
30712 /*@}*/
30713 
30714 /*!
30715  * @name Register XCVR_BBF_RES_TUNE_LIN_VAL_7_4, field BBF_RES_TUNE_LIN_VAL_7[31:24] (RW)
30716  *
30717  * BBF linear gain value for index 7 (format: 5.3). Nominal value is 10^(21/20).
30718  * Stored with 3 fractional bits, e.g. round([10^(21/20)]*2^3) = 90decimal
30719  */
30720 /*@{*/
30721 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7 field. */
30722 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7(base) ((XCVR_BBF_RES_TUNE_LIN_VAL_7_4_REG(base) & XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7_MASK) >> XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7_SHIFT)
30723 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_LIN_VAL_7_4_REG(base), XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7_WIDTH))
30724 
30725 /*! @brief Set the BBF_RES_TUNE_LIN_VAL_7 field to a new value. */
30726 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7(base, value) (XCVR_RMW_BBF_RES_TUNE_LIN_VAL_7_4(base, XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7_MASK, XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7(value)))
30727 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_LIN_VAL_7_4_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7_SHIFT), XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_7_4_BBF_RES_TUNE_LIN_VAL_7_WIDTH))
30728 /*@}*/
30729 
30730 /*******************************************************************************
30731  * XCVR_BBF_RES_TUNE_LIN_VAL_10_8 - BBF Resistor Tune Values 10..8
30732  ******************************************************************************/
30733 
30734 /*!
30735  * @brief XCVR_BBF_RES_TUNE_LIN_VAL_10_8 - BBF Resistor Tune Values 10..8 (RW)
30736  *
30737  * Reset value: 0x00000000U
30738  */
30739 /*!
30740  * @name Constants and macros for entire XCVR_BBF_RES_TUNE_LIN_VAL_10_8 register
30741  */
30742 /*@{*/
30743 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_10_8(base) (XCVR_BBF_RES_TUNE_LIN_VAL_10_8_REG(base))
30744 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_10_8(base, value) (XCVR_BBF_RES_TUNE_LIN_VAL_10_8_REG(base) = (value))
30745 #define XCVR_RMW_BBF_RES_TUNE_LIN_VAL_10_8(base, mask, value) (XCVR_WR_BBF_RES_TUNE_LIN_VAL_10_8(base, (XCVR_RD_BBF_RES_TUNE_LIN_VAL_10_8(base) & ~(mask)) | (value)))
30746 #define XCVR_SET_BBF_RES_TUNE_LIN_VAL_10_8(base, value) (BME_OR32(&XCVR_BBF_RES_TUNE_LIN_VAL_10_8_REG(base), (uint32_t)(value)))
30747 #define XCVR_CLR_BBF_RES_TUNE_LIN_VAL_10_8(base, value) (BME_AND32(&XCVR_BBF_RES_TUNE_LIN_VAL_10_8_REG(base), (uint32_t)(~(value))))
30748 #define XCVR_TOG_BBF_RES_TUNE_LIN_VAL_10_8(base, value) (BME_XOR32(&XCVR_BBF_RES_TUNE_LIN_VAL_10_8_REG(base), (uint32_t)(value)))
30749 /*@}*/
30750 
30751 /*
30752  * Constants & macros for individual XCVR_BBF_RES_TUNE_LIN_VAL_10_8 bitfields
30753  */
30754 
30755 /*!
30756  * @name Register XCVR_BBF_RES_TUNE_LIN_VAL_10_8, field BBF_RES_TUNE_LIN_VAL_8[7:0] (RW)
30757  *
30758  * BBF linear gain value for index 8 (format: 5.3). Nominal value is 10^(24/20).
30759  * Stored with 3 fractional bits, e.g. round([10^(24/20)]*2^3) = 127decimal
30760  */
30761 /*@{*/
30762 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8 field. */
30763 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8(base) ((XCVR_BBF_RES_TUNE_LIN_VAL_10_8_REG(base) & XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8_MASK) >> XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8_SHIFT)
30764 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_LIN_VAL_10_8_REG(base), XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8_WIDTH))
30765 
30766 /*! @brief Set the BBF_RES_TUNE_LIN_VAL_8 field to a new value. */
30767 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8(base, value) (XCVR_RMW_BBF_RES_TUNE_LIN_VAL_10_8(base, XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8_MASK, XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8(value)))
30768 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_LIN_VAL_10_8_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8_SHIFT), XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_8_WIDTH))
30769 /*@}*/
30770 
30771 /*!
30772  * @name Register XCVR_BBF_RES_TUNE_LIN_VAL_10_8, field BBF_RES_TUNE_LIN_VAL_9[15:8] (RW)
30773  *
30774  * BBF linear gain value for index 9 (format: 5.3). Nominal value is 10^(27/20).
30775  * Stored with 3 fractional bits, e.g. round([10^(27/20)]*2^3) = 179decimal
30776  */
30777 /*@{*/
30778 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9 field. */
30779 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9(base) ((XCVR_BBF_RES_TUNE_LIN_VAL_10_8_REG(base) & XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9_MASK) >> XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9_SHIFT)
30780 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_LIN_VAL_10_8_REG(base), XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9_WIDTH))
30781 
30782 /*! @brief Set the BBF_RES_TUNE_LIN_VAL_9 field to a new value. */
30783 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9(base, value) (XCVR_RMW_BBF_RES_TUNE_LIN_VAL_10_8(base, XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9_MASK, XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9(value)))
30784 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_LIN_VAL_10_8_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9_SHIFT), XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_9_WIDTH))
30785 /*@}*/
30786 
30787 /*!
30788  * @name Register XCVR_BBF_RES_TUNE_LIN_VAL_10_8, field BBF_RES_TUNE_LIN_VAL_10[23:16] (RW)
30789  *
30790  * BBF linear gain value for index 10 (format: 5.3). Nominal value is
30791  * 10^(30/20). Stored with 3 fractional bits, e.g. round([10^(30/20)]*2^3) = 253decimal
30792  */
30793 /*@{*/
30794 /*! @brief Read current value of the XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10 field. */
30795 #define XCVR_RD_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10(base) ((XCVR_BBF_RES_TUNE_LIN_VAL_10_8_REG(base) & XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10_MASK) >> XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10_SHIFT)
30796 #define XCVR_BRD_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10(base) (BME_UBFX32(&XCVR_BBF_RES_TUNE_LIN_VAL_10_8_REG(base), XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10_WIDTH))
30797 
30798 /*! @brief Set the BBF_RES_TUNE_LIN_VAL_10 field to a new value. */
30799 #define XCVR_WR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10(base, value) (XCVR_RMW_BBF_RES_TUNE_LIN_VAL_10_8(base, XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10_MASK, XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10(value)))
30800 #define XCVR_BWR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10(base, value) (BME_BFI32(&XCVR_BBF_RES_TUNE_LIN_VAL_10_8_REG(base), ((uint32_t)(value) << XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10_SHIFT), XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10_SHIFT, XCVR_BBF_RES_TUNE_LIN_VAL_10_8_BBF_RES_TUNE_LIN_VAL_10_WIDTH))
30801 /*@}*/
30802 
30803 /*******************************************************************************
30804  * XCVR_AGC_GAIN_TBL_03_00 - AGC Gain Tables Step 03..00
30805  ******************************************************************************/
30806 
30807 /*!
30808  * @brief XCVR_AGC_GAIN_TBL_03_00 - AGC Gain Tables Step 03..00 (RW)
30809  *
30810  * Reset value: 0x00000000U
30811  */
30812 /*!
30813  * @name Constants and macros for entire XCVR_AGC_GAIN_TBL_03_00 register
30814  */
30815 /*@{*/
30816 #define XCVR_RD_AGC_GAIN_TBL_03_00(base) (XCVR_AGC_GAIN_TBL_03_00_REG(base))
30817 #define XCVR_WR_AGC_GAIN_TBL_03_00(base, value) (XCVR_AGC_GAIN_TBL_03_00_REG(base) = (value))
30818 #define XCVR_RMW_AGC_GAIN_TBL_03_00(base, mask, value) (XCVR_WR_AGC_GAIN_TBL_03_00(base, (XCVR_RD_AGC_GAIN_TBL_03_00(base) & ~(mask)) | (value)))
30819 #define XCVR_SET_AGC_GAIN_TBL_03_00(base, value) (BME_OR32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), (uint32_t)(value)))
30820 #define XCVR_CLR_AGC_GAIN_TBL_03_00(base, value) (BME_AND32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), (uint32_t)(~(value))))
30821 #define XCVR_TOG_AGC_GAIN_TBL_03_00(base, value) (BME_XOR32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), (uint32_t)(value)))
30822 /*@}*/
30823 
30824 /*
30825  * Constants & macros for individual XCVR_AGC_GAIN_TBL_03_00 bitfields
30826  */
30827 
30828 /*!
30829  * @name Register XCVR_AGC_GAIN_TBL_03_00, field BBF_GAIN_00[3:0] (RW)
30830  *
30831  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
30832  */
30833 /*@{*/
30834 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_00 field. */
30835 #define XCVR_RD_AGC_GAIN_TBL_03_00_BBF_GAIN_00(base) ((XCVR_AGC_GAIN_TBL_03_00_REG(base) & XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_00_MASK) >> XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_00_SHIFT)
30836 #define XCVR_BRD_AGC_GAIN_TBL_03_00_BBF_GAIN_00(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_00_SHIFT, XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_00_WIDTH))
30837 
30838 /*! @brief Set the BBF_GAIN_00 field to a new value. */
30839 #define XCVR_WR_AGC_GAIN_TBL_03_00_BBF_GAIN_00(base, value) (XCVR_RMW_AGC_GAIN_TBL_03_00(base, XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_00_MASK, XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_00(value)))
30840 #define XCVR_BWR_AGC_GAIN_TBL_03_00_BBF_GAIN_00(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_00_SHIFT), XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_00_SHIFT, XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_00_WIDTH))
30841 /*@}*/
30842 
30843 /*!
30844  * @name Register XCVR_AGC_GAIN_TBL_03_00, field LNM_GAIN_00[7:4] (RW)
30845  *
30846  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
30847  */
30848 /*@{*/
30849 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_00 field. */
30850 #define XCVR_RD_AGC_GAIN_TBL_03_00_LNM_GAIN_00(base) ((XCVR_AGC_GAIN_TBL_03_00_REG(base) & XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_00_MASK) >> XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_00_SHIFT)
30851 #define XCVR_BRD_AGC_GAIN_TBL_03_00_LNM_GAIN_00(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_00_SHIFT, XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_00_WIDTH))
30852 
30853 /*! @brief Set the LNM_GAIN_00 field to a new value. */
30854 #define XCVR_WR_AGC_GAIN_TBL_03_00_LNM_GAIN_00(base, value) (XCVR_RMW_AGC_GAIN_TBL_03_00(base, XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_00_MASK, XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_00(value)))
30855 #define XCVR_BWR_AGC_GAIN_TBL_03_00_LNM_GAIN_00(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_00_SHIFT), XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_00_SHIFT, XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_00_WIDTH))
30856 /*@}*/
30857 
30858 /*!
30859  * @name Register XCVR_AGC_GAIN_TBL_03_00, field BBF_GAIN_01[11:8] (RW)
30860  *
30861  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
30862  */
30863 /*@{*/
30864 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_01 field. */
30865 #define XCVR_RD_AGC_GAIN_TBL_03_00_BBF_GAIN_01(base) ((XCVR_AGC_GAIN_TBL_03_00_REG(base) & XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_01_MASK) >> XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_01_SHIFT)
30866 #define XCVR_BRD_AGC_GAIN_TBL_03_00_BBF_GAIN_01(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_01_SHIFT, XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_01_WIDTH))
30867 
30868 /*! @brief Set the BBF_GAIN_01 field to a new value. */
30869 #define XCVR_WR_AGC_GAIN_TBL_03_00_BBF_GAIN_01(base, value) (XCVR_RMW_AGC_GAIN_TBL_03_00(base, XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_01_MASK, XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_01(value)))
30870 #define XCVR_BWR_AGC_GAIN_TBL_03_00_BBF_GAIN_01(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_01_SHIFT), XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_01_SHIFT, XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_01_WIDTH))
30871 /*@}*/
30872 
30873 /*!
30874  * @name Register XCVR_AGC_GAIN_TBL_03_00, field LNM_GAIN_01[15:12] (RW)
30875  *
30876  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
30877  */
30878 /*@{*/
30879 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_01 field. */
30880 #define XCVR_RD_AGC_GAIN_TBL_03_00_LNM_GAIN_01(base) ((XCVR_AGC_GAIN_TBL_03_00_REG(base) & XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_01_MASK) >> XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_01_SHIFT)
30881 #define XCVR_BRD_AGC_GAIN_TBL_03_00_LNM_GAIN_01(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_01_SHIFT, XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_01_WIDTH))
30882 
30883 /*! @brief Set the LNM_GAIN_01 field to a new value. */
30884 #define XCVR_WR_AGC_GAIN_TBL_03_00_LNM_GAIN_01(base, value) (XCVR_RMW_AGC_GAIN_TBL_03_00(base, XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_01_MASK, XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_01(value)))
30885 #define XCVR_BWR_AGC_GAIN_TBL_03_00_LNM_GAIN_01(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_01_SHIFT), XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_01_SHIFT, XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_01_WIDTH))
30886 /*@}*/
30887 
30888 /*!
30889  * @name Register XCVR_AGC_GAIN_TBL_03_00, field BBF_GAIN_02[19:16] (RW)
30890  *
30891  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
30892  */
30893 /*@{*/
30894 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_02 field. */
30895 #define XCVR_RD_AGC_GAIN_TBL_03_00_BBF_GAIN_02(base) ((XCVR_AGC_GAIN_TBL_03_00_REG(base) & XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_02_MASK) >> XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_02_SHIFT)
30896 #define XCVR_BRD_AGC_GAIN_TBL_03_00_BBF_GAIN_02(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_02_SHIFT, XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_02_WIDTH))
30897 
30898 /*! @brief Set the BBF_GAIN_02 field to a new value. */
30899 #define XCVR_WR_AGC_GAIN_TBL_03_00_BBF_GAIN_02(base, value) (XCVR_RMW_AGC_GAIN_TBL_03_00(base, XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_02_MASK, XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_02(value)))
30900 #define XCVR_BWR_AGC_GAIN_TBL_03_00_BBF_GAIN_02(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_02_SHIFT), XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_02_SHIFT, XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_02_WIDTH))
30901 /*@}*/
30902 
30903 /*!
30904  * @name Register XCVR_AGC_GAIN_TBL_03_00, field LNM_GAIN_02[23:20] (RW)
30905  *
30906  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
30907  */
30908 /*@{*/
30909 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_02 field. */
30910 #define XCVR_RD_AGC_GAIN_TBL_03_00_LNM_GAIN_02(base) ((XCVR_AGC_GAIN_TBL_03_00_REG(base) & XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_02_MASK) >> XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_02_SHIFT)
30911 #define XCVR_BRD_AGC_GAIN_TBL_03_00_LNM_GAIN_02(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_02_SHIFT, XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_02_WIDTH))
30912 
30913 /*! @brief Set the LNM_GAIN_02 field to a new value. */
30914 #define XCVR_WR_AGC_GAIN_TBL_03_00_LNM_GAIN_02(base, value) (XCVR_RMW_AGC_GAIN_TBL_03_00(base, XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_02_MASK, XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_02(value)))
30915 #define XCVR_BWR_AGC_GAIN_TBL_03_00_LNM_GAIN_02(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_02_SHIFT), XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_02_SHIFT, XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_02_WIDTH))
30916 /*@}*/
30917 
30918 /*!
30919  * @name Register XCVR_AGC_GAIN_TBL_03_00, field BBF_GAIN_03[27:24] (RW)
30920  *
30921  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
30922  */
30923 /*@{*/
30924 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_03 field. */
30925 #define XCVR_RD_AGC_GAIN_TBL_03_00_BBF_GAIN_03(base) ((XCVR_AGC_GAIN_TBL_03_00_REG(base) & XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_03_MASK) >> XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_03_SHIFT)
30926 #define XCVR_BRD_AGC_GAIN_TBL_03_00_BBF_GAIN_03(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_03_SHIFT, XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_03_WIDTH))
30927 
30928 /*! @brief Set the BBF_GAIN_03 field to a new value. */
30929 #define XCVR_WR_AGC_GAIN_TBL_03_00_BBF_GAIN_03(base, value) (XCVR_RMW_AGC_GAIN_TBL_03_00(base, XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_03_MASK, XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_03(value)))
30930 #define XCVR_BWR_AGC_GAIN_TBL_03_00_BBF_GAIN_03(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_03_SHIFT), XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_03_SHIFT, XCVR_AGC_GAIN_TBL_03_00_BBF_GAIN_03_WIDTH))
30931 /*@}*/
30932 
30933 /*!
30934  * @name Register XCVR_AGC_GAIN_TBL_03_00, field LNM_GAIN_03[31:28] (RW)
30935  *
30936  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
30937  */
30938 /*@{*/
30939 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_03 field. */
30940 #define XCVR_RD_AGC_GAIN_TBL_03_00_LNM_GAIN_03(base) ((XCVR_AGC_GAIN_TBL_03_00_REG(base) & XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_03_MASK) >> XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_03_SHIFT)
30941 #define XCVR_BRD_AGC_GAIN_TBL_03_00_LNM_GAIN_03(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_03_SHIFT, XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_03_WIDTH))
30942 
30943 /*! @brief Set the LNM_GAIN_03 field to a new value. */
30944 #define XCVR_WR_AGC_GAIN_TBL_03_00_LNM_GAIN_03(base, value) (XCVR_RMW_AGC_GAIN_TBL_03_00(base, XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_03_MASK, XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_03(value)))
30945 #define XCVR_BWR_AGC_GAIN_TBL_03_00_LNM_GAIN_03(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_03_00_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_03_SHIFT), XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_03_SHIFT, XCVR_AGC_GAIN_TBL_03_00_LNM_GAIN_03_WIDTH))
30946 /*@}*/
30947 
30948 /*******************************************************************************
30949  * XCVR_AGC_GAIN_TBL_07_04 - AGC Gain Tables Step 07..04
30950  ******************************************************************************/
30951 
30952 /*!
30953  * @brief XCVR_AGC_GAIN_TBL_07_04 - AGC Gain Tables Step 07..04 (RW)
30954  *
30955  * Reset value: 0x00000000U
30956  */
30957 /*!
30958  * @name Constants and macros for entire XCVR_AGC_GAIN_TBL_07_04 register
30959  */
30960 /*@{*/
30961 #define XCVR_RD_AGC_GAIN_TBL_07_04(base) (XCVR_AGC_GAIN_TBL_07_04_REG(base))
30962 #define XCVR_WR_AGC_GAIN_TBL_07_04(base, value) (XCVR_AGC_GAIN_TBL_07_04_REG(base) = (value))
30963 #define XCVR_RMW_AGC_GAIN_TBL_07_04(base, mask, value) (XCVR_WR_AGC_GAIN_TBL_07_04(base, (XCVR_RD_AGC_GAIN_TBL_07_04(base) & ~(mask)) | (value)))
30964 #define XCVR_SET_AGC_GAIN_TBL_07_04(base, value) (BME_OR32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), (uint32_t)(value)))
30965 #define XCVR_CLR_AGC_GAIN_TBL_07_04(base, value) (BME_AND32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), (uint32_t)(~(value))))
30966 #define XCVR_TOG_AGC_GAIN_TBL_07_04(base, value) (BME_XOR32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), (uint32_t)(value)))
30967 /*@}*/
30968 
30969 /*
30970  * Constants & macros for individual XCVR_AGC_GAIN_TBL_07_04 bitfields
30971  */
30972 
30973 /*!
30974  * @name Register XCVR_AGC_GAIN_TBL_07_04, field BBF_GAIN_04[3:0] (RW)
30975  *
30976  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
30977  */
30978 /*@{*/
30979 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_04 field. */
30980 #define XCVR_RD_AGC_GAIN_TBL_07_04_BBF_GAIN_04(base) ((XCVR_AGC_GAIN_TBL_07_04_REG(base) & XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_04_MASK) >> XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_04_SHIFT)
30981 #define XCVR_BRD_AGC_GAIN_TBL_07_04_BBF_GAIN_04(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_04_SHIFT, XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_04_WIDTH))
30982 
30983 /*! @brief Set the BBF_GAIN_04 field to a new value. */
30984 #define XCVR_WR_AGC_GAIN_TBL_07_04_BBF_GAIN_04(base, value) (XCVR_RMW_AGC_GAIN_TBL_07_04(base, XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_04_MASK, XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_04(value)))
30985 #define XCVR_BWR_AGC_GAIN_TBL_07_04_BBF_GAIN_04(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_04_SHIFT), XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_04_SHIFT, XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_04_WIDTH))
30986 /*@}*/
30987 
30988 /*!
30989  * @name Register XCVR_AGC_GAIN_TBL_07_04, field LNM_GAIN_04[7:4] (RW)
30990  *
30991  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
30992  */
30993 /*@{*/
30994 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_04 field. */
30995 #define XCVR_RD_AGC_GAIN_TBL_07_04_LNM_GAIN_04(base) ((XCVR_AGC_GAIN_TBL_07_04_REG(base) & XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_04_MASK) >> XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_04_SHIFT)
30996 #define XCVR_BRD_AGC_GAIN_TBL_07_04_LNM_GAIN_04(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_04_SHIFT, XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_04_WIDTH))
30997 
30998 /*! @brief Set the LNM_GAIN_04 field to a new value. */
30999 #define XCVR_WR_AGC_GAIN_TBL_07_04_LNM_GAIN_04(base, value) (XCVR_RMW_AGC_GAIN_TBL_07_04(base, XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_04_MASK, XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_04(value)))
31000 #define XCVR_BWR_AGC_GAIN_TBL_07_04_LNM_GAIN_04(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_04_SHIFT), XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_04_SHIFT, XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_04_WIDTH))
31001 /*@}*/
31002 
31003 /*!
31004  * @name Register XCVR_AGC_GAIN_TBL_07_04, field BBF_GAIN_05[11:8] (RW)
31005  *
31006  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31007  */
31008 /*@{*/
31009 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_05 field. */
31010 #define XCVR_RD_AGC_GAIN_TBL_07_04_BBF_GAIN_05(base) ((XCVR_AGC_GAIN_TBL_07_04_REG(base) & XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_05_MASK) >> XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_05_SHIFT)
31011 #define XCVR_BRD_AGC_GAIN_TBL_07_04_BBF_GAIN_05(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_05_SHIFT, XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_05_WIDTH))
31012 
31013 /*! @brief Set the BBF_GAIN_05 field to a new value. */
31014 #define XCVR_WR_AGC_GAIN_TBL_07_04_BBF_GAIN_05(base, value) (XCVR_RMW_AGC_GAIN_TBL_07_04(base, XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_05_MASK, XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_05(value)))
31015 #define XCVR_BWR_AGC_GAIN_TBL_07_04_BBF_GAIN_05(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_05_SHIFT), XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_05_SHIFT, XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_05_WIDTH))
31016 /*@}*/
31017 
31018 /*!
31019  * @name Register XCVR_AGC_GAIN_TBL_07_04, field LNM_GAIN_05[15:12] (RW)
31020  *
31021  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31022  */
31023 /*@{*/
31024 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_05 field. */
31025 #define XCVR_RD_AGC_GAIN_TBL_07_04_LNM_GAIN_05(base) ((XCVR_AGC_GAIN_TBL_07_04_REG(base) & XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_05_MASK) >> XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_05_SHIFT)
31026 #define XCVR_BRD_AGC_GAIN_TBL_07_04_LNM_GAIN_05(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_05_SHIFT, XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_05_WIDTH))
31027 
31028 /*! @brief Set the LNM_GAIN_05 field to a new value. */
31029 #define XCVR_WR_AGC_GAIN_TBL_07_04_LNM_GAIN_05(base, value) (XCVR_RMW_AGC_GAIN_TBL_07_04(base, XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_05_MASK, XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_05(value)))
31030 #define XCVR_BWR_AGC_GAIN_TBL_07_04_LNM_GAIN_05(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_05_SHIFT), XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_05_SHIFT, XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_05_WIDTH))
31031 /*@}*/
31032 
31033 /*!
31034  * @name Register XCVR_AGC_GAIN_TBL_07_04, field BBF_GAIN_06[19:16] (RW)
31035  *
31036  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31037  */
31038 /*@{*/
31039 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_06 field. */
31040 #define XCVR_RD_AGC_GAIN_TBL_07_04_BBF_GAIN_06(base) ((XCVR_AGC_GAIN_TBL_07_04_REG(base) & XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_06_MASK) >> XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_06_SHIFT)
31041 #define XCVR_BRD_AGC_GAIN_TBL_07_04_BBF_GAIN_06(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_06_SHIFT, XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_06_WIDTH))
31042 
31043 /*! @brief Set the BBF_GAIN_06 field to a new value. */
31044 #define XCVR_WR_AGC_GAIN_TBL_07_04_BBF_GAIN_06(base, value) (XCVR_RMW_AGC_GAIN_TBL_07_04(base, XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_06_MASK, XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_06(value)))
31045 #define XCVR_BWR_AGC_GAIN_TBL_07_04_BBF_GAIN_06(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_06_SHIFT), XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_06_SHIFT, XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_06_WIDTH))
31046 /*@}*/
31047 
31048 /*!
31049  * @name Register XCVR_AGC_GAIN_TBL_07_04, field LNM_GAIN_06[23:20] (RW)
31050  *
31051  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31052  */
31053 /*@{*/
31054 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_06 field. */
31055 #define XCVR_RD_AGC_GAIN_TBL_07_04_LNM_GAIN_06(base) ((XCVR_AGC_GAIN_TBL_07_04_REG(base) & XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_06_MASK) >> XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_06_SHIFT)
31056 #define XCVR_BRD_AGC_GAIN_TBL_07_04_LNM_GAIN_06(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_06_SHIFT, XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_06_WIDTH))
31057 
31058 /*! @brief Set the LNM_GAIN_06 field to a new value. */
31059 #define XCVR_WR_AGC_GAIN_TBL_07_04_LNM_GAIN_06(base, value) (XCVR_RMW_AGC_GAIN_TBL_07_04(base, XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_06_MASK, XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_06(value)))
31060 #define XCVR_BWR_AGC_GAIN_TBL_07_04_LNM_GAIN_06(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_06_SHIFT), XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_06_SHIFT, XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_06_WIDTH))
31061 /*@}*/
31062 
31063 /*!
31064  * @name Register XCVR_AGC_GAIN_TBL_07_04, field BBF_GAIN_07[27:24] (RW)
31065  *
31066  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31067  */
31068 /*@{*/
31069 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_07 field. */
31070 #define XCVR_RD_AGC_GAIN_TBL_07_04_BBF_GAIN_07(base) ((XCVR_AGC_GAIN_TBL_07_04_REG(base) & XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_07_MASK) >> XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_07_SHIFT)
31071 #define XCVR_BRD_AGC_GAIN_TBL_07_04_BBF_GAIN_07(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_07_SHIFT, XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_07_WIDTH))
31072 
31073 /*! @brief Set the BBF_GAIN_07 field to a new value. */
31074 #define XCVR_WR_AGC_GAIN_TBL_07_04_BBF_GAIN_07(base, value) (XCVR_RMW_AGC_GAIN_TBL_07_04(base, XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_07_MASK, XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_07(value)))
31075 #define XCVR_BWR_AGC_GAIN_TBL_07_04_BBF_GAIN_07(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_07_SHIFT), XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_07_SHIFT, XCVR_AGC_GAIN_TBL_07_04_BBF_GAIN_07_WIDTH))
31076 /*@}*/
31077 
31078 /*!
31079  * @name Register XCVR_AGC_GAIN_TBL_07_04, field LNM_GAIN_07[31:28] (RW)
31080  *
31081  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31082  */
31083 /*@{*/
31084 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_07 field. */
31085 #define XCVR_RD_AGC_GAIN_TBL_07_04_LNM_GAIN_07(base) ((XCVR_AGC_GAIN_TBL_07_04_REG(base) & XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_07_MASK) >> XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_07_SHIFT)
31086 #define XCVR_BRD_AGC_GAIN_TBL_07_04_LNM_GAIN_07(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_07_SHIFT, XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_07_WIDTH))
31087 
31088 /*! @brief Set the LNM_GAIN_07 field to a new value. */
31089 #define XCVR_WR_AGC_GAIN_TBL_07_04_LNM_GAIN_07(base, value) (XCVR_RMW_AGC_GAIN_TBL_07_04(base, XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_07_MASK, XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_07(value)))
31090 #define XCVR_BWR_AGC_GAIN_TBL_07_04_LNM_GAIN_07(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_07_04_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_07_SHIFT), XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_07_SHIFT, XCVR_AGC_GAIN_TBL_07_04_LNM_GAIN_07_WIDTH))
31091 /*@}*/
31092 
31093 /*******************************************************************************
31094  * XCVR_AGC_GAIN_TBL_11_08 - AGC Gain Tables Step 11..08
31095  ******************************************************************************/
31096 
31097 /*!
31098  * @brief XCVR_AGC_GAIN_TBL_11_08 - AGC Gain Tables Step 11..08 (RW)
31099  *
31100  * Reset value: 0x00000000U
31101  */
31102 /*!
31103  * @name Constants and macros for entire XCVR_AGC_GAIN_TBL_11_08 register
31104  */
31105 /*@{*/
31106 #define XCVR_RD_AGC_GAIN_TBL_11_08(base) (XCVR_AGC_GAIN_TBL_11_08_REG(base))
31107 #define XCVR_WR_AGC_GAIN_TBL_11_08(base, value) (XCVR_AGC_GAIN_TBL_11_08_REG(base) = (value))
31108 #define XCVR_RMW_AGC_GAIN_TBL_11_08(base, mask, value) (XCVR_WR_AGC_GAIN_TBL_11_08(base, (XCVR_RD_AGC_GAIN_TBL_11_08(base) & ~(mask)) | (value)))
31109 #define XCVR_SET_AGC_GAIN_TBL_11_08(base, value) (BME_OR32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), (uint32_t)(value)))
31110 #define XCVR_CLR_AGC_GAIN_TBL_11_08(base, value) (BME_AND32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), (uint32_t)(~(value))))
31111 #define XCVR_TOG_AGC_GAIN_TBL_11_08(base, value) (BME_XOR32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), (uint32_t)(value)))
31112 /*@}*/
31113 
31114 /*
31115  * Constants & macros for individual XCVR_AGC_GAIN_TBL_11_08 bitfields
31116  */
31117 
31118 /*!
31119  * @name Register XCVR_AGC_GAIN_TBL_11_08, field BBF_GAIN_08[3:0] (RW)
31120  *
31121  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31122  */
31123 /*@{*/
31124 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_08 field. */
31125 #define XCVR_RD_AGC_GAIN_TBL_11_08_BBF_GAIN_08(base) ((XCVR_AGC_GAIN_TBL_11_08_REG(base) & XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_08_MASK) >> XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_08_SHIFT)
31126 #define XCVR_BRD_AGC_GAIN_TBL_11_08_BBF_GAIN_08(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_08_SHIFT, XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_08_WIDTH))
31127 
31128 /*! @brief Set the BBF_GAIN_08 field to a new value. */
31129 #define XCVR_WR_AGC_GAIN_TBL_11_08_BBF_GAIN_08(base, value) (XCVR_RMW_AGC_GAIN_TBL_11_08(base, XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_08_MASK, XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_08(value)))
31130 #define XCVR_BWR_AGC_GAIN_TBL_11_08_BBF_GAIN_08(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_08_SHIFT), XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_08_SHIFT, XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_08_WIDTH))
31131 /*@}*/
31132 
31133 /*!
31134  * @name Register XCVR_AGC_GAIN_TBL_11_08, field LNM_GAIN_08[7:4] (RW)
31135  *
31136  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31137  */
31138 /*@{*/
31139 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_08 field. */
31140 #define XCVR_RD_AGC_GAIN_TBL_11_08_LNM_GAIN_08(base) ((XCVR_AGC_GAIN_TBL_11_08_REG(base) & XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_08_MASK) >> XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_08_SHIFT)
31141 #define XCVR_BRD_AGC_GAIN_TBL_11_08_LNM_GAIN_08(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_08_SHIFT, XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_08_WIDTH))
31142 
31143 /*! @brief Set the LNM_GAIN_08 field to a new value. */
31144 #define XCVR_WR_AGC_GAIN_TBL_11_08_LNM_GAIN_08(base, value) (XCVR_RMW_AGC_GAIN_TBL_11_08(base, XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_08_MASK, XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_08(value)))
31145 #define XCVR_BWR_AGC_GAIN_TBL_11_08_LNM_GAIN_08(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_08_SHIFT), XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_08_SHIFT, XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_08_WIDTH))
31146 /*@}*/
31147 
31148 /*!
31149  * @name Register XCVR_AGC_GAIN_TBL_11_08, field BBF_GAIN_09[11:8] (RW)
31150  *
31151  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31152  */
31153 /*@{*/
31154 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_09 field. */
31155 #define XCVR_RD_AGC_GAIN_TBL_11_08_BBF_GAIN_09(base) ((XCVR_AGC_GAIN_TBL_11_08_REG(base) & XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_09_MASK) >> XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_09_SHIFT)
31156 #define XCVR_BRD_AGC_GAIN_TBL_11_08_BBF_GAIN_09(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_09_SHIFT, XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_09_WIDTH))
31157 
31158 /*! @brief Set the BBF_GAIN_09 field to a new value. */
31159 #define XCVR_WR_AGC_GAIN_TBL_11_08_BBF_GAIN_09(base, value) (XCVR_RMW_AGC_GAIN_TBL_11_08(base, XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_09_MASK, XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_09(value)))
31160 #define XCVR_BWR_AGC_GAIN_TBL_11_08_BBF_GAIN_09(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_09_SHIFT), XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_09_SHIFT, XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_09_WIDTH))
31161 /*@}*/
31162 
31163 /*!
31164  * @name Register XCVR_AGC_GAIN_TBL_11_08, field LNM_GAIN_09[15:12] (RW)
31165  *
31166  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31167  */
31168 /*@{*/
31169 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_09 field. */
31170 #define XCVR_RD_AGC_GAIN_TBL_11_08_LNM_GAIN_09(base) ((XCVR_AGC_GAIN_TBL_11_08_REG(base) & XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_09_MASK) >> XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_09_SHIFT)
31171 #define XCVR_BRD_AGC_GAIN_TBL_11_08_LNM_GAIN_09(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_09_SHIFT, XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_09_WIDTH))
31172 
31173 /*! @brief Set the LNM_GAIN_09 field to a new value. */
31174 #define XCVR_WR_AGC_GAIN_TBL_11_08_LNM_GAIN_09(base, value) (XCVR_RMW_AGC_GAIN_TBL_11_08(base, XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_09_MASK, XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_09(value)))
31175 #define XCVR_BWR_AGC_GAIN_TBL_11_08_LNM_GAIN_09(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_09_SHIFT), XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_09_SHIFT, XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_09_WIDTH))
31176 /*@}*/
31177 
31178 /*!
31179  * @name Register XCVR_AGC_GAIN_TBL_11_08, field BBF_GAIN_10[19:16] (RW)
31180  *
31181  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31182  */
31183 /*@{*/
31184 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_10 field. */
31185 #define XCVR_RD_AGC_GAIN_TBL_11_08_BBF_GAIN_10(base) ((XCVR_AGC_GAIN_TBL_11_08_REG(base) & XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_10_MASK) >> XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_10_SHIFT)
31186 #define XCVR_BRD_AGC_GAIN_TBL_11_08_BBF_GAIN_10(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_10_SHIFT, XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_10_WIDTH))
31187 
31188 /*! @brief Set the BBF_GAIN_10 field to a new value. */
31189 #define XCVR_WR_AGC_GAIN_TBL_11_08_BBF_GAIN_10(base, value) (XCVR_RMW_AGC_GAIN_TBL_11_08(base, XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_10_MASK, XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_10(value)))
31190 #define XCVR_BWR_AGC_GAIN_TBL_11_08_BBF_GAIN_10(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_10_SHIFT), XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_10_SHIFT, XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_10_WIDTH))
31191 /*@}*/
31192 
31193 /*!
31194  * @name Register XCVR_AGC_GAIN_TBL_11_08, field LNM_GAIN_10[23:20] (RW)
31195  *
31196  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31197  */
31198 /*@{*/
31199 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_10 field. */
31200 #define XCVR_RD_AGC_GAIN_TBL_11_08_LNM_GAIN_10(base) ((XCVR_AGC_GAIN_TBL_11_08_REG(base) & XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_10_MASK) >> XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_10_SHIFT)
31201 #define XCVR_BRD_AGC_GAIN_TBL_11_08_LNM_GAIN_10(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_10_SHIFT, XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_10_WIDTH))
31202 
31203 /*! @brief Set the LNM_GAIN_10 field to a new value. */
31204 #define XCVR_WR_AGC_GAIN_TBL_11_08_LNM_GAIN_10(base, value) (XCVR_RMW_AGC_GAIN_TBL_11_08(base, XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_10_MASK, XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_10(value)))
31205 #define XCVR_BWR_AGC_GAIN_TBL_11_08_LNM_GAIN_10(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_10_SHIFT), XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_10_SHIFT, XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_10_WIDTH))
31206 /*@}*/
31207 
31208 /*!
31209  * @name Register XCVR_AGC_GAIN_TBL_11_08, field BBF_GAIN_11[27:24] (RW)
31210  *
31211  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31212  */
31213 /*@{*/
31214 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_11 field. */
31215 #define XCVR_RD_AGC_GAIN_TBL_11_08_BBF_GAIN_11(base) ((XCVR_AGC_GAIN_TBL_11_08_REG(base) & XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_11_MASK) >> XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_11_SHIFT)
31216 #define XCVR_BRD_AGC_GAIN_TBL_11_08_BBF_GAIN_11(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_11_SHIFT, XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_11_WIDTH))
31217 
31218 /*! @brief Set the BBF_GAIN_11 field to a new value. */
31219 #define XCVR_WR_AGC_GAIN_TBL_11_08_BBF_GAIN_11(base, value) (XCVR_RMW_AGC_GAIN_TBL_11_08(base, XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_11_MASK, XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_11(value)))
31220 #define XCVR_BWR_AGC_GAIN_TBL_11_08_BBF_GAIN_11(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_11_SHIFT), XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_11_SHIFT, XCVR_AGC_GAIN_TBL_11_08_BBF_GAIN_11_WIDTH))
31221 /*@}*/
31222 
31223 /*!
31224  * @name Register XCVR_AGC_GAIN_TBL_11_08, field LNM_GAIN_11[31:28] (RW)
31225  *
31226  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31227  */
31228 /*@{*/
31229 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_11 field. */
31230 #define XCVR_RD_AGC_GAIN_TBL_11_08_LNM_GAIN_11(base) ((XCVR_AGC_GAIN_TBL_11_08_REG(base) & XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_11_MASK) >> XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_11_SHIFT)
31231 #define XCVR_BRD_AGC_GAIN_TBL_11_08_LNM_GAIN_11(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_11_SHIFT, XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_11_WIDTH))
31232 
31233 /*! @brief Set the LNM_GAIN_11 field to a new value. */
31234 #define XCVR_WR_AGC_GAIN_TBL_11_08_LNM_GAIN_11(base, value) (XCVR_RMW_AGC_GAIN_TBL_11_08(base, XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_11_MASK, XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_11(value)))
31235 #define XCVR_BWR_AGC_GAIN_TBL_11_08_LNM_GAIN_11(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_11_08_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_11_SHIFT), XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_11_SHIFT, XCVR_AGC_GAIN_TBL_11_08_LNM_GAIN_11_WIDTH))
31236 /*@}*/
31237 
31238 /*******************************************************************************
31239  * XCVR_AGC_GAIN_TBL_15_12 - AGC Gain Tables Step 15..12
31240  ******************************************************************************/
31241 
31242 /*!
31243  * @brief XCVR_AGC_GAIN_TBL_15_12 - AGC Gain Tables Step 15..12 (RW)
31244  *
31245  * Reset value: 0x00000000U
31246  */
31247 /*!
31248  * @name Constants and macros for entire XCVR_AGC_GAIN_TBL_15_12 register
31249  */
31250 /*@{*/
31251 #define XCVR_RD_AGC_GAIN_TBL_15_12(base) (XCVR_AGC_GAIN_TBL_15_12_REG(base))
31252 #define XCVR_WR_AGC_GAIN_TBL_15_12(base, value) (XCVR_AGC_GAIN_TBL_15_12_REG(base) = (value))
31253 #define XCVR_RMW_AGC_GAIN_TBL_15_12(base, mask, value) (XCVR_WR_AGC_GAIN_TBL_15_12(base, (XCVR_RD_AGC_GAIN_TBL_15_12(base) & ~(mask)) | (value)))
31254 #define XCVR_SET_AGC_GAIN_TBL_15_12(base, value) (BME_OR32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), (uint32_t)(value)))
31255 #define XCVR_CLR_AGC_GAIN_TBL_15_12(base, value) (BME_AND32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), (uint32_t)(~(value))))
31256 #define XCVR_TOG_AGC_GAIN_TBL_15_12(base, value) (BME_XOR32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), (uint32_t)(value)))
31257 /*@}*/
31258 
31259 /*
31260  * Constants & macros for individual XCVR_AGC_GAIN_TBL_15_12 bitfields
31261  */
31262 
31263 /*!
31264  * @name Register XCVR_AGC_GAIN_TBL_15_12, field BBF_GAIN_12[3:0] (RW)
31265  *
31266  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31267  */
31268 /*@{*/
31269 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_12 field. */
31270 #define XCVR_RD_AGC_GAIN_TBL_15_12_BBF_GAIN_12(base) ((XCVR_AGC_GAIN_TBL_15_12_REG(base) & XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_12_MASK) >> XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_12_SHIFT)
31271 #define XCVR_BRD_AGC_GAIN_TBL_15_12_BBF_GAIN_12(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_12_SHIFT, XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_12_WIDTH))
31272 
31273 /*! @brief Set the BBF_GAIN_12 field to a new value. */
31274 #define XCVR_WR_AGC_GAIN_TBL_15_12_BBF_GAIN_12(base, value) (XCVR_RMW_AGC_GAIN_TBL_15_12(base, XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_12_MASK, XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_12(value)))
31275 #define XCVR_BWR_AGC_GAIN_TBL_15_12_BBF_GAIN_12(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_12_SHIFT), XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_12_SHIFT, XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_12_WIDTH))
31276 /*@}*/
31277 
31278 /*!
31279  * @name Register XCVR_AGC_GAIN_TBL_15_12, field LNM_GAIN_12[7:4] (RW)
31280  *
31281  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31282  */
31283 /*@{*/
31284 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_12 field. */
31285 #define XCVR_RD_AGC_GAIN_TBL_15_12_LNM_GAIN_12(base) ((XCVR_AGC_GAIN_TBL_15_12_REG(base) & XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_12_MASK) >> XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_12_SHIFT)
31286 #define XCVR_BRD_AGC_GAIN_TBL_15_12_LNM_GAIN_12(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_12_SHIFT, XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_12_WIDTH))
31287 
31288 /*! @brief Set the LNM_GAIN_12 field to a new value. */
31289 #define XCVR_WR_AGC_GAIN_TBL_15_12_LNM_GAIN_12(base, value) (XCVR_RMW_AGC_GAIN_TBL_15_12(base, XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_12_MASK, XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_12(value)))
31290 #define XCVR_BWR_AGC_GAIN_TBL_15_12_LNM_GAIN_12(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_12_SHIFT), XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_12_SHIFT, XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_12_WIDTH))
31291 /*@}*/
31292 
31293 /*!
31294  * @name Register XCVR_AGC_GAIN_TBL_15_12, field BBF_GAIN_13[11:8] (RW)
31295  *
31296  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31297  */
31298 /*@{*/
31299 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_13 field. */
31300 #define XCVR_RD_AGC_GAIN_TBL_15_12_BBF_GAIN_13(base) ((XCVR_AGC_GAIN_TBL_15_12_REG(base) & XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_13_MASK) >> XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_13_SHIFT)
31301 #define XCVR_BRD_AGC_GAIN_TBL_15_12_BBF_GAIN_13(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_13_SHIFT, XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_13_WIDTH))
31302 
31303 /*! @brief Set the BBF_GAIN_13 field to a new value. */
31304 #define XCVR_WR_AGC_GAIN_TBL_15_12_BBF_GAIN_13(base, value) (XCVR_RMW_AGC_GAIN_TBL_15_12(base, XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_13_MASK, XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_13(value)))
31305 #define XCVR_BWR_AGC_GAIN_TBL_15_12_BBF_GAIN_13(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_13_SHIFT), XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_13_SHIFT, XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_13_WIDTH))
31306 /*@}*/
31307 
31308 /*!
31309  * @name Register XCVR_AGC_GAIN_TBL_15_12, field LNM_GAIN_13[15:12] (RW)
31310  *
31311  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31312  */
31313 /*@{*/
31314 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_13 field. */
31315 #define XCVR_RD_AGC_GAIN_TBL_15_12_LNM_GAIN_13(base) ((XCVR_AGC_GAIN_TBL_15_12_REG(base) & XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_13_MASK) >> XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_13_SHIFT)
31316 #define XCVR_BRD_AGC_GAIN_TBL_15_12_LNM_GAIN_13(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_13_SHIFT, XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_13_WIDTH))
31317 
31318 /*! @brief Set the LNM_GAIN_13 field to a new value. */
31319 #define XCVR_WR_AGC_GAIN_TBL_15_12_LNM_GAIN_13(base, value) (XCVR_RMW_AGC_GAIN_TBL_15_12(base, XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_13_MASK, XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_13(value)))
31320 #define XCVR_BWR_AGC_GAIN_TBL_15_12_LNM_GAIN_13(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_13_SHIFT), XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_13_SHIFT, XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_13_WIDTH))
31321 /*@}*/
31322 
31323 /*!
31324  * @name Register XCVR_AGC_GAIN_TBL_15_12, field BBF_GAIN_14[19:16] (RW)
31325  *
31326  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31327  */
31328 /*@{*/
31329 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_14 field. */
31330 #define XCVR_RD_AGC_GAIN_TBL_15_12_BBF_GAIN_14(base) ((XCVR_AGC_GAIN_TBL_15_12_REG(base) & XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_14_MASK) >> XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_14_SHIFT)
31331 #define XCVR_BRD_AGC_GAIN_TBL_15_12_BBF_GAIN_14(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_14_SHIFT, XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_14_WIDTH))
31332 
31333 /*! @brief Set the BBF_GAIN_14 field to a new value. */
31334 #define XCVR_WR_AGC_GAIN_TBL_15_12_BBF_GAIN_14(base, value) (XCVR_RMW_AGC_GAIN_TBL_15_12(base, XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_14_MASK, XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_14(value)))
31335 #define XCVR_BWR_AGC_GAIN_TBL_15_12_BBF_GAIN_14(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_14_SHIFT), XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_14_SHIFT, XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_14_WIDTH))
31336 /*@}*/
31337 
31338 /*!
31339  * @name Register XCVR_AGC_GAIN_TBL_15_12, field LNM_GAIN_14[23:20] (RW)
31340  *
31341  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31342  */
31343 /*@{*/
31344 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_14 field. */
31345 #define XCVR_RD_AGC_GAIN_TBL_15_12_LNM_GAIN_14(base) ((XCVR_AGC_GAIN_TBL_15_12_REG(base) & XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_14_MASK) >> XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_14_SHIFT)
31346 #define XCVR_BRD_AGC_GAIN_TBL_15_12_LNM_GAIN_14(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_14_SHIFT, XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_14_WIDTH))
31347 
31348 /*! @brief Set the LNM_GAIN_14 field to a new value. */
31349 #define XCVR_WR_AGC_GAIN_TBL_15_12_LNM_GAIN_14(base, value) (XCVR_RMW_AGC_GAIN_TBL_15_12(base, XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_14_MASK, XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_14(value)))
31350 #define XCVR_BWR_AGC_GAIN_TBL_15_12_LNM_GAIN_14(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_14_SHIFT), XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_14_SHIFT, XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_14_WIDTH))
31351 /*@}*/
31352 
31353 /*!
31354  * @name Register XCVR_AGC_GAIN_TBL_15_12, field BBF_GAIN_15[27:24] (RW)
31355  *
31356  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31357  */
31358 /*@{*/
31359 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_15 field. */
31360 #define XCVR_RD_AGC_GAIN_TBL_15_12_BBF_GAIN_15(base) ((XCVR_AGC_GAIN_TBL_15_12_REG(base) & XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_15_MASK) >> XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_15_SHIFT)
31361 #define XCVR_BRD_AGC_GAIN_TBL_15_12_BBF_GAIN_15(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_15_SHIFT, XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_15_WIDTH))
31362 
31363 /*! @brief Set the BBF_GAIN_15 field to a new value. */
31364 #define XCVR_WR_AGC_GAIN_TBL_15_12_BBF_GAIN_15(base, value) (XCVR_RMW_AGC_GAIN_TBL_15_12(base, XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_15_MASK, XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_15(value)))
31365 #define XCVR_BWR_AGC_GAIN_TBL_15_12_BBF_GAIN_15(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_15_SHIFT), XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_15_SHIFT, XCVR_AGC_GAIN_TBL_15_12_BBF_GAIN_15_WIDTH))
31366 /*@}*/
31367 
31368 /*!
31369  * @name Register XCVR_AGC_GAIN_TBL_15_12, field LNM_GAIN_15[31:28] (RW)
31370  *
31371  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31372  */
31373 /*@{*/
31374 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_15 field. */
31375 #define XCVR_RD_AGC_GAIN_TBL_15_12_LNM_GAIN_15(base) ((XCVR_AGC_GAIN_TBL_15_12_REG(base) & XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_15_MASK) >> XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_15_SHIFT)
31376 #define XCVR_BRD_AGC_GAIN_TBL_15_12_LNM_GAIN_15(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_15_SHIFT, XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_15_WIDTH))
31377 
31378 /*! @brief Set the LNM_GAIN_15 field to a new value. */
31379 #define XCVR_WR_AGC_GAIN_TBL_15_12_LNM_GAIN_15(base, value) (XCVR_RMW_AGC_GAIN_TBL_15_12(base, XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_15_MASK, XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_15(value)))
31380 #define XCVR_BWR_AGC_GAIN_TBL_15_12_LNM_GAIN_15(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_15_12_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_15_SHIFT), XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_15_SHIFT, XCVR_AGC_GAIN_TBL_15_12_LNM_GAIN_15_WIDTH))
31381 /*@}*/
31382 
31383 /*******************************************************************************
31384  * XCVR_AGC_GAIN_TBL_19_16 - AGC Gain Tables Step 19..16
31385  ******************************************************************************/
31386 
31387 /*!
31388  * @brief XCVR_AGC_GAIN_TBL_19_16 - AGC Gain Tables Step 19..16 (RW)
31389  *
31390  * Reset value: 0x00000000U
31391  */
31392 /*!
31393  * @name Constants and macros for entire XCVR_AGC_GAIN_TBL_19_16 register
31394  */
31395 /*@{*/
31396 #define XCVR_RD_AGC_GAIN_TBL_19_16(base) (XCVR_AGC_GAIN_TBL_19_16_REG(base))
31397 #define XCVR_WR_AGC_GAIN_TBL_19_16(base, value) (XCVR_AGC_GAIN_TBL_19_16_REG(base) = (value))
31398 #define XCVR_RMW_AGC_GAIN_TBL_19_16(base, mask, value) (XCVR_WR_AGC_GAIN_TBL_19_16(base, (XCVR_RD_AGC_GAIN_TBL_19_16(base) & ~(mask)) | (value)))
31399 #define XCVR_SET_AGC_GAIN_TBL_19_16(base, value) (BME_OR32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), (uint32_t)(value)))
31400 #define XCVR_CLR_AGC_GAIN_TBL_19_16(base, value) (BME_AND32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), (uint32_t)(~(value))))
31401 #define XCVR_TOG_AGC_GAIN_TBL_19_16(base, value) (BME_XOR32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), (uint32_t)(value)))
31402 /*@}*/
31403 
31404 /*
31405  * Constants & macros for individual XCVR_AGC_GAIN_TBL_19_16 bitfields
31406  */
31407 
31408 /*!
31409  * @name Register XCVR_AGC_GAIN_TBL_19_16, field BBF_GAIN_16[3:0] (RW)
31410  *
31411  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31412  */
31413 /*@{*/
31414 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_16 field. */
31415 #define XCVR_RD_AGC_GAIN_TBL_19_16_BBF_GAIN_16(base) ((XCVR_AGC_GAIN_TBL_19_16_REG(base) & XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_16_MASK) >> XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_16_SHIFT)
31416 #define XCVR_BRD_AGC_GAIN_TBL_19_16_BBF_GAIN_16(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_16_SHIFT, XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_16_WIDTH))
31417 
31418 /*! @brief Set the BBF_GAIN_16 field to a new value. */
31419 #define XCVR_WR_AGC_GAIN_TBL_19_16_BBF_GAIN_16(base, value) (XCVR_RMW_AGC_GAIN_TBL_19_16(base, XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_16_MASK, XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_16(value)))
31420 #define XCVR_BWR_AGC_GAIN_TBL_19_16_BBF_GAIN_16(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_16_SHIFT), XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_16_SHIFT, XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_16_WIDTH))
31421 /*@}*/
31422 
31423 /*!
31424  * @name Register XCVR_AGC_GAIN_TBL_19_16, field LNM_GAIN_16[7:4] (RW)
31425  *
31426  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31427  */
31428 /*@{*/
31429 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_16 field. */
31430 #define XCVR_RD_AGC_GAIN_TBL_19_16_LNM_GAIN_16(base) ((XCVR_AGC_GAIN_TBL_19_16_REG(base) & XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_16_MASK) >> XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_16_SHIFT)
31431 #define XCVR_BRD_AGC_GAIN_TBL_19_16_LNM_GAIN_16(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_16_SHIFT, XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_16_WIDTH))
31432 
31433 /*! @brief Set the LNM_GAIN_16 field to a new value. */
31434 #define XCVR_WR_AGC_GAIN_TBL_19_16_LNM_GAIN_16(base, value) (XCVR_RMW_AGC_GAIN_TBL_19_16(base, XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_16_MASK, XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_16(value)))
31435 #define XCVR_BWR_AGC_GAIN_TBL_19_16_LNM_GAIN_16(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_16_SHIFT), XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_16_SHIFT, XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_16_WIDTH))
31436 /*@}*/
31437 
31438 /*!
31439  * @name Register XCVR_AGC_GAIN_TBL_19_16, field BBF_GAIN_17[11:8] (RW)
31440  *
31441  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31442  */
31443 /*@{*/
31444 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_17 field. */
31445 #define XCVR_RD_AGC_GAIN_TBL_19_16_BBF_GAIN_17(base) ((XCVR_AGC_GAIN_TBL_19_16_REG(base) & XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_17_MASK) >> XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_17_SHIFT)
31446 #define XCVR_BRD_AGC_GAIN_TBL_19_16_BBF_GAIN_17(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_17_SHIFT, XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_17_WIDTH))
31447 
31448 /*! @brief Set the BBF_GAIN_17 field to a new value. */
31449 #define XCVR_WR_AGC_GAIN_TBL_19_16_BBF_GAIN_17(base, value) (XCVR_RMW_AGC_GAIN_TBL_19_16(base, XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_17_MASK, XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_17(value)))
31450 #define XCVR_BWR_AGC_GAIN_TBL_19_16_BBF_GAIN_17(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_17_SHIFT), XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_17_SHIFT, XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_17_WIDTH))
31451 /*@}*/
31452 
31453 /*!
31454  * @name Register XCVR_AGC_GAIN_TBL_19_16, field LNM_GAIN_17[15:12] (RW)
31455  *
31456  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31457  */
31458 /*@{*/
31459 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_17 field. */
31460 #define XCVR_RD_AGC_GAIN_TBL_19_16_LNM_GAIN_17(base) ((XCVR_AGC_GAIN_TBL_19_16_REG(base) & XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_17_MASK) >> XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_17_SHIFT)
31461 #define XCVR_BRD_AGC_GAIN_TBL_19_16_LNM_GAIN_17(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_17_SHIFT, XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_17_WIDTH))
31462 
31463 /*! @brief Set the LNM_GAIN_17 field to a new value. */
31464 #define XCVR_WR_AGC_GAIN_TBL_19_16_LNM_GAIN_17(base, value) (XCVR_RMW_AGC_GAIN_TBL_19_16(base, XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_17_MASK, XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_17(value)))
31465 #define XCVR_BWR_AGC_GAIN_TBL_19_16_LNM_GAIN_17(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_17_SHIFT), XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_17_SHIFT, XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_17_WIDTH))
31466 /*@}*/
31467 
31468 /*!
31469  * @name Register XCVR_AGC_GAIN_TBL_19_16, field BBF_GAIN_18[19:16] (RW)
31470  *
31471  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31472  */
31473 /*@{*/
31474 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_18 field. */
31475 #define XCVR_RD_AGC_GAIN_TBL_19_16_BBF_GAIN_18(base) ((XCVR_AGC_GAIN_TBL_19_16_REG(base) & XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_18_MASK) >> XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_18_SHIFT)
31476 #define XCVR_BRD_AGC_GAIN_TBL_19_16_BBF_GAIN_18(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_18_SHIFT, XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_18_WIDTH))
31477 
31478 /*! @brief Set the BBF_GAIN_18 field to a new value. */
31479 #define XCVR_WR_AGC_GAIN_TBL_19_16_BBF_GAIN_18(base, value) (XCVR_RMW_AGC_GAIN_TBL_19_16(base, XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_18_MASK, XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_18(value)))
31480 #define XCVR_BWR_AGC_GAIN_TBL_19_16_BBF_GAIN_18(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_18_SHIFT), XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_18_SHIFT, XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_18_WIDTH))
31481 /*@}*/
31482 
31483 /*!
31484  * @name Register XCVR_AGC_GAIN_TBL_19_16, field LNM_GAIN_18[23:20] (RW)
31485  *
31486  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31487  */
31488 /*@{*/
31489 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_18 field. */
31490 #define XCVR_RD_AGC_GAIN_TBL_19_16_LNM_GAIN_18(base) ((XCVR_AGC_GAIN_TBL_19_16_REG(base) & XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_18_MASK) >> XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_18_SHIFT)
31491 #define XCVR_BRD_AGC_GAIN_TBL_19_16_LNM_GAIN_18(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_18_SHIFT, XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_18_WIDTH))
31492 
31493 /*! @brief Set the LNM_GAIN_18 field to a new value. */
31494 #define XCVR_WR_AGC_GAIN_TBL_19_16_LNM_GAIN_18(base, value) (XCVR_RMW_AGC_GAIN_TBL_19_16(base, XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_18_MASK, XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_18(value)))
31495 #define XCVR_BWR_AGC_GAIN_TBL_19_16_LNM_GAIN_18(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_18_SHIFT), XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_18_SHIFT, XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_18_WIDTH))
31496 /*@}*/
31497 
31498 /*!
31499  * @name Register XCVR_AGC_GAIN_TBL_19_16, field BBF_GAIN_19[27:24] (RW)
31500  *
31501  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31502  */
31503 /*@{*/
31504 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_19 field. */
31505 #define XCVR_RD_AGC_GAIN_TBL_19_16_BBF_GAIN_19(base) ((XCVR_AGC_GAIN_TBL_19_16_REG(base) & XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_19_MASK) >> XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_19_SHIFT)
31506 #define XCVR_BRD_AGC_GAIN_TBL_19_16_BBF_GAIN_19(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_19_SHIFT, XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_19_WIDTH))
31507 
31508 /*! @brief Set the BBF_GAIN_19 field to a new value. */
31509 #define XCVR_WR_AGC_GAIN_TBL_19_16_BBF_GAIN_19(base, value) (XCVR_RMW_AGC_GAIN_TBL_19_16(base, XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_19_MASK, XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_19(value)))
31510 #define XCVR_BWR_AGC_GAIN_TBL_19_16_BBF_GAIN_19(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_19_SHIFT), XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_19_SHIFT, XCVR_AGC_GAIN_TBL_19_16_BBF_GAIN_19_WIDTH))
31511 /*@}*/
31512 
31513 /*!
31514  * @name Register XCVR_AGC_GAIN_TBL_19_16, field LNM_GAIN_19[31:28] (RW)
31515  *
31516  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31517  */
31518 /*@{*/
31519 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_19 field. */
31520 #define XCVR_RD_AGC_GAIN_TBL_19_16_LNM_GAIN_19(base) ((XCVR_AGC_GAIN_TBL_19_16_REG(base) & XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_19_MASK) >> XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_19_SHIFT)
31521 #define XCVR_BRD_AGC_GAIN_TBL_19_16_LNM_GAIN_19(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_19_SHIFT, XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_19_WIDTH))
31522 
31523 /*! @brief Set the LNM_GAIN_19 field to a new value. */
31524 #define XCVR_WR_AGC_GAIN_TBL_19_16_LNM_GAIN_19(base, value) (XCVR_RMW_AGC_GAIN_TBL_19_16(base, XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_19_MASK, XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_19(value)))
31525 #define XCVR_BWR_AGC_GAIN_TBL_19_16_LNM_GAIN_19(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_19_16_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_19_SHIFT), XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_19_SHIFT, XCVR_AGC_GAIN_TBL_19_16_LNM_GAIN_19_WIDTH))
31526 /*@}*/
31527 
31528 /*******************************************************************************
31529  * XCVR_AGC_GAIN_TBL_23_20 - AGC Gain Tables Step 23..20
31530  ******************************************************************************/
31531 
31532 /*!
31533  * @brief XCVR_AGC_GAIN_TBL_23_20 - AGC Gain Tables Step 23..20 (RW)
31534  *
31535  * Reset value: 0x00000000U
31536  */
31537 /*!
31538  * @name Constants and macros for entire XCVR_AGC_GAIN_TBL_23_20 register
31539  */
31540 /*@{*/
31541 #define XCVR_RD_AGC_GAIN_TBL_23_20(base) (XCVR_AGC_GAIN_TBL_23_20_REG(base))
31542 #define XCVR_WR_AGC_GAIN_TBL_23_20(base, value) (XCVR_AGC_GAIN_TBL_23_20_REG(base) = (value))
31543 #define XCVR_RMW_AGC_GAIN_TBL_23_20(base, mask, value) (XCVR_WR_AGC_GAIN_TBL_23_20(base, (XCVR_RD_AGC_GAIN_TBL_23_20(base) & ~(mask)) | (value)))
31544 #define XCVR_SET_AGC_GAIN_TBL_23_20(base, value) (BME_OR32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), (uint32_t)(value)))
31545 #define XCVR_CLR_AGC_GAIN_TBL_23_20(base, value) (BME_AND32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), (uint32_t)(~(value))))
31546 #define XCVR_TOG_AGC_GAIN_TBL_23_20(base, value) (BME_XOR32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), (uint32_t)(value)))
31547 /*@}*/
31548 
31549 /*
31550  * Constants & macros for individual XCVR_AGC_GAIN_TBL_23_20 bitfields
31551  */
31552 
31553 /*!
31554  * @name Register XCVR_AGC_GAIN_TBL_23_20, field BBF_GAIN_20[3:0] (RW)
31555  *
31556  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31557  */
31558 /*@{*/
31559 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_20 field. */
31560 #define XCVR_RD_AGC_GAIN_TBL_23_20_BBF_GAIN_20(base) ((XCVR_AGC_GAIN_TBL_23_20_REG(base) & XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_20_MASK) >> XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_20_SHIFT)
31561 #define XCVR_BRD_AGC_GAIN_TBL_23_20_BBF_GAIN_20(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_20_SHIFT, XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_20_WIDTH))
31562 
31563 /*! @brief Set the BBF_GAIN_20 field to a new value. */
31564 #define XCVR_WR_AGC_GAIN_TBL_23_20_BBF_GAIN_20(base, value) (XCVR_RMW_AGC_GAIN_TBL_23_20(base, XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_20_MASK, XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_20(value)))
31565 #define XCVR_BWR_AGC_GAIN_TBL_23_20_BBF_GAIN_20(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_20_SHIFT), XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_20_SHIFT, XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_20_WIDTH))
31566 /*@}*/
31567 
31568 /*!
31569  * @name Register XCVR_AGC_GAIN_TBL_23_20, field LNM_GAIN_20[7:4] (RW)
31570  *
31571  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31572  */
31573 /*@{*/
31574 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_20 field. */
31575 #define XCVR_RD_AGC_GAIN_TBL_23_20_LNM_GAIN_20(base) ((XCVR_AGC_GAIN_TBL_23_20_REG(base) & XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_20_MASK) >> XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_20_SHIFT)
31576 #define XCVR_BRD_AGC_GAIN_TBL_23_20_LNM_GAIN_20(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_20_SHIFT, XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_20_WIDTH))
31577 
31578 /*! @brief Set the LNM_GAIN_20 field to a new value. */
31579 #define XCVR_WR_AGC_GAIN_TBL_23_20_LNM_GAIN_20(base, value) (XCVR_RMW_AGC_GAIN_TBL_23_20(base, XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_20_MASK, XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_20(value)))
31580 #define XCVR_BWR_AGC_GAIN_TBL_23_20_LNM_GAIN_20(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_20_SHIFT), XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_20_SHIFT, XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_20_WIDTH))
31581 /*@}*/
31582 
31583 /*!
31584  * @name Register XCVR_AGC_GAIN_TBL_23_20, field BBF_GAIN_21[11:8] (RW)
31585  *
31586  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31587  */
31588 /*@{*/
31589 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_21 field. */
31590 #define XCVR_RD_AGC_GAIN_TBL_23_20_BBF_GAIN_21(base) ((XCVR_AGC_GAIN_TBL_23_20_REG(base) & XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_21_MASK) >> XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_21_SHIFT)
31591 #define XCVR_BRD_AGC_GAIN_TBL_23_20_BBF_GAIN_21(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_21_SHIFT, XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_21_WIDTH))
31592 
31593 /*! @brief Set the BBF_GAIN_21 field to a new value. */
31594 #define XCVR_WR_AGC_GAIN_TBL_23_20_BBF_GAIN_21(base, value) (XCVR_RMW_AGC_GAIN_TBL_23_20(base, XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_21_MASK, XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_21(value)))
31595 #define XCVR_BWR_AGC_GAIN_TBL_23_20_BBF_GAIN_21(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_21_SHIFT), XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_21_SHIFT, XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_21_WIDTH))
31596 /*@}*/
31597 
31598 /*!
31599  * @name Register XCVR_AGC_GAIN_TBL_23_20, field LNM_GAIN_21[15:12] (RW)
31600  *
31601  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31602  */
31603 /*@{*/
31604 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_21 field. */
31605 #define XCVR_RD_AGC_GAIN_TBL_23_20_LNM_GAIN_21(base) ((XCVR_AGC_GAIN_TBL_23_20_REG(base) & XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_21_MASK) >> XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_21_SHIFT)
31606 #define XCVR_BRD_AGC_GAIN_TBL_23_20_LNM_GAIN_21(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_21_SHIFT, XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_21_WIDTH))
31607 
31608 /*! @brief Set the LNM_GAIN_21 field to a new value. */
31609 #define XCVR_WR_AGC_GAIN_TBL_23_20_LNM_GAIN_21(base, value) (XCVR_RMW_AGC_GAIN_TBL_23_20(base, XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_21_MASK, XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_21(value)))
31610 #define XCVR_BWR_AGC_GAIN_TBL_23_20_LNM_GAIN_21(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_21_SHIFT), XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_21_SHIFT, XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_21_WIDTH))
31611 /*@}*/
31612 
31613 /*!
31614  * @name Register XCVR_AGC_GAIN_TBL_23_20, field BBF_GAIN_22[19:16] (RW)
31615  *
31616  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31617  */
31618 /*@{*/
31619 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_22 field. */
31620 #define XCVR_RD_AGC_GAIN_TBL_23_20_BBF_GAIN_22(base) ((XCVR_AGC_GAIN_TBL_23_20_REG(base) & XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_22_MASK) >> XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_22_SHIFT)
31621 #define XCVR_BRD_AGC_GAIN_TBL_23_20_BBF_GAIN_22(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_22_SHIFT, XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_22_WIDTH))
31622 
31623 /*! @brief Set the BBF_GAIN_22 field to a new value. */
31624 #define XCVR_WR_AGC_GAIN_TBL_23_20_BBF_GAIN_22(base, value) (XCVR_RMW_AGC_GAIN_TBL_23_20(base, XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_22_MASK, XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_22(value)))
31625 #define XCVR_BWR_AGC_GAIN_TBL_23_20_BBF_GAIN_22(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_22_SHIFT), XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_22_SHIFT, XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_22_WIDTH))
31626 /*@}*/
31627 
31628 /*!
31629  * @name Register XCVR_AGC_GAIN_TBL_23_20, field LNM_GAIN_22[23:20] (RW)
31630  *
31631  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31632  */
31633 /*@{*/
31634 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_22 field. */
31635 #define XCVR_RD_AGC_GAIN_TBL_23_20_LNM_GAIN_22(base) ((XCVR_AGC_GAIN_TBL_23_20_REG(base) & XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_22_MASK) >> XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_22_SHIFT)
31636 #define XCVR_BRD_AGC_GAIN_TBL_23_20_LNM_GAIN_22(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_22_SHIFT, XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_22_WIDTH))
31637 
31638 /*! @brief Set the LNM_GAIN_22 field to a new value. */
31639 #define XCVR_WR_AGC_GAIN_TBL_23_20_LNM_GAIN_22(base, value) (XCVR_RMW_AGC_GAIN_TBL_23_20(base, XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_22_MASK, XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_22(value)))
31640 #define XCVR_BWR_AGC_GAIN_TBL_23_20_LNM_GAIN_22(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_22_SHIFT), XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_22_SHIFT, XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_22_WIDTH))
31641 /*@}*/
31642 
31643 /*!
31644  * @name Register XCVR_AGC_GAIN_TBL_23_20, field BBF_GAIN_23[27:24] (RW)
31645  *
31646  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31647  */
31648 /*@{*/
31649 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_23 field. */
31650 #define XCVR_RD_AGC_GAIN_TBL_23_20_BBF_GAIN_23(base) ((XCVR_AGC_GAIN_TBL_23_20_REG(base) & XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_23_MASK) >> XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_23_SHIFT)
31651 #define XCVR_BRD_AGC_GAIN_TBL_23_20_BBF_GAIN_23(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_23_SHIFT, XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_23_WIDTH))
31652 
31653 /*! @brief Set the BBF_GAIN_23 field to a new value. */
31654 #define XCVR_WR_AGC_GAIN_TBL_23_20_BBF_GAIN_23(base, value) (XCVR_RMW_AGC_GAIN_TBL_23_20(base, XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_23_MASK, XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_23(value)))
31655 #define XCVR_BWR_AGC_GAIN_TBL_23_20_BBF_GAIN_23(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_23_SHIFT), XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_23_SHIFT, XCVR_AGC_GAIN_TBL_23_20_BBF_GAIN_23_WIDTH))
31656 /*@}*/
31657 
31658 /*!
31659  * @name Register XCVR_AGC_GAIN_TBL_23_20, field LNM_GAIN_23[31:28] (RW)
31660  *
31661  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31662  */
31663 /*@{*/
31664 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_23 field. */
31665 #define XCVR_RD_AGC_GAIN_TBL_23_20_LNM_GAIN_23(base) ((XCVR_AGC_GAIN_TBL_23_20_REG(base) & XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_23_MASK) >> XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_23_SHIFT)
31666 #define XCVR_BRD_AGC_GAIN_TBL_23_20_LNM_GAIN_23(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_23_SHIFT, XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_23_WIDTH))
31667 
31668 /*! @brief Set the LNM_GAIN_23 field to a new value. */
31669 #define XCVR_WR_AGC_GAIN_TBL_23_20_LNM_GAIN_23(base, value) (XCVR_RMW_AGC_GAIN_TBL_23_20(base, XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_23_MASK, XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_23(value)))
31670 #define XCVR_BWR_AGC_GAIN_TBL_23_20_LNM_GAIN_23(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_23_20_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_23_SHIFT), XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_23_SHIFT, XCVR_AGC_GAIN_TBL_23_20_LNM_GAIN_23_WIDTH))
31671 /*@}*/
31672 
31673 /*******************************************************************************
31674  * XCVR_AGC_GAIN_TBL_26_24 - AGC Gain Tables Step 26..24
31675  ******************************************************************************/
31676 
31677 /*!
31678  * @brief XCVR_AGC_GAIN_TBL_26_24 - AGC Gain Tables Step 26..24 (RW)
31679  *
31680  * Reset value: 0x00000000U
31681  */
31682 /*!
31683  * @name Constants and macros for entire XCVR_AGC_GAIN_TBL_26_24 register
31684  */
31685 /*@{*/
31686 #define XCVR_RD_AGC_GAIN_TBL_26_24(base) (XCVR_AGC_GAIN_TBL_26_24_REG(base))
31687 #define XCVR_WR_AGC_GAIN_TBL_26_24(base, value) (XCVR_AGC_GAIN_TBL_26_24_REG(base) = (value))
31688 #define XCVR_RMW_AGC_GAIN_TBL_26_24(base, mask, value) (XCVR_WR_AGC_GAIN_TBL_26_24(base, (XCVR_RD_AGC_GAIN_TBL_26_24(base) & ~(mask)) | (value)))
31689 #define XCVR_SET_AGC_GAIN_TBL_26_24(base, value) (BME_OR32(&XCVR_AGC_GAIN_TBL_26_24_REG(base), (uint32_t)(value)))
31690 #define XCVR_CLR_AGC_GAIN_TBL_26_24(base, value) (BME_AND32(&XCVR_AGC_GAIN_TBL_26_24_REG(base), (uint32_t)(~(value))))
31691 #define XCVR_TOG_AGC_GAIN_TBL_26_24(base, value) (BME_XOR32(&XCVR_AGC_GAIN_TBL_26_24_REG(base), (uint32_t)(value)))
31692 /*@}*/
31693 
31694 /*
31695  * Constants & macros for individual XCVR_AGC_GAIN_TBL_26_24 bitfields
31696  */
31697 
31698 /*!
31699  * @name Register XCVR_AGC_GAIN_TBL_26_24, field BBF_GAIN_24[3:0] (RW)
31700  *
31701  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31702  */
31703 /*@{*/
31704 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_24 field. */
31705 #define XCVR_RD_AGC_GAIN_TBL_26_24_BBF_GAIN_24(base) ((XCVR_AGC_GAIN_TBL_26_24_REG(base) & XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_24_MASK) >> XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_24_SHIFT)
31706 #define XCVR_BRD_AGC_GAIN_TBL_26_24_BBF_GAIN_24(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_26_24_REG(base), XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_24_SHIFT, XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_24_WIDTH))
31707 
31708 /*! @brief Set the BBF_GAIN_24 field to a new value. */
31709 #define XCVR_WR_AGC_GAIN_TBL_26_24_BBF_GAIN_24(base, value) (XCVR_RMW_AGC_GAIN_TBL_26_24(base, XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_24_MASK, XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_24(value)))
31710 #define XCVR_BWR_AGC_GAIN_TBL_26_24_BBF_GAIN_24(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_26_24_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_24_SHIFT), XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_24_SHIFT, XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_24_WIDTH))
31711 /*@}*/
31712 
31713 /*!
31714  * @name Register XCVR_AGC_GAIN_TBL_26_24, field LNM_GAIN_24[7:4] (RW)
31715  *
31716  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31717  */
31718 /*@{*/
31719 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_24 field. */
31720 #define XCVR_RD_AGC_GAIN_TBL_26_24_LNM_GAIN_24(base) ((XCVR_AGC_GAIN_TBL_26_24_REG(base) & XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_24_MASK) >> XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_24_SHIFT)
31721 #define XCVR_BRD_AGC_GAIN_TBL_26_24_LNM_GAIN_24(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_26_24_REG(base), XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_24_SHIFT, XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_24_WIDTH))
31722 
31723 /*! @brief Set the LNM_GAIN_24 field to a new value. */
31724 #define XCVR_WR_AGC_GAIN_TBL_26_24_LNM_GAIN_24(base, value) (XCVR_RMW_AGC_GAIN_TBL_26_24(base, XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_24_MASK, XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_24(value)))
31725 #define XCVR_BWR_AGC_GAIN_TBL_26_24_LNM_GAIN_24(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_26_24_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_24_SHIFT), XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_24_SHIFT, XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_24_WIDTH))
31726 /*@}*/
31727 
31728 /*!
31729  * @name Register XCVR_AGC_GAIN_TBL_26_24, field BBF_GAIN_25[11:8] (RW)
31730  *
31731  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31732  */
31733 /*@{*/
31734 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_25 field. */
31735 #define XCVR_RD_AGC_GAIN_TBL_26_24_BBF_GAIN_25(base) ((XCVR_AGC_GAIN_TBL_26_24_REG(base) & XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_25_MASK) >> XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_25_SHIFT)
31736 #define XCVR_BRD_AGC_GAIN_TBL_26_24_BBF_GAIN_25(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_26_24_REG(base), XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_25_SHIFT, XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_25_WIDTH))
31737 
31738 /*! @brief Set the BBF_GAIN_25 field to a new value. */
31739 #define XCVR_WR_AGC_GAIN_TBL_26_24_BBF_GAIN_25(base, value) (XCVR_RMW_AGC_GAIN_TBL_26_24(base, XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_25_MASK, XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_25(value)))
31740 #define XCVR_BWR_AGC_GAIN_TBL_26_24_BBF_GAIN_25(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_26_24_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_25_SHIFT), XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_25_SHIFT, XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_25_WIDTH))
31741 /*@}*/
31742 
31743 /*!
31744  * @name Register XCVR_AGC_GAIN_TBL_26_24, field LNM_GAIN_25[15:12] (RW)
31745  *
31746  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31747  */
31748 /*@{*/
31749 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_25 field. */
31750 #define XCVR_RD_AGC_GAIN_TBL_26_24_LNM_GAIN_25(base) ((XCVR_AGC_GAIN_TBL_26_24_REG(base) & XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_25_MASK) >> XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_25_SHIFT)
31751 #define XCVR_BRD_AGC_GAIN_TBL_26_24_LNM_GAIN_25(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_26_24_REG(base), XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_25_SHIFT, XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_25_WIDTH))
31752 
31753 /*! @brief Set the LNM_GAIN_25 field to a new value. */
31754 #define XCVR_WR_AGC_GAIN_TBL_26_24_LNM_GAIN_25(base, value) (XCVR_RMW_AGC_GAIN_TBL_26_24(base, XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_25_MASK, XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_25(value)))
31755 #define XCVR_BWR_AGC_GAIN_TBL_26_24_LNM_GAIN_25(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_26_24_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_25_SHIFT), XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_25_SHIFT, XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_25_WIDTH))
31756 /*@}*/
31757 
31758 /*!
31759  * @name Register XCVR_AGC_GAIN_TBL_26_24, field BBF_GAIN_26[19:16] (RW)
31760  *
31761  * BBF GAIN 0=0 dB, 1=3 dB, 2=6 dB … A=30 dB.
31762  */
31763 /*@{*/
31764 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_26 field. */
31765 #define XCVR_RD_AGC_GAIN_TBL_26_24_BBF_GAIN_26(base) ((XCVR_AGC_GAIN_TBL_26_24_REG(base) & XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_26_MASK) >> XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_26_SHIFT)
31766 #define XCVR_BRD_AGC_GAIN_TBL_26_24_BBF_GAIN_26(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_26_24_REG(base), XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_26_SHIFT, XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_26_WIDTH))
31767 
31768 /*! @brief Set the BBF_GAIN_26 field to a new value. */
31769 #define XCVR_WR_AGC_GAIN_TBL_26_24_BBF_GAIN_26(base, value) (XCVR_RMW_AGC_GAIN_TBL_26_24(base, XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_26_MASK, XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_26(value)))
31770 #define XCVR_BWR_AGC_GAIN_TBL_26_24_BBF_GAIN_26(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_26_24_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_26_SHIFT), XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_26_SHIFT, XCVR_AGC_GAIN_TBL_26_24_BBF_GAIN_26_WIDTH))
31771 /*@}*/
31772 
31773 /*!
31774  * @name Register XCVR_AGC_GAIN_TBL_26_24, field LNM_GAIN_26[23:20] (RW)
31775  *
31776  * LNM GAIN 0=-3 dB, 1=3 dB, 2=9 dB … 8=45 dB.
31777  */
31778 /*@{*/
31779 /*! @brief Read current value of the XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_26 field. */
31780 #define XCVR_RD_AGC_GAIN_TBL_26_24_LNM_GAIN_26(base) ((XCVR_AGC_GAIN_TBL_26_24_REG(base) & XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_26_MASK) >> XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_26_SHIFT)
31781 #define XCVR_BRD_AGC_GAIN_TBL_26_24_LNM_GAIN_26(base) (BME_UBFX32(&XCVR_AGC_GAIN_TBL_26_24_REG(base), XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_26_SHIFT, XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_26_WIDTH))
31782 
31783 /*! @brief Set the LNM_GAIN_26 field to a new value. */
31784 #define XCVR_WR_AGC_GAIN_TBL_26_24_LNM_GAIN_26(base, value) (XCVR_RMW_AGC_GAIN_TBL_26_24(base, XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_26_MASK, XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_26(value)))
31785 #define XCVR_BWR_AGC_GAIN_TBL_26_24_LNM_GAIN_26(base, value) (BME_BFI32(&XCVR_AGC_GAIN_TBL_26_24_REG(base), ((uint32_t)(value) << XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_26_SHIFT), XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_26_SHIFT, XCVR_AGC_GAIN_TBL_26_24_LNM_GAIN_26_WIDTH))
31786 /*@}*/
31787 
31788 /*******************************************************************************
31789  * XCVR_DCOC_OFFSET_ - DCOC Offset
31790  ******************************************************************************/
31791 
31792 /*!
31793  * @brief XCVR_DCOC_OFFSET_ - DCOC Offset (RW)
31794  *
31795  * Reset value: 0x00000000U
31796  */
31797 /*!
31798  * @name Constants and macros for entire XCVR_DCOC_OFFSET_ register
31799  */
31800 /*@{*/
31801 #define XCVR_RD_DCOC_OFFSET_(base, index) (XCVR_DCOC_OFFSET__REG(base, index))
31802 #define XCVR_WR_DCOC_OFFSET_(base, index, value) (XCVR_DCOC_OFFSET__REG(base, index) = (value))
31803 #define XCVR_RMW_DCOC_OFFSET_(base, index, mask, value) (XCVR_WR_DCOC_OFFSET_(base, index, (XCVR_RD_DCOC_OFFSET_(base, index) & ~(mask)) | (value)))
31804 #define XCVR_SET_DCOC_OFFSET_(base, index, value) (BME_OR32(&XCVR_DCOC_OFFSET__REG(base, index), (uint32_t)(value)))
31805 #define XCVR_CLR_DCOC_OFFSET_(base, index, value) (BME_AND32(&XCVR_DCOC_OFFSET__REG(base, index), (uint32_t)(~(value))))
31806 #define XCVR_TOG_DCOC_OFFSET_(base, index, value) (BME_XOR32(&XCVR_DCOC_OFFSET__REG(base, index), (uint32_t)(value)))
31807 /*@}*/
31808 
31809 /*
31810  * Constants & macros for individual XCVR_DCOC_OFFSET_ bitfields
31811  */
31812 
31813 /*!
31814  * @name Register XCVR_DCOC_OFFSET_, field DCOC_BBF_OFFSET_I[5:0] (RW)
31815  *
31816  * DCOC BBF I-channel offset. When RX_DCOC_CAL_EN=1, this table is generated by
31817  * the DCOC during calibration. When RX_DCOC_CAL_EN=0, this table may optionally
31818  * be written by software.
31819  */
31820 /*@{*/
31821 /*! @brief Read current value of the XCVR_DCOC_OFFSET__DCOC_BBF_OFFSET_I field. */
31822 #define XCVR_RD_DCOC_OFFSET__DCOC_BBF_OFFSET_I(base, index) ((XCVR_DCOC_OFFSET__REG(base, index) & XCVR_DCOC_OFFSET__DCOC_BBF_OFFSET_I_MASK) >> XCVR_DCOC_OFFSET__DCOC_BBF_OFFSET_I_SHIFT)
31823 #define XCVR_BRD_DCOC_OFFSET__DCOC_BBF_OFFSET_I(base, index) (BME_UBFX32(&XCVR_DCOC_OFFSET__REG(base, index), XCVR_DCOC_OFFSET__DCOC_BBF_OFFSET_I_SHIFT, XCVR_DCOC_OFFSET__DCOC_BBF_OFFSET_I_WIDTH))
31824 
31825 /*! @brief Set the DCOC_BBF_OFFSET_I field to a new value. */
31826 #define XCVR_WR_DCOC_OFFSET__DCOC_BBF_OFFSET_I(base, index, value) (XCVR_RMW_DCOC_OFFSET_(base, index, XCVR_DCOC_OFFSET__DCOC_BBF_OFFSET_I_MASK, XCVR_DCOC_OFFSET__DCOC_BBF_OFFSET_I(value)))
31827 #define XCVR_BWR_DCOC_OFFSET__DCOC_BBF_OFFSET_I(base, index, value) (BME_BFI32(&XCVR_DCOC_OFFSET__REG(base, index), ((uint32_t)(value) << XCVR_DCOC_OFFSET__DCOC_BBF_OFFSET_I_SHIFT), XCVR_DCOC_OFFSET__DCOC_BBF_OFFSET_I_SHIFT, XCVR_DCOC_OFFSET__DCOC_BBF_OFFSET_I_WIDTH))
31828 /*@}*/
31829 
31830 /*!
31831  * @name Register XCVR_DCOC_OFFSET_, field DCOC_BBF_OFFSET_Q[13:8] (RW)
31832  *
31833  * DCOC BBF Q-channel offset. When RX_DCOC_CAL_EN=1, this table is generated by
31834  * the DCOC during calibration. When RX_DCOC_CAL_EN=0, this table may optionally
31835  * be written by software.
31836  */
31837 /*@{*/
31838 /*! @brief Read current value of the XCVR_DCOC_OFFSET__DCOC_BBF_OFFSET_Q field. */
31839 #define XCVR_RD_DCOC_OFFSET__DCOC_BBF_OFFSET_Q(base, index) ((XCVR_DCOC_OFFSET__REG(base, index) & XCVR_DCOC_OFFSET__DCOC_BBF_OFFSET_Q_MASK) >> XCVR_DCOC_OFFSET__DCOC_BBF_OFFSET_Q_SHIFT)
31840 #define XCVR_BRD_DCOC_OFFSET__DCOC_BBF_OFFSET_Q(base, index) (BME_UBFX32(&XCVR_DCOC_OFFSET__REG(base, index), XCVR_DCOC_OFFSET__DCOC_BBF_OFFSET_Q_SHIFT, XCVR_DCOC_OFFSET__DCOC_BBF_OFFSET_Q_WIDTH))
31841 
31842 /*! @brief Set the DCOC_BBF_OFFSET_Q field to a new value. */
31843 #define XCVR_WR_DCOC_OFFSET__DCOC_BBF_OFFSET_Q(base, index, value) (XCVR_RMW_DCOC_OFFSET_(base, index, XCVR_DCOC_OFFSET__DCOC_BBF_OFFSET_Q_MASK, XCVR_DCOC_OFFSET__DCOC_BBF_OFFSET_Q(value)))
31844 #define XCVR_BWR_DCOC_OFFSET__DCOC_BBF_OFFSET_Q(base, index, value) (BME_BFI32(&XCVR_DCOC_OFFSET__REG(base, index), ((uint32_t)(value) << XCVR_DCOC_OFFSET__DCOC_BBF_OFFSET_Q_SHIFT), XCVR_DCOC_OFFSET__DCOC_BBF_OFFSET_Q_SHIFT, XCVR_DCOC_OFFSET__DCOC_BBF_OFFSET_Q_WIDTH))
31845 /*@}*/
31846 
31847 /*!
31848  * @name Register XCVR_DCOC_OFFSET_, field DCOC_TZA_OFFSET_I[23:16] (RW)
31849  *
31850  * DCOC TZA I-channel offset. When RX_DCOC_CAL_EN=1, this table is generated by
31851  * the DCOC during calibration. When RX_DCOC_CAL_EN=0, this table may optionally
31852  * be written by software.
31853  */
31854 /*@{*/
31855 /*! @brief Read current value of the XCVR_DCOC_OFFSET__DCOC_TZA_OFFSET_I field. */
31856 #define XCVR_RD_DCOC_OFFSET__DCOC_TZA_OFFSET_I(base, index) ((XCVR_DCOC_OFFSET__REG(base, index) & XCVR_DCOC_OFFSET__DCOC_TZA_OFFSET_I_MASK) >> XCVR_DCOC_OFFSET__DCOC_TZA_OFFSET_I_SHIFT)
31857 #define XCVR_BRD_DCOC_OFFSET__DCOC_TZA_OFFSET_I(base, index) (BME_UBFX32(&XCVR_DCOC_OFFSET__REG(base, index), XCVR_DCOC_OFFSET__DCOC_TZA_OFFSET_I_SHIFT, XCVR_DCOC_OFFSET__DCOC_TZA_OFFSET_I_WIDTH))
31858 
31859 /*! @brief Set the DCOC_TZA_OFFSET_I field to a new value. */
31860 #define XCVR_WR_DCOC_OFFSET__DCOC_TZA_OFFSET_I(base, index, value) (XCVR_RMW_DCOC_OFFSET_(base, index, XCVR_DCOC_OFFSET__DCOC_TZA_OFFSET_I_MASK, XCVR_DCOC_OFFSET__DCOC_TZA_OFFSET_I(value)))
31861 #define XCVR_BWR_DCOC_OFFSET__DCOC_TZA_OFFSET_I(base, index, value) (BME_BFI32(&XCVR_DCOC_OFFSET__REG(base, index), ((uint32_t)(value) << XCVR_DCOC_OFFSET__DCOC_TZA_OFFSET_I_SHIFT), XCVR_DCOC_OFFSET__DCOC_TZA_OFFSET_I_SHIFT, XCVR_DCOC_OFFSET__DCOC_TZA_OFFSET_I_WIDTH))
31862 /*@}*/
31863 
31864 /*!
31865  * @name Register XCVR_DCOC_OFFSET_, field DCOC_TZA_OFFSET_Q[31:24] (RW)
31866  *
31867  * DCOC TZA Q-channel offset. When RX_DCOC_CAL_EN=1, this table is generated by
31868  * the DCOC during calibration. When RX_DCOC_CAL_EN=0, this table may optionally
31869  * be written by software.
31870  */
31871 /*@{*/
31872 /*! @brief Read current value of the XCVR_DCOC_OFFSET__DCOC_TZA_OFFSET_Q field. */
31873 #define XCVR_RD_DCOC_OFFSET__DCOC_TZA_OFFSET_Q(base, index) ((XCVR_DCOC_OFFSET__REG(base, index) & XCVR_DCOC_OFFSET__DCOC_TZA_OFFSET_Q_MASK) >> XCVR_DCOC_OFFSET__DCOC_TZA_OFFSET_Q_SHIFT)
31874 #define XCVR_BRD_DCOC_OFFSET__DCOC_TZA_OFFSET_Q(base, index) (BME_UBFX32(&XCVR_DCOC_OFFSET__REG(base, index), XCVR_DCOC_OFFSET__DCOC_TZA_OFFSET_Q_SHIFT, XCVR_DCOC_OFFSET__DCOC_TZA_OFFSET_Q_WIDTH))
31875 
31876 /*! @brief Set the DCOC_TZA_OFFSET_Q field to a new value. */
31877 #define XCVR_WR_DCOC_OFFSET__DCOC_TZA_OFFSET_Q(base, index, value) (XCVR_RMW_DCOC_OFFSET_(base, index, XCVR_DCOC_OFFSET__DCOC_TZA_OFFSET_Q_MASK, XCVR_DCOC_OFFSET__DCOC_TZA_OFFSET_Q(value)))
31878 #define XCVR_BWR_DCOC_OFFSET__DCOC_TZA_OFFSET_Q(base, index, value) (BME_BFI32(&XCVR_DCOC_OFFSET__REG(base, index), ((uint32_t)(value) << XCVR_DCOC_OFFSET__DCOC_TZA_OFFSET_Q_SHIFT), XCVR_DCOC_OFFSET__DCOC_TZA_OFFSET_Q_SHIFT, XCVR_DCOC_OFFSET__DCOC_TZA_OFFSET_Q_WIDTH))
31879 /*@}*/
31880 
31881 /*******************************************************************************
31882  * XCVR_DCOC_TZA_STEP_ - DCOC TZA DC step
31883  ******************************************************************************/
31884 
31885 /*!
31886  * @brief XCVR_DCOC_TZA_STEP_ - DCOC TZA DC step (RW)
31887  *
31888  * Reset value: 0x00000000U
31889  */
31890 /*!
31891  * @name Constants and macros for entire XCVR_DCOC_TZA_STEP_ register
31892  */
31893 /*@{*/
31894 #define XCVR_RD_DCOC_TZA_STEP_(base, index) (XCVR_DCOC_TZA_STEP__REG(base, index))
31895 #define XCVR_WR_DCOC_TZA_STEP_(base, index, value) (XCVR_DCOC_TZA_STEP__REG(base, index) = (value))
31896 #define XCVR_RMW_DCOC_TZA_STEP_(base, index, mask, value) (XCVR_WR_DCOC_TZA_STEP_(base, index, (XCVR_RD_DCOC_TZA_STEP_(base, index) & ~(mask)) | (value)))
31897 #define XCVR_SET_DCOC_TZA_STEP_(base, index, value) (BME_OR32(&XCVR_DCOC_TZA_STEP__REG(base, index), (uint32_t)(value)))
31898 #define XCVR_CLR_DCOC_TZA_STEP_(base, index, value) (BME_AND32(&XCVR_DCOC_TZA_STEP__REG(base, index), (uint32_t)(~(value))))
31899 #define XCVR_TOG_DCOC_TZA_STEP_(base, index, value) (BME_XOR32(&XCVR_DCOC_TZA_STEP__REG(base, index), (uint32_t)(value)))
31900 /*@}*/
31901 
31902 /*
31903  * Constants & macros for individual XCVR_DCOC_TZA_STEP_ bitfields
31904  */
31905 
31906 /*!
31907  * @name Register XCVR_DCOC_TZA_STEP_, field DCOC_TZA_STEP_RCP[12:0] (RW)
31908  *
31909  * DCOC TZA Reciprocal of Step Size, (format: [00]13). This the reciprocal of
31910  * the DCOC_TZA_STEP_GAIN. E.g., for DCOC_TZA_STEP_0, it's nominal value is
31911  * 1.0/9.209 or 0.10859. The value is stored as a 15bit fractional value (though only 13
31912  * bits are programmed), so use round(0.10859*2^15) = 3588decimal.
31913  */
31914 /*@{*/
31915 /*! @brief Read current value of the XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP field. */
31916 #define XCVR_RD_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP(base, index) ((XCVR_DCOC_TZA_STEP__REG(base, index) & XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK) >> XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT)
31917 #define XCVR_BRD_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP(base, index) (BME_UBFX32(&XCVR_DCOC_TZA_STEP__REG(base, index), XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT, XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_WIDTH))
31918 
31919 /*! @brief Set the DCOC_TZA_STEP_RCP field to a new value. */
31920 #define XCVR_WR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP(base, index, value) (XCVR_RMW_DCOC_TZA_STEP_(base, index, XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_MASK, XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP(value)))
31921 #define XCVR_BWR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP(base, index, value) (BME_BFI32(&XCVR_DCOC_TZA_STEP__REG(base, index), ((uint32_t)(value) << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT), XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_SHIFT, XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_RCP_WIDTH))
31922 /*@}*/
31923 
31924 /*!
31925  * @name Register XCVR_DCOC_TZA_STEP_, field DCOC_TZA_STEP_GAIN[27:16] (RW)
31926  *
31927  * DCOC TZA Step Size with gain (format 9.3). The nominal value for this is the
31928  * TZA DAC resolution (1.4/2^8= 5.47mV) times AGC gain of -1.7dB (
31929  * 10^(-1.7/20)=0.822) times an AGC mV to quantization scaling factor (2^11/1000 = 2.048),
31930  * times the nth BBF gain. E.g., for XCVR_DCOC_TZA_STEP_0 the BBF gain index 0 is
31931  * 0dB=1.0, so DCOC_TZA_STEP_GAIN = 9.209. This value is stored in the register with
31932  * 3 fractional bits, so use round(9.209*2^3) = 74 decimal.
31933  */
31934 /*@{*/
31935 /*! @brief Read current value of the XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN field. */
31936 #define XCVR_RD_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN(base, index) ((XCVR_DCOC_TZA_STEP__REG(base, index) & XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK) >> XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT)
31937 #define XCVR_BRD_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN(base, index) (BME_UBFX32(&XCVR_DCOC_TZA_STEP__REG(base, index), XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT, XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_WIDTH))
31938 
31939 /*! @brief Set the DCOC_TZA_STEP_GAIN field to a new value. */
31940 #define XCVR_WR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN(base, index, value) (XCVR_RMW_DCOC_TZA_STEP_(base, index, XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_MASK, XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN(value)))
31941 #define XCVR_BWR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN(base, index, value) (BME_BFI32(&XCVR_DCOC_TZA_STEP__REG(base, index), ((uint32_t)(value) << XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT), XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_SHIFT, XCVR_DCOC_TZA_STEP__DCOC_TZA_STEP_GAIN_WIDTH))
31942 /*@}*/
31943 
31944 /*******************************************************************************
31945  * XCVR_DCOC_CAL_ALPHA - DCOC Calibration Alpha
31946  ******************************************************************************/
31947 
31948 /*!
31949  * @brief XCVR_DCOC_CAL_ALPHA - DCOC Calibration Alpha (RO)
31950  *
31951  * Reset value: 0x00000000U
31952  */
31953 /*!
31954  * @name Constants and macros for entire XCVR_DCOC_CAL_ALPHA register
31955  */
31956 /*@{*/
31957 #define XCVR_RD_DCOC_CAL_ALPHA(base) (XCVR_DCOC_CAL_ALPHA_REG(base))
31958 /*@}*/
31959 
31960 /*
31961  * Constants & macros for individual XCVR_DCOC_CAL_ALPHA bitfields
31962  */
31963 
31964 /*!
31965  * @name Register XCVR_DCOC_CAL_ALPHA, field DCOC_CAL_ALPHA_I[15:0] (RO)
31966  *
31967  * DCOC Calibration I-channel ALPHA. This read-only, signed 16bit value
31968  * represents the I channel estimate of the ALPHA DC component calculated in DCOC
31969  * calibration. This is provided for debug/characterization purposes.
31970  */
31971 /*@{*/
31972 /*! @brief Read current value of the XCVR_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I field. */
31973 #define XCVR_RD_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I(base) ((XCVR_DCOC_CAL_ALPHA_REG(base) & XCVR_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_MASK) >> XCVR_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_SHIFT)
31974 #define XCVR_BRD_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I(base) (BME_UBFX32(&XCVR_DCOC_CAL_ALPHA_REG(base), XCVR_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_SHIFT, XCVR_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_I_WIDTH))
31975 /*@}*/
31976 
31977 /*!
31978  * @name Register XCVR_DCOC_CAL_ALPHA, field DCOC_CAL_ALPHA_Q[31:16] (RO)
31979  *
31980  * DCOC Calibration Q-channel ALPHA. This read-only, signed 16bit value
31981  * represents the Q channel estimate of the ALPHA DC component calculated in DCOC
31982  * calibration. This is provided for debug/characterization purposes.
31983  */
31984 /*@{*/
31985 /*! @brief Read current value of the XCVR_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q field. */
31986 #define XCVR_RD_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q(base) ((XCVR_DCOC_CAL_ALPHA_REG(base) & XCVR_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_MASK) >> XCVR_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_SHIFT)
31987 #define XCVR_BRD_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q(base) (BME_UBFX32(&XCVR_DCOC_CAL_ALPHA_REG(base), XCVR_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_SHIFT, XCVR_DCOC_CAL_ALPHA_DCOC_CAL_ALPHA_Q_WIDTH))
31988 /*@}*/
31989 
31990 /*******************************************************************************
31991  * XCVR_DCOC_CAL_BETA - DCOC Calibration Beta
31992  ******************************************************************************/
31993 
31994 /*!
31995  * @brief XCVR_DCOC_CAL_BETA - DCOC Calibration Beta (RO)
31996  *
31997  * Reset value: 0x00000000U
31998  */
31999 /*!
32000  * @name Constants and macros for entire XCVR_DCOC_CAL_BETA register
32001  */
32002 /*@{*/
32003 #define XCVR_RD_DCOC_CAL_BETA(base) (XCVR_DCOC_CAL_BETA_REG(base))
32004 /*@}*/
32005 
32006 /*
32007  * Constants & macros for individual XCVR_DCOC_CAL_BETA bitfields
32008  */
32009 
32010 /*!
32011  * @name Register XCVR_DCOC_CAL_BETA, field DCOC_CAL_BETA_I[15:0] (RO)
32012  *
32013  * DCOC Calibration I-channel BETA. This read-only, signed 16bit value
32014  * represents the I channel estimate of the BETA DC component calculated in DCOC
32015  * calibration. This is provided for debug/characterization purposes.
32016  */
32017 /*@{*/
32018 /*! @brief Read current value of the XCVR_DCOC_CAL_BETA_DCOC_CAL_BETA_I field. */
32019 #define XCVR_RD_DCOC_CAL_BETA_DCOC_CAL_BETA_I(base) ((XCVR_DCOC_CAL_BETA_REG(base) & XCVR_DCOC_CAL_BETA_DCOC_CAL_BETA_I_MASK) >> XCVR_DCOC_CAL_BETA_DCOC_CAL_BETA_I_SHIFT)
32020 #define XCVR_BRD_DCOC_CAL_BETA_DCOC_CAL_BETA_I(base) (BME_UBFX32(&XCVR_DCOC_CAL_BETA_REG(base), XCVR_DCOC_CAL_BETA_DCOC_CAL_BETA_I_SHIFT, XCVR_DCOC_CAL_BETA_DCOC_CAL_BETA_I_WIDTH))
32021 /*@}*/
32022 
32023 /*!
32024  * @name Register XCVR_DCOC_CAL_BETA, field DCOC_CAL_BETA_Q[31:16] (RO)
32025  *
32026  * DCOC Calibration Q-channel BETA. This read-only, signed 16bit value
32027  * represents the Q channel estimate of the BETA DC component calculated in DCOC
32028  * calibration. This is provided for debug/characterization purposes.
32029  */
32030 /*@{*/
32031 /*! @brief Read current value of the XCVR_DCOC_CAL_BETA_DCOC_CAL_BETA_Q field. */
32032 #define XCVR_RD_DCOC_CAL_BETA_DCOC_CAL_BETA_Q(base) ((XCVR_DCOC_CAL_BETA_REG(base) & XCVR_DCOC_CAL_BETA_DCOC_CAL_BETA_Q_MASK) >> XCVR_DCOC_CAL_BETA_DCOC_CAL_BETA_Q_SHIFT)
32033 #define XCVR_BRD_DCOC_CAL_BETA_DCOC_CAL_BETA_Q(base) (BME_UBFX32(&XCVR_DCOC_CAL_BETA_REG(base), XCVR_DCOC_CAL_BETA_DCOC_CAL_BETA_Q_SHIFT, XCVR_DCOC_CAL_BETA_DCOC_CAL_BETA_Q_WIDTH))
32034 /*@}*/
32035 
32036 /*******************************************************************************
32037  * XCVR_DCOC_CAL_GAMMA - DCOC Calibration Gamma
32038  ******************************************************************************/
32039 
32040 /*!
32041  * @brief XCVR_DCOC_CAL_GAMMA - DCOC Calibration Gamma (RO)
32042  *
32043  * Reset value: 0x00000000U
32044  */
32045 /*!
32046  * @name Constants and macros for entire XCVR_DCOC_CAL_GAMMA register
32047  */
32048 /*@{*/
32049 #define XCVR_RD_DCOC_CAL_GAMMA(base) (XCVR_DCOC_CAL_GAMMA_REG(base))
32050 /*@}*/
32051 
32052 /*
32053  * Constants & macros for individual XCVR_DCOC_CAL_GAMMA bitfields
32054  */
32055 
32056 /*!
32057  * @name Register XCVR_DCOC_CAL_GAMMA, field DCOC_CAL_GAMMA_I[15:0] (RO)
32058  *
32059  * DCOC Calibration I-channel GAMMA. This read-only, signed 16bit value
32060  * represents the I channel estimate of the GAMMA DC component calculated in DCOC
32061  * calibration. This is provided for debug/characterization purposes.
32062  */
32063 /*@{*/
32064 /*! @brief Read current value of the XCVR_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I field. */
32065 #define XCVR_RD_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I(base) ((XCVR_DCOC_CAL_GAMMA_REG(base) & XCVR_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_MASK) >> XCVR_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_SHIFT)
32066 #define XCVR_BRD_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAMMA_REG(base), XCVR_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_SHIFT, XCVR_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_I_WIDTH))
32067 /*@}*/
32068 
32069 /*!
32070  * @name Register XCVR_DCOC_CAL_GAMMA, field DCOC_CAL_GAMMA_Q[31:16] (RO)
32071  *
32072  * DCOC Calibration Q-channel GAMMA. This read-only, signed 16bit value
32073  * represents the Q channel estimate of the GAMMA DC component calculated in DCOC
32074  * calibration. This is provided for debug/characterization purposes.
32075  */
32076 /*@{*/
32077 /*! @brief Read current value of the XCVR_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q field. */
32078 #define XCVR_RD_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q(base) ((XCVR_DCOC_CAL_GAMMA_REG(base) & XCVR_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_MASK) >> XCVR_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_SHIFT)
32079 #define XCVR_BRD_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q(base) (BME_UBFX32(&XCVR_DCOC_CAL_GAMMA_REG(base), XCVR_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_SHIFT, XCVR_DCOC_CAL_GAMMA_DCOC_CAL_GAMMA_Q_WIDTH))
32080 /*@}*/
32081 
32082 /*******************************************************************************
32083  * XCVR_DCOC_CAL_IIR - DCOC Calibration IIR
32084  ******************************************************************************/
32085 
32086 /*!
32087  * @brief XCVR_DCOC_CAL_IIR - DCOC Calibration IIR (RW)
32088  *
32089  * Reset value: 0x00000000U
32090  */
32091 /*!
32092  * @name Constants and macros for entire XCVR_DCOC_CAL_IIR register
32093  */
32094 /*@{*/
32095 #define XCVR_RD_DCOC_CAL_IIR(base) (XCVR_DCOC_CAL_IIR_REG(base))
32096 #define XCVR_WR_DCOC_CAL_IIR(base, value) (XCVR_DCOC_CAL_IIR_REG(base) = (value))
32097 #define XCVR_RMW_DCOC_CAL_IIR(base, mask, value) (XCVR_WR_DCOC_CAL_IIR(base, (XCVR_RD_DCOC_CAL_IIR(base) & ~(mask)) | (value)))
32098 #define XCVR_SET_DCOC_CAL_IIR(base, value) (BME_OR32(&XCVR_DCOC_CAL_IIR_REG(base), (uint32_t)(value)))
32099 #define XCVR_CLR_DCOC_CAL_IIR(base, value) (BME_AND32(&XCVR_DCOC_CAL_IIR_REG(base), (uint32_t)(~(value))))
32100 #define XCVR_TOG_DCOC_CAL_IIR(base, value) (BME_XOR32(&XCVR_DCOC_CAL_IIR_REG(base), (uint32_t)(value)))
32101 /*@}*/
32102 
32103 /*
32104  * Constants & macros for individual XCVR_DCOC_CAL_IIR bitfields
32105  */
32106 
32107 /*!
32108  * @name Register XCVR_DCOC_CAL_IIR, field DCOC_CAL_IIR1A_IDX[1:0] (RW)
32109  *
32110  * DCOC Calibration IIR 1A Index. Defines the filter coefficient use for the 1st
32111  * IIR filter in the DCOC calibration DC estimator.
32112  *
32113  * Values:
32114  * - 0b00 - 1/1
32115  * - 0b01 - 1/4
32116  */
32117 /*@{*/
32118 /*! @brief Read current value of the XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX field. */
32119 #define XCVR_RD_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(base) ((XCVR_DCOC_CAL_IIR_REG(base) & XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_MASK) >> XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_SHIFT)
32120 #define XCVR_BRD_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(base) (BME_UBFX32(&XCVR_DCOC_CAL_IIR_REG(base), XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_SHIFT, XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_WIDTH))
32121 
32122 /*! @brief Set the DCOC_CAL_IIR1A_IDX field to a new value. */
32123 #define XCVR_WR_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(base, value) (XCVR_RMW_DCOC_CAL_IIR(base, XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_MASK, XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(value)))
32124 #define XCVR_BWR_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX(base, value) (BME_BFI32(&XCVR_DCOC_CAL_IIR_REG(base), ((uint32_t)(value) << XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_SHIFT), XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_SHIFT, XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR1A_IDX_WIDTH))
32125 /*@}*/
32126 
32127 /*!
32128  * @name Register XCVR_DCOC_CAL_IIR, field DCOC_CAL_IIR2A_IDX[3:2] (RW)
32129  *
32130  * DCOC Calibration IIR 2A Index. Defines the filter coefficient use for the 2nd
32131  * IIR filter in the DCOC calibration DC estimator.
32132  *
32133  * Values:
32134  * - 0b00 - 1/1
32135  * - 0b01 - 1/4
32136  */
32137 /*@{*/
32138 /*! @brief Read current value of the XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX field. */
32139 #define XCVR_RD_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(base) ((XCVR_DCOC_CAL_IIR_REG(base) & XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_MASK) >> XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_SHIFT)
32140 #define XCVR_BRD_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(base) (BME_UBFX32(&XCVR_DCOC_CAL_IIR_REG(base), XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_SHIFT, XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_WIDTH))
32141 
32142 /*! @brief Set the DCOC_CAL_IIR2A_IDX field to a new value. */
32143 #define XCVR_WR_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(base, value) (XCVR_RMW_DCOC_CAL_IIR(base, XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_MASK, XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(value)))
32144 #define XCVR_BWR_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX(base, value) (BME_BFI32(&XCVR_DCOC_CAL_IIR_REG(base), ((uint32_t)(value) << XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_SHIFT), XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_SHIFT, XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR2A_IDX_WIDTH))
32145 /*@}*/
32146 
32147 /*!
32148  * @name Register XCVR_DCOC_CAL_IIR, field DCOC_CAL_IIR3A_IDX[5:4] (RW)
32149  *
32150  * DCOC Calibration IIR 3A Index. Defines the filter coefficient use for the 3rd
32151  * IIR filter in the DCOC calibration DC estimator.
32152  *
32153  * Values:
32154  * - 0b00 - 1/4
32155  * - 0b01 - 1/8
32156  */
32157 /*@{*/
32158 /*! @brief Read current value of the XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX field. */
32159 #define XCVR_RD_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(base) ((XCVR_DCOC_CAL_IIR_REG(base) & XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_MASK) >> XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_SHIFT)
32160 #define XCVR_BRD_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(base) (BME_UBFX32(&XCVR_DCOC_CAL_IIR_REG(base), XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_SHIFT, XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_WIDTH))
32161 
32162 /*! @brief Set the DCOC_CAL_IIR3A_IDX field to a new value. */
32163 #define XCVR_WR_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(base, value) (XCVR_RMW_DCOC_CAL_IIR(base, XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_MASK, XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(value)))
32164 #define XCVR_BWR_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX(base, value) (BME_BFI32(&XCVR_DCOC_CAL_IIR_REG(base), ((uint32_t)(value) << XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_SHIFT), XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_SHIFT, XCVR_DCOC_CAL_IIR_DCOC_CAL_IIR3A_IDX_WIDTH))
32165 /*@}*/
32166 
32167 /*******************************************************************************
32168  * XCVR_DCOC_CAL - DCOC Calibration Result
32169  ******************************************************************************/
32170 
32171 /*!
32172  * @brief XCVR_DCOC_CAL - DCOC Calibration Result (RO)
32173  *
32174  * Reset value: 0x00000000U
32175  *
32176  * Result of one of the calibration iterations.
32177  */
32178 /*!
32179  * @name Constants and macros for entire XCVR_DCOC_CAL register
32180  */
32181 /*@{*/
32182 #define XCVR_RD_DCOC_CAL(base, index) (XCVR_DCOC_CAL_REG(base, index))
32183 /*@}*/
32184 
32185 /*
32186  * Constants & macros for individual XCVR_DCOC_CAL bitfields
32187  */
32188 
32189 /*!
32190  * @name Register XCVR_DCOC_CAL, field DCOC_CAL_RES_I[11:0] (RO)
32191  *
32192  * I channel DCOC calibration result. This 12bit signed value represents the
32193  * DCOC's I channel DC estimate for the nth calibration gain setting.This is
32194  * provided for debug/chacterization purposes.
32195  */
32196 /*@{*/
32197 /*! @brief Read current value of the XCVR_DCOC_CAL_DCOC_CAL_RES_I field. */
32198 #define XCVR_RD_DCOC_CAL_DCOC_CAL_RES_I(base, index) ((XCVR_DCOC_CAL_REG(base, index) & XCVR_DCOC_CAL_DCOC_CAL_RES_I_MASK) >> XCVR_DCOC_CAL_DCOC_CAL_RES_I_SHIFT)
32199 #define XCVR_BRD_DCOC_CAL_DCOC_CAL_RES_I(base, index) (BME_UBFX32(&XCVR_DCOC_CAL_REG(base, index), XCVR_DCOC_CAL_DCOC_CAL_RES_I_SHIFT, XCVR_DCOC_CAL_DCOC_CAL_RES_I_WIDTH))
32200 /*@}*/
32201 
32202 /*!
32203  * @name Register XCVR_DCOC_CAL, field DCOC_CAL_RES_Q[27:16] (RO)
32204  *
32205  * Q channel DCOC calibration result. This 12bit signed value represents the
32206  * DCOC's Q channel DC estimate for the nth calibration gain setting.This is
32207  * provided for debug/chacterization purposes.
32208  */
32209 /*@{*/
32210 /*! @brief Read current value of the XCVR_DCOC_CAL_DCOC_CAL_RES_Q field. */
32211 #define XCVR_RD_DCOC_CAL_DCOC_CAL_RES_Q(base, index) ((XCVR_DCOC_CAL_REG(base, index) & XCVR_DCOC_CAL_DCOC_CAL_RES_Q_MASK) >> XCVR_DCOC_CAL_DCOC_CAL_RES_Q_SHIFT)
32212 #define XCVR_BRD_DCOC_CAL_DCOC_CAL_RES_Q(base, index) (BME_UBFX32(&XCVR_DCOC_CAL_REG(base, index), XCVR_DCOC_CAL_DCOC_CAL_RES_Q_SHIFT, XCVR_DCOC_CAL_DCOC_CAL_RES_Q_WIDTH))
32213 /*@}*/
32214 
32215 /*******************************************************************************
32216  * XCVR_RX_CHF_COEF - Receive Channel Filter Coefficient
32217  ******************************************************************************/
32218 
32219 /*!
32220  * @brief XCVR_RX_CHF_COEF - Receive Channel Filter Coefficient (RW)
32221  *
32222  * Reset value: 0x00000000U
32223  *
32224  * Receive channel filter coefficient (8-bit signed fractional)
32225  */
32226 /*!
32227  * @name Constants and macros for entire XCVR_RX_CHF_COEF register
32228  */
32229 /*@{*/
32230 #define XCVR_RD_RX_CHF_COEF(base, index) (XCVR_RX_CHF_COEF_REG(base, index))
32231 #define XCVR_WR_RX_CHF_COEF(base, index, value) (XCVR_RX_CHF_COEF_REG(base, index) = (value))
32232 #define XCVR_RMW_RX_CHF_COEF(base, index, mask, value) (XCVR_WR_RX_CHF_COEF(base, index, (XCVR_RD_RX_CHF_COEF(base, index) & ~(mask)) | (value)))
32233 #define XCVR_SET_RX_CHF_COEF(base, index, value) (BME_OR32(&XCVR_RX_CHF_COEF_REG(base, index), (uint32_t)(value)))
32234 #define XCVR_CLR_RX_CHF_COEF(base, index, value) (BME_AND32(&XCVR_RX_CHF_COEF_REG(base, index), (uint32_t)(~(value))))
32235 #define XCVR_TOG_RX_CHF_COEF(base, index, value) (BME_XOR32(&XCVR_RX_CHF_COEF_REG(base, index), (uint32_t)(value)))
32236 /*@}*/
32237 
32238 /*
32239  * Constants & macros for individual XCVR_RX_CHF_COEF bitfields
32240  */
32241 
32242 /*!
32243  * @name Register XCVR_RX_CHF_COEF, field RX_CH_FILT_HX[7:0] (RW)
32244  *
32245  * Receive channel filter coefficient (8-bit signed fractional)
32246  */
32247 /*@{*/
32248 /*! @brief Read current value of the XCVR_RX_CHF_COEF_RX_CH_FILT_HX field. */
32249 #define XCVR_RD_RX_CHF_COEF_RX_CH_FILT_HX(base, index) ((XCVR_RX_CHF_COEF_REG(base, index) & XCVR_RX_CHF_COEF_RX_CH_FILT_HX_MASK) >> XCVR_RX_CHF_COEF_RX_CH_FILT_HX_SHIFT)
32250 #define XCVR_BRD_RX_CHF_COEF_RX_CH_FILT_HX(base, index) (BME_UBFX32(&XCVR_RX_CHF_COEF_REG(base, index), XCVR_RX_CHF_COEF_RX_CH_FILT_HX_SHIFT, XCVR_RX_CHF_COEF_RX_CH_FILT_HX_WIDTH))
32251 
32252 /*! @brief Set the RX_CH_FILT_HX field to a new value. */
32253 #define XCVR_WR_RX_CHF_COEF_RX_CH_FILT_HX(base, index, value) (XCVR_RMW_RX_CHF_COEF(base, index, XCVR_RX_CHF_COEF_RX_CH_FILT_HX_MASK, XCVR_RX_CHF_COEF_RX_CH_FILT_HX(value)))
32254 #define XCVR_BWR_RX_CHF_COEF_RX_CH_FILT_HX(base, index, value) (BME_BFI32(&XCVR_RX_CHF_COEF_REG(base, index), ((uint32_t)(value) << XCVR_RX_CHF_COEF_RX_CH_FILT_HX_SHIFT), XCVR_RX_CHF_COEF_RX_CH_FILT_HX_SHIFT, XCVR_RX_CHF_COEF_RX_CH_FILT_HX_WIDTH))
32255 /*@}*/
32256 
32257 /*******************************************************************************
32258  * XCVR_TX_DIG_CTRL - TX Digital Control
32259  ******************************************************************************/
32260 
32261 /*!
32262  * @brief XCVR_TX_DIG_CTRL - TX Digital Control (RW)
32263  *
32264  * Reset value: 0x00000140U
32265  */
32266 /*!
32267  * @name Constants and macros for entire XCVR_TX_DIG_CTRL register
32268  */
32269 /*@{*/
32270 #define XCVR_RD_TX_DIG_CTRL(base) (XCVR_TX_DIG_CTRL_REG(base))
32271 #define XCVR_WR_TX_DIG_CTRL(base, value) (XCVR_TX_DIG_CTRL_REG(base) = (value))
32272 #define XCVR_RMW_TX_DIG_CTRL(base, mask, value) (XCVR_WR_TX_DIG_CTRL(base, (XCVR_RD_TX_DIG_CTRL(base) & ~(mask)) | (value)))
32273 #define XCVR_SET_TX_DIG_CTRL(base, value) (BME_OR32(&XCVR_TX_DIG_CTRL_REG(base), (uint32_t)(value)))
32274 #define XCVR_CLR_TX_DIG_CTRL(base, value) (BME_AND32(&XCVR_TX_DIG_CTRL_REG(base), (uint32_t)(~(value))))
32275 #define XCVR_TOG_TX_DIG_CTRL(base, value) (BME_XOR32(&XCVR_TX_DIG_CTRL_REG(base), (uint32_t)(value)))
32276 /*@}*/
32277 
32278 /*
32279  * Constants & macros for individual XCVR_TX_DIG_CTRL bitfields
32280  */
32281 
32282 /*!
32283  * @name Register XCVR_TX_DIG_CTRL, field DFT_MODE[2:0] (RW)
32284  *
32285  * This register selects the Radio DFT mode as described below. In addition to
32286  * setting the Radio DFT mode, the DFT LFSR needs to be configured, and the Radio
32287  * Protocol needs to be chosen. Note that the LFSR Symbols mode is not supported
32288  * for GFSK Protocols, and the Tone modes bypass both the GFSK and the FSK
32289  * modulators.
32290  *
32291  * Values:
32292  * - 0b000 - Normal Radio Operation. DFT not engaged.
32293  * - 0b001 - Pattern Register Mode. TX DFT Modulation Pattern Register is
32294  *     shifted out as the transmission data stream. Note that the DFT_EN bit must be
32295  *     set.
32296  * - 0b010 - LFSR Data Mode. TX LFSR is used as the transmission data stream.
32297  *     Note that the LFSR_EN bit must be set.
32298  * - 0b011 - LFSR Symbol Mode. TX LFSR is used to create 802.15.4 symbols which
32299  *     are then converted to Chips and transmitted. Note that the LFSR_EN bit
32300  *     must be set.
32301  * - 0b100 - Not implemented on Apache 1.0, future use will allow a package pin
32302  *     to be used as the source of the TX data stream. Note that the DFT_EN bit
32303  *     must be set.
32304  * - 0b101 - Constant Frequency Mode. No data modulation is done, Radio
32305  *     transmits at the channel frequency selected.
32306  * - 0b110 - LFSR Tone Mode. TX LFSR is used to select the DFT Tone register to
32307  *     transmit, LFSR_EN bit must be set.
32308  * - 0b111 - Manual Tone Mode. TONE_SEL is used to select the DFT Tone register
32309  *     to transmit.
32310  */
32311 /*@{*/
32312 /*! @brief Read current value of the XCVR_TX_DIG_CTRL_DFT_MODE field. */
32313 #define XCVR_RD_TX_DIG_CTRL_DFT_MODE(base) ((XCVR_TX_DIG_CTRL_REG(base) & XCVR_TX_DIG_CTRL_DFT_MODE_MASK) >> XCVR_TX_DIG_CTRL_DFT_MODE_SHIFT)
32314 #define XCVR_BRD_TX_DIG_CTRL_DFT_MODE(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG_CTRL_DFT_MODE_SHIFT, XCVR_TX_DIG_CTRL_DFT_MODE_WIDTH))
32315 
32316 /*! @brief Set the DFT_MODE field to a new value. */
32317 #define XCVR_WR_TX_DIG_CTRL_DFT_MODE(base, value) (XCVR_RMW_TX_DIG_CTRL(base, XCVR_TX_DIG_CTRL_DFT_MODE_MASK, XCVR_TX_DIG_CTRL_DFT_MODE(value)))
32318 #define XCVR_BWR_TX_DIG_CTRL_DFT_MODE(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uint32_t)(value) << XCVR_TX_DIG_CTRL_DFT_MODE_SHIFT), XCVR_TX_DIG_CTRL_DFT_MODE_SHIFT, XCVR_TX_DIG_CTRL_DFT_MODE_WIDTH))
32319 /*@}*/
32320 
32321 /*!
32322  * @name Register XCVR_TX_DIG_CTRL, field DFT_EN[3] (RW)
32323  *
32324  * If the Radio is in DFT Pattern Register mode, then this bit is used to turn
32325  * on and off the modulation.
32326  */
32327 /*@{*/
32328 /*! @brief Read current value of the XCVR_TX_DIG_CTRL_DFT_EN field. */
32329 #define XCVR_RD_TX_DIG_CTRL_DFT_EN(base) ((XCVR_TX_DIG_CTRL_REG(base) & XCVR_TX_DIG_CTRL_DFT_EN_MASK) >> XCVR_TX_DIG_CTRL_DFT_EN_SHIFT)
32330 #define XCVR_BRD_TX_DIG_CTRL_DFT_EN(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG_CTRL_DFT_EN_SHIFT, XCVR_TX_DIG_CTRL_DFT_EN_WIDTH))
32331 
32332 /*! @brief Set the DFT_EN field to a new value. */
32333 #define XCVR_WR_TX_DIG_CTRL_DFT_EN(base, value) (XCVR_RMW_TX_DIG_CTRL(base, XCVR_TX_DIG_CTRL_DFT_EN_MASK, XCVR_TX_DIG_CTRL_DFT_EN(value)))
32334 #define XCVR_BWR_TX_DIG_CTRL_DFT_EN(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uint32_t)(value) << XCVR_TX_DIG_CTRL_DFT_EN_SHIFT), XCVR_TX_DIG_CTRL_DFT_EN_SHIFT, XCVR_TX_DIG_CTRL_DFT_EN_WIDTH))
32335 /*@}*/
32336 
32337 /*!
32338  * @name Register XCVR_TX_DIG_CTRL, field DFT_LFSR_LEN[6:4] (RW)
32339  *
32340  * This register selects the length of the DFT LFSR and the associated LFSR Tap
32341  * Mask. The Mask is in the form of [MSB...LSB]
32342  *
32343  * Values:
32344  * - 0b000 - LFSR 9, tap mask 100010000
32345  * - 0b001 - LFSR 10, tap mask 1001000000
32346  * - 0b010 - LFSR 11, tap mask 11101000000
32347  * - 0b011 - LFSR 13, tap mask 1101100000000
32348  * - 0b100 - LFSR 15, tap mask 111010000000000
32349  * - 0b101 - LFSR 17, tap mask 11110000000000000
32350  * - 0b110 - Reserved
32351  * - 0b111 - Reserved
32352  */
32353 /*@{*/
32354 /*! @brief Read current value of the XCVR_TX_DIG_CTRL_DFT_LFSR_LEN field. */
32355 #define XCVR_RD_TX_DIG_CTRL_DFT_LFSR_LEN(base) ((XCVR_TX_DIG_CTRL_REG(base) & XCVR_TX_DIG_CTRL_DFT_LFSR_LEN_MASK) >> XCVR_TX_DIG_CTRL_DFT_LFSR_LEN_SHIFT)
32356 #define XCVR_BRD_TX_DIG_CTRL_DFT_LFSR_LEN(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG_CTRL_DFT_LFSR_LEN_SHIFT, XCVR_TX_DIG_CTRL_DFT_LFSR_LEN_WIDTH))
32357 
32358 /*! @brief Set the DFT_LFSR_LEN field to a new value. */
32359 #define XCVR_WR_TX_DIG_CTRL_DFT_LFSR_LEN(base, value) (XCVR_RMW_TX_DIG_CTRL(base, XCVR_TX_DIG_CTRL_DFT_LFSR_LEN_MASK, XCVR_TX_DIG_CTRL_DFT_LFSR_LEN(value)))
32360 #define XCVR_BWR_TX_DIG_CTRL_DFT_LFSR_LEN(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uint32_t)(value) << XCVR_TX_DIG_CTRL_DFT_LFSR_LEN_SHIFT), XCVR_TX_DIG_CTRL_DFT_LFSR_LEN_SHIFT, XCVR_TX_DIG_CTRL_DFT_LFSR_LEN_WIDTH))
32361 /*@}*/
32362 
32363 /*!
32364  * @name Register XCVR_TX_DIG_CTRL, field LFSR_EN[7] (RW)
32365  *
32366  * This bit enables the DFT LFSR for use as a source for Data Padding and TX
32367  * Data in LFSR Data mode, for use as TX Symbols in LFSR Symbol mode, and for use as
32368  * the Tone Selector in LFSR Tone mode. Effectively this is the on-off switch
32369  * for modulation in these modes. Note that the LFSR is clocked at the DFT Clock
32370  * frequency.
32371  */
32372 /*@{*/
32373 /*! @brief Read current value of the XCVR_TX_DIG_CTRL_LFSR_EN field. */
32374 #define XCVR_RD_TX_DIG_CTRL_LFSR_EN(base) ((XCVR_TX_DIG_CTRL_REG(base) & XCVR_TX_DIG_CTRL_LFSR_EN_MASK) >> XCVR_TX_DIG_CTRL_LFSR_EN_SHIFT)
32375 #define XCVR_BRD_TX_DIG_CTRL_LFSR_EN(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG_CTRL_LFSR_EN_SHIFT, XCVR_TX_DIG_CTRL_LFSR_EN_WIDTH))
32376 
32377 /*! @brief Set the LFSR_EN field to a new value. */
32378 #define XCVR_WR_TX_DIG_CTRL_LFSR_EN(base, value) (XCVR_RMW_TX_DIG_CTRL(base, XCVR_TX_DIG_CTRL_LFSR_EN_MASK, XCVR_TX_DIG_CTRL_LFSR_EN(value)))
32379 #define XCVR_BWR_TX_DIG_CTRL_LFSR_EN(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uint32_t)(value) << XCVR_TX_DIG_CTRL_LFSR_EN_SHIFT), XCVR_TX_DIG_CTRL_LFSR_EN_SHIFT, XCVR_TX_DIG_CTRL_LFSR_EN_WIDTH))
32380 /*@}*/
32381 
32382 /*!
32383  * @name Register XCVR_TX_DIG_CTRL, field DFT_CLK_SEL[10:8] (RW)
32384  *
32385  * This register selects the frequency of the DFT clock that is used to shift
32386  * out the DFT Modulation Pattern and also used to clock the LFSR in DFT LFSR modes.
32387  *
32388  * Values:
32389  * - 0b000 - 62.5 kHz
32390  * - 0b001 - 125 kHz
32391  * - 0b010 - 250 kHz
32392  * - 0b011 - 500 kHz
32393  * - 0b100 - 1 MHz
32394  * - 0b101 - 2 MHz
32395  * - 0b110 - 4 MHz
32396  * - 0b111 - Clock is off
32397  */
32398 /*@{*/
32399 /*! @brief Read current value of the XCVR_TX_DIG_CTRL_DFT_CLK_SEL field. */
32400 #define XCVR_RD_TX_DIG_CTRL_DFT_CLK_SEL(base) ((XCVR_TX_DIG_CTRL_REG(base) & XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK) >> XCVR_TX_DIG_CTRL_DFT_CLK_SEL_SHIFT)
32401 #define XCVR_BRD_TX_DIG_CTRL_DFT_CLK_SEL(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG_CTRL_DFT_CLK_SEL_SHIFT, XCVR_TX_DIG_CTRL_DFT_CLK_SEL_WIDTH))
32402 
32403 /*! @brief Set the DFT_CLK_SEL field to a new value. */
32404 #define XCVR_WR_TX_DIG_CTRL_DFT_CLK_SEL(base, value) (XCVR_RMW_TX_DIG_CTRL(base, XCVR_TX_DIG_CTRL_DFT_CLK_SEL_MASK, XCVR_TX_DIG_CTRL_DFT_CLK_SEL(value)))
32405 #define XCVR_BWR_TX_DIG_CTRL_DFT_CLK_SEL(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uint32_t)(value) << XCVR_TX_DIG_CTRL_DFT_CLK_SEL_SHIFT), XCVR_TX_DIG_CTRL_DFT_CLK_SEL_SHIFT, XCVR_TX_DIG_CTRL_DFT_CLK_SEL_WIDTH))
32406 /*@}*/
32407 
32408 /*!
32409  * @name Register XCVR_TX_DIG_CTRL, field TONE_SEL[13:12] (RW)
32410  *
32411  * This register selects the DFT Tone register to use as the Modulation Source
32412  * in DFT Manual Tone mode. The selected Tone will be added as a constant
32413  * frequency offset to the current Radio frequency. Software can change the tone
32414  * selection to modulate the Radio frequency at a software derived frequency. Note that
32415  * the DFT LFSR Tone mode can be used to randomly modulate with tones at the DFT
32416  * Clock frequency.
32417  *
32418  * Values:
32419  * - 0b00 - DFT Tone 0
32420  * - 0b01 - DFT Tone 1
32421  * - 0b10 - DFT Tone 2
32422  * - 0b11 - DFT Tone 3
32423  */
32424 /*@{*/
32425 /*! @brief Read current value of the XCVR_TX_DIG_CTRL_TONE_SEL field. */
32426 #define XCVR_RD_TX_DIG_CTRL_TONE_SEL(base) ((XCVR_TX_DIG_CTRL_REG(base) & XCVR_TX_DIG_CTRL_TONE_SEL_MASK) >> XCVR_TX_DIG_CTRL_TONE_SEL_SHIFT)
32427 #define XCVR_BRD_TX_DIG_CTRL_TONE_SEL(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG_CTRL_TONE_SEL_SHIFT, XCVR_TX_DIG_CTRL_TONE_SEL_WIDTH))
32428 
32429 /*! @brief Set the TONE_SEL field to a new value. */
32430 #define XCVR_WR_TX_DIG_CTRL_TONE_SEL(base, value) (XCVR_RMW_TX_DIG_CTRL(base, XCVR_TX_DIG_CTRL_TONE_SEL_MASK, XCVR_TX_DIG_CTRL_TONE_SEL(value)))
32431 #define XCVR_BWR_TX_DIG_CTRL_TONE_SEL(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uint32_t)(value) << XCVR_TX_DIG_CTRL_TONE_SEL_SHIFT), XCVR_TX_DIG_CTRL_TONE_SEL_SHIFT, XCVR_TX_DIG_CTRL_TONE_SEL_WIDTH))
32432 /*@}*/
32433 
32434 /*!
32435  * @name Register XCVR_TX_DIG_CTRL, field POL[16] (RW)
32436  *
32437  * This bit selects between Even or Odd reference clock cycles to sample the TX
32438  * Modulators output values. The TX Modulator to sample is selected by the Radio
32439  * Protocol and the Radio DFT Mode, and can be either the GFSK modulator, the FSK
32440  * modulator, or the DFT Tone modulator. The resulting Oversampled Modulation is
32441  * the Baseband Frequency Word presented to the PLL
32442  *
32443  * Values:
32444  * - 0b0 - Selects Even clock cycle
32445  * - 0b1 - Selects Odd clock cycle, a one cycle delay
32446  */
32447 /*@{*/
32448 /*! @brief Read current value of the XCVR_TX_DIG_CTRL_POL field. */
32449 #define XCVR_RD_TX_DIG_CTRL_POL(base) ((XCVR_TX_DIG_CTRL_REG(base) & XCVR_TX_DIG_CTRL_POL_MASK) >> XCVR_TX_DIG_CTRL_POL_SHIFT)
32450 #define XCVR_BRD_TX_DIG_CTRL_POL(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG_CTRL_POL_SHIFT, XCVR_TX_DIG_CTRL_POL_WIDTH))
32451 
32452 /*! @brief Set the POL field to a new value. */
32453 #define XCVR_WR_TX_DIG_CTRL_POL(base, value) (XCVR_RMW_TX_DIG_CTRL(base, XCVR_TX_DIG_CTRL_POL_MASK, XCVR_TX_DIG_CTRL_POL(value)))
32454 #define XCVR_BWR_TX_DIG_CTRL_POL(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uint32_t)(value) << XCVR_TX_DIG_CTRL_POL_SHIFT), XCVR_TX_DIG_CTRL_POL_SHIFT, XCVR_TX_DIG_CTRL_POL_WIDTH))
32455 /*@}*/
32456 
32457 /*!
32458  * @name Register XCVR_TX_DIG_CTRL, field DP_SEL[20] (RW)
32459  *
32460  * In normal user GSFK modes the BLE link layer overrides this bit to match the
32461  * first bit of the packet preamble. In Radio Protocol 7, 128 Channel GFSK mode,
32462  * this register bit is active and selects the 8 bits of data padding. For DFT
32463  * GFSK modes, this register bit is active and the unselected data padding pattern
32464  * is added as an additional 8 bits of padding after the selected pattern is
32465  * shifted out. For 802.15.4 Radio Protocols, this register bit selects the data
32466  * padding pattern to be used as Symbols and converted to Chips for padding. In all
32467  * cases the LSB is the first bit shifted out as data padding.
32468  *
32469  * Values:
32470  * - 0b0 - Selects DATA_PADDING_PATTERN_0 as the source for data padding
32471  * - 0b1 - Selects DATA_PADDING_PATTERN_1 as the source for data padding
32472  */
32473 /*@{*/
32474 /*! @brief Read current value of the XCVR_TX_DIG_CTRL_DP_SEL field. */
32475 #define XCVR_RD_TX_DIG_CTRL_DP_SEL(base) ((XCVR_TX_DIG_CTRL_REG(base) & XCVR_TX_DIG_CTRL_DP_SEL_MASK) >> XCVR_TX_DIG_CTRL_DP_SEL_SHIFT)
32476 #define XCVR_BRD_TX_DIG_CTRL_DP_SEL(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG_CTRL_DP_SEL_SHIFT, XCVR_TX_DIG_CTRL_DP_SEL_WIDTH))
32477 
32478 /*! @brief Set the DP_SEL field to a new value. */
32479 #define XCVR_WR_TX_DIG_CTRL_DP_SEL(base, value) (XCVR_RMW_TX_DIG_CTRL(base, XCVR_TX_DIG_CTRL_DP_SEL_MASK, XCVR_TX_DIG_CTRL_DP_SEL(value)))
32480 #define XCVR_BWR_TX_DIG_CTRL_DP_SEL(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uint32_t)(value) << XCVR_TX_DIG_CTRL_DP_SEL_SHIFT), XCVR_TX_DIG_CTRL_DP_SEL_SHIFT, XCVR_TX_DIG_CTRL_DP_SEL_WIDTH))
32481 /*@}*/
32482 
32483 /*!
32484  * @name Register XCVR_TX_DIG_CTRL, field FREQ_WORD_ADJ[31:22] (RW)
32485  *
32486  * This register is a signed 9 bit number that is added to the GFSK modulator
32487  * output. This allows the GFSK modulation to be adjusted, or skewed, by a range of
32488  * -512 to +511.
32489  */
32490 /*@{*/
32491 /*! @brief Read current value of the XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ field. */
32492 #define XCVR_RD_TX_DIG_CTRL_FREQ_WORD_ADJ(base) ((XCVR_TX_DIG_CTRL_REG(base) & XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_MASK) >> XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_SHIFT)
32493 #define XCVR_BRD_TX_DIG_CTRL_FREQ_WORD_ADJ(base) (BME_UBFX32(&XCVR_TX_DIG_CTRL_REG(base), XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_SHIFT, XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_WIDTH))
32494 
32495 /*! @brief Set the FREQ_WORD_ADJ field to a new value. */
32496 #define XCVR_WR_TX_DIG_CTRL_FREQ_WORD_ADJ(base, value) (XCVR_RMW_TX_DIG_CTRL(base, XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_MASK, XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ(value)))
32497 #define XCVR_BWR_TX_DIG_CTRL_FREQ_WORD_ADJ(base, value) (BME_BFI32(&XCVR_TX_DIG_CTRL_REG(base), ((uint32_t)(value) << XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_SHIFT), XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_SHIFT, XCVR_TX_DIG_CTRL_FREQ_WORD_ADJ_WIDTH))
32498 /*@}*/
32499 
32500 /*******************************************************************************
32501  * XCVR_TX_DATA_PAD_PAT - TX Data Padding Pattern
32502  ******************************************************************************/
32503 
32504 /*!
32505  * @brief XCVR_TX_DATA_PAD_PAT - TX Data Padding Pattern (RW)
32506  *
32507  * Reset value: 0x7FFF55AAU
32508  */
32509 /*!
32510  * @name Constants and macros for entire XCVR_TX_DATA_PAD_PAT register
32511  */
32512 /*@{*/
32513 #define XCVR_RD_TX_DATA_PAD_PAT(base) (XCVR_TX_DATA_PAD_PAT_REG(base))
32514 #define XCVR_WR_TX_DATA_PAD_PAT(base, value) (XCVR_TX_DATA_PAD_PAT_REG(base) = (value))
32515 #define XCVR_RMW_TX_DATA_PAD_PAT(base, mask, value) (XCVR_WR_TX_DATA_PAD_PAT(base, (XCVR_RD_TX_DATA_PAD_PAT(base) & ~(mask)) | (value)))
32516 #define XCVR_SET_TX_DATA_PAD_PAT(base, value) (BME_OR32(&XCVR_TX_DATA_PAD_PAT_REG(base), (uint32_t)(value)))
32517 #define XCVR_CLR_TX_DATA_PAD_PAT(base, value) (BME_AND32(&XCVR_TX_DATA_PAD_PAT_REG(base), (uint32_t)(~(value))))
32518 #define XCVR_TOG_TX_DATA_PAD_PAT(base, value) (BME_XOR32(&XCVR_TX_DATA_PAD_PAT_REG(base), (uint32_t)(value)))
32519 /*@}*/
32520 
32521 /*
32522  * Constants & macros for individual XCVR_TX_DATA_PAD_PAT bitfields
32523  */
32524 
32525 /*!
32526  * @name Register XCVR_TX_DATA_PAD_PAT, field DATA_PADDING_PAT_0[7:0] (RW)
32527  *
32528  * These bits are used for Data Padding when Pattern 0 is selected, the LSB is
32529  * the first bit shifted out as padding.
32530  */
32531 /*@{*/
32532 /*! @brief Read current value of the XCVR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_0 field. */
32533 #define XCVR_RD_TX_DATA_PAD_PAT_DATA_PADDING_PAT_0(base) ((XCVR_TX_DATA_PAD_PAT_REG(base) & XCVR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_0_MASK) >> XCVR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_0_SHIFT)
32534 #define XCVR_BRD_TX_DATA_PAD_PAT_DATA_PADDING_PAT_0(base) (BME_UBFX32(&XCVR_TX_DATA_PAD_PAT_REG(base), XCVR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_0_SHIFT, XCVR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_0_WIDTH))
32535 
32536 /*! @brief Set the DATA_PADDING_PAT_0 field to a new value. */
32537 #define XCVR_WR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_0(base, value) (XCVR_RMW_TX_DATA_PAD_PAT(base, XCVR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_0_MASK, XCVR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_0(value)))
32538 #define XCVR_BWR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_0(base, value) (BME_BFI32(&XCVR_TX_DATA_PAD_PAT_REG(base), ((uint32_t)(value) << XCVR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_0_SHIFT), XCVR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_0_SHIFT, XCVR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_0_WIDTH))
32539 /*@}*/
32540 
32541 /*!
32542  * @name Register XCVR_TX_DATA_PAD_PAT, field DATA_PADDING_PAT_1[15:8] (RW)
32543  *
32544  * These bits are used for Data Padding when Pattern 1 is selected, the LSB is
32545  * the first bit shifted out as padding.
32546  */
32547 /*@{*/
32548 /*! @brief Read current value of the XCVR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_1 field. */
32549 #define XCVR_RD_TX_DATA_PAD_PAT_DATA_PADDING_PAT_1(base) ((XCVR_TX_DATA_PAD_PAT_REG(base) & XCVR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_1_MASK) >> XCVR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_1_SHIFT)
32550 #define XCVR_BRD_TX_DATA_PAD_PAT_DATA_PADDING_PAT_1(base) (BME_UBFX32(&XCVR_TX_DATA_PAD_PAT_REG(base), XCVR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_1_SHIFT, XCVR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_1_WIDTH))
32551 
32552 /*! @brief Set the DATA_PADDING_PAT_1 field to a new value. */
32553 #define XCVR_WR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_1(base, value) (XCVR_RMW_TX_DATA_PAD_PAT(base, XCVR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_1_MASK, XCVR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_1(value)))
32554 #define XCVR_BWR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_1(base, value) (BME_BFI32(&XCVR_TX_DATA_PAD_PAT_REG(base), ((uint32_t)(value) << XCVR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_1_SHIFT), XCVR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_1_SHIFT, XCVR_TX_DATA_PAD_PAT_DATA_PADDING_PAT_1_WIDTH))
32555 /*@}*/
32556 
32557 /*!
32558  * @name Register XCVR_TX_DATA_PAD_PAT, field DFT_LFSR_OUT[30:16] (RO)
32559  *
32560  * This register can be read to observe the current value of the DFT LFSR, only
32561  * bits [14:0] are available.
32562  */
32563 /*@{*/
32564 /*! @brief Read current value of the XCVR_TX_DATA_PAD_PAT_DFT_LFSR_OUT field. */
32565 #define XCVR_RD_TX_DATA_PAD_PAT_DFT_LFSR_OUT(base) ((XCVR_TX_DATA_PAD_PAT_REG(base) & XCVR_TX_DATA_PAD_PAT_DFT_LFSR_OUT_MASK) >> XCVR_TX_DATA_PAD_PAT_DFT_LFSR_OUT_SHIFT)
32566 #define XCVR_BRD_TX_DATA_PAD_PAT_DFT_LFSR_OUT(base) (BME_UBFX32(&XCVR_TX_DATA_PAD_PAT_REG(base), XCVR_TX_DATA_PAD_PAT_DFT_LFSR_OUT_SHIFT, XCVR_TX_DATA_PAD_PAT_DFT_LFSR_OUT_WIDTH))
32567 /*@}*/
32568 
32569 /*!
32570  * @name Register XCVR_TX_DATA_PAD_PAT, field LRM[31] (RW)
32571  *
32572  * When this bit is set the DFT LFSR will not be reset when LFSR_EN is cleared
32573  * and will instead continue to repeat its sequence as defined by the DFT_LFSR_LEN
32574  * bits when LFSR_EN is next set. When this bit is cleared the DFT LFSR will
32575  * reset every time LFSR_EN is cleared.
32576  */
32577 /*@{*/
32578 /*! @brief Read current value of the XCVR_TX_DATA_PAD_PAT_LRM field. */
32579 #define XCVR_RD_TX_DATA_PAD_PAT_LRM(base) ((XCVR_TX_DATA_PAD_PAT_REG(base) & XCVR_TX_DATA_PAD_PAT_LRM_MASK) >> XCVR_TX_DATA_PAD_PAT_LRM_SHIFT)
32580 #define XCVR_BRD_TX_DATA_PAD_PAT_LRM(base) (BME_UBFX32(&XCVR_TX_DATA_PAD_PAT_REG(base), XCVR_TX_DATA_PAD_PAT_LRM_SHIFT, XCVR_TX_DATA_PAD_PAT_LRM_WIDTH))
32581 
32582 /*! @brief Set the LRM field to a new value. */
32583 #define XCVR_WR_TX_DATA_PAD_PAT_LRM(base, value) (XCVR_RMW_TX_DATA_PAD_PAT(base, XCVR_TX_DATA_PAD_PAT_LRM_MASK, XCVR_TX_DATA_PAD_PAT_LRM(value)))
32584 #define XCVR_BWR_TX_DATA_PAD_PAT_LRM(base, value) (BME_BFI32(&XCVR_TX_DATA_PAD_PAT_REG(base), ((uint32_t)(value) << XCVR_TX_DATA_PAD_PAT_LRM_SHIFT), XCVR_TX_DATA_PAD_PAT_LRM_SHIFT, XCVR_TX_DATA_PAD_PAT_LRM_WIDTH))
32585 /*@}*/
32586 
32587 /*******************************************************************************
32588  * XCVR_TX_GFSK_MOD_CTRL - TX GFSK Modulation Control
32589  ******************************************************************************/
32590 
32591 /*!
32592  * @brief XCVR_TX_GFSK_MOD_CTRL - TX GFSK Modulation Control (RW)
32593  *
32594  * Reset value: 0x03014000U
32595  */
32596 /*!
32597  * @name Constants and macros for entire XCVR_TX_GFSK_MOD_CTRL register
32598  */
32599 /*@{*/
32600 #define XCVR_RD_TX_GFSK_MOD_CTRL(base) (XCVR_TX_GFSK_MOD_CTRL_REG(base))
32601 #define XCVR_WR_TX_GFSK_MOD_CTRL(base, value) (XCVR_TX_GFSK_MOD_CTRL_REG(base) = (value))
32602 #define XCVR_RMW_TX_GFSK_MOD_CTRL(base, mask, value) (XCVR_WR_TX_GFSK_MOD_CTRL(base, (XCVR_RD_TX_GFSK_MOD_CTRL(base) & ~(mask)) | (value)))
32603 #define XCVR_SET_TX_GFSK_MOD_CTRL(base, value) (BME_OR32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), (uint32_t)(value)))
32604 #define XCVR_CLR_TX_GFSK_MOD_CTRL(base, value) (BME_AND32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), (uint32_t)(~(value))))
32605 #define XCVR_TOG_TX_GFSK_MOD_CTRL(base, value) (BME_XOR32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), (uint32_t)(value)))
32606 /*@}*/
32607 
32608 /*
32609  * Constants & macros for individual XCVR_TX_GFSK_MOD_CTRL bitfields
32610  */
32611 
32612 /*!
32613  * @name Register XCVR_TX_GFSK_MOD_CTRL, field GFSK_MULTIPLY_TABLE_MANUAL[15:0] (RW)
32614  *
32615  * The GFSK Modulator Multiplier uses a lookup table to select the multiplicand
32616  * representing the (Frequency Deviation divided by the Low Port Sigma Delta LSB
32617  * resolution in Hz) for the Modulation requested based on the Modulation Index,
32618  * the Symbol Rate, and the Reference Clock Frequency. The lookup table value is
32619  * overridden by this register if GFSK_MLD is set, and these bits should then
32620  * contain a number that represents {FDev/SD_LSB integer[11:0] + FDev/SD_LSB
32621  * fraction[3:0]}
32622  */
32623 /*@{*/
32624 /*! @brief Read current value of the XCVR_TX_GFSK_MOD_CTRL_GFSK_MULTIPLY_TABLE_MANUAL field. */
32625 #define XCVR_RD_TX_GFSK_MOD_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(base) ((XCVR_TX_GFSK_MOD_CTRL_REG(base) & XCVR_TX_GFSK_MOD_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_MASK) >> XCVR_TX_GFSK_MOD_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_SHIFT)
32626 #define XCVR_BRD_TX_GFSK_MOD_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(base) (BME_UBFX32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), XCVR_TX_GFSK_MOD_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_SHIFT, XCVR_TX_GFSK_MOD_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_WIDTH))
32627 
32628 /*! @brief Set the GFSK_MULTIPLY_TABLE_MANUAL field to a new value. */
32629 #define XCVR_WR_TX_GFSK_MOD_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(base, value) (XCVR_RMW_TX_GFSK_MOD_CTRL(base, XCVR_TX_GFSK_MOD_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_MASK, XCVR_TX_GFSK_MOD_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(value)))
32630 #define XCVR_BWR_TX_GFSK_MOD_CTRL_GFSK_MULTIPLY_TABLE_MANUAL(base, value) (BME_BFI32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_TX_GFSK_MOD_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_SHIFT), XCVR_TX_GFSK_MOD_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_SHIFT, XCVR_TX_GFSK_MOD_CTRL_GFSK_MULTIPLY_TABLE_MANUAL_WIDTH))
32631 /*@}*/
32632 
32633 /*!
32634  * @name Register XCVR_TX_GFSK_MOD_CTRL, field GFSK_MI[17:16] (RW)
32635  *
32636  * This register selects the GFSK Modulation Index which together with the GFSK
32637  * Symbol Rate determines the Peak Modulation frequency.The formula used for the
32638  * Peak Modulation is (Symbol Rate / (2 x 1/Modulation Index))
32639  *
32640  * Values:
32641  * - 0b00 - 0.32
32642  * - 0b01 - 0.50
32643  * - 0b10 - 0.80
32644  * - 0b11 - 1.00
32645  */
32646 /*@{*/
32647 /*! @brief Read current value of the XCVR_TX_GFSK_MOD_CTRL_GFSK_MI field. */
32648 #define XCVR_RD_TX_GFSK_MOD_CTRL_GFSK_MI(base) ((XCVR_TX_GFSK_MOD_CTRL_REG(base) & XCVR_TX_GFSK_MOD_CTRL_GFSK_MI_MASK) >> XCVR_TX_GFSK_MOD_CTRL_GFSK_MI_SHIFT)
32649 #define XCVR_BRD_TX_GFSK_MOD_CTRL_GFSK_MI(base) (BME_UBFX32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), XCVR_TX_GFSK_MOD_CTRL_GFSK_MI_SHIFT, XCVR_TX_GFSK_MOD_CTRL_GFSK_MI_WIDTH))
32650 
32651 /*! @brief Set the GFSK_MI field to a new value. */
32652 #define XCVR_WR_TX_GFSK_MOD_CTRL_GFSK_MI(base, value) (XCVR_RMW_TX_GFSK_MOD_CTRL(base, XCVR_TX_GFSK_MOD_CTRL_GFSK_MI_MASK, XCVR_TX_GFSK_MOD_CTRL_GFSK_MI(value)))
32653 #define XCVR_BWR_TX_GFSK_MOD_CTRL_GFSK_MI(base, value) (BME_BFI32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_TX_GFSK_MOD_CTRL_GFSK_MI_SHIFT), XCVR_TX_GFSK_MOD_CTRL_GFSK_MI_SHIFT, XCVR_TX_GFSK_MOD_CTRL_GFSK_MI_WIDTH))
32654 /*@}*/
32655 
32656 /*!
32657  * @name Register XCVR_TX_GFSK_MOD_CTRL, field GFSK_MLD[20] (RW)
32658  *
32659  * If this bit is set, the GFSK Multiply Lookup table is disabled and
32660  * GFSK_MULTIPLY_TABLE_MANUAL is used instead.
32661  */
32662 /*@{*/
32663 /*! @brief Read current value of the XCVR_TX_GFSK_MOD_CTRL_GFSK_MLD field. */
32664 #define XCVR_RD_TX_GFSK_MOD_CTRL_GFSK_MLD(base) ((XCVR_TX_GFSK_MOD_CTRL_REG(base) & XCVR_TX_GFSK_MOD_CTRL_GFSK_MLD_MASK) >> XCVR_TX_GFSK_MOD_CTRL_GFSK_MLD_SHIFT)
32665 #define XCVR_BRD_TX_GFSK_MOD_CTRL_GFSK_MLD(base) (BME_UBFX32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), XCVR_TX_GFSK_MOD_CTRL_GFSK_MLD_SHIFT, XCVR_TX_GFSK_MOD_CTRL_GFSK_MLD_WIDTH))
32666 
32667 /*! @brief Set the GFSK_MLD field to a new value. */
32668 #define XCVR_WR_TX_GFSK_MOD_CTRL_GFSK_MLD(base, value) (XCVR_RMW_TX_GFSK_MOD_CTRL(base, XCVR_TX_GFSK_MOD_CTRL_GFSK_MLD_MASK, XCVR_TX_GFSK_MOD_CTRL_GFSK_MLD(value)))
32669 #define XCVR_BWR_TX_GFSK_MOD_CTRL_GFSK_MLD(base, value) (BME_BFI32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_TX_GFSK_MOD_CTRL_GFSK_MLD_SHIFT), XCVR_TX_GFSK_MOD_CTRL_GFSK_MLD_SHIFT, XCVR_TX_GFSK_MOD_CTRL_GFSK_MLD_WIDTH))
32670 /*@}*/
32671 
32672 /*!
32673  * @name Register XCVR_TX_GFSK_MOD_CTRL, field GFSK_SYMBOL_RATE[26:24] (RW)
32674  *
32675  * This register selects the GFSK Symbol Rate which together with the GFSK
32676  * Modulation Index determines the Peak Modulation frequency.The formula used for the
32677  * Peak Modulation is (Symbol Rate / (2 x 1/Modulation Index))
32678  *
32679  * Values:
32680  * - 0b000 - 50 kHz
32681  * - 0b001 - 100 kHz
32682  * - 0b010 - 200 kHz
32683  * - 0b011 - 1 MHz
32684  * - 0b100 - 2 MHz
32685  * - 0b101 - Reserved
32686  * - 0b110 - Reserved
32687  * - 0b111 - Reserved
32688  */
32689 /*@{*/
32690 /*! @brief Read current value of the XCVR_TX_GFSK_MOD_CTRL_GFSK_SYMBOL_RATE field. */
32691 #define XCVR_RD_TX_GFSK_MOD_CTRL_GFSK_SYMBOL_RATE(base) ((XCVR_TX_GFSK_MOD_CTRL_REG(base) & XCVR_TX_GFSK_MOD_CTRL_GFSK_SYMBOL_RATE_MASK) >> XCVR_TX_GFSK_MOD_CTRL_GFSK_SYMBOL_RATE_SHIFT)
32692 #define XCVR_BRD_TX_GFSK_MOD_CTRL_GFSK_SYMBOL_RATE(base) (BME_UBFX32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), XCVR_TX_GFSK_MOD_CTRL_GFSK_SYMBOL_RATE_SHIFT, XCVR_TX_GFSK_MOD_CTRL_GFSK_SYMBOL_RATE_WIDTH))
32693 
32694 /*! @brief Set the GFSK_SYMBOL_RATE field to a new value. */
32695 #define XCVR_WR_TX_GFSK_MOD_CTRL_GFSK_SYMBOL_RATE(base, value) (XCVR_RMW_TX_GFSK_MOD_CTRL(base, XCVR_TX_GFSK_MOD_CTRL_GFSK_SYMBOL_RATE_MASK, XCVR_TX_GFSK_MOD_CTRL_GFSK_SYMBOL_RATE(value)))
32696 #define XCVR_BWR_TX_GFSK_MOD_CTRL_GFSK_SYMBOL_RATE(base, value) (BME_BFI32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_TX_GFSK_MOD_CTRL_GFSK_SYMBOL_RATE_SHIFT), XCVR_TX_GFSK_MOD_CTRL_GFSK_SYMBOL_RATE_SHIFT, XCVR_TX_GFSK_MOD_CTRL_GFSK_SYMBOL_RATE_WIDTH))
32697 /*@}*/
32698 
32699 /*!
32700  * @name Register XCVR_TX_GFSK_MOD_CTRL, field GFSK_FLD[28] (RW)
32701  *
32702  * If this bit is set, the internal GFSK filter coefficients that are normally
32703  * derived from a lookup table based on the reference clock frequency, are
32704  * disabled, and the coefficients are instead derived from the GFSK_FILTER_COEFF_MANUAL1
32705  * and GFSK_FILTER_COEFF_MANUAL2 registers.
32706  */
32707 /*@{*/
32708 /*! @brief Read current value of the XCVR_TX_GFSK_MOD_CTRL_GFSK_FLD field. */
32709 #define XCVR_RD_TX_GFSK_MOD_CTRL_GFSK_FLD(base) ((XCVR_TX_GFSK_MOD_CTRL_REG(base) & XCVR_TX_GFSK_MOD_CTRL_GFSK_FLD_MASK) >> XCVR_TX_GFSK_MOD_CTRL_GFSK_FLD_SHIFT)
32710 #define XCVR_BRD_TX_GFSK_MOD_CTRL_GFSK_FLD(base) (BME_UBFX32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), XCVR_TX_GFSK_MOD_CTRL_GFSK_FLD_SHIFT, XCVR_TX_GFSK_MOD_CTRL_GFSK_FLD_WIDTH))
32711 
32712 /*! @brief Set the GFSK_FLD field to a new value. */
32713 #define XCVR_WR_TX_GFSK_MOD_CTRL_GFSK_FLD(base, value) (XCVR_RMW_TX_GFSK_MOD_CTRL(base, XCVR_TX_GFSK_MOD_CTRL_GFSK_FLD_MASK, XCVR_TX_GFSK_MOD_CTRL_GFSK_FLD(value)))
32714 #define XCVR_BWR_TX_GFSK_MOD_CTRL_GFSK_FLD(base, value) (BME_BFI32(&XCVR_TX_GFSK_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_TX_GFSK_MOD_CTRL_GFSK_FLD_SHIFT), XCVR_TX_GFSK_MOD_CTRL_GFSK_FLD_SHIFT, XCVR_TX_GFSK_MOD_CTRL_GFSK_FLD_WIDTH))
32715 /*@}*/
32716 
32717 /*******************************************************************************
32718  * XCVR_TX_GFSK_COEFF2 - TX GFSK Filter Coefficients 2
32719  ******************************************************************************/
32720 
32721 /*!
32722  * @brief XCVR_TX_GFSK_COEFF2 - TX GFSK Filter Coefficients 2 (RW)
32723  *
32724  * Reset value: 0xC0630401U
32725  *
32726  * The two registers TX_GFSK_COEFF1 and TX_GFSK_COEFF2 form a 64-bit little
32727  * endian register that is memory mapped internally as shown to override the GFSK
32728  * Filter Coefficients. In 64-bit they combine as
32729  * {TX_GFSK_COEFF2[31:0],TX_GFSK_COEFF1[31:0]} The resulting 64-bit value is GFSK Manual Filter Coefficient [63:0]
32730  */
32731 /*!
32732  * @name Constants and macros for entire XCVR_TX_GFSK_COEFF2 register
32733  */
32734 /*@{*/
32735 #define XCVR_RD_TX_GFSK_COEFF2(base) (XCVR_TX_GFSK_COEFF2_REG(base))
32736 #define XCVR_WR_TX_GFSK_COEFF2(base, value) (XCVR_TX_GFSK_COEFF2_REG(base) = (value))
32737 #define XCVR_RMW_TX_GFSK_COEFF2(base, mask, value) (XCVR_WR_TX_GFSK_COEFF2(base, (XCVR_RD_TX_GFSK_COEFF2(base) & ~(mask)) | (value)))
32738 #define XCVR_SET_TX_GFSK_COEFF2(base, value) (BME_OR32(&XCVR_TX_GFSK_COEFF2_REG(base), (uint32_t)(value)))
32739 #define XCVR_CLR_TX_GFSK_COEFF2(base, value) (BME_AND32(&XCVR_TX_GFSK_COEFF2_REG(base), (uint32_t)(~(value))))
32740 #define XCVR_TOG_TX_GFSK_COEFF2(base, value) (BME_XOR32(&XCVR_TX_GFSK_COEFF2_REG(base), (uint32_t)(value)))
32741 /*@}*/
32742 
32743 /*******************************************************************************
32744  * XCVR_TX_GFSK_COEFF1 - TX GFSK Filter Coefficients 1
32745  ******************************************************************************/
32746 
32747 /*!
32748  * @brief XCVR_TX_GFSK_COEFF1 - TX GFSK Filter Coefficients 1 (RW)
32749  *
32750  * Reset value: 0xBB29960DU
32751  *
32752  * The two registers TX_GFSK_COEFF1 and TX_GFSK_COEFF2 form a 64-bit little
32753  * endian register that is memory mapped internally as shown to override the GFSK
32754  * Filter Coefficients. In 64-bit they combine as
32755  * {TX_GFSK_COEFF2[31:0],TX_GFSK_COEFF1[31:0]} The resulting 64-bit value is GFSK Manual Filter Coefficient [63:0]
32756  */
32757 /*!
32758  * @name Constants and macros for entire XCVR_TX_GFSK_COEFF1 register
32759  */
32760 /*@{*/
32761 #define XCVR_RD_TX_GFSK_COEFF1(base) (XCVR_TX_GFSK_COEFF1_REG(base))
32762 #define XCVR_WR_TX_GFSK_COEFF1(base, value) (XCVR_TX_GFSK_COEFF1_REG(base) = (value))
32763 #define XCVR_RMW_TX_GFSK_COEFF1(base, mask, value) (XCVR_WR_TX_GFSK_COEFF1(base, (XCVR_RD_TX_GFSK_COEFF1(base) & ~(mask)) | (value)))
32764 #define XCVR_SET_TX_GFSK_COEFF1(base, value) (BME_OR32(&XCVR_TX_GFSK_COEFF1_REG(base), (uint32_t)(value)))
32765 #define XCVR_CLR_TX_GFSK_COEFF1(base, value) (BME_AND32(&XCVR_TX_GFSK_COEFF1_REG(base), (uint32_t)(~(value))))
32766 #define XCVR_TOG_TX_GFSK_COEFF1(base, value) (BME_XOR32(&XCVR_TX_GFSK_COEFF1_REG(base), (uint32_t)(value)))
32767 /*@}*/
32768 
32769 /*******************************************************************************
32770  * XCVR_TX_FSK_MOD_SCALE - TX FSK Modulation Scale
32771  ******************************************************************************/
32772 
32773 /*!
32774  * @brief XCVR_TX_FSK_MOD_SCALE - TX FSK Modulation Scale (RW)
32775  *
32776  * Reset value: 0x07FF1800U
32777  */
32778 /*!
32779  * @name Constants and macros for entire XCVR_TX_FSK_MOD_SCALE register
32780  */
32781 /*@{*/
32782 #define XCVR_RD_TX_FSK_MOD_SCALE(base) (XCVR_TX_FSK_MOD_SCALE_REG(base))
32783 #define XCVR_WR_TX_FSK_MOD_SCALE(base, value) (XCVR_TX_FSK_MOD_SCALE_REG(base) = (value))
32784 #define XCVR_RMW_TX_FSK_MOD_SCALE(base, mask, value) (XCVR_WR_TX_FSK_MOD_SCALE(base, (XCVR_RD_TX_FSK_MOD_SCALE(base) & ~(mask)) | (value)))
32785 #define XCVR_SET_TX_FSK_MOD_SCALE(base, value) (BME_OR32(&XCVR_TX_FSK_MOD_SCALE_REG(base), (uint32_t)(value)))
32786 #define XCVR_CLR_TX_FSK_MOD_SCALE(base, value) (BME_AND32(&XCVR_TX_FSK_MOD_SCALE_REG(base), (uint32_t)(~(value))))
32787 #define XCVR_TOG_TX_FSK_MOD_SCALE(base, value) (BME_XOR32(&XCVR_TX_FSK_MOD_SCALE_REG(base), (uint32_t)(value)))
32788 /*@}*/
32789 
32790 /*
32791  * Constants & macros for individual XCVR_TX_FSK_MOD_SCALE bitfields
32792  */
32793 
32794 /*!
32795  * @name Register XCVR_TX_FSK_MOD_SCALE, field FSK_MODULATION_SCALE_0[12:0] (RW)
32796  *
32797  * This register is used to provide the modulation level for a data 0 in
32798  * 802.15.4 Protocols. The signed 12 bit value that is represented by this register is
32799  * presented to the PLL as the Baseband Frequency Word. The frequency result for
32800  * this Modulation Scale will be the value of this register times the PLL Low Port
32801  * Modulator Frequency Resolution; a typical value for the Frequency Resolution
32802  * is 244.14 Hz. The reset value of this little endian register is 0x1800 which
32803  * is the 13-bit value of 1_1000_0000_0000 The two's complement of this reset
32804  * value is -2048 The range of signed values that this register supports is -4096 to
32805  * 4095
32806  */
32807 /*@{*/
32808 /*! @brief Read current value of the XCVR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_0 field. */
32809 #define XCVR_RD_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_0(base) ((XCVR_TX_FSK_MOD_SCALE_REG(base) & XCVR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_0_MASK) >> XCVR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_0_SHIFT)
32810 #define XCVR_BRD_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_0(base) (BME_UBFX32(&XCVR_TX_FSK_MOD_SCALE_REG(base), XCVR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_0_SHIFT, XCVR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_0_WIDTH))
32811 
32812 /*! @brief Set the FSK_MODULATION_SCALE_0 field to a new value. */
32813 #define XCVR_WR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_0(base, value) (XCVR_RMW_TX_FSK_MOD_SCALE(base, XCVR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_0_MASK, XCVR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_0(value)))
32814 #define XCVR_BWR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_0(base, value) (BME_BFI32(&XCVR_TX_FSK_MOD_SCALE_REG(base), ((uint32_t)(value) << XCVR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_0_SHIFT), XCVR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_0_SHIFT, XCVR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_0_WIDTH))
32815 /*@}*/
32816 
32817 /*!
32818  * @name Register XCVR_TX_FSK_MOD_SCALE, field FSK_MODULATION_SCALE_1[28:16] (RW)
32819  *
32820  * This register is used to provide the modulation level for a data 1 in
32821  * 802.15.4 Protocols. The signed 12 bit value that is represented by this register is
32822  * presented to the PLL as the Baseband Frequency Word. The frequency result for
32823  * this Modulation Scale will be the value of this register times the PLL Low Port
32824  * Modulator Frequency Resolution; a typical value for the Frequency Resolution
32825  * is 244.14 Hz. The reset value of this little endian register is 0x07FF which
32826  * is the 13-bit value of 0_0111_1111_1111 The two's complement of this reset
32827  * value is 2047 The range of signed values that this register supports is -4096 to
32828  * 4095
32829  */
32830 /*@{*/
32831 /*! @brief Read current value of the XCVR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1 field. */
32832 #define XCVR_RD_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1(base) ((XCVR_TX_FSK_MOD_SCALE_REG(base) & XCVR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1_MASK) >> XCVR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1_SHIFT)
32833 #define XCVR_BRD_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1(base) (BME_UBFX32(&XCVR_TX_FSK_MOD_SCALE_REG(base), XCVR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1_SHIFT, XCVR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1_WIDTH))
32834 
32835 /*! @brief Set the FSK_MODULATION_SCALE_1 field to a new value. */
32836 #define XCVR_WR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1(base, value) (XCVR_RMW_TX_FSK_MOD_SCALE(base, XCVR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1_MASK, XCVR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1(value)))
32837 #define XCVR_BWR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1(base, value) (BME_BFI32(&XCVR_TX_FSK_MOD_SCALE_REG(base), ((uint32_t)(value) << XCVR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1_SHIFT), XCVR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1_SHIFT, XCVR_TX_FSK_MOD_SCALE_FSK_MODULATION_SCALE_1_WIDTH))
32838 /*@}*/
32839 
32840 /*******************************************************************************
32841  * XCVR_TX_DFT_MOD_PAT - TX DFT Modulation Pattern
32842  ******************************************************************************/
32843 
32844 /*!
32845  * @brief XCVR_TX_DFT_MOD_PAT - TX DFT Modulation Pattern (RW)
32846  *
32847  * Reset value: 0x00000000U
32848  */
32849 /*!
32850  * @name Constants and macros for entire XCVR_TX_DFT_MOD_PAT register
32851  */
32852 /*@{*/
32853 #define XCVR_RD_TX_DFT_MOD_PAT(base) (XCVR_TX_DFT_MOD_PAT_REG(base))
32854 #define XCVR_WR_TX_DFT_MOD_PAT(base, value) (XCVR_TX_DFT_MOD_PAT_REG(base) = (value))
32855 #define XCVR_RMW_TX_DFT_MOD_PAT(base, mask, value) (XCVR_WR_TX_DFT_MOD_PAT(base, (XCVR_RD_TX_DFT_MOD_PAT(base) & ~(mask)) | (value)))
32856 #define XCVR_SET_TX_DFT_MOD_PAT(base, value) (BME_OR32(&XCVR_TX_DFT_MOD_PAT_REG(base), (uint32_t)(value)))
32857 #define XCVR_CLR_TX_DFT_MOD_PAT(base, value) (BME_AND32(&XCVR_TX_DFT_MOD_PAT_REG(base), (uint32_t)(~(value))))
32858 #define XCVR_TOG_TX_DFT_MOD_PAT(base, value) (BME_XOR32(&XCVR_TX_DFT_MOD_PAT_REG(base), (uint32_t)(value)))
32859 /*@}*/
32860 
32861 /*******************************************************************************
32862  * XCVR_TX_DFT_TONE_0_1 - TX DFT Tones 0 and 1
32863  ******************************************************************************/
32864 
32865 /*!
32866  * @brief XCVR_TX_DFT_TONE_0_1 - TX DFT Tones 0 and 1 (RW)
32867  *
32868  * Reset value: 0x10000FFFU
32869  *
32870  * The DFT Tone Registers are used in DFT Tone modes to bypass the GFSK and FSK
32871  * Modulators and instead present the selected Tone to the PLL as a constant tone
32872  * modulation. The two's complement range of these little endian registers is
32873  * -4096 to 4095
32874  */
32875 /*!
32876  * @name Constants and macros for entire XCVR_TX_DFT_TONE_0_1 register
32877  */
32878 /*@{*/
32879 #define XCVR_RD_TX_DFT_TONE_0_1(base) (XCVR_TX_DFT_TONE_0_1_REG(base))
32880 #define XCVR_WR_TX_DFT_TONE_0_1(base, value) (XCVR_TX_DFT_TONE_0_1_REG(base) = (value))
32881 #define XCVR_RMW_TX_DFT_TONE_0_1(base, mask, value) (XCVR_WR_TX_DFT_TONE_0_1(base, (XCVR_RD_TX_DFT_TONE_0_1(base) & ~(mask)) | (value)))
32882 #define XCVR_SET_TX_DFT_TONE_0_1(base, value) (BME_OR32(&XCVR_TX_DFT_TONE_0_1_REG(base), (uint32_t)(value)))
32883 #define XCVR_CLR_TX_DFT_TONE_0_1(base, value) (BME_AND32(&XCVR_TX_DFT_TONE_0_1_REG(base), (uint32_t)(~(value))))
32884 #define XCVR_TOG_TX_DFT_TONE_0_1(base, value) (BME_XOR32(&XCVR_TX_DFT_TONE_0_1_REG(base), (uint32_t)(value)))
32885 /*@}*/
32886 
32887 /*
32888  * Constants & macros for individual XCVR_TX_DFT_TONE_0_1 bitfields
32889  */
32890 
32891 /*!
32892  * @name Register XCVR_TX_DFT_TONE_0_1, field DFT_TONE_1[12:0] (RW)
32893  *
32894  * This register is used to provide the modulation level in DFT Tone Modes. The
32895  * signed 12 bit value that is represented by this register is presented to the
32896  * PLL as the Baseband Frequency Word. The frequency result for this Tone will be
32897  * the value of this register times the PLL Low Port Modulator Frequency
32898  * Resolution; a typical value for the Frequency Resolution is 244.14 Hz.
32899  */
32900 /*@{*/
32901 /*! @brief Read current value of the XCVR_TX_DFT_TONE_0_1_DFT_TONE_1 field. */
32902 #define XCVR_RD_TX_DFT_TONE_0_1_DFT_TONE_1(base) ((XCVR_TX_DFT_TONE_0_1_REG(base) & XCVR_TX_DFT_TONE_0_1_DFT_TONE_1_MASK) >> XCVR_TX_DFT_TONE_0_1_DFT_TONE_1_SHIFT)
32903 #define XCVR_BRD_TX_DFT_TONE_0_1_DFT_TONE_1(base) (BME_UBFX32(&XCVR_TX_DFT_TONE_0_1_REG(base), XCVR_TX_DFT_TONE_0_1_DFT_TONE_1_SHIFT, XCVR_TX_DFT_TONE_0_1_DFT_TONE_1_WIDTH))
32904 
32905 /*! @brief Set the DFT_TONE_1 field to a new value. */
32906 #define XCVR_WR_TX_DFT_TONE_0_1_DFT_TONE_1(base, value) (XCVR_RMW_TX_DFT_TONE_0_1(base, XCVR_TX_DFT_TONE_0_1_DFT_TONE_1_MASK, XCVR_TX_DFT_TONE_0_1_DFT_TONE_1(value)))
32907 #define XCVR_BWR_TX_DFT_TONE_0_1_DFT_TONE_1(base, value) (BME_BFI32(&XCVR_TX_DFT_TONE_0_1_REG(base), ((uint32_t)(value) << XCVR_TX_DFT_TONE_0_1_DFT_TONE_1_SHIFT), XCVR_TX_DFT_TONE_0_1_DFT_TONE_1_SHIFT, XCVR_TX_DFT_TONE_0_1_DFT_TONE_1_WIDTH))
32908 /*@}*/
32909 
32910 /*!
32911  * @name Register XCVR_TX_DFT_TONE_0_1, field DFT_TONE_0[28:16] (RW)
32912  *
32913  * This register is used to provide the modulation level in DFT Tone Modes. The
32914  * signed 12 bit value that is represented by this register is presented to the
32915  * PLL as the Baseband Frequency Word. The frequency result for this Tone will be
32916  * the value of this register times the PLL Low Port Modulator Frequency
32917  * Resolution; a typical value for the Frequency Resolution is 244.14 Hz.
32918  */
32919 /*@{*/
32920 /*! @brief Read current value of the XCVR_TX_DFT_TONE_0_1_DFT_TONE_0 field. */
32921 #define XCVR_RD_TX_DFT_TONE_0_1_DFT_TONE_0(base) ((XCVR_TX_DFT_TONE_0_1_REG(base) & XCVR_TX_DFT_TONE_0_1_DFT_TONE_0_MASK) >> XCVR_TX_DFT_TONE_0_1_DFT_TONE_0_SHIFT)
32922 #define XCVR_BRD_TX_DFT_TONE_0_1_DFT_TONE_0(base) (BME_UBFX32(&XCVR_TX_DFT_TONE_0_1_REG(base), XCVR_TX_DFT_TONE_0_1_DFT_TONE_0_SHIFT, XCVR_TX_DFT_TONE_0_1_DFT_TONE_0_WIDTH))
32923 
32924 /*! @brief Set the DFT_TONE_0 field to a new value. */
32925 #define XCVR_WR_TX_DFT_TONE_0_1_DFT_TONE_0(base, value) (XCVR_RMW_TX_DFT_TONE_0_1(base, XCVR_TX_DFT_TONE_0_1_DFT_TONE_0_MASK, XCVR_TX_DFT_TONE_0_1_DFT_TONE_0(value)))
32926 #define XCVR_BWR_TX_DFT_TONE_0_1_DFT_TONE_0(base, value) (BME_BFI32(&XCVR_TX_DFT_TONE_0_1_REG(base), ((uint32_t)(value) << XCVR_TX_DFT_TONE_0_1_DFT_TONE_0_SHIFT), XCVR_TX_DFT_TONE_0_1_DFT_TONE_0_SHIFT, XCVR_TX_DFT_TONE_0_1_DFT_TONE_0_WIDTH))
32927 /*@}*/
32928 
32929 /*******************************************************************************
32930  * XCVR_TX_DFT_TONE_2_3 - TX DFT Tones 2 and 3
32931  ******************************************************************************/
32932 
32933 /*!
32934  * @brief XCVR_TX_DFT_TONE_2_3 - TX DFT Tones 2 and 3 (RW)
32935  *
32936  * Reset value: 0x1E0001FFU
32937  *
32938  * The DFT Tone Registers are used in DFT Tone modes to bypass the GFSK and FSK
32939  * Modulators and instead present the selected Tone to the PLL as a constant tone
32940  * modulation. The two's complement range of these little endian registers is
32941  * -4096 to 4095
32942  */
32943 /*!
32944  * @name Constants and macros for entire XCVR_TX_DFT_TONE_2_3 register
32945  */
32946 /*@{*/
32947 #define XCVR_RD_TX_DFT_TONE_2_3(base) (XCVR_TX_DFT_TONE_2_3_REG(base))
32948 #define XCVR_WR_TX_DFT_TONE_2_3(base, value) (XCVR_TX_DFT_TONE_2_3_REG(base) = (value))
32949 #define XCVR_RMW_TX_DFT_TONE_2_3(base, mask, value) (XCVR_WR_TX_DFT_TONE_2_3(base, (XCVR_RD_TX_DFT_TONE_2_3(base) & ~(mask)) | (value)))
32950 #define XCVR_SET_TX_DFT_TONE_2_3(base, value) (BME_OR32(&XCVR_TX_DFT_TONE_2_3_REG(base), (uint32_t)(value)))
32951 #define XCVR_CLR_TX_DFT_TONE_2_3(base, value) (BME_AND32(&XCVR_TX_DFT_TONE_2_3_REG(base), (uint32_t)(~(value))))
32952 #define XCVR_TOG_TX_DFT_TONE_2_3(base, value) (BME_XOR32(&XCVR_TX_DFT_TONE_2_3_REG(base), (uint32_t)(value)))
32953 /*@}*/
32954 
32955 /*
32956  * Constants & macros for individual XCVR_TX_DFT_TONE_2_3 bitfields
32957  */
32958 
32959 /*!
32960  * @name Register XCVR_TX_DFT_TONE_2_3, field DFT_TONE_3[12:0] (RW)
32961  *
32962  * This register is used to provide the modulation level in DFT Tone Modes. The
32963  * signed 12 bit value that is represented by this register is presented to the
32964  * PLL as the Baseband Frequency Word. The frequency result for this Tone will be
32965  * the value of this register times the PLL Low Port Modulator Frequency
32966  * Resolution; a typical value for the Frequency Resolution is 244.14 Hz.
32967  */
32968 /*@{*/
32969 /*! @brief Read current value of the XCVR_TX_DFT_TONE_2_3_DFT_TONE_3 field. */
32970 #define XCVR_RD_TX_DFT_TONE_2_3_DFT_TONE_3(base) ((XCVR_TX_DFT_TONE_2_3_REG(base) & XCVR_TX_DFT_TONE_2_3_DFT_TONE_3_MASK) >> XCVR_TX_DFT_TONE_2_3_DFT_TONE_3_SHIFT)
32971 #define XCVR_BRD_TX_DFT_TONE_2_3_DFT_TONE_3(base) (BME_UBFX32(&XCVR_TX_DFT_TONE_2_3_REG(base), XCVR_TX_DFT_TONE_2_3_DFT_TONE_3_SHIFT, XCVR_TX_DFT_TONE_2_3_DFT_TONE_3_WIDTH))
32972 
32973 /*! @brief Set the DFT_TONE_3 field to a new value. */
32974 #define XCVR_WR_TX_DFT_TONE_2_3_DFT_TONE_3(base, value) (XCVR_RMW_TX_DFT_TONE_2_3(base, XCVR_TX_DFT_TONE_2_3_DFT_TONE_3_MASK, XCVR_TX_DFT_TONE_2_3_DFT_TONE_3(value)))
32975 #define XCVR_BWR_TX_DFT_TONE_2_3_DFT_TONE_3(base, value) (BME_BFI32(&XCVR_TX_DFT_TONE_2_3_REG(base), ((uint32_t)(value) << XCVR_TX_DFT_TONE_2_3_DFT_TONE_3_SHIFT), XCVR_TX_DFT_TONE_2_3_DFT_TONE_3_SHIFT, XCVR_TX_DFT_TONE_2_3_DFT_TONE_3_WIDTH))
32976 /*@}*/
32977 
32978 /*!
32979  * @name Register XCVR_TX_DFT_TONE_2_3, field DFT_TONE_2[28:16] (RW)
32980  *
32981  * This register is used to provide the modulation level in DFT Tone Modes. The
32982  * signed 12 bit value that is represented by this register is presented to the
32983  * PLL as the Baseband Frequency Word. The frequency result for this Tone will be
32984  * the value of this register times the PLL Low Port Modulator Frequency
32985  * Resolution; a typical value for the Frequency Resolution is 244.14 Hz.
32986  */
32987 /*@{*/
32988 /*! @brief Read current value of the XCVR_TX_DFT_TONE_2_3_DFT_TONE_2 field. */
32989 #define XCVR_RD_TX_DFT_TONE_2_3_DFT_TONE_2(base) ((XCVR_TX_DFT_TONE_2_3_REG(base) & XCVR_TX_DFT_TONE_2_3_DFT_TONE_2_MASK) >> XCVR_TX_DFT_TONE_2_3_DFT_TONE_2_SHIFT)
32990 #define XCVR_BRD_TX_DFT_TONE_2_3_DFT_TONE_2(base) (BME_UBFX32(&XCVR_TX_DFT_TONE_2_3_REG(base), XCVR_TX_DFT_TONE_2_3_DFT_TONE_2_SHIFT, XCVR_TX_DFT_TONE_2_3_DFT_TONE_2_WIDTH))
32991 
32992 /*! @brief Set the DFT_TONE_2 field to a new value. */
32993 #define XCVR_WR_TX_DFT_TONE_2_3_DFT_TONE_2(base, value) (XCVR_RMW_TX_DFT_TONE_2_3(base, XCVR_TX_DFT_TONE_2_3_DFT_TONE_2_MASK, XCVR_TX_DFT_TONE_2_3_DFT_TONE_2(value)))
32994 #define XCVR_BWR_TX_DFT_TONE_2_3_DFT_TONE_2(base, value) (BME_BFI32(&XCVR_TX_DFT_TONE_2_3_REG(base), ((uint32_t)(value) << XCVR_TX_DFT_TONE_2_3_DFT_TONE_2_SHIFT), XCVR_TX_DFT_TONE_2_3_DFT_TONE_2_SHIFT, XCVR_TX_DFT_TONE_2_3_DFT_TONE_2_WIDTH))
32995 /*@}*/
32996 
32997 /*******************************************************************************
32998  * XCVR_PLL_MOD_OVRD - PLL Modulation Overrides
32999  ******************************************************************************/
33000 
33001 /*!
33002  * @brief XCVR_PLL_MOD_OVRD - PLL Modulation Overrides (RW)
33003  *
33004  * Reset value: 0x00000000U
33005  */
33006 /*!
33007  * @name Constants and macros for entire XCVR_PLL_MOD_OVRD register
33008  */
33009 /*@{*/
33010 #define XCVR_RD_PLL_MOD_OVRD(base) (XCVR_PLL_MOD_OVRD_REG(base))
33011 #define XCVR_WR_PLL_MOD_OVRD(base, value) (XCVR_PLL_MOD_OVRD_REG(base) = (value))
33012 #define XCVR_RMW_PLL_MOD_OVRD(base, mask, value) (XCVR_WR_PLL_MOD_OVRD(base, (XCVR_RD_PLL_MOD_OVRD(base) & ~(mask)) | (value)))
33013 #define XCVR_SET_PLL_MOD_OVRD(base, value) (BME_OR32(&XCVR_PLL_MOD_OVRD_REG(base), (uint32_t)(value)))
33014 #define XCVR_CLR_PLL_MOD_OVRD(base, value) (BME_AND32(&XCVR_PLL_MOD_OVRD_REG(base), (uint32_t)(~(value))))
33015 #define XCVR_TOG_PLL_MOD_OVRD(base, value) (BME_XOR32(&XCVR_PLL_MOD_OVRD_REG(base), (uint32_t)(value)))
33016 /*@}*/
33017 
33018 /*
33019  * Constants & macros for individual XCVR_PLL_MOD_OVRD bitfields
33020  */
33021 
33022 /*!
33023  * @name Register XCVR_PLL_MOD_OVRD, field MODULATION_WORD_MANUAL[12:0] (RW)
33024  *
33025  * If MOD_DIS is set, the signed 12 bit value that is represented by this
33026  * register is the Baseband Frequency Word.
33027  */
33028 /*@{*/
33029 /*! @brief Read current value of the XCVR_PLL_MOD_OVRD_MODULATION_WORD_MANUAL field. */
33030 #define XCVR_RD_PLL_MOD_OVRD_MODULATION_WORD_MANUAL(base) ((XCVR_PLL_MOD_OVRD_REG(base) & XCVR_PLL_MOD_OVRD_MODULATION_WORD_MANUAL_MASK) >> XCVR_PLL_MOD_OVRD_MODULATION_WORD_MANUAL_SHIFT)
33031 #define XCVR_BRD_PLL_MOD_OVRD_MODULATION_WORD_MANUAL(base) (BME_UBFX32(&XCVR_PLL_MOD_OVRD_REG(base), XCVR_PLL_MOD_OVRD_MODULATION_WORD_MANUAL_SHIFT, XCVR_PLL_MOD_OVRD_MODULATION_WORD_MANUAL_WIDTH))
33032 
33033 /*! @brief Set the MODULATION_WORD_MANUAL field to a new value. */
33034 #define XCVR_WR_PLL_MOD_OVRD_MODULATION_WORD_MANUAL(base, value) (XCVR_RMW_PLL_MOD_OVRD(base, XCVR_PLL_MOD_OVRD_MODULATION_WORD_MANUAL_MASK, XCVR_PLL_MOD_OVRD_MODULATION_WORD_MANUAL(value)))
33035 #define XCVR_BWR_PLL_MOD_OVRD_MODULATION_WORD_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_MOD_OVRD_REG(base), ((uint32_t)(value) << XCVR_PLL_MOD_OVRD_MODULATION_WORD_MANUAL_SHIFT), XCVR_PLL_MOD_OVRD_MODULATION_WORD_MANUAL_SHIFT, XCVR_PLL_MOD_OVRD_MODULATION_WORD_MANUAL_WIDTH))
33036 /*@}*/
33037 
33038 /*!
33039  * @name Register XCVR_PLL_MOD_OVRD, field MOD_DIS[15] (RW)
33040  *
33041  * If this bit is set, any modulation from the TX Digital is disabled and the
33042  * source of the Baseband Frequency Word is the MODULATION_WORD_MANUAL register.
33043  */
33044 /*@{*/
33045 /*! @brief Read current value of the XCVR_PLL_MOD_OVRD_MOD_DIS field. */
33046 #define XCVR_RD_PLL_MOD_OVRD_MOD_DIS(base) ((XCVR_PLL_MOD_OVRD_REG(base) & XCVR_PLL_MOD_OVRD_MOD_DIS_MASK) >> XCVR_PLL_MOD_OVRD_MOD_DIS_SHIFT)
33047 #define XCVR_BRD_PLL_MOD_OVRD_MOD_DIS(base) (BME_UBFX32(&XCVR_PLL_MOD_OVRD_REG(base), XCVR_PLL_MOD_OVRD_MOD_DIS_SHIFT, XCVR_PLL_MOD_OVRD_MOD_DIS_WIDTH))
33048 
33049 /*! @brief Set the MOD_DIS field to a new value. */
33050 #define XCVR_WR_PLL_MOD_OVRD_MOD_DIS(base, value) (XCVR_RMW_PLL_MOD_OVRD(base, XCVR_PLL_MOD_OVRD_MOD_DIS_MASK, XCVR_PLL_MOD_OVRD_MOD_DIS(value)))
33051 #define XCVR_BWR_PLL_MOD_OVRD_MOD_DIS(base, value) (BME_BFI32(&XCVR_PLL_MOD_OVRD_REG(base), ((uint32_t)(value) << XCVR_PLL_MOD_OVRD_MOD_DIS_SHIFT), XCVR_PLL_MOD_OVRD_MOD_DIS_SHIFT, XCVR_PLL_MOD_OVRD_MOD_DIS_WIDTH))
33052 /*@}*/
33053 
33054 /*!
33055  * @name Register XCVR_PLL_MOD_OVRD, field HPM_BANK_MANUAL[23:16] (RW)
33056  *
33057  * If HPM_BANK_DIS is set, this register is the value that is applied to the VCO
33058  * High Port Bank.
33059  */
33060 /*@{*/
33061 /*! @brief Read current value of the XCVR_PLL_MOD_OVRD_HPM_BANK_MANUAL field. */
33062 #define XCVR_RD_PLL_MOD_OVRD_HPM_BANK_MANUAL(base) ((XCVR_PLL_MOD_OVRD_REG(base) & XCVR_PLL_MOD_OVRD_HPM_BANK_MANUAL_MASK) >> XCVR_PLL_MOD_OVRD_HPM_BANK_MANUAL_SHIFT)
33063 #define XCVR_BRD_PLL_MOD_OVRD_HPM_BANK_MANUAL(base) (BME_UBFX32(&XCVR_PLL_MOD_OVRD_REG(base), XCVR_PLL_MOD_OVRD_HPM_BANK_MANUAL_SHIFT, XCVR_PLL_MOD_OVRD_HPM_BANK_MANUAL_WIDTH))
33064 
33065 /*! @brief Set the HPM_BANK_MANUAL field to a new value. */
33066 #define XCVR_WR_PLL_MOD_OVRD_HPM_BANK_MANUAL(base, value) (XCVR_RMW_PLL_MOD_OVRD(base, XCVR_PLL_MOD_OVRD_HPM_BANK_MANUAL_MASK, XCVR_PLL_MOD_OVRD_HPM_BANK_MANUAL(value)))
33067 #define XCVR_BWR_PLL_MOD_OVRD_HPM_BANK_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_MOD_OVRD_REG(base), ((uint32_t)(value) << XCVR_PLL_MOD_OVRD_HPM_BANK_MANUAL_SHIFT), XCVR_PLL_MOD_OVRD_HPM_BANK_MANUAL_SHIFT, XCVR_PLL_MOD_OVRD_HPM_BANK_MANUAL_WIDTH))
33068 /*@}*/
33069 
33070 /*!
33071  * @name Register XCVR_PLL_MOD_OVRD, field HPM_BANK_DIS[27] (RW)
33072  *
33073  * If this bit is set, the High Port Bank Modulation is disabled, and the High
33074  * Port Bank value applied to the VCO comes from the HPM_BANK_MANUAL register.
33075  */
33076 /*@{*/
33077 /*! @brief Read current value of the XCVR_PLL_MOD_OVRD_HPM_BANK_DIS field. */
33078 #define XCVR_RD_PLL_MOD_OVRD_HPM_BANK_DIS(base) ((XCVR_PLL_MOD_OVRD_REG(base) & XCVR_PLL_MOD_OVRD_HPM_BANK_DIS_MASK) >> XCVR_PLL_MOD_OVRD_HPM_BANK_DIS_SHIFT)
33079 #define XCVR_BRD_PLL_MOD_OVRD_HPM_BANK_DIS(base) (BME_UBFX32(&XCVR_PLL_MOD_OVRD_REG(base), XCVR_PLL_MOD_OVRD_HPM_BANK_DIS_SHIFT, XCVR_PLL_MOD_OVRD_HPM_BANK_DIS_WIDTH))
33080 
33081 /*! @brief Set the HPM_BANK_DIS field to a new value. */
33082 #define XCVR_WR_PLL_MOD_OVRD_HPM_BANK_DIS(base, value) (XCVR_RMW_PLL_MOD_OVRD(base, XCVR_PLL_MOD_OVRD_HPM_BANK_DIS_MASK, XCVR_PLL_MOD_OVRD_HPM_BANK_DIS(value)))
33083 #define XCVR_BWR_PLL_MOD_OVRD_HPM_BANK_DIS(base, value) (BME_BFI32(&XCVR_PLL_MOD_OVRD_REG(base), ((uint32_t)(value) << XCVR_PLL_MOD_OVRD_HPM_BANK_DIS_SHIFT), XCVR_PLL_MOD_OVRD_HPM_BANK_DIS_SHIFT, XCVR_PLL_MOD_OVRD_HPM_BANK_DIS_WIDTH))
33084 /*@}*/
33085 
33086 /*!
33087  * @name Register XCVR_PLL_MOD_OVRD, field HPM_LSB_MANUAL[29:28] (RW)
33088  *
33089  * If HPM_LSB_DIS is set, this register is the value that is applied to the VCO
33090  * High Port LSB.
33091  */
33092 /*@{*/
33093 /*! @brief Read current value of the XCVR_PLL_MOD_OVRD_HPM_LSB_MANUAL field. */
33094 #define XCVR_RD_PLL_MOD_OVRD_HPM_LSB_MANUAL(base) ((XCVR_PLL_MOD_OVRD_REG(base) & XCVR_PLL_MOD_OVRD_HPM_LSB_MANUAL_MASK) >> XCVR_PLL_MOD_OVRD_HPM_LSB_MANUAL_SHIFT)
33095 #define XCVR_BRD_PLL_MOD_OVRD_HPM_LSB_MANUAL(base) (BME_UBFX32(&XCVR_PLL_MOD_OVRD_REG(base), XCVR_PLL_MOD_OVRD_HPM_LSB_MANUAL_SHIFT, XCVR_PLL_MOD_OVRD_HPM_LSB_MANUAL_WIDTH))
33096 
33097 /*! @brief Set the HPM_LSB_MANUAL field to a new value. */
33098 #define XCVR_WR_PLL_MOD_OVRD_HPM_LSB_MANUAL(base, value) (XCVR_RMW_PLL_MOD_OVRD(base, XCVR_PLL_MOD_OVRD_HPM_LSB_MANUAL_MASK, XCVR_PLL_MOD_OVRD_HPM_LSB_MANUAL(value)))
33099 #define XCVR_BWR_PLL_MOD_OVRD_HPM_LSB_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_MOD_OVRD_REG(base), ((uint32_t)(value) << XCVR_PLL_MOD_OVRD_HPM_LSB_MANUAL_SHIFT), XCVR_PLL_MOD_OVRD_HPM_LSB_MANUAL_SHIFT, XCVR_PLL_MOD_OVRD_HPM_LSB_MANUAL_WIDTH))
33100 /*@}*/
33101 
33102 /*!
33103  * @name Register XCVR_PLL_MOD_OVRD, field HPM_LSB_DIS[31] (RW)
33104  *
33105  * If this bit is set, the High Port Sigma Delta Modulator output is disabled,
33106  * and the High Port LSB value applied to the VCO comes from the HPM_LSB_MANUAL
33107  * register.
33108  */
33109 /*@{*/
33110 /*! @brief Read current value of the XCVR_PLL_MOD_OVRD_HPM_LSB_DIS field. */
33111 #define XCVR_RD_PLL_MOD_OVRD_HPM_LSB_DIS(base) ((XCVR_PLL_MOD_OVRD_REG(base) & XCVR_PLL_MOD_OVRD_HPM_LSB_DIS_MASK) >> XCVR_PLL_MOD_OVRD_HPM_LSB_DIS_SHIFT)
33112 #define XCVR_BRD_PLL_MOD_OVRD_HPM_LSB_DIS(base) (BME_UBFX32(&XCVR_PLL_MOD_OVRD_REG(base), XCVR_PLL_MOD_OVRD_HPM_LSB_DIS_SHIFT, XCVR_PLL_MOD_OVRD_HPM_LSB_DIS_WIDTH))
33113 
33114 /*! @brief Set the HPM_LSB_DIS field to a new value. */
33115 #define XCVR_WR_PLL_MOD_OVRD_HPM_LSB_DIS(base, value) (XCVR_RMW_PLL_MOD_OVRD(base, XCVR_PLL_MOD_OVRD_HPM_LSB_DIS_MASK, XCVR_PLL_MOD_OVRD_HPM_LSB_DIS(value)))
33116 #define XCVR_BWR_PLL_MOD_OVRD_HPM_LSB_DIS(base, value) (BME_BFI32(&XCVR_PLL_MOD_OVRD_REG(base), ((uint32_t)(value) << XCVR_PLL_MOD_OVRD_HPM_LSB_DIS_SHIFT), XCVR_PLL_MOD_OVRD_HPM_LSB_DIS_SHIFT, XCVR_PLL_MOD_OVRD_HPM_LSB_DIS_WIDTH))
33117 /*@}*/
33118 
33119 /*******************************************************************************
33120  * XCVR_PLL_CHAN_MAP - PLL Channel Mapping
33121  ******************************************************************************/
33122 
33123 /*!
33124  * @brief XCVR_PLL_CHAN_MAP - PLL Channel Mapping (RW)
33125  *
33126  * Reset value: 0x00000200U
33127  */
33128 /*!
33129  * @name Constants and macros for entire XCVR_PLL_CHAN_MAP register
33130  */
33131 /*@{*/
33132 #define XCVR_RD_PLL_CHAN_MAP(base) (XCVR_PLL_CHAN_MAP_REG(base))
33133 #define XCVR_WR_PLL_CHAN_MAP(base, value) (XCVR_PLL_CHAN_MAP_REG(base) = (value))
33134 #define XCVR_RMW_PLL_CHAN_MAP(base, mask, value) (XCVR_WR_PLL_CHAN_MAP(base, (XCVR_RD_PLL_CHAN_MAP(base) & ~(mask)) | (value)))
33135 #define XCVR_SET_PLL_CHAN_MAP(base, value) (BME_OR32(&XCVR_PLL_CHAN_MAP_REG(base), (uint32_t)(value)))
33136 #define XCVR_CLR_PLL_CHAN_MAP(base, value) (BME_AND32(&XCVR_PLL_CHAN_MAP_REG(base), (uint32_t)(~(value))))
33137 #define XCVR_TOG_PLL_CHAN_MAP(base, value) (BME_XOR32(&XCVR_PLL_CHAN_MAP_REG(base), (uint32_t)(value)))
33138 /*@}*/
33139 
33140 /*
33141  * Constants & macros for individual XCVR_PLL_CHAN_MAP bitfields
33142  */
33143 
33144 /*!
33145  * @name Register XCVR_PLL_CHAN_MAP, field CHANNEL_NUM[6:0] (RW)
33146  *
33147  * When this register is active, it can be used to directly select a Protocol
33148  * specific Channel Number, which is mapped internally to the correct Radio Carrier
33149  * Frequency for PLL tuning. The internal mapping is detailed in the table
33150  * below. This register is active when BOC or ZOC are set along with their
33151  * corresponding Radio Protocols, and this register is also active in the 128 Channel FSK
33152  * and GFSK protocols. The Radio Carrier Frequency in the 128 Channel FSK and GFSK
33153  * protocols can be calculated using the formula below: Radio Carrier Frequency =
33154  * (Channel Number + 2360) x 1 MHz The Radio Channel Frequency can also be
33155  * selected by setting the SDM_MAP_DIS bit in the PLL_LP_SDM_CTRL1 register along with
33156  * the LPM_INTG, LPM_NUM, and LPM_DENOM registers to get a frequency that equals
33157  * ((Reference Clock Frequency x 2) x (LPM_INTG + (LPM_NUM / LPM_DENOM)) This
33158  * table shows the internal mapping by Protocol of the Channel Numbers to the Radio
33159  * Carrier Frequency (MHz). Channel Number 000 BLE 001 BLE in MBAN 010 BLE
33160  * Overlap MBAN 100 Zigbee 101 802.15.4j 0 2402 2360 2402 2400 2363 1 2404 2361 2404
33161  * 2400 2368 2 2406 2362 2406 2400 2373 3 2408 2363 2408 2400 2378 4 2410 2364
33162  * 2410 2400 2383 5 2412 2365 2412 2400 2388 6 2414 2366 2414 2400 2393 7 2416 2367
33163  * 2416 2400 2367 8 2418 2368 2418 2400 2372 9 2420 2369 2420 2400 2377 10 2422
33164  * 2370 2422 2400 2382 11 2424 2371 2424 2405 2387 12 2426 2372 2426 2410 2392 13
33165  * 2428 2373 2428 2415 2397 14 2430 2374 2430 2420 2395 15 2432 2375 2432 2425
33166  * 2399 16 2434 2376 2434 2430 2399 17 2436 2377 2436 2435 2399 18 2438 2378 2438
33167  * 2440 2399 19 2440 2379 2440 2445 2399 20 2442 2380 2442 2450 2399 21 2444 2381
33168  * 2444 2455 2399 22 2446 2382 2446 2460 2399 23 2448 2383 2448 2465 2399 24 2450
33169  * 2384 2450 2470 2399 25 2452 2385 2452 2475 2399 26 2454 2386 2454 2480 2399
33170  * 27 2456 2387 2456 2400 2399 28 2458 2388 2458 2400 2399 29 2460 2389 2460 2400
33171  * 2399 30 2462 2390 2390 2400 2399 31 2464 2391 2391 2400 2399 32 2466 2392 2392
33172  * 2400 2399 33 2468 2393 2393 2400 2399 34 2470 2394 2394 2400 2399 35 2472
33173  * 2395 2395 2400 2399 36 2474 2396 2396 2400 2399 37 2476 2397 2397 2400 2399 38
33174  * 2478 2398 2398 2400 2399 39 2480 2399 2480 or 2399 * 2400 2399 Default 2400 2399
33175  * 2399 2400 2399 * The BLE MBAN Channel Remap bit, BMR, controls the frequency
33176  * mapping in this case.
33177  */
33178 /*@{*/
33179 /*! @brief Read current value of the XCVR_PLL_CHAN_MAP_CHANNEL_NUM field. */
33180 #define XCVR_RD_PLL_CHAN_MAP_CHANNEL_NUM(base) ((XCVR_PLL_CHAN_MAP_REG(base) & XCVR_PLL_CHAN_MAP_CHANNEL_NUM_MASK) >> XCVR_PLL_CHAN_MAP_CHANNEL_NUM_SHIFT)
33181 #define XCVR_BRD_PLL_CHAN_MAP_CHANNEL_NUM(base) (BME_UBFX32(&XCVR_PLL_CHAN_MAP_REG(base), XCVR_PLL_CHAN_MAP_CHANNEL_NUM_SHIFT, XCVR_PLL_CHAN_MAP_CHANNEL_NUM_WIDTH))
33182 
33183 /*! @brief Set the CHANNEL_NUM field to a new value. */
33184 #define XCVR_WR_PLL_CHAN_MAP_CHANNEL_NUM(base, value) (XCVR_RMW_PLL_CHAN_MAP(base, XCVR_PLL_CHAN_MAP_CHANNEL_NUM_MASK, XCVR_PLL_CHAN_MAP_CHANNEL_NUM(value)))
33185 #define XCVR_BWR_PLL_CHAN_MAP_CHANNEL_NUM(base, value) (BME_BFI32(&XCVR_PLL_CHAN_MAP_REG(base), ((uint32_t)(value) << XCVR_PLL_CHAN_MAP_CHANNEL_NUM_SHIFT), XCVR_PLL_CHAN_MAP_CHANNEL_NUM_SHIFT, XCVR_PLL_CHAN_MAP_CHANNEL_NUM_WIDTH))
33186 /*@}*/
33187 
33188 /*!
33189  * @name Register XCVR_PLL_CHAN_MAP, field BOC[8] (RW)
33190  *
33191  * This bit controls the source of the BLE channel selection.
33192  *
33193  * Values:
33194  * - 0b0 - BLE channel number comes from the BLE Link Layer
33195  * - 0b1 - BLE channel number comes from the CHANNEL_NUM register
33196  */
33197 /*@{*/
33198 /*! @brief Read current value of the XCVR_PLL_CHAN_MAP_BOC field. */
33199 #define XCVR_RD_PLL_CHAN_MAP_BOC(base) ((XCVR_PLL_CHAN_MAP_REG(base) & XCVR_PLL_CHAN_MAP_BOC_MASK) >> XCVR_PLL_CHAN_MAP_BOC_SHIFT)
33200 #define XCVR_BRD_PLL_CHAN_MAP_BOC(base) (BME_UBFX32(&XCVR_PLL_CHAN_MAP_REG(base), XCVR_PLL_CHAN_MAP_BOC_SHIFT, XCVR_PLL_CHAN_MAP_BOC_WIDTH))
33201 
33202 /*! @brief Set the BOC field to a new value. */
33203 #define XCVR_WR_PLL_CHAN_MAP_BOC(base, value) (XCVR_RMW_PLL_CHAN_MAP(base, XCVR_PLL_CHAN_MAP_BOC_MASK, XCVR_PLL_CHAN_MAP_BOC(value)))
33204 #define XCVR_BWR_PLL_CHAN_MAP_BOC(base, value) (BME_BFI32(&XCVR_PLL_CHAN_MAP_REG(base), ((uint32_t)(value) << XCVR_PLL_CHAN_MAP_BOC_SHIFT), XCVR_PLL_CHAN_MAP_BOC_SHIFT, XCVR_PLL_CHAN_MAP_BOC_WIDTH))
33205 /*@}*/
33206 
33207 /*!
33208  * @name Register XCVR_PLL_CHAN_MAP, field BMR[9] (RW)
33209  *
33210  * This bit controls the mapping of BLE channel 39 in Radio Protocol 2, BLE
33211  * overlap MBAN mode.
33212  *
33213  * Values:
33214  * - 0b0 - BLE channel 39 is mapped to BLE channel 39, 2.480 GHz
33215  * - 0b1 - BLE channel 39 is mapped to MBAN channel 39, 2.399 GHz
33216  */
33217 /*@{*/
33218 /*! @brief Read current value of the XCVR_PLL_CHAN_MAP_BMR field. */
33219 #define XCVR_RD_PLL_CHAN_MAP_BMR(base) ((XCVR_PLL_CHAN_MAP_REG(base) & XCVR_PLL_CHAN_MAP_BMR_MASK) >> XCVR_PLL_CHAN_MAP_BMR_SHIFT)
33220 #define XCVR_BRD_PLL_CHAN_MAP_BMR(base) (BME_UBFX32(&XCVR_PLL_CHAN_MAP_REG(base), XCVR_PLL_CHAN_MAP_BMR_SHIFT, XCVR_PLL_CHAN_MAP_BMR_WIDTH))
33221 
33222 /*! @brief Set the BMR field to a new value. */
33223 #define XCVR_WR_PLL_CHAN_MAP_BMR(base, value) (XCVR_RMW_PLL_CHAN_MAP(base, XCVR_PLL_CHAN_MAP_BMR_MASK, XCVR_PLL_CHAN_MAP_BMR(value)))
33224 #define XCVR_BWR_PLL_CHAN_MAP_BMR(base, value) (BME_BFI32(&XCVR_PLL_CHAN_MAP_REG(base), ((uint32_t)(value) << XCVR_PLL_CHAN_MAP_BMR_SHIFT), XCVR_PLL_CHAN_MAP_BMR_SHIFT, XCVR_PLL_CHAN_MAP_BMR_WIDTH))
33225 /*@}*/
33226 
33227 /*!
33228  * @name Register XCVR_PLL_CHAN_MAP, field ZOC[10] (RW)
33229  *
33230  * This bit controls the source of the Zigbee channel selection.
33231  *
33232  * Values:
33233  * - 0b0 - Zigbee channel number comes from the 802.15.4 Link Layer.
33234  * - 0b1 - Zigbee channel number comes from the CHANNEL_NUM register
33235  */
33236 /*@{*/
33237 /*! @brief Read current value of the XCVR_PLL_CHAN_MAP_ZOC field. */
33238 #define XCVR_RD_PLL_CHAN_MAP_ZOC(base) ((XCVR_PLL_CHAN_MAP_REG(base) & XCVR_PLL_CHAN_MAP_ZOC_MASK) >> XCVR_PLL_CHAN_MAP_ZOC_SHIFT)
33239 #define XCVR_BRD_PLL_CHAN_MAP_ZOC(base) (BME_UBFX32(&XCVR_PLL_CHAN_MAP_REG(base), XCVR_PLL_CHAN_MAP_ZOC_SHIFT, XCVR_PLL_CHAN_MAP_ZOC_WIDTH))
33240 
33241 /*! @brief Set the ZOC field to a new value. */
33242 #define XCVR_WR_PLL_CHAN_MAP_ZOC(base, value) (XCVR_RMW_PLL_CHAN_MAP(base, XCVR_PLL_CHAN_MAP_ZOC_MASK, XCVR_PLL_CHAN_MAP_ZOC(value)))
33243 #define XCVR_BWR_PLL_CHAN_MAP_ZOC(base, value) (BME_BFI32(&XCVR_PLL_CHAN_MAP_REG(base), ((uint32_t)(value) << XCVR_PLL_CHAN_MAP_ZOC_SHIFT), XCVR_PLL_CHAN_MAP_ZOC_SHIFT, XCVR_PLL_CHAN_MAP_ZOC_WIDTH))
33244 /*@}*/
33245 
33246 /*******************************************************************************
33247  * XCVR_PLL_LOCK_DETECT - PLL Lock Detect
33248  ******************************************************************************/
33249 
33250 /*!
33251  * @brief XCVR_PLL_LOCK_DETECT - PLL Lock Detect (RW)
33252  *
33253  * Reset value: 0x00202600U
33254  */
33255 /*!
33256  * @name Constants and macros for entire XCVR_PLL_LOCK_DETECT register
33257  */
33258 /*@{*/
33259 #define XCVR_RD_PLL_LOCK_DETECT(base) (XCVR_PLL_LOCK_DETECT_REG(base))
33260 #define XCVR_WR_PLL_LOCK_DETECT(base, value) (XCVR_PLL_LOCK_DETECT_REG(base) = (value))
33261 #define XCVR_RMW_PLL_LOCK_DETECT(base, mask, value) (XCVR_WR_PLL_LOCK_DETECT(base, (XCVR_RD_PLL_LOCK_DETECT(base) & ~(mask)) | (value)))
33262 #define XCVR_SET_PLL_LOCK_DETECT(base, value) (BME_OR32(&XCVR_PLL_LOCK_DETECT_REG(base), (uint32_t)(value)))
33263 #define XCVR_CLR_PLL_LOCK_DETECT(base, value) (BME_AND32(&XCVR_PLL_LOCK_DETECT_REG(base), (uint32_t)(~(value))))
33264 #define XCVR_TOG_PLL_LOCK_DETECT(base, value) (BME_XOR32(&XCVR_PLL_LOCK_DETECT_REG(base), (uint32_t)(value)))
33265 /*@}*/
33266 
33267 /*
33268  * Constants & macros for individual XCVR_PLL_LOCK_DETECT bitfields
33269  */
33270 
33271 /*!
33272  * @name Register XCVR_PLL_LOCK_DETECT, field CT_FAIL[0] (RO)
33273  *
33274  * If the Coarse Tune Calibration has completed and the best count difference is
33275  * out of the range selected by CTUNE_LDF_LEV, then this bit will be set.
33276  */
33277 /*@{*/
33278 /*! @brief Read current value of the XCVR_PLL_LOCK_DETECT_CT_FAIL field. */
33279 #define XCVR_RD_PLL_LOCK_DETECT_CT_FAIL(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK_DETECT_CT_FAIL_MASK) >> XCVR_PLL_LOCK_DETECT_CT_FAIL_SHIFT)
33280 #define XCVR_BRD_PLL_LOCK_DETECT_CT_FAIL(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL_LOCK_DETECT_CT_FAIL_SHIFT, XCVR_PLL_LOCK_DETECT_CT_FAIL_WIDTH))
33281 /*@}*/
33282 
33283 /*!
33284  * @name Register XCVR_PLL_LOCK_DETECT, field CTFF[1] (W1C)
33285  *
33286  * This bit is set when CT_FAIL is first set, and this bit is cleared by writing
33287  * a 1 to it.
33288  */
33289 /*@{*/
33290 /*! @brief Read current value of the XCVR_PLL_LOCK_DETECT_CTFF field. */
33291 #define XCVR_RD_PLL_LOCK_DETECT_CTFF(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK_DETECT_CTFF_MASK) >> XCVR_PLL_LOCK_DETECT_CTFF_SHIFT)
33292 #define XCVR_BRD_PLL_LOCK_DETECT_CTFF(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL_LOCK_DETECT_CTFF_SHIFT, XCVR_PLL_LOCK_DETECT_CTFF_WIDTH))
33293 
33294 /*! @brief Set the CTFF field to a new value. */
33295 #define XCVR_WR_PLL_LOCK_DETECT_CTFF(base, value) (XCVR_RMW_PLL_LOCK_DETECT(base, (XCVR_PLL_LOCK_DETECT_CTFF_MASK | XCVR_PLL_LOCK_DETECT_CSFF_MASK | XCVR_PLL_LOCK_DETECT_FTFF_MASK | XCVR_PLL_LOCK_DETECT_TAFF_MASK), XCVR_PLL_LOCK_DETECT_CTFF(value)))
33296 #define XCVR_BWR_PLL_LOCK_DETECT_CTFF(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(base), ((uint32_t)(value) << XCVR_PLL_LOCK_DETECT_CTFF_SHIFT), XCVR_PLL_LOCK_DETECT_CTFF_SHIFT, XCVR_PLL_LOCK_DETECT_CTFF_WIDTH))
33297 /*@}*/
33298 
33299 /*!
33300  * @name Register XCVR_PLL_LOCK_DETECT, field CS_FAIL[2] (RO)
33301  *
33302  * This bit shows the real-time status of the Cycle Slip State Machine Interrupt
33303  * which is configured using the control bits in the PLL_HPM_CAL1 and
33304  * PLL_HPM_CAL2 registers.
33305  */
33306 /*@{*/
33307 /*! @brief Read current value of the XCVR_PLL_LOCK_DETECT_CS_FAIL field. */
33308 #define XCVR_RD_PLL_LOCK_DETECT_CS_FAIL(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK_DETECT_CS_FAIL_MASK) >> XCVR_PLL_LOCK_DETECT_CS_FAIL_SHIFT)
33309 #define XCVR_BRD_PLL_LOCK_DETECT_CS_FAIL(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL_LOCK_DETECT_CS_FAIL_SHIFT, XCVR_PLL_LOCK_DETECT_CS_FAIL_WIDTH))
33310 /*@}*/
33311 
33312 /*!
33313  * @name Register XCVR_PLL_LOCK_DETECT, field CSFF[3] (W1C)
33314  *
33315  * This bit is set when CS_FAIL is first set, and this bit is cleared by writing
33316  * a 1 to it.
33317  */
33318 /*@{*/
33319 /*! @brief Read current value of the XCVR_PLL_LOCK_DETECT_CSFF field. */
33320 #define XCVR_RD_PLL_LOCK_DETECT_CSFF(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK_DETECT_CSFF_MASK) >> XCVR_PLL_LOCK_DETECT_CSFF_SHIFT)
33321 #define XCVR_BRD_PLL_LOCK_DETECT_CSFF(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL_LOCK_DETECT_CSFF_SHIFT, XCVR_PLL_LOCK_DETECT_CSFF_WIDTH))
33322 
33323 /*! @brief Set the CSFF field to a new value. */
33324 #define XCVR_WR_PLL_LOCK_DETECT_CSFF(base, value) (XCVR_RMW_PLL_LOCK_DETECT(base, (XCVR_PLL_LOCK_DETECT_CSFF_MASK | XCVR_PLL_LOCK_DETECT_CTFF_MASK | XCVR_PLL_LOCK_DETECT_FTFF_MASK | XCVR_PLL_LOCK_DETECT_TAFF_MASK), XCVR_PLL_LOCK_DETECT_CSFF(value)))
33325 #define XCVR_BWR_PLL_LOCK_DETECT_CSFF(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(base), ((uint32_t)(value) << XCVR_PLL_LOCK_DETECT_CSFF_SHIFT), XCVR_PLL_LOCK_DETECT_CSFF_SHIFT, XCVR_PLL_LOCK_DETECT_CSFF_WIDTH))
33326 /*@}*/
33327 
33328 /*!
33329  * @name Register XCVR_PLL_LOCK_DETECT, field FT_FAIL[4] (RO)
33330  *
33331  * If the Frequency Target Count has completed and the count was out of the
33332  * range selected by FTW_TX or FTW_RX, then this bit will be set.
33333  */
33334 /*@{*/
33335 /*! @brief Read current value of the XCVR_PLL_LOCK_DETECT_FT_FAIL field. */
33336 #define XCVR_RD_PLL_LOCK_DETECT_FT_FAIL(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK_DETECT_FT_FAIL_MASK) >> XCVR_PLL_LOCK_DETECT_FT_FAIL_SHIFT)
33337 #define XCVR_BRD_PLL_LOCK_DETECT_FT_FAIL(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL_LOCK_DETECT_FT_FAIL_SHIFT, XCVR_PLL_LOCK_DETECT_FT_FAIL_WIDTH))
33338 /*@}*/
33339 
33340 /*!
33341  * @name Register XCVR_PLL_LOCK_DETECT, field FTFF[5] (W1C)
33342  *
33343  * This bit is set when FT_FAIL is first set, and this bit is cleared by writing
33344  * a 1 to it.
33345  */
33346 /*@{*/
33347 /*! @brief Read current value of the XCVR_PLL_LOCK_DETECT_FTFF field. */
33348 #define XCVR_RD_PLL_LOCK_DETECT_FTFF(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK_DETECT_FTFF_MASK) >> XCVR_PLL_LOCK_DETECT_FTFF_SHIFT)
33349 #define XCVR_BRD_PLL_LOCK_DETECT_FTFF(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL_LOCK_DETECT_FTFF_SHIFT, XCVR_PLL_LOCK_DETECT_FTFF_WIDTH))
33350 
33351 /*! @brief Set the FTFF field to a new value. */
33352 #define XCVR_WR_PLL_LOCK_DETECT_FTFF(base, value) (XCVR_RMW_PLL_LOCK_DETECT(base, (XCVR_PLL_LOCK_DETECT_FTFF_MASK | XCVR_PLL_LOCK_DETECT_CTFF_MASK | XCVR_PLL_LOCK_DETECT_CSFF_MASK | XCVR_PLL_LOCK_DETECT_TAFF_MASK), XCVR_PLL_LOCK_DETECT_FTFF(value)))
33353 #define XCVR_BWR_PLL_LOCK_DETECT_FTFF(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(base), ((uint32_t)(value) << XCVR_PLL_LOCK_DETECT_FTFF_SHIFT), XCVR_PLL_LOCK_DETECT_FTFF_SHIFT, XCVR_PLL_LOCK_DETECT_FTFF_WIDTH))
33354 /*@}*/
33355 
33356 /*!
33357  * @name Register XCVR_PLL_LOCK_DETECT, field TAFF[7] (W1C)
33358  *
33359  * This bit is set if the TSM Sequence Aborts, and this bit is cleared by
33360  * writing a 1 to it.
33361  */
33362 /*@{*/
33363 /*! @brief Read current value of the XCVR_PLL_LOCK_DETECT_TAFF field. */
33364 #define XCVR_RD_PLL_LOCK_DETECT_TAFF(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK_DETECT_TAFF_MASK) >> XCVR_PLL_LOCK_DETECT_TAFF_SHIFT)
33365 #define XCVR_BRD_PLL_LOCK_DETECT_TAFF(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL_LOCK_DETECT_TAFF_SHIFT, XCVR_PLL_LOCK_DETECT_TAFF_WIDTH))
33366 
33367 /*! @brief Set the TAFF field to a new value. */
33368 #define XCVR_WR_PLL_LOCK_DETECT_TAFF(base, value) (XCVR_RMW_PLL_LOCK_DETECT(base, (XCVR_PLL_LOCK_DETECT_TAFF_MASK | XCVR_PLL_LOCK_DETECT_CTFF_MASK | XCVR_PLL_LOCK_DETECT_CSFF_MASK | XCVR_PLL_LOCK_DETECT_FTFF_MASK), XCVR_PLL_LOCK_DETECT_TAFF(value)))
33369 #define XCVR_BWR_PLL_LOCK_DETECT_TAFF(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(base), ((uint32_t)(value) << XCVR_PLL_LOCK_DETECT_TAFF_SHIFT), XCVR_PLL_LOCK_DETECT_TAFF_SHIFT, XCVR_PLL_LOCK_DETECT_TAFF_WIDTH))
33370 /*@}*/
33371 
33372 /*!
33373  * @name Register XCVR_PLL_LOCK_DETECT, field CTUNE_LDF_LEV[11:8] (RW)
33374  *
33375  * The CT_FAIL and CTFF bits will be set after Coarse Tune Calibration completes
33376  * if the absolute value of the Coarse Tune best count difference
33377  * (CTUNE_BEST_DIFF in the PLL_CTUNE_RESULTS register) is greater than this register value.
33378  */
33379 /*@{*/
33380 /*! @brief Read current value of the XCVR_PLL_LOCK_DETECT_CTUNE_LDF_LEV field. */
33381 #define XCVR_RD_PLL_LOCK_DETECT_CTUNE_LDF_LEV(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK_DETECT_CTUNE_LDF_LEV_MASK) >> XCVR_PLL_LOCK_DETECT_CTUNE_LDF_LEV_SHIFT)
33382 #define XCVR_BRD_PLL_LOCK_DETECT_CTUNE_LDF_LEV(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL_LOCK_DETECT_CTUNE_LDF_LEV_SHIFT, XCVR_PLL_LOCK_DETECT_CTUNE_LDF_LEV_WIDTH))
33383 
33384 /*! @brief Set the CTUNE_LDF_LEV field to a new value. */
33385 #define XCVR_WR_PLL_LOCK_DETECT_CTUNE_LDF_LEV(base, value) (XCVR_RMW_PLL_LOCK_DETECT(base, (XCVR_PLL_LOCK_DETECT_CTUNE_LDF_LEV_MASK | XCVR_PLL_LOCK_DETECT_CTFF_MASK | XCVR_PLL_LOCK_DETECT_CSFF_MASK | XCVR_PLL_LOCK_DETECT_FTFF_MASK | XCVR_PLL_LOCK_DETECT_TAFF_MASK), XCVR_PLL_LOCK_DETECT_CTUNE_LDF_LEV(value)))
33386 #define XCVR_BWR_PLL_LOCK_DETECT_CTUNE_LDF_LEV(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(base), ((uint32_t)(value) << XCVR_PLL_LOCK_DETECT_CTUNE_LDF_LEV_SHIFT), XCVR_PLL_LOCK_DETECT_CTUNE_LDF_LEV_SHIFT, XCVR_PLL_LOCK_DETECT_CTUNE_LDF_LEV_WIDTH))
33387 /*@}*/
33388 
33389 /*!
33390  * @name Register XCVR_PLL_LOCK_DETECT, field FTF_RX_THRSH[17:12] (RW)
33391  *
33392  * In Radio Receive Mode, the FT_FAIL and FTFF bits will be set after the
33393  * Frequency Target Count completes if the absolute value of the count difference from
33394  * the frequency target count is greater than this register value.
33395  */
33396 /*@{*/
33397 /*! @brief Read current value of the XCVR_PLL_LOCK_DETECT_FTF_RX_THRSH field. */
33398 #define XCVR_RD_PLL_LOCK_DETECT_FTF_RX_THRSH(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK_DETECT_FTF_RX_THRSH_MASK) >> XCVR_PLL_LOCK_DETECT_FTF_RX_THRSH_SHIFT)
33399 #define XCVR_BRD_PLL_LOCK_DETECT_FTF_RX_THRSH(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL_LOCK_DETECT_FTF_RX_THRSH_SHIFT, XCVR_PLL_LOCK_DETECT_FTF_RX_THRSH_WIDTH))
33400 
33401 /*! @brief Set the FTF_RX_THRSH field to a new value. */
33402 #define XCVR_WR_PLL_LOCK_DETECT_FTF_RX_THRSH(base, value) (XCVR_RMW_PLL_LOCK_DETECT(base, (XCVR_PLL_LOCK_DETECT_FTF_RX_THRSH_MASK | XCVR_PLL_LOCK_DETECT_CTFF_MASK | XCVR_PLL_LOCK_DETECT_CSFF_MASK | XCVR_PLL_LOCK_DETECT_FTFF_MASK | XCVR_PLL_LOCK_DETECT_TAFF_MASK), XCVR_PLL_LOCK_DETECT_FTF_RX_THRSH(value)))
33403 #define XCVR_BWR_PLL_LOCK_DETECT_FTF_RX_THRSH(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(base), ((uint32_t)(value) << XCVR_PLL_LOCK_DETECT_FTF_RX_THRSH_SHIFT), XCVR_PLL_LOCK_DETECT_FTF_RX_THRSH_SHIFT, XCVR_PLL_LOCK_DETECT_FTF_RX_THRSH_WIDTH))
33404 /*@}*/
33405 
33406 /*!
33407  * @name Register XCVR_PLL_LOCK_DETECT, field FTW_RX[19] (RW)
33408  *
33409  * In Radio Receive Mode, this bit selects the length of time to count for the
33410  * estimation of PLL lock frequency, which is compared with the Frequency Target
33411  * Window, set by FTF_RX.
33412  *
33413  * Values:
33414  * - 0b0 - 4 us
33415  * - 0b1 - 8 us
33416  */
33417 /*@{*/
33418 /*! @brief Read current value of the XCVR_PLL_LOCK_DETECT_FTW_RX field. */
33419 #define XCVR_RD_PLL_LOCK_DETECT_FTW_RX(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK_DETECT_FTW_RX_MASK) >> XCVR_PLL_LOCK_DETECT_FTW_RX_SHIFT)
33420 #define XCVR_BRD_PLL_LOCK_DETECT_FTW_RX(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL_LOCK_DETECT_FTW_RX_SHIFT, XCVR_PLL_LOCK_DETECT_FTW_RX_WIDTH))
33421 
33422 /*! @brief Set the FTW_RX field to a new value. */
33423 #define XCVR_WR_PLL_LOCK_DETECT_FTW_RX(base, value) (XCVR_RMW_PLL_LOCK_DETECT(base, (XCVR_PLL_LOCK_DETECT_FTW_RX_MASK | XCVR_PLL_LOCK_DETECT_CTFF_MASK | XCVR_PLL_LOCK_DETECT_CSFF_MASK | XCVR_PLL_LOCK_DETECT_FTFF_MASK | XCVR_PLL_LOCK_DETECT_TAFF_MASK), XCVR_PLL_LOCK_DETECT_FTW_RX(value)))
33424 #define XCVR_BWR_PLL_LOCK_DETECT_FTW_RX(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(base), ((uint32_t)(value) << XCVR_PLL_LOCK_DETECT_FTW_RX_SHIFT), XCVR_PLL_LOCK_DETECT_FTW_RX_SHIFT, XCVR_PLL_LOCK_DETECT_FTW_RX_WIDTH))
33425 /*@}*/
33426 
33427 /*!
33428  * @name Register XCVR_PLL_LOCK_DETECT, field FTF_TX_THRSH[25:20] (RW)
33429  *
33430  * In Radio Transmit Mode, the FT_FAIL and FTFF bits will be set after the
33431  * Frequency Target Count completes if the absolute value of the count difference from
33432  * the frequency target count is greater than this register value.
33433  */
33434 /*@{*/
33435 /*! @brief Read current value of the XCVR_PLL_LOCK_DETECT_FTF_TX_THRSH field. */
33436 #define XCVR_RD_PLL_LOCK_DETECT_FTF_TX_THRSH(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK_DETECT_FTF_TX_THRSH_MASK) >> XCVR_PLL_LOCK_DETECT_FTF_TX_THRSH_SHIFT)
33437 #define XCVR_BRD_PLL_LOCK_DETECT_FTF_TX_THRSH(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL_LOCK_DETECT_FTF_TX_THRSH_SHIFT, XCVR_PLL_LOCK_DETECT_FTF_TX_THRSH_WIDTH))
33438 
33439 /*! @brief Set the FTF_TX_THRSH field to a new value. */
33440 #define XCVR_WR_PLL_LOCK_DETECT_FTF_TX_THRSH(base, value) (XCVR_RMW_PLL_LOCK_DETECT(base, (XCVR_PLL_LOCK_DETECT_FTF_TX_THRSH_MASK | XCVR_PLL_LOCK_DETECT_CTFF_MASK | XCVR_PLL_LOCK_DETECT_CSFF_MASK | XCVR_PLL_LOCK_DETECT_FTFF_MASK | XCVR_PLL_LOCK_DETECT_TAFF_MASK), XCVR_PLL_LOCK_DETECT_FTF_TX_THRSH(value)))
33441 #define XCVR_BWR_PLL_LOCK_DETECT_FTF_TX_THRSH(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(base), ((uint32_t)(value) << XCVR_PLL_LOCK_DETECT_FTF_TX_THRSH_SHIFT), XCVR_PLL_LOCK_DETECT_FTF_TX_THRSH_SHIFT, XCVR_PLL_LOCK_DETECT_FTF_TX_THRSH_WIDTH))
33442 /*@}*/
33443 
33444 /*!
33445  * @name Register XCVR_PLL_LOCK_DETECT, field FTW_TX[27] (RW)
33446  *
33447  * In Radio Transmit Mode, this bit selects the length of time to count for the
33448  * estimation of PLL lock frequency, which is compared with the Frequency Target
33449  * Window, set by FTF_TX.
33450  *
33451  * Values:
33452  * - 0b0 - 4 us
33453  * - 0b1 - 8 us
33454  */
33455 /*@{*/
33456 /*! @brief Read current value of the XCVR_PLL_LOCK_DETECT_FTW_TX field. */
33457 #define XCVR_RD_PLL_LOCK_DETECT_FTW_TX(base) ((XCVR_PLL_LOCK_DETECT_REG(base) & XCVR_PLL_LOCK_DETECT_FTW_TX_MASK) >> XCVR_PLL_LOCK_DETECT_FTW_TX_SHIFT)
33458 #define XCVR_BRD_PLL_LOCK_DETECT_FTW_TX(base) (BME_UBFX32(&XCVR_PLL_LOCK_DETECT_REG(base), XCVR_PLL_LOCK_DETECT_FTW_TX_SHIFT, XCVR_PLL_LOCK_DETECT_FTW_TX_WIDTH))
33459 
33460 /*! @brief Set the FTW_TX field to a new value. */
33461 #define XCVR_WR_PLL_LOCK_DETECT_FTW_TX(base, value) (XCVR_RMW_PLL_LOCK_DETECT(base, (XCVR_PLL_LOCK_DETECT_FTW_TX_MASK | XCVR_PLL_LOCK_DETECT_CTFF_MASK | XCVR_PLL_LOCK_DETECT_CSFF_MASK | XCVR_PLL_LOCK_DETECT_FTFF_MASK | XCVR_PLL_LOCK_DETECT_TAFF_MASK), XCVR_PLL_LOCK_DETECT_FTW_TX(value)))
33462 #define XCVR_BWR_PLL_LOCK_DETECT_FTW_TX(base, value) (BME_BFI32(&XCVR_PLL_LOCK_DETECT_REG(base), ((uint32_t)(value) << XCVR_PLL_LOCK_DETECT_FTW_TX_SHIFT), XCVR_PLL_LOCK_DETECT_FTW_TX_SHIFT, XCVR_PLL_LOCK_DETECT_FTW_TX_WIDTH))
33463 /*@}*/
33464 
33465 /*******************************************************************************
33466  * XCVR_PLL_HP_MOD_CTRL - PLL High Port Modulation Control
33467  ******************************************************************************/
33468 
33469 /*!
33470  * @brief XCVR_PLL_HP_MOD_CTRL - PLL High Port Modulation Control (RW)
33471  *
33472  * Reset value: 0x00840000U
33473  */
33474 /*!
33475  * @name Constants and macros for entire XCVR_PLL_HP_MOD_CTRL register
33476  */
33477 /*@{*/
33478 #define XCVR_RD_PLL_HP_MOD_CTRL(base) (XCVR_PLL_HP_MOD_CTRL_REG(base))
33479 #define XCVR_WR_PLL_HP_MOD_CTRL(base, value) (XCVR_PLL_HP_MOD_CTRL_REG(base) = (value))
33480 #define XCVR_RMW_PLL_HP_MOD_CTRL(base, mask, value) (XCVR_WR_PLL_HP_MOD_CTRL(base, (XCVR_RD_PLL_HP_MOD_CTRL(base) & ~(mask)) | (value)))
33481 #define XCVR_SET_PLL_HP_MOD_CTRL(base, value) (BME_OR32(&XCVR_PLL_HP_MOD_CTRL_REG(base), (uint32_t)(value)))
33482 #define XCVR_CLR_PLL_HP_MOD_CTRL(base, value) (BME_AND32(&XCVR_PLL_HP_MOD_CTRL_REG(base), (uint32_t)(~(value))))
33483 #define XCVR_TOG_PLL_HP_MOD_CTRL(base, value) (BME_XOR32(&XCVR_PLL_HP_MOD_CTRL_REG(base), (uint32_t)(value)))
33484 /*@}*/
33485 
33486 /*
33487  * Constants & macros for individual XCVR_PLL_HP_MOD_CTRL bitfields
33488  */
33489 
33490 /*!
33491  * @name Register XCVR_PLL_HP_MOD_CTRL, field HPM_SDM_MANUAL[9:0] (RW)
33492  *
33493  * If HP_SDM_DIS is set, this register is the value that is applied as the
33494  * Numerator to the High Port SDM.
33495  */
33496 /*@{*/
33497 /*! @brief Read current value of the XCVR_PLL_HP_MOD_CTRL_HPM_SDM_MANUAL field. */
33498 #define XCVR_RD_PLL_HP_MOD_CTRL_HPM_SDM_MANUAL(base) ((XCVR_PLL_HP_MOD_CTRL_REG(base) & XCVR_PLL_HP_MOD_CTRL_HPM_SDM_MANUAL_MASK) >> XCVR_PLL_HP_MOD_CTRL_HPM_SDM_MANUAL_SHIFT)
33499 #define XCVR_BRD_PLL_HP_MOD_CTRL_HPM_SDM_MANUAL(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR_PLL_HP_MOD_CTRL_HPM_SDM_MANUAL_SHIFT, XCVR_PLL_HP_MOD_CTRL_HPM_SDM_MANUAL_WIDTH))
33500 
33501 /*! @brief Set the HPM_SDM_MANUAL field to a new value. */
33502 #define XCVR_WR_PLL_HP_MOD_CTRL_HPM_SDM_MANUAL(base, value) (XCVR_RMW_PLL_HP_MOD_CTRL(base, (XCVR_PLL_HP_MOD_CTRL_HPM_SDM_MANUAL_MASK | XCVR_PLL_HP_MOD_CTRL_HPFF_MASK), XCVR_PLL_HP_MOD_CTRL_HPM_SDM_MANUAL(value)))
33503 #define XCVR_BWR_PLL_HP_MOD_CTRL_HPM_SDM_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_HP_MOD_CTRL_HPM_SDM_MANUAL_SHIFT), XCVR_PLL_HP_MOD_CTRL_HPM_SDM_MANUAL_SHIFT, XCVR_PLL_HP_MOD_CTRL_HPM_SDM_MANUAL_WIDTH))
33504 /*@}*/
33505 
33506 /*!
33507  * @name Register XCVR_PLL_HP_MOD_CTRL, field HPFF[13] (W1C)
33508  *
33509  * This bit is set if the High Port Sigma Delta Modulator output is invalid due
33510  * to an error in the Fraction applied, and this bit is cleared by writing a 1 to
33511  * it.
33512  */
33513 /*@{*/
33514 /*! @brief Read current value of the XCVR_PLL_HP_MOD_CTRL_HPFF field. */
33515 #define XCVR_RD_PLL_HP_MOD_CTRL_HPFF(base) ((XCVR_PLL_HP_MOD_CTRL_REG(base) & XCVR_PLL_HP_MOD_CTRL_HPFF_MASK) >> XCVR_PLL_HP_MOD_CTRL_HPFF_SHIFT)
33516 #define XCVR_BRD_PLL_HP_MOD_CTRL_HPFF(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR_PLL_HP_MOD_CTRL_HPFF_SHIFT, XCVR_PLL_HP_MOD_CTRL_HPFF_WIDTH))
33517 
33518 /*! @brief Set the HPFF field to a new value. */
33519 #define XCVR_WR_PLL_HP_MOD_CTRL_HPFF(base, value) (XCVR_RMW_PLL_HP_MOD_CTRL(base, XCVR_PLL_HP_MOD_CTRL_HPFF_MASK, XCVR_PLL_HP_MOD_CTRL_HPFF(value)))
33520 #define XCVR_BWR_PLL_HP_MOD_CTRL_HPFF(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_HP_MOD_CTRL_HPFF_SHIFT), XCVR_PLL_HP_MOD_CTRL_HPFF_SHIFT, XCVR_PLL_HP_MOD_CTRL_HPFF_WIDTH))
33521 /*@}*/
33522 
33523 /*!
33524  * @name Register XCVR_PLL_HP_MOD_CTRL, field HP_SDM_INV[14] (RW)
33525  *
33526  * If this bit is set the High Port LSB Fractional Word, including any
33527  * Dithering, will be Inverted before it is applied to the High Port Sigma Delta Modulator.
33528  */
33529 /*@{*/
33530 /*! @brief Read current value of the XCVR_PLL_HP_MOD_CTRL_HP_SDM_INV field. */
33531 #define XCVR_RD_PLL_HP_MOD_CTRL_HP_SDM_INV(base) ((XCVR_PLL_HP_MOD_CTRL_REG(base) & XCVR_PLL_HP_MOD_CTRL_HP_SDM_INV_MASK) >> XCVR_PLL_HP_MOD_CTRL_HP_SDM_INV_SHIFT)
33532 #define XCVR_BRD_PLL_HP_MOD_CTRL_HP_SDM_INV(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR_PLL_HP_MOD_CTRL_HP_SDM_INV_SHIFT, XCVR_PLL_HP_MOD_CTRL_HP_SDM_INV_WIDTH))
33533 
33534 /*! @brief Set the HP_SDM_INV field to a new value. */
33535 #define XCVR_WR_PLL_HP_MOD_CTRL_HP_SDM_INV(base, value) (XCVR_RMW_PLL_HP_MOD_CTRL(base, (XCVR_PLL_HP_MOD_CTRL_HP_SDM_INV_MASK | XCVR_PLL_HP_MOD_CTRL_HPFF_MASK), XCVR_PLL_HP_MOD_CTRL_HP_SDM_INV(value)))
33536 #define XCVR_BWR_PLL_HP_MOD_CTRL_HP_SDM_INV(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_HP_MOD_CTRL_HP_SDM_INV_SHIFT), XCVR_PLL_HP_MOD_CTRL_HP_SDM_INV_SHIFT, XCVR_PLL_HP_MOD_CTRL_HP_SDM_INV_WIDTH))
33537 /*@}*/
33538 
33539 /*!
33540  * @name Register XCVR_PLL_HP_MOD_CTRL, field HP_SDM_DIS[15] (RW)
33541  *
33542  * If this bit is set, the High Port Modulation to the HP SDM is disabled, and
33543  * the HP SDM Numerator comes from the HPM_SDM_MANUAL register.
33544  */
33545 /*@{*/
33546 /*! @brief Read current value of the XCVR_PLL_HP_MOD_CTRL_HP_SDM_DIS field. */
33547 #define XCVR_RD_PLL_HP_MOD_CTRL_HP_SDM_DIS(base) ((XCVR_PLL_HP_MOD_CTRL_REG(base) & XCVR_PLL_HP_MOD_CTRL_HP_SDM_DIS_MASK) >> XCVR_PLL_HP_MOD_CTRL_HP_SDM_DIS_SHIFT)
33548 #define XCVR_BRD_PLL_HP_MOD_CTRL_HP_SDM_DIS(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR_PLL_HP_MOD_CTRL_HP_SDM_DIS_SHIFT, XCVR_PLL_HP_MOD_CTRL_HP_SDM_DIS_WIDTH))
33549 
33550 /*! @brief Set the HP_SDM_DIS field to a new value. */
33551 #define XCVR_WR_PLL_HP_MOD_CTRL_HP_SDM_DIS(base, value) (XCVR_RMW_PLL_HP_MOD_CTRL(base, (XCVR_PLL_HP_MOD_CTRL_HP_SDM_DIS_MASK | XCVR_PLL_HP_MOD_CTRL_HPFF_MASK), XCVR_PLL_HP_MOD_CTRL_HP_SDM_DIS(value)))
33552 #define XCVR_BWR_PLL_HP_MOD_CTRL_HP_SDM_DIS(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_HP_MOD_CTRL_HP_SDM_DIS_SHIFT), XCVR_PLL_HP_MOD_CTRL_HP_SDM_DIS_SHIFT, XCVR_PLL_HP_MOD_CTRL_HP_SDM_DIS_WIDTH))
33553 /*@}*/
33554 
33555 /*!
33556  * @name Register XCVR_PLL_HP_MOD_CTRL, field HPM_LFSR_LEN[18:16] (RW)
33557  *
33558  * This register selects the length of the HPM LFSR and the associated LFSR Tap
33559  * Mask
33560  *
33561  * Values:
33562  * - 0b000 - LFSR 9, tap mask 100010000
33563  * - 0b001 - LFSR 10, tap mask 1001000000
33564  * - 0b010 - LFSR 11, tap mask 11101000000
33565  * - 0b011 - LFSR 13, tap mask 1101100000000
33566  * - 0b100 - LFSR 15, tap mask 111010000000000
33567  * - 0b101 - LFSR 17, tap mask 11110000000000000
33568  * - 0b110 - Reserved
33569  * - 0b111 - Reserved
33570  */
33571 /*@{*/
33572 /*! @brief Read current value of the XCVR_PLL_HP_MOD_CTRL_HPM_LFSR_LEN field. */
33573 #define XCVR_RD_PLL_HP_MOD_CTRL_HPM_LFSR_LEN(base) ((XCVR_PLL_HP_MOD_CTRL_REG(base) & XCVR_PLL_HP_MOD_CTRL_HPM_LFSR_LEN_MASK) >> XCVR_PLL_HP_MOD_CTRL_HPM_LFSR_LEN_SHIFT)
33574 #define XCVR_BRD_PLL_HP_MOD_CTRL_HPM_LFSR_LEN(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR_PLL_HP_MOD_CTRL_HPM_LFSR_LEN_SHIFT, XCVR_PLL_HP_MOD_CTRL_HPM_LFSR_LEN_WIDTH))
33575 
33576 /*! @brief Set the HPM_LFSR_LEN field to a new value. */
33577 #define XCVR_WR_PLL_HP_MOD_CTRL_HPM_LFSR_LEN(base, value) (XCVR_RMW_PLL_HP_MOD_CTRL(base, (XCVR_PLL_HP_MOD_CTRL_HPM_LFSR_LEN_MASK | XCVR_PLL_HP_MOD_CTRL_HPFF_MASK), XCVR_PLL_HP_MOD_CTRL_HPM_LFSR_LEN(value)))
33578 #define XCVR_BWR_PLL_HP_MOD_CTRL_HPM_LFSR_LEN(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_HP_MOD_CTRL_HPM_LFSR_LEN_SHIFT), XCVR_PLL_HP_MOD_CTRL_HPM_LFSR_LEN_SHIFT, XCVR_PLL_HP_MOD_CTRL_HPM_LFSR_LEN_WIDTH))
33579 /*@}*/
33580 
33581 /*!
33582  * @name Register XCVR_PLL_HP_MOD_CTRL, field HP_DTH_SCL[20] (RW)
33583  *
33584  * If this bit is set, the LFSR dithering of the High Port LSB Fractional Word
33585  * will be multiplied by 2.
33586  */
33587 /*@{*/
33588 /*! @brief Read current value of the XCVR_PLL_HP_MOD_CTRL_HP_DTH_SCL field. */
33589 #define XCVR_RD_PLL_HP_MOD_CTRL_HP_DTH_SCL(base) ((XCVR_PLL_HP_MOD_CTRL_REG(base) & XCVR_PLL_HP_MOD_CTRL_HP_DTH_SCL_MASK) >> XCVR_PLL_HP_MOD_CTRL_HP_DTH_SCL_SHIFT)
33590 #define XCVR_BRD_PLL_HP_MOD_CTRL_HP_DTH_SCL(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR_PLL_HP_MOD_CTRL_HP_DTH_SCL_SHIFT, XCVR_PLL_HP_MOD_CTRL_HP_DTH_SCL_WIDTH))
33591 
33592 /*! @brief Set the HP_DTH_SCL field to a new value. */
33593 #define XCVR_WR_PLL_HP_MOD_CTRL_HP_DTH_SCL(base, value) (XCVR_RMW_PLL_HP_MOD_CTRL(base, (XCVR_PLL_HP_MOD_CTRL_HP_DTH_SCL_MASK | XCVR_PLL_HP_MOD_CTRL_HPFF_MASK), XCVR_PLL_HP_MOD_CTRL_HP_DTH_SCL(value)))
33594 #define XCVR_BWR_PLL_HP_MOD_CTRL_HP_DTH_SCL(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_HP_MOD_CTRL_HP_DTH_SCL_SHIFT), XCVR_PLL_HP_MOD_CTRL_HP_DTH_SCL_SHIFT, XCVR_PLL_HP_MOD_CTRL_HP_DTH_SCL_WIDTH))
33595 /*@}*/
33596 
33597 /*!
33598  * @name Register XCVR_PLL_HP_MOD_CTRL, field HPM_DTH_EN[23] (RW)
33599  *
33600  * If this bit is set, the High Port LSB Fractional Word will be Dithered by the
33601  * High Port LFSR before it is applied to the HP SDM.
33602  */
33603 /*@{*/
33604 /*! @brief Read current value of the XCVR_PLL_HP_MOD_CTRL_HPM_DTH_EN field. */
33605 #define XCVR_RD_PLL_HP_MOD_CTRL_HPM_DTH_EN(base) ((XCVR_PLL_HP_MOD_CTRL_REG(base) & XCVR_PLL_HP_MOD_CTRL_HPM_DTH_EN_MASK) >> XCVR_PLL_HP_MOD_CTRL_HPM_DTH_EN_SHIFT)
33606 #define XCVR_BRD_PLL_HP_MOD_CTRL_HPM_DTH_EN(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR_PLL_HP_MOD_CTRL_HPM_DTH_EN_SHIFT, XCVR_PLL_HP_MOD_CTRL_HPM_DTH_EN_WIDTH))
33607 
33608 /*! @brief Set the HPM_DTH_EN field to a new value. */
33609 #define XCVR_WR_PLL_HP_MOD_CTRL_HPM_DTH_EN(base, value) (XCVR_RMW_PLL_HP_MOD_CTRL(base, (XCVR_PLL_HP_MOD_CTRL_HPM_DTH_EN_MASK | XCVR_PLL_HP_MOD_CTRL_HPFF_MASK), XCVR_PLL_HP_MOD_CTRL_HPM_DTH_EN(value)))
33610 #define XCVR_BWR_PLL_HP_MOD_CTRL_HPM_DTH_EN(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_HP_MOD_CTRL_HPM_DTH_EN_SHIFT), XCVR_PLL_HP_MOD_CTRL_HPM_DTH_EN_SHIFT, XCVR_PLL_HP_MOD_CTRL_HPM_DTH_EN_WIDTH))
33611 /*@}*/
33612 
33613 /*!
33614  * @name Register XCVR_PLL_HP_MOD_CTRL, field HPM_SCALE[25:24] (RW)
33615  *
33616  * This register controls the scaling of the High Port Modulation Integer Value
33617  * applied to the VCO High Port Bank.
33618  *
33619  * Values:
33620  * - 0b00 - No Scaling
33621  * - 0b01 - Multiply by 2
33622  * - 0b10 - Divide by 2
33623  * - 0b11 - Reserved
33624  */
33625 /*@{*/
33626 /*! @brief Read current value of the XCVR_PLL_HP_MOD_CTRL_HPM_SCALE field. */
33627 #define XCVR_RD_PLL_HP_MOD_CTRL_HPM_SCALE(base) ((XCVR_PLL_HP_MOD_CTRL_REG(base) & XCVR_PLL_HP_MOD_CTRL_HPM_SCALE_MASK) >> XCVR_PLL_HP_MOD_CTRL_HPM_SCALE_SHIFT)
33628 #define XCVR_BRD_PLL_HP_MOD_CTRL_HPM_SCALE(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR_PLL_HP_MOD_CTRL_HPM_SCALE_SHIFT, XCVR_PLL_HP_MOD_CTRL_HPM_SCALE_WIDTH))
33629 
33630 /*! @brief Set the HPM_SCALE field to a new value. */
33631 #define XCVR_WR_PLL_HP_MOD_CTRL_HPM_SCALE(base, value) (XCVR_RMW_PLL_HP_MOD_CTRL(base, (XCVR_PLL_HP_MOD_CTRL_HPM_SCALE_MASK | XCVR_PLL_HP_MOD_CTRL_HPFF_MASK), XCVR_PLL_HP_MOD_CTRL_HPM_SCALE(value)))
33632 #define XCVR_BWR_PLL_HP_MOD_CTRL_HPM_SCALE(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_HP_MOD_CTRL_HPM_SCALE_SHIFT), XCVR_PLL_HP_MOD_CTRL_HPM_SCALE_SHIFT, XCVR_PLL_HP_MOD_CTRL_HPM_SCALE_WIDTH))
33633 /*@}*/
33634 
33635 /*!
33636  * @name Register XCVR_PLL_HP_MOD_CTRL, field HP_MOD_INV[31] (RW)
33637  *
33638  * If this bit is set, the Baseband Frequency Word will be Inverted before
33639  * Scaling and Dithering, and then applied to the High Port Bank and the High Port
33640  * Sigma Delta Modulator of the HP LSB. Note that the High Port SDM has it's own,
33641  * additional, inversion bit.
33642  */
33643 /*@{*/
33644 /*! @brief Read current value of the XCVR_PLL_HP_MOD_CTRL_HP_MOD_INV field. */
33645 #define XCVR_RD_PLL_HP_MOD_CTRL_HP_MOD_INV(base) ((XCVR_PLL_HP_MOD_CTRL_REG(base) & XCVR_PLL_HP_MOD_CTRL_HP_MOD_INV_MASK) >> XCVR_PLL_HP_MOD_CTRL_HP_MOD_INV_SHIFT)
33646 #define XCVR_BRD_PLL_HP_MOD_CTRL_HP_MOD_INV(base) (BME_UBFX32(&XCVR_PLL_HP_MOD_CTRL_REG(base), XCVR_PLL_HP_MOD_CTRL_HP_MOD_INV_SHIFT, XCVR_PLL_HP_MOD_CTRL_HP_MOD_INV_WIDTH))
33647 
33648 /*! @brief Set the HP_MOD_INV field to a new value. */
33649 #define XCVR_WR_PLL_HP_MOD_CTRL_HP_MOD_INV(base, value) (XCVR_RMW_PLL_HP_MOD_CTRL(base, (XCVR_PLL_HP_MOD_CTRL_HP_MOD_INV_MASK | XCVR_PLL_HP_MOD_CTRL_HPFF_MASK), XCVR_PLL_HP_MOD_CTRL_HP_MOD_INV(value)))
33650 #define XCVR_BWR_PLL_HP_MOD_CTRL_HP_MOD_INV(base, value) (BME_BFI32(&XCVR_PLL_HP_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_HP_MOD_CTRL_HP_MOD_INV_SHIFT), XCVR_PLL_HP_MOD_CTRL_HP_MOD_INV_SHIFT, XCVR_PLL_HP_MOD_CTRL_HP_MOD_INV_WIDTH))
33651 /*@}*/
33652 
33653 /*******************************************************************************
33654  * XCVR_PLL_HPM_CAL_CTRL - PLL HPM Calibration Control
33655  ******************************************************************************/
33656 
33657 /*!
33658  * @brief XCVR_PLL_HPM_CAL_CTRL - PLL HPM Calibration Control (RW)
33659  *
33660  * Reset value: 0x400002A2U
33661  */
33662 /*!
33663  * @name Constants and macros for entire XCVR_PLL_HPM_CAL_CTRL register
33664  */
33665 /*@{*/
33666 #define XCVR_RD_PLL_HPM_CAL_CTRL(base) (XCVR_PLL_HPM_CAL_CTRL_REG(base))
33667 #define XCVR_WR_PLL_HPM_CAL_CTRL(base, value) (XCVR_PLL_HPM_CAL_CTRL_REG(base) = (value))
33668 #define XCVR_RMW_PLL_HPM_CAL_CTRL(base, mask, value) (XCVR_WR_PLL_HPM_CAL_CTRL(base, (XCVR_RD_PLL_HPM_CAL_CTRL(base) & ~(mask)) | (value)))
33669 #define XCVR_SET_PLL_HPM_CAL_CTRL(base, value) (BME_OR32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), (uint32_t)(value)))
33670 #define XCVR_CLR_PLL_HPM_CAL_CTRL(base, value) (BME_AND32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), (uint32_t)(~(value))))
33671 #define XCVR_TOG_PLL_HPM_CAL_CTRL(base, value) (BME_XOR32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), (uint32_t)(value)))
33672 /*@}*/
33673 
33674 /*
33675  * Constants & macros for individual XCVR_PLL_HPM_CAL_CTRL bitfields
33676  */
33677 
33678 /*!
33679  * @name Register XCVR_PLL_HPM_CAL_CTRL, field HPM_CAL_FACTOR[12:0] (RO)
33680  *
33681  * This is the value currently being used by High Port Modulation Multiplier.
33682  */
33683 /*@{*/
33684 /*! @brief Read current value of the XCVR_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR field. */
33685 #define XCVR_RD_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR(base) ((XCVR_PLL_HPM_CAL_CTRL_REG(base) & XCVR_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_MASK) >> XCVR_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_SHIFT)
33686 #define XCVR_BRD_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR(base) (BME_UBFX32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), XCVR_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_SHIFT, XCVR_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_WIDTH))
33687 /*@}*/
33688 
33689 /*!
33690  * @name Register XCVR_PLL_HPM_CAL_CTRL, field HP_CAL_DIS[15] (RW)
33691  *
33692  * If this bit is set, the lookup table value for the HPM Calibration Factor is
33693  * overridden by the HPM_CAL_FACTOR_MANUAL register.
33694  */
33695 /*@{*/
33696 /*! @brief Read current value of the XCVR_PLL_HPM_CAL_CTRL_HP_CAL_DIS field. */
33697 #define XCVR_RD_PLL_HPM_CAL_CTRL_HP_CAL_DIS(base) ((XCVR_PLL_HPM_CAL_CTRL_REG(base) & XCVR_PLL_HPM_CAL_CTRL_HP_CAL_DIS_MASK) >> XCVR_PLL_HPM_CAL_CTRL_HP_CAL_DIS_SHIFT)
33698 #define XCVR_BRD_PLL_HPM_CAL_CTRL_HP_CAL_DIS(base) (BME_UBFX32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), XCVR_PLL_HPM_CAL_CTRL_HP_CAL_DIS_SHIFT, XCVR_PLL_HPM_CAL_CTRL_HP_CAL_DIS_WIDTH))
33699 
33700 /*! @brief Set the HP_CAL_DIS field to a new value. */
33701 #define XCVR_WR_PLL_HPM_CAL_CTRL_HP_CAL_DIS(base, value) (XCVR_RMW_PLL_HPM_CAL_CTRL(base, XCVR_PLL_HPM_CAL_CTRL_HP_CAL_DIS_MASK, XCVR_PLL_HPM_CAL_CTRL_HP_CAL_DIS(value)))
33702 #define XCVR_BWR_PLL_HPM_CAL_CTRL_HP_CAL_DIS(base, value) (BME_BFI32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_HPM_CAL_CTRL_HP_CAL_DIS_SHIFT), XCVR_PLL_HPM_CAL_CTRL_HP_CAL_DIS_SHIFT, XCVR_PLL_HPM_CAL_CTRL_HP_CAL_DIS_WIDTH))
33703 /*@}*/
33704 
33705 /*!
33706  * @name Register XCVR_PLL_HPM_CAL_CTRL, field HPM_CAL_FACTOR_MANUAL[28:16] (RW)
33707  *
33708  * If HP_CAL_DIS is set, this register is the unsigned 13 bit value used by the
33709  * HPM Multiplier, the maximum useable value is decimal 6400.
33710  */
33711 /*@{*/
33712 /*! @brief Read current value of the XCVR_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_MANUAL field. */
33713 #define XCVR_RD_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_MANUAL(base) ((XCVR_PLL_HPM_CAL_CTRL_REG(base) & XCVR_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_MANUAL_MASK) >> XCVR_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_MANUAL_SHIFT)
33714 #define XCVR_BRD_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_MANUAL(base) (BME_UBFX32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), XCVR_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_MANUAL_SHIFT, XCVR_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_MANUAL_WIDTH))
33715 
33716 /*! @brief Set the HPM_CAL_FACTOR_MANUAL field to a new value. */
33717 #define XCVR_WR_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_MANUAL(base, value) (XCVR_RMW_PLL_HPM_CAL_CTRL(base, XCVR_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_MANUAL_MASK, XCVR_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_MANUAL(value)))
33718 #define XCVR_BWR_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_MANUAL_SHIFT), XCVR_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_MANUAL_SHIFT, XCVR_PLL_HPM_CAL_CTRL_HPM_CAL_FACTOR_MANUAL_WIDTH))
33719 /*@}*/
33720 
33721 /*!
33722  * @name Register XCVR_PLL_HPM_CAL_CTRL, field HP_CAL_ARY[30] (RW)
33723  *
33724  * This bit selects the size of the array to be used by the math implemented in
33725  * the HPM Calibration Factor lookup table.
33726  *
33727  * Values:
33728  * - 0b0 - 128
33729  * - 0b1 - 256
33730  */
33731 /*@{*/
33732 /*! @brief Read current value of the XCVR_PLL_HPM_CAL_CTRL_HP_CAL_ARY field. */
33733 #define XCVR_RD_PLL_HPM_CAL_CTRL_HP_CAL_ARY(base) ((XCVR_PLL_HPM_CAL_CTRL_REG(base) & XCVR_PLL_HPM_CAL_CTRL_HP_CAL_ARY_MASK) >> XCVR_PLL_HPM_CAL_CTRL_HP_CAL_ARY_SHIFT)
33734 #define XCVR_BRD_PLL_HPM_CAL_CTRL_HP_CAL_ARY(base) (BME_UBFX32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), XCVR_PLL_HPM_CAL_CTRL_HP_CAL_ARY_SHIFT, XCVR_PLL_HPM_CAL_CTRL_HP_CAL_ARY_WIDTH))
33735 
33736 /*! @brief Set the HP_CAL_ARY field to a new value. */
33737 #define XCVR_WR_PLL_HPM_CAL_CTRL_HP_CAL_ARY(base, value) (XCVR_RMW_PLL_HPM_CAL_CTRL(base, XCVR_PLL_HPM_CAL_CTRL_HP_CAL_ARY_MASK, XCVR_PLL_HPM_CAL_CTRL_HP_CAL_ARY(value)))
33738 #define XCVR_BWR_PLL_HPM_CAL_CTRL_HP_CAL_ARY(base, value) (BME_BFI32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_HPM_CAL_CTRL_HP_CAL_ARY_SHIFT), XCVR_PLL_HPM_CAL_CTRL_HP_CAL_ARY_SHIFT, XCVR_PLL_HPM_CAL_CTRL_HP_CAL_ARY_WIDTH))
33739 /*@}*/
33740 
33741 /*!
33742  * @name Register XCVR_PLL_HPM_CAL_CTRL, field HP_CAL_TIME[31] (RW)
33743  *
33744  * This bit selects the length of time to count during HPM Calibration and is
33745  * used by the math implemented in the HPM Calibration Factor lookup table.
33746  *
33747  * Values:
33748  * - 0b0 - 25 us
33749  * - 0b1 - 50 us
33750  */
33751 /*@{*/
33752 /*! @brief Read current value of the XCVR_PLL_HPM_CAL_CTRL_HP_CAL_TIME field. */
33753 #define XCVR_RD_PLL_HPM_CAL_CTRL_HP_CAL_TIME(base) ((XCVR_PLL_HPM_CAL_CTRL_REG(base) & XCVR_PLL_HPM_CAL_CTRL_HP_CAL_TIME_MASK) >> XCVR_PLL_HPM_CAL_CTRL_HP_CAL_TIME_SHIFT)
33754 #define XCVR_BRD_PLL_HPM_CAL_CTRL_HP_CAL_TIME(base) (BME_UBFX32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), XCVR_PLL_HPM_CAL_CTRL_HP_CAL_TIME_SHIFT, XCVR_PLL_HPM_CAL_CTRL_HP_CAL_TIME_WIDTH))
33755 
33756 /*! @brief Set the HP_CAL_TIME field to a new value. */
33757 #define XCVR_WR_PLL_HPM_CAL_CTRL_HP_CAL_TIME(base, value) (XCVR_RMW_PLL_HPM_CAL_CTRL(base, XCVR_PLL_HPM_CAL_CTRL_HP_CAL_TIME_MASK, XCVR_PLL_HPM_CAL_CTRL_HP_CAL_TIME(value)))
33758 #define XCVR_BWR_PLL_HPM_CAL_CTRL_HP_CAL_TIME(base, value) (BME_BFI32(&XCVR_PLL_HPM_CAL_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_HPM_CAL_CTRL_HP_CAL_TIME_SHIFT), XCVR_PLL_HPM_CAL_CTRL_HP_CAL_TIME_SHIFT, XCVR_PLL_HPM_CAL_CTRL_HP_CAL_TIME_WIDTH))
33759 /*@}*/
33760 
33761 /*******************************************************************************
33762  * XCVR_PLL_LD_HPM_CAL1 - PLL Cycle Slip Lock Detect Configuration and HPM Calibration 1
33763  ******************************************************************************/
33764 
33765 /*!
33766  * @brief XCVR_PLL_LD_HPM_CAL1 - PLL Cycle Slip Lock Detect Configuration and HPM Calibration 1 (RW)
33767  *
33768  * Reset value: 0x44300000U
33769  */
33770 /*!
33771  * @name Constants and macros for entire XCVR_PLL_LD_HPM_CAL1 register
33772  */
33773 /*@{*/
33774 #define XCVR_RD_PLL_LD_HPM_CAL1(base) (XCVR_PLL_LD_HPM_CAL1_REG(base))
33775 #define XCVR_WR_PLL_LD_HPM_CAL1(base, value) (XCVR_PLL_LD_HPM_CAL1_REG(base) = (value))
33776 #define XCVR_RMW_PLL_LD_HPM_CAL1(base, mask, value) (XCVR_WR_PLL_LD_HPM_CAL1(base, (XCVR_RD_PLL_LD_HPM_CAL1(base) & ~(mask)) | (value)))
33777 #define XCVR_SET_PLL_LD_HPM_CAL1(base, value) (BME_OR32(&XCVR_PLL_LD_HPM_CAL1_REG(base), (uint32_t)(value)))
33778 #define XCVR_CLR_PLL_LD_HPM_CAL1(base, value) (BME_AND32(&XCVR_PLL_LD_HPM_CAL1_REG(base), (uint32_t)(~(value))))
33779 #define XCVR_TOG_PLL_LD_HPM_CAL1(base, value) (BME_XOR32(&XCVR_PLL_LD_HPM_CAL1_REG(base), (uint32_t)(value)))
33780 /*@}*/
33781 
33782 /*
33783  * Constants & macros for individual XCVR_PLL_LD_HPM_CAL1 bitfields
33784  */
33785 
33786 /*!
33787  * @name Register XCVR_PLL_LD_HPM_CAL1, field CNT_1[16:0] (RO)
33788  *
33789  * This is the Ripple counter value used for HPM Cal 1.
33790  */
33791 /*@{*/
33792 /*! @brief Read current value of the XCVR_PLL_LD_HPM_CAL1_CNT_1 field. */
33793 #define XCVR_RD_PLL_LD_HPM_CAL1_CNT_1(base) ((XCVR_PLL_LD_HPM_CAL1_REG(base) & XCVR_PLL_LD_HPM_CAL1_CNT_1_MASK) >> XCVR_PLL_LD_HPM_CAL1_CNT_1_SHIFT)
33794 #define XCVR_BRD_PLL_LD_HPM_CAL1_CNT_1(base) (XCVR_RD_PLL_LD_HPM_CAL1_CNT_1(base))
33795 /*@}*/
33796 
33797 /*!
33798  * @name Register XCVR_PLL_LD_HPM_CAL1, field CS_WT[22:20] (RW)
33799  *
33800  * This register sets the time to wait before restarting a Cycle Slip Search if
33801  * CS_RC, Cycle Slip Recycle, is set.
33802  *
33803  * Values:
33804  * - 0b000 - 128 us
33805  * - 0b001 - 256 us
33806  * - 0b010 - 384 us
33807  * - 0b011 - 512 us
33808  * - 0b100 - 640 us
33809  * - 0b101 - 768 us
33810  * - 0b110 - 896 us
33811  * - 0b111 - 1024 us
33812  */
33813 /*@{*/
33814 /*! @brief Read current value of the XCVR_PLL_LD_HPM_CAL1_CS_WT field. */
33815 #define XCVR_RD_PLL_LD_HPM_CAL1_CS_WT(base) ((XCVR_PLL_LD_HPM_CAL1_REG(base) & XCVR_PLL_LD_HPM_CAL1_CS_WT_MASK) >> XCVR_PLL_LD_HPM_CAL1_CS_WT_SHIFT)
33816 #define XCVR_BRD_PLL_LD_HPM_CAL1_CS_WT(base) (BME_UBFX32(&XCVR_PLL_LD_HPM_CAL1_REG(base), XCVR_PLL_LD_HPM_CAL1_CS_WT_SHIFT, XCVR_PLL_LD_HPM_CAL1_CS_WT_WIDTH))
33817 
33818 /*! @brief Set the CS_WT field to a new value. */
33819 #define XCVR_WR_PLL_LD_HPM_CAL1_CS_WT(base, value) (XCVR_RMW_PLL_LD_HPM_CAL1(base, XCVR_PLL_LD_HPM_CAL1_CS_WT_MASK, XCVR_PLL_LD_HPM_CAL1_CS_WT(value)))
33820 #define XCVR_BWR_PLL_LD_HPM_CAL1_CS_WT(base, value) (BME_BFI32(&XCVR_PLL_LD_HPM_CAL1_REG(base), ((uint32_t)(value) << XCVR_PLL_LD_HPM_CAL1_CS_WT_SHIFT), XCVR_PLL_LD_HPM_CAL1_CS_WT_SHIFT, XCVR_PLL_LD_HPM_CAL1_CS_WT_WIDTH))
33821 /*@}*/
33822 
33823 /*!
33824  * @name Register XCVR_PLL_LD_HPM_CAL1, field CS_FW[26:24] (RW)
33825  *
33826  * This register sets the window time for capturing Cycle Slip Flags before
33827  * shutting down.
33828  *
33829  * Values:
33830  * - 0b000 - 8 us
33831  * - 0b001 - 16 us
33832  * - 0b010 - 24 us
33833  * - 0b011 - 32 us
33834  * - 0b100 - 64 us
33835  * - 0b101 - 96 us
33836  * - 0b110 - 128 us
33837  * - 0b111 - 256 us
33838  */
33839 /*@{*/
33840 /*! @brief Read current value of the XCVR_PLL_LD_HPM_CAL1_CS_FW field. */
33841 #define XCVR_RD_PLL_LD_HPM_CAL1_CS_FW(base) ((XCVR_PLL_LD_HPM_CAL1_REG(base) & XCVR_PLL_LD_HPM_CAL1_CS_FW_MASK) >> XCVR_PLL_LD_HPM_CAL1_CS_FW_SHIFT)
33842 #define XCVR_BRD_PLL_LD_HPM_CAL1_CS_FW(base) (BME_UBFX32(&XCVR_PLL_LD_HPM_CAL1_REG(base), XCVR_PLL_LD_HPM_CAL1_CS_FW_SHIFT, XCVR_PLL_LD_HPM_CAL1_CS_FW_WIDTH))
33843 
33844 /*! @brief Set the CS_FW field to a new value. */
33845 #define XCVR_WR_PLL_LD_HPM_CAL1_CS_FW(base, value) (XCVR_RMW_PLL_LD_HPM_CAL1(base, XCVR_PLL_LD_HPM_CAL1_CS_FW_MASK, XCVR_PLL_LD_HPM_CAL1_CS_FW(value)))
33846 #define XCVR_BWR_PLL_LD_HPM_CAL1_CS_FW(base, value) (BME_BFI32(&XCVR_PLL_LD_HPM_CAL1_REG(base), ((uint32_t)(value) << XCVR_PLL_LD_HPM_CAL1_CS_FW_SHIFT), XCVR_PLL_LD_HPM_CAL1_CS_FW_SHIFT, XCVR_PLL_LD_HPM_CAL1_CS_FW_WIDTH))
33847 /*@}*/
33848 
33849 /*!
33850  * @name Register XCVR_PLL_LD_HPM_CAL1, field CS_FCNT[31:28] (RW)
33851  *
33852  * This register value is the maximum number of Cycle Slip Flags that can be
33853  * counted before the CS_FAIL is set.
33854  */
33855 /*@{*/
33856 /*! @brief Read current value of the XCVR_PLL_LD_HPM_CAL1_CS_FCNT field. */
33857 #define XCVR_RD_PLL_LD_HPM_CAL1_CS_FCNT(base) ((XCVR_PLL_LD_HPM_CAL1_REG(base) & XCVR_PLL_LD_HPM_CAL1_CS_FCNT_MASK) >> XCVR_PLL_LD_HPM_CAL1_CS_FCNT_SHIFT)
33858 #define XCVR_BRD_PLL_LD_HPM_CAL1_CS_FCNT(base) (BME_UBFX32(&XCVR_PLL_LD_HPM_CAL1_REG(base), XCVR_PLL_LD_HPM_CAL1_CS_FCNT_SHIFT, XCVR_PLL_LD_HPM_CAL1_CS_FCNT_WIDTH))
33859 
33860 /*! @brief Set the CS_FCNT field to a new value. */
33861 #define XCVR_WR_PLL_LD_HPM_CAL1_CS_FCNT(base, value) (XCVR_RMW_PLL_LD_HPM_CAL1(base, XCVR_PLL_LD_HPM_CAL1_CS_FCNT_MASK, XCVR_PLL_LD_HPM_CAL1_CS_FCNT(value)))
33862 #define XCVR_BWR_PLL_LD_HPM_CAL1_CS_FCNT(base, value) (BME_BFI32(&XCVR_PLL_LD_HPM_CAL1_REG(base), ((uint32_t)(value) << XCVR_PLL_LD_HPM_CAL1_CS_FCNT_SHIFT), XCVR_PLL_LD_HPM_CAL1_CS_FCNT_SHIFT, XCVR_PLL_LD_HPM_CAL1_CS_FCNT_WIDTH))
33863 /*@}*/
33864 
33865 /*******************************************************************************
33866  * XCVR_PLL_LD_HPM_CAL2 - PLL Cycle Slip Lock Detect Configuration and HPM Calibration 2
33867  ******************************************************************************/
33868 
33869 /*!
33870  * @brief XCVR_PLL_LD_HPM_CAL2 - PLL Cycle Slip Lock Detect Configuration and HPM Calibration 2 (RW)
33871  *
33872  * Reset value: 0x02100000U
33873  */
33874 /*!
33875  * @name Constants and macros for entire XCVR_PLL_LD_HPM_CAL2 register
33876  */
33877 /*@{*/
33878 #define XCVR_RD_PLL_LD_HPM_CAL2(base) (XCVR_PLL_LD_HPM_CAL2_REG(base))
33879 #define XCVR_WR_PLL_LD_HPM_CAL2(base, value) (XCVR_PLL_LD_HPM_CAL2_REG(base) = (value))
33880 #define XCVR_RMW_PLL_LD_HPM_CAL2(base, mask, value) (XCVR_WR_PLL_LD_HPM_CAL2(base, (XCVR_RD_PLL_LD_HPM_CAL2(base) & ~(mask)) | (value)))
33881 #define XCVR_SET_PLL_LD_HPM_CAL2(base, value) (BME_OR32(&XCVR_PLL_LD_HPM_CAL2_REG(base), (uint32_t)(value)))
33882 #define XCVR_CLR_PLL_LD_HPM_CAL2(base, value) (BME_AND32(&XCVR_PLL_LD_HPM_CAL2_REG(base), (uint32_t)(~(value))))
33883 #define XCVR_TOG_PLL_LD_HPM_CAL2(base, value) (BME_XOR32(&XCVR_PLL_LD_HPM_CAL2_REG(base), (uint32_t)(value)))
33884 /*@}*/
33885 
33886 /*
33887  * Constants & macros for individual XCVR_PLL_LD_HPM_CAL2 bitfields
33888  */
33889 
33890 /*!
33891  * @name Register XCVR_PLL_LD_HPM_CAL2, field CNT_2[16:0] (RO)
33892  *
33893  * This is the Ripple counter value used for HPM Cal 2.
33894  */
33895 /*@{*/
33896 /*! @brief Read current value of the XCVR_PLL_LD_HPM_CAL2_CNT_2 field. */
33897 #define XCVR_RD_PLL_LD_HPM_CAL2_CNT_2(base) ((XCVR_PLL_LD_HPM_CAL2_REG(base) & XCVR_PLL_LD_HPM_CAL2_CNT_2_MASK) >> XCVR_PLL_LD_HPM_CAL2_CNT_2_SHIFT)
33898 #define XCVR_BRD_PLL_LD_HPM_CAL2_CNT_2(base) (XCVR_RD_PLL_LD_HPM_CAL2_CNT_2(base))
33899 /*@}*/
33900 
33901 /*!
33902  * @name Register XCVR_PLL_LD_HPM_CAL2, field CS_RC[20] (RW)
33903  *
33904  * If this is bit is set, the Cycle Slip Lock Detector will restart after the
33905  * Cycle Slip Wait time.
33906  */
33907 /*@{*/
33908 /*! @brief Read current value of the XCVR_PLL_LD_HPM_CAL2_CS_RC field. */
33909 #define XCVR_RD_PLL_LD_HPM_CAL2_CS_RC(base) ((XCVR_PLL_LD_HPM_CAL2_REG(base) & XCVR_PLL_LD_HPM_CAL2_CS_RC_MASK) >> XCVR_PLL_LD_HPM_CAL2_CS_RC_SHIFT)
33910 #define XCVR_BRD_PLL_LD_HPM_CAL2_CS_RC(base) (BME_UBFX32(&XCVR_PLL_LD_HPM_CAL2_REG(base), XCVR_PLL_LD_HPM_CAL2_CS_RC_SHIFT, XCVR_PLL_LD_HPM_CAL2_CS_RC_WIDTH))
33911 
33912 /*! @brief Set the CS_RC field to a new value. */
33913 #define XCVR_WR_PLL_LD_HPM_CAL2_CS_RC(base, value) (XCVR_RMW_PLL_LD_HPM_CAL2(base, XCVR_PLL_LD_HPM_CAL2_CS_RC_MASK, XCVR_PLL_LD_HPM_CAL2_CS_RC(value)))
33914 #define XCVR_BWR_PLL_LD_HPM_CAL2_CS_RC(base, value) (BME_BFI32(&XCVR_PLL_LD_HPM_CAL2_REG(base), ((uint32_t)(value) << XCVR_PLL_LD_HPM_CAL2_CS_RC_SHIFT), XCVR_PLL_LD_HPM_CAL2_CS_RC_SHIFT, XCVR_PLL_LD_HPM_CAL2_CS_RC_WIDTH))
33915 /*@}*/
33916 
33917 /*!
33918  * @name Register XCVR_PLL_LD_HPM_CAL2, field CS_FT[28:24] (RW)
33919  *
33920  * This register sets the time to hold the analog cycle slip circuit in reset
33921  * after a Cycle Slip Flag, the time is a number of counts of the reference clock
33922  * equal to the value of this register.
33923  */
33924 /*@{*/
33925 /*! @brief Read current value of the XCVR_PLL_LD_HPM_CAL2_CS_FT field. */
33926 #define XCVR_RD_PLL_LD_HPM_CAL2_CS_FT(base) ((XCVR_PLL_LD_HPM_CAL2_REG(base) & XCVR_PLL_LD_HPM_CAL2_CS_FT_MASK) >> XCVR_PLL_LD_HPM_CAL2_CS_FT_SHIFT)
33927 #define XCVR_BRD_PLL_LD_HPM_CAL2_CS_FT(base) (BME_UBFX32(&XCVR_PLL_LD_HPM_CAL2_REG(base), XCVR_PLL_LD_HPM_CAL2_CS_FT_SHIFT, XCVR_PLL_LD_HPM_CAL2_CS_FT_WIDTH))
33928 
33929 /*! @brief Set the CS_FT field to a new value. */
33930 #define XCVR_WR_PLL_LD_HPM_CAL2_CS_FT(base, value) (XCVR_RMW_PLL_LD_HPM_CAL2(base, XCVR_PLL_LD_HPM_CAL2_CS_FT_MASK, XCVR_PLL_LD_HPM_CAL2_CS_FT(value)))
33931 #define XCVR_BWR_PLL_LD_HPM_CAL2_CS_FT(base, value) (BME_BFI32(&XCVR_PLL_LD_HPM_CAL2_REG(base), ((uint32_t)(value) << XCVR_PLL_LD_HPM_CAL2_CS_FT_SHIFT), XCVR_PLL_LD_HPM_CAL2_CS_FT_SHIFT, XCVR_PLL_LD_HPM_CAL2_CS_FT_WIDTH))
33932 /*@}*/
33933 
33934 /*******************************************************************************
33935  * XCVR_PLL_HPM_SDM_FRACTION - PLL HPM SDM Fraction
33936  ******************************************************************************/
33937 
33938 /*!
33939  * @brief XCVR_PLL_HPM_SDM_FRACTION - PLL HPM SDM Fraction (RW)
33940  *
33941  * Reset value: 0x01FF0000U
33942  */
33943 /*!
33944  * @name Constants and macros for entire XCVR_PLL_HPM_SDM_FRACTION register
33945  */
33946 /*@{*/
33947 #define XCVR_RD_PLL_HPM_SDM_FRACTION(base) (XCVR_PLL_HPM_SDM_FRACTION_REG(base))
33948 #define XCVR_WR_PLL_HPM_SDM_FRACTION(base, value) (XCVR_PLL_HPM_SDM_FRACTION_REG(base) = (value))
33949 #define XCVR_RMW_PLL_HPM_SDM_FRACTION(base, mask, value) (XCVR_WR_PLL_HPM_SDM_FRACTION(base, (XCVR_RD_PLL_HPM_SDM_FRACTION(base) & ~(mask)) | (value)))
33950 #define XCVR_SET_PLL_HPM_SDM_FRACTION(base, value) (BME_OR32(&XCVR_PLL_HPM_SDM_FRACTION_REG(base), (uint32_t)(value)))
33951 #define XCVR_CLR_PLL_HPM_SDM_FRACTION(base, value) (BME_AND32(&XCVR_PLL_HPM_SDM_FRACTION_REG(base), (uint32_t)(~(value))))
33952 #define XCVR_TOG_PLL_HPM_SDM_FRACTION(base, value) (BME_XOR32(&XCVR_PLL_HPM_SDM_FRACTION_REG(base), (uint32_t)(value)))
33953 /*@}*/
33954 
33955 /*
33956  * Constants & macros for individual XCVR_PLL_HPM_SDM_FRACTION bitfields
33957  */
33958 
33959 /*!
33960  * @name Register XCVR_PLL_HPM_SDM_FRACTION, field HPM_NUM_SELECTED[9:0] (RO)
33961  *
33962  * This is the numerator that is currently being applied to the High Port Sigma
33963  * Delta Modulator, for valid Sigma Delta operation the resulting fraction
33964  * NUM/DENOM must be in the range -0.6 to +0.6
33965  */
33966 /*@{*/
33967 /*! @brief Read current value of the XCVR_PLL_HPM_SDM_FRACTION_HPM_NUM_SELECTED field. */
33968 #define XCVR_RD_PLL_HPM_SDM_FRACTION_HPM_NUM_SELECTED(base) ((XCVR_PLL_HPM_SDM_FRACTION_REG(base) & XCVR_PLL_HPM_SDM_FRACTION_HPM_NUM_SELECTED_MASK) >> XCVR_PLL_HPM_SDM_FRACTION_HPM_NUM_SELECTED_SHIFT)
33969 #define XCVR_BRD_PLL_HPM_SDM_FRACTION_HPM_NUM_SELECTED(base) (BME_UBFX32(&XCVR_PLL_HPM_SDM_FRACTION_REG(base), XCVR_PLL_HPM_SDM_FRACTION_HPM_NUM_SELECTED_SHIFT, XCVR_PLL_HPM_SDM_FRACTION_HPM_NUM_SELECTED_WIDTH))
33970 /*@}*/
33971 
33972 /*!
33973  * @name Register XCVR_PLL_HPM_SDM_FRACTION, field HPM_DENOM[25:16] (RW)
33974  *
33975  * This is the denominator that is currently being applied to the High Port
33976  * Sigma Delta Modulator, for valid Sigma Delta operation the resulting fraction
33977  * NUM/DENOM must be in the range -0.6 to +0.6 The High Port Sigma Delta Modulator
33978  * LSB in Hz can be calculated as follows: HP SDM LSB Resolution = High Port Array
33979  * LSB in Hz / 2^6 = 6e3/256 = 93.75 Hz The High Port Array LSB is expected to be
33980  * 6 kHz after calibration.
33981  */
33982 /*@{*/
33983 /*! @brief Read current value of the XCVR_PLL_HPM_SDM_FRACTION_HPM_DENOM field. */
33984 #define XCVR_RD_PLL_HPM_SDM_FRACTION_HPM_DENOM(base) ((XCVR_PLL_HPM_SDM_FRACTION_REG(base) & XCVR_PLL_HPM_SDM_FRACTION_HPM_DENOM_MASK) >> XCVR_PLL_HPM_SDM_FRACTION_HPM_DENOM_SHIFT)
33985 #define XCVR_BRD_PLL_HPM_SDM_FRACTION_HPM_DENOM(base) (BME_UBFX32(&XCVR_PLL_HPM_SDM_FRACTION_REG(base), XCVR_PLL_HPM_SDM_FRACTION_HPM_DENOM_SHIFT, XCVR_PLL_HPM_SDM_FRACTION_HPM_DENOM_WIDTH))
33986 
33987 /*! @brief Set the HPM_DENOM field to a new value. */
33988 #define XCVR_WR_PLL_HPM_SDM_FRACTION_HPM_DENOM(base, value) (XCVR_RMW_PLL_HPM_SDM_FRACTION(base, XCVR_PLL_HPM_SDM_FRACTION_HPM_DENOM_MASK, XCVR_PLL_HPM_SDM_FRACTION_HPM_DENOM(value)))
33989 #define XCVR_BWR_PLL_HPM_SDM_FRACTION_HPM_DENOM(base, value) (BME_BFI32(&XCVR_PLL_HPM_SDM_FRACTION_REG(base), ((uint32_t)(value) << XCVR_PLL_HPM_SDM_FRACTION_HPM_DENOM_SHIFT), XCVR_PLL_HPM_SDM_FRACTION_HPM_DENOM_SHIFT, XCVR_PLL_HPM_SDM_FRACTION_HPM_DENOM_WIDTH))
33990 /*@}*/
33991 
33992 /*******************************************************************************
33993  * XCVR_PLL_LP_MOD_CTRL - PLL Low Port Modulation Control
33994  ******************************************************************************/
33995 
33996 /*!
33997  * @brief XCVR_PLL_LP_MOD_CTRL - PLL Low Port Modulation Control (RW)
33998  *
33999  * Reset value: 0x08080000U
34000  */
34001 /*!
34002  * @name Constants and macros for entire XCVR_PLL_LP_MOD_CTRL register
34003  */
34004 /*@{*/
34005 #define XCVR_RD_PLL_LP_MOD_CTRL(base) (XCVR_PLL_LP_MOD_CTRL_REG(base))
34006 #define XCVR_WR_PLL_LP_MOD_CTRL(base, value) (XCVR_PLL_LP_MOD_CTRL_REG(base) = (value))
34007 #define XCVR_RMW_PLL_LP_MOD_CTRL(base, mask, value) (XCVR_WR_PLL_LP_MOD_CTRL(base, (XCVR_RD_PLL_LP_MOD_CTRL(base) & ~(mask)) | (value)))
34008 #define XCVR_SET_PLL_LP_MOD_CTRL(base, value) (BME_OR32(&XCVR_PLL_LP_MOD_CTRL_REG(base), (uint32_t)(value)))
34009 #define XCVR_CLR_PLL_LP_MOD_CTRL(base, value) (BME_AND32(&XCVR_PLL_LP_MOD_CTRL_REG(base), (uint32_t)(~(value))))
34010 #define XCVR_TOG_PLL_LP_MOD_CTRL(base, value) (BME_XOR32(&XCVR_PLL_LP_MOD_CTRL_REG(base), (uint32_t)(value)))
34011 /*@}*/
34012 
34013 /*
34014  * Constants & macros for individual XCVR_PLL_LP_MOD_CTRL bitfields
34015  */
34016 
34017 /*!
34018  * @name Register XCVR_PLL_LP_MOD_CTRL, field PLL_LOOP_DIVIDER_MANUAL[5:0] (RW)
34019  *
34020  * If PLL_LD_DIS is set, this register is the value that is applied to the PLL
34021  * Loop Divider i.
34022  */
34023 /*@{*/
34024 /*! @brief Read current value of the XCVR_PLL_LP_MOD_CTRL_PLL_LOOP_DIVIDER_MANUAL field. */
34025 #define XCVR_RD_PLL_LP_MOD_CTRL_PLL_LOOP_DIVIDER_MANUAL(base) ((XCVR_PLL_LP_MOD_CTRL_REG(base) & XCVR_PLL_LP_MOD_CTRL_PLL_LOOP_DIVIDER_MANUAL_MASK) >> XCVR_PLL_LP_MOD_CTRL_PLL_LOOP_DIVIDER_MANUAL_SHIFT)
34026 #define XCVR_BRD_PLL_LP_MOD_CTRL_PLL_LOOP_DIVIDER_MANUAL(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCVR_PLL_LP_MOD_CTRL_PLL_LOOP_DIVIDER_MANUAL_SHIFT, XCVR_PLL_LP_MOD_CTRL_PLL_LOOP_DIVIDER_MANUAL_WIDTH))
34027 
34028 /*! @brief Set the PLL_LOOP_DIVIDER_MANUAL field to a new value. */
34029 #define XCVR_WR_PLL_LP_MOD_CTRL_PLL_LOOP_DIVIDER_MANUAL(base, value) (XCVR_RMW_PLL_LP_MOD_CTRL(base, (XCVR_PLL_LP_MOD_CTRL_PLL_LOOP_DIVIDER_MANUAL_MASK | XCVR_PLL_LP_MOD_CTRL_LPFF_MASK), XCVR_PLL_LP_MOD_CTRL_PLL_LOOP_DIVIDER_MANUAL(value)))
34030 #define XCVR_BWR_PLL_LP_MOD_CTRL_PLL_LOOP_DIVIDER_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_LP_MOD_CTRL_PLL_LOOP_DIVIDER_MANUAL_SHIFT), XCVR_PLL_LP_MOD_CTRL_PLL_LOOP_DIVIDER_MANUAL_SHIFT, XCVR_PLL_LP_MOD_CTRL_PLL_LOOP_DIVIDER_MANUAL_WIDTH))
34031 /*@}*/
34032 
34033 /*!
34034  * @name Register XCVR_PLL_LP_MOD_CTRL, field PLL_LD_DIS[11] (RW)
34035  *
34036  * If this bit is set, the Low Port Sigma Delta Modulator output is disabled,
34037  * and the PLL Loop Divider value applied to the PLL comes from the
34038  * PLL_LOOP_DIVIDER_MANUAL register.
34039  */
34040 /*@{*/
34041 /*! @brief Read current value of the XCVR_PLL_LP_MOD_CTRL_PLL_LD_DIS field. */
34042 #define XCVR_RD_PLL_LP_MOD_CTRL_PLL_LD_DIS(base) ((XCVR_PLL_LP_MOD_CTRL_REG(base) & XCVR_PLL_LP_MOD_CTRL_PLL_LD_DIS_MASK) >> XCVR_PLL_LP_MOD_CTRL_PLL_LD_DIS_SHIFT)
34043 #define XCVR_BRD_PLL_LP_MOD_CTRL_PLL_LD_DIS(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCVR_PLL_LP_MOD_CTRL_PLL_LD_DIS_SHIFT, XCVR_PLL_LP_MOD_CTRL_PLL_LD_DIS_WIDTH))
34044 
34045 /*! @brief Set the PLL_LD_DIS field to a new value. */
34046 #define XCVR_WR_PLL_LP_MOD_CTRL_PLL_LD_DIS(base, value) (XCVR_RMW_PLL_LP_MOD_CTRL(base, (XCVR_PLL_LP_MOD_CTRL_PLL_LD_DIS_MASK | XCVR_PLL_LP_MOD_CTRL_LPFF_MASK), XCVR_PLL_LP_MOD_CTRL_PLL_LD_DIS(value)))
34047 #define XCVR_BWR_PLL_LP_MOD_CTRL_PLL_LD_DIS(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_LP_MOD_CTRL_PLL_LD_DIS_SHIFT), XCVR_PLL_LP_MOD_CTRL_PLL_LD_DIS_SHIFT, XCVR_PLL_LP_MOD_CTRL_PLL_LD_DIS_WIDTH))
34048 /*@}*/
34049 
34050 /*!
34051  * @name Register XCVR_PLL_LP_MOD_CTRL, field LPFF[13] (W1C)
34052  *
34053  * This bit is set if the Low Port Sigma Delta Modulator output is invalid due
34054  * to an error in the Fraction applied, and this bit is cleared by writing a 1 to
34055  * it.
34056  */
34057 /*@{*/
34058 /*! @brief Read current value of the XCVR_PLL_LP_MOD_CTRL_LPFF field. */
34059 #define XCVR_RD_PLL_LP_MOD_CTRL_LPFF(base) ((XCVR_PLL_LP_MOD_CTRL_REG(base) & XCVR_PLL_LP_MOD_CTRL_LPFF_MASK) >> XCVR_PLL_LP_MOD_CTRL_LPFF_SHIFT)
34060 #define XCVR_BRD_PLL_LP_MOD_CTRL_LPFF(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCVR_PLL_LP_MOD_CTRL_LPFF_SHIFT, XCVR_PLL_LP_MOD_CTRL_LPFF_WIDTH))
34061 
34062 /*! @brief Set the LPFF field to a new value. */
34063 #define XCVR_WR_PLL_LP_MOD_CTRL_LPFF(base, value) (XCVR_RMW_PLL_LP_MOD_CTRL(base, XCVR_PLL_LP_MOD_CTRL_LPFF_MASK, XCVR_PLL_LP_MOD_CTRL_LPFF(value)))
34064 #define XCVR_BWR_PLL_LP_MOD_CTRL_LPFF(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_LP_MOD_CTRL_LPFF_SHIFT), XCVR_PLL_LP_MOD_CTRL_LPFF_SHIFT, XCVR_PLL_LP_MOD_CTRL_LPFF_WIDTH))
34065 /*@}*/
34066 
34067 /*!
34068  * @name Register XCVR_PLL_LP_MOD_CTRL, field LPM_SDM_INV[14] (RW)
34069  *
34070  * If this bit is set the Scaled Baseband Frequency Word, including any
34071  * Dithering, will be Inverted before it is applied to the Low Port Sigma Delta Modulator.
34072  */
34073 /*@{*/
34074 /*! @brief Read current value of the XCVR_PLL_LP_MOD_CTRL_LPM_SDM_INV field. */
34075 #define XCVR_RD_PLL_LP_MOD_CTRL_LPM_SDM_INV(base) ((XCVR_PLL_LP_MOD_CTRL_REG(base) & XCVR_PLL_LP_MOD_CTRL_LPM_SDM_INV_MASK) >> XCVR_PLL_LP_MOD_CTRL_LPM_SDM_INV_SHIFT)
34076 #define XCVR_BRD_PLL_LP_MOD_CTRL_LPM_SDM_INV(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCVR_PLL_LP_MOD_CTRL_LPM_SDM_INV_SHIFT, XCVR_PLL_LP_MOD_CTRL_LPM_SDM_INV_WIDTH))
34077 
34078 /*! @brief Set the LPM_SDM_INV field to a new value. */
34079 #define XCVR_WR_PLL_LP_MOD_CTRL_LPM_SDM_INV(base, value) (XCVR_RMW_PLL_LP_MOD_CTRL(base, (XCVR_PLL_LP_MOD_CTRL_LPM_SDM_INV_MASK | XCVR_PLL_LP_MOD_CTRL_LPFF_MASK), XCVR_PLL_LP_MOD_CTRL_LPM_SDM_INV(value)))
34080 #define XCVR_BWR_PLL_LP_MOD_CTRL_LPM_SDM_INV(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_LP_MOD_CTRL_LPM_SDM_INV_SHIFT), XCVR_PLL_LP_MOD_CTRL_LPM_SDM_INV_SHIFT, XCVR_PLL_LP_MOD_CTRL_LPM_SDM_INV_WIDTH))
34081 /*@}*/
34082 
34083 /*!
34084  * @name Register XCVR_PLL_LP_MOD_CTRL, field LPM_SDM_DIS[15] (RW)
34085  *
34086  * This bit controls the Modulation of the Low Port Sigma Delta. If this bit is
34087  * set, the Low Port Sigma Delta will be active and control the PLL to maintain a
34088  * steady frequency based on the current Integer, Numerator, and Denominator
34089  * values that are being applied. Modulation and Dithering will be disabled.
34090  */
34091 /*@{*/
34092 /*! @brief Read current value of the XCVR_PLL_LP_MOD_CTRL_LPM_SDM_DIS field. */
34093 #define XCVR_RD_PLL_LP_MOD_CTRL_LPM_SDM_DIS(base) ((XCVR_PLL_LP_MOD_CTRL_REG(base) & XCVR_PLL_LP_MOD_CTRL_LPM_SDM_DIS_MASK) >> XCVR_PLL_LP_MOD_CTRL_LPM_SDM_DIS_SHIFT)
34094 #define XCVR_BRD_PLL_LP_MOD_CTRL_LPM_SDM_DIS(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCVR_PLL_LP_MOD_CTRL_LPM_SDM_DIS_SHIFT, XCVR_PLL_LP_MOD_CTRL_LPM_SDM_DIS_WIDTH))
34095 
34096 /*! @brief Set the LPM_SDM_DIS field to a new value. */
34097 #define XCVR_WR_PLL_LP_MOD_CTRL_LPM_SDM_DIS(base, value) (XCVR_RMW_PLL_LP_MOD_CTRL(base, (XCVR_PLL_LP_MOD_CTRL_LPM_SDM_DIS_MASK | XCVR_PLL_LP_MOD_CTRL_LPFF_MASK), XCVR_PLL_LP_MOD_CTRL_LPM_SDM_DIS(value)))
34098 #define XCVR_BWR_PLL_LP_MOD_CTRL_LPM_SDM_DIS(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_LP_MOD_CTRL_LPM_SDM_DIS_SHIFT), XCVR_PLL_LP_MOD_CTRL_LPM_SDM_DIS_SHIFT, XCVR_PLL_LP_MOD_CTRL_LPM_SDM_DIS_WIDTH))
34099 /*@}*/
34100 
34101 /*!
34102  * @name Register XCVR_PLL_LP_MOD_CTRL, field LPM_DTH_SCL[19:16] (RW)
34103  *
34104  * This register controls the scale of the Dithering added to the Scaled
34105  * Baseband Frequency Word before it is applied to the Low Port Sigma Delta Modulator as
34106  * the LPM Numerator. The unit for the ranges shown below is the LP SDM LSB in
34107  * Hz.
34108  *
34109  * Values:
34110  * - 0b0000 - Reserved
34111  * - 0b0001 - Reserved
34112  * - 0b0010 - Reserved
34113  * - 0b0011 - Reserved
34114  * - 0b0100 - Reserved
34115  * - 0b0101 - -128 to 96
34116  * - 0b0110 - -256 to 192
34117  * - 0b0111 - -512 to 384
34118  * - 0b1000 - -1024 to 768
34119  * - 0b1001 - -2048 to 1536
34120  * - 0b1010 - -4096 to 3072
34121  * - 0b1011 - -8192 to 6144
34122  * - 0b1100 - Reserved
34123  * - 0b1101 - Reserved
34124  * - 0b1110 - Reserved
34125  * - 0b1111 - Reserved
34126  */
34127 /*@{*/
34128 /*! @brief Read current value of the XCVR_PLL_LP_MOD_CTRL_LPM_DTH_SCL field. */
34129 #define XCVR_RD_PLL_LP_MOD_CTRL_LPM_DTH_SCL(base) ((XCVR_PLL_LP_MOD_CTRL_REG(base) & XCVR_PLL_LP_MOD_CTRL_LPM_DTH_SCL_MASK) >> XCVR_PLL_LP_MOD_CTRL_LPM_DTH_SCL_SHIFT)
34130 #define XCVR_BRD_PLL_LP_MOD_CTRL_LPM_DTH_SCL(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCVR_PLL_LP_MOD_CTRL_LPM_DTH_SCL_SHIFT, XCVR_PLL_LP_MOD_CTRL_LPM_DTH_SCL_WIDTH))
34131 
34132 /*! @brief Set the LPM_DTH_SCL field to a new value. */
34133 #define XCVR_WR_PLL_LP_MOD_CTRL_LPM_DTH_SCL(base, value) (XCVR_RMW_PLL_LP_MOD_CTRL(base, (XCVR_PLL_LP_MOD_CTRL_LPM_DTH_SCL_MASK | XCVR_PLL_LP_MOD_CTRL_LPFF_MASK), XCVR_PLL_LP_MOD_CTRL_LPM_DTH_SCL(value)))
34134 #define XCVR_BWR_PLL_LP_MOD_CTRL_LPM_DTH_SCL(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_LP_MOD_CTRL_LPM_DTH_SCL_SHIFT), XCVR_PLL_LP_MOD_CTRL_LPM_DTH_SCL_SHIFT, XCVR_PLL_LP_MOD_CTRL_LPM_DTH_SCL_WIDTH))
34135 /*@}*/
34136 
34137 /*!
34138  * @name Register XCVR_PLL_LP_MOD_CTRL, field LPM_D_CTRL[22] (RW)
34139  *
34140  * If LPM_D_OVRD is set, this bit turns LPM Dithering on and off.
34141  */
34142 /*@{*/
34143 /*! @brief Read current value of the XCVR_PLL_LP_MOD_CTRL_LPM_D_CTRL field. */
34144 #define XCVR_RD_PLL_LP_MOD_CTRL_LPM_D_CTRL(base) ((XCVR_PLL_LP_MOD_CTRL_REG(base) & XCVR_PLL_LP_MOD_CTRL_LPM_D_CTRL_MASK) >> XCVR_PLL_LP_MOD_CTRL_LPM_D_CTRL_SHIFT)
34145 #define XCVR_BRD_PLL_LP_MOD_CTRL_LPM_D_CTRL(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCVR_PLL_LP_MOD_CTRL_LPM_D_CTRL_SHIFT, XCVR_PLL_LP_MOD_CTRL_LPM_D_CTRL_WIDTH))
34146 
34147 /*! @brief Set the LPM_D_CTRL field to a new value. */
34148 #define XCVR_WR_PLL_LP_MOD_CTRL_LPM_D_CTRL(base, value) (XCVR_RMW_PLL_LP_MOD_CTRL(base, (XCVR_PLL_LP_MOD_CTRL_LPM_D_CTRL_MASK | XCVR_PLL_LP_MOD_CTRL_LPFF_MASK), XCVR_PLL_LP_MOD_CTRL_LPM_D_CTRL(value)))
34149 #define XCVR_BWR_PLL_LP_MOD_CTRL_LPM_D_CTRL(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_LP_MOD_CTRL_LPM_D_CTRL_SHIFT), XCVR_PLL_LP_MOD_CTRL_LPM_D_CTRL_SHIFT, XCVR_PLL_LP_MOD_CTRL_LPM_D_CTRL_WIDTH))
34150 /*@}*/
34151 
34152 /*!
34153  * @name Register XCVR_PLL_LP_MOD_CTRL, field LPM_D_OVRD[23] (RW)
34154  *
34155  * When this bit is set, the Scaled Baseband Frequency Word applied to the Low
34156  * Port Sigma Delta Modulator will be dithered if LPM_D_CTRL is set, and not
34157  * dithered if LPM_D_CTRL is cleared. If this bit is cleared, then the LPM Numerator
34158  * will be dithered in Radio Receive mode, and also when the LPM Numerator
34159  * approaches an Integer value in order to preserve the validity of the Sigma Delta
34160  * Modulator output.
34161  */
34162 /*@{*/
34163 /*! @brief Read current value of the XCVR_PLL_LP_MOD_CTRL_LPM_D_OVRD field. */
34164 #define XCVR_RD_PLL_LP_MOD_CTRL_LPM_D_OVRD(base) ((XCVR_PLL_LP_MOD_CTRL_REG(base) & XCVR_PLL_LP_MOD_CTRL_LPM_D_OVRD_MASK) >> XCVR_PLL_LP_MOD_CTRL_LPM_D_OVRD_SHIFT)
34165 #define XCVR_BRD_PLL_LP_MOD_CTRL_LPM_D_OVRD(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCVR_PLL_LP_MOD_CTRL_LPM_D_OVRD_SHIFT, XCVR_PLL_LP_MOD_CTRL_LPM_D_OVRD_WIDTH))
34166 
34167 /*! @brief Set the LPM_D_OVRD field to a new value. */
34168 #define XCVR_WR_PLL_LP_MOD_CTRL_LPM_D_OVRD(base, value) (XCVR_RMW_PLL_LP_MOD_CTRL(base, (XCVR_PLL_LP_MOD_CTRL_LPM_D_OVRD_MASK | XCVR_PLL_LP_MOD_CTRL_LPFF_MASK), XCVR_PLL_LP_MOD_CTRL_LPM_D_OVRD(value)))
34169 #define XCVR_BWR_PLL_LP_MOD_CTRL_LPM_D_OVRD(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_LP_MOD_CTRL_LPM_D_OVRD_SHIFT), XCVR_PLL_LP_MOD_CTRL_LPM_D_OVRD_SHIFT, XCVR_PLL_LP_MOD_CTRL_LPM_D_OVRD_WIDTH))
34170 /*@}*/
34171 
34172 /*!
34173  * @name Register XCVR_PLL_LP_MOD_CTRL, field LPM_SCALE[27:24] (RW)
34174  *
34175  * This register controls the scaling of the Baseband Frequency Word and is used
34176  * to match the Modulation Frequency Deviation required to the Low Port Sigma
34177  * Delta Modulator LSB size in Hz.
34178  *
34179  * Values:
34180  * - 0b0000 - No Scaling
34181  * - 0b0001 - Multiply by 2
34182  * - 0b0010 - Multiply by 4
34183  * - 0b0011 - Multiply by 8
34184  * - 0b0100 - Multiply by 16
34185  * - 0b0101 - Multiply by 32
34186  * - 0b0110 - Multiply by 64
34187  * - 0b0111 - Multiply by 128
34188  * - 0b1000 - Multiply by 256
34189  * - 0b1001 - Multiply by 512
34190  * - 0b1010 - Multiply by 1024
34191  * - 0b1011 - Multiply by 2048
34192  * - 0b1100 - Reserved
34193  * - 0b1101 - Reserved
34194  * - 0b1110 - Reserved
34195  * - 0b1111 - Reserved
34196  */
34197 /*@{*/
34198 /*! @brief Read current value of the XCVR_PLL_LP_MOD_CTRL_LPM_SCALE field. */
34199 #define XCVR_RD_PLL_LP_MOD_CTRL_LPM_SCALE(base) ((XCVR_PLL_LP_MOD_CTRL_REG(base) & XCVR_PLL_LP_MOD_CTRL_LPM_SCALE_MASK) >> XCVR_PLL_LP_MOD_CTRL_LPM_SCALE_SHIFT)
34200 #define XCVR_BRD_PLL_LP_MOD_CTRL_LPM_SCALE(base) (BME_UBFX32(&XCVR_PLL_LP_MOD_CTRL_REG(base), XCVR_PLL_LP_MOD_CTRL_LPM_SCALE_SHIFT, XCVR_PLL_LP_MOD_CTRL_LPM_SCALE_WIDTH))
34201 
34202 /*! @brief Set the LPM_SCALE field to a new value. */
34203 #define XCVR_WR_PLL_LP_MOD_CTRL_LPM_SCALE(base, value) (XCVR_RMW_PLL_LP_MOD_CTRL(base, (XCVR_PLL_LP_MOD_CTRL_LPM_SCALE_MASK | XCVR_PLL_LP_MOD_CTRL_LPFF_MASK), XCVR_PLL_LP_MOD_CTRL_LPM_SCALE(value)))
34204 #define XCVR_BWR_PLL_LP_MOD_CTRL_LPM_SCALE(base, value) (BME_BFI32(&XCVR_PLL_LP_MOD_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_LP_MOD_CTRL_LPM_SCALE_SHIFT), XCVR_PLL_LP_MOD_CTRL_LPM_SCALE_SHIFT, XCVR_PLL_LP_MOD_CTRL_LPM_SCALE_WIDTH))
34205 /*@}*/
34206 
34207 /*******************************************************************************
34208  * XCVR_PLL_LP_SDM_CTRL1 - PLL Low Port SDM Control 1
34209  ******************************************************************************/
34210 
34211 /*!
34212  * @brief XCVR_PLL_LP_SDM_CTRL1 - PLL Low Port SDM Control 1 (RW)
34213  *
34214  * Reset value: 0x00260026U
34215  */
34216 /*!
34217  * @name Constants and macros for entire XCVR_PLL_LP_SDM_CTRL1 register
34218  */
34219 /*@{*/
34220 #define XCVR_RD_PLL_LP_SDM_CTRL1(base) (XCVR_PLL_LP_SDM_CTRL1_REG(base))
34221 #define XCVR_WR_PLL_LP_SDM_CTRL1(base, value) (XCVR_PLL_LP_SDM_CTRL1_REG(base) = (value))
34222 #define XCVR_RMW_PLL_LP_SDM_CTRL1(base, mask, value) (XCVR_WR_PLL_LP_SDM_CTRL1(base, (XCVR_RD_PLL_LP_SDM_CTRL1(base) & ~(mask)) | (value)))
34223 #define XCVR_SET_PLL_LP_SDM_CTRL1(base, value) (BME_OR32(&XCVR_PLL_LP_SDM_CTRL1_REG(base), (uint32_t)(value)))
34224 #define XCVR_CLR_PLL_LP_SDM_CTRL1(base, value) (BME_AND32(&XCVR_PLL_LP_SDM_CTRL1_REG(base), (uint32_t)(~(value))))
34225 #define XCVR_TOG_PLL_LP_SDM_CTRL1(base, value) (BME_XOR32(&XCVR_PLL_LP_SDM_CTRL1_REG(base), (uint32_t)(value)))
34226 /*@}*/
34227 
34228 /*
34229  * Constants & macros for individual XCVR_PLL_LP_SDM_CTRL1 bitfields
34230  */
34231 
34232 /*!
34233  * @name Register XCVR_PLL_LP_SDM_CTRL1, field LPM_INTG_SELECTED[6:0] (RO)
34234  *
34235  * This shows the integer value that is currently being applied to the low port
34236  * sigma delta modulator.
34237  */
34238 /*@{*/
34239 /*! @brief Read current value of the XCVR_PLL_LP_SDM_CTRL1_LPM_INTG_SELECTED field. */
34240 #define XCVR_RD_PLL_LP_SDM_CTRL1_LPM_INTG_SELECTED(base) ((XCVR_PLL_LP_SDM_CTRL1_REG(base) & XCVR_PLL_LP_SDM_CTRL1_LPM_INTG_SELECTED_MASK) >> XCVR_PLL_LP_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT)
34241 #define XCVR_BRD_PLL_LP_SDM_CTRL1_LPM_INTG_SELECTED(base) (BME_UBFX32(&XCVR_PLL_LP_SDM_CTRL1_REG(base), XCVR_PLL_LP_SDM_CTRL1_LPM_INTG_SELECTED_SHIFT, XCVR_PLL_LP_SDM_CTRL1_LPM_INTG_SELECTED_WIDTH))
34242 /*@}*/
34243 
34244 /*!
34245  * @name Register XCVR_PLL_LP_SDM_CTRL1, field LPM_INTG[22:16] (RW)
34246  *
34247  * If SDM_MAP_DIS is set, this register is the value that is applied to the Low
34248  * Port Sigma Delta Modulator for the Integer, the nominal range is 36 to 39 in
34249  * decimal.
34250  */
34251 /*@{*/
34252 /*! @brief Read current value of the XCVR_PLL_LP_SDM_CTRL1_LPM_INTG field. */
34253 #define XCVR_RD_PLL_LP_SDM_CTRL1_LPM_INTG(base) ((XCVR_PLL_LP_SDM_CTRL1_REG(base) & XCVR_PLL_LP_SDM_CTRL1_LPM_INTG_MASK) >> XCVR_PLL_LP_SDM_CTRL1_LPM_INTG_SHIFT)
34254 #define XCVR_BRD_PLL_LP_SDM_CTRL1_LPM_INTG(base) (BME_UBFX32(&XCVR_PLL_LP_SDM_CTRL1_REG(base), XCVR_PLL_LP_SDM_CTRL1_LPM_INTG_SHIFT, XCVR_PLL_LP_SDM_CTRL1_LPM_INTG_WIDTH))
34255 
34256 /*! @brief Set the LPM_INTG field to a new value. */
34257 #define XCVR_WR_PLL_LP_SDM_CTRL1_LPM_INTG(base, value) (XCVR_RMW_PLL_LP_SDM_CTRL1(base, XCVR_PLL_LP_SDM_CTRL1_LPM_INTG_MASK, XCVR_PLL_LP_SDM_CTRL1_LPM_INTG(value)))
34258 #define XCVR_BWR_PLL_LP_SDM_CTRL1_LPM_INTG(base, value) (BME_BFI32(&XCVR_PLL_LP_SDM_CTRL1_REG(base), ((uint32_t)(value) << XCVR_PLL_LP_SDM_CTRL1_LPM_INTG_SHIFT), XCVR_PLL_LP_SDM_CTRL1_LPM_INTG_SHIFT, XCVR_PLL_LP_SDM_CTRL1_LPM_INTG_WIDTH))
34259 /*@}*/
34260 
34261 /*!
34262  * @name Register XCVR_PLL_LP_SDM_CTRL1, field SDM_MAP_DIS[31] (RW)
34263  *
34264  * If this bit is set, the Low Port Sigma Delta Modulator internal frequency
34265  * mapping based on Protocol specific channel numbers is disabled, and the Radio
34266  * Channel Frequency is selected by setting the LPM_INTG, LPM_NUM, and LPM_DENOM
34267  * registers to get a frequency that equals ((Reference Clock Frequency x 2) x
34268  * (LPM_INTG + (LPM_NUM / LPM_DENOM))
34269  */
34270 /*@{*/
34271 /*! @brief Read current value of the XCVR_PLL_LP_SDM_CTRL1_SDM_MAP_DIS field. */
34272 #define XCVR_RD_PLL_LP_SDM_CTRL1_SDM_MAP_DIS(base) ((XCVR_PLL_LP_SDM_CTRL1_REG(base) & XCVR_PLL_LP_SDM_CTRL1_SDM_MAP_DIS_MASK) >> XCVR_PLL_LP_SDM_CTRL1_SDM_MAP_DIS_SHIFT)
34273 #define XCVR_BRD_PLL_LP_SDM_CTRL1_SDM_MAP_DIS(base) (BME_UBFX32(&XCVR_PLL_LP_SDM_CTRL1_REG(base), XCVR_PLL_LP_SDM_CTRL1_SDM_MAP_DIS_SHIFT, XCVR_PLL_LP_SDM_CTRL1_SDM_MAP_DIS_WIDTH))
34274 
34275 /*! @brief Set the SDM_MAP_DIS field to a new value. */
34276 #define XCVR_WR_PLL_LP_SDM_CTRL1_SDM_MAP_DIS(base, value) (XCVR_RMW_PLL_LP_SDM_CTRL1(base, XCVR_PLL_LP_SDM_CTRL1_SDM_MAP_DIS_MASK, XCVR_PLL_LP_SDM_CTRL1_SDM_MAP_DIS(value)))
34277 #define XCVR_BWR_PLL_LP_SDM_CTRL1_SDM_MAP_DIS(base, value) (BME_BFI32(&XCVR_PLL_LP_SDM_CTRL1_REG(base), ((uint32_t)(value) << XCVR_PLL_LP_SDM_CTRL1_SDM_MAP_DIS_SHIFT), XCVR_PLL_LP_SDM_CTRL1_SDM_MAP_DIS_SHIFT, XCVR_PLL_LP_SDM_CTRL1_SDM_MAP_DIS_WIDTH))
34278 /*@}*/
34279 
34280 /*******************************************************************************
34281  * XCVR_PLL_LP_SDM_CTRL2 - PLL Low Port SDM Control 2
34282  ******************************************************************************/
34283 
34284 /*!
34285  * @brief XCVR_PLL_LP_SDM_CTRL2 - PLL Low Port SDM Control 2 (RW)
34286  *
34287  * Reset value: 0x02000000U
34288  */
34289 /*!
34290  * @name Constants and macros for entire XCVR_PLL_LP_SDM_CTRL2 register
34291  */
34292 /*@{*/
34293 #define XCVR_RD_PLL_LP_SDM_CTRL2(base) (XCVR_PLL_LP_SDM_CTRL2_REG(base))
34294 #define XCVR_WR_PLL_LP_SDM_CTRL2(base, value) (XCVR_PLL_LP_SDM_CTRL2_REG(base) = (value))
34295 #define XCVR_RMW_PLL_LP_SDM_CTRL2(base, mask, value) (XCVR_WR_PLL_LP_SDM_CTRL2(base, (XCVR_RD_PLL_LP_SDM_CTRL2(base) & ~(mask)) | (value)))
34296 #define XCVR_SET_PLL_LP_SDM_CTRL2(base, value) (BME_OR32(&XCVR_PLL_LP_SDM_CTRL2_REG(base), (uint32_t)(value)))
34297 #define XCVR_CLR_PLL_LP_SDM_CTRL2(base, value) (BME_AND32(&XCVR_PLL_LP_SDM_CTRL2_REG(base), (uint32_t)(~(value))))
34298 #define XCVR_TOG_PLL_LP_SDM_CTRL2(base, value) (BME_XOR32(&XCVR_PLL_LP_SDM_CTRL2_REG(base), (uint32_t)(value)))
34299 /*@}*/
34300 
34301 /*
34302  * Constants & macros for individual XCVR_PLL_LP_SDM_CTRL2 bitfields
34303  */
34304 
34305 /*!
34306  * @name Register XCVR_PLL_LP_SDM_CTRL2, field LPM_NUM[27:0] (RW)
34307  *
34308  * If SDM_MAP_DIS is set, this register is the signed 27 bit value that is
34309  * applied to the Low Port Sigma Delta Modulator for the Numerator. For valid Sigma
34310  * Delta operation the resulting fraction NUM/DENOM must be in the range -0.6 to
34311  * +0.6
34312  */
34313 /*@{*/
34314 /*! @brief Read current value of the XCVR_PLL_LP_SDM_CTRL2_LPM_NUM field. */
34315 #define XCVR_RD_PLL_LP_SDM_CTRL2_LPM_NUM(base) ((XCVR_PLL_LP_SDM_CTRL2_REG(base) & XCVR_PLL_LP_SDM_CTRL2_LPM_NUM_MASK) >> XCVR_PLL_LP_SDM_CTRL2_LPM_NUM_SHIFT)
34316 #define XCVR_BRD_PLL_LP_SDM_CTRL2_LPM_NUM(base) (XCVR_RD_PLL_LP_SDM_CTRL2_LPM_NUM(base))
34317 
34318 /*! @brief Set the LPM_NUM field to a new value. */
34319 #define XCVR_WR_PLL_LP_SDM_CTRL2_LPM_NUM(base, value) (XCVR_RMW_PLL_LP_SDM_CTRL2(base, XCVR_PLL_LP_SDM_CTRL2_LPM_NUM_MASK, XCVR_PLL_LP_SDM_CTRL2_LPM_NUM(value)))
34320 #define XCVR_BWR_PLL_LP_SDM_CTRL2_LPM_NUM(base, value) (XCVR_WR_PLL_LP_SDM_CTRL2_LPM_NUM(base, value))
34321 /*@}*/
34322 
34323 /*******************************************************************************
34324  * XCVR_PLL_LP_SDM_CTRL3 - PLL Low Port SDM Control 3
34325  ******************************************************************************/
34326 
34327 /*!
34328  * @brief XCVR_PLL_LP_SDM_CTRL3 - PLL Low Port SDM Control 3 (RW)
34329  *
34330  * Reset value: 0x04000000U
34331  */
34332 /*!
34333  * @name Constants and macros for entire XCVR_PLL_LP_SDM_CTRL3 register
34334  */
34335 /*@{*/
34336 #define XCVR_RD_PLL_LP_SDM_CTRL3(base) (XCVR_PLL_LP_SDM_CTRL3_REG(base))
34337 #define XCVR_WR_PLL_LP_SDM_CTRL3(base, value) (XCVR_PLL_LP_SDM_CTRL3_REG(base) = (value))
34338 #define XCVR_RMW_PLL_LP_SDM_CTRL3(base, mask, value) (XCVR_WR_PLL_LP_SDM_CTRL3(base, (XCVR_RD_PLL_LP_SDM_CTRL3(base) & ~(mask)) | (value)))
34339 #define XCVR_SET_PLL_LP_SDM_CTRL3(base, value) (BME_OR32(&XCVR_PLL_LP_SDM_CTRL3_REG(base), (uint32_t)(value)))
34340 #define XCVR_CLR_PLL_LP_SDM_CTRL3(base, value) (BME_AND32(&XCVR_PLL_LP_SDM_CTRL3_REG(base), (uint32_t)(~(value))))
34341 #define XCVR_TOG_PLL_LP_SDM_CTRL3(base, value) (BME_XOR32(&XCVR_PLL_LP_SDM_CTRL3_REG(base), (uint32_t)(value)))
34342 /*@}*/
34343 
34344 /*
34345  * Constants & macros for individual XCVR_PLL_LP_SDM_CTRL3 bitfields
34346  */
34347 
34348 /*!
34349  * @name Register XCVR_PLL_LP_SDM_CTRL3, field LPM_DENOM[27:0] (RW)
34350  *
34351  * If SDM_MAP_DIS is set, this register is the signed 27 bit value that is
34352  * applied to the Low Port Sigma Delta Modulator for the Denominator. For valid Sigma
34353  * Delta operation the resulting fraction NUM/DENOM must be in the range -0.6 to
34354  * +0.6 The Low Port Sigma Delta Modulator LSB in Hz can be calculated as
34355  * follows: LP SDM LSB Resolution = Reference Clock Frequency / LPM_DENOM value The
34356  * default value of LPM_DENOM for a 32 MHz reference is 2 raised to the 26th power,
34357  * so the SDM LSB is 0.4768 Hz
34358  */
34359 /*@{*/
34360 /*! @brief Read current value of the XCVR_PLL_LP_SDM_CTRL3_LPM_DENOM field. */
34361 #define XCVR_RD_PLL_LP_SDM_CTRL3_LPM_DENOM(base) ((XCVR_PLL_LP_SDM_CTRL3_REG(base) & XCVR_PLL_LP_SDM_CTRL3_LPM_DENOM_MASK) >> XCVR_PLL_LP_SDM_CTRL3_LPM_DENOM_SHIFT)
34362 #define XCVR_BRD_PLL_LP_SDM_CTRL3_LPM_DENOM(base) (XCVR_RD_PLL_LP_SDM_CTRL3_LPM_DENOM(base))
34363 
34364 /*! @brief Set the LPM_DENOM field to a new value. */
34365 #define XCVR_WR_PLL_LP_SDM_CTRL3_LPM_DENOM(base, value) (XCVR_RMW_PLL_LP_SDM_CTRL3(base, XCVR_PLL_LP_SDM_CTRL3_LPM_DENOM_MASK, XCVR_PLL_LP_SDM_CTRL3_LPM_DENOM(value)))
34366 #define XCVR_BWR_PLL_LP_SDM_CTRL3_LPM_DENOM(base, value) (XCVR_WR_PLL_LP_SDM_CTRL3_LPM_DENOM(base, value))
34367 /*@}*/
34368 
34369 /*******************************************************************************
34370  * XCVR_PLL_LP_SDM_NUM - PLL Low Port SDM Numerator Applied
34371  ******************************************************************************/
34372 
34373 /*!
34374  * @brief XCVR_PLL_LP_SDM_NUM - PLL Low Port SDM Numerator Applied (RO)
34375  *
34376  * Reset value: 0x0E200000U
34377  */
34378 /*!
34379  * @name Constants and macros for entire XCVR_PLL_LP_SDM_NUM register
34380  */
34381 /*@{*/
34382 #define XCVR_RD_PLL_LP_SDM_NUM(base) (XCVR_PLL_LP_SDM_NUM_REG(base))
34383 /*@}*/
34384 
34385 /*
34386  * Constants & macros for individual XCVR_PLL_LP_SDM_NUM bitfields
34387  */
34388 
34389 /*!
34390  * @name Register XCVR_PLL_LP_SDM_NUM, field LPM_NUM_SELECTED[27:0] (RO)
34391  *
34392  * This is the value that is currently being applied to the sigma delta
34393  * modulator, for valid Sigma Delta operation the resulting fraction NUM/DENOM must be in
34394  * the range -0.6 to +0.6
34395  */
34396 /*@{*/
34397 /*! @brief Read current value of the XCVR_PLL_LP_SDM_NUM_LPM_NUM_SELECTED field. */
34398 #define XCVR_RD_PLL_LP_SDM_NUM_LPM_NUM_SELECTED(base) ((XCVR_PLL_LP_SDM_NUM_REG(base) & XCVR_PLL_LP_SDM_NUM_LPM_NUM_SELECTED_MASK) >> XCVR_PLL_LP_SDM_NUM_LPM_NUM_SELECTED_SHIFT)
34399 #define XCVR_BRD_PLL_LP_SDM_NUM_LPM_NUM_SELECTED(base) (XCVR_RD_PLL_LP_SDM_NUM_LPM_NUM_SELECTED(base))
34400 /*@}*/
34401 
34402 /*******************************************************************************
34403  * XCVR_PLL_LP_SDM_DENOM - PLL Low Port SDM Denominator Applied
34404  ******************************************************************************/
34405 
34406 /*!
34407  * @brief XCVR_PLL_LP_SDM_DENOM - PLL Low Port SDM Denominator Applied (RO)
34408  *
34409  * Reset value: 0x04000000U
34410  */
34411 /*!
34412  * @name Constants and macros for entire XCVR_PLL_LP_SDM_DENOM register
34413  */
34414 /*@{*/
34415 #define XCVR_RD_PLL_LP_SDM_DENOM(base) (XCVR_PLL_LP_SDM_DENOM_REG(base))
34416 /*@}*/
34417 
34418 /*
34419  * Constants & macros for individual XCVR_PLL_LP_SDM_DENOM bitfields
34420  */
34421 
34422 /*!
34423  * @name Register XCVR_PLL_LP_SDM_DENOM, field LPM_DENOM_SELECTED[27:0] (RO)
34424  *
34425  * This is the value that is currently being applied to the sigma delta
34426  * modulator, for valid Sigma Delta operation the resulting fraction NUM/DENOM must be in
34427  * the range -0.6 to +0.6
34428  */
34429 /*@{*/
34430 /*! @brief Read current value of the XCVR_PLL_LP_SDM_DENOM_LPM_DENOM_SELECTED field. */
34431 #define XCVR_RD_PLL_LP_SDM_DENOM_LPM_DENOM_SELECTED(base) ((XCVR_PLL_LP_SDM_DENOM_REG(base) & XCVR_PLL_LP_SDM_DENOM_LPM_DENOM_SELECTED_MASK) >> XCVR_PLL_LP_SDM_DENOM_LPM_DENOM_SELECTED_SHIFT)
34432 #define XCVR_BRD_PLL_LP_SDM_DENOM_LPM_DENOM_SELECTED(base) (XCVR_RD_PLL_LP_SDM_DENOM_LPM_DENOM_SELECTED(base))
34433 /*@}*/
34434 
34435 /*******************************************************************************
34436  * XCVR_PLL_DELAY_MATCH - PLL Delay Matching
34437  ******************************************************************************/
34438 
34439 /*!
34440  * @brief XCVR_PLL_DELAY_MATCH - PLL Delay Matching (RW)
34441  *
34442  * Reset value: 0x00000201U
34443  */
34444 /*!
34445  * @name Constants and macros for entire XCVR_PLL_DELAY_MATCH register
34446  */
34447 /*@{*/
34448 #define XCVR_RD_PLL_DELAY_MATCH(base) (XCVR_PLL_DELAY_MATCH_REG(base))
34449 #define XCVR_WR_PLL_DELAY_MATCH(base, value) (XCVR_PLL_DELAY_MATCH_REG(base) = (value))
34450 #define XCVR_RMW_PLL_DELAY_MATCH(base, mask, value) (XCVR_WR_PLL_DELAY_MATCH(base, (XCVR_RD_PLL_DELAY_MATCH(base) & ~(mask)) | (value)))
34451 #define XCVR_SET_PLL_DELAY_MATCH(base, value) (BME_OR32(&XCVR_PLL_DELAY_MATCH_REG(base), (uint32_t)(value)))
34452 #define XCVR_CLR_PLL_DELAY_MATCH(base, value) (BME_AND32(&XCVR_PLL_DELAY_MATCH_REG(base), (uint32_t)(~(value))))
34453 #define XCVR_TOG_PLL_DELAY_MATCH(base, value) (BME_XOR32(&XCVR_PLL_DELAY_MATCH_REG(base), (uint32_t)(value)))
34454 /*@}*/
34455 
34456 /*
34457  * Constants & macros for individual XCVR_PLL_DELAY_MATCH bitfields
34458  */
34459 
34460 /*!
34461  * @name Register XCVR_PLL_DELAY_MATCH, field LP_SDM_DELAY[3:0] (RW)
34462  *
34463  * This register selects the number of clock cycles of the (PLL Sigma Delta
34464  * Clock) to delay the Low Port Sigma Delta modulation of the PLL Loop Divider.
34465  */
34466 /*@{*/
34467 /*! @brief Read current value of the XCVR_PLL_DELAY_MATCH_LP_SDM_DELAY field. */
34468 #define XCVR_RD_PLL_DELAY_MATCH_LP_SDM_DELAY(base) ((XCVR_PLL_DELAY_MATCH_REG(base) & XCVR_PLL_DELAY_MATCH_LP_SDM_DELAY_MASK) >> XCVR_PLL_DELAY_MATCH_LP_SDM_DELAY_SHIFT)
34469 #define XCVR_BRD_PLL_DELAY_MATCH_LP_SDM_DELAY(base) (BME_UBFX32(&XCVR_PLL_DELAY_MATCH_REG(base), XCVR_PLL_DELAY_MATCH_LP_SDM_DELAY_SHIFT, XCVR_PLL_DELAY_MATCH_LP_SDM_DELAY_WIDTH))
34470 
34471 /*! @brief Set the LP_SDM_DELAY field to a new value. */
34472 #define XCVR_WR_PLL_DELAY_MATCH_LP_SDM_DELAY(base, value) (XCVR_RMW_PLL_DELAY_MATCH(base, XCVR_PLL_DELAY_MATCH_LP_SDM_DELAY_MASK, XCVR_PLL_DELAY_MATCH_LP_SDM_DELAY(value)))
34473 #define XCVR_BWR_PLL_DELAY_MATCH_LP_SDM_DELAY(base, value) (BME_BFI32(&XCVR_PLL_DELAY_MATCH_REG(base), ((uint32_t)(value) << XCVR_PLL_DELAY_MATCH_LP_SDM_DELAY_SHIFT), XCVR_PLL_DELAY_MATCH_LP_SDM_DELAY_SHIFT, XCVR_PLL_DELAY_MATCH_LP_SDM_DELAY_WIDTH))
34474 /*@}*/
34475 
34476 /*!
34477  * @name Register XCVR_PLL_DELAY_MATCH, field HPM_SDM_DELAY[11:8] (RW)
34478  *
34479  * This register selects the number of clock cycles of the (PLL Sigma Delta
34480  * Clock divided by 2) to delay the High Port Sigma Delta modulation of the VCO High
34481  * Port Bank LSB. Note that the High Port SDM is clocked by the (PLL Sigma Delta
34482  * Clock) but the modulation is based on a divide by 2 version of this same clock.
34483  */
34484 /*@{*/
34485 /*! @brief Read current value of the XCVR_PLL_DELAY_MATCH_HPM_SDM_DELAY field. */
34486 #define XCVR_RD_PLL_DELAY_MATCH_HPM_SDM_DELAY(base) ((XCVR_PLL_DELAY_MATCH_REG(base) & XCVR_PLL_DELAY_MATCH_HPM_SDM_DELAY_MASK) >> XCVR_PLL_DELAY_MATCH_HPM_SDM_DELAY_SHIFT)
34487 #define XCVR_BRD_PLL_DELAY_MATCH_HPM_SDM_DELAY(base) (BME_UBFX32(&XCVR_PLL_DELAY_MATCH_REG(base), XCVR_PLL_DELAY_MATCH_HPM_SDM_DELAY_SHIFT, XCVR_PLL_DELAY_MATCH_HPM_SDM_DELAY_WIDTH))
34488 
34489 /*! @brief Set the HPM_SDM_DELAY field to a new value. */
34490 #define XCVR_WR_PLL_DELAY_MATCH_HPM_SDM_DELAY(base, value) (XCVR_RMW_PLL_DELAY_MATCH(base, XCVR_PLL_DELAY_MATCH_HPM_SDM_DELAY_MASK, XCVR_PLL_DELAY_MATCH_HPM_SDM_DELAY(value)))
34491 #define XCVR_BWR_PLL_DELAY_MATCH_HPM_SDM_DELAY(base, value) (BME_BFI32(&XCVR_PLL_DELAY_MATCH_REG(base), ((uint32_t)(value) << XCVR_PLL_DELAY_MATCH_HPM_SDM_DELAY_SHIFT), XCVR_PLL_DELAY_MATCH_HPM_SDM_DELAY_SHIFT, XCVR_PLL_DELAY_MATCH_HPM_SDM_DELAY_WIDTH))
34492 /*@}*/
34493 
34494 /*!
34495  * @name Register XCVR_PLL_DELAY_MATCH, field HPM_BANK_DELAY[19:16] (RW)
34496  *
34497  * This register selects the number of clock cycles of the (PLL Sigma Delta
34498  * Clock divided by 2) to delay the High Port modulation of the VCO High Port Bank
34499  * Array.
34500  */
34501 /*@{*/
34502 /*! @brief Read current value of the XCVR_PLL_DELAY_MATCH_HPM_BANK_DELAY field. */
34503 #define XCVR_RD_PLL_DELAY_MATCH_HPM_BANK_DELAY(base) ((XCVR_PLL_DELAY_MATCH_REG(base) & XCVR_PLL_DELAY_MATCH_HPM_BANK_DELAY_MASK) >> XCVR_PLL_DELAY_MATCH_HPM_BANK_DELAY_SHIFT)
34504 #define XCVR_BRD_PLL_DELAY_MATCH_HPM_BANK_DELAY(base) (BME_UBFX32(&XCVR_PLL_DELAY_MATCH_REG(base), XCVR_PLL_DELAY_MATCH_HPM_BANK_DELAY_SHIFT, XCVR_PLL_DELAY_MATCH_HPM_BANK_DELAY_WIDTH))
34505 
34506 /*! @brief Set the HPM_BANK_DELAY field to a new value. */
34507 #define XCVR_WR_PLL_DELAY_MATCH_HPM_BANK_DELAY(base, value) (XCVR_RMW_PLL_DELAY_MATCH(base, XCVR_PLL_DELAY_MATCH_HPM_BANK_DELAY_MASK, XCVR_PLL_DELAY_MATCH_HPM_BANK_DELAY(value)))
34508 #define XCVR_BWR_PLL_DELAY_MATCH_HPM_BANK_DELAY(base, value) (BME_BFI32(&XCVR_PLL_DELAY_MATCH_REG(base), ((uint32_t)(value) << XCVR_PLL_DELAY_MATCH_HPM_BANK_DELAY_SHIFT), XCVR_PLL_DELAY_MATCH_HPM_BANK_DELAY_SHIFT, XCVR_PLL_DELAY_MATCH_HPM_BANK_DELAY_WIDTH))
34509 /*@}*/
34510 
34511 /*******************************************************************************
34512  * XCVR_PLL_CTUNE_CTRL - PLL Coarse Tune Control
34513  ******************************************************************************/
34514 
34515 /*!
34516  * @brief XCVR_PLL_CTUNE_CTRL - PLL Coarse Tune Control (RW)
34517  *
34518  * Reset value: 0x00000000U
34519  */
34520 /*!
34521  * @name Constants and macros for entire XCVR_PLL_CTUNE_CTRL register
34522  */
34523 /*@{*/
34524 #define XCVR_RD_PLL_CTUNE_CTRL(base) (XCVR_PLL_CTUNE_CTRL_REG(base))
34525 #define XCVR_WR_PLL_CTUNE_CTRL(base, value) (XCVR_PLL_CTUNE_CTRL_REG(base) = (value))
34526 #define XCVR_RMW_PLL_CTUNE_CTRL(base, mask, value) (XCVR_WR_PLL_CTUNE_CTRL(base, (XCVR_RD_PLL_CTUNE_CTRL(base) & ~(mask)) | (value)))
34527 #define XCVR_SET_PLL_CTUNE_CTRL(base, value) (BME_OR32(&XCVR_PLL_CTUNE_CTRL_REG(base), (uint32_t)(value)))
34528 #define XCVR_CLR_PLL_CTUNE_CTRL(base, value) (BME_AND32(&XCVR_PLL_CTUNE_CTRL_REG(base), (uint32_t)(~(value))))
34529 #define XCVR_TOG_PLL_CTUNE_CTRL(base, value) (BME_XOR32(&XCVR_PLL_CTUNE_CTRL_REG(base), (uint32_t)(value)))
34530 /*@}*/
34531 
34532 /*
34533  * Constants & macros for individual XCVR_PLL_CTUNE_CTRL bitfields
34534  */
34535 
34536 /*!
34537  * @name Register XCVR_PLL_CTUNE_CTRL, field CTUNE_TARGET_MANUAL[11:0] (RW)
34538  *
34539  * If CTUNE_TD is set, this register is the value that is presented to the
34540  * Coarse Tune Calibrator as the Frequency Target in MHz. The nominal range of this
34541  * target is from 2360 to 2487 in decimal.
34542  */
34543 /*@{*/
34544 /*! @brief Read current value of the XCVR_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL field. */
34545 #define XCVR_RD_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL(base) ((XCVR_PLL_CTUNE_CTRL_REG(base) & XCVR_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK) >> XCVR_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL_SHIFT)
34546 #define XCVR_BRD_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CTRL_REG(base), XCVR_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL_SHIFT, XCVR_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL_WIDTH))
34547 
34548 /*! @brief Set the CTUNE_TARGET_MANUAL field to a new value. */
34549 #define XCVR_WR_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL(base, value) (XCVR_RMW_PLL_CTUNE_CTRL(base, XCVR_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL_MASK, XCVR_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL(value)))
34550 #define XCVR_BWR_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_CTUNE_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL_SHIFT), XCVR_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL_SHIFT, XCVR_PLL_CTUNE_CTRL_CTUNE_TARGET_MANUAL_WIDTH))
34551 /*@}*/
34552 
34553 /*!
34554  * @name Register XCVR_PLL_CTUNE_CTRL, field CTUNE_TD[15] (RW)
34555  *
34556  * If this bit is set, the Frequency Target presented to the Coarse Tune
34557  * Calibrator comes from the CTUNE_TARGET_MANUAL register.
34558  */
34559 /*@{*/
34560 /*! @brief Read current value of the XCVR_PLL_CTUNE_CTRL_CTUNE_TD field. */
34561 #define XCVR_RD_PLL_CTUNE_CTRL_CTUNE_TD(base) ((XCVR_PLL_CTUNE_CTRL_REG(base) & XCVR_PLL_CTUNE_CTRL_CTUNE_TD_MASK) >> XCVR_PLL_CTUNE_CTRL_CTUNE_TD_SHIFT)
34562 #define XCVR_BRD_PLL_CTUNE_CTRL_CTUNE_TD(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CTRL_REG(base), XCVR_PLL_CTUNE_CTRL_CTUNE_TD_SHIFT, XCVR_PLL_CTUNE_CTRL_CTUNE_TD_WIDTH))
34563 
34564 /*! @brief Set the CTUNE_TD field to a new value. */
34565 #define XCVR_WR_PLL_CTUNE_CTRL_CTUNE_TD(base, value) (XCVR_RMW_PLL_CTUNE_CTRL(base, XCVR_PLL_CTUNE_CTRL_CTUNE_TD_MASK, XCVR_PLL_CTUNE_CTRL_CTUNE_TD(value)))
34566 #define XCVR_BWR_PLL_CTUNE_CTRL_CTUNE_TD(base, value) (BME_BFI32(&XCVR_PLL_CTUNE_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_CTUNE_CTRL_CTUNE_TD_SHIFT), XCVR_PLL_CTUNE_CTRL_CTUNE_TD_SHIFT, XCVR_PLL_CTUNE_CTRL_CTUNE_TD_WIDTH))
34567 /*@}*/
34568 
34569 /*!
34570  * @name Register XCVR_PLL_CTUNE_CTRL, field CTUNE_ADJUST[19:16] (RW)
34571  *
34572  * The PLL 17-bit Ripple Counter count used in Coarse Tune Calibration will be
34573  * increased by the value of this register in order to allow for any consistent
34574  * under-counting that might present itself in the analog circuit.
34575  */
34576 /*@{*/
34577 /*! @brief Read current value of the XCVR_PLL_CTUNE_CTRL_CTUNE_ADJUST field. */
34578 #define XCVR_RD_PLL_CTUNE_CTRL_CTUNE_ADJUST(base) ((XCVR_PLL_CTUNE_CTRL_REG(base) & XCVR_PLL_CTUNE_CTRL_CTUNE_ADJUST_MASK) >> XCVR_PLL_CTUNE_CTRL_CTUNE_ADJUST_SHIFT)
34579 #define XCVR_BRD_PLL_CTUNE_CTRL_CTUNE_ADJUST(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CTRL_REG(base), XCVR_PLL_CTUNE_CTRL_CTUNE_ADJUST_SHIFT, XCVR_PLL_CTUNE_CTRL_CTUNE_ADJUST_WIDTH))
34580 
34581 /*! @brief Set the CTUNE_ADJUST field to a new value. */
34582 #define XCVR_WR_PLL_CTUNE_CTRL_CTUNE_ADJUST(base, value) (XCVR_RMW_PLL_CTUNE_CTRL(base, XCVR_PLL_CTUNE_CTRL_CTUNE_ADJUST_MASK, XCVR_PLL_CTUNE_CTRL_CTUNE_ADJUST(value)))
34583 #define XCVR_BWR_PLL_CTUNE_CTRL_CTUNE_ADJUST(base, value) (BME_BFI32(&XCVR_PLL_CTUNE_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_CTUNE_CTRL_CTUNE_ADJUST_SHIFT), XCVR_PLL_CTUNE_CTRL_CTUNE_ADJUST_SHIFT, XCVR_PLL_CTUNE_CTRL_CTUNE_ADJUST_WIDTH))
34584 /*@}*/
34585 
34586 /*!
34587  * @name Register XCVR_PLL_CTUNE_CTRL, field CTUNE_MANUAL[30:24] (RW)
34588  *
34589  * If CTUNE_DIS is set, this register is the value that is applied to the VCO as
34590  * the Coarse Tune Band.
34591  */
34592 /*@{*/
34593 /*! @brief Read current value of the XCVR_PLL_CTUNE_CTRL_CTUNE_MANUAL field. */
34594 #define XCVR_RD_PLL_CTUNE_CTRL_CTUNE_MANUAL(base) ((XCVR_PLL_CTUNE_CTRL_REG(base) & XCVR_PLL_CTUNE_CTRL_CTUNE_MANUAL_MASK) >> XCVR_PLL_CTUNE_CTRL_CTUNE_MANUAL_SHIFT)
34595 #define XCVR_BRD_PLL_CTUNE_CTRL_CTUNE_MANUAL(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CTRL_REG(base), XCVR_PLL_CTUNE_CTRL_CTUNE_MANUAL_SHIFT, XCVR_PLL_CTUNE_CTRL_CTUNE_MANUAL_WIDTH))
34596 
34597 /*! @brief Set the CTUNE_MANUAL field to a new value. */
34598 #define XCVR_WR_PLL_CTUNE_CTRL_CTUNE_MANUAL(base, value) (XCVR_RMW_PLL_CTUNE_CTRL(base, XCVR_PLL_CTUNE_CTRL_CTUNE_MANUAL_MASK, XCVR_PLL_CTUNE_CTRL_CTUNE_MANUAL(value)))
34599 #define XCVR_BWR_PLL_CTUNE_CTRL_CTUNE_MANUAL(base, value) (BME_BFI32(&XCVR_PLL_CTUNE_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_CTUNE_CTRL_CTUNE_MANUAL_SHIFT), XCVR_PLL_CTUNE_CTRL_CTUNE_MANUAL_SHIFT, XCVR_PLL_CTUNE_CTRL_CTUNE_MANUAL_WIDTH))
34600 /*@}*/
34601 
34602 /*!
34603  * @name Register XCVR_PLL_CTUNE_CTRL, field CTUNE_DIS[31] (RW)
34604  *
34605  * If this bit is set, the Coarse Tune Band applied to the VCO comes from the
34606  * CTUNE_MANUAL register.
34607  */
34608 /*@{*/
34609 /*! @brief Read current value of the XCVR_PLL_CTUNE_CTRL_CTUNE_DIS field. */
34610 #define XCVR_RD_PLL_CTUNE_CTRL_CTUNE_DIS(base) ((XCVR_PLL_CTUNE_CTRL_REG(base) & XCVR_PLL_CTUNE_CTRL_CTUNE_DIS_MASK) >> XCVR_PLL_CTUNE_CTRL_CTUNE_DIS_SHIFT)
34611 #define XCVR_BRD_PLL_CTUNE_CTRL_CTUNE_DIS(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CTRL_REG(base), XCVR_PLL_CTUNE_CTRL_CTUNE_DIS_SHIFT, XCVR_PLL_CTUNE_CTRL_CTUNE_DIS_WIDTH))
34612 
34613 /*! @brief Set the CTUNE_DIS field to a new value. */
34614 #define XCVR_WR_PLL_CTUNE_CTRL_CTUNE_DIS(base, value) (XCVR_RMW_PLL_CTUNE_CTRL(base, XCVR_PLL_CTUNE_CTRL_CTUNE_DIS_MASK, XCVR_PLL_CTUNE_CTRL_CTUNE_DIS(value)))
34615 #define XCVR_BWR_PLL_CTUNE_CTRL_CTUNE_DIS(base, value) (BME_BFI32(&XCVR_PLL_CTUNE_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_CTUNE_CTRL_CTUNE_DIS_SHIFT), XCVR_PLL_CTUNE_CTRL_CTUNE_DIS_SHIFT, XCVR_PLL_CTUNE_CTRL_CTUNE_DIS_WIDTH))
34616 /*@}*/
34617 
34618 /*******************************************************************************
34619  * XCVR_PLL_CTUNE_CNT6 - PLL Coarse Tune Count 6
34620  ******************************************************************************/
34621 
34622 /*!
34623  * @brief XCVR_PLL_CTUNE_CNT6 - PLL Coarse Tune Count 6 (RO)
34624  *
34625  * Reset value: 0x00000000U
34626  */
34627 /*!
34628  * @name Constants and macros for entire XCVR_PLL_CTUNE_CNT6 register
34629  */
34630 /*@{*/
34631 #define XCVR_RD_PLL_CTUNE_CNT6(base) (XCVR_PLL_CTUNE_CNT6_REG(base))
34632 /*@}*/
34633 
34634 /*
34635  * Constants & macros for individual XCVR_PLL_CTUNE_CNT6 bitfields
34636  */
34637 
34638 /*!
34639  * @name Register XCVR_PLL_CTUNE_CNT6, field CTUNE_COUNT_6[11:0] (RO)
34640  *
34641  * This is the Ripple counter value used to set coarse tune band bit 6.
34642  */
34643 /*@{*/
34644 /*! @brief Read current value of the XCVR_PLL_CTUNE_CNT6_CTUNE_COUNT_6 field. */
34645 #define XCVR_RD_PLL_CTUNE_CNT6_CTUNE_COUNT_6(base) ((XCVR_PLL_CTUNE_CNT6_REG(base) & XCVR_PLL_CTUNE_CNT6_CTUNE_COUNT_6_MASK) >> XCVR_PLL_CTUNE_CNT6_CTUNE_COUNT_6_SHIFT)
34646 #define XCVR_BRD_PLL_CTUNE_CNT6_CTUNE_COUNT_6(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CNT6_REG(base), XCVR_PLL_CTUNE_CNT6_CTUNE_COUNT_6_SHIFT, XCVR_PLL_CTUNE_CNT6_CTUNE_COUNT_6_WIDTH))
34647 /*@}*/
34648 
34649 /*******************************************************************************
34650  * XCVR_PLL_CTUNE_CNT5_4 - PLL Coarse Tune Counts 5 and 4
34651  ******************************************************************************/
34652 
34653 /*!
34654  * @brief XCVR_PLL_CTUNE_CNT5_4 - PLL Coarse Tune Counts 5 and 4 (RO)
34655  *
34656  * Reset value: 0x00000000U
34657  */
34658 /*!
34659  * @name Constants and macros for entire XCVR_PLL_CTUNE_CNT5_4 register
34660  */
34661 /*@{*/
34662 #define XCVR_RD_PLL_CTUNE_CNT5_4(base) (XCVR_PLL_CTUNE_CNT5_4_REG(base))
34663 /*@}*/
34664 
34665 /*
34666  * Constants & macros for individual XCVR_PLL_CTUNE_CNT5_4 bitfields
34667  */
34668 
34669 /*!
34670  * @name Register XCVR_PLL_CTUNE_CNT5_4, field CTUNE_COUNT_4[11:0] (RO)
34671  *
34672  * This is the Ripple counter value used to set coarse tune band bit 4.
34673  */
34674 /*@{*/
34675 /*! @brief Read current value of the XCVR_PLL_CTUNE_CNT5_4_CTUNE_COUNT_4 field. */
34676 #define XCVR_RD_PLL_CTUNE_CNT5_4_CTUNE_COUNT_4(base) ((XCVR_PLL_CTUNE_CNT5_4_REG(base) & XCVR_PLL_CTUNE_CNT5_4_CTUNE_COUNT_4_MASK) >> XCVR_PLL_CTUNE_CNT5_4_CTUNE_COUNT_4_SHIFT)
34677 #define XCVR_BRD_PLL_CTUNE_CNT5_4_CTUNE_COUNT_4(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CNT5_4_REG(base), XCVR_PLL_CTUNE_CNT5_4_CTUNE_COUNT_4_SHIFT, XCVR_PLL_CTUNE_CNT5_4_CTUNE_COUNT_4_WIDTH))
34678 /*@}*/
34679 
34680 /*!
34681  * @name Register XCVR_PLL_CTUNE_CNT5_4, field CTUNE_COUNT_5[27:16] (RO)
34682  *
34683  * This is the Ripple counter value used to set coarse tune band bit 5.
34684  */
34685 /*@{*/
34686 /*! @brief Read current value of the XCVR_PLL_CTUNE_CNT5_4_CTUNE_COUNT_5 field. */
34687 #define XCVR_RD_PLL_CTUNE_CNT5_4_CTUNE_COUNT_5(base) ((XCVR_PLL_CTUNE_CNT5_4_REG(base) & XCVR_PLL_CTUNE_CNT5_4_CTUNE_COUNT_5_MASK) >> XCVR_PLL_CTUNE_CNT5_4_CTUNE_COUNT_5_SHIFT)
34688 #define XCVR_BRD_PLL_CTUNE_CNT5_4_CTUNE_COUNT_5(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CNT5_4_REG(base), XCVR_PLL_CTUNE_CNT5_4_CTUNE_COUNT_5_SHIFT, XCVR_PLL_CTUNE_CNT5_4_CTUNE_COUNT_5_WIDTH))
34689 /*@}*/
34690 
34691 /*******************************************************************************
34692  * XCVR_PLL_CTUNE_CNT3_2 - PLL Coarse Tune Counts 3 and 2
34693  ******************************************************************************/
34694 
34695 /*!
34696  * @brief XCVR_PLL_CTUNE_CNT3_2 - PLL Coarse Tune Counts 3 and 2 (RO)
34697  *
34698  * Reset value: 0x00000000U
34699  */
34700 /*!
34701  * @name Constants and macros for entire XCVR_PLL_CTUNE_CNT3_2 register
34702  */
34703 /*@{*/
34704 #define XCVR_RD_PLL_CTUNE_CNT3_2(base) (XCVR_PLL_CTUNE_CNT3_2_REG(base))
34705 /*@}*/
34706 
34707 /*
34708  * Constants & macros for individual XCVR_PLL_CTUNE_CNT3_2 bitfields
34709  */
34710 
34711 /*!
34712  * @name Register XCVR_PLL_CTUNE_CNT3_2, field CTUNE_COUNT_2[11:0] (RO)
34713  *
34714  * This is the Ripple counter value used to set coarse tune band bit 2.
34715  */
34716 /*@{*/
34717 /*! @brief Read current value of the XCVR_PLL_CTUNE_CNT3_2_CTUNE_COUNT_2 field. */
34718 #define XCVR_RD_PLL_CTUNE_CNT3_2_CTUNE_COUNT_2(base) ((XCVR_PLL_CTUNE_CNT3_2_REG(base) & XCVR_PLL_CTUNE_CNT3_2_CTUNE_COUNT_2_MASK) >> XCVR_PLL_CTUNE_CNT3_2_CTUNE_COUNT_2_SHIFT)
34719 #define XCVR_BRD_PLL_CTUNE_CNT3_2_CTUNE_COUNT_2(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CNT3_2_REG(base), XCVR_PLL_CTUNE_CNT3_2_CTUNE_COUNT_2_SHIFT, XCVR_PLL_CTUNE_CNT3_2_CTUNE_COUNT_2_WIDTH))
34720 /*@}*/
34721 
34722 /*!
34723  * @name Register XCVR_PLL_CTUNE_CNT3_2, field CTUNE_COUNT_3[27:16] (RO)
34724  *
34725  * This is the Ripple counter value used to set coarse tune band bit 3.
34726  */
34727 /*@{*/
34728 /*! @brief Read current value of the XCVR_PLL_CTUNE_CNT3_2_CTUNE_COUNT_3 field. */
34729 #define XCVR_RD_PLL_CTUNE_CNT3_2_CTUNE_COUNT_3(base) ((XCVR_PLL_CTUNE_CNT3_2_REG(base) & XCVR_PLL_CTUNE_CNT3_2_CTUNE_COUNT_3_MASK) >> XCVR_PLL_CTUNE_CNT3_2_CTUNE_COUNT_3_SHIFT)
34730 #define XCVR_BRD_PLL_CTUNE_CNT3_2_CTUNE_COUNT_3(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CNT3_2_REG(base), XCVR_PLL_CTUNE_CNT3_2_CTUNE_COUNT_3_SHIFT, XCVR_PLL_CTUNE_CNT3_2_CTUNE_COUNT_3_WIDTH))
34731 /*@}*/
34732 
34733 /*******************************************************************************
34734  * XCVR_PLL_CTUNE_CNT1_0 - PLL Coarse Tune Counts 1 and 0
34735  ******************************************************************************/
34736 
34737 /*!
34738  * @brief XCVR_PLL_CTUNE_CNT1_0 - PLL Coarse Tune Counts 1 and 0 (RO)
34739  *
34740  * Reset value: 0x00000000U
34741  */
34742 /*!
34743  * @name Constants and macros for entire XCVR_PLL_CTUNE_CNT1_0 register
34744  */
34745 /*@{*/
34746 #define XCVR_RD_PLL_CTUNE_CNT1_0(base) (XCVR_PLL_CTUNE_CNT1_0_REG(base))
34747 /*@}*/
34748 
34749 /*
34750  * Constants & macros for individual XCVR_PLL_CTUNE_CNT1_0 bitfields
34751  */
34752 
34753 /*!
34754  * @name Register XCVR_PLL_CTUNE_CNT1_0, field CTUNE_COUNT_0[11:0] (RO)
34755  *
34756  * This is the Ripple counter value used to set coarse tune band bit 0.
34757  */
34758 /*@{*/
34759 /*! @brief Read current value of the XCVR_PLL_CTUNE_CNT1_0_CTUNE_COUNT_0 field. */
34760 #define XCVR_RD_PLL_CTUNE_CNT1_0_CTUNE_COUNT_0(base) ((XCVR_PLL_CTUNE_CNT1_0_REG(base) & XCVR_PLL_CTUNE_CNT1_0_CTUNE_COUNT_0_MASK) >> XCVR_PLL_CTUNE_CNT1_0_CTUNE_COUNT_0_SHIFT)
34761 #define XCVR_BRD_PLL_CTUNE_CNT1_0_CTUNE_COUNT_0(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CNT1_0_REG(base), XCVR_PLL_CTUNE_CNT1_0_CTUNE_COUNT_0_SHIFT, XCVR_PLL_CTUNE_CNT1_0_CTUNE_COUNT_0_WIDTH))
34762 /*@}*/
34763 
34764 /*!
34765  * @name Register XCVR_PLL_CTUNE_CNT1_0, field CTUNE_COUNT_1[27:16] (RO)
34766  *
34767  * This is the Ripple counter value used to set coarse tune band bit 1.
34768  */
34769 /*@{*/
34770 /*! @brief Read current value of the XCVR_PLL_CTUNE_CNT1_0_CTUNE_COUNT_1 field. */
34771 #define XCVR_RD_PLL_CTUNE_CNT1_0_CTUNE_COUNT_1(base) ((XCVR_PLL_CTUNE_CNT1_0_REG(base) & XCVR_PLL_CTUNE_CNT1_0_CTUNE_COUNT_1_MASK) >> XCVR_PLL_CTUNE_CNT1_0_CTUNE_COUNT_1_SHIFT)
34772 #define XCVR_BRD_PLL_CTUNE_CNT1_0_CTUNE_COUNT_1(base) (BME_UBFX32(&XCVR_PLL_CTUNE_CNT1_0_REG(base), XCVR_PLL_CTUNE_CNT1_0_CTUNE_COUNT_1_SHIFT, XCVR_PLL_CTUNE_CNT1_0_CTUNE_COUNT_1_WIDTH))
34773 /*@}*/
34774 
34775 /*******************************************************************************
34776  * XCVR_PLL_CTUNE_RESULTS - PLL Coarse Tune Results
34777  ******************************************************************************/
34778 
34779 /*!
34780  * @brief XCVR_PLL_CTUNE_RESULTS - PLL Coarse Tune Results (RO)
34781  *
34782  * Reset value: 0x09620040U
34783  */
34784 /*!
34785  * @name Constants and macros for entire XCVR_PLL_CTUNE_RESULTS register
34786  */
34787 /*@{*/
34788 #define XCVR_RD_PLL_CTUNE_RESULTS(base) (XCVR_PLL_CTUNE_RESULTS_REG(base))
34789 /*@}*/
34790 
34791 /*
34792  * Constants & macros for individual XCVR_PLL_CTUNE_RESULTS bitfields
34793  */
34794 
34795 /*!
34796  * @name Register XCVR_PLL_CTUNE_RESULTS, field CTUNE_SELECTED[6:0] (RO)
34797  *
34798  * This is the current VCO Coarse Tune setting, it is the result of the Coarse
34799  * Tune Calibration, unless overridden using CTUNE_DIS.
34800  */
34801 /*@{*/
34802 /*! @brief Read current value of the XCVR_PLL_CTUNE_RESULTS_CTUNE_SELECTED field. */
34803 #define XCVR_RD_PLL_CTUNE_RESULTS_CTUNE_SELECTED(base) ((XCVR_PLL_CTUNE_RESULTS_REG(base) & XCVR_PLL_CTUNE_RESULTS_CTUNE_SELECTED_MASK) >> XCVR_PLL_CTUNE_RESULTS_CTUNE_SELECTED_SHIFT)
34804 #define XCVR_BRD_PLL_CTUNE_RESULTS_CTUNE_SELECTED(base) (BME_UBFX32(&XCVR_PLL_CTUNE_RESULTS_REG(base), XCVR_PLL_CTUNE_RESULTS_CTUNE_SELECTED_SHIFT, XCVR_PLL_CTUNE_RESULTS_CTUNE_SELECTED_WIDTH))
34805 /*@}*/
34806 
34807 /*!
34808  * @name Register XCVR_PLL_CTUNE_RESULTS, field CTUNE_BEST_DIFF[15:8] (RO)
34809  *
34810  * This is the absolute value of the best difference found during Coarse Tune
34811  * between the targeted frequency count and the actual frequency count.
34812  */
34813 /*@{*/
34814 /*! @brief Read current value of the XCVR_PLL_CTUNE_RESULTS_CTUNE_BEST_DIFF field. */
34815 #define XCVR_RD_PLL_CTUNE_RESULTS_CTUNE_BEST_DIFF(base) ((XCVR_PLL_CTUNE_RESULTS_REG(base) & XCVR_PLL_CTUNE_RESULTS_CTUNE_BEST_DIFF_MASK) >> XCVR_PLL_CTUNE_RESULTS_CTUNE_BEST_DIFF_SHIFT)
34816 #define XCVR_BRD_PLL_CTUNE_RESULTS_CTUNE_BEST_DIFF(base) (BME_UBFX32(&XCVR_PLL_CTUNE_RESULTS_REG(base), XCVR_PLL_CTUNE_RESULTS_CTUNE_BEST_DIFF_SHIFT, XCVR_PLL_CTUNE_RESULTS_CTUNE_BEST_DIFF_WIDTH))
34817 /*@}*/
34818 
34819 /*!
34820  * @name Register XCVR_PLL_CTUNE_RESULTS, field CTUNE_FREQ_TARGET[27:16] (RO)
34821  *
34822  * This is the Frequency Target in MHz that is currently being presented to the
34823  * Coarse Tune Calibrator.
34824  */
34825 /*@{*/
34826 /*! @brief Read current value of the XCVR_PLL_CTUNE_RESULTS_CTUNE_FREQ_TARGET field. */
34827 #define XCVR_RD_PLL_CTUNE_RESULTS_CTUNE_FREQ_TARGET(base) ((XCVR_PLL_CTUNE_RESULTS_REG(base) & XCVR_PLL_CTUNE_RESULTS_CTUNE_FREQ_TARGET_MASK) >> XCVR_PLL_CTUNE_RESULTS_CTUNE_FREQ_TARGET_SHIFT)
34828 #define XCVR_BRD_PLL_CTUNE_RESULTS_CTUNE_FREQ_TARGET(base) (BME_UBFX32(&XCVR_PLL_CTUNE_RESULTS_REG(base), XCVR_PLL_CTUNE_RESULTS_CTUNE_FREQ_TARGET_SHIFT, XCVR_PLL_CTUNE_RESULTS_CTUNE_FREQ_TARGET_WIDTH))
34829 /*@}*/
34830 
34831 /*******************************************************************************
34832  * XCVR_CTRL - Transceiver Control
34833  ******************************************************************************/
34834 
34835 /*!
34836  * @brief XCVR_CTRL - Transceiver Control (RW)
34837  *
34838  * Reset value: 0x00000000U
34839  */
34840 /*!
34841  * @name Constants and macros for entire XCVR_CTRL register
34842  */
34843 /*@{*/
34844 #define XCVR_RD_CTRL(base)       (XCVR_CTRL_REG(base))
34845 #define XCVR_WR_CTRL(base, value) (XCVR_CTRL_REG(base) = (value))
34846 #define XCVR_RMW_CTRL(base, mask, value) (XCVR_WR_CTRL(base, (XCVR_RD_CTRL(base) & ~(mask)) | (value)))
34847 #define XCVR_SET_CTRL(base, value) (BME_OR32(&XCVR_CTRL_REG(base), (uint32_t)(value)))
34848 #define XCVR_CLR_CTRL(base, value) (BME_AND32(&XCVR_CTRL_REG(base), (uint32_t)(~(value))))
34849 #define XCVR_TOG_CTRL(base, value) (BME_XOR32(&XCVR_CTRL_REG(base), (uint32_t)(value)))
34850 /*@}*/
34851 
34852 /*
34853  * Constants & macros for individual XCVR_CTRL bitfields
34854  */
34855 
34856 /*!
34857  * @name Register XCVR_CTRL, field PROTOCOL[2:0] (RW)
34858  *
34859  * This register selects the Radio Communication Protocol.
34860  *
34861  * Values:
34862  * - 0b000 - BLE
34863  * - 0b001 - BLE in MBAN
34864  * - 0b010 - BLE overlap MBAN
34865  * - 0b011 - Reserved
34866  * - 0b100 - Zigbee
34867  * - 0b101 - 802.15.4j
34868  * - 0b110 - 128 Channel FSK
34869  * - 0b111 - 128 Channel GFSK
34870  */
34871 /*@{*/
34872 /*! @brief Read current value of the XCVR_CTRL_PROTOCOL field. */
34873 #define XCVR_RD_CTRL_PROTOCOL(base) ((XCVR_CTRL_REG(base) & XCVR_CTRL_PROTOCOL_MASK) >> XCVR_CTRL_PROTOCOL_SHIFT)
34874 #define XCVR_BRD_CTRL_PROTOCOL(base) (BME_UBFX32(&XCVR_CTRL_REG(base), XCVR_CTRL_PROTOCOL_SHIFT, XCVR_CTRL_PROTOCOL_WIDTH))
34875 
34876 /*! @brief Set the PROTOCOL field to a new value. */
34877 #define XCVR_WR_CTRL_PROTOCOL(base, value) (XCVR_RMW_CTRL(base, XCVR_CTRL_PROTOCOL_MASK, XCVR_CTRL_PROTOCOL(value)))
34878 #define XCVR_BWR_CTRL_PROTOCOL(base, value) (BME_BFI32(&XCVR_CTRL_REG(base), ((uint32_t)(value) << XCVR_CTRL_PROTOCOL_SHIFT), XCVR_CTRL_PROTOCOL_SHIFT, XCVR_CTRL_PROTOCOL_WIDTH))
34879 /*@}*/
34880 
34881 /*!
34882  * @name Register XCVR_CTRL, field TGT_PWR_SRC[5:4] (RW)
34883  *
34884  * For determining transmit power, the TGT_PWR_SRC[1:0] bits control target
34885  * power selection, according to the following table. TGT_PWR_SRC[1:0] TARGET POWER
34886  * SOURCE 00 PA_POWER[3:0] register (XCVR space) 01 BTLE Link Layer 10 Zigbee Link
34887  * Layer (PA_PWR[3:0] register in ZIGBEE space) 11 PROTOCOL[2:0] bits select
34888  * target power source
34889  */
34890 /*@{*/
34891 /*! @brief Read current value of the XCVR_CTRL_TGT_PWR_SRC field. */
34892 #define XCVR_RD_CTRL_TGT_PWR_SRC(base) ((XCVR_CTRL_REG(base) & XCVR_CTRL_TGT_PWR_SRC_MASK) >> XCVR_CTRL_TGT_PWR_SRC_SHIFT)
34893 #define XCVR_BRD_CTRL_TGT_PWR_SRC(base) (BME_UBFX32(&XCVR_CTRL_REG(base), XCVR_CTRL_TGT_PWR_SRC_SHIFT, XCVR_CTRL_TGT_PWR_SRC_WIDTH))
34894 
34895 /*! @brief Set the TGT_PWR_SRC field to a new value. */
34896 #define XCVR_WR_CTRL_TGT_PWR_SRC(base, value) (XCVR_RMW_CTRL(base, XCVR_CTRL_TGT_PWR_SRC_MASK, XCVR_CTRL_TGT_PWR_SRC(value)))
34897 #define XCVR_BWR_CTRL_TGT_PWR_SRC(base, value) (BME_BFI32(&XCVR_CTRL_REG(base), ((uint32_t)(value) << XCVR_CTRL_TGT_PWR_SRC_SHIFT), XCVR_CTRL_TGT_PWR_SRC_SHIFT, XCVR_CTRL_TGT_PWR_SRC_WIDTH))
34898 /*@}*/
34899 
34900 /*!
34901  * @name Register XCVR_CTRL, field REF_CLK_FREQ[7:6] (RW)
34902  *
34903  * This register selects the Reference Clock Frequency for the Radio.
34904  *
34905  * Values:
34906  * - 0b00 - 32 MHz
34907  * - 0b01 - Reserved
34908  * - 0b10 - Reserved
34909  * - 0b11 - Reserved
34910  */
34911 /*@{*/
34912 /*! @brief Read current value of the XCVR_CTRL_REF_CLK_FREQ field. */
34913 #define XCVR_RD_CTRL_REF_CLK_FREQ(base) ((XCVR_CTRL_REG(base) & XCVR_CTRL_REF_CLK_FREQ_MASK) >> XCVR_CTRL_REF_CLK_FREQ_SHIFT)
34914 #define XCVR_BRD_CTRL_REF_CLK_FREQ(base) (BME_UBFX32(&XCVR_CTRL_REG(base), XCVR_CTRL_REF_CLK_FREQ_SHIFT, XCVR_CTRL_REF_CLK_FREQ_WIDTH))
34915 
34916 /*! @brief Set the REF_CLK_FREQ field to a new value. */
34917 #define XCVR_WR_CTRL_REF_CLK_FREQ(base, value) (XCVR_RMW_CTRL(base, XCVR_CTRL_REF_CLK_FREQ_MASK, XCVR_CTRL_REF_CLK_FREQ(value)))
34918 #define XCVR_BWR_CTRL_REF_CLK_FREQ(base, value) (BME_BFI32(&XCVR_CTRL_REG(base), ((uint32_t)(value) << XCVR_CTRL_REF_CLK_FREQ_SHIFT), XCVR_CTRL_REF_CLK_FREQ_SHIFT, XCVR_CTRL_REF_CLK_FREQ_WIDTH))
34919 /*@}*/
34920 
34921 /*******************************************************************************
34922  * XCVR_STATUS - Transceiver Status
34923  ******************************************************************************/
34924 
34925 /*!
34926  * @brief XCVR_STATUS - Transceiver Status (RO)
34927  *
34928  * Reset value: 0x00000000U
34929  */
34930 /*!
34931  * @name Constants and macros for entire XCVR_STATUS register
34932  */
34933 /*@{*/
34934 #define XCVR_RD_STATUS(base)     (XCVR_STATUS_REG(base))
34935 /*@}*/
34936 
34937 /*
34938  * Constants & macros for individual XCVR_STATUS bitfields
34939  */
34940 
34941 /*!
34942  * @name Register XCVR_STATUS, field TSM_COUNT[7:0] (RO)
34943  *
34944  * Reflects the instantaneous value of the TSM counter.
34945  */
34946 /*@{*/
34947 /*! @brief Read current value of the XCVR_STATUS_TSM_COUNT field. */
34948 #define XCVR_RD_STATUS_TSM_COUNT(base) ((XCVR_STATUS_REG(base) & XCVR_STATUS_TSM_COUNT_MASK) >> XCVR_STATUS_TSM_COUNT_SHIFT)
34949 #define XCVR_BRD_STATUS_TSM_COUNT(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_TSM_COUNT_SHIFT, XCVR_STATUS_TSM_COUNT_WIDTH))
34950 /*@}*/
34951 
34952 /*!
34953  * @name Register XCVR_STATUS, field PLL_SEQ_STATE[11:8] (RO)
34954  *
34955  * Reflects the state of the PLL digital state machine.
34956  *
34957  * Values:
34958  * - 0b0000 - PLL OFF
34959  * - 0b0010 - HPMCAL2
34960  */
34961 /*@{*/
34962 /*! @brief Read current value of the XCVR_STATUS_PLL_SEQ_STATE field. */
34963 #define XCVR_RD_STATUS_PLL_SEQ_STATE(base) ((XCVR_STATUS_REG(base) & XCVR_STATUS_PLL_SEQ_STATE_MASK) >> XCVR_STATUS_PLL_SEQ_STATE_SHIFT)
34964 #define XCVR_BRD_STATUS_PLL_SEQ_STATE(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_PLL_SEQ_STATE_SHIFT, XCVR_STATUS_PLL_SEQ_STATE_WIDTH))
34965 /*@}*/
34966 
34967 /*!
34968  * @name Register XCVR_STATUS, field RX_MODE[12] (RO)
34969  *
34970  * Indicates an RX transceiver operation is in progress.
34971  */
34972 /*@{*/
34973 /*! @brief Read current value of the XCVR_STATUS_RX_MODE field. */
34974 #define XCVR_RD_STATUS_RX_MODE(base) ((XCVR_STATUS_REG(base) & XCVR_STATUS_RX_MODE_MASK) >> XCVR_STATUS_RX_MODE_SHIFT)
34975 #define XCVR_BRD_STATUS_RX_MODE(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_RX_MODE_SHIFT, XCVR_STATUS_RX_MODE_WIDTH))
34976 /*@}*/
34977 
34978 /*!
34979  * @name Register XCVR_STATUS, field TX_MODE[13] (RO)
34980  *
34981  * Indicates an TX transceiver operation is in progress.
34982  */
34983 /*@{*/
34984 /*! @brief Read current value of the XCVR_STATUS_TX_MODE field. */
34985 #define XCVR_RD_STATUS_TX_MODE(base) ((XCVR_STATUS_REG(base) & XCVR_STATUS_TX_MODE_MASK) >> XCVR_STATUS_TX_MODE_SHIFT)
34986 #define XCVR_BRD_STATUS_TX_MODE(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_TX_MODE_SHIFT, XCVR_STATUS_TX_MODE_WIDTH))
34987 /*@}*/
34988 
34989 /*!
34990  * @name Register XCVR_STATUS, field BTLE_SYSCLK_REQ[16] (RO)
34991  *
34992  * Reflects the state of the BTLE oscillator request signal. BTLE_SYSCLK_REQ is
34993  * the BTLE control for the RF Oscillator. BTLE will deassert this signal upon
34994  * entering DSM (deep sleep mode) to request oscillator turn-off, and will
34995  * re-assert it prior to exiting DSM. The turn-on leadtime on this signal for exiting
34996  * DSM, is programmable with the BTLE block. This read-only bit can thus be queried
34997  * to ascertain the power-state of BTLE.
34998  */
34999 /*@{*/
35000 /*! @brief Read current value of the XCVR_STATUS_BTLE_SYSCLK_REQ field. */
35001 #define XCVR_RD_STATUS_BTLE_SYSCLK_REQ(base) ((XCVR_STATUS_REG(base) & XCVR_STATUS_BTLE_SYSCLK_REQ_MASK) >> XCVR_STATUS_BTLE_SYSCLK_REQ_SHIFT)
35002 #define XCVR_BRD_STATUS_BTLE_SYSCLK_REQ(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_BTLE_SYSCLK_REQ_SHIFT, XCVR_STATUS_BTLE_SYSCLK_REQ_WIDTH))
35003 /*@}*/
35004 
35005 /*!
35006  * @name Register XCVR_STATUS, field RIF_LL_ACTIVE[17] (RO)
35007  *
35008  * Reflects the state of the BTLE "Link Layer Active" status bit. RIF_LL_ACTIVE
35009  * is to be used by the host as an 'early' indication to prevent host to do any
35010  * operations while BTLE IP is doing transceiver operations, so as to reduce the
35011  * peak power and noise.
35012  */
35013 /*@{*/
35014 /*! @brief Read current value of the XCVR_STATUS_RIF_LL_ACTIVE field. */
35015 #define XCVR_RD_STATUS_RIF_LL_ACTIVE(base) ((XCVR_STATUS_REG(base) & XCVR_STATUS_RIF_LL_ACTIVE_MASK) >> XCVR_STATUS_RIF_LL_ACTIVE_SHIFT)
35016 #define XCVR_BRD_STATUS_RIF_LL_ACTIVE(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_RIF_LL_ACTIVE_SHIFT, XCVR_STATUS_RIF_LL_ACTIVE_WIDTH))
35017 /*@}*/
35018 
35019 /*!
35020  * @name Register XCVR_STATUS, field XTAL_READY[18] (RO)
35021  *
35022  * Oscillator warmup count complete.
35023  *
35024  * Values:
35025  * - 0b0 - Indicates that the RF Oscillator is disabled or has not completed its
35026  *     warmup.
35027  * - 0b1 - Indicates that the RF Oscillator has completed its warmup count and
35028  *     is ready for use.
35029  */
35030 /*@{*/
35031 /*! @brief Read current value of the XCVR_STATUS_XTAL_READY field. */
35032 #define XCVR_RD_STATUS_XTAL_READY(base) ((XCVR_STATUS_REG(base) & XCVR_STATUS_XTAL_READY_MASK) >> XCVR_STATUS_XTAL_READY_SHIFT)
35033 #define XCVR_BRD_STATUS_XTAL_READY(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_XTAL_READY_SHIFT, XCVR_STATUS_XTAL_READY_WIDTH))
35034 /*@}*/
35035 
35036 /*!
35037  * @name Register XCVR_STATUS, field SOC_USING_RF_OSC_CLK[19] (RO)
35038  *
35039  * SoC signal from the CLKGEN that asserts high when the MCG is configured to
35040  * use RF OSC clock as the SoC clock source
35041  */
35042 /*@{*/
35043 /*! @brief Read current value of the XCVR_STATUS_SOC_USING_RF_OSC_CLK field. */
35044 #define XCVR_RD_STATUS_SOC_USING_RF_OSC_CLK(base) ((XCVR_STATUS_REG(base) & XCVR_STATUS_SOC_USING_RF_OSC_CLK_MASK) >> XCVR_STATUS_SOC_USING_RF_OSC_CLK_SHIFT)
35045 #define XCVR_BRD_STATUS_SOC_USING_RF_OSC_CLK(base) (BME_UBFX32(&XCVR_STATUS_REG(base), XCVR_STATUS_SOC_USING_RF_OSC_CLK_SHIFT, XCVR_STATUS_SOC_USING_RF_OSC_CLK_WIDTH))
35046 /*@}*/
35047 
35048 /*******************************************************************************
35049  * XCVR_SOFT_RESET - Soft Reset
35050  ******************************************************************************/
35051 
35052 /*!
35053  * @brief XCVR_SOFT_RESET - Soft Reset (ROZ)
35054  *
35055  * Reset value: 0x00000000U
35056  *
35057  * Transceiver Soft Reset Note: Register not currently implemented.
35058  */
35059 /*!
35060  * @name Constants and macros for entire XCVR_SOFT_RESET register
35061  */
35062 /*@{*/
35063 #define XCVR_RD_SOFT_RESET(base) (XCVR_SOFT_RESET_REG(base))
35064 /*@}*/
35065 
35066 /*******************************************************************************
35067  * XCVR_OVERWRITE_VER - Overwrite Version
35068  ******************************************************************************/
35069 
35070 /*!
35071  * @brief XCVR_OVERWRITE_VER - Overwrite Version (RW)
35072  *
35073  * Reset value: 0x00000000U
35074  *
35075  * The Overwrite Version allows software to store a version number of trim and
35076  * calibration values which are used to overwrite the chip default values in the
35077  * registers. Typically, software would perform the overwrite of the defaults in
35078  * transceiver registers and then write the version number from the file
35079  * containing the overwrite values into this register. This register has no hardware
35080  * connections, it is simply a designated storage location for a version number.
35081  */
35082 /*!
35083  * @name Constants and macros for entire XCVR_OVERWRITE_VER register
35084  */
35085 /*@{*/
35086 #define XCVR_RD_OVERWRITE_VER(base) (XCVR_OVERWRITE_VER_REG(base))
35087 #define XCVR_WR_OVERWRITE_VER(base, value) (XCVR_OVERWRITE_VER_REG(base) = (value))
35088 #define XCVR_RMW_OVERWRITE_VER(base, mask, value) (XCVR_WR_OVERWRITE_VER(base, (XCVR_RD_OVERWRITE_VER(base) & ~(mask)) | (value)))
35089 #define XCVR_SET_OVERWRITE_VER(base, value) (BME_OR32(&XCVR_OVERWRITE_VER_REG(base), (uint32_t)(value)))
35090 #define XCVR_CLR_OVERWRITE_VER(base, value) (BME_AND32(&XCVR_OVERWRITE_VER_REG(base), (uint32_t)(~(value))))
35091 #define XCVR_TOG_OVERWRITE_VER(base, value) (BME_XOR32(&XCVR_OVERWRITE_VER_REG(base), (uint32_t)(value)))
35092 /*@}*/
35093 
35094 /*
35095  * Constants & macros for individual XCVR_OVERWRITE_VER bitfields
35096  */
35097 
35098 /*!
35099  * @name Register XCVR_OVERWRITE_VER, field OVERWRITE_VER[7:0] (RW)
35100  *
35101  * Points to the version number of the overwrites.h file used to initialize the
35102  * device; can be used by software to identify a version-controlled set of
35103  * non-default values to be written into the transceiver's register map.
35104  */
35105 /*@{*/
35106 /*! @brief Read current value of the XCVR_OVERWRITE_VER_OVERWRITE_VER field. */
35107 #define XCVR_RD_OVERWRITE_VER_OVERWRITE_VER(base) ((XCVR_OVERWRITE_VER_REG(base) & XCVR_OVERWRITE_VER_OVERWRITE_VER_MASK) >> XCVR_OVERWRITE_VER_OVERWRITE_VER_SHIFT)
35108 #define XCVR_BRD_OVERWRITE_VER_OVERWRITE_VER(base) (BME_UBFX32(&XCVR_OVERWRITE_VER_REG(base), XCVR_OVERWRITE_VER_OVERWRITE_VER_SHIFT, XCVR_OVERWRITE_VER_OVERWRITE_VER_WIDTH))
35109 
35110 /*! @brief Set the OVERWRITE_VER field to a new value. */
35111 #define XCVR_WR_OVERWRITE_VER_OVERWRITE_VER(base, value) (XCVR_RMW_OVERWRITE_VER(base, XCVR_OVERWRITE_VER_OVERWRITE_VER_MASK, XCVR_OVERWRITE_VER_OVERWRITE_VER(value)))
35112 #define XCVR_BWR_OVERWRITE_VER_OVERWRITE_VER(base, value) (BME_BFI32(&XCVR_OVERWRITE_VER_REG(base), ((uint32_t)(value) << XCVR_OVERWRITE_VER_OVERWRITE_VER_SHIFT), XCVR_OVERWRITE_VER_OVERWRITE_VER_SHIFT, XCVR_OVERWRITE_VER_OVERWRITE_VER_WIDTH))
35113 /*@}*/
35114 
35115 /*******************************************************************************
35116  * XCVR_DMA_CTRL - DMA Control
35117  ******************************************************************************/
35118 
35119 /*!
35120  * @brief XCVR_DMA_CTRL - DMA Control (RW)
35121  *
35122  * Reset value: 0x00000000U
35123  *
35124  * Transceiver DMA per-channel enable register. Transceiver DMA is intended for
35125  * engineering evaluation only. If DMA_I_EN and DMA_Q_EN are both set, I channel
35126  * samples appear in register field DMA_DATA[DMA_DATA_11_0] (lower halfword), and
35127  * Q channel samples appears in DMA_DATA[DMA_DATA_27_16] (upper halfword).
35128  */
35129 /*!
35130  * @name Constants and macros for entire XCVR_DMA_CTRL register
35131  */
35132 /*@{*/
35133 #define XCVR_RD_DMA_CTRL(base)   (XCVR_DMA_CTRL_REG(base))
35134 #define XCVR_WR_DMA_CTRL(base, value) (XCVR_DMA_CTRL_REG(base) = (value))
35135 #define XCVR_RMW_DMA_CTRL(base, mask, value) (XCVR_WR_DMA_CTRL(base, (XCVR_RD_DMA_CTRL(base) & ~(mask)) | (value)))
35136 #define XCVR_SET_DMA_CTRL(base, value) (BME_OR32(&XCVR_DMA_CTRL_REG(base), (uint32_t)(value)))
35137 #define XCVR_CLR_DMA_CTRL(base, value) (BME_AND32(&XCVR_DMA_CTRL_REG(base), (uint32_t)(~(value))))
35138 #define XCVR_TOG_DMA_CTRL(base, value) (BME_XOR32(&XCVR_DMA_CTRL_REG(base), (uint32_t)(value)))
35139 /*@}*/
35140 
35141 /*
35142  * Constants & macros for individual XCVR_DMA_CTRL bitfields
35143  */
35144 
35145 /*!
35146  * @name Register XCVR_DMA_CTRL, field DMA_I_EN[0] (RW)
35147  *
35148  * DMA I Enable
35149  *
35150  * Values:
35151  * - 0b0 - Transceiver I channel DMA disabled.
35152  * - 0b1 - Enable the transceiver DMA engine to store RX_DIG I channel outputs
35153  *     to system memory.
35154  */
35155 /*@{*/
35156 /*! @brief Read current value of the XCVR_DMA_CTRL_DMA_I_EN field. */
35157 #define XCVR_RD_DMA_CTRL_DMA_I_EN(base) ((XCVR_DMA_CTRL_REG(base) & XCVR_DMA_CTRL_DMA_I_EN_MASK) >> XCVR_DMA_CTRL_DMA_I_EN_SHIFT)
35158 #define XCVR_BRD_DMA_CTRL_DMA_I_EN(base) (BME_UBFX32(&XCVR_DMA_CTRL_REG(base), XCVR_DMA_CTRL_DMA_I_EN_SHIFT, XCVR_DMA_CTRL_DMA_I_EN_WIDTH))
35159 
35160 /*! @brief Set the DMA_I_EN field to a new value. */
35161 #define XCVR_WR_DMA_CTRL_DMA_I_EN(base, value) (XCVR_RMW_DMA_CTRL(base, XCVR_DMA_CTRL_DMA_I_EN_MASK, XCVR_DMA_CTRL_DMA_I_EN(value)))
35162 #define XCVR_BWR_DMA_CTRL_DMA_I_EN(base, value) (BME_BFI32(&XCVR_DMA_CTRL_REG(base), ((uint32_t)(value) << XCVR_DMA_CTRL_DMA_I_EN_SHIFT), XCVR_DMA_CTRL_DMA_I_EN_SHIFT, XCVR_DMA_CTRL_DMA_I_EN_WIDTH))
35163 /*@}*/
35164 
35165 /*!
35166  * @name Register XCVR_DMA_CTRL, field DMA_Q_EN[1] (RW)
35167  *
35168  * DMA Q Enable
35169  *
35170  * Values:
35171  * - 0b0 - Transceiver Q channel DMA disabled.
35172  * - 0b1 - Enable the transceiver DMA engine to store RX_DIG Q channel outputs
35173  *     to system memory.
35174  */
35175 /*@{*/
35176 /*! @brief Read current value of the XCVR_DMA_CTRL_DMA_Q_EN field. */
35177 #define XCVR_RD_DMA_CTRL_DMA_Q_EN(base) ((XCVR_DMA_CTRL_REG(base) & XCVR_DMA_CTRL_DMA_Q_EN_MASK) >> XCVR_DMA_CTRL_DMA_Q_EN_SHIFT)
35178 #define XCVR_BRD_DMA_CTRL_DMA_Q_EN(base) (BME_UBFX32(&XCVR_DMA_CTRL_REG(base), XCVR_DMA_CTRL_DMA_Q_EN_SHIFT, XCVR_DMA_CTRL_DMA_Q_EN_WIDTH))
35179 
35180 /*! @brief Set the DMA_Q_EN field to a new value. */
35181 #define XCVR_WR_DMA_CTRL_DMA_Q_EN(base, value) (XCVR_RMW_DMA_CTRL(base, XCVR_DMA_CTRL_DMA_Q_EN_MASK, XCVR_DMA_CTRL_DMA_Q_EN(value)))
35182 #define XCVR_BWR_DMA_CTRL_DMA_Q_EN(base, value) (BME_BFI32(&XCVR_DMA_CTRL_REG(base), ((uint32_t)(value) << XCVR_DMA_CTRL_DMA_Q_EN_SHIFT), XCVR_DMA_CTRL_DMA_Q_EN_SHIFT, XCVR_DMA_CTRL_DMA_Q_EN_WIDTH))
35183 /*@}*/
35184 
35185 /*******************************************************************************
35186  * XCVR_DMA_DATA - DMA Data
35187  ******************************************************************************/
35188 
35189 /*!
35190  * @brief XCVR_DMA_DATA - DMA Data (RO)
35191  *
35192  * Reset value: 0x00000000U
35193  *
35194  * Transceiver DMA Data. Not intended to be read directly by application
35195  * software, this register is merely an address slot where the SoC DMA controller can
35196  * access the RX_DIG samples to be transferred to memory. After enabling
35197  * transceiver DMA, the first sample pair should be discarded due to DMA controller
35198  * latency; all subsequent samples are valid
35199  */
35200 /*!
35201  * @name Constants and macros for entire XCVR_DMA_DATA register
35202  */
35203 /*@{*/
35204 #define XCVR_RD_DMA_DATA(base)   (XCVR_DMA_DATA_REG(base))
35205 /*@}*/
35206 
35207 /*
35208  * Constants & macros for individual XCVR_DMA_DATA bitfields
35209  */
35210 
35211 /*!
35212  * @name Register XCVR_DMA_DATA, field DMA_DATA_11_0[11:0] (RO)
35213  *
35214  * Reflection of the RX_DIG DMA data to be stored to system memory. The
35215  * transceiver DMA engine acquires 12-bit samples from RX_DIG, and deposits them in this
35216  * register field. If DMA I channel is enabled, i.e. DMA_CTRL[DMA_I_EN]=1, then
35217  * this register field contains I channel samples; otherwise it contains Q channel
35218  * samples. For single-channel mode, this register field represents the first
35219  * consecutive RX_DIG sample of the sample-pair; for dual-channel mode, I and Q
35220  * samples are captured simultaneously.
35221  */
35222 /*@{*/
35223 /*! @brief Read current value of the XCVR_DMA_DATA_DMA_DATA_11_0 field. */
35224 #define XCVR_RD_DMA_DATA_DMA_DATA_11_0(base) ((XCVR_DMA_DATA_REG(base) & XCVR_DMA_DATA_DMA_DATA_11_0_MASK) >> XCVR_DMA_DATA_DMA_DATA_11_0_SHIFT)
35225 #define XCVR_BRD_DMA_DATA_DMA_DATA_11_0(base) (BME_UBFX32(&XCVR_DMA_DATA_REG(base), XCVR_DMA_DATA_DMA_DATA_11_0_SHIFT, XCVR_DMA_DATA_DMA_DATA_11_0_WIDTH))
35226 /*@}*/
35227 
35228 /*!
35229  * @name Register XCVR_DMA_DATA, field DMA_DATA_27_16[27:16] (RO)
35230  *
35231  * Reflection of the RX_DIG DMA data to be stored to system memory. The
35232  * transceiver DMA engine acquires 12-bit samples from RX_DIG, and deposits them in this
35233  * register field. If DMA Q channel is enabled, i.e. DMA_CTRL[DMA_Q_EN]=1, then
35234  * this register field contains Q channel samples; otherwise it contains I channel
35235  * samples. For single-channel mode, this register field represents the second
35236  * consecutive RX_DIG sample of the sample-pair; for dual-channel mode, I and Q
35237  * samples are captured simultaneously.
35238  */
35239 /*@{*/
35240 /*! @brief Read current value of the XCVR_DMA_DATA_DMA_DATA_27_16 field. */
35241 #define XCVR_RD_DMA_DATA_DMA_DATA_27_16(base) ((XCVR_DMA_DATA_REG(base) & XCVR_DMA_DATA_DMA_DATA_27_16_MASK) >> XCVR_DMA_DATA_DMA_DATA_27_16_SHIFT)
35242 #define XCVR_BRD_DMA_DATA_DMA_DATA_27_16(base) (BME_UBFX32(&XCVR_DMA_DATA_REG(base), XCVR_DMA_DATA_DMA_DATA_27_16_SHIFT, XCVR_DMA_DATA_DMA_DATA_27_16_WIDTH))
35243 /*@}*/
35244 
35245 /*******************************************************************************
35246  * XCVR_DTEST_CTRL - Digital Test Control
35247  ******************************************************************************/
35248 
35249 /*!
35250  * @brief XCVR_DTEST_CTRL - Digital Test Control (RW)
35251  *
35252  * Reset value: 0x00000000U
35253  *
35254  * Digital Test Control. Allows selection and enablement of a page of DTEST
35255  * signals to appear on the SoC DTEST pins. This register configures only the
35256  * transceiver for DTEST mode; since DTEST pads on the SoC are multiplexed with other
35257  * functions, SoC Port Pin programming is also required for each DTEST output
35258  */
35259 /*!
35260  * @name Constants and macros for entire XCVR_DTEST_CTRL register
35261  */
35262 /*@{*/
35263 #define XCVR_RD_DTEST_CTRL(base) (XCVR_DTEST_CTRL_REG(base))
35264 #define XCVR_WR_DTEST_CTRL(base, value) (XCVR_DTEST_CTRL_REG(base) = (value))
35265 #define XCVR_RMW_DTEST_CTRL(base, mask, value) (XCVR_WR_DTEST_CTRL(base, (XCVR_RD_DTEST_CTRL(base) & ~(mask)) | (value)))
35266 #define XCVR_SET_DTEST_CTRL(base, value) (BME_OR32(&XCVR_DTEST_CTRL_REG(base), (uint32_t)(value)))
35267 #define XCVR_CLR_DTEST_CTRL(base, value) (BME_AND32(&XCVR_DTEST_CTRL_REG(base), (uint32_t)(~(value))))
35268 #define XCVR_TOG_DTEST_CTRL(base, value) (BME_XOR32(&XCVR_DTEST_CTRL_REG(base), (uint32_t)(value)))
35269 /*@}*/
35270 
35271 /*
35272  * Constants & macros for individual XCVR_DTEST_CTRL bitfields
35273  */
35274 
35275 /*!
35276  * @name Register XCVR_DTEST_CTRL, field DTEST_PAGE[5:0] (RW)
35277  *
35278  * DTEST Page signal assignments are defined in a spreadsheet located at
35279  * http://compass.freescale.net/livelink/livelink/open/231923338.
35280  */
35281 /*@{*/
35282 /*! @brief Read current value of the XCVR_DTEST_CTRL_DTEST_PAGE field. */
35283 #define XCVR_RD_DTEST_CTRL_DTEST_PAGE(base) ((XCVR_DTEST_CTRL_REG(base) & XCVR_DTEST_CTRL_DTEST_PAGE_MASK) >> XCVR_DTEST_CTRL_DTEST_PAGE_SHIFT)
35284 #define XCVR_BRD_DTEST_CTRL_DTEST_PAGE(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTEST_CTRL_DTEST_PAGE_SHIFT, XCVR_DTEST_CTRL_DTEST_PAGE_WIDTH))
35285 
35286 /*! @brief Set the DTEST_PAGE field to a new value. */
35287 #define XCVR_WR_DTEST_CTRL_DTEST_PAGE(base, value) (XCVR_RMW_DTEST_CTRL(base, XCVR_DTEST_CTRL_DTEST_PAGE_MASK, XCVR_DTEST_CTRL_DTEST_PAGE(value)))
35288 #define XCVR_BWR_DTEST_CTRL_DTEST_PAGE(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((uint32_t)(value) << XCVR_DTEST_CTRL_DTEST_PAGE_SHIFT), XCVR_DTEST_CTRL_DTEST_PAGE_SHIFT, XCVR_DTEST_CTRL_DTEST_PAGE_WIDTH))
35289 /*@}*/
35290 
35291 /*!
35292  * @name Register XCVR_DTEST_CTRL, field DTEST_EN[7] (RW)
35293  *
35294  * DTEST enable
35295  *
35296  * Values:
35297  * - 0b0 - Disables DTEST. The IC's DTEST pins assume their mission function.
35298  * - 0b1 - Enables DTEST. The contents of the selected page (DTEST_PAGE) will
35299  *     appear on the IC's DTEST output pins.
35300  */
35301 /*@{*/
35302 /*! @brief Read current value of the XCVR_DTEST_CTRL_DTEST_EN field. */
35303 #define XCVR_RD_DTEST_CTRL_DTEST_EN(base) ((XCVR_DTEST_CTRL_REG(base) & XCVR_DTEST_CTRL_DTEST_EN_MASK) >> XCVR_DTEST_CTRL_DTEST_EN_SHIFT)
35304 #define XCVR_BRD_DTEST_CTRL_DTEST_EN(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTEST_CTRL_DTEST_EN_SHIFT, XCVR_DTEST_CTRL_DTEST_EN_WIDTH))
35305 
35306 /*! @brief Set the DTEST_EN field to a new value. */
35307 #define XCVR_WR_DTEST_CTRL_DTEST_EN(base, value) (XCVR_RMW_DTEST_CTRL(base, XCVR_DTEST_CTRL_DTEST_EN_MASK, XCVR_DTEST_CTRL_DTEST_EN(value)))
35308 #define XCVR_BWR_DTEST_CTRL_DTEST_EN(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((uint32_t)(value) << XCVR_DTEST_CTRL_DTEST_EN_SHIFT), XCVR_DTEST_CTRL_DTEST_EN_SHIFT, XCVR_DTEST_CTRL_DTEST_EN_WIDTH))
35309 /*@}*/
35310 
35311 /*!
35312  * @name Register XCVR_DTEST_CTRL, field GPIO0_OVLAY_PIN[11:8] (RW)
35313  *
35314  * The TSM-controlled output GPIO0_TRIG_EN can be routed to any DTEST pin,
35315  * regardless of page selection (DTEST_PAGE), replacing the nominal page-selected
35316  * output for that pin. When TSM_GPIO_OVLAY_0 = 1, this register selects the DTEST
35317  * pin onto which GPIO0_TRIG_EN will appear, any of DTEST0 - DTEST13. When
35318  * TSM_GPIO_OVLAY_0 = 0, this register is ignored, and the DTEST Page Table dictates the
35319  * node that appears on each DTEST pin.
35320  */
35321 /*@{*/
35322 /*! @brief Read current value of the XCVR_DTEST_CTRL_GPIO0_OVLAY_PIN field. */
35323 #define XCVR_RD_DTEST_CTRL_GPIO0_OVLAY_PIN(base) ((XCVR_DTEST_CTRL_REG(base) & XCVR_DTEST_CTRL_GPIO0_OVLAY_PIN_MASK) >> XCVR_DTEST_CTRL_GPIO0_OVLAY_PIN_SHIFT)
35324 #define XCVR_BRD_DTEST_CTRL_GPIO0_OVLAY_PIN(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTEST_CTRL_GPIO0_OVLAY_PIN_SHIFT, XCVR_DTEST_CTRL_GPIO0_OVLAY_PIN_WIDTH))
35325 
35326 /*! @brief Set the GPIO0_OVLAY_PIN field to a new value. */
35327 #define XCVR_WR_DTEST_CTRL_GPIO0_OVLAY_PIN(base, value) (XCVR_RMW_DTEST_CTRL(base, XCVR_DTEST_CTRL_GPIO0_OVLAY_PIN_MASK, XCVR_DTEST_CTRL_GPIO0_OVLAY_PIN(value)))
35328 #define XCVR_BWR_DTEST_CTRL_GPIO0_OVLAY_PIN(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((uint32_t)(value) << XCVR_DTEST_CTRL_GPIO0_OVLAY_PIN_SHIFT), XCVR_DTEST_CTRL_GPIO0_OVLAY_PIN_SHIFT, XCVR_DTEST_CTRL_GPIO0_OVLAY_PIN_WIDTH))
35329 /*@}*/
35330 
35331 /*!
35332  * @name Register XCVR_DTEST_CTRL, field GPIO1_OVLAY_PIN[15:12] (RW)
35333  *
35334  * The TSM-controlled output GPIO1_TRIG_EN can be routed to any DTEST pin,
35335  * regardless of page selection (DTEST_PAGE), replacing the nominal page-selected
35336  * output for that pin. When TSM_GPIO_OVLAY_1 = 1, this register selects the DTEST
35337  * pin onto which GPIO1_TRIG_EN will appear, any of DTEST0 - DTEST13. When
35338  * TSM_GPIO_OVLAY_1 = 0, this register is ignored, and the DTEST Page Table dictates the
35339  * node that appears on each DTEST pin.
35340  */
35341 /*@{*/
35342 /*! @brief Read current value of the XCVR_DTEST_CTRL_GPIO1_OVLAY_PIN field. */
35343 #define XCVR_RD_DTEST_CTRL_GPIO1_OVLAY_PIN(base) ((XCVR_DTEST_CTRL_REG(base) & XCVR_DTEST_CTRL_GPIO1_OVLAY_PIN_MASK) >> XCVR_DTEST_CTRL_GPIO1_OVLAY_PIN_SHIFT)
35344 #define XCVR_BRD_DTEST_CTRL_GPIO1_OVLAY_PIN(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTEST_CTRL_GPIO1_OVLAY_PIN_SHIFT, XCVR_DTEST_CTRL_GPIO1_OVLAY_PIN_WIDTH))
35345 
35346 /*! @brief Set the GPIO1_OVLAY_PIN field to a new value. */
35347 #define XCVR_WR_DTEST_CTRL_GPIO1_OVLAY_PIN(base, value) (XCVR_RMW_DTEST_CTRL(base, XCVR_DTEST_CTRL_GPIO1_OVLAY_PIN_MASK, XCVR_DTEST_CTRL_GPIO1_OVLAY_PIN(value)))
35348 #define XCVR_BWR_DTEST_CTRL_GPIO1_OVLAY_PIN(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((uint32_t)(value) << XCVR_DTEST_CTRL_GPIO1_OVLAY_PIN_SHIFT), XCVR_DTEST_CTRL_GPIO1_OVLAY_PIN_SHIFT, XCVR_DTEST_CTRL_GPIO1_OVLAY_PIN_WIDTH))
35349 /*@}*/
35350 
35351 /*!
35352  * @name Register XCVR_DTEST_CTRL, field TSM_GPIO_OVLAY_0[16] (RW)
35353  *
35354  * The TSM-controlled output GPIO0_TRIG_EN can be routed to any DTEST pin,
35355  * regardless of page selection (DTEST_PAGE), replacing the nominal page-selected
35356  * output for that pin. When TSM_GPIO_OVLAY_0 = 1, the register GPIO0_OVLAY_PIN[3:0]
35357  * selects the DTEST pin on which GPIO0_TRIG_EN will appear, any of DTEST0 -
35358  * DTEST13. When TSM_GPIO_OVLAY_0 = 0, there is no overlay, and the DTEST Page Table
35359  * dictates the node that appears on each DTEST pin.
35360  *
35361  * Values:
35362  * - 0b0 - there is no overlay, and the DTEST Page Table dictates the node that
35363  *     appears on each DTEST pin.
35364  * - 0b1 - the register GPIO0_OVLAY_PIN[3:0] selects the DTEST pin on which
35365  *     GPIO0_TRIG_EN will appear.
35366  */
35367 /*@{*/
35368 /*! @brief Read current value of the XCVR_DTEST_CTRL_TSM_GPIO_OVLAY_0 field. */
35369 #define XCVR_RD_DTEST_CTRL_TSM_GPIO_OVLAY_0(base) ((XCVR_DTEST_CTRL_REG(base) & XCVR_DTEST_CTRL_TSM_GPIO_OVLAY_0_MASK) >> XCVR_DTEST_CTRL_TSM_GPIO_OVLAY_0_SHIFT)
35370 #define XCVR_BRD_DTEST_CTRL_TSM_GPIO_OVLAY_0(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTEST_CTRL_TSM_GPIO_OVLAY_0_SHIFT, XCVR_DTEST_CTRL_TSM_GPIO_OVLAY_0_WIDTH))
35371 
35372 /*! @brief Set the TSM_GPIO_OVLAY_0 field to a new value. */
35373 #define XCVR_WR_DTEST_CTRL_TSM_GPIO_OVLAY_0(base, value) (XCVR_RMW_DTEST_CTRL(base, XCVR_DTEST_CTRL_TSM_GPIO_OVLAY_0_MASK, XCVR_DTEST_CTRL_TSM_GPIO_OVLAY_0(value)))
35374 #define XCVR_BWR_DTEST_CTRL_TSM_GPIO_OVLAY_0(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((uint32_t)(value) << XCVR_DTEST_CTRL_TSM_GPIO_OVLAY_0_SHIFT), XCVR_DTEST_CTRL_TSM_GPIO_OVLAY_0_SHIFT, XCVR_DTEST_CTRL_TSM_GPIO_OVLAY_0_WIDTH))
35375 /*@}*/
35376 
35377 /*!
35378  * @name Register XCVR_DTEST_CTRL, field TSM_GPIO_OVLAY_1[17] (RW)
35379  *
35380  * The TSM-controlled output GPIO1_TRIG_EN can be routed to any DTEST pin,
35381  * regardless of page selection (DTEST_PAGE), replacing the nominal page-selected
35382  * output for that pin. When TSM_GPIO_OVLAY_1 = 1, the register GPIO1_OVLAY_PIN[3:0]
35383  * selects the DTEST pin on which GPIO1_TRIG_EN will appear, any of DTEST0 -
35384  * DTEST13. When TSM_GPIO_OVLAY_1 = 0, there is no overlay, and the DTEST Page Table
35385  * dictates the node that appears on each DTEST pin.
35386  *
35387  * Values:
35388  * - 0b0 - there is no overlay, and the DTEST Page Table dictates the node that
35389  *     appears on each DTEST pin.
35390  * - 0b1 - the register GPIO1_OVLAY_PIN[3:0] selects the DTEST pin on which
35391  *     GPIO1_TRIG_EN will appear.
35392  */
35393 /*@{*/
35394 /*! @brief Read current value of the XCVR_DTEST_CTRL_TSM_GPIO_OVLAY_1 field. */
35395 #define XCVR_RD_DTEST_CTRL_TSM_GPIO_OVLAY_1(base) ((XCVR_DTEST_CTRL_REG(base) & XCVR_DTEST_CTRL_TSM_GPIO_OVLAY_1_MASK) >> XCVR_DTEST_CTRL_TSM_GPIO_OVLAY_1_SHIFT)
35396 #define XCVR_BRD_DTEST_CTRL_TSM_GPIO_OVLAY_1(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTEST_CTRL_TSM_GPIO_OVLAY_1_SHIFT, XCVR_DTEST_CTRL_TSM_GPIO_OVLAY_1_WIDTH))
35397 
35398 /*! @brief Set the TSM_GPIO_OVLAY_1 field to a new value. */
35399 #define XCVR_WR_DTEST_CTRL_TSM_GPIO_OVLAY_1(base, value) (XCVR_RMW_DTEST_CTRL(base, XCVR_DTEST_CTRL_TSM_GPIO_OVLAY_1_MASK, XCVR_DTEST_CTRL_TSM_GPIO_OVLAY_1(value)))
35400 #define XCVR_BWR_DTEST_CTRL_TSM_GPIO_OVLAY_1(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((uint32_t)(value) << XCVR_DTEST_CTRL_TSM_GPIO_OVLAY_1_SHIFT), XCVR_DTEST_CTRL_TSM_GPIO_OVLAY_1_SHIFT, XCVR_DTEST_CTRL_TSM_GPIO_OVLAY_1_WIDTH))
35401 /*@}*/
35402 
35403 /*!
35404  * @name Register XCVR_DTEST_CTRL, field DTEST_SHFT[26:24] (RW)
35405  *
35406  * This register field DTEST_SHFT[1:0] control the amount of "arithmetic shift",
35407  * which can optionally be applied to DTEST output busses. DTEST_SHFT affects
35408  * only 2 DTEST output busses: PLL_RIPPLE_COUNTER[16:0] on DTEST page: PLLRIPPLE
35409  * (0x02). Shift is to the left (magnitude increasing) RX_DIG_IQ[11:0] on DTEST
35410  * page: RXDIGIQ (0x0E). Shift is to the right (magnitude decreasing) The bits of
35411  * PLL_RIPPLE_COUNTER[16:0], an unsigned value, are shifted by DTEST_SHFT[1:0]
35412  * according to the following table DTEST_SHFT[1:0] THESE BITS APPEAR ON DTEST[13:0]
35413  * 00 PLL_RIPPLE_COUNTER[16:3] 01 PLL_RIPPLE_COUNTER[15:2] 10
35414  * PLL_RIPPLE_COUNTER[14:1] 11 PLL_RIPPLE_COUNTER[13:0] The bits of RX_DIG_IQ[11:0], a signed value,
35415  * are shifted/sign-extended by DTEST_SHFT[1:0] according to the following table
35416  * DTEST_SHFT[1:0] THESE BITS APPEAR ON DTEST[13:2] 00 RX_DIG_IQ[11:0] (no
35417  * shift) 01 RX_DIG_IQ[11],RX_DIG_IQ[11:1] (right shift by 1) 10
35418  * RX_DIG_IQ[11],RX_DIG_IQ[11],RX_DIG_IQ[11:2] (right shift by 2) 11 RX_DIG_IQ[11:0] (no shift)
35419  */
35420 /*@{*/
35421 /*! @brief Read current value of the XCVR_DTEST_CTRL_DTEST_SHFT field. */
35422 #define XCVR_RD_DTEST_CTRL_DTEST_SHFT(base) ((XCVR_DTEST_CTRL_REG(base) & XCVR_DTEST_CTRL_DTEST_SHFT_MASK) >> XCVR_DTEST_CTRL_DTEST_SHFT_SHIFT)
35423 #define XCVR_BRD_DTEST_CTRL_DTEST_SHFT(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTEST_CTRL_DTEST_SHFT_SHIFT, XCVR_DTEST_CTRL_DTEST_SHFT_WIDTH))
35424 
35425 /*! @brief Set the DTEST_SHFT field to a new value. */
35426 #define XCVR_WR_DTEST_CTRL_DTEST_SHFT(base, value) (XCVR_RMW_DTEST_CTRL(base, XCVR_DTEST_CTRL_DTEST_SHFT_MASK, XCVR_DTEST_CTRL_DTEST_SHFT(value)))
35427 #define XCVR_BWR_DTEST_CTRL_DTEST_SHFT(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((uint32_t)(value) << XCVR_DTEST_CTRL_DTEST_SHFT_SHIFT), XCVR_DTEST_CTRL_DTEST_SHFT_SHIFT, XCVR_DTEST_CTRL_DTEST_SHFT_WIDTH))
35428 /*@}*/
35429 
35430 /*!
35431  * @name Register XCVR_DTEST_CTRL, field RAW_MODE_I[28] (RW)
35432  *
35433  * DTEST I Channel Raw Mode allows raw, unfiltered ADC samples to be brought out
35434  * to DTEST pins on the RXDIGIQ DTEST page. In raw mode, 2 5-bit ADC samples are
35435  * concatenated into a single 12-bit DMA sample. DMA transfers these samples to
35436  * memory in the same way it transfers filtered samples. Raw mode is only
35437  * supported when the RX_DIG is programmed to decimate-by-2. The procedure to active Raw
35438  * mode on I channel is as follows: 1. RX_DIG_CTRL[RX_ADC_RAW_EN]=1 2.
35439  * RX_DIG_CTRL[RX_DEC_FILT_OSR]=0 3. DTEST_CTRL[DTEST_PAGE]=0x0E (RXDIGIQ) 4.
35440  * DTEST_CTRL[DTEST_EN]=1 5. DTEST_CTRL[RAW_MODE_I]=1
35441  */
35442 /*@{*/
35443 /*! @brief Read current value of the XCVR_DTEST_CTRL_RAW_MODE_I field. */
35444 #define XCVR_RD_DTEST_CTRL_RAW_MODE_I(base) ((XCVR_DTEST_CTRL_REG(base) & XCVR_DTEST_CTRL_RAW_MODE_I_MASK) >> XCVR_DTEST_CTRL_RAW_MODE_I_SHIFT)
35445 #define XCVR_BRD_DTEST_CTRL_RAW_MODE_I(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTEST_CTRL_RAW_MODE_I_SHIFT, XCVR_DTEST_CTRL_RAW_MODE_I_WIDTH))
35446 
35447 /*! @brief Set the RAW_MODE_I field to a new value. */
35448 #define XCVR_WR_DTEST_CTRL_RAW_MODE_I(base, value) (XCVR_RMW_DTEST_CTRL(base, XCVR_DTEST_CTRL_RAW_MODE_I_MASK, XCVR_DTEST_CTRL_RAW_MODE_I(value)))
35449 #define XCVR_BWR_DTEST_CTRL_RAW_MODE_I(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((uint32_t)(value) << XCVR_DTEST_CTRL_RAW_MODE_I_SHIFT), XCVR_DTEST_CTRL_RAW_MODE_I_SHIFT, XCVR_DTEST_CTRL_RAW_MODE_I_WIDTH))
35450 /*@}*/
35451 
35452 /*!
35453  * @name Register XCVR_DTEST_CTRL, field RAW_MODE_Q[29] (RW)
35454  *
35455  * DTEST Q Channel Raw Mode allows raw, unfiltered ADC samples to be brought out
35456  * to DTEST pins on the RXDIGIQ DTEST page. In raw mode, 2 5-bit ADC samples are
35457  * concatenated into a single 12-bit DMA sample. DMA transfers these samples to
35458  * memory in the same way it transfers filtered samples. Raw mode is only
35459  * supported when the RX_DIG is programmed to decimate-by-2. The procedure to active Raw
35460  * mode on Q channel is as follows: 1. RX_DIG_CTRL[RX_ADC_RAW_EN]=1 2.
35461  * RX_DIG_CTRL[RX_DEC_FILT_OSR]=0 3. DTEST_CTRL[DTEST_PAGE]=0x0E (RXDIGIQ) 4.
35462  * DTEST_CTRL[DTEST_EN]=1 5. DTEST_CTRL[RAW_MODE_Q]=1
35463  */
35464 /*@{*/
35465 /*! @brief Read current value of the XCVR_DTEST_CTRL_RAW_MODE_Q field. */
35466 #define XCVR_RD_DTEST_CTRL_RAW_MODE_Q(base) ((XCVR_DTEST_CTRL_REG(base) & XCVR_DTEST_CTRL_RAW_MODE_Q_MASK) >> XCVR_DTEST_CTRL_RAW_MODE_Q_SHIFT)
35467 #define XCVR_BRD_DTEST_CTRL_RAW_MODE_Q(base) (BME_UBFX32(&XCVR_DTEST_CTRL_REG(base), XCVR_DTEST_CTRL_RAW_MODE_Q_SHIFT, XCVR_DTEST_CTRL_RAW_MODE_Q_WIDTH))
35468 
35469 /*! @brief Set the RAW_MODE_Q field to a new value. */
35470 #define XCVR_WR_DTEST_CTRL_RAW_MODE_Q(base, value) (XCVR_RMW_DTEST_CTRL(base, XCVR_DTEST_CTRL_RAW_MODE_Q_MASK, XCVR_DTEST_CTRL_RAW_MODE_Q(value)))
35471 #define XCVR_BWR_DTEST_CTRL_RAW_MODE_Q(base, value) (BME_BFI32(&XCVR_DTEST_CTRL_REG(base), ((uint32_t)(value) << XCVR_DTEST_CTRL_RAW_MODE_Q_SHIFT), XCVR_DTEST_CTRL_RAW_MODE_Q_SHIFT, XCVR_DTEST_CTRL_RAW_MODE_Q_WIDTH))
35472 /*@}*/
35473 
35474 /*******************************************************************************
35475  * XCVR_PB_CTRL - Packet Buffer Control Register
35476  ******************************************************************************/
35477 
35478 /*!
35479  * @brief XCVR_PB_CTRL - Packet Buffer Control Register (RW)
35480  *
35481  * Reset value: 0x00000000U
35482  */
35483 /*!
35484  * @name Constants and macros for entire XCVR_PB_CTRL register
35485  */
35486 /*@{*/
35487 #define XCVR_RD_PB_CTRL(base)    (XCVR_PB_CTRL_REG(base))
35488 #define XCVR_WR_PB_CTRL(base, value) (XCVR_PB_CTRL_REG(base) = (value))
35489 #define XCVR_RMW_PB_CTRL(base, mask, value) (XCVR_WR_PB_CTRL(base, (XCVR_RD_PB_CTRL(base) & ~(mask)) | (value)))
35490 #define XCVR_SET_PB_CTRL(base, value) (BME_OR32(&XCVR_PB_CTRL_REG(base), (uint32_t)(value)))
35491 #define XCVR_CLR_PB_CTRL(base, value) (BME_AND32(&XCVR_PB_CTRL_REG(base), (uint32_t)(~(value))))
35492 #define XCVR_TOG_PB_CTRL(base, value) (BME_XOR32(&XCVR_PB_CTRL_REG(base), (uint32_t)(value)))
35493 /*@}*/
35494 
35495 /*
35496  * Constants & macros for individual XCVR_PB_CTRL bitfields
35497  */
35498 
35499 /*!
35500  * @name Register XCVR_PB_CTRL, field PB_PROTECT[0] (RW)
35501  *
35502  * Protect Packet Buffer contents against overwriting by the next received packet
35503  *
35504  * Values:
35505  * - 0b0 - Incoming received packets overwrite Packet Buffer contents (default)
35506  * - 0b1 - Incoming received packets are blocked from overwriting Packet Buffer
35507  *     contents
35508  */
35509 /*@{*/
35510 /*! @brief Read current value of the XCVR_PB_CTRL_PB_PROTECT field. */
35511 #define XCVR_RD_PB_CTRL_PB_PROTECT(base) ((XCVR_PB_CTRL_REG(base) & XCVR_PB_CTRL_PB_PROTECT_MASK) >> XCVR_PB_CTRL_PB_PROTECT_SHIFT)
35512 #define XCVR_BRD_PB_CTRL_PB_PROTECT(base) (BME_UBFX32(&XCVR_PB_CTRL_REG(base), XCVR_PB_CTRL_PB_PROTECT_SHIFT, XCVR_PB_CTRL_PB_PROTECT_WIDTH))
35513 
35514 /*! @brief Set the PB_PROTECT field to a new value. */
35515 #define XCVR_WR_PB_CTRL_PB_PROTECT(base, value) (XCVR_RMW_PB_CTRL(base, XCVR_PB_CTRL_PB_PROTECT_MASK, XCVR_PB_CTRL_PB_PROTECT(value)))
35516 #define XCVR_BWR_PB_CTRL_PB_PROTECT(base, value) (BME_BFI32(&XCVR_PB_CTRL_REG(base), ((uint32_t)(value) << XCVR_PB_CTRL_PB_PROTECT_SHIFT), XCVR_PB_CTRL_PB_PROTECT_SHIFT, XCVR_PB_CTRL_PB_PROTECT_WIDTH))
35517 /*@}*/
35518 
35519 /*******************************************************************************
35520  * XCVR_TSM_CTRL - Transceiver Sequence Manager Control
35521  ******************************************************************************/
35522 
35523 /*!
35524  * @brief XCVR_TSM_CTRL - Transceiver Sequence Manager Control (RW)
35525  *
35526  * Reset value: 0xFF000000U
35527  */
35528 /*!
35529  * @name Constants and macros for entire XCVR_TSM_CTRL register
35530  */
35531 /*@{*/
35532 #define XCVR_RD_TSM_CTRL(base)   (XCVR_TSM_CTRL_REG(base))
35533 #define XCVR_WR_TSM_CTRL(base, value) (XCVR_TSM_CTRL_REG(base) = (value))
35534 #define XCVR_RMW_TSM_CTRL(base, mask, value) (XCVR_WR_TSM_CTRL(base, (XCVR_RD_TSM_CTRL(base) & ~(mask)) | (value)))
35535 #define XCVR_SET_TSM_CTRL(base, value) (BME_OR32(&XCVR_TSM_CTRL_REG(base), (uint32_t)(value)))
35536 #define XCVR_CLR_TSM_CTRL(base, value) (BME_AND32(&XCVR_TSM_CTRL_REG(base), (uint32_t)(~(value))))
35537 #define XCVR_TOG_TSM_CTRL(base, value) (BME_XOR32(&XCVR_TSM_CTRL_REG(base), (uint32_t)(value)))
35538 /*@}*/
35539 
35540 /*
35541  * Constants & macros for individual XCVR_TSM_CTRL bitfields
35542  */
35543 
35544 /*!
35545  * @name Register XCVR_TSM_CTRL, field FORCE_TX_EN[2] (RW)
35546  *
35547  * Direct software control to launch a TX TSM sequence. Initiates a TX Warmup
35548  * sequence on a 0 to 1 transition and a TX Warmdown sequence on a 1 to 0
35549  * transition.
35550  *
35551  * Values:
35552  * - 0b0 - TSM Idle
35553  * - 0b1 - TSM executes a TX sequence
35554  */
35555 /*@{*/
35556 /*! @brief Read current value of the XCVR_TSM_CTRL_FORCE_TX_EN field. */
35557 #define XCVR_RD_TSM_CTRL_FORCE_TX_EN(base) ((XCVR_TSM_CTRL_REG(base) & XCVR_TSM_CTRL_FORCE_TX_EN_MASK) >> XCVR_TSM_CTRL_FORCE_TX_EN_SHIFT)
35558 #define XCVR_BRD_TSM_CTRL_FORCE_TX_EN(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_FORCE_TX_EN_SHIFT, XCVR_TSM_CTRL_FORCE_TX_EN_WIDTH))
35559 
35560 /*! @brief Set the FORCE_TX_EN field to a new value. */
35561 #define XCVR_WR_TSM_CTRL_FORCE_TX_EN(base, value) (XCVR_RMW_TSM_CTRL(base, XCVR_TSM_CTRL_FORCE_TX_EN_MASK, XCVR_TSM_CTRL_FORCE_TX_EN(value)))
35562 #define XCVR_BWR_TSM_CTRL_FORCE_TX_EN(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t)(value) << XCVR_TSM_CTRL_FORCE_TX_EN_SHIFT), XCVR_TSM_CTRL_FORCE_TX_EN_SHIFT, XCVR_TSM_CTRL_FORCE_TX_EN_WIDTH))
35563 /*@}*/
35564 
35565 /*!
35566  * @name Register XCVR_TSM_CTRL, field FORCE_RX_EN[3] (RW)
35567  *
35568  * Direct software control to launch a RX TSM sequence. Initiates RX Warmup on a
35569  * 0 to 1 transition and RX Warmdown on a 1 to 0 transition.
35570  *
35571  * Values:
35572  * - 0b0 - TSM Idle
35573  * - 0b1 - TSM executes a RX sequence
35574  */
35575 /*@{*/
35576 /*! @brief Read current value of the XCVR_TSM_CTRL_FORCE_RX_EN field. */
35577 #define XCVR_RD_TSM_CTRL_FORCE_RX_EN(base) ((XCVR_TSM_CTRL_REG(base) & XCVR_TSM_CTRL_FORCE_RX_EN_MASK) >> XCVR_TSM_CTRL_FORCE_RX_EN_SHIFT)
35578 #define XCVR_BRD_TSM_CTRL_FORCE_RX_EN(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_FORCE_RX_EN_SHIFT, XCVR_TSM_CTRL_FORCE_RX_EN_WIDTH))
35579 
35580 /*! @brief Set the FORCE_RX_EN field to a new value. */
35581 #define XCVR_WR_TSM_CTRL_FORCE_RX_EN(base, value) (XCVR_RMW_TSM_CTRL(base, XCVR_TSM_CTRL_FORCE_RX_EN_MASK, XCVR_TSM_CTRL_FORCE_RX_EN(value)))
35582 #define XCVR_BWR_TSM_CTRL_FORCE_RX_EN(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t)(value) << XCVR_TSM_CTRL_FORCE_RX_EN_SHIFT), XCVR_TSM_CTRL_FORCE_RX_EN_SHIFT, XCVR_TSM_CTRL_FORCE_RX_EN_WIDTH))
35583 /*@}*/
35584 
35585 /*!
35586  * @name Register XCVR_TSM_CTRL, field PA_RAMP_SEL[5:4] (RW)
35587  *
35588  * Selects the ramp-rate, and thus the duration, for PA ramping. Ramp-rate is
35589  * the rate at which the PA ramping logic steps through the PA Bias Table. the
35590  * default TSM TX sequence needs to be adjusted (re-programmed) for a 4us or 8us
35591  * ramp. PA_RAMP_SEL[1:0] TOTAL RAMP DURATION DURATION OF EACH RAMP STEP 00 No ramp
35592  * No ramp 01 2us 0.25us 10 4us 0.5us 11 8us 1us
35593  */
35594 /*@{*/
35595 /*! @brief Read current value of the XCVR_TSM_CTRL_PA_RAMP_SEL field. */
35596 #define XCVR_RD_TSM_CTRL_PA_RAMP_SEL(base) ((XCVR_TSM_CTRL_REG(base) & XCVR_TSM_CTRL_PA_RAMP_SEL_MASK) >> XCVR_TSM_CTRL_PA_RAMP_SEL_SHIFT)
35597 #define XCVR_BRD_TSM_CTRL_PA_RAMP_SEL(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_PA_RAMP_SEL_SHIFT, XCVR_TSM_CTRL_PA_RAMP_SEL_WIDTH))
35598 
35599 /*! @brief Set the PA_RAMP_SEL field to a new value. */
35600 #define XCVR_WR_TSM_CTRL_PA_RAMP_SEL(base, value) (XCVR_RMW_TSM_CTRL(base, XCVR_TSM_CTRL_PA_RAMP_SEL_MASK, XCVR_TSM_CTRL_PA_RAMP_SEL(value)))
35601 #define XCVR_BWR_TSM_CTRL_PA_RAMP_SEL(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t)(value) << XCVR_TSM_CTRL_PA_RAMP_SEL_SHIFT), XCVR_TSM_CTRL_PA_RAMP_SEL_SHIFT, XCVR_TSM_CTRL_PA_RAMP_SEL_WIDTH))
35602 /*@}*/
35603 
35604 /*!
35605  * @name Register XCVR_TSM_CTRL, field DATA_PADDING_EN[6] (RW)
35606  *
35607  * Enables TX Data Padding. Data padding works in conjunction with PA ramping to
35608  * minimize spectral transients during PA turn-on and turn-off. The nature of
35609  * the data padding depends on the setting of XCVR_CTRL[PROTOCOL].
35610  *
35611  * Values:
35612  * - 0b0 - Disable TX Data Padding
35613  * - 0b1 - Enable TX Data Padding
35614  */
35615 /*@{*/
35616 /*! @brief Read current value of the XCVR_TSM_CTRL_DATA_PADDING_EN field. */
35617 #define XCVR_RD_TSM_CTRL_DATA_PADDING_EN(base) ((XCVR_TSM_CTRL_REG(base) & XCVR_TSM_CTRL_DATA_PADDING_EN_MASK) >> XCVR_TSM_CTRL_DATA_PADDING_EN_SHIFT)
35618 #define XCVR_BRD_TSM_CTRL_DATA_PADDING_EN(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_DATA_PADDING_EN_SHIFT, XCVR_TSM_CTRL_DATA_PADDING_EN_WIDTH))
35619 
35620 /*! @brief Set the DATA_PADDING_EN field to a new value. */
35621 #define XCVR_WR_TSM_CTRL_DATA_PADDING_EN(base, value) (XCVR_RMW_TSM_CTRL(base, XCVR_TSM_CTRL_DATA_PADDING_EN_MASK, XCVR_TSM_CTRL_DATA_PADDING_EN(value)))
35622 #define XCVR_BWR_TSM_CTRL_DATA_PADDING_EN(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t)(value) << XCVR_TSM_CTRL_DATA_PADDING_EN_SHIFT), XCVR_TSM_CTRL_DATA_PADDING_EN_SHIFT, XCVR_TSM_CTRL_DATA_PADDING_EN_WIDTH))
35623 /*@}*/
35624 
35625 /*!
35626  * @name Register XCVR_TSM_CTRL, field TX_ABORT_DIS[16] (RW)
35627  *
35628  * TX Abort disable. When set, prevents PLL unlock events during TX sequences
35629  * from aborting the sequence.
35630  */
35631 /*@{*/
35632 /*! @brief Read current value of the XCVR_TSM_CTRL_TX_ABORT_DIS field. */
35633 #define XCVR_RD_TSM_CTRL_TX_ABORT_DIS(base) ((XCVR_TSM_CTRL_REG(base) & XCVR_TSM_CTRL_TX_ABORT_DIS_MASK) >> XCVR_TSM_CTRL_TX_ABORT_DIS_SHIFT)
35634 #define XCVR_BRD_TSM_CTRL_TX_ABORT_DIS(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_TX_ABORT_DIS_SHIFT, XCVR_TSM_CTRL_TX_ABORT_DIS_WIDTH))
35635 
35636 /*! @brief Set the TX_ABORT_DIS field to a new value. */
35637 #define XCVR_WR_TSM_CTRL_TX_ABORT_DIS(base, value) (XCVR_RMW_TSM_CTRL(base, XCVR_TSM_CTRL_TX_ABORT_DIS_MASK, XCVR_TSM_CTRL_TX_ABORT_DIS(value)))
35638 #define XCVR_BWR_TSM_CTRL_TX_ABORT_DIS(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t)(value) << XCVR_TSM_CTRL_TX_ABORT_DIS_SHIFT), XCVR_TSM_CTRL_TX_ABORT_DIS_SHIFT, XCVR_TSM_CTRL_TX_ABORT_DIS_WIDTH))
35639 /*@}*/
35640 
35641 /*!
35642  * @name Register XCVR_TSM_CTRL, field RX_ABORT_DIS[17] (RW)
35643  *
35644  * RX Abort disable. When set, prevents PLL unlock events during RX sequences
35645  * from aborting the sequence.
35646  */
35647 /*@{*/
35648 /*! @brief Read current value of the XCVR_TSM_CTRL_RX_ABORT_DIS field. */
35649 #define XCVR_RD_TSM_CTRL_RX_ABORT_DIS(base) ((XCVR_TSM_CTRL_REG(base) & XCVR_TSM_CTRL_RX_ABORT_DIS_MASK) >> XCVR_TSM_CTRL_RX_ABORT_DIS_SHIFT)
35650 #define XCVR_BRD_TSM_CTRL_RX_ABORT_DIS(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_RX_ABORT_DIS_SHIFT, XCVR_TSM_CTRL_RX_ABORT_DIS_WIDTH))
35651 
35652 /*! @brief Set the RX_ABORT_DIS field to a new value. */
35653 #define XCVR_WR_TSM_CTRL_RX_ABORT_DIS(base, value) (XCVR_RMW_TSM_CTRL(base, XCVR_TSM_CTRL_RX_ABORT_DIS_MASK, XCVR_TSM_CTRL_RX_ABORT_DIS(value)))
35654 #define XCVR_BWR_TSM_CTRL_RX_ABORT_DIS(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t)(value) << XCVR_TSM_CTRL_RX_ABORT_DIS_SHIFT), XCVR_TSM_CTRL_RX_ABORT_DIS_SHIFT, XCVR_TSM_CTRL_RX_ABORT_DIS_WIDTH))
35655 /*@}*/
35656 
35657 /*!
35658  * @name Register XCVR_TSM_CTRL, field ABORT_ON_CTUNE[18] (RW)
35659  *
35660  * Values:
35661  * - 0b0 - don't allow TSM abort on Coarse Tune Unlock Detect
35662  * - 0b1 - allow TSM abort on Coarse Tune Unlock Detect
35663  */
35664 /*@{*/
35665 /*! @brief Read current value of the XCVR_TSM_CTRL_ABORT_ON_CTUNE field. */
35666 #define XCVR_RD_TSM_CTRL_ABORT_ON_CTUNE(base) ((XCVR_TSM_CTRL_REG(base) & XCVR_TSM_CTRL_ABORT_ON_CTUNE_MASK) >> XCVR_TSM_CTRL_ABORT_ON_CTUNE_SHIFT)
35667 #define XCVR_BRD_TSM_CTRL_ABORT_ON_CTUNE(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_ABORT_ON_CTUNE_SHIFT, XCVR_TSM_CTRL_ABORT_ON_CTUNE_WIDTH))
35668 
35669 /*! @brief Set the ABORT_ON_CTUNE field to a new value. */
35670 #define XCVR_WR_TSM_CTRL_ABORT_ON_CTUNE(base, value) (XCVR_RMW_TSM_CTRL(base, XCVR_TSM_CTRL_ABORT_ON_CTUNE_MASK, XCVR_TSM_CTRL_ABORT_ON_CTUNE(value)))
35671 #define XCVR_BWR_TSM_CTRL_ABORT_ON_CTUNE(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t)(value) << XCVR_TSM_CTRL_ABORT_ON_CTUNE_SHIFT), XCVR_TSM_CTRL_ABORT_ON_CTUNE_SHIFT, XCVR_TSM_CTRL_ABORT_ON_CTUNE_WIDTH))
35672 /*@}*/
35673 
35674 /*!
35675  * @name Register XCVR_TSM_CTRL, field ABORT_ON_CYCLE_SLIP[19] (RW)
35676  *
35677  * Values:
35678  * - 0b0 - don't allow TSM abort on Cycle Slip Unlock Detect
35679  * - 0b1 - allow TSM abort on Cycle Slip Unlock Detect
35680  */
35681 /*@{*/
35682 /*! @brief Read current value of the XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP field. */
35683 #define XCVR_RD_TSM_CTRL_ABORT_ON_CYCLE_SLIP(base) ((XCVR_TSM_CTRL_REG(base) & XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_MASK) >> XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_SHIFT)
35684 #define XCVR_BRD_TSM_CTRL_ABORT_ON_CYCLE_SLIP(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_SHIFT, XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_WIDTH))
35685 
35686 /*! @brief Set the ABORT_ON_CYCLE_SLIP field to a new value. */
35687 #define XCVR_WR_TSM_CTRL_ABORT_ON_CYCLE_SLIP(base, value) (XCVR_RMW_TSM_CTRL(base, XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_MASK, XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP(value)))
35688 #define XCVR_BWR_TSM_CTRL_ABORT_ON_CYCLE_SLIP(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t)(value) << XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_SHIFT), XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_SHIFT, XCVR_TSM_CTRL_ABORT_ON_CYCLE_SLIP_WIDTH))
35689 /*@}*/
35690 
35691 /*!
35692  * @name Register XCVR_TSM_CTRL, field ABORT_ON_FREQ_TARG[20] (RW)
35693  *
35694  * Values:
35695  * - 0b0 - don't allow TSM abort on Frequency Target Unlock Detect
35696  * - 0b1 - allow TSM abort on Frequency Target Unlock Detect
35697  */
35698 /*@{*/
35699 /*! @brief Read current value of the XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG field. */
35700 #define XCVR_RD_TSM_CTRL_ABORT_ON_FREQ_TARG(base) ((XCVR_TSM_CTRL_REG(base) & XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_MASK) >> XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_SHIFT)
35701 #define XCVR_BRD_TSM_CTRL_ABORT_ON_FREQ_TARG(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_SHIFT, XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_WIDTH))
35702 
35703 /*! @brief Set the ABORT_ON_FREQ_TARG field to a new value. */
35704 #define XCVR_WR_TSM_CTRL_ABORT_ON_FREQ_TARG(base, value) (XCVR_RMW_TSM_CTRL(base, XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_MASK, XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG(value)))
35705 #define XCVR_BWR_TSM_CTRL_ABORT_ON_FREQ_TARG(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t)(value) << XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_SHIFT), XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_SHIFT, XCVR_TSM_CTRL_ABORT_ON_FREQ_TARG_WIDTH))
35706 /*@}*/
35707 
35708 /*!
35709  * @name Register XCVR_TSM_CTRL, field BKPT[31:24] (RW)
35710  *
35711  * Temporarily halt a TSM sequence during the warmup or warmdown phase. When the
35712  * TSM counter matches the value of BKPT[7:0], breakpoint will take effect and
35713  * the TSM counter will stop and hold its count. Breakpoint will remain in effect
35714  * as long as BKPT[7:0] matches the TSM counter value. The TSM Breakpoint can be
35715  * lifted by modifying the contents of this register. The default value of this
35716  * register, 0xFF, is greater than the length of the longest possible sequence, so
35717  * a breakpoint will never be triggered unless BKPT[7:0] is programmed to a
35718  * value less than the length of sequence.
35719  */
35720 /*@{*/
35721 /*! @brief Read current value of the XCVR_TSM_CTRL_BKPT field. */
35722 #define XCVR_RD_TSM_CTRL_BKPT(base) ((XCVR_TSM_CTRL_REG(base) & XCVR_TSM_CTRL_BKPT_MASK) >> XCVR_TSM_CTRL_BKPT_SHIFT)
35723 #define XCVR_BRD_TSM_CTRL_BKPT(base) (BME_UBFX32(&XCVR_TSM_CTRL_REG(base), XCVR_TSM_CTRL_BKPT_SHIFT, XCVR_TSM_CTRL_BKPT_WIDTH))
35724 
35725 /*! @brief Set the BKPT field to a new value. */
35726 #define XCVR_WR_TSM_CTRL_BKPT(base, value) (XCVR_RMW_TSM_CTRL(base, XCVR_TSM_CTRL_BKPT_MASK, XCVR_TSM_CTRL_BKPT(value)))
35727 #define XCVR_BWR_TSM_CTRL_BKPT(base, value) (BME_BFI32(&XCVR_TSM_CTRL_REG(base), ((uint32_t)(value) << XCVR_TSM_CTRL_BKPT_SHIFT), XCVR_TSM_CTRL_BKPT_SHIFT, XCVR_TSM_CTRL_BKPT_WIDTH))
35728 /*@}*/
35729 
35730 /*******************************************************************************
35731  * XCVR_END_OF_SEQ - End of Sequence Control
35732  ******************************************************************************/
35733 
35734 /*!
35735  * @brief XCVR_END_OF_SEQ - End of Sequence Control (RW)
35736  *
35737  * Reset value: 0x65646A67U
35738  */
35739 /*!
35740  * @name Constants and macros for entire XCVR_END_OF_SEQ register
35741  */
35742 /*@{*/
35743 #define XCVR_RD_END_OF_SEQ(base) (XCVR_END_OF_SEQ_REG(base))
35744 #define XCVR_WR_END_OF_SEQ(base, value) (XCVR_END_OF_SEQ_REG(base) = (value))
35745 #define XCVR_RMW_END_OF_SEQ(base, mask, value) (XCVR_WR_END_OF_SEQ(base, (XCVR_RD_END_OF_SEQ(base) & ~(mask)) | (value)))
35746 #define XCVR_SET_END_OF_SEQ(base, value) (BME_OR32(&XCVR_END_OF_SEQ_REG(base), (uint32_t)(value)))
35747 #define XCVR_CLR_END_OF_SEQ(base, value) (BME_AND32(&XCVR_END_OF_SEQ_REG(base), (uint32_t)(~(value))))
35748 #define XCVR_TOG_END_OF_SEQ(base, value) (BME_XOR32(&XCVR_END_OF_SEQ_REG(base), (uint32_t)(value)))
35749 /*@}*/
35750 
35751 /*
35752  * Constants & macros for individual XCVR_END_OF_SEQ bitfields
35753  */
35754 
35755 /*!
35756  * @name Register XCVR_END_OF_SEQ, field END_OF_TX_WU[7:0] (RW)
35757  *
35758  * This register defines the length of the TSM TX warmup sequence. After the
35759  * assertion of a TX sequence-initiating event, when the TSM counter reaches the
35760  * count matching this register, it will stop and hold its count, and the TSM will
35761  * transition from the WARMUP to the ON phase.
35762  */
35763 /*@{*/
35764 /*! @brief Read current value of the XCVR_END_OF_SEQ_END_OF_TX_WU field. */
35765 #define XCVR_RD_END_OF_SEQ_END_OF_TX_WU(base) ((XCVR_END_OF_SEQ_REG(base) & XCVR_END_OF_SEQ_END_OF_TX_WU_MASK) >> XCVR_END_OF_SEQ_END_OF_TX_WU_SHIFT)
35766 #define XCVR_BRD_END_OF_SEQ_END_OF_TX_WU(base) (BME_UBFX32(&XCVR_END_OF_SEQ_REG(base), XCVR_END_OF_SEQ_END_OF_TX_WU_SHIFT, XCVR_END_OF_SEQ_END_OF_TX_WU_WIDTH))
35767 
35768 /*! @brief Set the END_OF_TX_WU field to a new value. */
35769 #define XCVR_WR_END_OF_SEQ_END_OF_TX_WU(base, value) (XCVR_RMW_END_OF_SEQ(base, XCVR_END_OF_SEQ_END_OF_TX_WU_MASK, XCVR_END_OF_SEQ_END_OF_TX_WU(value)))
35770 #define XCVR_BWR_END_OF_SEQ_END_OF_TX_WU(base, value) (BME_BFI32(&XCVR_END_OF_SEQ_REG(base), ((uint32_t)(value) << XCVR_END_OF_SEQ_END_OF_TX_WU_SHIFT), XCVR_END_OF_SEQ_END_OF_TX_WU_SHIFT, XCVR_END_OF_SEQ_END_OF_TX_WU_WIDTH))
35771 /*@}*/
35772 
35773 /*!
35774  * @name Register XCVR_END_OF_SEQ, field END_OF_TX_WD[15:8] (RW)
35775  *
35776  * This register defines the point at which the TSM TX sequence warmdown
35777  * completes, and the TSM returns to idle. The duration of the TSM warmdown phase is
35778  * determined by: END_OF_TX_WD - END_OF_TX_WU. For example: the sequence register
35779  * defaults render the END_OF_TX_WD=0x69 and END_OF_TX_WU=0x66, so the duration of
35780  * the warmdown phase is 0x69 - 0x66 = 3 microseconds.
35781  */
35782 /*@{*/
35783 /*! @brief Read current value of the XCVR_END_OF_SEQ_END_OF_TX_WD field. */
35784 #define XCVR_RD_END_OF_SEQ_END_OF_TX_WD(base) ((XCVR_END_OF_SEQ_REG(base) & XCVR_END_OF_SEQ_END_OF_TX_WD_MASK) >> XCVR_END_OF_SEQ_END_OF_TX_WD_SHIFT)
35785 #define XCVR_BRD_END_OF_SEQ_END_OF_TX_WD(base) (BME_UBFX32(&XCVR_END_OF_SEQ_REG(base), XCVR_END_OF_SEQ_END_OF_TX_WD_SHIFT, XCVR_END_OF_SEQ_END_OF_TX_WD_WIDTH))
35786 
35787 /*! @brief Set the END_OF_TX_WD field to a new value. */
35788 #define XCVR_WR_END_OF_SEQ_END_OF_TX_WD(base, value) (XCVR_RMW_END_OF_SEQ(base, XCVR_END_OF_SEQ_END_OF_TX_WD_MASK, XCVR_END_OF_SEQ_END_OF_TX_WD(value)))
35789 #define XCVR_BWR_END_OF_SEQ_END_OF_TX_WD(base, value) (BME_BFI32(&XCVR_END_OF_SEQ_REG(base), ((uint32_t)(value) << XCVR_END_OF_SEQ_END_OF_TX_WD_SHIFT), XCVR_END_OF_SEQ_END_OF_TX_WD_SHIFT, XCVR_END_OF_SEQ_END_OF_TX_WD_WIDTH))
35790 /*@}*/
35791 
35792 /*!
35793  * @name Register XCVR_END_OF_SEQ, field END_OF_RX_WU[23:16] (RW)
35794  *
35795  * This register defines the length of the TSM RX warmup sequence. After the
35796  * assertion of a RX sequence-initiating event, when the TSM counter reaches the
35797  * count matching this register, it will stop and hold its count, and the TSM will
35798  * transition from the WARMUP to the ON phase.
35799  */
35800 /*@{*/
35801 /*! @brief Read current value of the XCVR_END_OF_SEQ_END_OF_RX_WU field. */
35802 #define XCVR_RD_END_OF_SEQ_END_OF_RX_WU(base) ((XCVR_END_OF_SEQ_REG(base) & XCVR_END_OF_SEQ_END_OF_RX_WU_MASK) >> XCVR_END_OF_SEQ_END_OF_RX_WU_SHIFT)
35803 #define XCVR_BRD_END_OF_SEQ_END_OF_RX_WU(base) (BME_UBFX32(&XCVR_END_OF_SEQ_REG(base), XCVR_END_OF_SEQ_END_OF_RX_WU_SHIFT, XCVR_END_OF_SEQ_END_OF_RX_WU_WIDTH))
35804 
35805 /*! @brief Set the END_OF_RX_WU field to a new value. */
35806 #define XCVR_WR_END_OF_SEQ_END_OF_RX_WU(base, value) (XCVR_RMW_END_OF_SEQ(base, XCVR_END_OF_SEQ_END_OF_RX_WU_MASK, XCVR_END_OF_SEQ_END_OF_RX_WU(value)))
35807 #define XCVR_BWR_END_OF_SEQ_END_OF_RX_WU(base, value) (BME_BFI32(&XCVR_END_OF_SEQ_REG(base), ((uint32_t)(value) << XCVR_END_OF_SEQ_END_OF_RX_WU_SHIFT), XCVR_END_OF_SEQ_END_OF_RX_WU_SHIFT, XCVR_END_OF_SEQ_END_OF_RX_WU_WIDTH))
35808 /*@}*/
35809 
35810 /*!
35811  * @name Register XCVR_END_OF_SEQ, field END_OF_RX_WD[31:24] (RW)
35812  *
35813  * This register defines the point at which the TSM RX sequence warmdown
35814  * completes, and the TSM returns to idle. The duration of the TSM warmdown phase is
35815  * determined by: END_OF_RX_WD - END_OF_RX_WU. For example: the sequence register
35816  * defaults render the END_OF_RX_WD=0x33 and END_OF_RX_WU=0x32, so the duration of
35817  * the warmdown phase is 0x33 - 0x32 = 1 microseconds.
35818  */
35819 /*@{*/
35820 /*! @brief Read current value of the XCVR_END_OF_SEQ_END_OF_RX_WD field. */
35821 #define XCVR_RD_END_OF_SEQ_END_OF_RX_WD(base) ((XCVR_END_OF_SEQ_REG(base) & XCVR_END_OF_SEQ_END_OF_RX_WD_MASK) >> XCVR_END_OF_SEQ_END_OF_RX_WD_SHIFT)
35822 #define XCVR_BRD_END_OF_SEQ_END_OF_RX_WD(base) (BME_UBFX32(&XCVR_END_OF_SEQ_REG(base), XCVR_END_OF_SEQ_END_OF_RX_WD_SHIFT, XCVR_END_OF_SEQ_END_OF_RX_WD_WIDTH))
35823 
35824 /*! @brief Set the END_OF_RX_WD field to a new value. */
35825 #define XCVR_WR_END_OF_SEQ_END_OF_RX_WD(base, value) (XCVR_RMW_END_OF_SEQ(base, XCVR_END_OF_SEQ_END_OF_RX_WD_MASK, XCVR_END_OF_SEQ_END_OF_RX_WD(value)))
35826 #define XCVR_BWR_END_OF_SEQ_END_OF_RX_WD(base, value) (BME_BFI32(&XCVR_END_OF_SEQ_REG(base), ((uint32_t)(value) << XCVR_END_OF_SEQ_END_OF_RX_WD_SHIFT), XCVR_END_OF_SEQ_END_OF_RX_WD_SHIFT, XCVR_END_OF_SEQ_END_OF_RX_WD_WIDTH))
35827 /*@}*/
35828 
35829 /*******************************************************************************
35830  * XCVR_TSM_OVRD0 - TSM Override 0
35831  ******************************************************************************/
35832 
35833 /*!
35834  * @brief XCVR_TSM_OVRD0 - TSM Override 0 (RW)
35835  *
35836  * Reset value: 0x00000000U
35837  */
35838 /*!
35839  * @name Constants and macros for entire XCVR_TSM_OVRD0 register
35840  */
35841 /*@{*/
35842 #define XCVR_RD_TSM_OVRD0(base)  (XCVR_TSM_OVRD0_REG(base))
35843 #define XCVR_WR_TSM_OVRD0(base, value) (XCVR_TSM_OVRD0_REG(base) = (value))
35844 #define XCVR_RMW_TSM_OVRD0(base, mask, value) (XCVR_WR_TSM_OVRD0(base, (XCVR_RD_TSM_OVRD0(base) & ~(mask)) | (value)))
35845 #define XCVR_SET_TSM_OVRD0(base, value) (BME_OR32(&XCVR_TSM_OVRD0_REG(base), (uint32_t)(value)))
35846 #define XCVR_CLR_TSM_OVRD0(base, value) (BME_AND32(&XCVR_TSM_OVRD0_REG(base), (uint32_t)(~(value))))
35847 #define XCVR_TOG_TSM_OVRD0(base, value) (BME_XOR32(&XCVR_TSM_OVRD0_REG(base), (uint32_t)(value)))
35848 /*@}*/
35849 
35850 /*
35851  * Constants & macros for individual XCVR_TSM_OVRD0 bitfields
35852  */
35853 
35854 /*!
35855  * @name Register XCVR_TSM_OVRD0, field PLL_REG_EN_OVRD_EN[0] (RW)
35856  *
35857  * Values:
35858  * - 0b0 - Normal operation.
35859  * - 0b1 - Use the state of PLL_REG_EN_OVRD to override the signal "pll_reg_en".
35860  */
35861 /*@{*/
35862 /*! @brief Read current value of the XCVR_TSM_OVRD0_PLL_REG_EN_OVRD_EN field. */
35863 #define XCVR_RD_TSM_OVRD0_PLL_REG_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_REG_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD0_PLL_REG_EN_OVRD_EN_SHIFT)
35864 #define XCVR_BRD_TSM_OVRD0_PLL_REG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_PLL_REG_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_PLL_REG_EN_OVRD_EN_WIDTH))
35865 
35866 /*! @brief Set the PLL_REG_EN_OVRD_EN field to a new value. */
35867 #define XCVR_WR_TSM_OVRD0_PLL_REG_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL_REG_EN_OVRD_EN_MASK, XCVR_TSM_OVRD0_PLL_REG_EN_OVRD_EN(value)))
35868 #define XCVR_BWR_TSM_OVRD0_PLL_REG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_PLL_REG_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD0_PLL_REG_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_PLL_REG_EN_OVRD_EN_WIDTH))
35869 /*@}*/
35870 
35871 /*!
35872  * @name Register XCVR_TSM_OVRD0, field PLL_REG_EN_OVRD[1] (RW)
35873  *
35874  * When PLL_REG_EN_OVRD_EN=1, this value overrides the mission mode state of the
35875  * signal "pll_reg_en". This bit is ignored when PLL_REG_EN_OVRD_EN==0.
35876  */
35877 /*@{*/
35878 /*! @brief Read current value of the XCVR_TSM_OVRD0_PLL_REG_EN_OVRD field. */
35879 #define XCVR_RD_TSM_OVRD0_PLL_REG_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_REG_EN_OVRD_MASK) >> XCVR_TSM_OVRD0_PLL_REG_EN_OVRD_SHIFT)
35880 #define XCVR_BRD_TSM_OVRD0_PLL_REG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_PLL_REG_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_PLL_REG_EN_OVRD_WIDTH))
35881 
35882 /*! @brief Set the PLL_REG_EN_OVRD field to a new value. */
35883 #define XCVR_WR_TSM_OVRD0_PLL_REG_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL_REG_EN_OVRD_MASK, XCVR_TSM_OVRD0_PLL_REG_EN_OVRD(value)))
35884 #define XCVR_BWR_TSM_OVRD0_PLL_REG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_PLL_REG_EN_OVRD_SHIFT), XCVR_TSM_OVRD0_PLL_REG_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_PLL_REG_EN_OVRD_WIDTH))
35885 /*@}*/
35886 
35887 /*!
35888  * @name Register XCVR_TSM_OVRD0, field PLL_VCO_REG_EN_OVRD_EN[2] (RW)
35889  *
35890  * Values:
35891  * - 0b0 - Normal operation.
35892  * - 0b1 - Use the state of PLL_VCO_REG_EN_OVRD to override the signal
35893  *     "pll_vco_reg_en".
35894  */
35895 /*@{*/
35896 /*! @brief Read current value of the XCVR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_EN field. */
35897 #define XCVR_RD_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_EN_SHIFT)
35898 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_EN_WIDTH))
35899 
35900 /*! @brief Set the PLL_VCO_REG_EN_OVRD_EN field to a new value. */
35901 #define XCVR_WR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_EN_MASK, XCVR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_EN(value)))
35902 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_EN_WIDTH))
35903 /*@}*/
35904 
35905 /*!
35906  * @name Register XCVR_TSM_OVRD0, field PLL_VCO_REG_EN_OVRD[3] (RW)
35907  *
35908  * When PLL_VCO_REG_EN_OVRD_EN=1, this value overrides the mission mode state of
35909  * the signal "pll_vco_reg_en". This bit is ignored when
35910  * PLL_VCO_REG_EN_OVRD_EN==0.
35911  */
35912 /*@{*/
35913 /*! @brief Read current value of the XCVR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD field. */
35914 #define XCVR_RD_TSM_OVRD0_PLL_VCO_REG_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_MASK) >> XCVR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_SHIFT)
35915 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_REG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_WIDTH))
35916 
35917 /*! @brief Set the PLL_VCO_REG_EN_OVRD field to a new value. */
35918 #define XCVR_WR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_MASK, XCVR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD(value)))
35919 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_SHIFT), XCVR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_PLL_VCO_REG_EN_OVRD_WIDTH))
35920 /*@}*/
35921 
35922 /*!
35923  * @name Register XCVR_TSM_OVRD0, field QGEN_REG_EN_OVRD_EN[4] (RW)
35924  *
35925  * Values:
35926  * - 0b0 - Normal operation.
35927  * - 0b1 - Use the state of QGEN_REG_EN_OVRD to override the signal
35928  *     "qgen_reg_en".
35929  */
35930 /*@{*/
35931 /*! @brief Read current value of the XCVR_TSM_OVRD0_QGEN_REG_EN_OVRD_EN field. */
35932 #define XCVR_RD_TSM_OVRD0_QGEN_REG_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_QGEN_REG_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD0_QGEN_REG_EN_OVRD_EN_SHIFT)
35933 #define XCVR_BRD_TSM_OVRD0_QGEN_REG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_QGEN_REG_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_QGEN_REG_EN_OVRD_EN_WIDTH))
35934 
35935 /*! @brief Set the QGEN_REG_EN_OVRD_EN field to a new value. */
35936 #define XCVR_WR_TSM_OVRD0_QGEN_REG_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_QGEN_REG_EN_OVRD_EN_MASK, XCVR_TSM_OVRD0_QGEN_REG_EN_OVRD_EN(value)))
35937 #define XCVR_BWR_TSM_OVRD0_QGEN_REG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_QGEN_REG_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD0_QGEN_REG_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_QGEN_REG_EN_OVRD_EN_WIDTH))
35938 /*@}*/
35939 
35940 /*!
35941  * @name Register XCVR_TSM_OVRD0, field QGEN_REG_EN_OVRD[5] (RW)
35942  *
35943  * When QGEN_REG_EN_OVRD_EN=1, this value overrides the mission mode state of
35944  * the signal "qgen_reg_en". This bit is ignored when QGEN_REG_EN_OVRD_EN==0.
35945  */
35946 /*@{*/
35947 /*! @brief Read current value of the XCVR_TSM_OVRD0_QGEN_REG_EN_OVRD field. */
35948 #define XCVR_RD_TSM_OVRD0_QGEN_REG_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_QGEN_REG_EN_OVRD_MASK) >> XCVR_TSM_OVRD0_QGEN_REG_EN_OVRD_SHIFT)
35949 #define XCVR_BRD_TSM_OVRD0_QGEN_REG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_QGEN_REG_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_QGEN_REG_EN_OVRD_WIDTH))
35950 
35951 /*! @brief Set the QGEN_REG_EN_OVRD field to a new value. */
35952 #define XCVR_WR_TSM_OVRD0_QGEN_REG_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_QGEN_REG_EN_OVRD_MASK, XCVR_TSM_OVRD0_QGEN_REG_EN_OVRD(value)))
35953 #define XCVR_BWR_TSM_OVRD0_QGEN_REG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_QGEN_REG_EN_OVRD_SHIFT), XCVR_TSM_OVRD0_QGEN_REG_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_QGEN_REG_EN_OVRD_WIDTH))
35954 /*@}*/
35955 
35956 /*!
35957  * @name Register XCVR_TSM_OVRD0, field TCA_TX_REG_EN_OVRD_EN[6] (RW)
35958  *
35959  * Values:
35960  * - 0b0 - Normal operation.
35961  * - 0b1 - Use the state of TCA_TX_REG_EN_OVRD to override the signal
35962  *     "tca_tx_reg_en".
35963  */
35964 /*@{*/
35965 /*! @brief Read current value of the XCVR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_EN field. */
35966 #define XCVR_RD_TSM_OVRD0_TCA_TX_REG_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_EN_SHIFT)
35967 #define XCVR_BRD_TSM_OVRD0_TCA_TX_REG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_EN_WIDTH))
35968 
35969 /*! @brief Set the TCA_TX_REG_EN_OVRD_EN field to a new value. */
35970 #define XCVR_WR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_EN_MASK, XCVR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_EN(value)))
35971 #define XCVR_BWR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_EN_WIDTH))
35972 /*@}*/
35973 
35974 /*!
35975  * @name Register XCVR_TSM_OVRD0, field TCA_TX_REG_EN_OVRD[7] (RW)
35976  *
35977  * When TCA_TX_REG_EN_OVRD_EN=1, this value overrides the mission mode state of
35978  * the signal "tca_tx_reg_en". This bit is ignored when TCA_TX_REG_EN_OVRD_EN==0.
35979  */
35980 /*@{*/
35981 /*! @brief Read current value of the XCVR_TSM_OVRD0_TCA_TX_REG_EN_OVRD field. */
35982 #define XCVR_RD_TSM_OVRD0_TCA_TX_REG_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_MASK) >> XCVR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_SHIFT)
35983 #define XCVR_BRD_TSM_OVRD0_TCA_TX_REG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_WIDTH))
35984 
35985 /*! @brief Set the TCA_TX_REG_EN_OVRD field to a new value. */
35986 #define XCVR_WR_TSM_OVRD0_TCA_TX_REG_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_MASK, XCVR_TSM_OVRD0_TCA_TX_REG_EN_OVRD(value)))
35987 #define XCVR_BWR_TSM_OVRD0_TCA_TX_REG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_SHIFT), XCVR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_TCA_TX_REG_EN_OVRD_WIDTH))
35988 /*@}*/
35989 
35990 /*!
35991  * @name Register XCVR_TSM_OVRD0, field ADC_ANA_REG_EN_OVRD_EN[8] (RW)
35992  *
35993  * Values:
35994  * - 0b0 - Normal operation.
35995  * - 0b1 - Use the state of ADC_ANA_REG_EN_OVRD to override the signal
35996  *     "adc_ana_reg_en".
35997  */
35998 /*@{*/
35999 /*! @brief Read current value of the XCVR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_EN field. */
36000 #define XCVR_RD_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_EN_SHIFT)
36001 #define XCVR_BRD_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_EN_WIDTH))
36002 
36003 /*! @brief Set the ADC_ANA_REG_EN_OVRD_EN field to a new value. */
36004 #define XCVR_WR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_EN_MASK, XCVR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_EN(value)))
36005 #define XCVR_BWR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_EN_WIDTH))
36006 /*@}*/
36007 
36008 /*!
36009  * @name Register XCVR_TSM_OVRD0, field ADC_ANA_REG_EN_OVRD[9] (RW)
36010  *
36011  * When ADC_ANA_REG_EN_OVRD_EN=1, this value overrides the mission mode state of
36012  * the signal "adc_ana_reg_en". This bit is ignored when
36013  * ADC_ANA_REG_EN_OVRD_EN==0.
36014  */
36015 /*@{*/
36016 /*! @brief Read current value of the XCVR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD field. */
36017 #define XCVR_RD_TSM_OVRD0_ADC_ANA_REG_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_MASK) >> XCVR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_SHIFT)
36018 #define XCVR_BRD_TSM_OVRD0_ADC_ANA_REG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_WIDTH))
36019 
36020 /*! @brief Set the ADC_ANA_REG_EN_OVRD field to a new value. */
36021 #define XCVR_WR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_MASK, XCVR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD(value)))
36022 #define XCVR_BWR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_SHIFT), XCVR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_ADC_ANA_REG_EN_OVRD_WIDTH))
36023 /*@}*/
36024 
36025 /*!
36026  * @name Register XCVR_TSM_OVRD0, field ADC_DIG_REG_EN_OVRD_EN[10] (RW)
36027  *
36028  * Values:
36029  * - 0b0 - Normal operation.
36030  * - 0b1 - Use the state of ADC_DIG_REG_EN_OVRD to override the signal
36031  *     "adc_dig_reg_en".
36032  */
36033 /*@{*/
36034 /*! @brief Read current value of the XCVR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_EN field. */
36035 #define XCVR_RD_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_EN_SHIFT)
36036 #define XCVR_BRD_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_EN_WIDTH))
36037 
36038 /*! @brief Set the ADC_DIG_REG_EN_OVRD_EN field to a new value. */
36039 #define XCVR_WR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_EN_MASK, XCVR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_EN(value)))
36040 #define XCVR_BWR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_EN_WIDTH))
36041 /*@}*/
36042 
36043 /*!
36044  * @name Register XCVR_TSM_OVRD0, field ADC_DIG_REG_EN_OVRD[11] (RW)
36045  *
36046  * When ADC_DIG_REG_EN_OVRD_EN=1, this value overrides the mission mode state of
36047  * the signal "adc_dig_reg_en". This bit is ignored when
36048  * ADC_DIG_REG_EN_OVRD_EN==0.
36049  */
36050 /*@{*/
36051 /*! @brief Read current value of the XCVR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD field. */
36052 #define XCVR_RD_TSM_OVRD0_ADC_DIG_REG_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_MASK) >> XCVR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_SHIFT)
36053 #define XCVR_BRD_TSM_OVRD0_ADC_DIG_REG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_WIDTH))
36054 
36055 /*! @brief Set the ADC_DIG_REG_EN_OVRD field to a new value. */
36056 #define XCVR_WR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_MASK, XCVR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD(value)))
36057 #define XCVR_BWR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_SHIFT), XCVR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_ADC_DIG_REG_EN_OVRD_WIDTH))
36058 /*@}*/
36059 
36060 /*!
36061  * @name Register XCVR_TSM_OVRD0, field XTAL_PLL_REF_CLK_EN_OVRD_EN[12] (RW)
36062  *
36063  * Values:
36064  * - 0b0 - Normal operation.
36065  * - 0b1 - Use the state of XTAL_PLL_REF_CLK_EN_OVRD to override the signal
36066  *     "xtal_pll_ref_clk_en".
36067  */
36068 /*@{*/
36069 /*! @brief Read current value of the XCVR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_EN field. */
36070 #define XCVR_RD_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_EN_SHIFT)
36071 #define XCVR_BRD_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_EN_WIDTH))
36072 
36073 /*! @brief Set the XTAL_PLL_REF_CLK_EN_OVRD_EN field to a new value. */
36074 #define XCVR_WR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_EN_MASK, XCVR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_EN(value)))
36075 #define XCVR_BWR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_EN_WIDTH))
36076 /*@}*/
36077 
36078 /*!
36079  * @name Register XCVR_TSM_OVRD0, field XTAL_PLL_REF_CLK_EN_OVRD[13] (RW)
36080  *
36081  * When XTAL_PLL_REF_CLK_EN_OVRD_EN=1, this value overrides the mission mode
36082  * state of the signal "xtal_pll_ref_clk_en". This bit is ignored when
36083  * XTAL_PLL_REF_CLK_EN_OVRD_EN==0.
36084  */
36085 /*@{*/
36086 /*! @brief Read current value of the XCVR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD field. */
36087 #define XCVR_RD_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_MASK) >> XCVR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_SHIFT)
36088 #define XCVR_BRD_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_WIDTH))
36089 
36090 /*! @brief Set the XTAL_PLL_REF_CLK_EN_OVRD field to a new value. */
36091 #define XCVR_WR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_MASK, XCVR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD(value)))
36092 #define XCVR_BWR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_SHIFT), XCVR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_XTAL_PLL_REF_CLK_EN_OVRD_WIDTH))
36093 /*@}*/
36094 
36095 /*!
36096  * @name Register XCVR_TSM_OVRD0, field XTAL_ADC_REF_CLK_EN_OVRD_EN[14] (RW)
36097  *
36098  * Values:
36099  * - 0b0 - Normal operation.
36100  * - 0b1 - Use the state of XTAL_ADC_REF_CLK_EN_OVRD to override the signal
36101  *     "xtal_adc_ref_clk_en".
36102  */
36103 /*@{*/
36104 /*! @brief Read current value of the XCVR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_EN field. */
36105 #define XCVR_RD_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_EN_SHIFT)
36106 #define XCVR_BRD_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_EN_WIDTH))
36107 
36108 /*! @brief Set the XTAL_ADC_REF_CLK_EN_OVRD_EN field to a new value. */
36109 #define XCVR_WR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_EN_MASK, XCVR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_EN(value)))
36110 #define XCVR_BWR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_EN_WIDTH))
36111 /*@}*/
36112 
36113 /*!
36114  * @name Register XCVR_TSM_OVRD0, field XTAL_ADC_REF_CLK_EN_OVRD[15] (RW)
36115  *
36116  * When XTAL_ADC_REF_CLK_EN_OVRD_EN=1, this value overrides the mission mode
36117  * state of the signal "xtal_adc_ref_clk_en". This bit is ignored when
36118  * XTAL_ADC_REF_CLK_EN_OVRD_EN==0.
36119  */
36120 /*@{*/
36121 /*! @brief Read current value of the XCVR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD field. */
36122 #define XCVR_RD_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_MASK) >> XCVR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_SHIFT)
36123 #define XCVR_BRD_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_WIDTH))
36124 
36125 /*! @brief Set the XTAL_ADC_REF_CLK_EN_OVRD field to a new value. */
36126 #define XCVR_WR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_MASK, XCVR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD(value)))
36127 #define XCVR_BWR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_SHIFT), XCVR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_XTAL_ADC_REF_CLK_EN_OVRD_WIDTH))
36128 /*@}*/
36129 
36130 /*!
36131  * @name Register XCVR_TSM_OVRD0, field PLL_VCO_AUTOTUNE_EN_OVRD_EN[16] (RW)
36132  *
36133  * Values:
36134  * - 0b0 - Normal operation.
36135  * - 0b1 - Use the state of PLL_VCO_AUTOTUNE_EN_OVRD to override the signal
36136  *     "pll_vco_autotune_en".
36137  */
36138 /*@{*/
36139 /*! @brief Read current value of the XCVR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_EN field. */
36140 #define XCVR_RD_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_EN_SHIFT)
36141 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_EN_WIDTH))
36142 
36143 /*! @brief Set the PLL_VCO_AUTOTUNE_EN_OVRD_EN field to a new value. */
36144 #define XCVR_WR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_EN_MASK, XCVR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_EN(value)))
36145 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_EN_WIDTH))
36146 /*@}*/
36147 
36148 /*!
36149  * @name Register XCVR_TSM_OVRD0, field PLL_VCO_AUTOTUNE_EN_OVRD[17] (RW)
36150  *
36151  * When PLL_VCO_AUTOTUNE_EN_OVRD_EN=1, this value overrides the mission mode
36152  * state of the signal "pll_vco_autotune_en". This bit is ignored when
36153  * PLL_VCO_AUTOTUNE_EN_OVRD_EN==0.
36154  */
36155 /*@{*/
36156 /*! @brief Read current value of the XCVR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD field. */
36157 #define XCVR_RD_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_MASK) >> XCVR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_SHIFT)
36158 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_WIDTH))
36159 
36160 /*! @brief Set the PLL_VCO_AUTOTUNE_EN_OVRD field to a new value. */
36161 #define XCVR_WR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_MASK, XCVR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD(value)))
36162 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_SHIFT), XCVR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_PLL_VCO_AUTOTUNE_EN_OVRD_WIDTH))
36163 /*@}*/
36164 
36165 /*!
36166  * @name Register XCVR_TSM_OVRD0, field PLL_CYCLE_SLIP_LD_EN_OVRD_EN[18] (RW)
36167  *
36168  * Values:
36169  * - 0b0 - Normal operation.
36170  * - 0b1 - Use the state of PLL_CYCLE_SLIP_LD_EN_OVRD to override the signal
36171  *     "pll_cycle_slip_ld_en".
36172  */
36173 /*@{*/
36174 /*! @brief Read current value of the XCVR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_EN field. */
36175 #define XCVR_RD_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_EN_SHIFT)
36176 #define XCVR_BRD_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_EN_WIDTH))
36177 
36178 /*! @brief Set the PLL_CYCLE_SLIP_LD_EN_OVRD_EN field to a new value. */
36179 #define XCVR_WR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_EN_MASK, XCVR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_EN(value)))
36180 #define XCVR_BWR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_EN_WIDTH))
36181 /*@}*/
36182 
36183 /*!
36184  * @name Register XCVR_TSM_OVRD0, field PLL_CYCLE_SLIP_LD_EN_OVRD[19] (RW)
36185  *
36186  * When PLL_CYCLE_SLIP_LD_EN_OVRD_EN=1, this value overrides the mission mode
36187  * state of the signal "pll_cycle_slip_ld_en". This bit is ignored when
36188  * PLL_CYCLE_SLIP_LD_EN_OVRD_EN==0.
36189  */
36190 /*@{*/
36191 /*! @brief Read current value of the XCVR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD field. */
36192 #define XCVR_RD_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_MASK) >> XCVR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_SHIFT)
36193 #define XCVR_BRD_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_WIDTH))
36194 
36195 /*! @brief Set the PLL_CYCLE_SLIP_LD_EN_OVRD field to a new value. */
36196 #define XCVR_WR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_MASK, XCVR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD(value)))
36197 #define XCVR_BWR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_SHIFT), XCVR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_PLL_CYCLE_SLIP_LD_EN_OVRD_WIDTH))
36198 /*@}*/
36199 
36200 /*!
36201  * @name Register XCVR_TSM_OVRD0, field PLL_VCO_EN_OVRD_EN[20] (RW)
36202  *
36203  * Values:
36204  * - 0b0 - Normal operation.
36205  * - 0b1 - Use the state of PLL_VCO_EN_OVRD to override the signal "pll_vco_en".
36206  */
36207 /*@{*/
36208 /*! @brief Read current value of the XCVR_TSM_OVRD0_PLL_VCO_EN_OVRD_EN field. */
36209 #define XCVR_RD_TSM_OVRD0_PLL_VCO_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_VCO_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD0_PLL_VCO_EN_OVRD_EN_SHIFT)
36210 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_PLL_VCO_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_PLL_VCO_EN_OVRD_EN_WIDTH))
36211 
36212 /*! @brief Set the PLL_VCO_EN_OVRD_EN field to a new value. */
36213 #define XCVR_WR_TSM_OVRD0_PLL_VCO_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL_VCO_EN_OVRD_EN_MASK, XCVR_TSM_OVRD0_PLL_VCO_EN_OVRD_EN(value)))
36214 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_PLL_VCO_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD0_PLL_VCO_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_PLL_VCO_EN_OVRD_EN_WIDTH))
36215 /*@}*/
36216 
36217 /*!
36218  * @name Register XCVR_TSM_OVRD0, field PLL_VCO_EN_OVRD[21] (RW)
36219  *
36220  * When PLL_VCO_EN_OVRD_EN=1, this value overrides the mission mode state of the
36221  * signal "pll_vco_en". This bit is ignored when PLL_VCO_EN_OVRD_EN==0.
36222  */
36223 /*@{*/
36224 /*! @brief Read current value of the XCVR_TSM_OVRD0_PLL_VCO_EN_OVRD field. */
36225 #define XCVR_RD_TSM_OVRD0_PLL_VCO_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_VCO_EN_OVRD_MASK) >> XCVR_TSM_OVRD0_PLL_VCO_EN_OVRD_SHIFT)
36226 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_PLL_VCO_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_PLL_VCO_EN_OVRD_WIDTH))
36227 
36228 /*! @brief Set the PLL_VCO_EN_OVRD field to a new value. */
36229 #define XCVR_WR_TSM_OVRD0_PLL_VCO_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL_VCO_EN_OVRD_MASK, XCVR_TSM_OVRD0_PLL_VCO_EN_OVRD(value)))
36230 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_PLL_VCO_EN_OVRD_SHIFT), XCVR_TSM_OVRD0_PLL_VCO_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_PLL_VCO_EN_OVRD_WIDTH))
36231 /*@}*/
36232 
36233 /*!
36234  * @name Register XCVR_TSM_OVRD0, field PLL_VCO_BUF_RX_EN_OVRD_EN[22] (RW)
36235  *
36236  * Values:
36237  * - 0b0 - Normal operation.
36238  * - 0b1 - Use the state of PLL_VCO_BUF_RX_EN_OVRD to override the signal
36239  *     "pll_vco_buf_rx_en".
36240  */
36241 /*@{*/
36242 /*! @brief Read current value of the XCVR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_EN field. */
36243 #define XCVR_RD_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_EN_SHIFT)
36244 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_EN_WIDTH))
36245 
36246 /*! @brief Set the PLL_VCO_BUF_RX_EN_OVRD_EN field to a new value. */
36247 #define XCVR_WR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_EN_MASK, XCVR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_EN(value)))
36248 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_EN_WIDTH))
36249 /*@}*/
36250 
36251 /*!
36252  * @name Register XCVR_TSM_OVRD0, field PLL_VCO_BUF_RX_EN_OVRD[23] (RW)
36253  *
36254  * When PLL_VCO_BUF_RX_EN_OVRD_EN=1, this value overrides the mission mode state
36255  * of the signal "pll_vco_buf_rx_en". This bit is ignored when
36256  * PLL_VCO_BUF_RX_EN_OVRD_EN==0.
36257  */
36258 /*@{*/
36259 /*! @brief Read current value of the XCVR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD field. */
36260 #define XCVR_RD_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_MASK) >> XCVR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_SHIFT)
36261 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_WIDTH))
36262 
36263 /*! @brief Set the PLL_VCO_BUF_RX_EN_OVRD field to a new value. */
36264 #define XCVR_WR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_MASK, XCVR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD(value)))
36265 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_SHIFT), XCVR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_PLL_VCO_BUF_RX_EN_OVRD_WIDTH))
36266 /*@}*/
36267 
36268 /*!
36269  * @name Register XCVR_TSM_OVRD0, field PLL_VCO_BUF_TX_EN_OVRD_EN[24] (RW)
36270  *
36271  * Values:
36272  * - 0b0 - Normal operation.
36273  * - 0b1 - Use the state of PLL_VCO_BUF_TX_EN_OVRD to override the signal
36274  *     "pll_vco_buf_tx_en".
36275  */
36276 /*@{*/
36277 /*! @brief Read current value of the XCVR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_EN field. */
36278 #define XCVR_RD_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_EN_SHIFT)
36279 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_EN_WIDTH))
36280 
36281 /*! @brief Set the PLL_VCO_BUF_TX_EN_OVRD_EN field to a new value. */
36282 #define XCVR_WR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_EN_MASK, XCVR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_EN(value)))
36283 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_EN_WIDTH))
36284 /*@}*/
36285 
36286 /*!
36287  * @name Register XCVR_TSM_OVRD0, field PLL_VCO_BUF_TX_EN_OVRD[25] (RW)
36288  *
36289  * When PLL_VCO_BUF_TX_EN_OVRD_EN=1, this value overrides the mission mode state
36290  * of the signal "pll_vco_buf_tx_en". This bit is ignored when
36291  * PLL_VCO_BUF_TX_EN_OVRD_EN==0.
36292  */
36293 /*@{*/
36294 /*! @brief Read current value of the XCVR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD field. */
36295 #define XCVR_RD_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_MASK) >> XCVR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_SHIFT)
36296 #define XCVR_BRD_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_WIDTH))
36297 
36298 /*! @brief Set the PLL_VCO_BUF_TX_EN_OVRD field to a new value. */
36299 #define XCVR_WR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_MASK, XCVR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD(value)))
36300 #define XCVR_BWR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_SHIFT), XCVR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_PLL_VCO_BUF_TX_EN_OVRD_WIDTH))
36301 /*@}*/
36302 
36303 /*!
36304  * @name Register XCVR_TSM_OVRD0, field PLL_PA_BUF_EN_OVRD_EN[26] (RW)
36305  *
36306  * Values:
36307  * - 0b0 - Normal operation.
36308  * - 0b1 - Use the state of PLL_PA_BUF_EN_OVRD to override the signal
36309  *     "pll_pa_buf_en".
36310  */
36311 /*@{*/
36312 /*! @brief Read current value of the XCVR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_EN field. */
36313 #define XCVR_RD_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_EN_SHIFT)
36314 #define XCVR_BRD_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_EN_WIDTH))
36315 
36316 /*! @brief Set the PLL_PA_BUF_EN_OVRD_EN field to a new value. */
36317 #define XCVR_WR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_EN_MASK, XCVR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_EN(value)))
36318 #define XCVR_BWR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_EN_WIDTH))
36319 /*@}*/
36320 
36321 /*!
36322  * @name Register XCVR_TSM_OVRD0, field PLL_PA_BUF_EN_OVRD[27] (RW)
36323  *
36324  * When PLL_PA_BUF_EN_OVRD_EN=1, this value overrides the mission mode state of
36325  * the signal "pll_pa_buf_en". This bit is ignored when PLL_PA_BUF_EN_OVRD_EN==0.
36326  */
36327 /*@{*/
36328 /*! @brief Read current value of the XCVR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD field. */
36329 #define XCVR_RD_TSM_OVRD0_PLL_PA_BUF_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_MASK) >> XCVR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_SHIFT)
36330 #define XCVR_BRD_TSM_OVRD0_PLL_PA_BUF_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_WIDTH))
36331 
36332 /*! @brief Set the PLL_PA_BUF_EN_OVRD field to a new value. */
36333 #define XCVR_WR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_MASK, XCVR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD(value)))
36334 #define XCVR_BWR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_SHIFT), XCVR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_PLL_PA_BUF_EN_OVRD_WIDTH))
36335 /*@}*/
36336 
36337 /*!
36338  * @name Register XCVR_TSM_OVRD0, field PLL_LDV_EN_OVRD_EN[28] (RW)
36339  *
36340  * Values:
36341  * - 0b0 - Normal operation.
36342  * - 0b1 - Use the state of PLL_LDV_EN_OVRD to override the signal "pll_ldv_en".
36343  */
36344 /*@{*/
36345 /*! @brief Read current value of the XCVR_TSM_OVRD0_PLL_LDV_EN_OVRD_EN field. */
36346 #define XCVR_RD_TSM_OVRD0_PLL_LDV_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_LDV_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD0_PLL_LDV_EN_OVRD_EN_SHIFT)
36347 #define XCVR_BRD_TSM_OVRD0_PLL_LDV_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_PLL_LDV_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_PLL_LDV_EN_OVRD_EN_WIDTH))
36348 
36349 /*! @brief Set the PLL_LDV_EN_OVRD_EN field to a new value. */
36350 #define XCVR_WR_TSM_OVRD0_PLL_LDV_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL_LDV_EN_OVRD_EN_MASK, XCVR_TSM_OVRD0_PLL_LDV_EN_OVRD_EN(value)))
36351 #define XCVR_BWR_TSM_OVRD0_PLL_LDV_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_PLL_LDV_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD0_PLL_LDV_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_PLL_LDV_EN_OVRD_EN_WIDTH))
36352 /*@}*/
36353 
36354 /*!
36355  * @name Register XCVR_TSM_OVRD0, field PLL_LDV_EN_OVRD[29] (RW)
36356  *
36357  * When PLL_LDV_EN_OVRD_EN=1, this value overrides the mission mode state of the
36358  * signal "pll_ldv_en". This bit is ignored when PLL_LDV_EN_OVRD_EN==0.
36359  */
36360 /*@{*/
36361 /*! @brief Read current value of the XCVR_TSM_OVRD0_PLL_LDV_EN_OVRD field. */
36362 #define XCVR_RD_TSM_OVRD0_PLL_LDV_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_LDV_EN_OVRD_MASK) >> XCVR_TSM_OVRD0_PLL_LDV_EN_OVRD_SHIFT)
36363 #define XCVR_BRD_TSM_OVRD0_PLL_LDV_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_PLL_LDV_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_PLL_LDV_EN_OVRD_WIDTH))
36364 
36365 /*! @brief Set the PLL_LDV_EN_OVRD field to a new value. */
36366 #define XCVR_WR_TSM_OVRD0_PLL_LDV_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL_LDV_EN_OVRD_MASK, XCVR_TSM_OVRD0_PLL_LDV_EN_OVRD(value)))
36367 #define XCVR_BWR_TSM_OVRD0_PLL_LDV_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_PLL_LDV_EN_OVRD_SHIFT), XCVR_TSM_OVRD0_PLL_LDV_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_PLL_LDV_EN_OVRD_WIDTH))
36368 /*@}*/
36369 
36370 /*!
36371  * @name Register XCVR_TSM_OVRD0, field PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN[30] (RW)
36372  *
36373  * Values:
36374  * - 0b0 - Normal operation.
36375  * - 0b1 - Use the state of PLL_RX_LDV_RIPPLE_MUX_EN_OVRD to override the signal
36376  *     "pll_rx_ldv_ripple_mux_en".
36377  */
36378 /*@{*/
36379 /*! @brief Read current value of the XCVR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN field. */
36380 #define XCVR_RD_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN_SHIFT)
36381 #define XCVR_BRD_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN_WIDTH))
36382 
36383 /*! @brief Set the PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN field to a new value. */
36384 #define XCVR_WR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN_MASK, XCVR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN(value)))
36385 #define XCVR_BWR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN_WIDTH))
36386 /*@}*/
36387 
36388 /*!
36389  * @name Register XCVR_TSM_OVRD0, field PLL_RX_LDV_RIPPLE_MUX_EN_OVRD[31] (RW)
36390  *
36391  * When PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN=1, this value overrides the mission
36392  * mode state of the signal "pll_rx_ldv_ripple_mux_en". This bit is ignored when
36393  * PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_EN==0.
36394  */
36395 /*@{*/
36396 /*! @brief Read current value of the XCVR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD field. */
36397 #define XCVR_RD_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD(base) ((XCVR_TSM_OVRD0_REG(base) & XCVR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_MASK) >> XCVR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_SHIFT)
36398 #define XCVR_BRD_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD0_REG(base), XCVR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_WIDTH))
36399 
36400 /*! @brief Set the PLL_RX_LDV_RIPPLE_MUX_EN_OVRD field to a new value. */
36401 #define XCVR_WR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD0(base, XCVR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_MASK, XCVR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD(value)))
36402 #define XCVR_BWR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD0_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_SHIFT), XCVR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_SHIFT, XCVR_TSM_OVRD0_PLL_RX_LDV_RIPPLE_MUX_EN_OVRD_WIDTH))
36403 /*@}*/
36404 
36405 /*******************************************************************************
36406  * XCVR_TSM_OVRD1 - TSM Override 1
36407  ******************************************************************************/
36408 
36409 /*!
36410  * @brief XCVR_TSM_OVRD1 - TSM Override 1 (RW)
36411  *
36412  * Reset value: 0x00000000U
36413  */
36414 /*!
36415  * @name Constants and macros for entire XCVR_TSM_OVRD1 register
36416  */
36417 /*@{*/
36418 #define XCVR_RD_TSM_OVRD1(base)  (XCVR_TSM_OVRD1_REG(base))
36419 #define XCVR_WR_TSM_OVRD1(base, value) (XCVR_TSM_OVRD1_REG(base) = (value))
36420 #define XCVR_RMW_TSM_OVRD1(base, mask, value) (XCVR_WR_TSM_OVRD1(base, (XCVR_RD_TSM_OVRD1(base) & ~(mask)) | (value)))
36421 #define XCVR_SET_TSM_OVRD1(base, value) (BME_OR32(&XCVR_TSM_OVRD1_REG(base), (uint32_t)(value)))
36422 #define XCVR_CLR_TSM_OVRD1(base, value) (BME_AND32(&XCVR_TSM_OVRD1_REG(base), (uint32_t)(~(value))))
36423 #define XCVR_TOG_TSM_OVRD1(base, value) (BME_XOR32(&XCVR_TSM_OVRD1_REG(base), (uint32_t)(value)))
36424 /*@}*/
36425 
36426 /*
36427  * Constants & macros for individual XCVR_TSM_OVRD1 bitfields
36428  */
36429 
36430 /*!
36431  * @name Register XCVR_TSM_OVRD1, field PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN[0] (RW)
36432  *
36433  * Values:
36434  * - 0b0 - Normal operation.
36435  * - 0b1 - Use the state of PLL_TX_LDV_RIPPLE_MUX_EN_OVRD to override the signal
36436  *     "pll_tx_ldv_ripple_mux_en".
36437  */
36438 /*@{*/
36439 /*! @brief Read current value of the XCVR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN field. */
36440 #define XCVR_RD_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN_SHIFT)
36441 #define XCVR_BRD_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN_WIDTH))
36442 
36443 /*! @brief Set the PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN field to a new value. */
36444 #define XCVR_WR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN_MASK, XCVR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN(value)))
36445 #define XCVR_BWR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN_WIDTH))
36446 /*@}*/
36447 
36448 /*!
36449  * @name Register XCVR_TSM_OVRD1, field PLL_TX_LDV_RIPPLE_MUX_EN_OVRD[1] (RW)
36450  *
36451  * When PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN=1, this value overrides the mission
36452  * mode state of the signal "pll_tx_ldv_ripple_mux_en". This bit is ignored when
36453  * PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_EN==0.
36454  */
36455 /*@{*/
36456 /*! @brief Read current value of the XCVR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD field. */
36457 #define XCVR_RD_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_MASK) >> XCVR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_SHIFT)
36458 #define XCVR_BRD_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_WIDTH))
36459 
36460 /*! @brief Set the PLL_TX_LDV_RIPPLE_MUX_EN_OVRD field to a new value. */
36461 #define XCVR_WR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_MASK, XCVR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD(value)))
36462 #define XCVR_BWR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_SHIFT), XCVR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_PLL_TX_LDV_RIPPLE_MUX_EN_OVRD_WIDTH))
36463 /*@}*/
36464 
36465 /*!
36466  * @name Register XCVR_TSM_OVRD1, field PLL_FILTER_CHARGE_EN_OVRD_EN[2] (RW)
36467  *
36468  * Values:
36469  * - 0b0 - Normal operation.
36470  * - 0b1 - Use the state of PLL_FILTER_CHARGE_EN_OVRD to override the signal
36471  *     "pll_filter_charge_en".
36472  */
36473 /*@{*/
36474 /*! @brief Read current value of the XCVR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_EN field. */
36475 #define XCVR_RD_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_EN_SHIFT)
36476 #define XCVR_BRD_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_EN_WIDTH))
36477 
36478 /*! @brief Set the PLL_FILTER_CHARGE_EN_OVRD_EN field to a new value. */
36479 #define XCVR_WR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_EN_MASK, XCVR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_EN(value)))
36480 #define XCVR_BWR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_EN_WIDTH))
36481 /*@}*/
36482 
36483 /*!
36484  * @name Register XCVR_TSM_OVRD1, field PLL_FILTER_CHARGE_EN_OVRD[3] (RW)
36485  *
36486  * When PLL_FILTER_CHARGE_EN_OVRD_EN=1, this value overrides the mission mode
36487  * state of the signal "pll_filter_charge_en". This bit is ignored when
36488  * PLL_FILTER_CHARGE_EN_OVRD_EN==0.
36489  */
36490 /*@{*/
36491 /*! @brief Read current value of the XCVR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD field. */
36492 #define XCVR_RD_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_MASK) >> XCVR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_SHIFT)
36493 #define XCVR_BRD_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_WIDTH))
36494 
36495 /*! @brief Set the PLL_FILTER_CHARGE_EN_OVRD field to a new value. */
36496 #define XCVR_WR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_MASK, XCVR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD(value)))
36497 #define XCVR_BWR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_SHIFT), XCVR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_PLL_FILTER_CHARGE_EN_OVRD_WIDTH))
36498 /*@}*/
36499 
36500 /*!
36501  * @name Register XCVR_TSM_OVRD1, field PLL_PHDET_EN_OVRD_EN[4] (RW)
36502  *
36503  * Values:
36504  * - 0b0 - Normal operation.
36505  * - 0b1 - Use the state of PLL_PHDET_EN_OVRD to override the signal
36506  *     "pll_phdet_en".
36507  */
36508 /*@{*/
36509 /*! @brief Read current value of the XCVR_TSM_OVRD1_PLL_PHDET_EN_OVRD_EN field. */
36510 #define XCVR_RD_TSM_OVRD1_PLL_PHDET_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_PLL_PHDET_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD1_PLL_PHDET_EN_OVRD_EN_SHIFT)
36511 #define XCVR_BRD_TSM_OVRD1_PLL_PHDET_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_PLL_PHDET_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_PLL_PHDET_EN_OVRD_EN_WIDTH))
36512 
36513 /*! @brief Set the PLL_PHDET_EN_OVRD_EN field to a new value. */
36514 #define XCVR_WR_TSM_OVRD1_PLL_PHDET_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_PLL_PHDET_EN_OVRD_EN_MASK, XCVR_TSM_OVRD1_PLL_PHDET_EN_OVRD_EN(value)))
36515 #define XCVR_BWR_TSM_OVRD1_PLL_PHDET_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_PLL_PHDET_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD1_PLL_PHDET_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_PLL_PHDET_EN_OVRD_EN_WIDTH))
36516 /*@}*/
36517 
36518 /*!
36519  * @name Register XCVR_TSM_OVRD1, field PLL_PHDET_EN_OVRD[5] (RW)
36520  *
36521  * When PLL_PHDET_EN_OVRD_EN=1, this value overrides the mission mode state of
36522  * the signal "pll_phdet_en". This bit is ignored when PLL_PHDET_EN_OVRD_EN==0.
36523  */
36524 /*@{*/
36525 /*! @brief Read current value of the XCVR_TSM_OVRD1_PLL_PHDET_EN_OVRD field. */
36526 #define XCVR_RD_TSM_OVRD1_PLL_PHDET_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_PLL_PHDET_EN_OVRD_MASK) >> XCVR_TSM_OVRD1_PLL_PHDET_EN_OVRD_SHIFT)
36527 #define XCVR_BRD_TSM_OVRD1_PLL_PHDET_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_PLL_PHDET_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_PLL_PHDET_EN_OVRD_WIDTH))
36528 
36529 /*! @brief Set the PLL_PHDET_EN_OVRD field to a new value. */
36530 #define XCVR_WR_TSM_OVRD1_PLL_PHDET_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_PLL_PHDET_EN_OVRD_MASK, XCVR_TSM_OVRD1_PLL_PHDET_EN_OVRD(value)))
36531 #define XCVR_BWR_TSM_OVRD1_PLL_PHDET_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_PLL_PHDET_EN_OVRD_SHIFT), XCVR_TSM_OVRD1_PLL_PHDET_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_PLL_PHDET_EN_OVRD_WIDTH))
36532 /*@}*/
36533 
36534 /*!
36535  * @name Register XCVR_TSM_OVRD1, field QGEN25_EN_OVRD_EN[6] (RW)
36536  *
36537  * Values:
36538  * - 0b0 - Normal operation.
36539  * - 0b1 - Use the state of QGEN25_EN_OVRD to override the signal "qgen25_en".
36540  */
36541 /*@{*/
36542 /*! @brief Read current value of the XCVR_TSM_OVRD1_QGEN25_EN_OVRD_EN field. */
36543 #define XCVR_RD_TSM_OVRD1_QGEN25_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_QGEN25_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD1_QGEN25_EN_OVRD_EN_SHIFT)
36544 #define XCVR_BRD_TSM_OVRD1_QGEN25_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_QGEN25_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_QGEN25_EN_OVRD_EN_WIDTH))
36545 
36546 /*! @brief Set the QGEN25_EN_OVRD_EN field to a new value. */
36547 #define XCVR_WR_TSM_OVRD1_QGEN25_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_QGEN25_EN_OVRD_EN_MASK, XCVR_TSM_OVRD1_QGEN25_EN_OVRD_EN(value)))
36548 #define XCVR_BWR_TSM_OVRD1_QGEN25_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_QGEN25_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD1_QGEN25_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_QGEN25_EN_OVRD_EN_WIDTH))
36549 /*@}*/
36550 
36551 /*!
36552  * @name Register XCVR_TSM_OVRD1, field QGEN25_EN_OVRD[7] (RW)
36553  *
36554  * When QGEN25_EN_OVRD_EN=1, this value overrides the mission mode state of the
36555  * signal "qgen25_en". This bit is ignored when QGEN25_EN_OVRD_EN==0.
36556  */
36557 /*@{*/
36558 /*! @brief Read current value of the XCVR_TSM_OVRD1_QGEN25_EN_OVRD field. */
36559 #define XCVR_RD_TSM_OVRD1_QGEN25_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_QGEN25_EN_OVRD_MASK) >> XCVR_TSM_OVRD1_QGEN25_EN_OVRD_SHIFT)
36560 #define XCVR_BRD_TSM_OVRD1_QGEN25_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_QGEN25_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_QGEN25_EN_OVRD_WIDTH))
36561 
36562 /*! @brief Set the QGEN25_EN_OVRD field to a new value. */
36563 #define XCVR_WR_TSM_OVRD1_QGEN25_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_QGEN25_EN_OVRD_MASK, XCVR_TSM_OVRD1_QGEN25_EN_OVRD(value)))
36564 #define XCVR_BWR_TSM_OVRD1_QGEN25_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_QGEN25_EN_OVRD_SHIFT), XCVR_TSM_OVRD1_QGEN25_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_QGEN25_EN_OVRD_WIDTH))
36565 /*@}*/
36566 
36567 /*!
36568  * @name Register XCVR_TSM_OVRD1, field TX_EN_OVRD_EN[8] (RW)
36569  *
36570  * Values:
36571  * - 0b0 - Normal operation.
36572  * - 0b1 - Use the state of TX_EN_OVRD to override the signal "tx_en".
36573  */
36574 /*@{*/
36575 /*! @brief Read current value of the XCVR_TSM_OVRD1_TX_EN_OVRD_EN field. */
36576 #define XCVR_RD_TSM_OVRD1_TX_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_TX_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD1_TX_EN_OVRD_EN_SHIFT)
36577 #define XCVR_BRD_TSM_OVRD1_TX_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_TX_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_TX_EN_OVRD_EN_WIDTH))
36578 
36579 /*! @brief Set the TX_EN_OVRD_EN field to a new value. */
36580 #define XCVR_WR_TSM_OVRD1_TX_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_TX_EN_OVRD_EN_MASK, XCVR_TSM_OVRD1_TX_EN_OVRD_EN(value)))
36581 #define XCVR_BWR_TSM_OVRD1_TX_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_TX_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD1_TX_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_TX_EN_OVRD_EN_WIDTH))
36582 /*@}*/
36583 
36584 /*!
36585  * @name Register XCVR_TSM_OVRD1, field TX_EN_OVRD[9] (RW)
36586  *
36587  * When TX_EN_OVRD_EN=1, this value overrides the mission mode state of the
36588  * signal "tx_en". This bit is ignored when TX_EN_OVRD_EN==0.
36589  */
36590 /*@{*/
36591 /*! @brief Read current value of the XCVR_TSM_OVRD1_TX_EN_OVRD field. */
36592 #define XCVR_RD_TSM_OVRD1_TX_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_TX_EN_OVRD_MASK) >> XCVR_TSM_OVRD1_TX_EN_OVRD_SHIFT)
36593 #define XCVR_BRD_TSM_OVRD1_TX_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_TX_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_TX_EN_OVRD_WIDTH))
36594 
36595 /*! @brief Set the TX_EN_OVRD field to a new value. */
36596 #define XCVR_WR_TSM_OVRD1_TX_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_TX_EN_OVRD_MASK, XCVR_TSM_OVRD1_TX_EN_OVRD(value)))
36597 #define XCVR_BWR_TSM_OVRD1_TX_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_TX_EN_OVRD_SHIFT), XCVR_TSM_OVRD1_TX_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_TX_EN_OVRD_WIDTH))
36598 /*@}*/
36599 
36600 /*!
36601  * @name Register XCVR_TSM_OVRD1, field ADC_EN_OVRD_EN[10] (RW)
36602  *
36603  * Values:
36604  * - 0b0 - Normal operation.
36605  * - 0b1 - Use the state of ADC_EN_OVRD to override the signal "adc_en".
36606  */
36607 /*@{*/
36608 /*! @brief Read current value of the XCVR_TSM_OVRD1_ADC_EN_OVRD_EN field. */
36609 #define XCVR_RD_TSM_OVRD1_ADC_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD1_ADC_EN_OVRD_EN_SHIFT)
36610 #define XCVR_BRD_TSM_OVRD1_ADC_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_ADC_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_ADC_EN_OVRD_EN_WIDTH))
36611 
36612 /*! @brief Set the ADC_EN_OVRD_EN field to a new value. */
36613 #define XCVR_WR_TSM_OVRD1_ADC_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_ADC_EN_OVRD_EN_MASK, XCVR_TSM_OVRD1_ADC_EN_OVRD_EN(value)))
36614 #define XCVR_BWR_TSM_OVRD1_ADC_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_ADC_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD1_ADC_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_ADC_EN_OVRD_EN_WIDTH))
36615 /*@}*/
36616 
36617 /*!
36618  * @name Register XCVR_TSM_OVRD1, field ADC_EN_OVRD[11] (RW)
36619  *
36620  * When ADC_EN_OVRD_EN=1, this value overrides the mission mode state of the
36621  * signal "adc_en". This bit is ignored when ADC_EN_OVRD_EN==0.
36622  */
36623 /*@{*/
36624 /*! @brief Read current value of the XCVR_TSM_OVRD1_ADC_EN_OVRD field. */
36625 #define XCVR_RD_TSM_OVRD1_ADC_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_EN_OVRD_MASK) >> XCVR_TSM_OVRD1_ADC_EN_OVRD_SHIFT)
36626 #define XCVR_BRD_TSM_OVRD1_ADC_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_ADC_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_ADC_EN_OVRD_WIDTH))
36627 
36628 /*! @brief Set the ADC_EN_OVRD field to a new value. */
36629 #define XCVR_WR_TSM_OVRD1_ADC_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_ADC_EN_OVRD_MASK, XCVR_TSM_OVRD1_ADC_EN_OVRD(value)))
36630 #define XCVR_BWR_TSM_OVRD1_ADC_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_ADC_EN_OVRD_SHIFT), XCVR_TSM_OVRD1_ADC_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_ADC_EN_OVRD_WIDTH))
36631 /*@}*/
36632 
36633 /*!
36634  * @name Register XCVR_TSM_OVRD1, field ADC_BIAS_EN_OVRD_EN[12] (RW)
36635  *
36636  * Values:
36637  * - 0b0 - Normal operation.
36638  * - 0b1 - Use the state of ADC_BIAS_EN_OVRD to override the signal
36639  *     "adc_bias_en".
36640  */
36641 /*@{*/
36642 /*! @brief Read current value of the XCVR_TSM_OVRD1_ADC_BIAS_EN_OVRD_EN field. */
36643 #define XCVR_RD_TSM_OVRD1_ADC_BIAS_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_BIAS_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD1_ADC_BIAS_EN_OVRD_EN_SHIFT)
36644 #define XCVR_BRD_TSM_OVRD1_ADC_BIAS_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_ADC_BIAS_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_ADC_BIAS_EN_OVRD_EN_WIDTH))
36645 
36646 /*! @brief Set the ADC_BIAS_EN_OVRD_EN field to a new value. */
36647 #define XCVR_WR_TSM_OVRD1_ADC_BIAS_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_ADC_BIAS_EN_OVRD_EN_MASK, XCVR_TSM_OVRD1_ADC_BIAS_EN_OVRD_EN(value)))
36648 #define XCVR_BWR_TSM_OVRD1_ADC_BIAS_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_ADC_BIAS_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD1_ADC_BIAS_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_ADC_BIAS_EN_OVRD_EN_WIDTH))
36649 /*@}*/
36650 
36651 /*!
36652  * @name Register XCVR_TSM_OVRD1, field ADC_BIAS_EN_OVRD[13] (RW)
36653  *
36654  * When ADC_BIAS_EN_OVRD_EN=1, this value overrides the mission mode state of
36655  * the signal "adc_bias_en". This bit is ignored when ADC_BIAS_EN_OVRD_EN==0.
36656  */
36657 /*@{*/
36658 /*! @brief Read current value of the XCVR_TSM_OVRD1_ADC_BIAS_EN_OVRD field. */
36659 #define XCVR_RD_TSM_OVRD1_ADC_BIAS_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_BIAS_EN_OVRD_MASK) >> XCVR_TSM_OVRD1_ADC_BIAS_EN_OVRD_SHIFT)
36660 #define XCVR_BRD_TSM_OVRD1_ADC_BIAS_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_ADC_BIAS_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_ADC_BIAS_EN_OVRD_WIDTH))
36661 
36662 /*! @brief Set the ADC_BIAS_EN_OVRD field to a new value. */
36663 #define XCVR_WR_TSM_OVRD1_ADC_BIAS_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_ADC_BIAS_EN_OVRD_MASK, XCVR_TSM_OVRD1_ADC_BIAS_EN_OVRD(value)))
36664 #define XCVR_BWR_TSM_OVRD1_ADC_BIAS_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_ADC_BIAS_EN_OVRD_SHIFT), XCVR_TSM_OVRD1_ADC_BIAS_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_ADC_BIAS_EN_OVRD_WIDTH))
36665 /*@}*/
36666 
36667 /*!
36668  * @name Register XCVR_TSM_OVRD1, field ADC_CLK_EN_OVRD_EN[14] (RW)
36669  *
36670  * Values:
36671  * - 0b0 - Normal operation.
36672  * - 0b1 - Use the state of ADC_CLK_EN_OVRD to override the signal "adc_clk_en".
36673  */
36674 /*@{*/
36675 /*! @brief Read current value of the XCVR_TSM_OVRD1_ADC_CLK_EN_OVRD_EN field. */
36676 #define XCVR_RD_TSM_OVRD1_ADC_CLK_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_CLK_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD1_ADC_CLK_EN_OVRD_EN_SHIFT)
36677 #define XCVR_BRD_TSM_OVRD1_ADC_CLK_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_ADC_CLK_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_ADC_CLK_EN_OVRD_EN_WIDTH))
36678 
36679 /*! @brief Set the ADC_CLK_EN_OVRD_EN field to a new value. */
36680 #define XCVR_WR_TSM_OVRD1_ADC_CLK_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_ADC_CLK_EN_OVRD_EN_MASK, XCVR_TSM_OVRD1_ADC_CLK_EN_OVRD_EN(value)))
36681 #define XCVR_BWR_TSM_OVRD1_ADC_CLK_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_ADC_CLK_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD1_ADC_CLK_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_ADC_CLK_EN_OVRD_EN_WIDTH))
36682 /*@}*/
36683 
36684 /*!
36685  * @name Register XCVR_TSM_OVRD1, field ADC_CLK_EN_OVRD[15] (RW)
36686  *
36687  * When ADC_CLK_EN_OVRD_EN=1, this value overrides the mission mode state of the
36688  * signal "adc_clk_en". This bit is ignored when ADC_CLK_EN_OVRD_EN==0.
36689  */
36690 /*@{*/
36691 /*! @brief Read current value of the XCVR_TSM_OVRD1_ADC_CLK_EN_OVRD field. */
36692 #define XCVR_RD_TSM_OVRD1_ADC_CLK_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_CLK_EN_OVRD_MASK) >> XCVR_TSM_OVRD1_ADC_CLK_EN_OVRD_SHIFT)
36693 #define XCVR_BRD_TSM_OVRD1_ADC_CLK_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_ADC_CLK_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_ADC_CLK_EN_OVRD_WIDTH))
36694 
36695 /*! @brief Set the ADC_CLK_EN_OVRD field to a new value. */
36696 #define XCVR_WR_TSM_OVRD1_ADC_CLK_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_ADC_CLK_EN_OVRD_MASK, XCVR_TSM_OVRD1_ADC_CLK_EN_OVRD(value)))
36697 #define XCVR_BWR_TSM_OVRD1_ADC_CLK_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_ADC_CLK_EN_OVRD_SHIFT), XCVR_TSM_OVRD1_ADC_CLK_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_ADC_CLK_EN_OVRD_WIDTH))
36698 /*@}*/
36699 
36700 /*!
36701  * @name Register XCVR_TSM_OVRD1, field ADC_I_ADC_EN_OVRD_EN[16] (RW)
36702  *
36703  * Values:
36704  * - 0b0 - Normal operation.
36705  * - 0b1 - Use the state of ADC_I_ADC_EN_OVRD to override the signal
36706  *     "adc_i_adc_en".
36707  */
36708 /*@{*/
36709 /*! @brief Read current value of the XCVR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_EN field. */
36710 #define XCVR_RD_TSM_OVRD1_ADC_I_ADC_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_EN_SHIFT)
36711 #define XCVR_BRD_TSM_OVRD1_ADC_I_ADC_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_EN_WIDTH))
36712 
36713 /*! @brief Set the ADC_I_ADC_EN_OVRD_EN field to a new value. */
36714 #define XCVR_WR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_EN_MASK, XCVR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_EN(value)))
36715 #define XCVR_BWR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_EN_WIDTH))
36716 /*@}*/
36717 
36718 /*!
36719  * @name Register XCVR_TSM_OVRD1, field ADC_I_ADC_EN_OVRD[17] (RW)
36720  *
36721  * When ADC_I_ADC_EN_OVRD_EN=1, this value overrides the mission mode state of
36722  * the signal "adc_i_adc_en". This bit is ignored when ADC_I_ADC_EN_OVRD_EN==0.
36723  */
36724 /*@{*/
36725 /*! @brief Read current value of the XCVR_TSM_OVRD1_ADC_I_ADC_EN_OVRD field. */
36726 #define XCVR_RD_TSM_OVRD1_ADC_I_ADC_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_MASK) >> XCVR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_SHIFT)
36727 #define XCVR_BRD_TSM_OVRD1_ADC_I_ADC_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_WIDTH))
36728 
36729 /*! @brief Set the ADC_I_ADC_EN_OVRD field to a new value. */
36730 #define XCVR_WR_TSM_OVRD1_ADC_I_ADC_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_MASK, XCVR_TSM_OVRD1_ADC_I_ADC_EN_OVRD(value)))
36731 #define XCVR_BWR_TSM_OVRD1_ADC_I_ADC_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_SHIFT), XCVR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_ADC_I_ADC_EN_OVRD_WIDTH))
36732 /*@}*/
36733 
36734 /*!
36735  * @name Register XCVR_TSM_OVRD1, field ADC_Q_ADC_EN_OVRD_EN[18] (RW)
36736  *
36737  * Values:
36738  * - 0b0 - Normal operation.
36739  * - 0b1 - Use the state of ADC_Q_ADC_EN_OVRD to override the signal
36740  *     "adc_q_adc_en".
36741  */
36742 /*@{*/
36743 /*! @brief Read current value of the XCVR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_EN field. */
36744 #define XCVR_RD_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_EN_SHIFT)
36745 #define XCVR_BRD_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_EN_WIDTH))
36746 
36747 /*! @brief Set the ADC_Q_ADC_EN_OVRD_EN field to a new value. */
36748 #define XCVR_WR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_EN_MASK, XCVR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_EN(value)))
36749 #define XCVR_BWR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_EN_WIDTH))
36750 /*@}*/
36751 
36752 /*!
36753  * @name Register XCVR_TSM_OVRD1, field ADC_Q_ADC_EN_OVRD[19] (RW)
36754  *
36755  * When ADC_Q_ADC_EN_OVRD_EN=1, this value overrides the mission mode state of
36756  * the signal "adc_q_adc_en". This bit is ignored when ADC_Q_ADC_EN_OVRD_EN==0.
36757  */
36758 /*@{*/
36759 /*! @brief Read current value of the XCVR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD field. */
36760 #define XCVR_RD_TSM_OVRD1_ADC_Q_ADC_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_MASK) >> XCVR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_SHIFT)
36761 #define XCVR_BRD_TSM_OVRD1_ADC_Q_ADC_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_WIDTH))
36762 
36763 /*! @brief Set the ADC_Q_ADC_EN_OVRD field to a new value. */
36764 #define XCVR_WR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_MASK, XCVR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD(value)))
36765 #define XCVR_BWR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_SHIFT), XCVR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_ADC_Q_ADC_EN_OVRD_WIDTH))
36766 /*@}*/
36767 
36768 /*!
36769  * @name Register XCVR_TSM_OVRD1, field ADC_DAC1_EN_OVRD_EN[20] (RW)
36770  *
36771  * Values:
36772  * - 0b0 - Normal operation.
36773  * - 0b1 - Use the state of ADC_DAC1_EN_OVRD to override the signal
36774  *     "adc_dac1_en".
36775  */
36776 /*@{*/
36777 /*! @brief Read current value of the XCVR_TSM_OVRD1_ADC_DAC1_EN_OVRD_EN field. */
36778 #define XCVR_RD_TSM_OVRD1_ADC_DAC1_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_DAC1_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD1_ADC_DAC1_EN_OVRD_EN_SHIFT)
36779 #define XCVR_BRD_TSM_OVRD1_ADC_DAC1_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_ADC_DAC1_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_ADC_DAC1_EN_OVRD_EN_WIDTH))
36780 
36781 /*! @brief Set the ADC_DAC1_EN_OVRD_EN field to a new value. */
36782 #define XCVR_WR_TSM_OVRD1_ADC_DAC1_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_ADC_DAC1_EN_OVRD_EN_MASK, XCVR_TSM_OVRD1_ADC_DAC1_EN_OVRD_EN(value)))
36783 #define XCVR_BWR_TSM_OVRD1_ADC_DAC1_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_ADC_DAC1_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD1_ADC_DAC1_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_ADC_DAC1_EN_OVRD_EN_WIDTH))
36784 /*@}*/
36785 
36786 /*!
36787  * @name Register XCVR_TSM_OVRD1, field ADC_DAC1_EN_OVRD[21] (RW)
36788  *
36789  * When ADC_DAC1_EN_OVRD_EN=1, this value overrides the mission mode state of
36790  * the signal "adc_dac1_en". This bit is ignored when ADC_DAC1_EN_OVRD_EN==0.
36791  */
36792 /*@{*/
36793 /*! @brief Read current value of the XCVR_TSM_OVRD1_ADC_DAC1_EN_OVRD field. */
36794 #define XCVR_RD_TSM_OVRD1_ADC_DAC1_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_DAC1_EN_OVRD_MASK) >> XCVR_TSM_OVRD1_ADC_DAC1_EN_OVRD_SHIFT)
36795 #define XCVR_BRD_TSM_OVRD1_ADC_DAC1_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_ADC_DAC1_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_ADC_DAC1_EN_OVRD_WIDTH))
36796 
36797 /*! @brief Set the ADC_DAC1_EN_OVRD field to a new value. */
36798 #define XCVR_WR_TSM_OVRD1_ADC_DAC1_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_ADC_DAC1_EN_OVRD_MASK, XCVR_TSM_OVRD1_ADC_DAC1_EN_OVRD(value)))
36799 #define XCVR_BWR_TSM_OVRD1_ADC_DAC1_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_ADC_DAC1_EN_OVRD_SHIFT), XCVR_TSM_OVRD1_ADC_DAC1_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_ADC_DAC1_EN_OVRD_WIDTH))
36800 /*@}*/
36801 
36802 /*!
36803  * @name Register XCVR_TSM_OVRD1, field ADC_DAC2_EN_OVRD_EN[22] (RW)
36804  *
36805  * Values:
36806  * - 0b0 - Normal operation.
36807  * - 0b1 - Use the state of ADC_DAC2_EN_OVRD to override the signal
36808  *     "adc_dac2_en".
36809  */
36810 /*@{*/
36811 /*! @brief Read current value of the XCVR_TSM_OVRD1_ADC_DAC2_EN_OVRD_EN field. */
36812 #define XCVR_RD_TSM_OVRD1_ADC_DAC2_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_DAC2_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD1_ADC_DAC2_EN_OVRD_EN_SHIFT)
36813 #define XCVR_BRD_TSM_OVRD1_ADC_DAC2_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_ADC_DAC2_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_ADC_DAC2_EN_OVRD_EN_WIDTH))
36814 
36815 /*! @brief Set the ADC_DAC2_EN_OVRD_EN field to a new value. */
36816 #define XCVR_WR_TSM_OVRD1_ADC_DAC2_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_ADC_DAC2_EN_OVRD_EN_MASK, XCVR_TSM_OVRD1_ADC_DAC2_EN_OVRD_EN(value)))
36817 #define XCVR_BWR_TSM_OVRD1_ADC_DAC2_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_ADC_DAC2_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD1_ADC_DAC2_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_ADC_DAC2_EN_OVRD_EN_WIDTH))
36818 /*@}*/
36819 
36820 /*!
36821  * @name Register XCVR_TSM_OVRD1, field ADC_DAC2_EN_OVRD[23] (RW)
36822  *
36823  * When ADC_DAC2_EN_OVRD_EN=1, this value overrides the mission mode state of
36824  * the signal "adc_dac2_en". This bit is ignored when ADC_DAC2_EN_OVRD_EN==0.
36825  */
36826 /*@{*/
36827 /*! @brief Read current value of the XCVR_TSM_OVRD1_ADC_DAC2_EN_OVRD field. */
36828 #define XCVR_RD_TSM_OVRD1_ADC_DAC2_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_DAC2_EN_OVRD_MASK) >> XCVR_TSM_OVRD1_ADC_DAC2_EN_OVRD_SHIFT)
36829 #define XCVR_BRD_TSM_OVRD1_ADC_DAC2_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_ADC_DAC2_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_ADC_DAC2_EN_OVRD_WIDTH))
36830 
36831 /*! @brief Set the ADC_DAC2_EN_OVRD field to a new value. */
36832 #define XCVR_WR_TSM_OVRD1_ADC_DAC2_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_ADC_DAC2_EN_OVRD_MASK, XCVR_TSM_OVRD1_ADC_DAC2_EN_OVRD(value)))
36833 #define XCVR_BWR_TSM_OVRD1_ADC_DAC2_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_ADC_DAC2_EN_OVRD_SHIFT), XCVR_TSM_OVRD1_ADC_DAC2_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_ADC_DAC2_EN_OVRD_WIDTH))
36834 /*@}*/
36835 
36836 /*!
36837  * @name Register XCVR_TSM_OVRD1, field ADC_RST_EN_OVRD_EN[24] (RW)
36838  *
36839  * Values:
36840  * - 0b0 - Normal operation.
36841  * - 0b1 - Use the state of ADC_RST_EN_OVRD to override the signal "adc_rst_en".
36842  */
36843 /*@{*/
36844 /*! @brief Read current value of the XCVR_TSM_OVRD1_ADC_RST_EN_OVRD_EN field. */
36845 #define XCVR_RD_TSM_OVRD1_ADC_RST_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_RST_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD1_ADC_RST_EN_OVRD_EN_SHIFT)
36846 #define XCVR_BRD_TSM_OVRD1_ADC_RST_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_ADC_RST_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_ADC_RST_EN_OVRD_EN_WIDTH))
36847 
36848 /*! @brief Set the ADC_RST_EN_OVRD_EN field to a new value. */
36849 #define XCVR_WR_TSM_OVRD1_ADC_RST_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_ADC_RST_EN_OVRD_EN_MASK, XCVR_TSM_OVRD1_ADC_RST_EN_OVRD_EN(value)))
36850 #define XCVR_BWR_TSM_OVRD1_ADC_RST_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_ADC_RST_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD1_ADC_RST_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_ADC_RST_EN_OVRD_EN_WIDTH))
36851 /*@}*/
36852 
36853 /*!
36854  * @name Register XCVR_TSM_OVRD1, field ADC_RST_EN_OVRD[25] (RW)
36855  *
36856  * When ADC_RST_EN_OVRD_EN=1, this value overrides the mission mode state of the
36857  * signal "adc_rst_en". This bit is ignored when ADC_RST_EN_OVRD_EN==0.
36858  */
36859 /*@{*/
36860 /*! @brief Read current value of the XCVR_TSM_OVRD1_ADC_RST_EN_OVRD field. */
36861 #define XCVR_RD_TSM_OVRD1_ADC_RST_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_ADC_RST_EN_OVRD_MASK) >> XCVR_TSM_OVRD1_ADC_RST_EN_OVRD_SHIFT)
36862 #define XCVR_BRD_TSM_OVRD1_ADC_RST_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_ADC_RST_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_ADC_RST_EN_OVRD_WIDTH))
36863 
36864 /*! @brief Set the ADC_RST_EN_OVRD field to a new value. */
36865 #define XCVR_WR_TSM_OVRD1_ADC_RST_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_ADC_RST_EN_OVRD_MASK, XCVR_TSM_OVRD1_ADC_RST_EN_OVRD(value)))
36866 #define XCVR_BWR_TSM_OVRD1_ADC_RST_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_ADC_RST_EN_OVRD_SHIFT), XCVR_TSM_OVRD1_ADC_RST_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_ADC_RST_EN_OVRD_WIDTH))
36867 /*@}*/
36868 
36869 /*!
36870  * @name Register XCVR_TSM_OVRD1, field BBF_I_EN_OVRD_EN[26] (RW)
36871  *
36872  * Values:
36873  * - 0b0 - Normal operation.
36874  * - 0b1 - Use the state of BBF_I_EN_OVRD to override the signal "bbf_i_en".
36875  */
36876 /*@{*/
36877 /*! @brief Read current value of the XCVR_TSM_OVRD1_BBF_I_EN_OVRD_EN field. */
36878 #define XCVR_RD_TSM_OVRD1_BBF_I_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_BBF_I_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD1_BBF_I_EN_OVRD_EN_SHIFT)
36879 #define XCVR_BRD_TSM_OVRD1_BBF_I_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_BBF_I_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_BBF_I_EN_OVRD_EN_WIDTH))
36880 
36881 /*! @brief Set the BBF_I_EN_OVRD_EN field to a new value. */
36882 #define XCVR_WR_TSM_OVRD1_BBF_I_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_BBF_I_EN_OVRD_EN_MASK, XCVR_TSM_OVRD1_BBF_I_EN_OVRD_EN(value)))
36883 #define XCVR_BWR_TSM_OVRD1_BBF_I_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_BBF_I_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD1_BBF_I_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_BBF_I_EN_OVRD_EN_WIDTH))
36884 /*@}*/
36885 
36886 /*!
36887  * @name Register XCVR_TSM_OVRD1, field BBF_I_EN_OVRD[27] (RW)
36888  *
36889  * When BBF_I_EN_OVRD_EN=1, this value overrides the mission mode state of the
36890  * signal "bbf_i_en". This bit is ignored when BBF_I_EN_OVRD_EN==0.
36891  */
36892 /*@{*/
36893 /*! @brief Read current value of the XCVR_TSM_OVRD1_BBF_I_EN_OVRD field. */
36894 #define XCVR_RD_TSM_OVRD1_BBF_I_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_BBF_I_EN_OVRD_MASK) >> XCVR_TSM_OVRD1_BBF_I_EN_OVRD_SHIFT)
36895 #define XCVR_BRD_TSM_OVRD1_BBF_I_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_BBF_I_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_BBF_I_EN_OVRD_WIDTH))
36896 
36897 /*! @brief Set the BBF_I_EN_OVRD field to a new value. */
36898 #define XCVR_WR_TSM_OVRD1_BBF_I_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_BBF_I_EN_OVRD_MASK, XCVR_TSM_OVRD1_BBF_I_EN_OVRD(value)))
36899 #define XCVR_BWR_TSM_OVRD1_BBF_I_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_BBF_I_EN_OVRD_SHIFT), XCVR_TSM_OVRD1_BBF_I_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_BBF_I_EN_OVRD_WIDTH))
36900 /*@}*/
36901 
36902 /*!
36903  * @name Register XCVR_TSM_OVRD1, field BBF_Q_EN_OVRD_EN[28] (RW)
36904  *
36905  * Values:
36906  * - 0b0 - Normal operation.
36907  * - 0b1 - Use the state of BBF_Q_EN_OVRD to override the signal "bbf_q_en".
36908  */
36909 /*@{*/
36910 /*! @brief Read current value of the XCVR_TSM_OVRD1_BBF_Q_EN_OVRD_EN field. */
36911 #define XCVR_RD_TSM_OVRD1_BBF_Q_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_BBF_Q_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD1_BBF_Q_EN_OVRD_EN_SHIFT)
36912 #define XCVR_BRD_TSM_OVRD1_BBF_Q_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_BBF_Q_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_BBF_Q_EN_OVRD_EN_WIDTH))
36913 
36914 /*! @brief Set the BBF_Q_EN_OVRD_EN field to a new value. */
36915 #define XCVR_WR_TSM_OVRD1_BBF_Q_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_BBF_Q_EN_OVRD_EN_MASK, XCVR_TSM_OVRD1_BBF_Q_EN_OVRD_EN(value)))
36916 #define XCVR_BWR_TSM_OVRD1_BBF_Q_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_BBF_Q_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD1_BBF_Q_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_BBF_Q_EN_OVRD_EN_WIDTH))
36917 /*@}*/
36918 
36919 /*!
36920  * @name Register XCVR_TSM_OVRD1, field BBF_Q_EN_OVRD[29] (RW)
36921  *
36922  * When BBF_Q_EN_OVRD_EN=1, this value overrides the mission mode state of the
36923  * signal "bbf_q_en". This bit is ignored when BBF_Q_EN_OVRD_EN==0.
36924  */
36925 /*@{*/
36926 /*! @brief Read current value of the XCVR_TSM_OVRD1_BBF_Q_EN_OVRD field. */
36927 #define XCVR_RD_TSM_OVRD1_BBF_Q_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_BBF_Q_EN_OVRD_MASK) >> XCVR_TSM_OVRD1_BBF_Q_EN_OVRD_SHIFT)
36928 #define XCVR_BRD_TSM_OVRD1_BBF_Q_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_BBF_Q_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_BBF_Q_EN_OVRD_WIDTH))
36929 
36930 /*! @brief Set the BBF_Q_EN_OVRD field to a new value. */
36931 #define XCVR_WR_TSM_OVRD1_BBF_Q_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_BBF_Q_EN_OVRD_MASK, XCVR_TSM_OVRD1_BBF_Q_EN_OVRD(value)))
36932 #define XCVR_BWR_TSM_OVRD1_BBF_Q_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_BBF_Q_EN_OVRD_SHIFT), XCVR_TSM_OVRD1_BBF_Q_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_BBF_Q_EN_OVRD_WIDTH))
36933 /*@}*/
36934 
36935 /*!
36936  * @name Register XCVR_TSM_OVRD1, field BBF_PDET_EN_OVRD_EN[30] (RW)
36937  *
36938  * Values:
36939  * - 0b0 - Normal operation.
36940  * - 0b1 - Use the state of BBF_PDET_EN_OVRD to override the signal
36941  *     "bbf_pdet_en".
36942  */
36943 /*@{*/
36944 /*! @brief Read current value of the XCVR_TSM_OVRD1_BBF_PDET_EN_OVRD_EN field. */
36945 #define XCVR_RD_TSM_OVRD1_BBF_PDET_EN_OVRD_EN(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_BBF_PDET_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD1_BBF_PDET_EN_OVRD_EN_SHIFT)
36946 #define XCVR_BRD_TSM_OVRD1_BBF_PDET_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_BBF_PDET_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_BBF_PDET_EN_OVRD_EN_WIDTH))
36947 
36948 /*! @brief Set the BBF_PDET_EN_OVRD_EN field to a new value. */
36949 #define XCVR_WR_TSM_OVRD1_BBF_PDET_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_BBF_PDET_EN_OVRD_EN_MASK, XCVR_TSM_OVRD1_BBF_PDET_EN_OVRD_EN(value)))
36950 #define XCVR_BWR_TSM_OVRD1_BBF_PDET_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_BBF_PDET_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD1_BBF_PDET_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD1_BBF_PDET_EN_OVRD_EN_WIDTH))
36951 /*@}*/
36952 
36953 /*!
36954  * @name Register XCVR_TSM_OVRD1, field BBF_PDET_EN_OVRD[31] (RW)
36955  *
36956  * When BBF_PDET_EN_OVRD_EN=1, this value overrides the mission mode state of
36957  * the signal "bbf_pdet_en". This bit is ignored when BBF_PDET_EN_OVRD_EN==0.
36958  */
36959 /*@{*/
36960 /*! @brief Read current value of the XCVR_TSM_OVRD1_BBF_PDET_EN_OVRD field. */
36961 #define XCVR_RD_TSM_OVRD1_BBF_PDET_EN_OVRD(base) ((XCVR_TSM_OVRD1_REG(base) & XCVR_TSM_OVRD1_BBF_PDET_EN_OVRD_MASK) >> XCVR_TSM_OVRD1_BBF_PDET_EN_OVRD_SHIFT)
36962 #define XCVR_BRD_TSM_OVRD1_BBF_PDET_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD1_REG(base), XCVR_TSM_OVRD1_BBF_PDET_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_BBF_PDET_EN_OVRD_WIDTH))
36963 
36964 /*! @brief Set the BBF_PDET_EN_OVRD field to a new value. */
36965 #define XCVR_WR_TSM_OVRD1_BBF_PDET_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD1(base, XCVR_TSM_OVRD1_BBF_PDET_EN_OVRD_MASK, XCVR_TSM_OVRD1_BBF_PDET_EN_OVRD(value)))
36966 #define XCVR_BWR_TSM_OVRD1_BBF_PDET_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD1_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD1_BBF_PDET_EN_OVRD_SHIFT), XCVR_TSM_OVRD1_BBF_PDET_EN_OVRD_SHIFT, XCVR_TSM_OVRD1_BBF_PDET_EN_OVRD_WIDTH))
36967 /*@}*/
36968 
36969 /*******************************************************************************
36970  * XCVR_TSM_OVRD2 - TSM Override 2
36971  ******************************************************************************/
36972 
36973 /*!
36974  * @brief XCVR_TSM_OVRD2 - TSM Override 2 (RW)
36975  *
36976  * Reset value: 0x00000000U
36977  */
36978 /*!
36979  * @name Constants and macros for entire XCVR_TSM_OVRD2 register
36980  */
36981 /*@{*/
36982 #define XCVR_RD_TSM_OVRD2(base)  (XCVR_TSM_OVRD2_REG(base))
36983 #define XCVR_WR_TSM_OVRD2(base, value) (XCVR_TSM_OVRD2_REG(base) = (value))
36984 #define XCVR_RMW_TSM_OVRD2(base, mask, value) (XCVR_WR_TSM_OVRD2(base, (XCVR_RD_TSM_OVRD2(base) & ~(mask)) | (value)))
36985 #define XCVR_SET_TSM_OVRD2(base, value) (BME_OR32(&XCVR_TSM_OVRD2_REG(base), (uint32_t)(value)))
36986 #define XCVR_CLR_TSM_OVRD2(base, value) (BME_AND32(&XCVR_TSM_OVRD2_REG(base), (uint32_t)(~(value))))
36987 #define XCVR_TOG_TSM_OVRD2(base, value) (BME_XOR32(&XCVR_TSM_OVRD2_REG(base), (uint32_t)(value)))
36988 /*@}*/
36989 
36990 /*
36991  * Constants & macros for individual XCVR_TSM_OVRD2 bitfields
36992  */
36993 
36994 /*!
36995  * @name Register XCVR_TSM_OVRD2, field BBF_DCOC_EN_OVRD_EN[0] (RW)
36996  *
36997  * Values:
36998  * - 0b0 - Normal operation.
36999  * - 0b1 - Use the state of BBF_DCOC_EN_OVRD to override the signal
37000  *     "bbf_dcoc_en".
37001  */
37002 /*@{*/
37003 /*! @brief Read current value of the XCVR_TSM_OVRD2_BBF_DCOC_EN_OVRD_EN field. */
37004 #define XCVR_RD_TSM_OVRD2_BBF_DCOC_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_BBF_DCOC_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD2_BBF_DCOC_EN_OVRD_EN_SHIFT)
37005 #define XCVR_BRD_TSM_OVRD2_BBF_DCOC_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_BBF_DCOC_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_BBF_DCOC_EN_OVRD_EN_WIDTH))
37006 
37007 /*! @brief Set the BBF_DCOC_EN_OVRD_EN field to a new value. */
37008 #define XCVR_WR_TSM_OVRD2_BBF_DCOC_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_BBF_DCOC_EN_OVRD_EN_MASK, XCVR_TSM_OVRD2_BBF_DCOC_EN_OVRD_EN(value)))
37009 #define XCVR_BWR_TSM_OVRD2_BBF_DCOC_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_BBF_DCOC_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD2_BBF_DCOC_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_BBF_DCOC_EN_OVRD_EN_WIDTH))
37010 /*@}*/
37011 
37012 /*!
37013  * @name Register XCVR_TSM_OVRD2, field BBF_DCOC_EN_OVRD[1] (RW)
37014  *
37015  * When BBF_DCOC_EN_OVRD_EN=1, this value overrides the mission mode state of
37016  * the signal "bbf_dcoc_en". This bit is ignored when BBF_DCOC_EN_OVRD_EN==0.
37017  */
37018 /*@{*/
37019 /*! @brief Read current value of the XCVR_TSM_OVRD2_BBF_DCOC_EN_OVRD field. */
37020 #define XCVR_RD_TSM_OVRD2_BBF_DCOC_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_BBF_DCOC_EN_OVRD_MASK) >> XCVR_TSM_OVRD2_BBF_DCOC_EN_OVRD_SHIFT)
37021 #define XCVR_BRD_TSM_OVRD2_BBF_DCOC_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_BBF_DCOC_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_BBF_DCOC_EN_OVRD_WIDTH))
37022 
37023 /*! @brief Set the BBF_DCOC_EN_OVRD field to a new value. */
37024 #define XCVR_WR_TSM_OVRD2_BBF_DCOC_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_BBF_DCOC_EN_OVRD_MASK, XCVR_TSM_OVRD2_BBF_DCOC_EN_OVRD(value)))
37025 #define XCVR_BWR_TSM_OVRD2_BBF_DCOC_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_BBF_DCOC_EN_OVRD_SHIFT), XCVR_TSM_OVRD2_BBF_DCOC_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_BBF_DCOC_EN_OVRD_WIDTH))
37026 /*@}*/
37027 
37028 /*!
37029  * @name Register XCVR_TSM_OVRD2, field TCA_EN_OVRD_EN[2] (RW)
37030  *
37031  * Values:
37032  * - 0b0 - Normal operation.
37033  * - 0b1 - Use the state of TCA_EN_OVRD to override the signal "tca_en".
37034  */
37035 /*@{*/
37036 /*! @brief Read current value of the XCVR_TSM_OVRD2_TCA_EN_OVRD_EN field. */
37037 #define XCVR_RD_TSM_OVRD2_TCA_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TCA_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD2_TCA_EN_OVRD_EN_SHIFT)
37038 #define XCVR_BRD_TSM_OVRD2_TCA_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_TCA_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_TCA_EN_OVRD_EN_WIDTH))
37039 
37040 /*! @brief Set the TCA_EN_OVRD_EN field to a new value. */
37041 #define XCVR_WR_TSM_OVRD2_TCA_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_TCA_EN_OVRD_EN_MASK, XCVR_TSM_OVRD2_TCA_EN_OVRD_EN(value)))
37042 #define XCVR_BWR_TSM_OVRD2_TCA_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_TCA_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD2_TCA_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_TCA_EN_OVRD_EN_WIDTH))
37043 /*@}*/
37044 
37045 /*!
37046  * @name Register XCVR_TSM_OVRD2, field TCA_EN_OVRD[3] (RW)
37047  *
37048  * When TCA_EN_OVRD_EN=1, this value overrides the mission mode state of the
37049  * signal "tca_en". This bit is ignored when TCA_EN_OVRD_EN==0.
37050  */
37051 /*@{*/
37052 /*! @brief Read current value of the XCVR_TSM_OVRD2_TCA_EN_OVRD field. */
37053 #define XCVR_RD_TSM_OVRD2_TCA_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TCA_EN_OVRD_MASK) >> XCVR_TSM_OVRD2_TCA_EN_OVRD_SHIFT)
37054 #define XCVR_BRD_TSM_OVRD2_TCA_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_TCA_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_TCA_EN_OVRD_WIDTH))
37055 
37056 /*! @brief Set the TCA_EN_OVRD field to a new value. */
37057 #define XCVR_WR_TSM_OVRD2_TCA_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_TCA_EN_OVRD_MASK, XCVR_TSM_OVRD2_TCA_EN_OVRD(value)))
37058 #define XCVR_BWR_TSM_OVRD2_TCA_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_TCA_EN_OVRD_SHIFT), XCVR_TSM_OVRD2_TCA_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_TCA_EN_OVRD_WIDTH))
37059 /*@}*/
37060 
37061 /*!
37062  * @name Register XCVR_TSM_OVRD2, field TZA_I_EN_OVRD_EN[4] (RW)
37063  *
37064  * Values:
37065  * - 0b0 - Normal operation.
37066  * - 0b1 - Use the state of TZA_I_EN_OVRD to override the signal "tza_i_en".
37067  */
37068 /*@{*/
37069 /*! @brief Read current value of the XCVR_TSM_OVRD2_TZA_I_EN_OVRD_EN field. */
37070 #define XCVR_RD_TSM_OVRD2_TZA_I_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TZA_I_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD2_TZA_I_EN_OVRD_EN_SHIFT)
37071 #define XCVR_BRD_TSM_OVRD2_TZA_I_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_TZA_I_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_TZA_I_EN_OVRD_EN_WIDTH))
37072 
37073 /*! @brief Set the TZA_I_EN_OVRD_EN field to a new value. */
37074 #define XCVR_WR_TSM_OVRD2_TZA_I_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_TZA_I_EN_OVRD_EN_MASK, XCVR_TSM_OVRD2_TZA_I_EN_OVRD_EN(value)))
37075 #define XCVR_BWR_TSM_OVRD2_TZA_I_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_TZA_I_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD2_TZA_I_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_TZA_I_EN_OVRD_EN_WIDTH))
37076 /*@}*/
37077 
37078 /*!
37079  * @name Register XCVR_TSM_OVRD2, field TZA_I_EN_OVRD[5] (RW)
37080  *
37081  * When TZA_I_EN_OVRD_EN=1, this value overrides the mission mode state of the
37082  * signal "tza_i_en". This bit is ignored when TZA_I_EN_OVRD_EN==0.
37083  */
37084 /*@{*/
37085 /*! @brief Read current value of the XCVR_TSM_OVRD2_TZA_I_EN_OVRD field. */
37086 #define XCVR_RD_TSM_OVRD2_TZA_I_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TZA_I_EN_OVRD_MASK) >> XCVR_TSM_OVRD2_TZA_I_EN_OVRD_SHIFT)
37087 #define XCVR_BRD_TSM_OVRD2_TZA_I_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_TZA_I_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_TZA_I_EN_OVRD_WIDTH))
37088 
37089 /*! @brief Set the TZA_I_EN_OVRD field to a new value. */
37090 #define XCVR_WR_TSM_OVRD2_TZA_I_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_TZA_I_EN_OVRD_MASK, XCVR_TSM_OVRD2_TZA_I_EN_OVRD(value)))
37091 #define XCVR_BWR_TSM_OVRD2_TZA_I_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_TZA_I_EN_OVRD_SHIFT), XCVR_TSM_OVRD2_TZA_I_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_TZA_I_EN_OVRD_WIDTH))
37092 /*@}*/
37093 
37094 /*!
37095  * @name Register XCVR_TSM_OVRD2, field TZA_Q_EN_OVRD_EN[6] (RW)
37096  *
37097  * Values:
37098  * - 0b0 - Normal operation.
37099  * - 0b1 - Use the state of TZA_Q_EN_OVRD to override the signal "tza_q_en".
37100  */
37101 /*@{*/
37102 /*! @brief Read current value of the XCVR_TSM_OVRD2_TZA_Q_EN_OVRD_EN field. */
37103 #define XCVR_RD_TSM_OVRD2_TZA_Q_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TZA_Q_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD2_TZA_Q_EN_OVRD_EN_SHIFT)
37104 #define XCVR_BRD_TSM_OVRD2_TZA_Q_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_TZA_Q_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_TZA_Q_EN_OVRD_EN_WIDTH))
37105 
37106 /*! @brief Set the TZA_Q_EN_OVRD_EN field to a new value. */
37107 #define XCVR_WR_TSM_OVRD2_TZA_Q_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_TZA_Q_EN_OVRD_EN_MASK, XCVR_TSM_OVRD2_TZA_Q_EN_OVRD_EN(value)))
37108 #define XCVR_BWR_TSM_OVRD2_TZA_Q_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_TZA_Q_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD2_TZA_Q_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_TZA_Q_EN_OVRD_EN_WIDTH))
37109 /*@}*/
37110 
37111 /*!
37112  * @name Register XCVR_TSM_OVRD2, field TZA_Q_EN_OVRD[7] (RW)
37113  *
37114  * When TZA_Q_EN_OVRD_EN=1, this value overrides the mission mode state of the
37115  * signal "tza_q_en". This bit is ignored when TZA_Q_EN_OVRD_EN==0.
37116  */
37117 /*@{*/
37118 /*! @brief Read current value of the XCVR_TSM_OVRD2_TZA_Q_EN_OVRD field. */
37119 #define XCVR_RD_TSM_OVRD2_TZA_Q_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TZA_Q_EN_OVRD_MASK) >> XCVR_TSM_OVRD2_TZA_Q_EN_OVRD_SHIFT)
37120 #define XCVR_BRD_TSM_OVRD2_TZA_Q_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_TZA_Q_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_TZA_Q_EN_OVRD_WIDTH))
37121 
37122 /*! @brief Set the TZA_Q_EN_OVRD field to a new value. */
37123 #define XCVR_WR_TSM_OVRD2_TZA_Q_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_TZA_Q_EN_OVRD_MASK, XCVR_TSM_OVRD2_TZA_Q_EN_OVRD(value)))
37124 #define XCVR_BWR_TSM_OVRD2_TZA_Q_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_TZA_Q_EN_OVRD_SHIFT), XCVR_TSM_OVRD2_TZA_Q_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_TZA_Q_EN_OVRD_WIDTH))
37125 /*@}*/
37126 
37127 /*!
37128  * @name Register XCVR_TSM_OVRD2, field TZA_PDET_EN_OVRD_EN[8] (RW)
37129  *
37130  * Values:
37131  * - 0b0 - Normal operation.
37132  * - 0b1 - Use the state of TZA_PDET_EN_OVRD to override the signal
37133  *     "tza_pdet_en".
37134  */
37135 /*@{*/
37136 /*! @brief Read current value of the XCVR_TSM_OVRD2_TZA_PDET_EN_OVRD_EN field. */
37137 #define XCVR_RD_TSM_OVRD2_TZA_PDET_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TZA_PDET_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD2_TZA_PDET_EN_OVRD_EN_SHIFT)
37138 #define XCVR_BRD_TSM_OVRD2_TZA_PDET_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_TZA_PDET_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_TZA_PDET_EN_OVRD_EN_WIDTH))
37139 
37140 /*! @brief Set the TZA_PDET_EN_OVRD_EN field to a new value. */
37141 #define XCVR_WR_TSM_OVRD2_TZA_PDET_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_TZA_PDET_EN_OVRD_EN_MASK, XCVR_TSM_OVRD2_TZA_PDET_EN_OVRD_EN(value)))
37142 #define XCVR_BWR_TSM_OVRD2_TZA_PDET_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_TZA_PDET_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD2_TZA_PDET_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_TZA_PDET_EN_OVRD_EN_WIDTH))
37143 /*@}*/
37144 
37145 /*!
37146  * @name Register XCVR_TSM_OVRD2, field TZA_PDET_EN_OVRD[9] (RW)
37147  *
37148  * When TZA_PDET_EN_OVRD_EN=1, this value overrides the mission mode state of
37149  * the signal "tza_pdet_en". This bit is ignored when TZA_PDET_EN_OVRD_EN==0.
37150  */
37151 /*@{*/
37152 /*! @brief Read current value of the XCVR_TSM_OVRD2_TZA_PDET_EN_OVRD field. */
37153 #define XCVR_RD_TSM_OVRD2_TZA_PDET_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TZA_PDET_EN_OVRD_MASK) >> XCVR_TSM_OVRD2_TZA_PDET_EN_OVRD_SHIFT)
37154 #define XCVR_BRD_TSM_OVRD2_TZA_PDET_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_TZA_PDET_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_TZA_PDET_EN_OVRD_WIDTH))
37155 
37156 /*! @brief Set the TZA_PDET_EN_OVRD field to a new value. */
37157 #define XCVR_WR_TSM_OVRD2_TZA_PDET_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_TZA_PDET_EN_OVRD_MASK, XCVR_TSM_OVRD2_TZA_PDET_EN_OVRD(value)))
37158 #define XCVR_BWR_TSM_OVRD2_TZA_PDET_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_TZA_PDET_EN_OVRD_SHIFT), XCVR_TSM_OVRD2_TZA_PDET_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_TZA_PDET_EN_OVRD_WIDTH))
37159 /*@}*/
37160 
37161 /*!
37162  * @name Register XCVR_TSM_OVRD2, field TZA_DCOC_EN_OVRD_EN[10] (RW)
37163  *
37164  * Values:
37165  * - 0b0 - Normal operation.
37166  * - 0b1 - Use the state of TZA_DCOC_EN_OVRD to override the signal
37167  *     "tza_dcoc_en".
37168  */
37169 /*@{*/
37170 /*! @brief Read current value of the XCVR_TSM_OVRD2_TZA_DCOC_EN_OVRD_EN field. */
37171 #define XCVR_RD_TSM_OVRD2_TZA_DCOC_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TZA_DCOC_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD2_TZA_DCOC_EN_OVRD_EN_SHIFT)
37172 #define XCVR_BRD_TSM_OVRD2_TZA_DCOC_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_TZA_DCOC_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_TZA_DCOC_EN_OVRD_EN_WIDTH))
37173 
37174 /*! @brief Set the TZA_DCOC_EN_OVRD_EN field to a new value. */
37175 #define XCVR_WR_TSM_OVRD2_TZA_DCOC_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_TZA_DCOC_EN_OVRD_EN_MASK, XCVR_TSM_OVRD2_TZA_DCOC_EN_OVRD_EN(value)))
37176 #define XCVR_BWR_TSM_OVRD2_TZA_DCOC_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_TZA_DCOC_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD2_TZA_DCOC_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_TZA_DCOC_EN_OVRD_EN_WIDTH))
37177 /*@}*/
37178 
37179 /*!
37180  * @name Register XCVR_TSM_OVRD2, field TZA_DCOC_EN_OVRD[11] (RW)
37181  *
37182  * When TZA_DCOC_EN_OVRD_EN=1, this value overrides the mission mode state of
37183  * the signal "tza_dcoc_en". This bit is ignored when TZA_DCOC_EN_OVRD_EN==0.
37184  */
37185 /*@{*/
37186 /*! @brief Read current value of the XCVR_TSM_OVRD2_TZA_DCOC_EN_OVRD field. */
37187 #define XCVR_RD_TSM_OVRD2_TZA_DCOC_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TZA_DCOC_EN_OVRD_MASK) >> XCVR_TSM_OVRD2_TZA_DCOC_EN_OVRD_SHIFT)
37188 #define XCVR_BRD_TSM_OVRD2_TZA_DCOC_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_TZA_DCOC_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_TZA_DCOC_EN_OVRD_WIDTH))
37189 
37190 /*! @brief Set the TZA_DCOC_EN_OVRD field to a new value. */
37191 #define XCVR_WR_TSM_OVRD2_TZA_DCOC_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_TZA_DCOC_EN_OVRD_MASK, XCVR_TSM_OVRD2_TZA_DCOC_EN_OVRD(value)))
37192 #define XCVR_BWR_TSM_OVRD2_TZA_DCOC_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_TZA_DCOC_EN_OVRD_SHIFT), XCVR_TSM_OVRD2_TZA_DCOC_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_TZA_DCOC_EN_OVRD_WIDTH))
37193 /*@}*/
37194 
37195 /*!
37196  * @name Register XCVR_TSM_OVRD2, field PLL_DIG_EN_OVRD_EN[12] (RW)
37197  *
37198  * Values:
37199  * - 0b0 - Normal operation.
37200  * - 0b1 - Use the state of PLL_DIG_EN_OVRD to override the signal "pll_dig_en".
37201  */
37202 /*@{*/
37203 /*! @brief Read current value of the XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN field. */
37204 #define XCVR_RD_TSM_OVRD2_PLL_DIG_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_SHIFT)
37205 #define XCVR_BRD_TSM_OVRD2_PLL_DIG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_WIDTH))
37206 
37207 /*! @brief Set the PLL_DIG_EN_OVRD_EN field to a new value. */
37208 #define XCVR_WR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_MASK, XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN(value)))
37209 #define XCVR_BWR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_EN_WIDTH))
37210 /*@}*/
37211 
37212 /*!
37213  * @name Register XCVR_TSM_OVRD2, field PLL_DIG_EN_OVRD[13] (RW)
37214  *
37215  * When PLL_DIG_EN_OVRD_EN=1, this value overrides the mission mode state of the
37216  * signal "pll_dig_en". This bit is ignored when PLL_DIG_EN_OVRD_EN==0.
37217  */
37218 /*@{*/
37219 /*! @brief Read current value of the XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD field. */
37220 #define XCVR_RD_TSM_OVRD2_PLL_DIG_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_MASK) >> XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_SHIFT)
37221 #define XCVR_BRD_TSM_OVRD2_PLL_DIG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_WIDTH))
37222 
37223 /*! @brief Set the PLL_DIG_EN_OVRD field to a new value. */
37224 #define XCVR_WR_TSM_OVRD2_PLL_DIG_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_MASK, XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD(value)))
37225 #define XCVR_BWR_TSM_OVRD2_PLL_DIG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_SHIFT), XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_PLL_DIG_EN_OVRD_WIDTH))
37226 /*@}*/
37227 
37228 /*!
37229  * @name Register XCVR_TSM_OVRD2, field TX_DIG_EN_OVRD_EN[14] (RW)
37230  *
37231  * Values:
37232  * - 0b0 - Normal operation.
37233  * - 0b1 - Use the state of TX_DIG_EN_OVRD to override the signal "tx_dig_en".
37234  */
37235 /*@{*/
37236 /*! @brief Read current value of the XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN field. */
37237 #define XCVR_RD_TSM_OVRD2_TX_DIG_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_SHIFT)
37238 #define XCVR_BRD_TSM_OVRD2_TX_DIG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_WIDTH))
37239 
37240 /*! @brief Set the TX_DIG_EN_OVRD_EN field to a new value. */
37241 #define XCVR_WR_TSM_OVRD2_TX_DIG_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_MASK, XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN(value)))
37242 #define XCVR_BWR_TSM_OVRD2_TX_DIG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_EN_WIDTH))
37243 /*@}*/
37244 
37245 /*!
37246  * @name Register XCVR_TSM_OVRD2, field TX_DIG_EN_OVRD[15] (RW)
37247  *
37248  * When TX_DIG_EN_OVRD_EN=1, this value overrides the mission mode state of the
37249  * signal "tx_dig_en". This bit is ignored when TX_DIG_EN_OVRD_EN==0.
37250  */
37251 /*@{*/
37252 /*! @brief Read current value of the XCVR_TSM_OVRD2_TX_DIG_EN_OVRD field. */
37253 #define XCVR_RD_TSM_OVRD2_TX_DIG_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_MASK) >> XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_SHIFT)
37254 #define XCVR_BRD_TSM_OVRD2_TX_DIG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_WIDTH))
37255 
37256 /*! @brief Set the TX_DIG_EN_OVRD field to a new value. */
37257 #define XCVR_WR_TSM_OVRD2_TX_DIG_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_MASK, XCVR_TSM_OVRD2_TX_DIG_EN_OVRD(value)))
37258 #define XCVR_BWR_TSM_OVRD2_TX_DIG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_SHIFT), XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_TX_DIG_EN_OVRD_WIDTH))
37259 /*@}*/
37260 
37261 /*!
37262  * @name Register XCVR_TSM_OVRD2, field RX_DIG_EN_OVRD_EN[16] (RW)
37263  *
37264  * Values:
37265  * - 0b0 - Normal operation.
37266  * - 0b1 - Use the state of RX_DIG_EN_OVRD to override the signal "rx_dig_en".
37267  */
37268 /*@{*/
37269 /*! @brief Read current value of the XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN field. */
37270 #define XCVR_RD_TSM_OVRD2_RX_DIG_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_SHIFT)
37271 #define XCVR_BRD_TSM_OVRD2_RX_DIG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_WIDTH))
37272 
37273 /*! @brief Set the RX_DIG_EN_OVRD_EN field to a new value. */
37274 #define XCVR_WR_TSM_OVRD2_RX_DIG_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_MASK, XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN(value)))
37275 #define XCVR_BWR_TSM_OVRD2_RX_DIG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_EN_WIDTH))
37276 /*@}*/
37277 
37278 /*!
37279  * @name Register XCVR_TSM_OVRD2, field RX_DIG_EN_OVRD[17] (RW)
37280  *
37281  * When RX_DIG_EN_OVRD_EN=1, this value overrides the mission mode state of the
37282  * signal "rx_dig_en". This bit is ignored when RX_DIG_EN_OVRD_EN==0.
37283  */
37284 /*@{*/
37285 /*! @brief Read current value of the XCVR_TSM_OVRD2_RX_DIG_EN_OVRD field. */
37286 #define XCVR_RD_TSM_OVRD2_RX_DIG_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_MASK) >> XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_SHIFT)
37287 #define XCVR_BRD_TSM_OVRD2_RX_DIG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_WIDTH))
37288 
37289 /*! @brief Set the RX_DIG_EN_OVRD field to a new value. */
37290 #define XCVR_WR_TSM_OVRD2_RX_DIG_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_MASK, XCVR_TSM_OVRD2_RX_DIG_EN_OVRD(value)))
37291 #define XCVR_BWR_TSM_OVRD2_RX_DIG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_SHIFT), XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_RX_DIG_EN_OVRD_WIDTH))
37292 /*@}*/
37293 
37294 /*!
37295  * @name Register XCVR_TSM_OVRD2, field RX_INIT_OVRD_EN[18] (RW)
37296  *
37297  * Values:
37298  * - 0b0 - Normal operation.
37299  * - 0b1 - Use the state of RX_INIT_OVRD to override the signal "rx_init".
37300  */
37301 /*@{*/
37302 /*! @brief Read current value of the XCVR_TSM_OVRD2_RX_INIT_OVRD_EN field. */
37303 #define XCVR_RD_TSM_OVRD2_RX_INIT_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_MASK) >> XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_SHIFT)
37304 #define XCVR_BRD_TSM_OVRD2_RX_INIT_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_WIDTH))
37305 
37306 /*! @brief Set the RX_INIT_OVRD_EN field to a new value. */
37307 #define XCVR_WR_TSM_OVRD2_RX_INIT_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_MASK, XCVR_TSM_OVRD2_RX_INIT_OVRD_EN(value)))
37308 #define XCVR_BWR_TSM_OVRD2_RX_INIT_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_SHIFT), XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_RX_INIT_OVRD_EN_WIDTH))
37309 /*@}*/
37310 
37311 /*!
37312  * @name Register XCVR_TSM_OVRD2, field RX_INIT_OVRD[19] (RW)
37313  *
37314  * When RX_INIT_OVRD_EN=1, this value overrides the mission mode state of the
37315  * signal "rx_init". This bit is ignored when RX_INIT_OVRD_EN==0.
37316  */
37317 /*@{*/
37318 /*! @brief Read current value of the XCVR_TSM_OVRD2_RX_INIT_OVRD field. */
37319 #define XCVR_RD_TSM_OVRD2_RX_INIT_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_RX_INIT_OVRD_MASK) >> XCVR_TSM_OVRD2_RX_INIT_OVRD_SHIFT)
37320 #define XCVR_BRD_TSM_OVRD2_RX_INIT_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_RX_INIT_OVRD_SHIFT, XCVR_TSM_OVRD2_RX_INIT_OVRD_WIDTH))
37321 
37322 /*! @brief Set the RX_INIT_OVRD field to a new value. */
37323 #define XCVR_WR_TSM_OVRD2_RX_INIT_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_RX_INIT_OVRD_MASK, XCVR_TSM_OVRD2_RX_INIT_OVRD(value)))
37324 #define XCVR_BWR_TSM_OVRD2_RX_INIT_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_RX_INIT_OVRD_SHIFT), XCVR_TSM_OVRD2_RX_INIT_OVRD_SHIFT, XCVR_TSM_OVRD2_RX_INIT_OVRD_WIDTH))
37325 /*@}*/
37326 
37327 /*!
37328  * @name Register XCVR_TSM_OVRD2, field SIGMA_DELTA_EN_OVRD_EN[20] (RW)
37329  *
37330  * Values:
37331  * - 0b0 - Normal operation.
37332  * - 0b1 - Use the state of SIGMA_DELTA_EN_OVRD to override the signal
37333  *     "sigma_delta_en".
37334  */
37335 /*@{*/
37336 /*! @brief Read current value of the XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN field. */
37337 #define XCVR_RD_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_SHIFT)
37338 #define XCVR_BRD_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_WIDTH))
37339 
37340 /*! @brief Set the SIGMA_DELTA_EN_OVRD_EN field to a new value. */
37341 #define XCVR_WR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_MASK, XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN(value)))
37342 #define XCVR_BWR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_EN_WIDTH))
37343 /*@}*/
37344 
37345 /*!
37346  * @name Register XCVR_TSM_OVRD2, field SIGMA_DELTA_EN_OVRD[21] (RW)
37347  *
37348  * When SIGMA_DELTA_EN_OVRD_EN=1, this value overrides the mission mode state of
37349  * the signal "sigma_delta_en". This bit is ignored when
37350  * SIGMA_DELTA_EN_OVRD_EN==0.
37351  */
37352 /*@{*/
37353 /*! @brief Read current value of the XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD field. */
37354 #define XCVR_RD_TSM_OVRD2_SIGMA_DELTA_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_MASK) >> XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_SHIFT)
37355 #define XCVR_BRD_TSM_OVRD2_SIGMA_DELTA_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_WIDTH))
37356 
37357 /*! @brief Set the SIGMA_DELTA_EN_OVRD field to a new value. */
37358 #define XCVR_WR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_MASK, XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD(value)))
37359 #define XCVR_BWR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_SHIFT), XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_SIGMA_DELTA_EN_OVRD_WIDTH))
37360 /*@}*/
37361 
37362 /*!
37363  * @name Register XCVR_TSM_OVRD2, field ZBDEM_RX_EN_OVRD_EN[22] (RW)
37364  *
37365  * Values:
37366  * - 0b0 - Normal operation.
37367  * - 0b1 - Use the state of ZBDEM_RX_EN_OVRD to override the signal
37368  *     "zbdem_rx_en".
37369  */
37370 /*@{*/
37371 /*! @brief Read current value of the XCVR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_EN field. */
37372 #define XCVR_RD_TSM_OVRD2_ZBDEM_RX_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_EN_SHIFT)
37373 #define XCVR_BRD_TSM_OVRD2_ZBDEM_RX_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_EN_WIDTH))
37374 
37375 /*! @brief Set the ZBDEM_RX_EN_OVRD_EN field to a new value. */
37376 #define XCVR_WR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_EN_MASK, XCVR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_EN(value)))
37377 #define XCVR_BWR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_EN_WIDTH))
37378 /*@}*/
37379 
37380 /*!
37381  * @name Register XCVR_TSM_OVRD2, field ZBDEM_RX_EN_OVRD[23] (RW)
37382  *
37383  * When ZBDEM_RX_EN_OVRD_EN=1, this value overrides the mission mode state of
37384  * the signal "zbdem_rx_en". This bit is ignored when ZBDEM_RX_EN_OVRD_EN==0.
37385  */
37386 /*@{*/
37387 /*! @brief Read current value of the XCVR_TSM_OVRD2_ZBDEM_RX_EN_OVRD field. */
37388 #define XCVR_RD_TSM_OVRD2_ZBDEM_RX_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_MASK) >> XCVR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_SHIFT)
37389 #define XCVR_BRD_TSM_OVRD2_ZBDEM_RX_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_WIDTH))
37390 
37391 /*! @brief Set the ZBDEM_RX_EN_OVRD field to a new value. */
37392 #define XCVR_WR_TSM_OVRD2_ZBDEM_RX_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_MASK, XCVR_TSM_OVRD2_ZBDEM_RX_EN_OVRD(value)))
37393 #define XCVR_BWR_TSM_OVRD2_ZBDEM_RX_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_SHIFT), XCVR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_ZBDEM_RX_EN_OVRD_WIDTH))
37394 /*@}*/
37395 
37396 /*!
37397  * @name Register XCVR_TSM_OVRD2, field DCOC_EN_OVRD_EN[24] (RW)
37398  *
37399  * Values:
37400  * - 0b0 - Normal operation.
37401  * - 0b1 - Use the state of DCOC_EN_OVRD to override the signal "dcoc_en".
37402  */
37403 /*@{*/
37404 /*! @brief Read current value of the XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN field. */
37405 #define XCVR_RD_TSM_OVRD2_DCOC_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_SHIFT)
37406 #define XCVR_BRD_TSM_OVRD2_DCOC_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_WIDTH))
37407 
37408 /*! @brief Set the DCOC_EN_OVRD_EN field to a new value. */
37409 #define XCVR_WR_TSM_OVRD2_DCOC_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_MASK, XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN(value)))
37410 #define XCVR_BWR_TSM_OVRD2_DCOC_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_DCOC_EN_OVRD_EN_WIDTH))
37411 /*@}*/
37412 
37413 /*!
37414  * @name Register XCVR_TSM_OVRD2, field DCOC_EN_OVRD[25] (RW)
37415  *
37416  * When DCOC_EN_OVRD_EN=1, this value overrides the mission mode state of the
37417  * signal "dcoc_en". This bit is ignored when DCOC_EN_OVRD_EN==0.
37418  */
37419 /*@{*/
37420 /*! @brief Read current value of the XCVR_TSM_OVRD2_DCOC_EN_OVRD field. */
37421 #define XCVR_RD_TSM_OVRD2_DCOC_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_DCOC_EN_OVRD_MASK) >> XCVR_TSM_OVRD2_DCOC_EN_OVRD_SHIFT)
37422 #define XCVR_BRD_TSM_OVRD2_DCOC_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_DCOC_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_DCOC_EN_OVRD_WIDTH))
37423 
37424 /*! @brief Set the DCOC_EN_OVRD field to a new value. */
37425 #define XCVR_WR_TSM_OVRD2_DCOC_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_DCOC_EN_OVRD_MASK, XCVR_TSM_OVRD2_DCOC_EN_OVRD(value)))
37426 #define XCVR_BWR_TSM_OVRD2_DCOC_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_DCOC_EN_OVRD_SHIFT), XCVR_TSM_OVRD2_DCOC_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_DCOC_EN_OVRD_WIDTH))
37427 /*@}*/
37428 
37429 /*!
37430  * @name Register XCVR_TSM_OVRD2, field DCOC_INIT_OVRD_EN[26] (RW)
37431  *
37432  * Values:
37433  * - 0b0 - Normal operation.
37434  * - 0b1 - Use the state of DCOC_INIT_OVRD to override the signal "dcoc_init".
37435  */
37436 /*@{*/
37437 /*! @brief Read current value of the XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN field. */
37438 #define XCVR_RD_TSM_OVRD2_DCOC_INIT_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_MASK) >> XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_SHIFT)
37439 #define XCVR_BRD_TSM_OVRD2_DCOC_INIT_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_WIDTH))
37440 
37441 /*! @brief Set the DCOC_INIT_OVRD_EN field to a new value. */
37442 #define XCVR_WR_TSM_OVRD2_DCOC_INIT_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_MASK, XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN(value)))
37443 #define XCVR_BWR_TSM_OVRD2_DCOC_INIT_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_SHIFT), XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_DCOC_INIT_OVRD_EN_WIDTH))
37444 /*@}*/
37445 
37446 /*!
37447  * @name Register XCVR_TSM_OVRD2, field DCOC_INIT_OVRD[27] (RW)
37448  *
37449  * When DCOC_INIT_OVRD_EN=1, this value overrides the mission mode state of the
37450  * signal "dcoc_init". This bit is ignored when DCOC_INIT_OVRD_EN==0.
37451  */
37452 /*@{*/
37453 /*! @brief Read current value of the XCVR_TSM_OVRD2_DCOC_INIT_OVRD field. */
37454 #define XCVR_RD_TSM_OVRD2_DCOC_INIT_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_DCOC_INIT_OVRD_MASK) >> XCVR_TSM_OVRD2_DCOC_INIT_OVRD_SHIFT)
37455 #define XCVR_BRD_TSM_OVRD2_DCOC_INIT_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_DCOC_INIT_OVRD_SHIFT, XCVR_TSM_OVRD2_DCOC_INIT_OVRD_WIDTH))
37456 
37457 /*! @brief Set the DCOC_INIT_OVRD field to a new value. */
37458 #define XCVR_WR_TSM_OVRD2_DCOC_INIT_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_DCOC_INIT_OVRD_MASK, XCVR_TSM_OVRD2_DCOC_INIT_OVRD(value)))
37459 #define XCVR_BWR_TSM_OVRD2_DCOC_INIT_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_DCOC_INIT_OVRD_SHIFT), XCVR_TSM_OVRD2_DCOC_INIT_OVRD_SHIFT, XCVR_TSM_OVRD2_DCOC_INIT_OVRD_WIDTH))
37460 /*@}*/
37461 
37462 /*!
37463  * @name Register XCVR_TSM_OVRD2, field FREQ_TARG_LD_EN_OVRD_EN[28] (RW)
37464  *
37465  * Values:
37466  * - 0b0 - Normal operation.
37467  * - 0b1 - Use the state of FREQ_TARG_LD_EN_OVRD to override the signal
37468  *     "freq_targ_ld_en".
37469  */
37470 /*@{*/
37471 /*! @brief Read current value of the XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN field. */
37472 #define XCVR_RD_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_SHIFT)
37473 #define XCVR_BRD_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_WIDTH))
37474 
37475 /*! @brief Set the FREQ_TARG_LD_EN_OVRD_EN field to a new value. */
37476 #define XCVR_WR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_MASK, XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN(value)))
37477 #define XCVR_BWR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_EN_WIDTH))
37478 /*@}*/
37479 
37480 /*!
37481  * @name Register XCVR_TSM_OVRD2, field FREQ_TARG_LD_EN_OVRD[29] (RW)
37482  *
37483  * When FREQ_TARG_LD_EN_OVRD_EN=1, this value overrides the mission mode state
37484  * of the signal "freq_targ_ld_en". This bit is ignored when
37485  * FREQ_TARG_LD_EN_OVRD_EN==0.
37486  */
37487 /*@{*/
37488 /*! @brief Read current value of the XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD field. */
37489 #define XCVR_RD_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_MASK) >> XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_SHIFT)
37490 #define XCVR_BRD_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_WIDTH))
37491 
37492 /*! @brief Set the FREQ_TARG_LD_EN_OVRD field to a new value. */
37493 #define XCVR_WR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_MASK, XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(value)))
37494 #define XCVR_BWR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_SHIFT), XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_FREQ_TARG_LD_EN_OVRD_WIDTH))
37495 /*@}*/
37496 
37497 /*!
37498  * @name Register XCVR_TSM_OVRD2, field SAR_ADC_TRIG_EN_OVRD_EN[30] (RW)
37499  *
37500  * Values:
37501  * - 0b0 - Normal operation.
37502  * - 0b1 - Use the state of SAR_ADC_TRIG_EN_OVRD to override the signal
37503  *     "sar_adc_trig_en".
37504  */
37505 /*@{*/
37506 /*! @brief Read current value of the XCVR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_EN field. */
37507 #define XCVR_RD_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_EN(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_EN_SHIFT)
37508 #define XCVR_BRD_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_EN_WIDTH))
37509 
37510 /*! @brief Set the SAR_ADC_TRIG_EN_OVRD_EN field to a new value. */
37511 #define XCVR_WR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_EN_MASK, XCVR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_EN(value)))
37512 #define XCVR_BWR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_EN_WIDTH))
37513 /*@}*/
37514 
37515 /*!
37516  * @name Register XCVR_TSM_OVRD2, field SAR_ADC_TRIG_EN_OVRD[31] (RW)
37517  *
37518  * When SAR_ADC_TRIG_EN_OVRD_EN=1, this value overrides the mission mode state
37519  * of the signal "sar_adc_trig_en". This bit is ignored when
37520  * SAR_ADC_TRIG_EN_OVRD_EN==0.
37521  */
37522 /*@{*/
37523 /*! @brief Read current value of the XCVR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD field. */
37524 #define XCVR_RD_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD(base) ((XCVR_TSM_OVRD2_REG(base) & XCVR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_MASK) >> XCVR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_SHIFT)
37525 #define XCVR_BRD_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD2_REG(base), XCVR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_WIDTH))
37526 
37527 /*! @brief Set the SAR_ADC_TRIG_EN_OVRD field to a new value. */
37528 #define XCVR_WR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD2(base, XCVR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_MASK, XCVR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD(value)))
37529 #define XCVR_BWR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD2_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_SHIFT), XCVR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_SHIFT, XCVR_TSM_OVRD2_SAR_ADC_TRIG_EN_OVRD_WIDTH))
37530 /*@}*/
37531 
37532 /*******************************************************************************
37533  * XCVR_TSM_OVRD3 - TSM Override 3
37534  ******************************************************************************/
37535 
37536 /*!
37537  * @brief XCVR_TSM_OVRD3 - TSM Override 3 (RW)
37538  *
37539  * Reset value: 0x00000000U
37540  */
37541 /*!
37542  * @name Constants and macros for entire XCVR_TSM_OVRD3 register
37543  */
37544 /*@{*/
37545 #define XCVR_RD_TSM_OVRD3(base)  (XCVR_TSM_OVRD3_REG(base))
37546 #define XCVR_WR_TSM_OVRD3(base, value) (XCVR_TSM_OVRD3_REG(base) = (value))
37547 #define XCVR_RMW_TSM_OVRD3(base, mask, value) (XCVR_WR_TSM_OVRD3(base, (XCVR_RD_TSM_OVRD3(base) & ~(mask)) | (value)))
37548 #define XCVR_SET_TSM_OVRD3(base, value) (BME_OR32(&XCVR_TSM_OVRD3_REG(base), (uint32_t)(value)))
37549 #define XCVR_CLR_TSM_OVRD3(base, value) (BME_AND32(&XCVR_TSM_OVRD3_REG(base), (uint32_t)(~(value))))
37550 #define XCVR_TOG_TSM_OVRD3(base, value) (BME_XOR32(&XCVR_TSM_OVRD3_REG(base), (uint32_t)(value)))
37551 /*@}*/
37552 
37553 /*
37554  * Constants & macros for individual XCVR_TSM_OVRD3 bitfields
37555  */
37556 
37557 /*!
37558  * @name Register XCVR_TSM_OVRD3, field TSM_SPARE0_EN_OVRD_EN[0] (RW)
37559  *
37560  * Values:
37561  * - 0b0 - Normal operation.
37562  * - 0b1 - Use the state of TSM_SPARE0_EN_OVRD to override the signal
37563  *     "tsm_spare0_en".
37564  */
37565 /*@{*/
37566 /*! @brief Read current value of the XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN field. */
37567 #define XCVR_RD_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_SHIFT)
37568 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_WIDTH))
37569 
37570 /*! @brief Set the TSM_SPARE0_EN_OVRD_EN field to a new value. */
37571 #define XCVR_WR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_MASK, XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN(value)))
37572 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_EN_WIDTH))
37573 /*@}*/
37574 
37575 /*!
37576  * @name Register XCVR_TSM_OVRD3, field TSM_SPARE0_EN_OVRD[1] (RW)
37577  *
37578  * When TSM_SPARE0_EN_OVRD_EN=1, this value overrides the mission mode state of
37579  * the signal "tsm_spare0_en". This bit is ignored when TSM_SPARE0_EN_OVRD_EN==0.
37580  */
37581 /*@{*/
37582 /*! @brief Read current value of the XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD field. */
37583 #define XCVR_RD_TSM_OVRD3_TSM_SPARE0_EN_OVRD(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_MASK) >> XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_SHIFT)
37584 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE0_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_SHIFT, XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_WIDTH))
37585 
37586 /*! @brief Set the TSM_SPARE0_EN_OVRD field to a new value. */
37587 #define XCVR_WR_TSM_OVRD3_TSM_SPARE0_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_MASK, XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD(value)))
37588 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE0_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_SHIFT), XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_SHIFT, XCVR_TSM_OVRD3_TSM_SPARE0_EN_OVRD_WIDTH))
37589 /*@}*/
37590 
37591 /*!
37592  * @name Register XCVR_TSM_OVRD3, field TSM_SPARE1_EN_OVRD_EN[2] (RW)
37593  *
37594  * Values:
37595  * - 0b0 - Normal operation.
37596  * - 0b1 - Use the state of TSM_SPARE1_EN_OVRD to override the signal
37597  *     "tsm_spare1_en".
37598  */
37599 /*@{*/
37600 /*! @brief Read current value of the XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN field. */
37601 #define XCVR_RD_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_SHIFT)
37602 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_WIDTH))
37603 
37604 /*! @brief Set the TSM_SPARE1_EN_OVRD_EN field to a new value. */
37605 #define XCVR_WR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_MASK, XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN(value)))
37606 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_EN_WIDTH))
37607 /*@}*/
37608 
37609 /*!
37610  * @name Register XCVR_TSM_OVRD3, field TSM_SPARE1_EN_OVRD[3] (RW)
37611  *
37612  * When TSM_SPARE1_EN_OVRD_EN=1, this value overrides the mission mode state of
37613  * the signal "tsm_spare1_en". This bit is ignored when TSM_SPARE1_EN_OVRD_EN==0.
37614  */
37615 /*@{*/
37616 /*! @brief Read current value of the XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD field. */
37617 #define XCVR_RD_TSM_OVRD3_TSM_SPARE1_EN_OVRD(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_MASK) >> XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_SHIFT)
37618 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE1_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_SHIFT, XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_WIDTH))
37619 
37620 /*! @brief Set the TSM_SPARE1_EN_OVRD field to a new value. */
37621 #define XCVR_WR_TSM_OVRD3_TSM_SPARE1_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_MASK, XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD(value)))
37622 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE1_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_SHIFT), XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_SHIFT, XCVR_TSM_OVRD3_TSM_SPARE1_EN_OVRD_WIDTH))
37623 /*@}*/
37624 
37625 /*!
37626  * @name Register XCVR_TSM_OVRD3, field TSM_SPARE2_EN_OVRD_EN[4] (RW)
37627  *
37628  * Values:
37629  * - 0b0 - Normal operation.
37630  * - 0b1 - Use the state of TSM_SPARE2_EN_OVRD to override the signal
37631  *     "tsm_spare2_en".
37632  */
37633 /*@{*/
37634 /*! @brief Read current value of the XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN field. */
37635 #define XCVR_RD_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_SHIFT)
37636 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_WIDTH))
37637 
37638 /*! @brief Set the TSM_SPARE2_EN_OVRD_EN field to a new value. */
37639 #define XCVR_WR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_MASK, XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN(value)))
37640 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_EN_WIDTH))
37641 /*@}*/
37642 
37643 /*!
37644  * @name Register XCVR_TSM_OVRD3, field TSM_SPARE2_EN_OVRD[5] (RW)
37645  *
37646  * When TSM_SPARE2_EN_OVRD_EN=1, this value overrides the mission mode state of
37647  * the signal "tsm_spare2_en". This bit is ignored when TSM_SPARE2_EN_OVRD_EN==0.
37648  */
37649 /*@{*/
37650 /*! @brief Read current value of the XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD field. */
37651 #define XCVR_RD_TSM_OVRD3_TSM_SPARE2_EN_OVRD(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_MASK) >> XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_SHIFT)
37652 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE2_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_SHIFT, XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_WIDTH))
37653 
37654 /*! @brief Set the TSM_SPARE2_EN_OVRD field to a new value. */
37655 #define XCVR_WR_TSM_OVRD3_TSM_SPARE2_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_MASK, XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD(value)))
37656 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE2_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_SHIFT), XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_SHIFT, XCVR_TSM_OVRD3_TSM_SPARE2_EN_OVRD_WIDTH))
37657 /*@}*/
37658 
37659 /*!
37660  * @name Register XCVR_TSM_OVRD3, field TSM_SPARE3_EN_OVRD_EN[6] (RW)
37661  *
37662  * Values:
37663  * - 0b0 - Normal operation.
37664  * - 0b1 - Use the state of TSM_SPARE3_EN_OVRD to override the signal
37665  *     "tsm_spare3_en".
37666  */
37667 /*@{*/
37668 /*! @brief Read current value of the XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN field. */
37669 #define XCVR_RD_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_MASK) >> XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_SHIFT)
37670 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_WIDTH))
37671 
37672 /*! @brief Set the TSM_SPARE3_EN_OVRD_EN field to a new value. */
37673 #define XCVR_WR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_MASK, XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN(value)))
37674 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_SHIFT), XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_SHIFT, XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_EN_WIDTH))
37675 /*@}*/
37676 
37677 /*!
37678  * @name Register XCVR_TSM_OVRD3, field TSM_SPARE3_EN_OVRD[7] (RW)
37679  *
37680  * When TSM_SPARE3_EN_OVRD_EN=1, this value overrides the mission mode state of
37681  * the signal "tsm_spare3_en". This bit is ignored when TSM_SPARE3_EN_OVRD_EN==0.
37682  */
37683 /*@{*/
37684 /*! @brief Read current value of the XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD field. */
37685 #define XCVR_RD_TSM_OVRD3_TSM_SPARE3_EN_OVRD(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_MASK) >> XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_SHIFT)
37686 #define XCVR_BRD_TSM_OVRD3_TSM_SPARE3_EN_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_SHIFT, XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_WIDTH))
37687 
37688 /*! @brief Set the TSM_SPARE3_EN_OVRD field to a new value. */
37689 #define XCVR_WR_TSM_OVRD3_TSM_SPARE3_EN_OVRD(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_MASK, XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD(value)))
37690 #define XCVR_BWR_TSM_OVRD3_TSM_SPARE3_EN_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_SHIFT), XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_SHIFT, XCVR_TSM_OVRD3_TSM_SPARE3_EN_OVRD_WIDTH))
37691 /*@}*/
37692 
37693 /*!
37694  * @name Register XCVR_TSM_OVRD3, field TX_MODE_OVRD_EN[8] (RW)
37695  *
37696  * Values:
37697  * - 0b0 - Normal operation.
37698  * - 0b1 - Use the state of TX_MODE_OVRD to override the signal "tx_mode".
37699  */
37700 /*@{*/
37701 /*! @brief Read current value of the XCVR_TSM_OVRD3_TX_MODE_OVRD_EN field. */
37702 #define XCVR_RD_TSM_OVRD3_TX_MODE_OVRD_EN(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_MASK) >> XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_SHIFT)
37703 #define XCVR_BRD_TSM_OVRD3_TX_MODE_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_SHIFT, XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_WIDTH))
37704 
37705 /*! @brief Set the TX_MODE_OVRD_EN field to a new value. */
37706 #define XCVR_WR_TSM_OVRD3_TX_MODE_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_MASK, XCVR_TSM_OVRD3_TX_MODE_OVRD_EN(value)))
37707 #define XCVR_BWR_TSM_OVRD3_TX_MODE_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_SHIFT), XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_SHIFT, XCVR_TSM_OVRD3_TX_MODE_OVRD_EN_WIDTH))
37708 /*@}*/
37709 
37710 /*!
37711  * @name Register XCVR_TSM_OVRD3, field TX_MODE_OVRD[9] (RW)
37712  *
37713  * When TX_MODE_OVRD_EN=1, this value overrides the mission mode state of the
37714  * signal "tx_mode". This bit is ignored when TX_MODE_OVRD_EN==0.
37715  */
37716 /*@{*/
37717 /*! @brief Read current value of the XCVR_TSM_OVRD3_TX_MODE_OVRD field. */
37718 #define XCVR_RD_TSM_OVRD3_TX_MODE_OVRD(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_TX_MODE_OVRD_MASK) >> XCVR_TSM_OVRD3_TX_MODE_OVRD_SHIFT)
37719 #define XCVR_BRD_TSM_OVRD3_TX_MODE_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM_OVRD3_TX_MODE_OVRD_SHIFT, XCVR_TSM_OVRD3_TX_MODE_OVRD_WIDTH))
37720 
37721 /*! @brief Set the TX_MODE_OVRD field to a new value. */
37722 #define XCVR_WR_TSM_OVRD3_TX_MODE_OVRD(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVRD3_TX_MODE_OVRD_MASK, XCVR_TSM_OVRD3_TX_MODE_OVRD(value)))
37723 #define XCVR_BWR_TSM_OVRD3_TX_MODE_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD3_TX_MODE_OVRD_SHIFT), XCVR_TSM_OVRD3_TX_MODE_OVRD_SHIFT, XCVR_TSM_OVRD3_TX_MODE_OVRD_WIDTH))
37724 /*@}*/
37725 
37726 /*!
37727  * @name Register XCVR_TSM_OVRD3, field RX_MODE_OVRD_EN[10] (RW)
37728  *
37729  * Values:
37730  * - 0b0 - Normal operation.
37731  * - 0b1 - Use the state of RX_MODE_OVRD to override the signal "rx_mode".
37732  */
37733 /*@{*/
37734 /*! @brief Read current value of the XCVR_TSM_OVRD3_RX_MODE_OVRD_EN field. */
37735 #define XCVR_RD_TSM_OVRD3_RX_MODE_OVRD_EN(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_MASK) >> XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_SHIFT)
37736 #define XCVR_BRD_TSM_OVRD3_RX_MODE_OVRD_EN(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_SHIFT, XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_WIDTH))
37737 
37738 /*! @brief Set the RX_MODE_OVRD_EN field to a new value. */
37739 #define XCVR_WR_TSM_OVRD3_RX_MODE_OVRD_EN(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_MASK, XCVR_TSM_OVRD3_RX_MODE_OVRD_EN(value)))
37740 #define XCVR_BWR_TSM_OVRD3_RX_MODE_OVRD_EN(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_SHIFT), XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_SHIFT, XCVR_TSM_OVRD3_RX_MODE_OVRD_EN_WIDTH))
37741 /*@}*/
37742 
37743 /*!
37744  * @name Register XCVR_TSM_OVRD3, field RX_MODE_OVRD[11] (RW)
37745  *
37746  * When RX_MODE_OVRD_EN=1, this value overrides the mission mode state of the
37747  * signal "rx_mode". This bit is ignored when RX_MODE_OVRD_EN==0.
37748  */
37749 /*@{*/
37750 /*! @brief Read current value of the XCVR_TSM_OVRD3_RX_MODE_OVRD field. */
37751 #define XCVR_RD_TSM_OVRD3_RX_MODE_OVRD(base) ((XCVR_TSM_OVRD3_REG(base) & XCVR_TSM_OVRD3_RX_MODE_OVRD_MASK) >> XCVR_TSM_OVRD3_RX_MODE_OVRD_SHIFT)
37752 #define XCVR_BRD_TSM_OVRD3_RX_MODE_OVRD(base) (BME_UBFX32(&XCVR_TSM_OVRD3_REG(base), XCVR_TSM_OVRD3_RX_MODE_OVRD_SHIFT, XCVR_TSM_OVRD3_RX_MODE_OVRD_WIDTH))
37753 
37754 /*! @brief Set the RX_MODE_OVRD field to a new value. */
37755 #define XCVR_WR_TSM_OVRD3_RX_MODE_OVRD(base, value) (XCVR_RMW_TSM_OVRD3(base, XCVR_TSM_OVRD3_RX_MODE_OVRD_MASK, XCVR_TSM_OVRD3_RX_MODE_OVRD(value)))
37756 #define XCVR_BWR_TSM_OVRD3_RX_MODE_OVRD(base, value) (BME_BFI32(&XCVR_TSM_OVRD3_REG(base), ((uint32_t)(value) << XCVR_TSM_OVRD3_RX_MODE_OVRD_SHIFT), XCVR_TSM_OVRD3_RX_MODE_OVRD_SHIFT, XCVR_TSM_OVRD3_RX_MODE_OVRD_WIDTH))
37757 /*@}*/
37758 
37759 /*******************************************************************************
37760  * XCVR_PA_POWER - PA Power
37761  ******************************************************************************/
37762 
37763 /*!
37764  * @brief XCVR_PA_POWER - PA Power (RW)
37765  *
37766  * Reset value: 0x00000000U
37767  *
37768  * This contents of this register are used as PA target power when
37769  * XCVR_CTRL[TGT_PWR_SRC] = 00.
37770  */
37771 /*!
37772  * @name Constants and macros for entire XCVR_PA_POWER register
37773  */
37774 /*@{*/
37775 #define XCVR_RD_PA_POWER(base)   (XCVR_PA_POWER_REG(base))
37776 #define XCVR_WR_PA_POWER(base, value) (XCVR_PA_POWER_REG(base) = (value))
37777 #define XCVR_RMW_PA_POWER(base, mask, value) (XCVR_WR_PA_POWER(base, (XCVR_RD_PA_POWER(base) & ~(mask)) | (value)))
37778 #define XCVR_SET_PA_POWER(base, value) (BME_OR32(&XCVR_PA_POWER_REG(base), (uint32_t)(value)))
37779 #define XCVR_CLR_PA_POWER(base, value) (BME_AND32(&XCVR_PA_POWER_REG(base), (uint32_t)(~(value))))
37780 #define XCVR_TOG_PA_POWER(base, value) (BME_XOR32(&XCVR_PA_POWER_REG(base), (uint32_t)(value)))
37781 /*@}*/
37782 
37783 /*
37784  * Constants & macros for individual XCVR_PA_POWER bitfields
37785  */
37786 
37787 /*!
37788  * @name Register XCVR_PA_POWER, field PA_POWER[3:0] (RW)
37789  *
37790  * PA Target Power
37791  */
37792 /*@{*/
37793 /*! @brief Read current value of the XCVR_PA_POWER_PA_POWER field. */
37794 #define XCVR_RD_PA_POWER_PA_POWER(base) ((XCVR_PA_POWER_REG(base) & XCVR_PA_POWER_PA_POWER_MASK) >> XCVR_PA_POWER_PA_POWER_SHIFT)
37795 #define XCVR_BRD_PA_POWER_PA_POWER(base) (BME_UBFX32(&XCVR_PA_POWER_REG(base), XCVR_PA_POWER_PA_POWER_SHIFT, XCVR_PA_POWER_PA_POWER_WIDTH))
37796 
37797 /*! @brief Set the PA_POWER field to a new value. */
37798 #define XCVR_WR_PA_POWER_PA_POWER(base, value) (XCVR_RMW_PA_POWER(base, XCVR_PA_POWER_PA_POWER_MASK, XCVR_PA_POWER_PA_POWER(value)))
37799 #define XCVR_BWR_PA_POWER_PA_POWER(base, value) (BME_BFI32(&XCVR_PA_POWER_REG(base), ((uint32_t)(value) << XCVR_PA_POWER_PA_POWER_SHIFT), XCVR_PA_POWER_PA_POWER_SHIFT, XCVR_PA_POWER_PA_POWER_WIDTH))
37800 /*@}*/
37801 
37802 /*******************************************************************************
37803  * XCVR_PA_BIAS_TBL0 - PA Bias Table 0
37804  ******************************************************************************/
37805 
37806 /*!
37807  * @brief XCVR_PA_BIAS_TBL0 - PA Bias Table 0 (RW)
37808  *
37809  * Reset value: 0x00000000U
37810  */
37811 /*!
37812  * @name Constants and macros for entire XCVR_PA_BIAS_TBL0 register
37813  */
37814 /*@{*/
37815 #define XCVR_RD_PA_BIAS_TBL0(base) (XCVR_PA_BIAS_TBL0_REG(base))
37816 #define XCVR_WR_PA_BIAS_TBL0(base, value) (XCVR_PA_BIAS_TBL0_REG(base) = (value))
37817 #define XCVR_RMW_PA_BIAS_TBL0(base, mask, value) (XCVR_WR_PA_BIAS_TBL0(base, (XCVR_RD_PA_BIAS_TBL0(base) & ~(mask)) | (value)))
37818 #define XCVR_SET_PA_BIAS_TBL0(base, value) (BME_OR32(&XCVR_PA_BIAS_TBL0_REG(base), (uint32_t)(value)))
37819 #define XCVR_CLR_PA_BIAS_TBL0(base, value) (BME_AND32(&XCVR_PA_BIAS_TBL0_REG(base), (uint32_t)(~(value))))
37820 #define XCVR_TOG_PA_BIAS_TBL0(base, value) (BME_XOR32(&XCVR_PA_BIAS_TBL0_REG(base), (uint32_t)(value)))
37821 /*@}*/
37822 
37823 /*
37824  * Constants & macros for individual XCVR_PA_BIAS_TBL0 bitfields
37825  */
37826 
37827 /*!
37828  * @name Register XCVR_PA_BIAS_TBL0, field PA_BIAS0[3:0] (RW)
37829  *
37830  * If PA ramping is enabled (TSM_CTRL[PA_RAMP_SEL] > 00), the contents of this
37831  * register are presented to the PA during PA ramping, when TSM tx_en transitions
37832  * low to high, and then for the duration of the first ramp step. During PA ramp
37833  * down, the contents of this register are the PA power value during the final
37834  * ramp step. In both cases, PA_BIAS0 cannot exceed target power (enforced by PA
37835  * ramping logic). When PA ramping is enabled, the contents of PA_BIAS0 are also
37836  * presented to the PA during sequence-idle conditions.
37837  */
37838 /*@{*/
37839 /*! @brief Read current value of the XCVR_PA_BIAS_TBL0_PA_BIAS0 field. */
37840 #define XCVR_RD_PA_BIAS_TBL0_PA_BIAS0(base) ((XCVR_PA_BIAS_TBL0_REG(base) & XCVR_PA_BIAS_TBL0_PA_BIAS0_MASK) >> XCVR_PA_BIAS_TBL0_PA_BIAS0_SHIFT)
37841 #define XCVR_BRD_PA_BIAS_TBL0_PA_BIAS0(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL0_REG(base), XCVR_PA_BIAS_TBL0_PA_BIAS0_SHIFT, XCVR_PA_BIAS_TBL0_PA_BIAS0_WIDTH))
37842 
37843 /*! @brief Set the PA_BIAS0 field to a new value. */
37844 #define XCVR_WR_PA_BIAS_TBL0_PA_BIAS0(base, value) (XCVR_RMW_PA_BIAS_TBL0(base, XCVR_PA_BIAS_TBL0_PA_BIAS0_MASK, XCVR_PA_BIAS_TBL0_PA_BIAS0(value)))
37845 #define XCVR_BWR_PA_BIAS_TBL0_PA_BIAS0(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL0_REG(base), ((uint32_t)(value) << XCVR_PA_BIAS_TBL0_PA_BIAS0_SHIFT), XCVR_PA_BIAS_TBL0_PA_BIAS0_SHIFT, XCVR_PA_BIAS_TBL0_PA_BIAS0_WIDTH))
37846 /*@}*/
37847 
37848 /*!
37849  * @name Register XCVR_PA_BIAS_TBL0, field PA_BIAS1[11:8] (RW)
37850  *
37851  * If PA ramping is enabled (TSM_CTRL[PA_RAMP_SEL] > 00), the contents of this
37852  * register are presented to the PA during PA ramping, for the duration of the
37853  * second ramp step. During PA ramp down, the contents of this register are the PA
37854  * power value during the second-to-last ramp step. In both cases, PA_BIAS1 cannot
37855  * exceed target power (enforced by PA ramping logic).
37856  */
37857 /*@{*/
37858 /*! @brief Read current value of the XCVR_PA_BIAS_TBL0_PA_BIAS1 field. */
37859 #define XCVR_RD_PA_BIAS_TBL0_PA_BIAS1(base) ((XCVR_PA_BIAS_TBL0_REG(base) & XCVR_PA_BIAS_TBL0_PA_BIAS1_MASK) >> XCVR_PA_BIAS_TBL0_PA_BIAS1_SHIFT)
37860 #define XCVR_BRD_PA_BIAS_TBL0_PA_BIAS1(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL0_REG(base), XCVR_PA_BIAS_TBL0_PA_BIAS1_SHIFT, XCVR_PA_BIAS_TBL0_PA_BIAS1_WIDTH))
37861 
37862 /*! @brief Set the PA_BIAS1 field to a new value. */
37863 #define XCVR_WR_PA_BIAS_TBL0_PA_BIAS1(base, value) (XCVR_RMW_PA_BIAS_TBL0(base, XCVR_PA_BIAS_TBL0_PA_BIAS1_MASK, XCVR_PA_BIAS_TBL0_PA_BIAS1(value)))
37864 #define XCVR_BWR_PA_BIAS_TBL0_PA_BIAS1(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL0_REG(base), ((uint32_t)(value) << XCVR_PA_BIAS_TBL0_PA_BIAS1_SHIFT), XCVR_PA_BIAS_TBL0_PA_BIAS1_SHIFT, XCVR_PA_BIAS_TBL0_PA_BIAS1_WIDTH))
37865 /*@}*/
37866 
37867 /*!
37868  * @name Register XCVR_PA_BIAS_TBL0, field PA_BIAS2[19:16] (RW)
37869  *
37870  * If PA ramping is enabled (TSM_CTRL[PA_RAMP_EN] > 00), the contents of this
37871  * register are presented to the PA during PA ramping, for the duration of the
37872  * third ramp step. During PA ramp down, the contents of this register are the PA
37873  * power value during the third-to-last ramp step. In both cases, PA_BIAS2 cannot
37874  * exceed target power (enforced by PA ramping logic).
37875  */
37876 /*@{*/
37877 /*! @brief Read current value of the XCVR_PA_BIAS_TBL0_PA_BIAS2 field. */
37878 #define XCVR_RD_PA_BIAS_TBL0_PA_BIAS2(base) ((XCVR_PA_BIAS_TBL0_REG(base) & XCVR_PA_BIAS_TBL0_PA_BIAS2_MASK) >> XCVR_PA_BIAS_TBL0_PA_BIAS2_SHIFT)
37879 #define XCVR_BRD_PA_BIAS_TBL0_PA_BIAS2(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL0_REG(base), XCVR_PA_BIAS_TBL0_PA_BIAS2_SHIFT, XCVR_PA_BIAS_TBL0_PA_BIAS2_WIDTH))
37880 
37881 /*! @brief Set the PA_BIAS2 field to a new value. */
37882 #define XCVR_WR_PA_BIAS_TBL0_PA_BIAS2(base, value) (XCVR_RMW_PA_BIAS_TBL0(base, XCVR_PA_BIAS_TBL0_PA_BIAS2_MASK, XCVR_PA_BIAS_TBL0_PA_BIAS2(value)))
37883 #define XCVR_BWR_PA_BIAS_TBL0_PA_BIAS2(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL0_REG(base), ((uint32_t)(value) << XCVR_PA_BIAS_TBL0_PA_BIAS2_SHIFT), XCVR_PA_BIAS_TBL0_PA_BIAS2_SHIFT, XCVR_PA_BIAS_TBL0_PA_BIAS2_WIDTH))
37884 /*@}*/
37885 
37886 /*!
37887  * @name Register XCVR_PA_BIAS_TBL0, field PA_BIAS3[27:24] (RW)
37888  *
37889  * If PA ramping is enabled (TSM_CTRL[PA_RAMP_EN] > 00), the contents of this
37890  * register are presented to the PA during PA ramping, for the duration of the
37891  * fourth ramp step. During PA ramp down, the contents of this register are the PA
37892  * power value during the fourth-to-last ramp step. In both cases, PA_BIAS3 cannot
37893  * exceed target power (enforced by PA ramping logic).
37894  */
37895 /*@{*/
37896 /*! @brief Read current value of the XCVR_PA_BIAS_TBL0_PA_BIAS3 field. */
37897 #define XCVR_RD_PA_BIAS_TBL0_PA_BIAS3(base) ((XCVR_PA_BIAS_TBL0_REG(base) & XCVR_PA_BIAS_TBL0_PA_BIAS3_MASK) >> XCVR_PA_BIAS_TBL0_PA_BIAS3_SHIFT)
37898 #define XCVR_BRD_PA_BIAS_TBL0_PA_BIAS3(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL0_REG(base), XCVR_PA_BIAS_TBL0_PA_BIAS3_SHIFT, XCVR_PA_BIAS_TBL0_PA_BIAS3_WIDTH))
37899 
37900 /*! @brief Set the PA_BIAS3 field to a new value. */
37901 #define XCVR_WR_PA_BIAS_TBL0_PA_BIAS3(base, value) (XCVR_RMW_PA_BIAS_TBL0(base, XCVR_PA_BIAS_TBL0_PA_BIAS3_MASK, XCVR_PA_BIAS_TBL0_PA_BIAS3(value)))
37902 #define XCVR_BWR_PA_BIAS_TBL0_PA_BIAS3(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL0_REG(base), ((uint32_t)(value) << XCVR_PA_BIAS_TBL0_PA_BIAS3_SHIFT), XCVR_PA_BIAS_TBL0_PA_BIAS3_SHIFT, XCVR_PA_BIAS_TBL0_PA_BIAS3_WIDTH))
37903 /*@}*/
37904 
37905 /*******************************************************************************
37906  * XCVR_PA_BIAS_TBL1 - PA Bias Table 1
37907  ******************************************************************************/
37908 
37909 /*!
37910  * @brief XCVR_PA_BIAS_TBL1 - PA Bias Table 1 (RW)
37911  *
37912  * Reset value: 0x00000000U
37913  */
37914 /*!
37915  * @name Constants and macros for entire XCVR_PA_BIAS_TBL1 register
37916  */
37917 /*@{*/
37918 #define XCVR_RD_PA_BIAS_TBL1(base) (XCVR_PA_BIAS_TBL1_REG(base))
37919 #define XCVR_WR_PA_BIAS_TBL1(base, value) (XCVR_PA_BIAS_TBL1_REG(base) = (value))
37920 #define XCVR_RMW_PA_BIAS_TBL1(base, mask, value) (XCVR_WR_PA_BIAS_TBL1(base, (XCVR_RD_PA_BIAS_TBL1(base) & ~(mask)) | (value)))
37921 #define XCVR_SET_PA_BIAS_TBL1(base, value) (BME_OR32(&XCVR_PA_BIAS_TBL1_REG(base), (uint32_t)(value)))
37922 #define XCVR_CLR_PA_BIAS_TBL1(base, value) (BME_AND32(&XCVR_PA_BIAS_TBL1_REG(base), (uint32_t)(~(value))))
37923 #define XCVR_TOG_PA_BIAS_TBL1(base, value) (BME_XOR32(&XCVR_PA_BIAS_TBL1_REG(base), (uint32_t)(value)))
37924 /*@}*/
37925 
37926 /*
37927  * Constants & macros for individual XCVR_PA_BIAS_TBL1 bitfields
37928  */
37929 
37930 /*!
37931  * @name Register XCVR_PA_BIAS_TBL1, field PA_BIAS4[3:0] (RW)
37932  *
37933  * If PA ramping is enabled (TSM_CTRL[PA_RAMP_EN] > 00), the contents of this
37934  * register are presented to the PA during PA ramping, for the duration of the
37935  * fifth ramp step. During PA ramp down, the contents of this register are the PA
37936  * power value during the fifth-to-last ramp step. In both cases, PA_BIAS4 cannot
37937  * exceed target power (enforced by PA ramping logic).
37938  */
37939 /*@{*/
37940 /*! @brief Read current value of the XCVR_PA_BIAS_TBL1_PA_BIAS4 field. */
37941 #define XCVR_RD_PA_BIAS_TBL1_PA_BIAS4(base) ((XCVR_PA_BIAS_TBL1_REG(base) & XCVR_PA_BIAS_TBL1_PA_BIAS4_MASK) >> XCVR_PA_BIAS_TBL1_PA_BIAS4_SHIFT)
37942 #define XCVR_BRD_PA_BIAS_TBL1_PA_BIAS4(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL1_REG(base), XCVR_PA_BIAS_TBL1_PA_BIAS4_SHIFT, XCVR_PA_BIAS_TBL1_PA_BIAS4_WIDTH))
37943 
37944 /*! @brief Set the PA_BIAS4 field to a new value. */
37945 #define XCVR_WR_PA_BIAS_TBL1_PA_BIAS4(base, value) (XCVR_RMW_PA_BIAS_TBL1(base, XCVR_PA_BIAS_TBL1_PA_BIAS4_MASK, XCVR_PA_BIAS_TBL1_PA_BIAS4(value)))
37946 #define XCVR_BWR_PA_BIAS_TBL1_PA_BIAS4(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL1_REG(base), ((uint32_t)(value) << XCVR_PA_BIAS_TBL1_PA_BIAS4_SHIFT), XCVR_PA_BIAS_TBL1_PA_BIAS4_SHIFT, XCVR_PA_BIAS_TBL1_PA_BIAS4_WIDTH))
37947 /*@}*/
37948 
37949 /*!
37950  * @name Register XCVR_PA_BIAS_TBL1, field PA_BIAS5[11:8] (RW)
37951  *
37952  * If PA ramping is enabled (TSM_CTRL[PA_RAMP_EN] > 00), the contents of this
37953  * register are presented to the PA during PA ramping, for the duration of the
37954  * sixth ramp step. During PA ramp down, the contents of this register are the PA
37955  * power value during the sixth-to-last ramp step. In both cases, PA_BIAS5 cannot
37956  * exceed target power (enforced by PA ramping logic).
37957  */
37958 /*@{*/
37959 /*! @brief Read current value of the XCVR_PA_BIAS_TBL1_PA_BIAS5 field. */
37960 #define XCVR_RD_PA_BIAS_TBL1_PA_BIAS5(base) ((XCVR_PA_BIAS_TBL1_REG(base) & XCVR_PA_BIAS_TBL1_PA_BIAS5_MASK) >> XCVR_PA_BIAS_TBL1_PA_BIAS5_SHIFT)
37961 #define XCVR_BRD_PA_BIAS_TBL1_PA_BIAS5(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL1_REG(base), XCVR_PA_BIAS_TBL1_PA_BIAS5_SHIFT, XCVR_PA_BIAS_TBL1_PA_BIAS5_WIDTH))
37962 
37963 /*! @brief Set the PA_BIAS5 field to a new value. */
37964 #define XCVR_WR_PA_BIAS_TBL1_PA_BIAS5(base, value) (XCVR_RMW_PA_BIAS_TBL1(base, XCVR_PA_BIAS_TBL1_PA_BIAS5_MASK, XCVR_PA_BIAS_TBL1_PA_BIAS5(value)))
37965 #define XCVR_BWR_PA_BIAS_TBL1_PA_BIAS5(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL1_REG(base), ((uint32_t)(value) << XCVR_PA_BIAS_TBL1_PA_BIAS5_SHIFT), XCVR_PA_BIAS_TBL1_PA_BIAS5_SHIFT, XCVR_PA_BIAS_TBL1_PA_BIAS5_WIDTH))
37966 /*@}*/
37967 
37968 /*!
37969  * @name Register XCVR_PA_BIAS_TBL1, field PA_BIAS6[19:16] (RW)
37970  *
37971  * If PA ramping is enabled (TSM_CTRL[PA_RAMP_EN] > 00), the contents of this
37972  * register are presented to the PA during PA ramping, for the duration of the
37973  * seventh ramp step. During PA ramp down, the contents of this register are the PA
37974  * power value during the seventh-to-last ramp step. In both cases, PA_BIAS6
37975  * cannot exceed target power (enforced by PA ramping logic).
37976  */
37977 /*@{*/
37978 /*! @brief Read current value of the XCVR_PA_BIAS_TBL1_PA_BIAS6 field. */
37979 #define XCVR_RD_PA_BIAS_TBL1_PA_BIAS6(base) ((XCVR_PA_BIAS_TBL1_REG(base) & XCVR_PA_BIAS_TBL1_PA_BIAS6_MASK) >> XCVR_PA_BIAS_TBL1_PA_BIAS6_SHIFT)
37980 #define XCVR_BRD_PA_BIAS_TBL1_PA_BIAS6(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL1_REG(base), XCVR_PA_BIAS_TBL1_PA_BIAS6_SHIFT, XCVR_PA_BIAS_TBL1_PA_BIAS6_WIDTH))
37981 
37982 /*! @brief Set the PA_BIAS6 field to a new value. */
37983 #define XCVR_WR_PA_BIAS_TBL1_PA_BIAS6(base, value) (XCVR_RMW_PA_BIAS_TBL1(base, XCVR_PA_BIAS_TBL1_PA_BIAS6_MASK, XCVR_PA_BIAS_TBL1_PA_BIAS6(value)))
37984 #define XCVR_BWR_PA_BIAS_TBL1_PA_BIAS6(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL1_REG(base), ((uint32_t)(value) << XCVR_PA_BIAS_TBL1_PA_BIAS6_SHIFT), XCVR_PA_BIAS_TBL1_PA_BIAS6_SHIFT, XCVR_PA_BIAS_TBL1_PA_BIAS6_WIDTH))
37985 /*@}*/
37986 
37987 /*!
37988  * @name Register XCVR_PA_BIAS_TBL1, field PA_BIAS7[27:24] (RW)
37989  *
37990  * If PA ramping is enabled (TSM_CTRL[PA_RAMP_EN] > 00), the contents of this
37991  * register are presented to the PA during PA ramping, for the duration of the
37992  * eighth (final) ramp step. During PA ramp down, the contents of this register are
37993  * the PA power value during the eighth-to-last (first) ramp step. In both cases,
37994  * PA_BIAS7 cannot exceed target power (enforced by PA ramping logic).
37995  */
37996 /*@{*/
37997 /*! @brief Read current value of the XCVR_PA_BIAS_TBL1_PA_BIAS7 field. */
37998 #define XCVR_RD_PA_BIAS_TBL1_PA_BIAS7(base) ((XCVR_PA_BIAS_TBL1_REG(base) & XCVR_PA_BIAS_TBL1_PA_BIAS7_MASK) >> XCVR_PA_BIAS_TBL1_PA_BIAS7_SHIFT)
37999 #define XCVR_BRD_PA_BIAS_TBL1_PA_BIAS7(base) (BME_UBFX32(&XCVR_PA_BIAS_TBL1_REG(base), XCVR_PA_BIAS_TBL1_PA_BIAS7_SHIFT, XCVR_PA_BIAS_TBL1_PA_BIAS7_WIDTH))
38000 
38001 /*! @brief Set the PA_BIAS7 field to a new value. */
38002 #define XCVR_WR_PA_BIAS_TBL1_PA_BIAS7(base, value) (XCVR_RMW_PA_BIAS_TBL1(base, XCVR_PA_BIAS_TBL1_PA_BIAS7_MASK, XCVR_PA_BIAS_TBL1_PA_BIAS7(value)))
38003 #define XCVR_BWR_PA_BIAS_TBL1_PA_BIAS7(base, value) (BME_BFI32(&XCVR_PA_BIAS_TBL1_REG(base), ((uint32_t)(value) << XCVR_PA_BIAS_TBL1_PA_BIAS7_SHIFT), XCVR_PA_BIAS_TBL1_PA_BIAS7_SHIFT, XCVR_PA_BIAS_TBL1_PA_BIAS7_WIDTH))
38004 /*@}*/
38005 
38006 /*******************************************************************************
38007  * XCVR_RECYCLE_COUNT - Recycle Count Register
38008  ******************************************************************************/
38009 
38010 /*!
38011  * @brief XCVR_RECYCLE_COUNT - Recycle Count Register (RW)
38012  *
38013  * Reset value: 0x00000826U
38014  */
38015 /*!
38016  * @name Constants and macros for entire XCVR_RECYCLE_COUNT register
38017  */
38018 /*@{*/
38019 #define XCVR_RD_RECYCLE_COUNT(base) (XCVR_RECYCLE_COUNT_REG(base))
38020 #define XCVR_WR_RECYCLE_COUNT(base, value) (XCVR_RECYCLE_COUNT_REG(base) = (value))
38021 #define XCVR_RMW_RECYCLE_COUNT(base, mask, value) (XCVR_WR_RECYCLE_COUNT(base, (XCVR_RD_RECYCLE_COUNT(base) & ~(mask)) | (value)))
38022 #define XCVR_SET_RECYCLE_COUNT(base, value) (BME_OR32(&XCVR_RECYCLE_COUNT_REG(base), (uint32_t)(value)))
38023 #define XCVR_CLR_RECYCLE_COUNT(base, value) (BME_AND32(&XCVR_RECYCLE_COUNT_REG(base), (uint32_t)(~(value))))
38024 #define XCVR_TOG_RECYCLE_COUNT(base, value) (BME_XOR32(&XCVR_RECYCLE_COUNT_REG(base), (uint32_t)(value)))
38025 /*@}*/
38026 
38027 /*
38028  * Constants & macros for individual XCVR_RECYCLE_COUNT bitfields
38029  */
38030 
38031 /*!
38032  * @name Register XCVR_RECYCLE_COUNT, field RECYCLE_COUNT0[7:0] (RW)
38033  *
38034  * The RECYCLE_COUNT0[7:0] register determines the TSM count value to which the
38035  * TSM "recycles" when the Zigbee Sequence Manager (ZSM) state "RX_CYC" is
38036  * reached and the ZSM asserts tsm_recycle[0] to TSM. This register also determines the
38037  * TSM count value to which the TSM recycles when the ZSM state RX_CCCA is
38038  * reached because tsm_recycle[0] is also asserted in this state. The intention is for
38039  * this register to be programmed to a TSM count value such that the TSM
38040  * re-asserts its "rx_init" output, but there are no restrictions on programming this
38041  * register. An RX recycle is a command from ZSM to TSM to jump from the TSM ON
38042  * phase back to a programmable point in the WARMUP phase, and resume counting from
38043  * there. A recycle will result from the reception of a packet with bad CRC or
38044  * one which fails packet-filtering rules, or the end of a CCA operation in
38045  * Continuous CCA mode which results in a channel indicating "busy".
38046  */
38047 /*@{*/
38048 /*! @brief Read current value of the XCVR_RECYCLE_COUNT_RECYCLE_COUNT0 field. */
38049 #define XCVR_RD_RECYCLE_COUNT_RECYCLE_COUNT0(base) ((XCVR_RECYCLE_COUNT_REG(base) & XCVR_RECYCLE_COUNT_RECYCLE_COUNT0_MASK) >> XCVR_RECYCLE_COUNT_RECYCLE_COUNT0_SHIFT)
38050 #define XCVR_BRD_RECYCLE_COUNT_RECYCLE_COUNT0(base) (BME_UBFX32(&XCVR_RECYCLE_COUNT_REG(base), XCVR_RECYCLE_COUNT_RECYCLE_COUNT0_SHIFT, XCVR_RECYCLE_COUNT_RECYCLE_COUNT0_WIDTH))
38051 
38052 /*! @brief Set the RECYCLE_COUNT0 field to a new value. */
38053 #define XCVR_WR_RECYCLE_COUNT_RECYCLE_COUNT0(base, value) (XCVR_RMW_RECYCLE_COUNT(base, XCVR_RECYCLE_COUNT_RECYCLE_COUNT0_MASK, XCVR_RECYCLE_COUNT_RECYCLE_COUNT0(value)))
38054 #define XCVR_BWR_RECYCLE_COUNT_RECYCLE_COUNT0(base, value) (BME_BFI32(&XCVR_RECYCLE_COUNT_REG(base), ((uint32_t)(value) << XCVR_RECYCLE_COUNT_RECYCLE_COUNT0_SHIFT), XCVR_RECYCLE_COUNT_RECYCLE_COUNT0_SHIFT, XCVR_RECYCLE_COUNT_RECYCLE_COUNT0_WIDTH))
38055 /*@}*/
38056 
38057 /*!
38058  * @name Register XCVR_RECYCLE_COUNT, field RECYCLE_COUNT1[15:8] (RW)
38059  *
38060  * The RECYCLE_COUNT1[7:0] register determines the TSM count value to which the
38061  * TSM "recycles" when the Zigbee Sequence Manager (ZSM) state "RX_PAN1" is
38062  * reached and the ZSM asserts tsm_recycle[1] to TSM. The intention is for this
38063  * register to be programmed to a TSM count value such that the TSM de-asserts, and
38064  * then re-asserts its "pll_dig_en" output, to effectuate a Dual PAN on-the-fly
38065  * channel change, but there are no restrictions on programming this register. An RX
38066  * recycle is a command from ZSM to TSM to jump from the TSM ON phase back to a
38067  * programmable point in the WARMUP phase, and resume counting from there. A
38068  * recycle will result from the expiration of the Dual PAN Dwell Timer, at which point
38069  * an RF-channel change is required. This necessitates the desassertion and
38070  * reassertion of pll_dig_en, hence the return to the WARMUP phase at the appropriate
38071  * point.
38072  */
38073 /*@{*/
38074 /*! @brief Read current value of the XCVR_RECYCLE_COUNT_RECYCLE_COUNT1 field. */
38075 #define XCVR_RD_RECYCLE_COUNT_RECYCLE_COUNT1(base) ((XCVR_RECYCLE_COUNT_REG(base) & XCVR_RECYCLE_COUNT_RECYCLE_COUNT1_MASK) >> XCVR_RECYCLE_COUNT_RECYCLE_COUNT1_SHIFT)
38076 #define XCVR_BRD_RECYCLE_COUNT_RECYCLE_COUNT1(base) (BME_UBFX32(&XCVR_RECYCLE_COUNT_REG(base), XCVR_RECYCLE_COUNT_RECYCLE_COUNT1_SHIFT, XCVR_RECYCLE_COUNT_RECYCLE_COUNT1_WIDTH))
38077 
38078 /*! @brief Set the RECYCLE_COUNT1 field to a new value. */
38079 #define XCVR_WR_RECYCLE_COUNT_RECYCLE_COUNT1(base, value) (XCVR_RMW_RECYCLE_COUNT(base, XCVR_RECYCLE_COUNT_RECYCLE_COUNT1_MASK, XCVR_RECYCLE_COUNT_RECYCLE_COUNT1(value)))
38080 #define XCVR_BWR_RECYCLE_COUNT_RECYCLE_COUNT1(base, value) (BME_BFI32(&XCVR_RECYCLE_COUNT_REG(base), ((uint32_t)(value) << XCVR_RECYCLE_COUNT_RECYCLE_COUNT1_SHIFT), XCVR_RECYCLE_COUNT_RECYCLE_COUNT1_SHIFT, XCVR_RECYCLE_COUNT_RECYCLE_COUNT1_WIDTH))
38081 /*@}*/
38082 
38083 /*******************************************************************************
38084  * XCVR_TSM_TIMING00 - TSM_TIMING00
38085  ******************************************************************************/
38086 
38087 /*!
38088  * @brief XCVR_TSM_TIMING00 - TSM_TIMING00 (RW)
38089  *
38090  * Reset value: 0x65006A00U
38091  *
38092  * This register contains the timing values to control the assertion and
38093  * deassertion times for both TX and RX sequences for the PLL_REG_EN TSM signal or
38094  * signal group.
38095  */
38096 /*!
38097  * @name Constants and macros for entire XCVR_TSM_TIMING00 register
38098  */
38099 /*@{*/
38100 #define XCVR_RD_TSM_TIMING00(base) (XCVR_TSM_TIMING00_REG(base))
38101 #define XCVR_WR_TSM_TIMING00(base, value) (XCVR_TSM_TIMING00_REG(base) = (value))
38102 #define XCVR_RMW_TSM_TIMING00(base, mask, value) (XCVR_WR_TSM_TIMING00(base, (XCVR_RD_TSM_TIMING00(base) & ~(mask)) | (value)))
38103 #define XCVR_SET_TSM_TIMING00(base, value) (BME_OR32(&XCVR_TSM_TIMING00_REG(base), (uint32_t)(value)))
38104 #define XCVR_CLR_TSM_TIMING00(base, value) (BME_AND32(&XCVR_TSM_TIMING00_REG(base), (uint32_t)(~(value))))
38105 #define XCVR_TOG_TSM_TIMING00(base, value) (BME_XOR32(&XCVR_TSM_TIMING00_REG(base), (uint32_t)(value)))
38106 /*@}*/
38107 
38108 /*
38109  * Constants & macros for individual XCVR_TSM_TIMING00 bitfields
38110  */
38111 
38112 /*!
38113  * @name Register XCVR_TSM_TIMING00, field PLL_REG_EN_TX_HI[7:0] (RW)
38114  *
38115  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
38116  * at which the PLL_REG_EN signal or group will transition from LO to HI.
38117  */
38118 /*@{*/
38119 /*! @brief Read current value of the XCVR_TSM_TIMING00_PLL_REG_EN_TX_HI field. */
38120 #define XCVR_RD_TSM_TIMING00_PLL_REG_EN_TX_HI(base) ((XCVR_TSM_TIMING00_REG(base) & XCVR_TSM_TIMING00_PLL_REG_EN_TX_HI_MASK) >> XCVR_TSM_TIMING00_PLL_REG_EN_TX_HI_SHIFT)
38121 #define XCVR_BRD_TSM_TIMING00_PLL_REG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING00_REG(base), XCVR_TSM_TIMING00_PLL_REG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING00_PLL_REG_EN_TX_HI_WIDTH))
38122 
38123 /*! @brief Set the PLL_REG_EN_TX_HI field to a new value. */
38124 #define XCVR_WR_TSM_TIMING00_PLL_REG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING00(base, XCVR_TSM_TIMING00_PLL_REG_EN_TX_HI_MASK, XCVR_TSM_TIMING00_PLL_REG_EN_TX_HI(value)))
38125 #define XCVR_BWR_TSM_TIMING00_PLL_REG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING00_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING00_PLL_REG_EN_TX_HI_SHIFT), XCVR_TSM_TIMING00_PLL_REG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING00_PLL_REG_EN_TX_HI_WIDTH))
38126 /*@}*/
38127 
38128 /*!
38129  * @name Register XCVR_TSM_TIMING00, field PLL_REG_EN_TX_LO[15:8] (RW)
38130  *
38131  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
38132  * at which the PLL_REG_EN signal or group will transition from HI to LO.
38133  */
38134 /*@{*/
38135 /*! @brief Read current value of the XCVR_TSM_TIMING00_PLL_REG_EN_TX_LO field. */
38136 #define XCVR_RD_TSM_TIMING00_PLL_REG_EN_TX_LO(base) ((XCVR_TSM_TIMING00_REG(base) & XCVR_TSM_TIMING00_PLL_REG_EN_TX_LO_MASK) >> XCVR_TSM_TIMING00_PLL_REG_EN_TX_LO_SHIFT)
38137 #define XCVR_BRD_TSM_TIMING00_PLL_REG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING00_REG(base), XCVR_TSM_TIMING00_PLL_REG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING00_PLL_REG_EN_TX_LO_WIDTH))
38138 
38139 /*! @brief Set the PLL_REG_EN_TX_LO field to a new value. */
38140 #define XCVR_WR_TSM_TIMING00_PLL_REG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING00(base, XCVR_TSM_TIMING00_PLL_REG_EN_TX_LO_MASK, XCVR_TSM_TIMING00_PLL_REG_EN_TX_LO(value)))
38141 #define XCVR_BWR_TSM_TIMING00_PLL_REG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING00_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING00_PLL_REG_EN_TX_LO_SHIFT), XCVR_TSM_TIMING00_PLL_REG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING00_PLL_REG_EN_TX_LO_WIDTH))
38142 /*@}*/
38143 
38144 /*!
38145  * @name Register XCVR_TSM_TIMING00, field PLL_REG_EN_RX_HI[23:16] (RW)
38146  *
38147  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
38148  * at which the PLL_REG_EN signal or group will transition from LO to HI.
38149  */
38150 /*@{*/
38151 /*! @brief Read current value of the XCVR_TSM_TIMING00_PLL_REG_EN_RX_HI field. */
38152 #define XCVR_RD_TSM_TIMING00_PLL_REG_EN_RX_HI(base) ((XCVR_TSM_TIMING00_REG(base) & XCVR_TSM_TIMING00_PLL_REG_EN_RX_HI_MASK) >> XCVR_TSM_TIMING00_PLL_REG_EN_RX_HI_SHIFT)
38153 #define XCVR_BRD_TSM_TIMING00_PLL_REG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING00_REG(base), XCVR_TSM_TIMING00_PLL_REG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING00_PLL_REG_EN_RX_HI_WIDTH))
38154 
38155 /*! @brief Set the PLL_REG_EN_RX_HI field to a new value. */
38156 #define XCVR_WR_TSM_TIMING00_PLL_REG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING00(base, XCVR_TSM_TIMING00_PLL_REG_EN_RX_HI_MASK, XCVR_TSM_TIMING00_PLL_REG_EN_RX_HI(value)))
38157 #define XCVR_BWR_TSM_TIMING00_PLL_REG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING00_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING00_PLL_REG_EN_RX_HI_SHIFT), XCVR_TSM_TIMING00_PLL_REG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING00_PLL_REG_EN_RX_HI_WIDTH))
38158 /*@}*/
38159 
38160 /*!
38161  * @name Register XCVR_TSM_TIMING00, field PLL_REG_EN_RX_LO[31:24] (RW)
38162  *
38163  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
38164  * at which the PLL_REG_EN signal or group will transition from HI to LO.
38165  */
38166 /*@{*/
38167 /*! @brief Read current value of the XCVR_TSM_TIMING00_PLL_REG_EN_RX_LO field. */
38168 #define XCVR_RD_TSM_TIMING00_PLL_REG_EN_RX_LO(base) ((XCVR_TSM_TIMING00_REG(base) & XCVR_TSM_TIMING00_PLL_REG_EN_RX_LO_MASK) >> XCVR_TSM_TIMING00_PLL_REG_EN_RX_LO_SHIFT)
38169 #define XCVR_BRD_TSM_TIMING00_PLL_REG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING00_REG(base), XCVR_TSM_TIMING00_PLL_REG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING00_PLL_REG_EN_RX_LO_WIDTH))
38170 
38171 /*! @brief Set the PLL_REG_EN_RX_LO field to a new value. */
38172 #define XCVR_WR_TSM_TIMING00_PLL_REG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING00(base, XCVR_TSM_TIMING00_PLL_REG_EN_RX_LO_MASK, XCVR_TSM_TIMING00_PLL_REG_EN_RX_LO(value)))
38173 #define XCVR_BWR_TSM_TIMING00_PLL_REG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING00_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING00_PLL_REG_EN_RX_LO_SHIFT), XCVR_TSM_TIMING00_PLL_REG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING00_PLL_REG_EN_RX_LO_WIDTH))
38174 /*@}*/
38175 
38176 /*******************************************************************************
38177  * XCVR_TSM_TIMING01 - TSM_TIMING01
38178  ******************************************************************************/
38179 
38180 /*!
38181  * @brief XCVR_TSM_TIMING01 - TSM_TIMING01 (RW)
38182  *
38183  * Reset value: 0x65006A00U
38184  *
38185  * This register contains the timing values to control the assertion and
38186  * deassertion times for both TX and RX sequences for the PLL_VCO_REG_EN TSM signal or
38187  * signal group.
38188  */
38189 /*!
38190  * @name Constants and macros for entire XCVR_TSM_TIMING01 register
38191  */
38192 /*@{*/
38193 #define XCVR_RD_TSM_TIMING01(base) (XCVR_TSM_TIMING01_REG(base))
38194 #define XCVR_WR_TSM_TIMING01(base, value) (XCVR_TSM_TIMING01_REG(base) = (value))
38195 #define XCVR_RMW_TSM_TIMING01(base, mask, value) (XCVR_WR_TSM_TIMING01(base, (XCVR_RD_TSM_TIMING01(base) & ~(mask)) | (value)))
38196 #define XCVR_SET_TSM_TIMING01(base, value) (BME_OR32(&XCVR_TSM_TIMING01_REG(base), (uint32_t)(value)))
38197 #define XCVR_CLR_TSM_TIMING01(base, value) (BME_AND32(&XCVR_TSM_TIMING01_REG(base), (uint32_t)(~(value))))
38198 #define XCVR_TOG_TSM_TIMING01(base, value) (BME_XOR32(&XCVR_TSM_TIMING01_REG(base), (uint32_t)(value)))
38199 /*@}*/
38200 
38201 /*
38202  * Constants & macros for individual XCVR_TSM_TIMING01 bitfields
38203  */
38204 
38205 /*!
38206  * @name Register XCVR_TSM_TIMING01, field PLL_VCO_REG_EN_TX_HI[7:0] (RW)
38207  *
38208  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
38209  * at which the PLL_VCO_REG_EN signal or group will transition from LO to HI.
38210  */
38211 /*@{*/
38212 /*! @brief Read current value of the XCVR_TSM_TIMING01_PLL_VCO_REG_EN_TX_HI field. */
38213 #define XCVR_RD_TSM_TIMING01_PLL_VCO_REG_EN_TX_HI(base) ((XCVR_TSM_TIMING01_REG(base) & XCVR_TSM_TIMING01_PLL_VCO_REG_EN_TX_HI_MASK) >> XCVR_TSM_TIMING01_PLL_VCO_REG_EN_TX_HI_SHIFT)
38214 #define XCVR_BRD_TSM_TIMING01_PLL_VCO_REG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING01_REG(base), XCVR_TSM_TIMING01_PLL_VCO_REG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING01_PLL_VCO_REG_EN_TX_HI_WIDTH))
38215 
38216 /*! @brief Set the PLL_VCO_REG_EN_TX_HI field to a new value. */
38217 #define XCVR_WR_TSM_TIMING01_PLL_VCO_REG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING01(base, XCVR_TSM_TIMING01_PLL_VCO_REG_EN_TX_HI_MASK, XCVR_TSM_TIMING01_PLL_VCO_REG_EN_TX_HI(value)))
38218 #define XCVR_BWR_TSM_TIMING01_PLL_VCO_REG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING01_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING01_PLL_VCO_REG_EN_TX_HI_SHIFT), XCVR_TSM_TIMING01_PLL_VCO_REG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING01_PLL_VCO_REG_EN_TX_HI_WIDTH))
38219 /*@}*/
38220 
38221 /*!
38222  * @name Register XCVR_TSM_TIMING01, field PLL_VCO_REG_EN_TX_LO[15:8] (RW)
38223  *
38224  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
38225  * at which the PLL_VCO_REG_EN signal or group will transition from HI to LO.
38226  */
38227 /*@{*/
38228 /*! @brief Read current value of the XCVR_TSM_TIMING01_PLL_VCO_REG_EN_TX_LO field. */
38229 #define XCVR_RD_TSM_TIMING01_PLL_VCO_REG_EN_TX_LO(base) ((XCVR_TSM_TIMING01_REG(base) & XCVR_TSM_TIMING01_PLL_VCO_REG_EN_TX_LO_MASK) >> XCVR_TSM_TIMING01_PLL_VCO_REG_EN_TX_LO_SHIFT)
38230 #define XCVR_BRD_TSM_TIMING01_PLL_VCO_REG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING01_REG(base), XCVR_TSM_TIMING01_PLL_VCO_REG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING01_PLL_VCO_REG_EN_TX_LO_WIDTH))
38231 
38232 /*! @brief Set the PLL_VCO_REG_EN_TX_LO field to a new value. */
38233 #define XCVR_WR_TSM_TIMING01_PLL_VCO_REG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING01(base, XCVR_TSM_TIMING01_PLL_VCO_REG_EN_TX_LO_MASK, XCVR_TSM_TIMING01_PLL_VCO_REG_EN_TX_LO(value)))
38234 #define XCVR_BWR_TSM_TIMING01_PLL_VCO_REG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING01_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING01_PLL_VCO_REG_EN_TX_LO_SHIFT), XCVR_TSM_TIMING01_PLL_VCO_REG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING01_PLL_VCO_REG_EN_TX_LO_WIDTH))
38235 /*@}*/
38236 
38237 /*!
38238  * @name Register XCVR_TSM_TIMING01, field PLL_VCO_REG_EN_RX_HI[23:16] (RW)
38239  *
38240  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
38241  * at which the PLL_VCO_REG_EN signal or group will transition from LO to HI.
38242  */
38243 /*@{*/
38244 /*! @brief Read current value of the XCVR_TSM_TIMING01_PLL_VCO_REG_EN_RX_HI field. */
38245 #define XCVR_RD_TSM_TIMING01_PLL_VCO_REG_EN_RX_HI(base) ((XCVR_TSM_TIMING01_REG(base) & XCVR_TSM_TIMING01_PLL_VCO_REG_EN_RX_HI_MASK) >> XCVR_TSM_TIMING01_PLL_VCO_REG_EN_RX_HI_SHIFT)
38246 #define XCVR_BRD_TSM_TIMING01_PLL_VCO_REG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING01_REG(base), XCVR_TSM_TIMING01_PLL_VCO_REG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING01_PLL_VCO_REG_EN_RX_HI_WIDTH))
38247 
38248 /*! @brief Set the PLL_VCO_REG_EN_RX_HI field to a new value. */
38249 #define XCVR_WR_TSM_TIMING01_PLL_VCO_REG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING01(base, XCVR_TSM_TIMING01_PLL_VCO_REG_EN_RX_HI_MASK, XCVR_TSM_TIMING01_PLL_VCO_REG_EN_RX_HI(value)))
38250 #define XCVR_BWR_TSM_TIMING01_PLL_VCO_REG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING01_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING01_PLL_VCO_REG_EN_RX_HI_SHIFT), XCVR_TSM_TIMING01_PLL_VCO_REG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING01_PLL_VCO_REG_EN_RX_HI_WIDTH))
38251 /*@}*/
38252 
38253 /*!
38254  * @name Register XCVR_TSM_TIMING01, field PLL_VCO_REG_EN_RX_LO[31:24] (RW)
38255  *
38256  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
38257  * at which the PLL_VCO_REG_EN signal or group will transition from HI to LO.
38258  */
38259 /*@{*/
38260 /*! @brief Read current value of the XCVR_TSM_TIMING01_PLL_VCO_REG_EN_RX_LO field. */
38261 #define XCVR_RD_TSM_TIMING01_PLL_VCO_REG_EN_RX_LO(base) ((XCVR_TSM_TIMING01_REG(base) & XCVR_TSM_TIMING01_PLL_VCO_REG_EN_RX_LO_MASK) >> XCVR_TSM_TIMING01_PLL_VCO_REG_EN_RX_LO_SHIFT)
38262 #define XCVR_BRD_TSM_TIMING01_PLL_VCO_REG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING01_REG(base), XCVR_TSM_TIMING01_PLL_VCO_REG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING01_PLL_VCO_REG_EN_RX_LO_WIDTH))
38263 
38264 /*! @brief Set the PLL_VCO_REG_EN_RX_LO field to a new value. */
38265 #define XCVR_WR_TSM_TIMING01_PLL_VCO_REG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING01(base, XCVR_TSM_TIMING01_PLL_VCO_REG_EN_RX_LO_MASK, XCVR_TSM_TIMING01_PLL_VCO_REG_EN_RX_LO(value)))
38266 #define XCVR_BWR_TSM_TIMING01_PLL_VCO_REG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING01_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING01_PLL_VCO_REG_EN_RX_LO_SHIFT), XCVR_TSM_TIMING01_PLL_VCO_REG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING01_PLL_VCO_REG_EN_RX_LO_WIDTH))
38267 /*@}*/
38268 
38269 /*******************************************************************************
38270  * XCVR_TSM_TIMING02 - TSM_TIMING02
38271  ******************************************************************************/
38272 
38273 /*!
38274  * @brief XCVR_TSM_TIMING02 - TSM_TIMING02 (RW)
38275  *
38276  * Reset value: 0x65006A00U
38277  *
38278  * This register contains the timing values to control the assertion and
38279  * deassertion times for both TX and RX sequences for the QGEN_REG_EN TSM signal or
38280  * signal group.
38281  */
38282 /*!
38283  * @name Constants and macros for entire XCVR_TSM_TIMING02 register
38284  */
38285 /*@{*/
38286 #define XCVR_RD_TSM_TIMING02(base) (XCVR_TSM_TIMING02_REG(base))
38287 #define XCVR_WR_TSM_TIMING02(base, value) (XCVR_TSM_TIMING02_REG(base) = (value))
38288 #define XCVR_RMW_TSM_TIMING02(base, mask, value) (XCVR_WR_TSM_TIMING02(base, (XCVR_RD_TSM_TIMING02(base) & ~(mask)) | (value)))
38289 #define XCVR_SET_TSM_TIMING02(base, value) (BME_OR32(&XCVR_TSM_TIMING02_REG(base), (uint32_t)(value)))
38290 #define XCVR_CLR_TSM_TIMING02(base, value) (BME_AND32(&XCVR_TSM_TIMING02_REG(base), (uint32_t)(~(value))))
38291 #define XCVR_TOG_TSM_TIMING02(base, value) (BME_XOR32(&XCVR_TSM_TIMING02_REG(base), (uint32_t)(value)))
38292 /*@}*/
38293 
38294 /*
38295  * Constants & macros for individual XCVR_TSM_TIMING02 bitfields
38296  */
38297 
38298 /*!
38299  * @name Register XCVR_TSM_TIMING02, field QGEN_REG_EN_TX_HI[7:0] (RW)
38300  *
38301  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
38302  * at which the QGEN_REG_EN signal or group will transition from LO to HI.
38303  */
38304 /*@{*/
38305 /*! @brief Read current value of the XCVR_TSM_TIMING02_QGEN_REG_EN_TX_HI field. */
38306 #define XCVR_RD_TSM_TIMING02_QGEN_REG_EN_TX_HI(base) ((XCVR_TSM_TIMING02_REG(base) & XCVR_TSM_TIMING02_QGEN_REG_EN_TX_HI_MASK) >> XCVR_TSM_TIMING02_QGEN_REG_EN_TX_HI_SHIFT)
38307 #define XCVR_BRD_TSM_TIMING02_QGEN_REG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING02_REG(base), XCVR_TSM_TIMING02_QGEN_REG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING02_QGEN_REG_EN_TX_HI_WIDTH))
38308 
38309 /*! @brief Set the QGEN_REG_EN_TX_HI field to a new value. */
38310 #define XCVR_WR_TSM_TIMING02_QGEN_REG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING02(base, XCVR_TSM_TIMING02_QGEN_REG_EN_TX_HI_MASK, XCVR_TSM_TIMING02_QGEN_REG_EN_TX_HI(value)))
38311 #define XCVR_BWR_TSM_TIMING02_QGEN_REG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING02_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING02_QGEN_REG_EN_TX_HI_SHIFT), XCVR_TSM_TIMING02_QGEN_REG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING02_QGEN_REG_EN_TX_HI_WIDTH))
38312 /*@}*/
38313 
38314 /*!
38315  * @name Register XCVR_TSM_TIMING02, field QGEN_REG_EN_TX_LO[15:8] (RW)
38316  *
38317  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
38318  * at which the QGEN_REG_EN signal or group will transition from HI to LO.
38319  */
38320 /*@{*/
38321 /*! @brief Read current value of the XCVR_TSM_TIMING02_QGEN_REG_EN_TX_LO field. */
38322 #define XCVR_RD_TSM_TIMING02_QGEN_REG_EN_TX_LO(base) ((XCVR_TSM_TIMING02_REG(base) & XCVR_TSM_TIMING02_QGEN_REG_EN_TX_LO_MASK) >> XCVR_TSM_TIMING02_QGEN_REG_EN_TX_LO_SHIFT)
38323 #define XCVR_BRD_TSM_TIMING02_QGEN_REG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING02_REG(base), XCVR_TSM_TIMING02_QGEN_REG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING02_QGEN_REG_EN_TX_LO_WIDTH))
38324 
38325 /*! @brief Set the QGEN_REG_EN_TX_LO field to a new value. */
38326 #define XCVR_WR_TSM_TIMING02_QGEN_REG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING02(base, XCVR_TSM_TIMING02_QGEN_REG_EN_TX_LO_MASK, XCVR_TSM_TIMING02_QGEN_REG_EN_TX_LO(value)))
38327 #define XCVR_BWR_TSM_TIMING02_QGEN_REG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING02_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING02_QGEN_REG_EN_TX_LO_SHIFT), XCVR_TSM_TIMING02_QGEN_REG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING02_QGEN_REG_EN_TX_LO_WIDTH))
38328 /*@}*/
38329 
38330 /*!
38331  * @name Register XCVR_TSM_TIMING02, field QGEN_REG_EN_RX_HI[23:16] (RW)
38332  *
38333  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
38334  * at which the QGEN_REG_EN signal or group will transition from LO to HI.
38335  */
38336 /*@{*/
38337 /*! @brief Read current value of the XCVR_TSM_TIMING02_QGEN_REG_EN_RX_HI field. */
38338 #define XCVR_RD_TSM_TIMING02_QGEN_REG_EN_RX_HI(base) ((XCVR_TSM_TIMING02_REG(base) & XCVR_TSM_TIMING02_QGEN_REG_EN_RX_HI_MASK) >> XCVR_TSM_TIMING02_QGEN_REG_EN_RX_HI_SHIFT)
38339 #define XCVR_BRD_TSM_TIMING02_QGEN_REG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING02_REG(base), XCVR_TSM_TIMING02_QGEN_REG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING02_QGEN_REG_EN_RX_HI_WIDTH))
38340 
38341 /*! @brief Set the QGEN_REG_EN_RX_HI field to a new value. */
38342 #define XCVR_WR_TSM_TIMING02_QGEN_REG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING02(base, XCVR_TSM_TIMING02_QGEN_REG_EN_RX_HI_MASK, XCVR_TSM_TIMING02_QGEN_REG_EN_RX_HI(value)))
38343 #define XCVR_BWR_TSM_TIMING02_QGEN_REG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING02_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING02_QGEN_REG_EN_RX_HI_SHIFT), XCVR_TSM_TIMING02_QGEN_REG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING02_QGEN_REG_EN_RX_HI_WIDTH))
38344 /*@}*/
38345 
38346 /*!
38347  * @name Register XCVR_TSM_TIMING02, field QGEN_REG_EN_RX_LO[31:24] (RW)
38348  *
38349  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
38350  * at which the QGEN_REG_EN signal or group will transition from HI to LO.
38351  */
38352 /*@{*/
38353 /*! @brief Read current value of the XCVR_TSM_TIMING02_QGEN_REG_EN_RX_LO field. */
38354 #define XCVR_RD_TSM_TIMING02_QGEN_REG_EN_RX_LO(base) ((XCVR_TSM_TIMING02_REG(base) & XCVR_TSM_TIMING02_QGEN_REG_EN_RX_LO_MASK) >> XCVR_TSM_TIMING02_QGEN_REG_EN_RX_LO_SHIFT)
38355 #define XCVR_BRD_TSM_TIMING02_QGEN_REG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING02_REG(base), XCVR_TSM_TIMING02_QGEN_REG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING02_QGEN_REG_EN_RX_LO_WIDTH))
38356 
38357 /*! @brief Set the QGEN_REG_EN_RX_LO field to a new value. */
38358 #define XCVR_WR_TSM_TIMING02_QGEN_REG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING02(base, XCVR_TSM_TIMING02_QGEN_REG_EN_RX_LO_MASK, XCVR_TSM_TIMING02_QGEN_REG_EN_RX_LO(value)))
38359 #define XCVR_BWR_TSM_TIMING02_QGEN_REG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING02_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING02_QGEN_REG_EN_RX_LO_SHIFT), XCVR_TSM_TIMING02_QGEN_REG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING02_QGEN_REG_EN_RX_LO_WIDTH))
38360 /*@}*/
38361 
38362 /*******************************************************************************
38363  * XCVR_TSM_TIMING03 - TSM_TIMING03
38364  ******************************************************************************/
38365 
38366 /*!
38367  * @brief XCVR_TSM_TIMING03 - TSM_TIMING03 (RW)
38368  *
38369  * Reset value: 0x65006A00U
38370  *
38371  * This register contains the timing values to control the assertion and
38372  * deassertion times for both TX and RX sequences for the TCA_TX_REG_EN TSM signal or
38373  * signal group.
38374  */
38375 /*!
38376  * @name Constants and macros for entire XCVR_TSM_TIMING03 register
38377  */
38378 /*@{*/
38379 #define XCVR_RD_TSM_TIMING03(base) (XCVR_TSM_TIMING03_REG(base))
38380 #define XCVR_WR_TSM_TIMING03(base, value) (XCVR_TSM_TIMING03_REG(base) = (value))
38381 #define XCVR_RMW_TSM_TIMING03(base, mask, value) (XCVR_WR_TSM_TIMING03(base, (XCVR_RD_TSM_TIMING03(base) & ~(mask)) | (value)))
38382 #define XCVR_SET_TSM_TIMING03(base, value) (BME_OR32(&XCVR_TSM_TIMING03_REG(base), (uint32_t)(value)))
38383 #define XCVR_CLR_TSM_TIMING03(base, value) (BME_AND32(&XCVR_TSM_TIMING03_REG(base), (uint32_t)(~(value))))
38384 #define XCVR_TOG_TSM_TIMING03(base, value) (BME_XOR32(&XCVR_TSM_TIMING03_REG(base), (uint32_t)(value)))
38385 /*@}*/
38386 
38387 /*
38388  * Constants & macros for individual XCVR_TSM_TIMING03 bitfields
38389  */
38390 
38391 /*!
38392  * @name Register XCVR_TSM_TIMING03, field TCA_TX_REG_EN_TX_HI[7:0] (RW)
38393  *
38394  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
38395  * at which the TCA_TX_REG_EN signal or group will transition from LO to HI.
38396  */
38397 /*@{*/
38398 /*! @brief Read current value of the XCVR_TSM_TIMING03_TCA_TX_REG_EN_TX_HI field. */
38399 #define XCVR_RD_TSM_TIMING03_TCA_TX_REG_EN_TX_HI(base) ((XCVR_TSM_TIMING03_REG(base) & XCVR_TSM_TIMING03_TCA_TX_REG_EN_TX_HI_MASK) >> XCVR_TSM_TIMING03_TCA_TX_REG_EN_TX_HI_SHIFT)
38400 #define XCVR_BRD_TSM_TIMING03_TCA_TX_REG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING03_REG(base), XCVR_TSM_TIMING03_TCA_TX_REG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING03_TCA_TX_REG_EN_TX_HI_WIDTH))
38401 
38402 /*! @brief Set the TCA_TX_REG_EN_TX_HI field to a new value. */
38403 #define XCVR_WR_TSM_TIMING03_TCA_TX_REG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING03(base, XCVR_TSM_TIMING03_TCA_TX_REG_EN_TX_HI_MASK, XCVR_TSM_TIMING03_TCA_TX_REG_EN_TX_HI(value)))
38404 #define XCVR_BWR_TSM_TIMING03_TCA_TX_REG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING03_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING03_TCA_TX_REG_EN_TX_HI_SHIFT), XCVR_TSM_TIMING03_TCA_TX_REG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING03_TCA_TX_REG_EN_TX_HI_WIDTH))
38405 /*@}*/
38406 
38407 /*!
38408  * @name Register XCVR_TSM_TIMING03, field TCA_TX_REG_EN_TX_LO[15:8] (RW)
38409  *
38410  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
38411  * at which the TCA_TX_REG_EN signal or group will transition from HI to LO.
38412  */
38413 /*@{*/
38414 /*! @brief Read current value of the XCVR_TSM_TIMING03_TCA_TX_REG_EN_TX_LO field. */
38415 #define XCVR_RD_TSM_TIMING03_TCA_TX_REG_EN_TX_LO(base) ((XCVR_TSM_TIMING03_REG(base) & XCVR_TSM_TIMING03_TCA_TX_REG_EN_TX_LO_MASK) >> XCVR_TSM_TIMING03_TCA_TX_REG_EN_TX_LO_SHIFT)
38416 #define XCVR_BRD_TSM_TIMING03_TCA_TX_REG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING03_REG(base), XCVR_TSM_TIMING03_TCA_TX_REG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING03_TCA_TX_REG_EN_TX_LO_WIDTH))
38417 
38418 /*! @brief Set the TCA_TX_REG_EN_TX_LO field to a new value. */
38419 #define XCVR_WR_TSM_TIMING03_TCA_TX_REG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING03(base, XCVR_TSM_TIMING03_TCA_TX_REG_EN_TX_LO_MASK, XCVR_TSM_TIMING03_TCA_TX_REG_EN_TX_LO(value)))
38420 #define XCVR_BWR_TSM_TIMING03_TCA_TX_REG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING03_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING03_TCA_TX_REG_EN_TX_LO_SHIFT), XCVR_TSM_TIMING03_TCA_TX_REG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING03_TCA_TX_REG_EN_TX_LO_WIDTH))
38421 /*@}*/
38422 
38423 /*!
38424  * @name Register XCVR_TSM_TIMING03, field TCA_TX_REG_EN_RX_HI[23:16] (RW)
38425  *
38426  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
38427  * at which the TCA_TX_REG_EN signal or group will transition from LO to HI.
38428  */
38429 /*@{*/
38430 /*! @brief Read current value of the XCVR_TSM_TIMING03_TCA_TX_REG_EN_RX_HI field. */
38431 #define XCVR_RD_TSM_TIMING03_TCA_TX_REG_EN_RX_HI(base) ((XCVR_TSM_TIMING03_REG(base) & XCVR_TSM_TIMING03_TCA_TX_REG_EN_RX_HI_MASK) >> XCVR_TSM_TIMING03_TCA_TX_REG_EN_RX_HI_SHIFT)
38432 #define XCVR_BRD_TSM_TIMING03_TCA_TX_REG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING03_REG(base), XCVR_TSM_TIMING03_TCA_TX_REG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING03_TCA_TX_REG_EN_RX_HI_WIDTH))
38433 
38434 /*! @brief Set the TCA_TX_REG_EN_RX_HI field to a new value. */
38435 #define XCVR_WR_TSM_TIMING03_TCA_TX_REG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING03(base, XCVR_TSM_TIMING03_TCA_TX_REG_EN_RX_HI_MASK, XCVR_TSM_TIMING03_TCA_TX_REG_EN_RX_HI(value)))
38436 #define XCVR_BWR_TSM_TIMING03_TCA_TX_REG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING03_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING03_TCA_TX_REG_EN_RX_HI_SHIFT), XCVR_TSM_TIMING03_TCA_TX_REG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING03_TCA_TX_REG_EN_RX_HI_WIDTH))
38437 /*@}*/
38438 
38439 /*!
38440  * @name Register XCVR_TSM_TIMING03, field TCA_TX_REG_EN_RX_LO[31:24] (RW)
38441  *
38442  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
38443  * at which the TCA_TX_REG_EN signal or group will transition from HI to LO.
38444  */
38445 /*@{*/
38446 /*! @brief Read current value of the XCVR_TSM_TIMING03_TCA_TX_REG_EN_RX_LO field. */
38447 #define XCVR_RD_TSM_TIMING03_TCA_TX_REG_EN_RX_LO(base) ((XCVR_TSM_TIMING03_REG(base) & XCVR_TSM_TIMING03_TCA_TX_REG_EN_RX_LO_MASK) >> XCVR_TSM_TIMING03_TCA_TX_REG_EN_RX_LO_SHIFT)
38448 #define XCVR_BRD_TSM_TIMING03_TCA_TX_REG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING03_REG(base), XCVR_TSM_TIMING03_TCA_TX_REG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING03_TCA_TX_REG_EN_RX_LO_WIDTH))
38449 
38450 /*! @brief Set the TCA_TX_REG_EN_RX_LO field to a new value. */
38451 #define XCVR_WR_TSM_TIMING03_TCA_TX_REG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING03(base, XCVR_TSM_TIMING03_TCA_TX_REG_EN_RX_LO_MASK, XCVR_TSM_TIMING03_TCA_TX_REG_EN_RX_LO(value)))
38452 #define XCVR_BWR_TSM_TIMING03_TCA_TX_REG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING03_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING03_TCA_TX_REG_EN_RX_LO_SHIFT), XCVR_TSM_TIMING03_TCA_TX_REG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING03_TCA_TX_REG_EN_RX_LO_WIDTH))
38453 /*@}*/
38454 
38455 /*******************************************************************************
38456  * XCVR_TSM_TIMING04 - TSM_TIMING04
38457  ******************************************************************************/
38458 
38459 /*!
38460  * @brief XCVR_TSM_TIMING04 - TSM_TIMING04 (RW)
38461  *
38462  * Reset value: 0x6500FFFFU
38463  *
38464  * This register contains the timing values to control the assertion and
38465  * deassertion times for both TX and RX sequences for the ADC_REG_EN TSM signal or
38466  * signal group.
38467  */
38468 /*!
38469  * @name Constants and macros for entire XCVR_TSM_TIMING04 register
38470  */
38471 /*@{*/
38472 #define XCVR_RD_TSM_TIMING04(base) (XCVR_TSM_TIMING04_REG(base))
38473 #define XCVR_WR_TSM_TIMING04(base, value) (XCVR_TSM_TIMING04_REG(base) = (value))
38474 #define XCVR_RMW_TSM_TIMING04(base, mask, value) (XCVR_WR_TSM_TIMING04(base, (XCVR_RD_TSM_TIMING04(base) & ~(mask)) | (value)))
38475 #define XCVR_SET_TSM_TIMING04(base, value) (BME_OR32(&XCVR_TSM_TIMING04_REG(base), (uint32_t)(value)))
38476 #define XCVR_CLR_TSM_TIMING04(base, value) (BME_AND32(&XCVR_TSM_TIMING04_REG(base), (uint32_t)(~(value))))
38477 #define XCVR_TOG_TSM_TIMING04(base, value) (BME_XOR32(&XCVR_TSM_TIMING04_REG(base), (uint32_t)(value)))
38478 /*@}*/
38479 
38480 /*
38481  * Constants & macros for individual XCVR_TSM_TIMING04 bitfields
38482  */
38483 
38484 /*!
38485  * @name Register XCVR_TSM_TIMING04, field ADC_REG_EN_RX_HI[23:16] (RW)
38486  *
38487  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
38488  * at which the ADC_REG_EN signal or group will transition from LO to HI.
38489  */
38490 /*@{*/
38491 /*! @brief Read current value of the XCVR_TSM_TIMING04_ADC_REG_EN_RX_HI field. */
38492 #define XCVR_RD_TSM_TIMING04_ADC_REG_EN_RX_HI(base) ((XCVR_TSM_TIMING04_REG(base) & XCVR_TSM_TIMING04_ADC_REG_EN_RX_HI_MASK) >> XCVR_TSM_TIMING04_ADC_REG_EN_RX_HI_SHIFT)
38493 #define XCVR_BRD_TSM_TIMING04_ADC_REG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING04_REG(base), XCVR_TSM_TIMING04_ADC_REG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING04_ADC_REG_EN_RX_HI_WIDTH))
38494 
38495 /*! @brief Set the ADC_REG_EN_RX_HI field to a new value. */
38496 #define XCVR_WR_TSM_TIMING04_ADC_REG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING04(base, XCVR_TSM_TIMING04_ADC_REG_EN_RX_HI_MASK, XCVR_TSM_TIMING04_ADC_REG_EN_RX_HI(value)))
38497 #define XCVR_BWR_TSM_TIMING04_ADC_REG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING04_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING04_ADC_REG_EN_RX_HI_SHIFT), XCVR_TSM_TIMING04_ADC_REG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING04_ADC_REG_EN_RX_HI_WIDTH))
38498 /*@}*/
38499 
38500 /*!
38501  * @name Register XCVR_TSM_TIMING04, field ADC_REG_EN_RX_LO[31:24] (RW)
38502  *
38503  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
38504  * at which the ADC_REG_EN signal or group will transition from HI to LO.
38505  */
38506 /*@{*/
38507 /*! @brief Read current value of the XCVR_TSM_TIMING04_ADC_REG_EN_RX_LO field. */
38508 #define XCVR_RD_TSM_TIMING04_ADC_REG_EN_RX_LO(base) ((XCVR_TSM_TIMING04_REG(base) & XCVR_TSM_TIMING04_ADC_REG_EN_RX_LO_MASK) >> XCVR_TSM_TIMING04_ADC_REG_EN_RX_LO_SHIFT)
38509 #define XCVR_BRD_TSM_TIMING04_ADC_REG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING04_REG(base), XCVR_TSM_TIMING04_ADC_REG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING04_ADC_REG_EN_RX_LO_WIDTH))
38510 
38511 /*! @brief Set the ADC_REG_EN_RX_LO field to a new value. */
38512 #define XCVR_WR_TSM_TIMING04_ADC_REG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING04(base, XCVR_TSM_TIMING04_ADC_REG_EN_RX_LO_MASK, XCVR_TSM_TIMING04_ADC_REG_EN_RX_LO(value)))
38513 #define XCVR_BWR_TSM_TIMING04_ADC_REG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING04_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING04_ADC_REG_EN_RX_LO_SHIFT), XCVR_TSM_TIMING04_ADC_REG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING04_ADC_REG_EN_RX_LO_WIDTH))
38514 /*@}*/
38515 
38516 /*******************************************************************************
38517  * XCVR_TSM_TIMING05 - TSM_TIMING05
38518  ******************************************************************************/
38519 
38520 /*!
38521  * @brief XCVR_TSM_TIMING05 - TSM_TIMING05 (RW)
38522  *
38523  * Reset value: 0x650B6A3FU
38524  *
38525  * This register contains the timing values to control the assertion and
38526  * deassertion times for both TX and RX sequences for the PLL_REF_CLK_EN TSM signal or
38527  * signal group.
38528  */
38529 /*!
38530  * @name Constants and macros for entire XCVR_TSM_TIMING05 register
38531  */
38532 /*@{*/
38533 #define XCVR_RD_TSM_TIMING05(base) (XCVR_TSM_TIMING05_REG(base))
38534 #define XCVR_WR_TSM_TIMING05(base, value) (XCVR_TSM_TIMING05_REG(base) = (value))
38535 #define XCVR_RMW_TSM_TIMING05(base, mask, value) (XCVR_WR_TSM_TIMING05(base, (XCVR_RD_TSM_TIMING05(base) & ~(mask)) | (value)))
38536 #define XCVR_SET_TSM_TIMING05(base, value) (BME_OR32(&XCVR_TSM_TIMING05_REG(base), (uint32_t)(value)))
38537 #define XCVR_CLR_TSM_TIMING05(base, value) (BME_AND32(&XCVR_TSM_TIMING05_REG(base), (uint32_t)(~(value))))
38538 #define XCVR_TOG_TSM_TIMING05(base, value) (BME_XOR32(&XCVR_TSM_TIMING05_REG(base), (uint32_t)(value)))
38539 /*@}*/
38540 
38541 /*
38542  * Constants & macros for individual XCVR_TSM_TIMING05 bitfields
38543  */
38544 
38545 /*!
38546  * @name Register XCVR_TSM_TIMING05, field PLL_REF_CLK_EN_TX_HI[7:0] (RW)
38547  *
38548  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
38549  * at which the PLL_REF_CLK_EN signal or group will transition from LO to HI.
38550  */
38551 /*@{*/
38552 /*! @brief Read current value of the XCVR_TSM_TIMING05_PLL_REF_CLK_EN_TX_HI field. */
38553 #define XCVR_RD_TSM_TIMING05_PLL_REF_CLK_EN_TX_HI(base) ((XCVR_TSM_TIMING05_REG(base) & XCVR_TSM_TIMING05_PLL_REF_CLK_EN_TX_HI_MASK) >> XCVR_TSM_TIMING05_PLL_REF_CLK_EN_TX_HI_SHIFT)
38554 #define XCVR_BRD_TSM_TIMING05_PLL_REF_CLK_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING05_REG(base), XCVR_TSM_TIMING05_PLL_REF_CLK_EN_TX_HI_SHIFT, XCVR_TSM_TIMING05_PLL_REF_CLK_EN_TX_HI_WIDTH))
38555 
38556 /*! @brief Set the PLL_REF_CLK_EN_TX_HI field to a new value. */
38557 #define XCVR_WR_TSM_TIMING05_PLL_REF_CLK_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING05(base, XCVR_TSM_TIMING05_PLL_REF_CLK_EN_TX_HI_MASK, XCVR_TSM_TIMING05_PLL_REF_CLK_EN_TX_HI(value)))
38558 #define XCVR_BWR_TSM_TIMING05_PLL_REF_CLK_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING05_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING05_PLL_REF_CLK_EN_TX_HI_SHIFT), XCVR_TSM_TIMING05_PLL_REF_CLK_EN_TX_HI_SHIFT, XCVR_TSM_TIMING05_PLL_REF_CLK_EN_TX_HI_WIDTH))
38559 /*@}*/
38560 
38561 /*!
38562  * @name Register XCVR_TSM_TIMING05, field PLL_REF_CLK_EN_TX_LO[15:8] (RW)
38563  *
38564  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
38565  * at which the PLL_REF_CLK_EN signal or group will transition from HI to LO.
38566  */
38567 /*@{*/
38568 /*! @brief Read current value of the XCVR_TSM_TIMING05_PLL_REF_CLK_EN_TX_LO field. */
38569 #define XCVR_RD_TSM_TIMING05_PLL_REF_CLK_EN_TX_LO(base) ((XCVR_TSM_TIMING05_REG(base) & XCVR_TSM_TIMING05_PLL_REF_CLK_EN_TX_LO_MASK) >> XCVR_TSM_TIMING05_PLL_REF_CLK_EN_TX_LO_SHIFT)
38570 #define XCVR_BRD_TSM_TIMING05_PLL_REF_CLK_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING05_REG(base), XCVR_TSM_TIMING05_PLL_REF_CLK_EN_TX_LO_SHIFT, XCVR_TSM_TIMING05_PLL_REF_CLK_EN_TX_LO_WIDTH))
38571 
38572 /*! @brief Set the PLL_REF_CLK_EN_TX_LO field to a new value. */
38573 #define XCVR_WR_TSM_TIMING05_PLL_REF_CLK_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING05(base, XCVR_TSM_TIMING05_PLL_REF_CLK_EN_TX_LO_MASK, XCVR_TSM_TIMING05_PLL_REF_CLK_EN_TX_LO(value)))
38574 #define XCVR_BWR_TSM_TIMING05_PLL_REF_CLK_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING05_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING05_PLL_REF_CLK_EN_TX_LO_SHIFT), XCVR_TSM_TIMING05_PLL_REF_CLK_EN_TX_LO_SHIFT, XCVR_TSM_TIMING05_PLL_REF_CLK_EN_TX_LO_WIDTH))
38575 /*@}*/
38576 
38577 /*!
38578  * @name Register XCVR_TSM_TIMING05, field PLL_REF_CLK_EN_RX_HI[23:16] (RW)
38579  *
38580  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
38581  * at which the PLL_REF_CLK_EN signal or group will transition from LO to HI.
38582  */
38583 /*@{*/
38584 /*! @brief Read current value of the XCVR_TSM_TIMING05_PLL_REF_CLK_EN_RX_HI field. */
38585 #define XCVR_RD_TSM_TIMING05_PLL_REF_CLK_EN_RX_HI(base) ((XCVR_TSM_TIMING05_REG(base) & XCVR_TSM_TIMING05_PLL_REF_CLK_EN_RX_HI_MASK) >> XCVR_TSM_TIMING05_PLL_REF_CLK_EN_RX_HI_SHIFT)
38586 #define XCVR_BRD_TSM_TIMING05_PLL_REF_CLK_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING05_REG(base), XCVR_TSM_TIMING05_PLL_REF_CLK_EN_RX_HI_SHIFT, XCVR_TSM_TIMING05_PLL_REF_CLK_EN_RX_HI_WIDTH))
38587 
38588 /*! @brief Set the PLL_REF_CLK_EN_RX_HI field to a new value. */
38589 #define XCVR_WR_TSM_TIMING05_PLL_REF_CLK_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING05(base, XCVR_TSM_TIMING05_PLL_REF_CLK_EN_RX_HI_MASK, XCVR_TSM_TIMING05_PLL_REF_CLK_EN_RX_HI(value)))
38590 #define XCVR_BWR_TSM_TIMING05_PLL_REF_CLK_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING05_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING05_PLL_REF_CLK_EN_RX_HI_SHIFT), XCVR_TSM_TIMING05_PLL_REF_CLK_EN_RX_HI_SHIFT, XCVR_TSM_TIMING05_PLL_REF_CLK_EN_RX_HI_WIDTH))
38591 /*@}*/
38592 
38593 /*!
38594  * @name Register XCVR_TSM_TIMING05, field PLL_REF_CLK_EN_RX_LO[31:24] (RW)
38595  *
38596  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
38597  * at which the PLL_REF_CLK_EN signal or group will transition from HI to LO.
38598  */
38599 /*@{*/
38600 /*! @brief Read current value of the XCVR_TSM_TIMING05_PLL_REF_CLK_EN_RX_LO field. */
38601 #define XCVR_RD_TSM_TIMING05_PLL_REF_CLK_EN_RX_LO(base) ((XCVR_TSM_TIMING05_REG(base) & XCVR_TSM_TIMING05_PLL_REF_CLK_EN_RX_LO_MASK) >> XCVR_TSM_TIMING05_PLL_REF_CLK_EN_RX_LO_SHIFT)
38602 #define XCVR_BRD_TSM_TIMING05_PLL_REF_CLK_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING05_REG(base), XCVR_TSM_TIMING05_PLL_REF_CLK_EN_RX_LO_SHIFT, XCVR_TSM_TIMING05_PLL_REF_CLK_EN_RX_LO_WIDTH))
38603 
38604 /*! @brief Set the PLL_REF_CLK_EN_RX_LO field to a new value. */
38605 #define XCVR_WR_TSM_TIMING05_PLL_REF_CLK_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING05(base, XCVR_TSM_TIMING05_PLL_REF_CLK_EN_RX_LO_MASK, XCVR_TSM_TIMING05_PLL_REF_CLK_EN_RX_LO(value)))
38606 #define XCVR_BWR_TSM_TIMING05_PLL_REF_CLK_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING05_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING05_PLL_REF_CLK_EN_RX_LO_SHIFT), XCVR_TSM_TIMING05_PLL_REF_CLK_EN_RX_LO_SHIFT, XCVR_TSM_TIMING05_PLL_REF_CLK_EN_RX_LO_WIDTH))
38607 /*@}*/
38608 
38609 /*******************************************************************************
38610  * XCVR_TSM_TIMING06 - TSM_TIMING06
38611  ******************************************************************************/
38612 
38613 /*!
38614  * @brief XCVR_TSM_TIMING06 - TSM_TIMING06 (RW)
38615  *
38616  * Reset value: 0x651AFFFFU
38617  *
38618  * This register contains the timing values to control the assertion and
38619  * deassertion times for both TX and RX sequences for the ADC_CLK_EN TSM signal or
38620  * signal group.
38621  */
38622 /*!
38623  * @name Constants and macros for entire XCVR_TSM_TIMING06 register
38624  */
38625 /*@{*/
38626 #define XCVR_RD_TSM_TIMING06(base) (XCVR_TSM_TIMING06_REG(base))
38627 #define XCVR_WR_TSM_TIMING06(base, value) (XCVR_TSM_TIMING06_REG(base) = (value))
38628 #define XCVR_RMW_TSM_TIMING06(base, mask, value) (XCVR_WR_TSM_TIMING06(base, (XCVR_RD_TSM_TIMING06(base) & ~(mask)) | (value)))
38629 #define XCVR_SET_TSM_TIMING06(base, value) (BME_OR32(&XCVR_TSM_TIMING06_REG(base), (uint32_t)(value)))
38630 #define XCVR_CLR_TSM_TIMING06(base, value) (BME_AND32(&XCVR_TSM_TIMING06_REG(base), (uint32_t)(~(value))))
38631 #define XCVR_TOG_TSM_TIMING06(base, value) (BME_XOR32(&XCVR_TSM_TIMING06_REG(base), (uint32_t)(value)))
38632 /*@}*/
38633 
38634 /*
38635  * Constants & macros for individual XCVR_TSM_TIMING06 bitfields
38636  */
38637 
38638 /*!
38639  * @name Register XCVR_TSM_TIMING06, field ADC_CLK_EN_RX_HI[23:16] (RW)
38640  *
38641  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
38642  * at which the ADC_CLK_EN signal or group will transition from LO to HI.
38643  */
38644 /*@{*/
38645 /*! @brief Read current value of the XCVR_TSM_TIMING06_ADC_CLK_EN_RX_HI field. */
38646 #define XCVR_RD_TSM_TIMING06_ADC_CLK_EN_RX_HI(base) ((XCVR_TSM_TIMING06_REG(base) & XCVR_TSM_TIMING06_ADC_CLK_EN_RX_HI_MASK) >> XCVR_TSM_TIMING06_ADC_CLK_EN_RX_HI_SHIFT)
38647 #define XCVR_BRD_TSM_TIMING06_ADC_CLK_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING06_REG(base), XCVR_TSM_TIMING06_ADC_CLK_EN_RX_HI_SHIFT, XCVR_TSM_TIMING06_ADC_CLK_EN_RX_HI_WIDTH))
38648 
38649 /*! @brief Set the ADC_CLK_EN_RX_HI field to a new value. */
38650 #define XCVR_WR_TSM_TIMING06_ADC_CLK_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING06(base, XCVR_TSM_TIMING06_ADC_CLK_EN_RX_HI_MASK, XCVR_TSM_TIMING06_ADC_CLK_EN_RX_HI(value)))
38651 #define XCVR_BWR_TSM_TIMING06_ADC_CLK_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING06_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING06_ADC_CLK_EN_RX_HI_SHIFT), XCVR_TSM_TIMING06_ADC_CLK_EN_RX_HI_SHIFT, XCVR_TSM_TIMING06_ADC_CLK_EN_RX_HI_WIDTH))
38652 /*@}*/
38653 
38654 /*!
38655  * @name Register XCVR_TSM_TIMING06, field ADC_CLK_EN_RX_LO[31:24] (RW)
38656  *
38657  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
38658  * at which the ADC_CLK_EN signal or group will transition from HI to LO.
38659  */
38660 /*@{*/
38661 /*! @brief Read current value of the XCVR_TSM_TIMING06_ADC_CLK_EN_RX_LO field. */
38662 #define XCVR_RD_TSM_TIMING06_ADC_CLK_EN_RX_LO(base) ((XCVR_TSM_TIMING06_REG(base) & XCVR_TSM_TIMING06_ADC_CLK_EN_RX_LO_MASK) >> XCVR_TSM_TIMING06_ADC_CLK_EN_RX_LO_SHIFT)
38663 #define XCVR_BRD_TSM_TIMING06_ADC_CLK_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING06_REG(base), XCVR_TSM_TIMING06_ADC_CLK_EN_RX_LO_SHIFT, XCVR_TSM_TIMING06_ADC_CLK_EN_RX_LO_WIDTH))
38664 
38665 /*! @brief Set the ADC_CLK_EN_RX_LO field to a new value. */
38666 #define XCVR_WR_TSM_TIMING06_ADC_CLK_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING06(base, XCVR_TSM_TIMING06_ADC_CLK_EN_RX_LO_MASK, XCVR_TSM_TIMING06_ADC_CLK_EN_RX_LO(value)))
38667 #define XCVR_BWR_TSM_TIMING06_ADC_CLK_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING06_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING06_ADC_CLK_EN_RX_LO_SHIFT), XCVR_TSM_TIMING06_ADC_CLK_EN_RX_LO_SHIFT, XCVR_TSM_TIMING06_ADC_CLK_EN_RX_LO_WIDTH))
38668 /*@}*/
38669 
38670 /*******************************************************************************
38671  * XCVR_TSM_TIMING07 - TSM_TIMING07
38672  ******************************************************************************/
38673 
38674 /*!
38675  * @brief XCVR_TSM_TIMING07 - TSM_TIMING07 (RW)
38676  *
38677  * Reset value: 0x1A004E00U
38678  *
38679  * This register contains the timing values to control the assertion and
38680  * deassertion times for both TX and RX sequences for the PLL_VCO_AUTOTUNE_EN TSM signal
38681  * or signal group.
38682  */
38683 /*!
38684  * @name Constants and macros for entire XCVR_TSM_TIMING07 register
38685  */
38686 /*@{*/
38687 #define XCVR_RD_TSM_TIMING07(base) (XCVR_TSM_TIMING07_REG(base))
38688 #define XCVR_WR_TSM_TIMING07(base, value) (XCVR_TSM_TIMING07_REG(base) = (value))
38689 #define XCVR_RMW_TSM_TIMING07(base, mask, value) (XCVR_WR_TSM_TIMING07(base, (XCVR_RD_TSM_TIMING07(base) & ~(mask)) | (value)))
38690 #define XCVR_SET_TSM_TIMING07(base, value) (BME_OR32(&XCVR_TSM_TIMING07_REG(base), (uint32_t)(value)))
38691 #define XCVR_CLR_TSM_TIMING07(base, value) (BME_AND32(&XCVR_TSM_TIMING07_REG(base), (uint32_t)(~(value))))
38692 #define XCVR_TOG_TSM_TIMING07(base, value) (BME_XOR32(&XCVR_TSM_TIMING07_REG(base), (uint32_t)(value)))
38693 /*@}*/
38694 
38695 /*
38696  * Constants & macros for individual XCVR_TSM_TIMING07 bitfields
38697  */
38698 
38699 /*!
38700  * @name Register XCVR_TSM_TIMING07, field PLL_VCO_AUTOTUNE_EN_TX_HI[7:0] (RW)
38701  *
38702  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
38703  * at which the PLL_VCO_AUTOTUNE_EN signal or group will transition from LO to
38704  * HI.
38705  */
38706 /*@{*/
38707 /*! @brief Read current value of the XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_HI field. */
38708 #define XCVR_RD_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_HI(base) ((XCVR_TSM_TIMING07_REG(base) & XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_HI_MASK) >> XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_HI_SHIFT)
38709 #define XCVR_BRD_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING07_REG(base), XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_HI_SHIFT, XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_HI_WIDTH))
38710 
38711 /*! @brief Set the PLL_VCO_AUTOTUNE_EN_TX_HI field to a new value. */
38712 #define XCVR_WR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING07(base, XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_HI_MASK, XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_HI(value)))
38713 #define XCVR_BWR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING07_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_HI_SHIFT), XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_HI_SHIFT, XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_HI_WIDTH))
38714 /*@}*/
38715 
38716 /*!
38717  * @name Register XCVR_TSM_TIMING07, field PLL_VCO_AUTOTUNE_EN_TX_LO[15:8] (RW)
38718  *
38719  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
38720  * at which the PLL_VCO_AUTOTUNE_EN signal or group will transition from HI to
38721  * LO.
38722  */
38723 /*@{*/
38724 /*! @brief Read current value of the XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_LO field. */
38725 #define XCVR_RD_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_LO(base) ((XCVR_TSM_TIMING07_REG(base) & XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_LO_MASK) >> XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_LO_SHIFT)
38726 #define XCVR_BRD_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING07_REG(base), XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_LO_SHIFT, XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_LO_WIDTH))
38727 
38728 /*! @brief Set the PLL_VCO_AUTOTUNE_EN_TX_LO field to a new value. */
38729 #define XCVR_WR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING07(base, XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_LO_MASK, XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_LO(value)))
38730 #define XCVR_BWR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING07_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_LO_SHIFT), XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_LO_SHIFT, XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_TX_LO_WIDTH))
38731 /*@}*/
38732 
38733 /*!
38734  * @name Register XCVR_TSM_TIMING07, field PLL_VCO_AUTOTUNE_EN_RX_HI[23:16] (RW)
38735  *
38736  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
38737  * at which the PLL_VCO_AUTOTUNE_EN signal or group will transition from LO to
38738  * HI.
38739  */
38740 /*@{*/
38741 /*! @brief Read current value of the XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_HI field. */
38742 #define XCVR_RD_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_HI(base) ((XCVR_TSM_TIMING07_REG(base) & XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_HI_MASK) >> XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_HI_SHIFT)
38743 #define XCVR_BRD_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING07_REG(base), XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_HI_SHIFT, XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_HI_WIDTH))
38744 
38745 /*! @brief Set the PLL_VCO_AUTOTUNE_EN_RX_HI field to a new value. */
38746 #define XCVR_WR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING07(base, XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_HI_MASK, XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_HI(value)))
38747 #define XCVR_BWR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING07_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_HI_SHIFT), XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_HI_SHIFT, XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_HI_WIDTH))
38748 /*@}*/
38749 
38750 /*!
38751  * @name Register XCVR_TSM_TIMING07, field PLL_VCO_AUTOTUNE_EN_RX_LO[31:24] (RW)
38752  *
38753  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
38754  * at which the PLL_VCO_AUTOTUNE_EN signal or group will transition from HI to
38755  * LO.
38756  */
38757 /*@{*/
38758 /*! @brief Read current value of the XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_LO field. */
38759 #define XCVR_RD_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_LO(base) ((XCVR_TSM_TIMING07_REG(base) & XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_LO_MASK) >> XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_LO_SHIFT)
38760 #define XCVR_BRD_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING07_REG(base), XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_LO_SHIFT, XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_LO_WIDTH))
38761 
38762 /*! @brief Set the PLL_VCO_AUTOTUNE_EN_RX_LO field to a new value. */
38763 #define XCVR_WR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING07(base, XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_LO_MASK, XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_LO(value)))
38764 #define XCVR_BWR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING07_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_LO_SHIFT), XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_LO_SHIFT, XCVR_TSM_TIMING07_PLL_VCO_AUTOTUNE_EN_RX_LO_WIDTH))
38765 /*@}*/
38766 
38767 /*******************************************************************************
38768  * XCVR_TSM_TIMING08 - TSM_TIMING08
38769  ******************************************************************************/
38770 
38771 /*!
38772  * @brief XCVR_TSM_TIMING08 - TSM_TIMING08 (RW)
38773  *
38774  * Reset value: 0x65336867U
38775  *
38776  * This register contains the timing values to control the assertion and
38777  * deassertion times for both TX and RX sequences for the PLL_CYCLE_SLIP_LD_EN TSM
38778  * signal or signal group.
38779  */
38780 /*!
38781  * @name Constants and macros for entire XCVR_TSM_TIMING08 register
38782  */
38783 /*@{*/
38784 #define XCVR_RD_TSM_TIMING08(base) (XCVR_TSM_TIMING08_REG(base))
38785 #define XCVR_WR_TSM_TIMING08(base, value) (XCVR_TSM_TIMING08_REG(base) = (value))
38786 #define XCVR_RMW_TSM_TIMING08(base, mask, value) (XCVR_WR_TSM_TIMING08(base, (XCVR_RD_TSM_TIMING08(base) & ~(mask)) | (value)))
38787 #define XCVR_SET_TSM_TIMING08(base, value) (BME_OR32(&XCVR_TSM_TIMING08_REG(base), (uint32_t)(value)))
38788 #define XCVR_CLR_TSM_TIMING08(base, value) (BME_AND32(&XCVR_TSM_TIMING08_REG(base), (uint32_t)(~(value))))
38789 #define XCVR_TOG_TSM_TIMING08(base, value) (BME_XOR32(&XCVR_TSM_TIMING08_REG(base), (uint32_t)(value)))
38790 /*@}*/
38791 
38792 /*
38793  * Constants & macros for individual XCVR_TSM_TIMING08 bitfields
38794  */
38795 
38796 /*!
38797  * @name Register XCVR_TSM_TIMING08, field PLL_CYCLE_SLIP_LD_EN_TX_HI[7:0] (RW)
38798  *
38799  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
38800  * at which the PLL_CYCLE_SLIP_LD_EN signal or group will transition from LO to
38801  * HI.
38802  */
38803 /*@{*/
38804 /*! @brief Read current value of the XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_HI field. */
38805 #define XCVR_RD_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_HI(base) ((XCVR_TSM_TIMING08_REG(base) & XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_HI_MASK) >> XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_HI_SHIFT)
38806 #define XCVR_BRD_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING08_REG(base), XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_HI_SHIFT, XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_HI_WIDTH))
38807 
38808 /*! @brief Set the PLL_CYCLE_SLIP_LD_EN_TX_HI field to a new value. */
38809 #define XCVR_WR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING08(base, XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_HI_MASK, XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_HI(value)))
38810 #define XCVR_BWR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING08_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_HI_SHIFT), XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_HI_SHIFT, XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_HI_WIDTH))
38811 /*@}*/
38812 
38813 /*!
38814  * @name Register XCVR_TSM_TIMING08, field PLL_CYCLE_SLIP_LD_EN_TX_LO[15:8] (RW)
38815  *
38816  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
38817  * at which the PLL_CYCLE_SLIP_LD_EN signal or group will transition from HI to
38818  * LO.
38819  */
38820 /*@{*/
38821 /*! @brief Read current value of the XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_LO field. */
38822 #define XCVR_RD_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_LO(base) ((XCVR_TSM_TIMING08_REG(base) & XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_LO_MASK) >> XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_LO_SHIFT)
38823 #define XCVR_BRD_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING08_REG(base), XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_LO_SHIFT, XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_LO_WIDTH))
38824 
38825 /*! @brief Set the PLL_CYCLE_SLIP_LD_EN_TX_LO field to a new value. */
38826 #define XCVR_WR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING08(base, XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_LO_MASK, XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_LO(value)))
38827 #define XCVR_BWR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING08_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_LO_SHIFT), XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_LO_SHIFT, XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_TX_LO_WIDTH))
38828 /*@}*/
38829 
38830 /*!
38831  * @name Register XCVR_TSM_TIMING08, field PLL_CYCLE_SLIP_LD_EN_RX_HI[23:16] (RW)
38832  *
38833  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
38834  * at which the PLL_CYCLE_SLIP_LD_EN signal or group will transition from LO to
38835  * HI.
38836  */
38837 /*@{*/
38838 /*! @brief Read current value of the XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_HI field. */
38839 #define XCVR_RD_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_HI(base) ((XCVR_TSM_TIMING08_REG(base) & XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_HI_MASK) >> XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_HI_SHIFT)
38840 #define XCVR_BRD_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING08_REG(base), XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_HI_SHIFT, XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_HI_WIDTH))
38841 
38842 /*! @brief Set the PLL_CYCLE_SLIP_LD_EN_RX_HI field to a new value. */
38843 #define XCVR_WR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING08(base, XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_HI_MASK, XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_HI(value)))
38844 #define XCVR_BWR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING08_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_HI_SHIFT), XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_HI_SHIFT, XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_HI_WIDTH))
38845 /*@}*/
38846 
38847 /*!
38848  * @name Register XCVR_TSM_TIMING08, field PLL_CYCLE_SLIP_LD_EN_RX_LO[31:24] (RW)
38849  *
38850  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
38851  * at which the PLL_CYCLE_SLIP_LD_EN signal or group will transition from HI to
38852  * LO.
38853  */
38854 /*@{*/
38855 /*! @brief Read current value of the XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_LO field. */
38856 #define XCVR_RD_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_LO(base) ((XCVR_TSM_TIMING08_REG(base) & XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_LO_MASK) >> XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_LO_SHIFT)
38857 #define XCVR_BRD_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING08_REG(base), XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_LO_SHIFT, XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_LO_WIDTH))
38858 
38859 /*! @brief Set the PLL_CYCLE_SLIP_LD_EN_RX_LO field to a new value. */
38860 #define XCVR_WR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING08(base, XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_LO_MASK, XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_LO(value)))
38861 #define XCVR_BWR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING08_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_LO_SHIFT), XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_LO_SHIFT, XCVR_TSM_TIMING08_PLL_CYCLE_SLIP_LD_EN_RX_LO_WIDTH))
38862 /*@}*/
38863 
38864 /*******************************************************************************
38865  * XCVR_TSM_TIMING09 - TSM_TIMING09
38866  ******************************************************************************/
38867 
38868 /*!
38869  * @brief XCVR_TSM_TIMING09 - TSM_TIMING09 (RW)
38870  *
38871  * Reset value: 0x65056A05U
38872  *
38873  * This register contains the timing values to control the assertion and
38874  * deassertion times for both TX and RX sequences for the PLL_VCO_EN TSM signal or
38875  * signal group.
38876  */
38877 /*!
38878  * @name Constants and macros for entire XCVR_TSM_TIMING09 register
38879  */
38880 /*@{*/
38881 #define XCVR_RD_TSM_TIMING09(base) (XCVR_TSM_TIMING09_REG(base))
38882 #define XCVR_WR_TSM_TIMING09(base, value) (XCVR_TSM_TIMING09_REG(base) = (value))
38883 #define XCVR_RMW_TSM_TIMING09(base, mask, value) (XCVR_WR_TSM_TIMING09(base, (XCVR_RD_TSM_TIMING09(base) & ~(mask)) | (value)))
38884 #define XCVR_SET_TSM_TIMING09(base, value) (BME_OR32(&XCVR_TSM_TIMING09_REG(base), (uint32_t)(value)))
38885 #define XCVR_CLR_TSM_TIMING09(base, value) (BME_AND32(&XCVR_TSM_TIMING09_REG(base), (uint32_t)(~(value))))
38886 #define XCVR_TOG_TSM_TIMING09(base, value) (BME_XOR32(&XCVR_TSM_TIMING09_REG(base), (uint32_t)(value)))
38887 /*@}*/
38888 
38889 /*
38890  * Constants & macros for individual XCVR_TSM_TIMING09 bitfields
38891  */
38892 
38893 /*!
38894  * @name Register XCVR_TSM_TIMING09, field PLL_VCO_EN_TX_HI[7:0] (RW)
38895  *
38896  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
38897  * at which the PLL_VCO_EN signal or group will transition from LO to HI.
38898  */
38899 /*@{*/
38900 /*! @brief Read current value of the XCVR_TSM_TIMING09_PLL_VCO_EN_TX_HI field. */
38901 #define XCVR_RD_TSM_TIMING09_PLL_VCO_EN_TX_HI(base) ((XCVR_TSM_TIMING09_REG(base) & XCVR_TSM_TIMING09_PLL_VCO_EN_TX_HI_MASK) >> XCVR_TSM_TIMING09_PLL_VCO_EN_TX_HI_SHIFT)
38902 #define XCVR_BRD_TSM_TIMING09_PLL_VCO_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING09_REG(base), XCVR_TSM_TIMING09_PLL_VCO_EN_TX_HI_SHIFT, XCVR_TSM_TIMING09_PLL_VCO_EN_TX_HI_WIDTH))
38903 
38904 /*! @brief Set the PLL_VCO_EN_TX_HI field to a new value. */
38905 #define XCVR_WR_TSM_TIMING09_PLL_VCO_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING09(base, XCVR_TSM_TIMING09_PLL_VCO_EN_TX_HI_MASK, XCVR_TSM_TIMING09_PLL_VCO_EN_TX_HI(value)))
38906 #define XCVR_BWR_TSM_TIMING09_PLL_VCO_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING09_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING09_PLL_VCO_EN_TX_HI_SHIFT), XCVR_TSM_TIMING09_PLL_VCO_EN_TX_HI_SHIFT, XCVR_TSM_TIMING09_PLL_VCO_EN_TX_HI_WIDTH))
38907 /*@}*/
38908 
38909 /*!
38910  * @name Register XCVR_TSM_TIMING09, field PLL_VCO_EN_TX_LO[15:8] (RW)
38911  *
38912  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
38913  * at which the PLL_VCO_EN signal or group will transition from HI to LO.
38914  */
38915 /*@{*/
38916 /*! @brief Read current value of the XCVR_TSM_TIMING09_PLL_VCO_EN_TX_LO field. */
38917 #define XCVR_RD_TSM_TIMING09_PLL_VCO_EN_TX_LO(base) ((XCVR_TSM_TIMING09_REG(base) & XCVR_TSM_TIMING09_PLL_VCO_EN_TX_LO_MASK) >> XCVR_TSM_TIMING09_PLL_VCO_EN_TX_LO_SHIFT)
38918 #define XCVR_BRD_TSM_TIMING09_PLL_VCO_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING09_REG(base), XCVR_TSM_TIMING09_PLL_VCO_EN_TX_LO_SHIFT, XCVR_TSM_TIMING09_PLL_VCO_EN_TX_LO_WIDTH))
38919 
38920 /*! @brief Set the PLL_VCO_EN_TX_LO field to a new value. */
38921 #define XCVR_WR_TSM_TIMING09_PLL_VCO_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING09(base, XCVR_TSM_TIMING09_PLL_VCO_EN_TX_LO_MASK, XCVR_TSM_TIMING09_PLL_VCO_EN_TX_LO(value)))
38922 #define XCVR_BWR_TSM_TIMING09_PLL_VCO_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING09_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING09_PLL_VCO_EN_TX_LO_SHIFT), XCVR_TSM_TIMING09_PLL_VCO_EN_TX_LO_SHIFT, XCVR_TSM_TIMING09_PLL_VCO_EN_TX_LO_WIDTH))
38923 /*@}*/
38924 
38925 /*!
38926  * @name Register XCVR_TSM_TIMING09, field PLL_VCO_EN_RX_HI[23:16] (RW)
38927  *
38928  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
38929  * at which the PLL_VCO_EN signal or group will transition from LO to HI.
38930  */
38931 /*@{*/
38932 /*! @brief Read current value of the XCVR_TSM_TIMING09_PLL_VCO_EN_RX_HI field. */
38933 #define XCVR_RD_TSM_TIMING09_PLL_VCO_EN_RX_HI(base) ((XCVR_TSM_TIMING09_REG(base) & XCVR_TSM_TIMING09_PLL_VCO_EN_RX_HI_MASK) >> XCVR_TSM_TIMING09_PLL_VCO_EN_RX_HI_SHIFT)
38934 #define XCVR_BRD_TSM_TIMING09_PLL_VCO_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING09_REG(base), XCVR_TSM_TIMING09_PLL_VCO_EN_RX_HI_SHIFT, XCVR_TSM_TIMING09_PLL_VCO_EN_RX_HI_WIDTH))
38935 
38936 /*! @brief Set the PLL_VCO_EN_RX_HI field to a new value. */
38937 #define XCVR_WR_TSM_TIMING09_PLL_VCO_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING09(base, XCVR_TSM_TIMING09_PLL_VCO_EN_RX_HI_MASK, XCVR_TSM_TIMING09_PLL_VCO_EN_RX_HI(value)))
38938 #define XCVR_BWR_TSM_TIMING09_PLL_VCO_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING09_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING09_PLL_VCO_EN_RX_HI_SHIFT), XCVR_TSM_TIMING09_PLL_VCO_EN_RX_HI_SHIFT, XCVR_TSM_TIMING09_PLL_VCO_EN_RX_HI_WIDTH))
38939 /*@}*/
38940 
38941 /*!
38942  * @name Register XCVR_TSM_TIMING09, field PLL_VCO_EN_RX_LO[31:24] (RW)
38943  *
38944  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
38945  * at which the PLL_VCO_EN signal or group will transition from HI to LO.
38946  */
38947 /*@{*/
38948 /*! @brief Read current value of the XCVR_TSM_TIMING09_PLL_VCO_EN_RX_LO field. */
38949 #define XCVR_RD_TSM_TIMING09_PLL_VCO_EN_RX_LO(base) ((XCVR_TSM_TIMING09_REG(base) & XCVR_TSM_TIMING09_PLL_VCO_EN_RX_LO_MASK) >> XCVR_TSM_TIMING09_PLL_VCO_EN_RX_LO_SHIFT)
38950 #define XCVR_BRD_TSM_TIMING09_PLL_VCO_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING09_REG(base), XCVR_TSM_TIMING09_PLL_VCO_EN_RX_LO_SHIFT, XCVR_TSM_TIMING09_PLL_VCO_EN_RX_LO_WIDTH))
38951 
38952 /*! @brief Set the PLL_VCO_EN_RX_LO field to a new value. */
38953 #define XCVR_WR_TSM_TIMING09_PLL_VCO_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING09(base, XCVR_TSM_TIMING09_PLL_VCO_EN_RX_LO_MASK, XCVR_TSM_TIMING09_PLL_VCO_EN_RX_LO(value)))
38954 #define XCVR_BWR_TSM_TIMING09_PLL_VCO_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING09_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING09_PLL_VCO_EN_RX_LO_SHIFT), XCVR_TSM_TIMING09_PLL_VCO_EN_RX_LO_SHIFT, XCVR_TSM_TIMING09_PLL_VCO_EN_RX_LO_WIDTH))
38955 /*@}*/
38956 
38957 /*******************************************************************************
38958  * XCVR_TSM_TIMING10 - TSM_TIMING10
38959  ******************************************************************************/
38960 
38961 /*!
38962  * @brief XCVR_TSM_TIMING10 - TSM_TIMING10 (RW)
38963  *
38964  * Reset value: 0x6509FFFFU
38965  *
38966  * This register contains the timing values to control the assertion and
38967  * deassertion times for both TX and RX sequences for the PLL_VCO_BUF_RX_EN TSM signal
38968  * or signal group.
38969  */
38970 /*!
38971  * @name Constants and macros for entire XCVR_TSM_TIMING10 register
38972  */
38973 /*@{*/
38974 #define XCVR_RD_TSM_TIMING10(base) (XCVR_TSM_TIMING10_REG(base))
38975 #define XCVR_WR_TSM_TIMING10(base, value) (XCVR_TSM_TIMING10_REG(base) = (value))
38976 #define XCVR_RMW_TSM_TIMING10(base, mask, value) (XCVR_WR_TSM_TIMING10(base, (XCVR_RD_TSM_TIMING10(base) & ~(mask)) | (value)))
38977 #define XCVR_SET_TSM_TIMING10(base, value) (BME_OR32(&XCVR_TSM_TIMING10_REG(base), (uint32_t)(value)))
38978 #define XCVR_CLR_TSM_TIMING10(base, value) (BME_AND32(&XCVR_TSM_TIMING10_REG(base), (uint32_t)(~(value))))
38979 #define XCVR_TOG_TSM_TIMING10(base, value) (BME_XOR32(&XCVR_TSM_TIMING10_REG(base), (uint32_t)(value)))
38980 /*@}*/
38981 
38982 /*
38983  * Constants & macros for individual XCVR_TSM_TIMING10 bitfields
38984  */
38985 
38986 /*!
38987  * @name Register XCVR_TSM_TIMING10, field PLL_VCO_BUF_RX_EN_RX_HI[23:16] (RW)
38988  *
38989  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
38990  * at which the PLL_VCO_BUF_RX_EN signal or group will transition from LO to HI.
38991  */
38992 /*@{*/
38993 /*! @brief Read current value of the XCVR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_HI field. */
38994 #define XCVR_RD_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_HI(base) ((XCVR_TSM_TIMING10_REG(base) & XCVR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_HI_MASK) >> XCVR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_HI_SHIFT)
38995 #define XCVR_BRD_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING10_REG(base), XCVR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_HI_SHIFT, XCVR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_HI_WIDTH))
38996 
38997 /*! @brief Set the PLL_VCO_BUF_RX_EN_RX_HI field to a new value. */
38998 #define XCVR_WR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING10(base, XCVR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_HI_MASK, XCVR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_HI(value)))
38999 #define XCVR_BWR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING10_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_HI_SHIFT), XCVR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_HI_SHIFT, XCVR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_HI_WIDTH))
39000 /*@}*/
39001 
39002 /*!
39003  * @name Register XCVR_TSM_TIMING10, field PLL_VCO_BUF_RX_EN_RX_LO[31:24] (RW)
39004  *
39005  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
39006  * at which the PLL_VCO_BUF_RX_EN signal or group will transition from HI to LO.
39007  */
39008 /*@{*/
39009 /*! @brief Read current value of the XCVR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_LO field. */
39010 #define XCVR_RD_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_LO(base) ((XCVR_TSM_TIMING10_REG(base) & XCVR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_LO_MASK) >> XCVR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_LO_SHIFT)
39011 #define XCVR_BRD_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING10_REG(base), XCVR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_LO_SHIFT, XCVR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_LO_WIDTH))
39012 
39013 /*! @brief Set the PLL_VCO_BUF_RX_EN_RX_LO field to a new value. */
39014 #define XCVR_WR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING10(base, XCVR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_LO_MASK, XCVR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_LO(value)))
39015 #define XCVR_BWR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING10_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_LO_SHIFT), XCVR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_LO_SHIFT, XCVR_TSM_TIMING10_PLL_VCO_BUF_RX_EN_RX_LO_WIDTH))
39016 /*@}*/
39017 
39018 /*******************************************************************************
39019  * XCVR_TSM_TIMING11 - TSM_TIMING11
39020  ******************************************************************************/
39021 
39022 /*!
39023  * @brief XCVR_TSM_TIMING11 - TSM_TIMING11 (RW)
39024  *
39025  * Reset value: 0xFFFF6A09U
39026  *
39027  * This register contains the timing values to control the assertion and
39028  * deassertion times for both TX and RX sequences for the PLL_VCO_BUF_TX_EN TSM signal
39029  * or signal group.
39030  */
39031 /*!
39032  * @name Constants and macros for entire XCVR_TSM_TIMING11 register
39033  */
39034 /*@{*/
39035 #define XCVR_RD_TSM_TIMING11(base) (XCVR_TSM_TIMING11_REG(base))
39036 #define XCVR_WR_TSM_TIMING11(base, value) (XCVR_TSM_TIMING11_REG(base) = (value))
39037 #define XCVR_RMW_TSM_TIMING11(base, mask, value) (XCVR_WR_TSM_TIMING11(base, (XCVR_RD_TSM_TIMING11(base) & ~(mask)) | (value)))
39038 #define XCVR_SET_TSM_TIMING11(base, value) (BME_OR32(&XCVR_TSM_TIMING11_REG(base), (uint32_t)(value)))
39039 #define XCVR_CLR_TSM_TIMING11(base, value) (BME_AND32(&XCVR_TSM_TIMING11_REG(base), (uint32_t)(~(value))))
39040 #define XCVR_TOG_TSM_TIMING11(base, value) (BME_XOR32(&XCVR_TSM_TIMING11_REG(base), (uint32_t)(value)))
39041 /*@}*/
39042 
39043 /*
39044  * Constants & macros for individual XCVR_TSM_TIMING11 bitfields
39045  */
39046 
39047 /*!
39048  * @name Register XCVR_TSM_TIMING11, field PLL_VCO_BUF_TX_EN_TX_HI[7:0] (RW)
39049  *
39050  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
39051  * at which the PLL_VCO_BUF_TX_EN signal or group will transition from LO to HI.
39052  */
39053 /*@{*/
39054 /*! @brief Read current value of the XCVR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_HI field. */
39055 #define XCVR_RD_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_HI(base) ((XCVR_TSM_TIMING11_REG(base) & XCVR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_HI_MASK) >> XCVR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_HI_SHIFT)
39056 #define XCVR_BRD_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING11_REG(base), XCVR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_HI_SHIFT, XCVR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_HI_WIDTH))
39057 
39058 /*! @brief Set the PLL_VCO_BUF_TX_EN_TX_HI field to a new value. */
39059 #define XCVR_WR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING11(base, XCVR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_HI_MASK, XCVR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_HI(value)))
39060 #define XCVR_BWR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING11_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_HI_SHIFT), XCVR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_HI_SHIFT, XCVR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_HI_WIDTH))
39061 /*@}*/
39062 
39063 /*!
39064  * @name Register XCVR_TSM_TIMING11, field PLL_VCO_BUF_TX_EN_TX_LO[15:8] (RW)
39065  *
39066  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
39067  * at which the PLL_VCO_BUF_TX_EN signal or group will transition from HI to LO.
39068  */
39069 /*@{*/
39070 /*! @brief Read current value of the XCVR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_LO field. */
39071 #define XCVR_RD_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_LO(base) ((XCVR_TSM_TIMING11_REG(base) & XCVR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_LO_MASK) >> XCVR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_LO_SHIFT)
39072 #define XCVR_BRD_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING11_REG(base), XCVR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_LO_SHIFT, XCVR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_LO_WIDTH))
39073 
39074 /*! @brief Set the PLL_VCO_BUF_TX_EN_TX_LO field to a new value. */
39075 #define XCVR_WR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING11(base, XCVR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_LO_MASK, XCVR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_LO(value)))
39076 #define XCVR_BWR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING11_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_LO_SHIFT), XCVR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_LO_SHIFT, XCVR_TSM_TIMING11_PLL_VCO_BUF_TX_EN_TX_LO_WIDTH))
39077 /*@}*/
39078 
39079 /*******************************************************************************
39080  * XCVR_TSM_TIMING12 - TSM_TIMING12
39081  ******************************************************************************/
39082 
39083 /*!
39084  * @brief XCVR_TSM_TIMING12 - TSM_TIMING12 (RW)
39085  *
39086  * Reset value: 0xFFFF6A64U
39087  *
39088  * This register contains the timing values to control the assertion and
39089  * deassertion times for both TX and RX sequences for the PLL_PA_BUF_EN TSM signal or
39090  * signal group.
39091  */
39092 /*!
39093  * @name Constants and macros for entire XCVR_TSM_TIMING12 register
39094  */
39095 /*@{*/
39096 #define XCVR_RD_TSM_TIMING12(base) (XCVR_TSM_TIMING12_REG(base))
39097 #define XCVR_WR_TSM_TIMING12(base, value) (XCVR_TSM_TIMING12_REG(base) = (value))
39098 #define XCVR_RMW_TSM_TIMING12(base, mask, value) (XCVR_WR_TSM_TIMING12(base, (XCVR_RD_TSM_TIMING12(base) & ~(mask)) | (value)))
39099 #define XCVR_SET_TSM_TIMING12(base, value) (BME_OR32(&XCVR_TSM_TIMING12_REG(base), (uint32_t)(value)))
39100 #define XCVR_CLR_TSM_TIMING12(base, value) (BME_AND32(&XCVR_TSM_TIMING12_REG(base), (uint32_t)(~(value))))
39101 #define XCVR_TOG_TSM_TIMING12(base, value) (BME_XOR32(&XCVR_TSM_TIMING12_REG(base), (uint32_t)(value)))
39102 /*@}*/
39103 
39104 /*
39105  * Constants & macros for individual XCVR_TSM_TIMING12 bitfields
39106  */
39107 
39108 /*!
39109  * @name Register XCVR_TSM_TIMING12, field PLL_PA_BUF_EN_TX_HI[7:0] (RW)
39110  *
39111  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
39112  * at which the PLL_PA_BUF_EN signal or group will transition from LO to HI.
39113  */
39114 /*@{*/
39115 /*! @brief Read current value of the XCVR_TSM_TIMING12_PLL_PA_BUF_EN_TX_HI field. */
39116 #define XCVR_RD_TSM_TIMING12_PLL_PA_BUF_EN_TX_HI(base) ((XCVR_TSM_TIMING12_REG(base) & XCVR_TSM_TIMING12_PLL_PA_BUF_EN_TX_HI_MASK) >> XCVR_TSM_TIMING12_PLL_PA_BUF_EN_TX_HI_SHIFT)
39117 #define XCVR_BRD_TSM_TIMING12_PLL_PA_BUF_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING12_REG(base), XCVR_TSM_TIMING12_PLL_PA_BUF_EN_TX_HI_SHIFT, XCVR_TSM_TIMING12_PLL_PA_BUF_EN_TX_HI_WIDTH))
39118 
39119 /*! @brief Set the PLL_PA_BUF_EN_TX_HI field to a new value. */
39120 #define XCVR_WR_TSM_TIMING12_PLL_PA_BUF_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING12(base, XCVR_TSM_TIMING12_PLL_PA_BUF_EN_TX_HI_MASK, XCVR_TSM_TIMING12_PLL_PA_BUF_EN_TX_HI(value)))
39121 #define XCVR_BWR_TSM_TIMING12_PLL_PA_BUF_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING12_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING12_PLL_PA_BUF_EN_TX_HI_SHIFT), XCVR_TSM_TIMING12_PLL_PA_BUF_EN_TX_HI_SHIFT, XCVR_TSM_TIMING12_PLL_PA_BUF_EN_TX_HI_WIDTH))
39122 /*@}*/
39123 
39124 /*!
39125  * @name Register XCVR_TSM_TIMING12, field PLL_PA_BUF_EN_TX_LO[15:8] (RW)
39126  *
39127  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
39128  * at which the PLL_PA_BUF_EN signal or group will transition from HI to LO.
39129  */
39130 /*@{*/
39131 /*! @brief Read current value of the XCVR_TSM_TIMING12_PLL_PA_BUF_EN_TX_LO field. */
39132 #define XCVR_RD_TSM_TIMING12_PLL_PA_BUF_EN_TX_LO(base) ((XCVR_TSM_TIMING12_REG(base) & XCVR_TSM_TIMING12_PLL_PA_BUF_EN_TX_LO_MASK) >> XCVR_TSM_TIMING12_PLL_PA_BUF_EN_TX_LO_SHIFT)
39133 #define XCVR_BRD_TSM_TIMING12_PLL_PA_BUF_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING12_REG(base), XCVR_TSM_TIMING12_PLL_PA_BUF_EN_TX_LO_SHIFT, XCVR_TSM_TIMING12_PLL_PA_BUF_EN_TX_LO_WIDTH))
39134 
39135 /*! @brief Set the PLL_PA_BUF_EN_TX_LO field to a new value. */
39136 #define XCVR_WR_TSM_TIMING12_PLL_PA_BUF_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING12(base, XCVR_TSM_TIMING12_PLL_PA_BUF_EN_TX_LO_MASK, XCVR_TSM_TIMING12_PLL_PA_BUF_EN_TX_LO(value)))
39137 #define XCVR_BWR_TSM_TIMING12_PLL_PA_BUF_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING12_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING12_PLL_PA_BUF_EN_TX_LO_SHIFT), XCVR_TSM_TIMING12_PLL_PA_BUF_EN_TX_LO_SHIFT, XCVR_TSM_TIMING12_PLL_PA_BUF_EN_TX_LO_WIDTH))
39138 /*@}*/
39139 
39140 /*******************************************************************************
39141  * XCVR_TSM_TIMING13 - TSM_TIMING13
39142  ******************************************************************************/
39143 
39144 /*!
39145  * @brief XCVR_TSM_TIMING13 - TSM_TIMING13 (RW)
39146  *
39147  * Reset value: 0x651A6A4EU
39148  *
39149  * This register contains the timing values to control the assertion and
39150  * deassertion times for both TX and RX sequences for the PLL_LDV_EN TSM signal or
39151  * signal group.
39152  */
39153 /*!
39154  * @name Constants and macros for entire XCVR_TSM_TIMING13 register
39155  */
39156 /*@{*/
39157 #define XCVR_RD_TSM_TIMING13(base) (XCVR_TSM_TIMING13_REG(base))
39158 #define XCVR_WR_TSM_TIMING13(base, value) (XCVR_TSM_TIMING13_REG(base) = (value))
39159 #define XCVR_RMW_TSM_TIMING13(base, mask, value) (XCVR_WR_TSM_TIMING13(base, (XCVR_RD_TSM_TIMING13(base) & ~(mask)) | (value)))
39160 #define XCVR_SET_TSM_TIMING13(base, value) (BME_OR32(&XCVR_TSM_TIMING13_REG(base), (uint32_t)(value)))
39161 #define XCVR_CLR_TSM_TIMING13(base, value) (BME_AND32(&XCVR_TSM_TIMING13_REG(base), (uint32_t)(~(value))))
39162 #define XCVR_TOG_TSM_TIMING13(base, value) (BME_XOR32(&XCVR_TSM_TIMING13_REG(base), (uint32_t)(value)))
39163 /*@}*/
39164 
39165 /*
39166  * Constants & macros for individual XCVR_TSM_TIMING13 bitfields
39167  */
39168 
39169 /*!
39170  * @name Register XCVR_TSM_TIMING13, field PLL_LDV_EN_TX_HI[7:0] (RW)
39171  *
39172  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
39173  * at which the PLL_LDV_EN signal or group will transition from LO to HI.
39174  */
39175 /*@{*/
39176 /*! @brief Read current value of the XCVR_TSM_TIMING13_PLL_LDV_EN_TX_HI field. */
39177 #define XCVR_RD_TSM_TIMING13_PLL_LDV_EN_TX_HI(base) ((XCVR_TSM_TIMING13_REG(base) & XCVR_TSM_TIMING13_PLL_LDV_EN_TX_HI_MASK) >> XCVR_TSM_TIMING13_PLL_LDV_EN_TX_HI_SHIFT)
39178 #define XCVR_BRD_TSM_TIMING13_PLL_LDV_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING13_REG(base), XCVR_TSM_TIMING13_PLL_LDV_EN_TX_HI_SHIFT, XCVR_TSM_TIMING13_PLL_LDV_EN_TX_HI_WIDTH))
39179 
39180 /*! @brief Set the PLL_LDV_EN_TX_HI field to a new value. */
39181 #define XCVR_WR_TSM_TIMING13_PLL_LDV_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING13(base, XCVR_TSM_TIMING13_PLL_LDV_EN_TX_HI_MASK, XCVR_TSM_TIMING13_PLL_LDV_EN_TX_HI(value)))
39182 #define XCVR_BWR_TSM_TIMING13_PLL_LDV_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING13_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING13_PLL_LDV_EN_TX_HI_SHIFT), XCVR_TSM_TIMING13_PLL_LDV_EN_TX_HI_SHIFT, XCVR_TSM_TIMING13_PLL_LDV_EN_TX_HI_WIDTH))
39183 /*@}*/
39184 
39185 /*!
39186  * @name Register XCVR_TSM_TIMING13, field PLL_LDV_EN_TX_LO[15:8] (RW)
39187  *
39188  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
39189  * at which the PLL_LDV_EN signal or group will transition from HI to LO.
39190  */
39191 /*@{*/
39192 /*! @brief Read current value of the XCVR_TSM_TIMING13_PLL_LDV_EN_TX_LO field. */
39193 #define XCVR_RD_TSM_TIMING13_PLL_LDV_EN_TX_LO(base) ((XCVR_TSM_TIMING13_REG(base) & XCVR_TSM_TIMING13_PLL_LDV_EN_TX_LO_MASK) >> XCVR_TSM_TIMING13_PLL_LDV_EN_TX_LO_SHIFT)
39194 #define XCVR_BRD_TSM_TIMING13_PLL_LDV_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING13_REG(base), XCVR_TSM_TIMING13_PLL_LDV_EN_TX_LO_SHIFT, XCVR_TSM_TIMING13_PLL_LDV_EN_TX_LO_WIDTH))
39195 
39196 /*! @brief Set the PLL_LDV_EN_TX_LO field to a new value. */
39197 #define XCVR_WR_TSM_TIMING13_PLL_LDV_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING13(base, XCVR_TSM_TIMING13_PLL_LDV_EN_TX_LO_MASK, XCVR_TSM_TIMING13_PLL_LDV_EN_TX_LO(value)))
39198 #define XCVR_BWR_TSM_TIMING13_PLL_LDV_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING13_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING13_PLL_LDV_EN_TX_LO_SHIFT), XCVR_TSM_TIMING13_PLL_LDV_EN_TX_LO_SHIFT, XCVR_TSM_TIMING13_PLL_LDV_EN_TX_LO_WIDTH))
39199 /*@}*/
39200 
39201 /*!
39202  * @name Register XCVR_TSM_TIMING13, field PLL_LDV_EN_RX_HI[23:16] (RW)
39203  *
39204  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
39205  * at which the PLL_LDV_EN signal or group will transition from LO to HI.
39206  */
39207 /*@{*/
39208 /*! @brief Read current value of the XCVR_TSM_TIMING13_PLL_LDV_EN_RX_HI field. */
39209 #define XCVR_RD_TSM_TIMING13_PLL_LDV_EN_RX_HI(base) ((XCVR_TSM_TIMING13_REG(base) & XCVR_TSM_TIMING13_PLL_LDV_EN_RX_HI_MASK) >> XCVR_TSM_TIMING13_PLL_LDV_EN_RX_HI_SHIFT)
39210 #define XCVR_BRD_TSM_TIMING13_PLL_LDV_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING13_REG(base), XCVR_TSM_TIMING13_PLL_LDV_EN_RX_HI_SHIFT, XCVR_TSM_TIMING13_PLL_LDV_EN_RX_HI_WIDTH))
39211 
39212 /*! @brief Set the PLL_LDV_EN_RX_HI field to a new value. */
39213 #define XCVR_WR_TSM_TIMING13_PLL_LDV_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING13(base, XCVR_TSM_TIMING13_PLL_LDV_EN_RX_HI_MASK, XCVR_TSM_TIMING13_PLL_LDV_EN_RX_HI(value)))
39214 #define XCVR_BWR_TSM_TIMING13_PLL_LDV_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING13_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING13_PLL_LDV_EN_RX_HI_SHIFT), XCVR_TSM_TIMING13_PLL_LDV_EN_RX_HI_SHIFT, XCVR_TSM_TIMING13_PLL_LDV_EN_RX_HI_WIDTH))
39215 /*@}*/
39216 
39217 /*!
39218  * @name Register XCVR_TSM_TIMING13, field PLL_LDV_EN_RX_LO[31:24] (RW)
39219  *
39220  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
39221  * at which the PLL_LDV_EN signal or group will transition from HI to LO.
39222  */
39223 /*@{*/
39224 /*! @brief Read current value of the XCVR_TSM_TIMING13_PLL_LDV_EN_RX_LO field. */
39225 #define XCVR_RD_TSM_TIMING13_PLL_LDV_EN_RX_LO(base) ((XCVR_TSM_TIMING13_REG(base) & XCVR_TSM_TIMING13_PLL_LDV_EN_RX_LO_MASK) >> XCVR_TSM_TIMING13_PLL_LDV_EN_RX_LO_SHIFT)
39226 #define XCVR_BRD_TSM_TIMING13_PLL_LDV_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING13_REG(base), XCVR_TSM_TIMING13_PLL_LDV_EN_RX_LO_SHIFT, XCVR_TSM_TIMING13_PLL_LDV_EN_RX_LO_WIDTH))
39227 
39228 /*! @brief Set the PLL_LDV_EN_RX_LO field to a new value. */
39229 #define XCVR_WR_TSM_TIMING13_PLL_LDV_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING13(base, XCVR_TSM_TIMING13_PLL_LDV_EN_RX_LO_MASK, XCVR_TSM_TIMING13_PLL_LDV_EN_RX_LO(value)))
39230 #define XCVR_BWR_TSM_TIMING13_PLL_LDV_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING13_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING13_PLL_LDV_EN_RX_LO_SHIFT), XCVR_TSM_TIMING13_PLL_LDV_EN_RX_LO_SHIFT, XCVR_TSM_TIMING13_PLL_LDV_EN_RX_LO_WIDTH))
39231 /*@}*/
39232 
39233 /*******************************************************************************
39234  * XCVR_TSM_TIMING14 - TSM_TIMING14
39235  ******************************************************************************/
39236 
39237 /*!
39238  * @brief XCVR_TSM_TIMING14 - TSM_TIMING14 (RW)
39239  *
39240  * Reset value: 0x650AFFFFU
39241  *
39242  * This register contains the timing values to control the assertion and
39243  * deassertion times for both TX and RX sequences for the PLL_RX_LDV_RIPPLE_MUX_EN TSM
39244  * signal or signal group.
39245  */
39246 /*!
39247  * @name Constants and macros for entire XCVR_TSM_TIMING14 register
39248  */
39249 /*@{*/
39250 #define XCVR_RD_TSM_TIMING14(base) (XCVR_TSM_TIMING14_REG(base))
39251 #define XCVR_WR_TSM_TIMING14(base, value) (XCVR_TSM_TIMING14_REG(base) = (value))
39252 #define XCVR_RMW_TSM_TIMING14(base, mask, value) (XCVR_WR_TSM_TIMING14(base, (XCVR_RD_TSM_TIMING14(base) & ~(mask)) | (value)))
39253 #define XCVR_SET_TSM_TIMING14(base, value) (BME_OR32(&XCVR_TSM_TIMING14_REG(base), (uint32_t)(value)))
39254 #define XCVR_CLR_TSM_TIMING14(base, value) (BME_AND32(&XCVR_TSM_TIMING14_REG(base), (uint32_t)(~(value))))
39255 #define XCVR_TOG_TSM_TIMING14(base, value) (BME_XOR32(&XCVR_TSM_TIMING14_REG(base), (uint32_t)(value)))
39256 /*@}*/
39257 
39258 /*
39259  * Constants & macros for individual XCVR_TSM_TIMING14 bitfields
39260  */
39261 
39262 /*!
39263  * @name Register XCVR_TSM_TIMING14, field PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI[23:16] (RW)
39264  *
39265  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
39266  * at which the PLL_RX_LDV_RIPPLE_MUX_EN signal or group will transition from LO
39267  * to HI.
39268  */
39269 /*@{*/
39270 /*! @brief Read current value of the XCVR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI field. */
39271 #define XCVR_RD_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI(base) ((XCVR_TSM_TIMING14_REG(base) & XCVR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI_MASK) >> XCVR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI_SHIFT)
39272 #define XCVR_BRD_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING14_REG(base), XCVR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI_SHIFT, XCVR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI_WIDTH))
39273 
39274 /*! @brief Set the PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI field to a new value. */
39275 #define XCVR_WR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING14(base, XCVR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI_MASK, XCVR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI(value)))
39276 #define XCVR_BWR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING14_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI_SHIFT), XCVR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI_SHIFT, XCVR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_HI_WIDTH))
39277 /*@}*/
39278 
39279 /*!
39280  * @name Register XCVR_TSM_TIMING14, field PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO[31:24] (RW)
39281  *
39282  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
39283  * at which the PLL_RX_LDV_RIPPLE_MUX_EN signal or group will transition from HI
39284  * to LO.
39285  */
39286 /*@{*/
39287 /*! @brief Read current value of the XCVR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO field. */
39288 #define XCVR_RD_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO(base) ((XCVR_TSM_TIMING14_REG(base) & XCVR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO_MASK) >> XCVR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO_SHIFT)
39289 #define XCVR_BRD_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING14_REG(base), XCVR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO_SHIFT, XCVR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO_WIDTH))
39290 
39291 /*! @brief Set the PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO field to a new value. */
39292 #define XCVR_WR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING14(base, XCVR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO_MASK, XCVR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO(value)))
39293 #define XCVR_BWR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING14_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO_SHIFT), XCVR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO_SHIFT, XCVR_TSM_TIMING14_PLL_RX_LDV_RIPPLE_MUX_EN_RX_LO_WIDTH))
39294 /*@}*/
39295 
39296 /*******************************************************************************
39297  * XCVR_TSM_TIMING15 - TSM_TIMING15
39298  ******************************************************************************/
39299 
39300 /*!
39301  * @brief XCVR_TSM_TIMING15 - TSM_TIMING15 (RW)
39302  *
39303  * Reset value: 0xFFFF6A0AU
39304  *
39305  * This register contains the timing values to control the assertion and
39306  * deassertion times for both TX and RX sequences for the PLL_TX_LDV_RIPPLE_MUX_EN TSM
39307  * signal or signal group.
39308  */
39309 /*!
39310  * @name Constants and macros for entire XCVR_TSM_TIMING15 register
39311  */
39312 /*@{*/
39313 #define XCVR_RD_TSM_TIMING15(base) (XCVR_TSM_TIMING15_REG(base))
39314 #define XCVR_WR_TSM_TIMING15(base, value) (XCVR_TSM_TIMING15_REG(base) = (value))
39315 #define XCVR_RMW_TSM_TIMING15(base, mask, value) (XCVR_WR_TSM_TIMING15(base, (XCVR_RD_TSM_TIMING15(base) & ~(mask)) | (value)))
39316 #define XCVR_SET_TSM_TIMING15(base, value) (BME_OR32(&XCVR_TSM_TIMING15_REG(base), (uint32_t)(value)))
39317 #define XCVR_CLR_TSM_TIMING15(base, value) (BME_AND32(&XCVR_TSM_TIMING15_REG(base), (uint32_t)(~(value))))
39318 #define XCVR_TOG_TSM_TIMING15(base, value) (BME_XOR32(&XCVR_TSM_TIMING15_REG(base), (uint32_t)(value)))
39319 /*@}*/
39320 
39321 /*
39322  * Constants & macros for individual XCVR_TSM_TIMING15 bitfields
39323  */
39324 
39325 /*!
39326  * @name Register XCVR_TSM_TIMING15, field PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI[7:0] (RW)
39327  *
39328  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
39329  * at which the PLL_TX_LDV_RIPPLE_MUX_EN signal or group will transition from LO
39330  * to HI.
39331  */
39332 /*@{*/
39333 /*! @brief Read current value of the XCVR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI field. */
39334 #define XCVR_RD_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI(base) ((XCVR_TSM_TIMING15_REG(base) & XCVR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI_MASK) >> XCVR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI_SHIFT)
39335 #define XCVR_BRD_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING15_REG(base), XCVR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI_SHIFT, XCVR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI_WIDTH))
39336 
39337 /*! @brief Set the PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI field to a new value. */
39338 #define XCVR_WR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING15(base, XCVR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI_MASK, XCVR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI(value)))
39339 #define XCVR_BWR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING15_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI_SHIFT), XCVR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI_SHIFT, XCVR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_HI_WIDTH))
39340 /*@}*/
39341 
39342 /*!
39343  * @name Register XCVR_TSM_TIMING15, field PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO[15:8] (RW)
39344  *
39345  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
39346  * at which the PLL_TX_LDV_RIPPLE_MUX_EN signal or group will transition from HI
39347  * to LO.
39348  */
39349 /*@{*/
39350 /*! @brief Read current value of the XCVR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO field. */
39351 #define XCVR_RD_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO(base) ((XCVR_TSM_TIMING15_REG(base) & XCVR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO_MASK) >> XCVR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO_SHIFT)
39352 #define XCVR_BRD_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING15_REG(base), XCVR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO_SHIFT, XCVR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO_WIDTH))
39353 
39354 /*! @brief Set the PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO field to a new value. */
39355 #define XCVR_WR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING15(base, XCVR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO_MASK, XCVR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO(value)))
39356 #define XCVR_BWR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING15_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO_SHIFT), XCVR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO_SHIFT, XCVR_TSM_TIMING15_PLL_TX_LDV_RIPPLE_MUX_EN_TX_LO_WIDTH))
39357 /*@}*/
39358 
39359 /*******************************************************************************
39360  * XCVR_TSM_TIMING16 - TSM_TIMING16
39361  ******************************************************************************/
39362 
39363 /*!
39364  * @brief XCVR_TSM_TIMING16 - TSM_TIMING16 (RW)
39365  *
39366  * Reset value: 0x1A104E44U
39367  *
39368  * This register contains the timing values to control the assertion and
39369  * deassertion times for both TX and RX sequences for the PLL_FILTER_CHARGE_EN TSM
39370  * signal or signal group.
39371  */
39372 /*!
39373  * @name Constants and macros for entire XCVR_TSM_TIMING16 register
39374  */
39375 /*@{*/
39376 #define XCVR_RD_TSM_TIMING16(base) (XCVR_TSM_TIMING16_REG(base))
39377 #define XCVR_WR_TSM_TIMING16(base, value) (XCVR_TSM_TIMING16_REG(base) = (value))
39378 #define XCVR_RMW_TSM_TIMING16(base, mask, value) (XCVR_WR_TSM_TIMING16(base, (XCVR_RD_TSM_TIMING16(base) & ~(mask)) | (value)))
39379 #define XCVR_SET_TSM_TIMING16(base, value) (BME_OR32(&XCVR_TSM_TIMING16_REG(base), (uint32_t)(value)))
39380 #define XCVR_CLR_TSM_TIMING16(base, value) (BME_AND32(&XCVR_TSM_TIMING16_REG(base), (uint32_t)(~(value))))
39381 #define XCVR_TOG_TSM_TIMING16(base, value) (BME_XOR32(&XCVR_TSM_TIMING16_REG(base), (uint32_t)(value)))
39382 /*@}*/
39383 
39384 /*
39385  * Constants & macros for individual XCVR_TSM_TIMING16 bitfields
39386  */
39387 
39388 /*!
39389  * @name Register XCVR_TSM_TIMING16, field PLL_FILTER_CHARGE_EN_TX_HI[7:0] (RW)
39390  *
39391  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
39392  * at which the PLL_FILTER_CHARGE_EN signal or group will transition from LO to
39393  * HI.
39394  */
39395 /*@{*/
39396 /*! @brief Read current value of the XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_HI field. */
39397 #define XCVR_RD_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_HI(base) ((XCVR_TSM_TIMING16_REG(base) & XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_HI_MASK) >> XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_HI_SHIFT)
39398 #define XCVR_BRD_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING16_REG(base), XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_HI_SHIFT, XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_HI_WIDTH))
39399 
39400 /*! @brief Set the PLL_FILTER_CHARGE_EN_TX_HI field to a new value. */
39401 #define XCVR_WR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING16(base, XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_HI_MASK, XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_HI(value)))
39402 #define XCVR_BWR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING16_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_HI_SHIFT), XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_HI_SHIFT, XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_HI_WIDTH))
39403 /*@}*/
39404 
39405 /*!
39406  * @name Register XCVR_TSM_TIMING16, field PLL_FILTER_CHARGE_EN_TX_LO[15:8] (RW)
39407  *
39408  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
39409  * at which the PLL_FILTER_CHARGE_EN signal or group will transition from HI to
39410  * LO.
39411  */
39412 /*@{*/
39413 /*! @brief Read current value of the XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_LO field. */
39414 #define XCVR_RD_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_LO(base) ((XCVR_TSM_TIMING16_REG(base) & XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_LO_MASK) >> XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_LO_SHIFT)
39415 #define XCVR_BRD_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING16_REG(base), XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_LO_SHIFT, XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_LO_WIDTH))
39416 
39417 /*! @brief Set the PLL_FILTER_CHARGE_EN_TX_LO field to a new value. */
39418 #define XCVR_WR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING16(base, XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_LO_MASK, XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_LO(value)))
39419 #define XCVR_BWR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING16_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_LO_SHIFT), XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_LO_SHIFT, XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_TX_LO_WIDTH))
39420 /*@}*/
39421 
39422 /*!
39423  * @name Register XCVR_TSM_TIMING16, field PLL_FILTER_CHARGE_EN_RX_HI[23:16] (RW)
39424  *
39425  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
39426  * at which the PLL_FILTER_CHARGE_EN signal or group will transition from LO to
39427  * HI.
39428  */
39429 /*@{*/
39430 /*! @brief Read current value of the XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_HI field. */
39431 #define XCVR_RD_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_HI(base) ((XCVR_TSM_TIMING16_REG(base) & XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_HI_MASK) >> XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_HI_SHIFT)
39432 #define XCVR_BRD_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING16_REG(base), XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_HI_SHIFT, XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_HI_WIDTH))
39433 
39434 /*! @brief Set the PLL_FILTER_CHARGE_EN_RX_HI field to a new value. */
39435 #define XCVR_WR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING16(base, XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_HI_MASK, XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_HI(value)))
39436 #define XCVR_BWR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING16_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_HI_SHIFT), XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_HI_SHIFT, XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_HI_WIDTH))
39437 /*@}*/
39438 
39439 /*!
39440  * @name Register XCVR_TSM_TIMING16, field PLL_FILTER_CHARGE_EN_RX_LO[31:24] (RW)
39441  *
39442  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
39443  * at which the PLL_FILTER_CHARGE_EN signal or group will transition from HI to
39444  * LO.
39445  */
39446 /*@{*/
39447 /*! @brief Read current value of the XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_LO field. */
39448 #define XCVR_RD_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_LO(base) ((XCVR_TSM_TIMING16_REG(base) & XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_LO_MASK) >> XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_LO_SHIFT)
39449 #define XCVR_BRD_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING16_REG(base), XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_LO_SHIFT, XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_LO_WIDTH))
39450 
39451 /*! @brief Set the PLL_FILTER_CHARGE_EN_RX_LO field to a new value. */
39452 #define XCVR_WR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING16(base, XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_LO_MASK, XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_LO(value)))
39453 #define XCVR_BWR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING16_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_LO_SHIFT), XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_LO_SHIFT, XCVR_TSM_TIMING16_PLL_FILTER_CHARGE_EN_RX_LO_WIDTH))
39454 /*@}*/
39455 
39456 /*******************************************************************************
39457  * XCVR_TSM_TIMING17 - TSM_TIMING17
39458  ******************************************************************************/
39459 
39460 /*!
39461  * @brief XCVR_TSM_TIMING17 - TSM_TIMING17 (RW)
39462  *
39463  * Reset value: 0x65106A44U
39464  *
39465  * This register contains the timing values to control the assertion and
39466  * deassertion times for both TX and RX sequences for the PLL_PHDET_EN TSM signal or
39467  * signal group.
39468  */
39469 /*!
39470  * @name Constants and macros for entire XCVR_TSM_TIMING17 register
39471  */
39472 /*@{*/
39473 #define XCVR_RD_TSM_TIMING17(base) (XCVR_TSM_TIMING17_REG(base))
39474 #define XCVR_WR_TSM_TIMING17(base, value) (XCVR_TSM_TIMING17_REG(base) = (value))
39475 #define XCVR_RMW_TSM_TIMING17(base, mask, value) (XCVR_WR_TSM_TIMING17(base, (XCVR_RD_TSM_TIMING17(base) & ~(mask)) | (value)))
39476 #define XCVR_SET_TSM_TIMING17(base, value) (BME_OR32(&XCVR_TSM_TIMING17_REG(base), (uint32_t)(value)))
39477 #define XCVR_CLR_TSM_TIMING17(base, value) (BME_AND32(&XCVR_TSM_TIMING17_REG(base), (uint32_t)(~(value))))
39478 #define XCVR_TOG_TSM_TIMING17(base, value) (BME_XOR32(&XCVR_TSM_TIMING17_REG(base), (uint32_t)(value)))
39479 /*@}*/
39480 
39481 /*
39482  * Constants & macros for individual XCVR_TSM_TIMING17 bitfields
39483  */
39484 
39485 /*!
39486  * @name Register XCVR_TSM_TIMING17, field PLL_PHDET_EN_TX_HI[7:0] (RW)
39487  *
39488  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
39489  * at which the PLL_PHDET_EN signal or group will transition from LO to HI.
39490  */
39491 /*@{*/
39492 /*! @brief Read current value of the XCVR_TSM_TIMING17_PLL_PHDET_EN_TX_HI field. */
39493 #define XCVR_RD_TSM_TIMING17_PLL_PHDET_EN_TX_HI(base) ((XCVR_TSM_TIMING17_REG(base) & XCVR_TSM_TIMING17_PLL_PHDET_EN_TX_HI_MASK) >> XCVR_TSM_TIMING17_PLL_PHDET_EN_TX_HI_SHIFT)
39494 #define XCVR_BRD_TSM_TIMING17_PLL_PHDET_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING17_REG(base), XCVR_TSM_TIMING17_PLL_PHDET_EN_TX_HI_SHIFT, XCVR_TSM_TIMING17_PLL_PHDET_EN_TX_HI_WIDTH))
39495 
39496 /*! @brief Set the PLL_PHDET_EN_TX_HI field to a new value. */
39497 #define XCVR_WR_TSM_TIMING17_PLL_PHDET_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING17(base, XCVR_TSM_TIMING17_PLL_PHDET_EN_TX_HI_MASK, XCVR_TSM_TIMING17_PLL_PHDET_EN_TX_HI(value)))
39498 #define XCVR_BWR_TSM_TIMING17_PLL_PHDET_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING17_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING17_PLL_PHDET_EN_TX_HI_SHIFT), XCVR_TSM_TIMING17_PLL_PHDET_EN_TX_HI_SHIFT, XCVR_TSM_TIMING17_PLL_PHDET_EN_TX_HI_WIDTH))
39499 /*@}*/
39500 
39501 /*!
39502  * @name Register XCVR_TSM_TIMING17, field PLL_PHDET_EN_TX_LO[15:8] (RW)
39503  *
39504  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
39505  * at which the PLL_PHDET_EN signal or group will transition from HI to LO.
39506  */
39507 /*@{*/
39508 /*! @brief Read current value of the XCVR_TSM_TIMING17_PLL_PHDET_EN_TX_LO field. */
39509 #define XCVR_RD_TSM_TIMING17_PLL_PHDET_EN_TX_LO(base) ((XCVR_TSM_TIMING17_REG(base) & XCVR_TSM_TIMING17_PLL_PHDET_EN_TX_LO_MASK) >> XCVR_TSM_TIMING17_PLL_PHDET_EN_TX_LO_SHIFT)
39510 #define XCVR_BRD_TSM_TIMING17_PLL_PHDET_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING17_REG(base), XCVR_TSM_TIMING17_PLL_PHDET_EN_TX_LO_SHIFT, XCVR_TSM_TIMING17_PLL_PHDET_EN_TX_LO_WIDTH))
39511 
39512 /*! @brief Set the PLL_PHDET_EN_TX_LO field to a new value. */
39513 #define XCVR_WR_TSM_TIMING17_PLL_PHDET_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING17(base, XCVR_TSM_TIMING17_PLL_PHDET_EN_TX_LO_MASK, XCVR_TSM_TIMING17_PLL_PHDET_EN_TX_LO(value)))
39514 #define XCVR_BWR_TSM_TIMING17_PLL_PHDET_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING17_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING17_PLL_PHDET_EN_TX_LO_SHIFT), XCVR_TSM_TIMING17_PLL_PHDET_EN_TX_LO_SHIFT, XCVR_TSM_TIMING17_PLL_PHDET_EN_TX_LO_WIDTH))
39515 /*@}*/
39516 
39517 /*!
39518  * @name Register XCVR_TSM_TIMING17, field PLL_PHDET_EN_RX_HI[23:16] (RW)
39519  *
39520  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
39521  * at which the PLL_PHDET_EN signal or group will transition from LO to HI.
39522  */
39523 /*@{*/
39524 /*! @brief Read current value of the XCVR_TSM_TIMING17_PLL_PHDET_EN_RX_HI field. */
39525 #define XCVR_RD_TSM_TIMING17_PLL_PHDET_EN_RX_HI(base) ((XCVR_TSM_TIMING17_REG(base) & XCVR_TSM_TIMING17_PLL_PHDET_EN_RX_HI_MASK) >> XCVR_TSM_TIMING17_PLL_PHDET_EN_RX_HI_SHIFT)
39526 #define XCVR_BRD_TSM_TIMING17_PLL_PHDET_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING17_REG(base), XCVR_TSM_TIMING17_PLL_PHDET_EN_RX_HI_SHIFT, XCVR_TSM_TIMING17_PLL_PHDET_EN_RX_HI_WIDTH))
39527 
39528 /*! @brief Set the PLL_PHDET_EN_RX_HI field to a new value. */
39529 #define XCVR_WR_TSM_TIMING17_PLL_PHDET_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING17(base, XCVR_TSM_TIMING17_PLL_PHDET_EN_RX_HI_MASK, XCVR_TSM_TIMING17_PLL_PHDET_EN_RX_HI(value)))
39530 #define XCVR_BWR_TSM_TIMING17_PLL_PHDET_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING17_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING17_PLL_PHDET_EN_RX_HI_SHIFT), XCVR_TSM_TIMING17_PLL_PHDET_EN_RX_HI_SHIFT, XCVR_TSM_TIMING17_PLL_PHDET_EN_RX_HI_WIDTH))
39531 /*@}*/
39532 
39533 /*!
39534  * @name Register XCVR_TSM_TIMING17, field PLL_PHDET_EN_RX_LO[31:24] (RW)
39535  *
39536  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
39537  * at which the PLL_PHDET_EN signal or group will transition from HI to LO.
39538  */
39539 /*@{*/
39540 /*! @brief Read current value of the XCVR_TSM_TIMING17_PLL_PHDET_EN_RX_LO field. */
39541 #define XCVR_RD_TSM_TIMING17_PLL_PHDET_EN_RX_LO(base) ((XCVR_TSM_TIMING17_REG(base) & XCVR_TSM_TIMING17_PLL_PHDET_EN_RX_LO_MASK) >> XCVR_TSM_TIMING17_PLL_PHDET_EN_RX_LO_SHIFT)
39542 #define XCVR_BRD_TSM_TIMING17_PLL_PHDET_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING17_REG(base), XCVR_TSM_TIMING17_PLL_PHDET_EN_RX_LO_SHIFT, XCVR_TSM_TIMING17_PLL_PHDET_EN_RX_LO_WIDTH))
39543 
39544 /*! @brief Set the PLL_PHDET_EN_RX_LO field to a new value. */
39545 #define XCVR_WR_TSM_TIMING17_PLL_PHDET_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING17(base, XCVR_TSM_TIMING17_PLL_PHDET_EN_RX_LO_MASK, XCVR_TSM_TIMING17_PLL_PHDET_EN_RX_LO(value)))
39546 #define XCVR_BWR_TSM_TIMING17_PLL_PHDET_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING17_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING17_PLL_PHDET_EN_RX_LO_SHIFT), XCVR_TSM_TIMING17_PLL_PHDET_EN_RX_LO_SHIFT, XCVR_TSM_TIMING17_PLL_PHDET_EN_RX_LO_WIDTH))
39547 /*@}*/
39548 
39549 /*******************************************************************************
39550  * XCVR_TSM_TIMING18 - TSM_TIMING18
39551  ******************************************************************************/
39552 
39553 /*!
39554  * @brief XCVR_TSM_TIMING18 - TSM_TIMING18 (RW)
39555  *
39556  * Reset value: 0x6505FFFFU
39557  *
39558  * This register contains the timing values to control the assertion and
39559  * deassertion times for both TX and RX sequences for the QGEN25_EN TSM signal or signal
39560  * group.
39561  */
39562 /*!
39563  * @name Constants and macros for entire XCVR_TSM_TIMING18 register
39564  */
39565 /*@{*/
39566 #define XCVR_RD_TSM_TIMING18(base) (XCVR_TSM_TIMING18_REG(base))
39567 #define XCVR_WR_TSM_TIMING18(base, value) (XCVR_TSM_TIMING18_REG(base) = (value))
39568 #define XCVR_RMW_TSM_TIMING18(base, mask, value) (XCVR_WR_TSM_TIMING18(base, (XCVR_RD_TSM_TIMING18(base) & ~(mask)) | (value)))
39569 #define XCVR_SET_TSM_TIMING18(base, value) (BME_OR32(&XCVR_TSM_TIMING18_REG(base), (uint32_t)(value)))
39570 #define XCVR_CLR_TSM_TIMING18(base, value) (BME_AND32(&XCVR_TSM_TIMING18_REG(base), (uint32_t)(~(value))))
39571 #define XCVR_TOG_TSM_TIMING18(base, value) (BME_XOR32(&XCVR_TSM_TIMING18_REG(base), (uint32_t)(value)))
39572 /*@}*/
39573 
39574 /*
39575  * Constants & macros for individual XCVR_TSM_TIMING18 bitfields
39576  */
39577 
39578 /*!
39579  * @name Register XCVR_TSM_TIMING18, field QGEN25_EN_RX_HI[23:16] (RW)
39580  *
39581  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
39582  * at which the QGEN25_EN signal or group will transition from LO to HI.
39583  */
39584 /*@{*/
39585 /*! @brief Read current value of the XCVR_TSM_TIMING18_QGEN25_EN_RX_HI field. */
39586 #define XCVR_RD_TSM_TIMING18_QGEN25_EN_RX_HI(base) ((XCVR_TSM_TIMING18_REG(base) & XCVR_TSM_TIMING18_QGEN25_EN_RX_HI_MASK) >> XCVR_TSM_TIMING18_QGEN25_EN_RX_HI_SHIFT)
39587 #define XCVR_BRD_TSM_TIMING18_QGEN25_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING18_REG(base), XCVR_TSM_TIMING18_QGEN25_EN_RX_HI_SHIFT, XCVR_TSM_TIMING18_QGEN25_EN_RX_HI_WIDTH))
39588 
39589 /*! @brief Set the QGEN25_EN_RX_HI field to a new value. */
39590 #define XCVR_WR_TSM_TIMING18_QGEN25_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING18(base, XCVR_TSM_TIMING18_QGEN25_EN_RX_HI_MASK, XCVR_TSM_TIMING18_QGEN25_EN_RX_HI(value)))
39591 #define XCVR_BWR_TSM_TIMING18_QGEN25_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING18_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING18_QGEN25_EN_RX_HI_SHIFT), XCVR_TSM_TIMING18_QGEN25_EN_RX_HI_SHIFT, XCVR_TSM_TIMING18_QGEN25_EN_RX_HI_WIDTH))
39592 /*@}*/
39593 
39594 /*!
39595  * @name Register XCVR_TSM_TIMING18, field QGEN25_EN_RX_LO[31:24] (RW)
39596  *
39597  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
39598  * at which the QGEN25_EN signal or group will transition from HI to LO.
39599  */
39600 /*@{*/
39601 /*! @brief Read current value of the XCVR_TSM_TIMING18_QGEN25_EN_RX_LO field. */
39602 #define XCVR_RD_TSM_TIMING18_QGEN25_EN_RX_LO(base) ((XCVR_TSM_TIMING18_REG(base) & XCVR_TSM_TIMING18_QGEN25_EN_RX_LO_MASK) >> XCVR_TSM_TIMING18_QGEN25_EN_RX_LO_SHIFT)
39603 #define XCVR_BRD_TSM_TIMING18_QGEN25_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING18_REG(base), XCVR_TSM_TIMING18_QGEN25_EN_RX_LO_SHIFT, XCVR_TSM_TIMING18_QGEN25_EN_RX_LO_WIDTH))
39604 
39605 /*! @brief Set the QGEN25_EN_RX_LO field to a new value. */
39606 #define XCVR_WR_TSM_TIMING18_QGEN25_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING18(base, XCVR_TSM_TIMING18_QGEN25_EN_RX_LO_MASK, XCVR_TSM_TIMING18_QGEN25_EN_RX_LO(value)))
39607 #define XCVR_BWR_TSM_TIMING18_QGEN25_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING18_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING18_QGEN25_EN_RX_LO_SHIFT), XCVR_TSM_TIMING18_QGEN25_EN_RX_LO_SHIFT, XCVR_TSM_TIMING18_QGEN25_EN_RX_LO_WIDTH))
39608 /*@}*/
39609 
39610 /*******************************************************************************
39611  * XCVR_TSM_TIMING19 - TSM_TIMING19
39612  ******************************************************************************/
39613 
39614 /*!
39615  * @brief XCVR_TSM_TIMING19 - TSM_TIMING19 (RW)
39616  *
39617  * Reset value: 0xFFFF6864U
39618  *
39619  * This register contains the timing values to control the assertion and
39620  * deassertion times for both TX and RX sequences for the TX_EN TSM signal or signal
39621  * group.
39622  */
39623 /*!
39624  * @name Constants and macros for entire XCVR_TSM_TIMING19 register
39625  */
39626 /*@{*/
39627 #define XCVR_RD_TSM_TIMING19(base) (XCVR_TSM_TIMING19_REG(base))
39628 #define XCVR_WR_TSM_TIMING19(base, value) (XCVR_TSM_TIMING19_REG(base) = (value))
39629 #define XCVR_RMW_TSM_TIMING19(base, mask, value) (XCVR_WR_TSM_TIMING19(base, (XCVR_RD_TSM_TIMING19(base) & ~(mask)) | (value)))
39630 #define XCVR_SET_TSM_TIMING19(base, value) (BME_OR32(&XCVR_TSM_TIMING19_REG(base), (uint32_t)(value)))
39631 #define XCVR_CLR_TSM_TIMING19(base, value) (BME_AND32(&XCVR_TSM_TIMING19_REG(base), (uint32_t)(~(value))))
39632 #define XCVR_TOG_TSM_TIMING19(base, value) (BME_XOR32(&XCVR_TSM_TIMING19_REG(base), (uint32_t)(value)))
39633 /*@}*/
39634 
39635 /*
39636  * Constants & macros for individual XCVR_TSM_TIMING19 bitfields
39637  */
39638 
39639 /*!
39640  * @name Register XCVR_TSM_TIMING19, field TX_EN_TX_HI[7:0] (RW)
39641  *
39642  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
39643  * at which the TX_EN signal or group will transition from LO to HI.
39644  */
39645 /*@{*/
39646 /*! @brief Read current value of the XCVR_TSM_TIMING19_TX_EN_TX_HI field. */
39647 #define XCVR_RD_TSM_TIMING19_TX_EN_TX_HI(base) ((XCVR_TSM_TIMING19_REG(base) & XCVR_TSM_TIMING19_TX_EN_TX_HI_MASK) >> XCVR_TSM_TIMING19_TX_EN_TX_HI_SHIFT)
39648 #define XCVR_BRD_TSM_TIMING19_TX_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING19_REG(base), XCVR_TSM_TIMING19_TX_EN_TX_HI_SHIFT, XCVR_TSM_TIMING19_TX_EN_TX_HI_WIDTH))
39649 
39650 /*! @brief Set the TX_EN_TX_HI field to a new value. */
39651 #define XCVR_WR_TSM_TIMING19_TX_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING19(base, XCVR_TSM_TIMING19_TX_EN_TX_HI_MASK, XCVR_TSM_TIMING19_TX_EN_TX_HI(value)))
39652 #define XCVR_BWR_TSM_TIMING19_TX_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING19_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING19_TX_EN_TX_HI_SHIFT), XCVR_TSM_TIMING19_TX_EN_TX_HI_SHIFT, XCVR_TSM_TIMING19_TX_EN_TX_HI_WIDTH))
39653 /*@}*/
39654 
39655 /*!
39656  * @name Register XCVR_TSM_TIMING19, field TX_EN_TX_LO[15:8] (RW)
39657  *
39658  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
39659  * at which the TX_EN signal or group will transition from HI to LO.
39660  */
39661 /*@{*/
39662 /*! @brief Read current value of the XCVR_TSM_TIMING19_TX_EN_TX_LO field. */
39663 #define XCVR_RD_TSM_TIMING19_TX_EN_TX_LO(base) ((XCVR_TSM_TIMING19_REG(base) & XCVR_TSM_TIMING19_TX_EN_TX_LO_MASK) >> XCVR_TSM_TIMING19_TX_EN_TX_LO_SHIFT)
39664 #define XCVR_BRD_TSM_TIMING19_TX_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING19_REG(base), XCVR_TSM_TIMING19_TX_EN_TX_LO_SHIFT, XCVR_TSM_TIMING19_TX_EN_TX_LO_WIDTH))
39665 
39666 /*! @brief Set the TX_EN_TX_LO field to a new value. */
39667 #define XCVR_WR_TSM_TIMING19_TX_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING19(base, XCVR_TSM_TIMING19_TX_EN_TX_LO_MASK, XCVR_TSM_TIMING19_TX_EN_TX_LO(value)))
39668 #define XCVR_BWR_TSM_TIMING19_TX_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING19_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING19_TX_EN_TX_LO_SHIFT), XCVR_TSM_TIMING19_TX_EN_TX_LO_SHIFT, XCVR_TSM_TIMING19_TX_EN_TX_LO_WIDTH))
39669 /*@}*/
39670 
39671 /*******************************************************************************
39672  * XCVR_TSM_TIMING20 - TSM_TIMING20
39673  ******************************************************************************/
39674 
39675 /*!
39676  * @brief XCVR_TSM_TIMING20 - TSM_TIMING20 (RW)
39677  *
39678  * Reset value: 0x651AFFFFU
39679  *
39680  * This register contains the timing values to control the assertion and
39681  * deassertion times for both TX and RX sequences for the ADC_EN TSM signal or signal
39682  * group.
39683  */
39684 /*!
39685  * @name Constants and macros for entire XCVR_TSM_TIMING20 register
39686  */
39687 /*@{*/
39688 #define XCVR_RD_TSM_TIMING20(base) (XCVR_TSM_TIMING20_REG(base))
39689 #define XCVR_WR_TSM_TIMING20(base, value) (XCVR_TSM_TIMING20_REG(base) = (value))
39690 #define XCVR_RMW_TSM_TIMING20(base, mask, value) (XCVR_WR_TSM_TIMING20(base, (XCVR_RD_TSM_TIMING20(base) & ~(mask)) | (value)))
39691 #define XCVR_SET_TSM_TIMING20(base, value) (BME_OR32(&XCVR_TSM_TIMING20_REG(base), (uint32_t)(value)))
39692 #define XCVR_CLR_TSM_TIMING20(base, value) (BME_AND32(&XCVR_TSM_TIMING20_REG(base), (uint32_t)(~(value))))
39693 #define XCVR_TOG_TSM_TIMING20(base, value) (BME_XOR32(&XCVR_TSM_TIMING20_REG(base), (uint32_t)(value)))
39694 /*@}*/
39695 
39696 /*
39697  * Constants & macros for individual XCVR_TSM_TIMING20 bitfields
39698  */
39699 
39700 /*!
39701  * @name Register XCVR_TSM_TIMING20, field ADC_EN_RX_HI[23:16] (RW)
39702  *
39703  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
39704  * at which the ADC_EN signal or group will transition from LO to HI.
39705  */
39706 /*@{*/
39707 /*! @brief Read current value of the XCVR_TSM_TIMING20_ADC_EN_RX_HI field. */
39708 #define XCVR_RD_TSM_TIMING20_ADC_EN_RX_HI(base) ((XCVR_TSM_TIMING20_REG(base) & XCVR_TSM_TIMING20_ADC_EN_RX_HI_MASK) >> XCVR_TSM_TIMING20_ADC_EN_RX_HI_SHIFT)
39709 #define XCVR_BRD_TSM_TIMING20_ADC_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING20_REG(base), XCVR_TSM_TIMING20_ADC_EN_RX_HI_SHIFT, XCVR_TSM_TIMING20_ADC_EN_RX_HI_WIDTH))
39710 
39711 /*! @brief Set the ADC_EN_RX_HI field to a new value. */
39712 #define XCVR_WR_TSM_TIMING20_ADC_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING20(base, XCVR_TSM_TIMING20_ADC_EN_RX_HI_MASK, XCVR_TSM_TIMING20_ADC_EN_RX_HI(value)))
39713 #define XCVR_BWR_TSM_TIMING20_ADC_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING20_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING20_ADC_EN_RX_HI_SHIFT), XCVR_TSM_TIMING20_ADC_EN_RX_HI_SHIFT, XCVR_TSM_TIMING20_ADC_EN_RX_HI_WIDTH))
39714 /*@}*/
39715 
39716 /*!
39717  * @name Register XCVR_TSM_TIMING20, field ADC_EN_RX_LO[31:24] (RW)
39718  *
39719  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
39720  * at which the ADC_EN signal or group will transition from HI to LO.
39721  */
39722 /*@{*/
39723 /*! @brief Read current value of the XCVR_TSM_TIMING20_ADC_EN_RX_LO field. */
39724 #define XCVR_RD_TSM_TIMING20_ADC_EN_RX_LO(base) ((XCVR_TSM_TIMING20_REG(base) & XCVR_TSM_TIMING20_ADC_EN_RX_LO_MASK) >> XCVR_TSM_TIMING20_ADC_EN_RX_LO_SHIFT)
39725 #define XCVR_BRD_TSM_TIMING20_ADC_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING20_REG(base), XCVR_TSM_TIMING20_ADC_EN_RX_LO_SHIFT, XCVR_TSM_TIMING20_ADC_EN_RX_LO_WIDTH))
39726 
39727 /*! @brief Set the ADC_EN_RX_LO field to a new value. */
39728 #define XCVR_WR_TSM_TIMING20_ADC_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING20(base, XCVR_TSM_TIMING20_ADC_EN_RX_LO_MASK, XCVR_TSM_TIMING20_ADC_EN_RX_LO(value)))
39729 #define XCVR_BWR_TSM_TIMING20_ADC_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING20_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING20_ADC_EN_RX_LO_SHIFT), XCVR_TSM_TIMING20_ADC_EN_RX_LO_SHIFT, XCVR_TSM_TIMING20_ADC_EN_RX_LO_WIDTH))
39730 /*@}*/
39731 
39732 /*******************************************************************************
39733  * XCVR_TSM_TIMING21 - TSM_TIMING21
39734  ******************************************************************************/
39735 
39736 /*!
39737  * @brief XCVR_TSM_TIMING21 - TSM_TIMING21 (RW)
39738  *
39739  * Reset value: 0x651AFFFFU
39740  *
39741  * This register contains the timing values to control the assertion and
39742  * deassertion times for both TX and RX sequences for the ADC_I_Q_EN TSM signal or
39743  * signal group.
39744  */
39745 /*!
39746  * @name Constants and macros for entire XCVR_TSM_TIMING21 register
39747  */
39748 /*@{*/
39749 #define XCVR_RD_TSM_TIMING21(base) (XCVR_TSM_TIMING21_REG(base))
39750 #define XCVR_WR_TSM_TIMING21(base, value) (XCVR_TSM_TIMING21_REG(base) = (value))
39751 #define XCVR_RMW_TSM_TIMING21(base, mask, value) (XCVR_WR_TSM_TIMING21(base, (XCVR_RD_TSM_TIMING21(base) & ~(mask)) | (value)))
39752 #define XCVR_SET_TSM_TIMING21(base, value) (BME_OR32(&XCVR_TSM_TIMING21_REG(base), (uint32_t)(value)))
39753 #define XCVR_CLR_TSM_TIMING21(base, value) (BME_AND32(&XCVR_TSM_TIMING21_REG(base), (uint32_t)(~(value))))
39754 #define XCVR_TOG_TSM_TIMING21(base, value) (BME_XOR32(&XCVR_TSM_TIMING21_REG(base), (uint32_t)(value)))
39755 /*@}*/
39756 
39757 /*
39758  * Constants & macros for individual XCVR_TSM_TIMING21 bitfields
39759  */
39760 
39761 /*!
39762  * @name Register XCVR_TSM_TIMING21, field ADC_I_Q_EN_RX_HI[23:16] (RW)
39763  *
39764  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
39765  * at which the ADC_I_Q_EN signal or group will transition from LO to HI.
39766  */
39767 /*@{*/
39768 /*! @brief Read current value of the XCVR_TSM_TIMING21_ADC_I_Q_EN_RX_HI field. */
39769 #define XCVR_RD_TSM_TIMING21_ADC_I_Q_EN_RX_HI(base) ((XCVR_TSM_TIMING21_REG(base) & XCVR_TSM_TIMING21_ADC_I_Q_EN_RX_HI_MASK) >> XCVR_TSM_TIMING21_ADC_I_Q_EN_RX_HI_SHIFT)
39770 #define XCVR_BRD_TSM_TIMING21_ADC_I_Q_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING21_REG(base), XCVR_TSM_TIMING21_ADC_I_Q_EN_RX_HI_SHIFT, XCVR_TSM_TIMING21_ADC_I_Q_EN_RX_HI_WIDTH))
39771 
39772 /*! @brief Set the ADC_I_Q_EN_RX_HI field to a new value. */
39773 #define XCVR_WR_TSM_TIMING21_ADC_I_Q_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING21(base, XCVR_TSM_TIMING21_ADC_I_Q_EN_RX_HI_MASK, XCVR_TSM_TIMING21_ADC_I_Q_EN_RX_HI(value)))
39774 #define XCVR_BWR_TSM_TIMING21_ADC_I_Q_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING21_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING21_ADC_I_Q_EN_RX_HI_SHIFT), XCVR_TSM_TIMING21_ADC_I_Q_EN_RX_HI_SHIFT, XCVR_TSM_TIMING21_ADC_I_Q_EN_RX_HI_WIDTH))
39775 /*@}*/
39776 
39777 /*!
39778  * @name Register XCVR_TSM_TIMING21, field ADC_I_Q_EN_RX_LO[31:24] (RW)
39779  *
39780  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
39781  * at which the ADC_I_Q_EN signal or group will transition from HI to LO.
39782  */
39783 /*@{*/
39784 /*! @brief Read current value of the XCVR_TSM_TIMING21_ADC_I_Q_EN_RX_LO field. */
39785 #define XCVR_RD_TSM_TIMING21_ADC_I_Q_EN_RX_LO(base) ((XCVR_TSM_TIMING21_REG(base) & XCVR_TSM_TIMING21_ADC_I_Q_EN_RX_LO_MASK) >> XCVR_TSM_TIMING21_ADC_I_Q_EN_RX_LO_SHIFT)
39786 #define XCVR_BRD_TSM_TIMING21_ADC_I_Q_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING21_REG(base), XCVR_TSM_TIMING21_ADC_I_Q_EN_RX_LO_SHIFT, XCVR_TSM_TIMING21_ADC_I_Q_EN_RX_LO_WIDTH))
39787 
39788 /*! @brief Set the ADC_I_Q_EN_RX_LO field to a new value. */
39789 #define XCVR_WR_TSM_TIMING21_ADC_I_Q_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING21(base, XCVR_TSM_TIMING21_ADC_I_Q_EN_RX_LO_MASK, XCVR_TSM_TIMING21_ADC_I_Q_EN_RX_LO(value)))
39790 #define XCVR_BWR_TSM_TIMING21_ADC_I_Q_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING21_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING21_ADC_I_Q_EN_RX_LO_SHIFT), XCVR_TSM_TIMING21_ADC_I_Q_EN_RX_LO_SHIFT, XCVR_TSM_TIMING21_ADC_I_Q_EN_RX_LO_WIDTH))
39791 /*@}*/
39792 
39793 /*******************************************************************************
39794  * XCVR_TSM_TIMING22 - TSM_TIMING22
39795  ******************************************************************************/
39796 
39797 /*!
39798  * @brief XCVR_TSM_TIMING22 - TSM_TIMING22 (RW)
39799  *
39800  * Reset value: 0x651AFFFFU
39801  *
39802  * This register contains the timing values to control the assertion and
39803  * deassertion times for both TX and RX sequences for the ADC_DAC_EN TSM signal or
39804  * signal group.
39805  */
39806 /*!
39807  * @name Constants and macros for entire XCVR_TSM_TIMING22 register
39808  */
39809 /*@{*/
39810 #define XCVR_RD_TSM_TIMING22(base) (XCVR_TSM_TIMING22_REG(base))
39811 #define XCVR_WR_TSM_TIMING22(base, value) (XCVR_TSM_TIMING22_REG(base) = (value))
39812 #define XCVR_RMW_TSM_TIMING22(base, mask, value) (XCVR_WR_TSM_TIMING22(base, (XCVR_RD_TSM_TIMING22(base) & ~(mask)) | (value)))
39813 #define XCVR_SET_TSM_TIMING22(base, value) (BME_OR32(&XCVR_TSM_TIMING22_REG(base), (uint32_t)(value)))
39814 #define XCVR_CLR_TSM_TIMING22(base, value) (BME_AND32(&XCVR_TSM_TIMING22_REG(base), (uint32_t)(~(value))))
39815 #define XCVR_TOG_TSM_TIMING22(base, value) (BME_XOR32(&XCVR_TSM_TIMING22_REG(base), (uint32_t)(value)))
39816 /*@}*/
39817 
39818 /*
39819  * Constants & macros for individual XCVR_TSM_TIMING22 bitfields
39820  */
39821 
39822 /*!
39823  * @name Register XCVR_TSM_TIMING22, field ADC_DAC_EN_RX_HI[23:16] (RW)
39824  *
39825  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
39826  * at which the ADC_DAC_EN signal or group will transition from LO to HI.
39827  */
39828 /*@{*/
39829 /*! @brief Read current value of the XCVR_TSM_TIMING22_ADC_DAC_EN_RX_HI field. */
39830 #define XCVR_RD_TSM_TIMING22_ADC_DAC_EN_RX_HI(base) ((XCVR_TSM_TIMING22_REG(base) & XCVR_TSM_TIMING22_ADC_DAC_EN_RX_HI_MASK) >> XCVR_TSM_TIMING22_ADC_DAC_EN_RX_HI_SHIFT)
39831 #define XCVR_BRD_TSM_TIMING22_ADC_DAC_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING22_REG(base), XCVR_TSM_TIMING22_ADC_DAC_EN_RX_HI_SHIFT, XCVR_TSM_TIMING22_ADC_DAC_EN_RX_HI_WIDTH))
39832 
39833 /*! @brief Set the ADC_DAC_EN_RX_HI field to a new value. */
39834 #define XCVR_WR_TSM_TIMING22_ADC_DAC_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING22(base, XCVR_TSM_TIMING22_ADC_DAC_EN_RX_HI_MASK, XCVR_TSM_TIMING22_ADC_DAC_EN_RX_HI(value)))
39835 #define XCVR_BWR_TSM_TIMING22_ADC_DAC_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING22_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING22_ADC_DAC_EN_RX_HI_SHIFT), XCVR_TSM_TIMING22_ADC_DAC_EN_RX_HI_SHIFT, XCVR_TSM_TIMING22_ADC_DAC_EN_RX_HI_WIDTH))
39836 /*@}*/
39837 
39838 /*!
39839  * @name Register XCVR_TSM_TIMING22, field ADC_DAC_EN_RX_LO[31:24] (RW)
39840  *
39841  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
39842  * at which the ADC_DAC_EN signal or group will transition from HI to LO.
39843  */
39844 /*@{*/
39845 /*! @brief Read current value of the XCVR_TSM_TIMING22_ADC_DAC_EN_RX_LO field. */
39846 #define XCVR_RD_TSM_TIMING22_ADC_DAC_EN_RX_LO(base) ((XCVR_TSM_TIMING22_REG(base) & XCVR_TSM_TIMING22_ADC_DAC_EN_RX_LO_MASK) >> XCVR_TSM_TIMING22_ADC_DAC_EN_RX_LO_SHIFT)
39847 #define XCVR_BRD_TSM_TIMING22_ADC_DAC_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING22_REG(base), XCVR_TSM_TIMING22_ADC_DAC_EN_RX_LO_SHIFT, XCVR_TSM_TIMING22_ADC_DAC_EN_RX_LO_WIDTH))
39848 
39849 /*! @brief Set the ADC_DAC_EN_RX_LO field to a new value. */
39850 #define XCVR_WR_TSM_TIMING22_ADC_DAC_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING22(base, XCVR_TSM_TIMING22_ADC_DAC_EN_RX_LO_MASK, XCVR_TSM_TIMING22_ADC_DAC_EN_RX_LO(value)))
39851 #define XCVR_BWR_TSM_TIMING22_ADC_DAC_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING22_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING22_ADC_DAC_EN_RX_LO_SHIFT), XCVR_TSM_TIMING22_ADC_DAC_EN_RX_LO_SHIFT, XCVR_TSM_TIMING22_ADC_DAC_EN_RX_LO_WIDTH))
39852 /*@}*/
39853 
39854 /*******************************************************************************
39855  * XCVR_TSM_TIMING23 - TSM_TIMING23
39856  ******************************************************************************/
39857 
39858 /*!
39859  * @brief XCVR_TSM_TIMING23 - TSM_TIMING23 (RW)
39860  *
39861  * Reset value: 0x651AFFFFU
39862  *
39863  * This register contains the timing values to control the assertion and
39864  * deassertion times for both TX and RX sequences for the ADC_RST_EN TSM signal or
39865  * signal group.
39866  */
39867 /*!
39868  * @name Constants and macros for entire XCVR_TSM_TIMING23 register
39869  */
39870 /*@{*/
39871 #define XCVR_RD_TSM_TIMING23(base) (XCVR_TSM_TIMING23_REG(base))
39872 #define XCVR_WR_TSM_TIMING23(base, value) (XCVR_TSM_TIMING23_REG(base) = (value))
39873 #define XCVR_RMW_TSM_TIMING23(base, mask, value) (XCVR_WR_TSM_TIMING23(base, (XCVR_RD_TSM_TIMING23(base) & ~(mask)) | (value)))
39874 #define XCVR_SET_TSM_TIMING23(base, value) (BME_OR32(&XCVR_TSM_TIMING23_REG(base), (uint32_t)(value)))
39875 #define XCVR_CLR_TSM_TIMING23(base, value) (BME_AND32(&XCVR_TSM_TIMING23_REG(base), (uint32_t)(~(value))))
39876 #define XCVR_TOG_TSM_TIMING23(base, value) (BME_XOR32(&XCVR_TSM_TIMING23_REG(base), (uint32_t)(value)))
39877 /*@}*/
39878 
39879 /*
39880  * Constants & macros for individual XCVR_TSM_TIMING23 bitfields
39881  */
39882 
39883 /*!
39884  * @name Register XCVR_TSM_TIMING23, field ADC_RST_EN_RX_HI[23:16] (RW)
39885  *
39886  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
39887  * at which the ADC_RST_EN signal or group will transition from LO to HI.
39888  */
39889 /*@{*/
39890 /*! @brief Read current value of the XCVR_TSM_TIMING23_ADC_RST_EN_RX_HI field. */
39891 #define XCVR_RD_TSM_TIMING23_ADC_RST_EN_RX_HI(base) ((XCVR_TSM_TIMING23_REG(base) & XCVR_TSM_TIMING23_ADC_RST_EN_RX_HI_MASK) >> XCVR_TSM_TIMING23_ADC_RST_EN_RX_HI_SHIFT)
39892 #define XCVR_BRD_TSM_TIMING23_ADC_RST_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING23_REG(base), XCVR_TSM_TIMING23_ADC_RST_EN_RX_HI_SHIFT, XCVR_TSM_TIMING23_ADC_RST_EN_RX_HI_WIDTH))
39893 
39894 /*! @brief Set the ADC_RST_EN_RX_HI field to a new value. */
39895 #define XCVR_WR_TSM_TIMING23_ADC_RST_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING23(base, XCVR_TSM_TIMING23_ADC_RST_EN_RX_HI_MASK, XCVR_TSM_TIMING23_ADC_RST_EN_RX_HI(value)))
39896 #define XCVR_BWR_TSM_TIMING23_ADC_RST_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING23_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING23_ADC_RST_EN_RX_HI_SHIFT), XCVR_TSM_TIMING23_ADC_RST_EN_RX_HI_SHIFT, XCVR_TSM_TIMING23_ADC_RST_EN_RX_HI_WIDTH))
39897 /*@}*/
39898 
39899 /*!
39900  * @name Register XCVR_TSM_TIMING23, field ADC_RST_EN_RX_LO[31:24] (RW)
39901  *
39902  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
39903  * at which the ADC_RST_EN signal or group will transition from HI to LO.
39904  */
39905 /*@{*/
39906 /*! @brief Read current value of the XCVR_TSM_TIMING23_ADC_RST_EN_RX_LO field. */
39907 #define XCVR_RD_TSM_TIMING23_ADC_RST_EN_RX_LO(base) ((XCVR_TSM_TIMING23_REG(base) & XCVR_TSM_TIMING23_ADC_RST_EN_RX_LO_MASK) >> XCVR_TSM_TIMING23_ADC_RST_EN_RX_LO_SHIFT)
39908 #define XCVR_BRD_TSM_TIMING23_ADC_RST_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING23_REG(base), XCVR_TSM_TIMING23_ADC_RST_EN_RX_LO_SHIFT, XCVR_TSM_TIMING23_ADC_RST_EN_RX_LO_WIDTH))
39909 
39910 /*! @brief Set the ADC_RST_EN_RX_LO field to a new value. */
39911 #define XCVR_WR_TSM_TIMING23_ADC_RST_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING23(base, XCVR_TSM_TIMING23_ADC_RST_EN_RX_LO_MASK, XCVR_TSM_TIMING23_ADC_RST_EN_RX_LO(value)))
39912 #define XCVR_BWR_TSM_TIMING23_ADC_RST_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING23_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING23_ADC_RST_EN_RX_LO_SHIFT), XCVR_TSM_TIMING23_ADC_RST_EN_RX_LO_SHIFT, XCVR_TSM_TIMING23_ADC_RST_EN_RX_LO_WIDTH))
39913 /*@}*/
39914 
39915 /*******************************************************************************
39916  * XCVR_TSM_TIMING24 - TSM_TIMING24
39917  ******************************************************************************/
39918 
39919 /*!
39920  * @brief XCVR_TSM_TIMING24 - TSM_TIMING24 (RW)
39921  *
39922  * Reset value: 0x6518FFFFU
39923  *
39924  * This register contains the timing values to control the assertion and
39925  * deassertion times for both TX and RX sequences for the BBF_EN TSM signal or signal
39926  * group.
39927  */
39928 /*!
39929  * @name Constants and macros for entire XCVR_TSM_TIMING24 register
39930  */
39931 /*@{*/
39932 #define XCVR_RD_TSM_TIMING24(base) (XCVR_TSM_TIMING24_REG(base))
39933 #define XCVR_WR_TSM_TIMING24(base, value) (XCVR_TSM_TIMING24_REG(base) = (value))
39934 #define XCVR_RMW_TSM_TIMING24(base, mask, value) (XCVR_WR_TSM_TIMING24(base, (XCVR_RD_TSM_TIMING24(base) & ~(mask)) | (value)))
39935 #define XCVR_SET_TSM_TIMING24(base, value) (BME_OR32(&XCVR_TSM_TIMING24_REG(base), (uint32_t)(value)))
39936 #define XCVR_CLR_TSM_TIMING24(base, value) (BME_AND32(&XCVR_TSM_TIMING24_REG(base), (uint32_t)(~(value))))
39937 #define XCVR_TOG_TSM_TIMING24(base, value) (BME_XOR32(&XCVR_TSM_TIMING24_REG(base), (uint32_t)(value)))
39938 /*@}*/
39939 
39940 /*
39941  * Constants & macros for individual XCVR_TSM_TIMING24 bitfields
39942  */
39943 
39944 /*!
39945  * @name Register XCVR_TSM_TIMING24, field BBF_EN_RX_HI[23:16] (RW)
39946  *
39947  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
39948  * at which the BBF_EN signal or group will transition from LO to HI.
39949  */
39950 /*@{*/
39951 /*! @brief Read current value of the XCVR_TSM_TIMING24_BBF_EN_RX_HI field. */
39952 #define XCVR_RD_TSM_TIMING24_BBF_EN_RX_HI(base) ((XCVR_TSM_TIMING24_REG(base) & XCVR_TSM_TIMING24_BBF_EN_RX_HI_MASK) >> XCVR_TSM_TIMING24_BBF_EN_RX_HI_SHIFT)
39953 #define XCVR_BRD_TSM_TIMING24_BBF_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING24_REG(base), XCVR_TSM_TIMING24_BBF_EN_RX_HI_SHIFT, XCVR_TSM_TIMING24_BBF_EN_RX_HI_WIDTH))
39954 
39955 /*! @brief Set the BBF_EN_RX_HI field to a new value. */
39956 #define XCVR_WR_TSM_TIMING24_BBF_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING24(base, XCVR_TSM_TIMING24_BBF_EN_RX_HI_MASK, XCVR_TSM_TIMING24_BBF_EN_RX_HI(value)))
39957 #define XCVR_BWR_TSM_TIMING24_BBF_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING24_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING24_BBF_EN_RX_HI_SHIFT), XCVR_TSM_TIMING24_BBF_EN_RX_HI_SHIFT, XCVR_TSM_TIMING24_BBF_EN_RX_HI_WIDTH))
39958 /*@}*/
39959 
39960 /*!
39961  * @name Register XCVR_TSM_TIMING24, field BBF_EN_RX_LO[31:24] (RW)
39962  *
39963  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
39964  * at which the BBF_EN signal or group will transition from HI to LO.
39965  */
39966 /*@{*/
39967 /*! @brief Read current value of the XCVR_TSM_TIMING24_BBF_EN_RX_LO field. */
39968 #define XCVR_RD_TSM_TIMING24_BBF_EN_RX_LO(base) ((XCVR_TSM_TIMING24_REG(base) & XCVR_TSM_TIMING24_BBF_EN_RX_LO_MASK) >> XCVR_TSM_TIMING24_BBF_EN_RX_LO_SHIFT)
39969 #define XCVR_BRD_TSM_TIMING24_BBF_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING24_REG(base), XCVR_TSM_TIMING24_BBF_EN_RX_LO_SHIFT, XCVR_TSM_TIMING24_BBF_EN_RX_LO_WIDTH))
39970 
39971 /*! @brief Set the BBF_EN_RX_LO field to a new value. */
39972 #define XCVR_WR_TSM_TIMING24_BBF_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING24(base, XCVR_TSM_TIMING24_BBF_EN_RX_LO_MASK, XCVR_TSM_TIMING24_BBF_EN_RX_LO(value)))
39973 #define XCVR_BWR_TSM_TIMING24_BBF_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING24_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING24_BBF_EN_RX_LO_SHIFT), XCVR_TSM_TIMING24_BBF_EN_RX_LO_SHIFT, XCVR_TSM_TIMING24_BBF_EN_RX_LO_WIDTH))
39974 /*@}*/
39975 
39976 /*******************************************************************************
39977  * XCVR_TSM_TIMING25 - TSM_TIMING25
39978  ******************************************************************************/
39979 
39980 /*!
39981  * @brief XCVR_TSM_TIMING25 - TSM_TIMING25 (RW)
39982  *
39983  * Reset value: 0x6518FFFFU
39984  *
39985  * This register contains the timing values to control the assertion and
39986  * deassertion times for both TX and RX sequences for the TCA_EN TSM signal or signal
39987  * group.
39988  */
39989 /*!
39990  * @name Constants and macros for entire XCVR_TSM_TIMING25 register
39991  */
39992 /*@{*/
39993 #define XCVR_RD_TSM_TIMING25(base) (XCVR_TSM_TIMING25_REG(base))
39994 #define XCVR_WR_TSM_TIMING25(base, value) (XCVR_TSM_TIMING25_REG(base) = (value))
39995 #define XCVR_RMW_TSM_TIMING25(base, mask, value) (XCVR_WR_TSM_TIMING25(base, (XCVR_RD_TSM_TIMING25(base) & ~(mask)) | (value)))
39996 #define XCVR_SET_TSM_TIMING25(base, value) (BME_OR32(&XCVR_TSM_TIMING25_REG(base), (uint32_t)(value)))
39997 #define XCVR_CLR_TSM_TIMING25(base, value) (BME_AND32(&XCVR_TSM_TIMING25_REG(base), (uint32_t)(~(value))))
39998 #define XCVR_TOG_TSM_TIMING25(base, value) (BME_XOR32(&XCVR_TSM_TIMING25_REG(base), (uint32_t)(value)))
39999 /*@}*/
40000 
40001 /*
40002  * Constants & macros for individual XCVR_TSM_TIMING25 bitfields
40003  */
40004 
40005 /*!
40006  * @name Register XCVR_TSM_TIMING25, field TCA_EN_RX_HI[23:16] (RW)
40007  *
40008  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40009  * at which the TCA_EN signal or group will transition from LO to HI.
40010  */
40011 /*@{*/
40012 /*! @brief Read current value of the XCVR_TSM_TIMING25_TCA_EN_RX_HI field. */
40013 #define XCVR_RD_TSM_TIMING25_TCA_EN_RX_HI(base) ((XCVR_TSM_TIMING25_REG(base) & XCVR_TSM_TIMING25_TCA_EN_RX_HI_MASK) >> XCVR_TSM_TIMING25_TCA_EN_RX_HI_SHIFT)
40014 #define XCVR_BRD_TSM_TIMING25_TCA_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING25_REG(base), XCVR_TSM_TIMING25_TCA_EN_RX_HI_SHIFT, XCVR_TSM_TIMING25_TCA_EN_RX_HI_WIDTH))
40015 
40016 /*! @brief Set the TCA_EN_RX_HI field to a new value. */
40017 #define XCVR_WR_TSM_TIMING25_TCA_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING25(base, XCVR_TSM_TIMING25_TCA_EN_RX_HI_MASK, XCVR_TSM_TIMING25_TCA_EN_RX_HI(value)))
40018 #define XCVR_BWR_TSM_TIMING25_TCA_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING25_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING25_TCA_EN_RX_HI_SHIFT), XCVR_TSM_TIMING25_TCA_EN_RX_HI_SHIFT, XCVR_TSM_TIMING25_TCA_EN_RX_HI_WIDTH))
40019 /*@}*/
40020 
40021 /*!
40022  * @name Register XCVR_TSM_TIMING25, field TCA_EN_RX_LO[31:24] (RW)
40023  *
40024  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40025  * at which the TCA_EN signal or group will transition from HI to LO.
40026  */
40027 /*@{*/
40028 /*! @brief Read current value of the XCVR_TSM_TIMING25_TCA_EN_RX_LO field. */
40029 #define XCVR_RD_TSM_TIMING25_TCA_EN_RX_LO(base) ((XCVR_TSM_TIMING25_REG(base) & XCVR_TSM_TIMING25_TCA_EN_RX_LO_MASK) >> XCVR_TSM_TIMING25_TCA_EN_RX_LO_SHIFT)
40030 #define XCVR_BRD_TSM_TIMING25_TCA_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING25_REG(base), XCVR_TSM_TIMING25_TCA_EN_RX_LO_SHIFT, XCVR_TSM_TIMING25_TCA_EN_RX_LO_WIDTH))
40031 
40032 /*! @brief Set the TCA_EN_RX_LO field to a new value. */
40033 #define XCVR_WR_TSM_TIMING25_TCA_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING25(base, XCVR_TSM_TIMING25_TCA_EN_RX_LO_MASK, XCVR_TSM_TIMING25_TCA_EN_RX_LO(value)))
40034 #define XCVR_BWR_TSM_TIMING25_TCA_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING25_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING25_TCA_EN_RX_LO_SHIFT), XCVR_TSM_TIMING25_TCA_EN_RX_LO_SHIFT, XCVR_TSM_TIMING25_TCA_EN_RX_LO_WIDTH))
40035 /*@}*/
40036 
40037 /*******************************************************************************
40038  * XCVR_TSM_TIMING26 - TSM_TIMING26
40039  ******************************************************************************/
40040 
40041 /*!
40042  * @brief XCVR_TSM_TIMING26 - TSM_TIMING26 (RW)
40043  *
40044  * Reset value: 0x65096A09U
40045  *
40046  * This register contains the timing values to control the assertion and
40047  * deassertion times for both TX and RX sequences for the PLL_DIG_EN TSM signal or
40048  * signal group.
40049  */
40050 /*!
40051  * @name Constants and macros for entire XCVR_TSM_TIMING26 register
40052  */
40053 /*@{*/
40054 #define XCVR_RD_TSM_TIMING26(base) (XCVR_TSM_TIMING26_REG(base))
40055 #define XCVR_WR_TSM_TIMING26(base, value) (XCVR_TSM_TIMING26_REG(base) = (value))
40056 #define XCVR_RMW_TSM_TIMING26(base, mask, value) (XCVR_WR_TSM_TIMING26(base, (XCVR_RD_TSM_TIMING26(base) & ~(mask)) | (value)))
40057 #define XCVR_SET_TSM_TIMING26(base, value) (BME_OR32(&XCVR_TSM_TIMING26_REG(base), (uint32_t)(value)))
40058 #define XCVR_CLR_TSM_TIMING26(base, value) (BME_AND32(&XCVR_TSM_TIMING26_REG(base), (uint32_t)(~(value))))
40059 #define XCVR_TOG_TSM_TIMING26(base, value) (BME_XOR32(&XCVR_TSM_TIMING26_REG(base), (uint32_t)(value)))
40060 /*@}*/
40061 
40062 /*
40063  * Constants & macros for individual XCVR_TSM_TIMING26 bitfields
40064  */
40065 
40066 /*!
40067  * @name Register XCVR_TSM_TIMING26, field PLL_DIG_EN_TX_HI[7:0] (RW)
40068  *
40069  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
40070  * at which the PLL_DIG_EN signal or group will transition from LO to HI.
40071  */
40072 /*@{*/
40073 /*! @brief Read current value of the XCVR_TSM_TIMING26_PLL_DIG_EN_TX_HI field. */
40074 #define XCVR_RD_TSM_TIMING26_PLL_DIG_EN_TX_HI(base) ((XCVR_TSM_TIMING26_REG(base) & XCVR_TSM_TIMING26_PLL_DIG_EN_TX_HI_MASK) >> XCVR_TSM_TIMING26_PLL_DIG_EN_TX_HI_SHIFT)
40075 #define XCVR_BRD_TSM_TIMING26_PLL_DIG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING26_REG(base), XCVR_TSM_TIMING26_PLL_DIG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING26_PLL_DIG_EN_TX_HI_WIDTH))
40076 
40077 /*! @brief Set the PLL_DIG_EN_TX_HI field to a new value. */
40078 #define XCVR_WR_TSM_TIMING26_PLL_DIG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING26(base, XCVR_TSM_TIMING26_PLL_DIG_EN_TX_HI_MASK, XCVR_TSM_TIMING26_PLL_DIG_EN_TX_HI(value)))
40079 #define XCVR_BWR_TSM_TIMING26_PLL_DIG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING26_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING26_PLL_DIG_EN_TX_HI_SHIFT), XCVR_TSM_TIMING26_PLL_DIG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING26_PLL_DIG_EN_TX_HI_WIDTH))
40080 /*@}*/
40081 
40082 /*!
40083  * @name Register XCVR_TSM_TIMING26, field PLL_DIG_EN_TX_LO[15:8] (RW)
40084  *
40085  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
40086  * at which the PLL_DIG_EN signal or group will transition from HI to LO.
40087  */
40088 /*@{*/
40089 /*! @brief Read current value of the XCVR_TSM_TIMING26_PLL_DIG_EN_TX_LO field. */
40090 #define XCVR_RD_TSM_TIMING26_PLL_DIG_EN_TX_LO(base) ((XCVR_TSM_TIMING26_REG(base) & XCVR_TSM_TIMING26_PLL_DIG_EN_TX_LO_MASK) >> XCVR_TSM_TIMING26_PLL_DIG_EN_TX_LO_SHIFT)
40091 #define XCVR_BRD_TSM_TIMING26_PLL_DIG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING26_REG(base), XCVR_TSM_TIMING26_PLL_DIG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING26_PLL_DIG_EN_TX_LO_WIDTH))
40092 
40093 /*! @brief Set the PLL_DIG_EN_TX_LO field to a new value. */
40094 #define XCVR_WR_TSM_TIMING26_PLL_DIG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING26(base, XCVR_TSM_TIMING26_PLL_DIG_EN_TX_LO_MASK, XCVR_TSM_TIMING26_PLL_DIG_EN_TX_LO(value)))
40095 #define XCVR_BWR_TSM_TIMING26_PLL_DIG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING26_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING26_PLL_DIG_EN_TX_LO_SHIFT), XCVR_TSM_TIMING26_PLL_DIG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING26_PLL_DIG_EN_TX_LO_WIDTH))
40096 /*@}*/
40097 
40098 /*!
40099  * @name Register XCVR_TSM_TIMING26, field PLL_DIG_EN_RX_HI[23:16] (RW)
40100  *
40101  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40102  * at which the PLL_DIG_EN signal or group will transition from LO to HI.
40103  */
40104 /*@{*/
40105 /*! @brief Read current value of the XCVR_TSM_TIMING26_PLL_DIG_EN_RX_HI field. */
40106 #define XCVR_RD_TSM_TIMING26_PLL_DIG_EN_RX_HI(base) ((XCVR_TSM_TIMING26_REG(base) & XCVR_TSM_TIMING26_PLL_DIG_EN_RX_HI_MASK) >> XCVR_TSM_TIMING26_PLL_DIG_EN_RX_HI_SHIFT)
40107 #define XCVR_BRD_TSM_TIMING26_PLL_DIG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING26_REG(base), XCVR_TSM_TIMING26_PLL_DIG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING26_PLL_DIG_EN_RX_HI_WIDTH))
40108 
40109 /*! @brief Set the PLL_DIG_EN_RX_HI field to a new value. */
40110 #define XCVR_WR_TSM_TIMING26_PLL_DIG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING26(base, XCVR_TSM_TIMING26_PLL_DIG_EN_RX_HI_MASK, XCVR_TSM_TIMING26_PLL_DIG_EN_RX_HI(value)))
40111 #define XCVR_BWR_TSM_TIMING26_PLL_DIG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING26_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING26_PLL_DIG_EN_RX_HI_SHIFT), XCVR_TSM_TIMING26_PLL_DIG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING26_PLL_DIG_EN_RX_HI_WIDTH))
40112 /*@}*/
40113 
40114 /*!
40115  * @name Register XCVR_TSM_TIMING26, field PLL_DIG_EN_RX_LO[31:24] (RW)
40116  *
40117  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40118  * at which the PLL_DIG_EN signal or group will transition from HI to LO.
40119  */
40120 /*@{*/
40121 /*! @brief Read current value of the XCVR_TSM_TIMING26_PLL_DIG_EN_RX_LO field. */
40122 #define XCVR_RD_TSM_TIMING26_PLL_DIG_EN_RX_LO(base) ((XCVR_TSM_TIMING26_REG(base) & XCVR_TSM_TIMING26_PLL_DIG_EN_RX_LO_MASK) >> XCVR_TSM_TIMING26_PLL_DIG_EN_RX_LO_SHIFT)
40123 #define XCVR_BRD_TSM_TIMING26_PLL_DIG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING26_REG(base), XCVR_TSM_TIMING26_PLL_DIG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING26_PLL_DIG_EN_RX_LO_WIDTH))
40124 
40125 /*! @brief Set the PLL_DIG_EN_RX_LO field to a new value. */
40126 #define XCVR_WR_TSM_TIMING26_PLL_DIG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING26(base, XCVR_TSM_TIMING26_PLL_DIG_EN_RX_LO_MASK, XCVR_TSM_TIMING26_PLL_DIG_EN_RX_LO(value)))
40127 #define XCVR_BWR_TSM_TIMING26_PLL_DIG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING26_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING26_PLL_DIG_EN_RX_LO_SHIFT), XCVR_TSM_TIMING26_PLL_DIG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING26_PLL_DIG_EN_RX_LO_WIDTH))
40128 /*@}*/
40129 
40130 /*******************************************************************************
40131  * XCVR_TSM_TIMING27 - TSM_TIMING27
40132  ******************************************************************************/
40133 
40134 /*!
40135  * @brief XCVR_TSM_TIMING27 - TSM_TIMING27 (RW)
40136  *
40137  * Reset value: 0xFFFF6A67U
40138  *
40139  * This register contains the timing values to control the assertion and
40140  * deassertion times for both TX and RX sequences for the TX_DIG_EN TSM signal or signal
40141  * group.
40142  */
40143 /*!
40144  * @name Constants and macros for entire XCVR_TSM_TIMING27 register
40145  */
40146 /*@{*/
40147 #define XCVR_RD_TSM_TIMING27(base) (XCVR_TSM_TIMING27_REG(base))
40148 #define XCVR_WR_TSM_TIMING27(base, value) (XCVR_TSM_TIMING27_REG(base) = (value))
40149 #define XCVR_RMW_TSM_TIMING27(base, mask, value) (XCVR_WR_TSM_TIMING27(base, (XCVR_RD_TSM_TIMING27(base) & ~(mask)) | (value)))
40150 #define XCVR_SET_TSM_TIMING27(base, value) (BME_OR32(&XCVR_TSM_TIMING27_REG(base), (uint32_t)(value)))
40151 #define XCVR_CLR_TSM_TIMING27(base, value) (BME_AND32(&XCVR_TSM_TIMING27_REG(base), (uint32_t)(~(value))))
40152 #define XCVR_TOG_TSM_TIMING27(base, value) (BME_XOR32(&XCVR_TSM_TIMING27_REG(base), (uint32_t)(value)))
40153 /*@}*/
40154 
40155 /*
40156  * Constants & macros for individual XCVR_TSM_TIMING27 bitfields
40157  */
40158 
40159 /*!
40160  * @name Register XCVR_TSM_TIMING27, field TX_DIG_EN_TX_HI[7:0] (RW)
40161  *
40162  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
40163  * at which the TX_DIG_EN signal or group will transition from LO to HI.
40164  */
40165 /*@{*/
40166 /*! @brief Read current value of the XCVR_TSM_TIMING27_TX_DIG_EN_TX_HI field. */
40167 #define XCVR_RD_TSM_TIMING27_TX_DIG_EN_TX_HI(base) ((XCVR_TSM_TIMING27_REG(base) & XCVR_TSM_TIMING27_TX_DIG_EN_TX_HI_MASK) >> XCVR_TSM_TIMING27_TX_DIG_EN_TX_HI_SHIFT)
40168 #define XCVR_BRD_TSM_TIMING27_TX_DIG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING27_REG(base), XCVR_TSM_TIMING27_TX_DIG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING27_TX_DIG_EN_TX_HI_WIDTH))
40169 
40170 /*! @brief Set the TX_DIG_EN_TX_HI field to a new value. */
40171 #define XCVR_WR_TSM_TIMING27_TX_DIG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING27(base, XCVR_TSM_TIMING27_TX_DIG_EN_TX_HI_MASK, XCVR_TSM_TIMING27_TX_DIG_EN_TX_HI(value)))
40172 #define XCVR_BWR_TSM_TIMING27_TX_DIG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING27_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING27_TX_DIG_EN_TX_HI_SHIFT), XCVR_TSM_TIMING27_TX_DIG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING27_TX_DIG_EN_TX_HI_WIDTH))
40173 /*@}*/
40174 
40175 /*!
40176  * @name Register XCVR_TSM_TIMING27, field TX_DIG_EN_TX_LO[15:8] (RW)
40177  *
40178  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
40179  * at which the TX_DIG_EN signal or group will transition from HI to LO.
40180  */
40181 /*@{*/
40182 /*! @brief Read current value of the XCVR_TSM_TIMING27_TX_DIG_EN_TX_LO field. */
40183 #define XCVR_RD_TSM_TIMING27_TX_DIG_EN_TX_LO(base) ((XCVR_TSM_TIMING27_REG(base) & XCVR_TSM_TIMING27_TX_DIG_EN_TX_LO_MASK) >> XCVR_TSM_TIMING27_TX_DIG_EN_TX_LO_SHIFT)
40184 #define XCVR_BRD_TSM_TIMING27_TX_DIG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING27_REG(base), XCVR_TSM_TIMING27_TX_DIG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING27_TX_DIG_EN_TX_LO_WIDTH))
40185 
40186 /*! @brief Set the TX_DIG_EN_TX_LO field to a new value. */
40187 #define XCVR_WR_TSM_TIMING27_TX_DIG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING27(base, XCVR_TSM_TIMING27_TX_DIG_EN_TX_LO_MASK, XCVR_TSM_TIMING27_TX_DIG_EN_TX_LO(value)))
40188 #define XCVR_BWR_TSM_TIMING27_TX_DIG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING27_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING27_TX_DIG_EN_TX_LO_SHIFT), XCVR_TSM_TIMING27_TX_DIG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING27_TX_DIG_EN_TX_LO_WIDTH))
40189 /*@}*/
40190 
40191 /*******************************************************************************
40192  * XCVR_TSM_TIMING28 - TSM_TIMING28
40193  ******************************************************************************/
40194 
40195 /*!
40196  * @brief XCVR_TSM_TIMING28 - TSM_TIMING28 (RW)
40197  *
40198  * Reset value: 0x6562FFFFU
40199  *
40200  * This register contains the timing values to control the assertion and
40201  * deassertion times for both TX and RX sequences for the RX_DIG_EN TSM signal or signal
40202  * group.
40203  */
40204 /*!
40205  * @name Constants and macros for entire XCVR_TSM_TIMING28 register
40206  */
40207 /*@{*/
40208 #define XCVR_RD_TSM_TIMING28(base) (XCVR_TSM_TIMING28_REG(base))
40209 #define XCVR_WR_TSM_TIMING28(base, value) (XCVR_TSM_TIMING28_REG(base) = (value))
40210 #define XCVR_RMW_TSM_TIMING28(base, mask, value) (XCVR_WR_TSM_TIMING28(base, (XCVR_RD_TSM_TIMING28(base) & ~(mask)) | (value)))
40211 #define XCVR_SET_TSM_TIMING28(base, value) (BME_OR32(&XCVR_TSM_TIMING28_REG(base), (uint32_t)(value)))
40212 #define XCVR_CLR_TSM_TIMING28(base, value) (BME_AND32(&XCVR_TSM_TIMING28_REG(base), (uint32_t)(~(value))))
40213 #define XCVR_TOG_TSM_TIMING28(base, value) (BME_XOR32(&XCVR_TSM_TIMING28_REG(base), (uint32_t)(value)))
40214 /*@}*/
40215 
40216 /*
40217  * Constants & macros for individual XCVR_TSM_TIMING28 bitfields
40218  */
40219 
40220 /*!
40221  * @name Register XCVR_TSM_TIMING28, field RX_DIG_EN_RX_HI[23:16] (RW)
40222  *
40223  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40224  * at which the RX_DIG_EN signal or group will transition from LO to HI.
40225  */
40226 /*@{*/
40227 /*! @brief Read current value of the XCVR_TSM_TIMING28_RX_DIG_EN_RX_HI field. */
40228 #define XCVR_RD_TSM_TIMING28_RX_DIG_EN_RX_HI(base) ((XCVR_TSM_TIMING28_REG(base) & XCVR_TSM_TIMING28_RX_DIG_EN_RX_HI_MASK) >> XCVR_TSM_TIMING28_RX_DIG_EN_RX_HI_SHIFT)
40229 #define XCVR_BRD_TSM_TIMING28_RX_DIG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING28_REG(base), XCVR_TSM_TIMING28_RX_DIG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING28_RX_DIG_EN_RX_HI_WIDTH))
40230 
40231 /*! @brief Set the RX_DIG_EN_RX_HI field to a new value. */
40232 #define XCVR_WR_TSM_TIMING28_RX_DIG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING28(base, XCVR_TSM_TIMING28_RX_DIG_EN_RX_HI_MASK, XCVR_TSM_TIMING28_RX_DIG_EN_RX_HI(value)))
40233 #define XCVR_BWR_TSM_TIMING28_RX_DIG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING28_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING28_RX_DIG_EN_RX_HI_SHIFT), XCVR_TSM_TIMING28_RX_DIG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING28_RX_DIG_EN_RX_HI_WIDTH))
40234 /*@}*/
40235 
40236 /*!
40237  * @name Register XCVR_TSM_TIMING28, field RX_DIG_EN_RX_LO[31:24] (RW)
40238  *
40239  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40240  * at which the RX_DIG_EN signal or group will transition from HI to LO.
40241  */
40242 /*@{*/
40243 /*! @brief Read current value of the XCVR_TSM_TIMING28_RX_DIG_EN_RX_LO field. */
40244 #define XCVR_RD_TSM_TIMING28_RX_DIG_EN_RX_LO(base) ((XCVR_TSM_TIMING28_REG(base) & XCVR_TSM_TIMING28_RX_DIG_EN_RX_LO_MASK) >> XCVR_TSM_TIMING28_RX_DIG_EN_RX_LO_SHIFT)
40245 #define XCVR_BRD_TSM_TIMING28_RX_DIG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING28_REG(base), XCVR_TSM_TIMING28_RX_DIG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING28_RX_DIG_EN_RX_LO_WIDTH))
40246 
40247 /*! @brief Set the RX_DIG_EN_RX_LO field to a new value. */
40248 #define XCVR_WR_TSM_TIMING28_RX_DIG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING28(base, XCVR_TSM_TIMING28_RX_DIG_EN_RX_LO_MASK, XCVR_TSM_TIMING28_RX_DIG_EN_RX_LO(value)))
40249 #define XCVR_BWR_TSM_TIMING28_RX_DIG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING28_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING28_RX_DIG_EN_RX_LO_SHIFT), XCVR_TSM_TIMING28_RX_DIG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING28_RX_DIG_EN_RX_LO_WIDTH))
40250 /*@}*/
40251 
40252 /*******************************************************************************
40253  * XCVR_TSM_TIMING29 - TSM_TIMING29
40254  ******************************************************************************/
40255 
40256 /*!
40257  * @brief XCVR_TSM_TIMING29 - TSM_TIMING29 (RW)
40258  *
40259  * Reset value: 0x6362FFFFU
40260  *
40261  * This register contains the timing values to control the assertion and
40262  * deassertion times for both TX and RX sequences for the RX_INIT TSM signal or signal
40263  * group.
40264  */
40265 /*!
40266  * @name Constants and macros for entire XCVR_TSM_TIMING29 register
40267  */
40268 /*@{*/
40269 #define XCVR_RD_TSM_TIMING29(base) (XCVR_TSM_TIMING29_REG(base))
40270 #define XCVR_WR_TSM_TIMING29(base, value) (XCVR_TSM_TIMING29_REG(base) = (value))
40271 #define XCVR_RMW_TSM_TIMING29(base, mask, value) (XCVR_WR_TSM_TIMING29(base, (XCVR_RD_TSM_TIMING29(base) & ~(mask)) | (value)))
40272 #define XCVR_SET_TSM_TIMING29(base, value) (BME_OR32(&XCVR_TSM_TIMING29_REG(base), (uint32_t)(value)))
40273 #define XCVR_CLR_TSM_TIMING29(base, value) (BME_AND32(&XCVR_TSM_TIMING29_REG(base), (uint32_t)(~(value))))
40274 #define XCVR_TOG_TSM_TIMING29(base, value) (BME_XOR32(&XCVR_TSM_TIMING29_REG(base), (uint32_t)(value)))
40275 /*@}*/
40276 
40277 /*
40278  * Constants & macros for individual XCVR_TSM_TIMING29 bitfields
40279  */
40280 
40281 /*!
40282  * @name Register XCVR_TSM_TIMING29, field RX_INIT_RX_HI[23:16] (RW)
40283  *
40284  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40285  * at which the RX_INIT signal or group will transition from LO to HI.
40286  */
40287 /*@{*/
40288 /*! @brief Read current value of the XCVR_TSM_TIMING29_RX_INIT_RX_HI field. */
40289 #define XCVR_RD_TSM_TIMING29_RX_INIT_RX_HI(base) ((XCVR_TSM_TIMING29_REG(base) & XCVR_TSM_TIMING29_RX_INIT_RX_HI_MASK) >> XCVR_TSM_TIMING29_RX_INIT_RX_HI_SHIFT)
40290 #define XCVR_BRD_TSM_TIMING29_RX_INIT_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING29_REG(base), XCVR_TSM_TIMING29_RX_INIT_RX_HI_SHIFT, XCVR_TSM_TIMING29_RX_INIT_RX_HI_WIDTH))
40291 
40292 /*! @brief Set the RX_INIT_RX_HI field to a new value. */
40293 #define XCVR_WR_TSM_TIMING29_RX_INIT_RX_HI(base, value) (XCVR_RMW_TSM_TIMING29(base, XCVR_TSM_TIMING29_RX_INIT_RX_HI_MASK, XCVR_TSM_TIMING29_RX_INIT_RX_HI(value)))
40294 #define XCVR_BWR_TSM_TIMING29_RX_INIT_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING29_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING29_RX_INIT_RX_HI_SHIFT), XCVR_TSM_TIMING29_RX_INIT_RX_HI_SHIFT, XCVR_TSM_TIMING29_RX_INIT_RX_HI_WIDTH))
40295 /*@}*/
40296 
40297 /*!
40298  * @name Register XCVR_TSM_TIMING29, field RX_INIT_RX_LO[31:24] (RW)
40299  *
40300  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40301  * at which the RX_INIT signal or group will transition from HI to LO.
40302  */
40303 /*@{*/
40304 /*! @brief Read current value of the XCVR_TSM_TIMING29_RX_INIT_RX_LO field. */
40305 #define XCVR_RD_TSM_TIMING29_RX_INIT_RX_LO(base) ((XCVR_TSM_TIMING29_REG(base) & XCVR_TSM_TIMING29_RX_INIT_RX_LO_MASK) >> XCVR_TSM_TIMING29_RX_INIT_RX_LO_SHIFT)
40306 #define XCVR_BRD_TSM_TIMING29_RX_INIT_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING29_REG(base), XCVR_TSM_TIMING29_RX_INIT_RX_LO_SHIFT, XCVR_TSM_TIMING29_RX_INIT_RX_LO_WIDTH))
40307 
40308 /*! @brief Set the RX_INIT_RX_LO field to a new value. */
40309 #define XCVR_WR_TSM_TIMING29_RX_INIT_RX_LO(base, value) (XCVR_RMW_TSM_TIMING29(base, XCVR_TSM_TIMING29_RX_INIT_RX_LO_MASK, XCVR_TSM_TIMING29_RX_INIT_RX_LO(value)))
40310 #define XCVR_BWR_TSM_TIMING29_RX_INIT_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING29_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING29_RX_INIT_RX_LO_SHIFT), XCVR_TSM_TIMING29_RX_INIT_RX_LO_SHIFT, XCVR_TSM_TIMING29_RX_INIT_RX_LO_WIDTH))
40311 /*@}*/
40312 
40313 /*******************************************************************************
40314  * XCVR_TSM_TIMING30 - TSM_TIMING30
40315  ******************************************************************************/
40316 
40317 /*!
40318  * @brief XCVR_TSM_TIMING30 - TSM_TIMING30 (RW)
40319  *
40320  * Reset value: 0x65106A44U
40321  *
40322  * This register contains the timing values to control the assertion and
40323  * deassertion times for both TX and RX sequences for the SIGMA_DELTA_EN TSM signal or
40324  * signal group.
40325  */
40326 /*!
40327  * @name Constants and macros for entire XCVR_TSM_TIMING30 register
40328  */
40329 /*@{*/
40330 #define XCVR_RD_TSM_TIMING30(base) (XCVR_TSM_TIMING30_REG(base))
40331 #define XCVR_WR_TSM_TIMING30(base, value) (XCVR_TSM_TIMING30_REG(base) = (value))
40332 #define XCVR_RMW_TSM_TIMING30(base, mask, value) (XCVR_WR_TSM_TIMING30(base, (XCVR_RD_TSM_TIMING30(base) & ~(mask)) | (value)))
40333 #define XCVR_SET_TSM_TIMING30(base, value) (BME_OR32(&XCVR_TSM_TIMING30_REG(base), (uint32_t)(value)))
40334 #define XCVR_CLR_TSM_TIMING30(base, value) (BME_AND32(&XCVR_TSM_TIMING30_REG(base), (uint32_t)(~(value))))
40335 #define XCVR_TOG_TSM_TIMING30(base, value) (BME_XOR32(&XCVR_TSM_TIMING30_REG(base), (uint32_t)(value)))
40336 /*@}*/
40337 
40338 /*
40339  * Constants & macros for individual XCVR_TSM_TIMING30 bitfields
40340  */
40341 
40342 /*!
40343  * @name Register XCVR_TSM_TIMING30, field SIGMA_DELTA_EN_TX_HI[7:0] (RW)
40344  *
40345  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
40346  * at which the SIGMA_DELTA_EN signal or group will transition from LO to HI.
40347  */
40348 /*@{*/
40349 /*! @brief Read current value of the XCVR_TSM_TIMING30_SIGMA_DELTA_EN_TX_HI field. */
40350 #define XCVR_RD_TSM_TIMING30_SIGMA_DELTA_EN_TX_HI(base) ((XCVR_TSM_TIMING30_REG(base) & XCVR_TSM_TIMING30_SIGMA_DELTA_EN_TX_HI_MASK) >> XCVR_TSM_TIMING30_SIGMA_DELTA_EN_TX_HI_SHIFT)
40351 #define XCVR_BRD_TSM_TIMING30_SIGMA_DELTA_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING30_REG(base), XCVR_TSM_TIMING30_SIGMA_DELTA_EN_TX_HI_SHIFT, XCVR_TSM_TIMING30_SIGMA_DELTA_EN_TX_HI_WIDTH))
40352 
40353 /*! @brief Set the SIGMA_DELTA_EN_TX_HI field to a new value. */
40354 #define XCVR_WR_TSM_TIMING30_SIGMA_DELTA_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING30(base, XCVR_TSM_TIMING30_SIGMA_DELTA_EN_TX_HI_MASK, XCVR_TSM_TIMING30_SIGMA_DELTA_EN_TX_HI(value)))
40355 #define XCVR_BWR_TSM_TIMING30_SIGMA_DELTA_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING30_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING30_SIGMA_DELTA_EN_TX_HI_SHIFT), XCVR_TSM_TIMING30_SIGMA_DELTA_EN_TX_HI_SHIFT, XCVR_TSM_TIMING30_SIGMA_DELTA_EN_TX_HI_WIDTH))
40356 /*@}*/
40357 
40358 /*!
40359  * @name Register XCVR_TSM_TIMING30, field SIGMA_DELTA_EN_TX_LO[15:8] (RW)
40360  *
40361  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
40362  * at which the SIGMA_DELTA_EN signal or group will transition from HI to LO.
40363  */
40364 /*@{*/
40365 /*! @brief Read current value of the XCVR_TSM_TIMING30_SIGMA_DELTA_EN_TX_LO field. */
40366 #define XCVR_RD_TSM_TIMING30_SIGMA_DELTA_EN_TX_LO(base) ((XCVR_TSM_TIMING30_REG(base) & XCVR_TSM_TIMING30_SIGMA_DELTA_EN_TX_LO_MASK) >> XCVR_TSM_TIMING30_SIGMA_DELTA_EN_TX_LO_SHIFT)
40367 #define XCVR_BRD_TSM_TIMING30_SIGMA_DELTA_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING30_REG(base), XCVR_TSM_TIMING30_SIGMA_DELTA_EN_TX_LO_SHIFT, XCVR_TSM_TIMING30_SIGMA_DELTA_EN_TX_LO_WIDTH))
40368 
40369 /*! @brief Set the SIGMA_DELTA_EN_TX_LO field to a new value. */
40370 #define XCVR_WR_TSM_TIMING30_SIGMA_DELTA_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING30(base, XCVR_TSM_TIMING30_SIGMA_DELTA_EN_TX_LO_MASK, XCVR_TSM_TIMING30_SIGMA_DELTA_EN_TX_LO(value)))
40371 #define XCVR_BWR_TSM_TIMING30_SIGMA_DELTA_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING30_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING30_SIGMA_DELTA_EN_TX_LO_SHIFT), XCVR_TSM_TIMING30_SIGMA_DELTA_EN_TX_LO_SHIFT, XCVR_TSM_TIMING30_SIGMA_DELTA_EN_TX_LO_WIDTH))
40372 /*@}*/
40373 
40374 /*!
40375  * @name Register XCVR_TSM_TIMING30, field SIGMA_DELTA_EN_RX_HI[23:16] (RW)
40376  *
40377  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40378  * at which the SIGMA_DELTA_EN signal or group will transition from LO to HI.
40379  */
40380 /*@{*/
40381 /*! @brief Read current value of the XCVR_TSM_TIMING30_SIGMA_DELTA_EN_RX_HI field. */
40382 #define XCVR_RD_TSM_TIMING30_SIGMA_DELTA_EN_RX_HI(base) ((XCVR_TSM_TIMING30_REG(base) & XCVR_TSM_TIMING30_SIGMA_DELTA_EN_RX_HI_MASK) >> XCVR_TSM_TIMING30_SIGMA_DELTA_EN_RX_HI_SHIFT)
40383 #define XCVR_BRD_TSM_TIMING30_SIGMA_DELTA_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING30_REG(base), XCVR_TSM_TIMING30_SIGMA_DELTA_EN_RX_HI_SHIFT, XCVR_TSM_TIMING30_SIGMA_DELTA_EN_RX_HI_WIDTH))
40384 
40385 /*! @brief Set the SIGMA_DELTA_EN_RX_HI field to a new value. */
40386 #define XCVR_WR_TSM_TIMING30_SIGMA_DELTA_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING30(base, XCVR_TSM_TIMING30_SIGMA_DELTA_EN_RX_HI_MASK, XCVR_TSM_TIMING30_SIGMA_DELTA_EN_RX_HI(value)))
40387 #define XCVR_BWR_TSM_TIMING30_SIGMA_DELTA_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING30_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING30_SIGMA_DELTA_EN_RX_HI_SHIFT), XCVR_TSM_TIMING30_SIGMA_DELTA_EN_RX_HI_SHIFT, XCVR_TSM_TIMING30_SIGMA_DELTA_EN_RX_HI_WIDTH))
40388 /*@}*/
40389 
40390 /*!
40391  * @name Register XCVR_TSM_TIMING30, field SIGMA_DELTA_EN_RX_LO[31:24] (RW)
40392  *
40393  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40394  * at which the SIGMA_DELTA_EN signal or group will transition from HI to LO.
40395  */
40396 /*@{*/
40397 /*! @brief Read current value of the XCVR_TSM_TIMING30_SIGMA_DELTA_EN_RX_LO field. */
40398 #define XCVR_RD_TSM_TIMING30_SIGMA_DELTA_EN_RX_LO(base) ((XCVR_TSM_TIMING30_REG(base) & XCVR_TSM_TIMING30_SIGMA_DELTA_EN_RX_LO_MASK) >> XCVR_TSM_TIMING30_SIGMA_DELTA_EN_RX_LO_SHIFT)
40399 #define XCVR_BRD_TSM_TIMING30_SIGMA_DELTA_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING30_REG(base), XCVR_TSM_TIMING30_SIGMA_DELTA_EN_RX_LO_SHIFT, XCVR_TSM_TIMING30_SIGMA_DELTA_EN_RX_LO_WIDTH))
40400 
40401 /*! @brief Set the SIGMA_DELTA_EN_RX_LO field to a new value. */
40402 #define XCVR_WR_TSM_TIMING30_SIGMA_DELTA_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING30(base, XCVR_TSM_TIMING30_SIGMA_DELTA_EN_RX_LO_MASK, XCVR_TSM_TIMING30_SIGMA_DELTA_EN_RX_LO(value)))
40403 #define XCVR_BWR_TSM_TIMING30_SIGMA_DELTA_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING30_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING30_SIGMA_DELTA_EN_RX_LO_SHIFT), XCVR_TSM_TIMING30_SIGMA_DELTA_EN_RX_LO_SHIFT, XCVR_TSM_TIMING30_SIGMA_DELTA_EN_RX_LO_WIDTH))
40404 /*@}*/
40405 
40406 /*******************************************************************************
40407  * XCVR_TSM_TIMING31 - TSM_TIMING31
40408  ******************************************************************************/
40409 
40410 /*!
40411  * @brief XCVR_TSM_TIMING31 - TSM_TIMING31 (RW)
40412  *
40413  * Reset value: 0x6562FFFFU
40414  *
40415  * This register contains the timing values to control the assertion and
40416  * deassertion times for both TX and RX sequences for the ZBDEM_RX_EN TSM signal or
40417  * signal group.
40418  */
40419 /*!
40420  * @name Constants and macros for entire XCVR_TSM_TIMING31 register
40421  */
40422 /*@{*/
40423 #define XCVR_RD_TSM_TIMING31(base) (XCVR_TSM_TIMING31_REG(base))
40424 #define XCVR_WR_TSM_TIMING31(base, value) (XCVR_TSM_TIMING31_REG(base) = (value))
40425 #define XCVR_RMW_TSM_TIMING31(base, mask, value) (XCVR_WR_TSM_TIMING31(base, (XCVR_RD_TSM_TIMING31(base) & ~(mask)) | (value)))
40426 #define XCVR_SET_TSM_TIMING31(base, value) (BME_OR32(&XCVR_TSM_TIMING31_REG(base), (uint32_t)(value)))
40427 #define XCVR_CLR_TSM_TIMING31(base, value) (BME_AND32(&XCVR_TSM_TIMING31_REG(base), (uint32_t)(~(value))))
40428 #define XCVR_TOG_TSM_TIMING31(base, value) (BME_XOR32(&XCVR_TSM_TIMING31_REG(base), (uint32_t)(value)))
40429 /*@}*/
40430 
40431 /*
40432  * Constants & macros for individual XCVR_TSM_TIMING31 bitfields
40433  */
40434 
40435 /*!
40436  * @name Register XCVR_TSM_TIMING31, field ZBDEM_RX_EN_RX_HI[23:16] (RW)
40437  *
40438  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40439  * at which the ZBDEM_RX_EN signal or group will transition from LO to HI.
40440  */
40441 /*@{*/
40442 /*! @brief Read current value of the XCVR_TSM_TIMING31_ZBDEM_RX_EN_RX_HI field. */
40443 #define XCVR_RD_TSM_TIMING31_ZBDEM_RX_EN_RX_HI(base) ((XCVR_TSM_TIMING31_REG(base) & XCVR_TSM_TIMING31_ZBDEM_RX_EN_RX_HI_MASK) >> XCVR_TSM_TIMING31_ZBDEM_RX_EN_RX_HI_SHIFT)
40444 #define XCVR_BRD_TSM_TIMING31_ZBDEM_RX_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING31_REG(base), XCVR_TSM_TIMING31_ZBDEM_RX_EN_RX_HI_SHIFT, XCVR_TSM_TIMING31_ZBDEM_RX_EN_RX_HI_WIDTH))
40445 
40446 /*! @brief Set the ZBDEM_RX_EN_RX_HI field to a new value. */
40447 #define XCVR_WR_TSM_TIMING31_ZBDEM_RX_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING31(base, XCVR_TSM_TIMING31_ZBDEM_RX_EN_RX_HI_MASK, XCVR_TSM_TIMING31_ZBDEM_RX_EN_RX_HI(value)))
40448 #define XCVR_BWR_TSM_TIMING31_ZBDEM_RX_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING31_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING31_ZBDEM_RX_EN_RX_HI_SHIFT), XCVR_TSM_TIMING31_ZBDEM_RX_EN_RX_HI_SHIFT, XCVR_TSM_TIMING31_ZBDEM_RX_EN_RX_HI_WIDTH))
40449 /*@}*/
40450 
40451 /*!
40452  * @name Register XCVR_TSM_TIMING31, field ZBDEM_RX_EN_RX_LO[31:24] (RW)
40453  *
40454  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40455  * at which the ZBDEM_RX_EN signal or group will transition from HI to LO.
40456  */
40457 /*@{*/
40458 /*! @brief Read current value of the XCVR_TSM_TIMING31_ZBDEM_RX_EN_RX_LO field. */
40459 #define XCVR_RD_TSM_TIMING31_ZBDEM_RX_EN_RX_LO(base) ((XCVR_TSM_TIMING31_REG(base) & XCVR_TSM_TIMING31_ZBDEM_RX_EN_RX_LO_MASK) >> XCVR_TSM_TIMING31_ZBDEM_RX_EN_RX_LO_SHIFT)
40460 #define XCVR_BRD_TSM_TIMING31_ZBDEM_RX_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING31_REG(base), XCVR_TSM_TIMING31_ZBDEM_RX_EN_RX_LO_SHIFT, XCVR_TSM_TIMING31_ZBDEM_RX_EN_RX_LO_WIDTH))
40461 
40462 /*! @brief Set the ZBDEM_RX_EN_RX_LO field to a new value. */
40463 #define XCVR_WR_TSM_TIMING31_ZBDEM_RX_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING31(base, XCVR_TSM_TIMING31_ZBDEM_RX_EN_RX_LO_MASK, XCVR_TSM_TIMING31_ZBDEM_RX_EN_RX_LO(value)))
40464 #define XCVR_BWR_TSM_TIMING31_ZBDEM_RX_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING31_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING31_ZBDEM_RX_EN_RX_LO_SHIFT), XCVR_TSM_TIMING31_ZBDEM_RX_EN_RX_LO_SHIFT, XCVR_TSM_TIMING31_ZBDEM_RX_EN_RX_LO_WIDTH))
40465 /*@}*/
40466 
40467 /*******************************************************************************
40468  * XCVR_TSM_TIMING32 - TSM_TIMING32
40469  ******************************************************************************/
40470 
40471 /*!
40472  * @brief XCVR_TSM_TIMING32 - TSM_TIMING32 (RW)
40473  *
40474  * Reset value: 0x6526FFFFU
40475  *
40476  * This register contains the timing values to control the assertion and
40477  * deassertion times for both TX and RX sequences for the DCOC_EN TSM signal or signal
40478  * group.
40479  */
40480 /*!
40481  * @name Constants and macros for entire XCVR_TSM_TIMING32 register
40482  */
40483 /*@{*/
40484 #define XCVR_RD_TSM_TIMING32(base) (XCVR_TSM_TIMING32_REG(base))
40485 #define XCVR_WR_TSM_TIMING32(base, value) (XCVR_TSM_TIMING32_REG(base) = (value))
40486 #define XCVR_RMW_TSM_TIMING32(base, mask, value) (XCVR_WR_TSM_TIMING32(base, (XCVR_RD_TSM_TIMING32(base) & ~(mask)) | (value)))
40487 #define XCVR_SET_TSM_TIMING32(base, value) (BME_OR32(&XCVR_TSM_TIMING32_REG(base), (uint32_t)(value)))
40488 #define XCVR_CLR_TSM_TIMING32(base, value) (BME_AND32(&XCVR_TSM_TIMING32_REG(base), (uint32_t)(~(value))))
40489 #define XCVR_TOG_TSM_TIMING32(base, value) (BME_XOR32(&XCVR_TSM_TIMING32_REG(base), (uint32_t)(value)))
40490 /*@}*/
40491 
40492 /*
40493  * Constants & macros for individual XCVR_TSM_TIMING32 bitfields
40494  */
40495 
40496 /*!
40497  * @name Register XCVR_TSM_TIMING32, field DCOC_EN_RX_HI[23:16] (RW)
40498  *
40499  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40500  * at which the DCOC_EN signal or group will transition from LO to HI.
40501  */
40502 /*@{*/
40503 /*! @brief Read current value of the XCVR_TSM_TIMING32_DCOC_EN_RX_HI field. */
40504 #define XCVR_RD_TSM_TIMING32_DCOC_EN_RX_HI(base) ((XCVR_TSM_TIMING32_REG(base) & XCVR_TSM_TIMING32_DCOC_EN_RX_HI_MASK) >> XCVR_TSM_TIMING32_DCOC_EN_RX_HI_SHIFT)
40505 #define XCVR_BRD_TSM_TIMING32_DCOC_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING32_REG(base), XCVR_TSM_TIMING32_DCOC_EN_RX_HI_SHIFT, XCVR_TSM_TIMING32_DCOC_EN_RX_HI_WIDTH))
40506 
40507 /*! @brief Set the DCOC_EN_RX_HI field to a new value. */
40508 #define XCVR_WR_TSM_TIMING32_DCOC_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING32(base, XCVR_TSM_TIMING32_DCOC_EN_RX_HI_MASK, XCVR_TSM_TIMING32_DCOC_EN_RX_HI(value)))
40509 #define XCVR_BWR_TSM_TIMING32_DCOC_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING32_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING32_DCOC_EN_RX_HI_SHIFT), XCVR_TSM_TIMING32_DCOC_EN_RX_HI_SHIFT, XCVR_TSM_TIMING32_DCOC_EN_RX_HI_WIDTH))
40510 /*@}*/
40511 
40512 /*!
40513  * @name Register XCVR_TSM_TIMING32, field DCOC_EN_RX_LO[31:24] (RW)
40514  *
40515  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40516  * at which the DCOC_EN signal or group will transition from HI to LO.
40517  */
40518 /*@{*/
40519 /*! @brief Read current value of the XCVR_TSM_TIMING32_DCOC_EN_RX_LO field. */
40520 #define XCVR_RD_TSM_TIMING32_DCOC_EN_RX_LO(base) ((XCVR_TSM_TIMING32_REG(base) & XCVR_TSM_TIMING32_DCOC_EN_RX_LO_MASK) >> XCVR_TSM_TIMING32_DCOC_EN_RX_LO_SHIFT)
40521 #define XCVR_BRD_TSM_TIMING32_DCOC_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING32_REG(base), XCVR_TSM_TIMING32_DCOC_EN_RX_LO_SHIFT, XCVR_TSM_TIMING32_DCOC_EN_RX_LO_WIDTH))
40522 
40523 /*! @brief Set the DCOC_EN_RX_LO field to a new value. */
40524 #define XCVR_WR_TSM_TIMING32_DCOC_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING32(base, XCVR_TSM_TIMING32_DCOC_EN_RX_LO_MASK, XCVR_TSM_TIMING32_DCOC_EN_RX_LO(value)))
40525 #define XCVR_BWR_TSM_TIMING32_DCOC_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING32_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING32_DCOC_EN_RX_LO_SHIFT), XCVR_TSM_TIMING32_DCOC_EN_RX_LO_SHIFT, XCVR_TSM_TIMING32_DCOC_EN_RX_LO_WIDTH))
40526 /*@}*/
40527 
40528 /*******************************************************************************
40529  * XCVR_TSM_TIMING33 - TSM_TIMING33
40530  ******************************************************************************/
40531 
40532 /*!
40533  * @brief XCVR_TSM_TIMING33 - TSM_TIMING33 (RW)
40534  *
40535  * Reset value: 0x2726FFFFU
40536  *
40537  * This register contains the timing values to control the assertion and
40538  * deassertion times for both TX and RX sequences for the DCOC_INIT TSM signal or signal
40539  * group.
40540  */
40541 /*!
40542  * @name Constants and macros for entire XCVR_TSM_TIMING33 register
40543  */
40544 /*@{*/
40545 #define XCVR_RD_TSM_TIMING33(base) (XCVR_TSM_TIMING33_REG(base))
40546 #define XCVR_WR_TSM_TIMING33(base, value) (XCVR_TSM_TIMING33_REG(base) = (value))
40547 #define XCVR_RMW_TSM_TIMING33(base, mask, value) (XCVR_WR_TSM_TIMING33(base, (XCVR_RD_TSM_TIMING33(base) & ~(mask)) | (value)))
40548 #define XCVR_SET_TSM_TIMING33(base, value) (BME_OR32(&XCVR_TSM_TIMING33_REG(base), (uint32_t)(value)))
40549 #define XCVR_CLR_TSM_TIMING33(base, value) (BME_AND32(&XCVR_TSM_TIMING33_REG(base), (uint32_t)(~(value))))
40550 #define XCVR_TOG_TSM_TIMING33(base, value) (BME_XOR32(&XCVR_TSM_TIMING33_REG(base), (uint32_t)(value)))
40551 /*@}*/
40552 
40553 /*
40554  * Constants & macros for individual XCVR_TSM_TIMING33 bitfields
40555  */
40556 
40557 /*!
40558  * @name Register XCVR_TSM_TIMING33, field DCOC_INIT_RX_HI[23:16] (RW)
40559  *
40560  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40561  * at which the DCOC_INIT signal or group will transition from LO to HI.
40562  */
40563 /*@{*/
40564 /*! @brief Read current value of the XCVR_TSM_TIMING33_DCOC_INIT_RX_HI field. */
40565 #define XCVR_RD_TSM_TIMING33_DCOC_INIT_RX_HI(base) ((XCVR_TSM_TIMING33_REG(base) & XCVR_TSM_TIMING33_DCOC_INIT_RX_HI_MASK) >> XCVR_TSM_TIMING33_DCOC_INIT_RX_HI_SHIFT)
40566 #define XCVR_BRD_TSM_TIMING33_DCOC_INIT_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING33_REG(base), XCVR_TSM_TIMING33_DCOC_INIT_RX_HI_SHIFT, XCVR_TSM_TIMING33_DCOC_INIT_RX_HI_WIDTH))
40567 
40568 /*! @brief Set the DCOC_INIT_RX_HI field to a new value. */
40569 #define XCVR_WR_TSM_TIMING33_DCOC_INIT_RX_HI(base, value) (XCVR_RMW_TSM_TIMING33(base, XCVR_TSM_TIMING33_DCOC_INIT_RX_HI_MASK, XCVR_TSM_TIMING33_DCOC_INIT_RX_HI(value)))
40570 #define XCVR_BWR_TSM_TIMING33_DCOC_INIT_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING33_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING33_DCOC_INIT_RX_HI_SHIFT), XCVR_TSM_TIMING33_DCOC_INIT_RX_HI_SHIFT, XCVR_TSM_TIMING33_DCOC_INIT_RX_HI_WIDTH))
40571 /*@}*/
40572 
40573 /*!
40574  * @name Register XCVR_TSM_TIMING33, field DCOC_INIT_RX_LO[31:24] (RW)
40575  *
40576  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40577  * at which the DCOC_INIT signal or group will transition from HI to LO.
40578  */
40579 /*@{*/
40580 /*! @brief Read current value of the XCVR_TSM_TIMING33_DCOC_INIT_RX_LO field. */
40581 #define XCVR_RD_TSM_TIMING33_DCOC_INIT_RX_LO(base) ((XCVR_TSM_TIMING33_REG(base) & XCVR_TSM_TIMING33_DCOC_INIT_RX_LO_MASK) >> XCVR_TSM_TIMING33_DCOC_INIT_RX_LO_SHIFT)
40582 #define XCVR_BRD_TSM_TIMING33_DCOC_INIT_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING33_REG(base), XCVR_TSM_TIMING33_DCOC_INIT_RX_LO_SHIFT, XCVR_TSM_TIMING33_DCOC_INIT_RX_LO_WIDTH))
40583 
40584 /*! @brief Set the DCOC_INIT_RX_LO field to a new value. */
40585 #define XCVR_WR_TSM_TIMING33_DCOC_INIT_RX_LO(base, value) (XCVR_RMW_TSM_TIMING33(base, XCVR_TSM_TIMING33_DCOC_INIT_RX_LO_MASK, XCVR_TSM_TIMING33_DCOC_INIT_RX_LO(value)))
40586 #define XCVR_BWR_TSM_TIMING33_DCOC_INIT_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING33_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING33_DCOC_INIT_RX_LO_SHIFT), XCVR_TSM_TIMING33_DCOC_INIT_RX_LO_SHIFT, XCVR_TSM_TIMING33_DCOC_INIT_RX_LO_WIDTH))
40587 /*@}*/
40588 
40589 /*******************************************************************************
40590  * XCVR_TSM_TIMING34 - TSM_TIMING34
40591  ******************************************************************************/
40592 
40593 /*!
40594  * @brief XCVR_TSM_TIMING34 - TSM_TIMING34 (RW)
40595  *
40596  * Reset value: 0x65336865U
40597  *
40598  * This register contains the timing values to control the assertion and
40599  * deassertion times for both TX and RX sequences for the FREQ_TARG_LD_EN TSM signal or
40600  * signal group.
40601  */
40602 /*!
40603  * @name Constants and macros for entire XCVR_TSM_TIMING34 register
40604  */
40605 /*@{*/
40606 #define XCVR_RD_TSM_TIMING34(base) (XCVR_TSM_TIMING34_REG(base))
40607 #define XCVR_WR_TSM_TIMING34(base, value) (XCVR_TSM_TIMING34_REG(base) = (value))
40608 #define XCVR_RMW_TSM_TIMING34(base, mask, value) (XCVR_WR_TSM_TIMING34(base, (XCVR_RD_TSM_TIMING34(base) & ~(mask)) | (value)))
40609 #define XCVR_SET_TSM_TIMING34(base, value) (BME_OR32(&XCVR_TSM_TIMING34_REG(base), (uint32_t)(value)))
40610 #define XCVR_CLR_TSM_TIMING34(base, value) (BME_AND32(&XCVR_TSM_TIMING34_REG(base), (uint32_t)(~(value))))
40611 #define XCVR_TOG_TSM_TIMING34(base, value) (BME_XOR32(&XCVR_TSM_TIMING34_REG(base), (uint32_t)(value)))
40612 /*@}*/
40613 
40614 /*
40615  * Constants & macros for individual XCVR_TSM_TIMING34 bitfields
40616  */
40617 
40618 /*!
40619  * @name Register XCVR_TSM_TIMING34, field FREQ_TARG_LD_EN_TX_HI[7:0] (RW)
40620  *
40621  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
40622  * at which the FREQ_TARG_LD_EN signal or group will transition from LO to HI.
40623  */
40624 /*@{*/
40625 /*! @brief Read current value of the XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_HI field. */
40626 #define XCVR_RD_TSM_TIMING34_FREQ_TARG_LD_EN_TX_HI(base) ((XCVR_TSM_TIMING34_REG(base) & XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_HI_MASK) >> XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_HI_SHIFT)
40627 #define XCVR_BRD_TSM_TIMING34_FREQ_TARG_LD_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING34_REG(base), XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_HI_SHIFT, XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_HI_WIDTH))
40628 
40629 /*! @brief Set the FREQ_TARG_LD_EN_TX_HI field to a new value. */
40630 #define XCVR_WR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING34(base, XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_HI_MASK, XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_HI(value)))
40631 #define XCVR_BWR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING34_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_HI_SHIFT), XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_HI_SHIFT, XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_HI_WIDTH))
40632 /*@}*/
40633 
40634 /*!
40635  * @name Register XCVR_TSM_TIMING34, field FREQ_TARG_LD_EN_TX_LO[15:8] (RW)
40636  *
40637  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
40638  * at which the FREQ_TARG_LD_EN signal or group will transition from HI to LO.
40639  */
40640 /*@{*/
40641 /*! @brief Read current value of the XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_LO field. */
40642 #define XCVR_RD_TSM_TIMING34_FREQ_TARG_LD_EN_TX_LO(base) ((XCVR_TSM_TIMING34_REG(base) & XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_LO_MASK) >> XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_LO_SHIFT)
40643 #define XCVR_BRD_TSM_TIMING34_FREQ_TARG_LD_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING34_REG(base), XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_LO_SHIFT, XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_LO_WIDTH))
40644 
40645 /*! @brief Set the FREQ_TARG_LD_EN_TX_LO field to a new value. */
40646 #define XCVR_WR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING34(base, XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_LO_MASK, XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_LO(value)))
40647 #define XCVR_BWR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING34_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_LO_SHIFT), XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_LO_SHIFT, XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_TX_LO_WIDTH))
40648 /*@}*/
40649 
40650 /*!
40651  * @name Register XCVR_TSM_TIMING34, field FREQ_TARG_LD_EN_RX_HI[23:16] (RW)
40652  *
40653  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40654  * at which the FREQ_TARG_LD_EN signal or group will transition from LO to HI.
40655  */
40656 /*@{*/
40657 /*! @brief Read current value of the XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_HI field. */
40658 #define XCVR_RD_TSM_TIMING34_FREQ_TARG_LD_EN_RX_HI(base) ((XCVR_TSM_TIMING34_REG(base) & XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_HI_MASK) >> XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_HI_SHIFT)
40659 #define XCVR_BRD_TSM_TIMING34_FREQ_TARG_LD_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING34_REG(base), XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_HI_SHIFT, XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_HI_WIDTH))
40660 
40661 /*! @brief Set the FREQ_TARG_LD_EN_RX_HI field to a new value. */
40662 #define XCVR_WR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING34(base, XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_HI_MASK, XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_HI(value)))
40663 #define XCVR_BWR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING34_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_HI_SHIFT), XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_HI_SHIFT, XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_HI_WIDTH))
40664 /*@}*/
40665 
40666 /*!
40667  * @name Register XCVR_TSM_TIMING34, field FREQ_TARG_LD_EN_RX_LO[31:24] (RW)
40668  *
40669  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40670  * at which the FREQ_TARG_LD_EN signal or group will transition from HI to LO.
40671  */
40672 /*@{*/
40673 /*! @brief Read current value of the XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_LO field. */
40674 #define XCVR_RD_TSM_TIMING34_FREQ_TARG_LD_EN_RX_LO(base) ((XCVR_TSM_TIMING34_REG(base) & XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_LO_MASK) >> XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_LO_SHIFT)
40675 #define XCVR_BRD_TSM_TIMING34_FREQ_TARG_LD_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING34_REG(base), XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_LO_SHIFT, XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_LO_WIDTH))
40676 
40677 /*! @brief Set the FREQ_TARG_LD_EN_RX_LO field to a new value. */
40678 #define XCVR_WR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING34(base, XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_LO_MASK, XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_LO(value)))
40679 #define XCVR_BWR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING34_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_LO_SHIFT), XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_LO_SHIFT, XCVR_TSM_TIMING34_FREQ_TARG_LD_EN_RX_LO_WIDTH))
40680 /*@}*/
40681 
40682 /*******************************************************************************
40683  * XCVR_TSM_TIMING35 - TSM_TIMING35
40684  ******************************************************************************/
40685 
40686 /*!
40687  * @brief XCVR_TSM_TIMING35 - TSM_TIMING35 (RW)
40688  *
40689  * Reset value: 0xFFFFFFFFU
40690  *
40691  * This register contains the timing values to control the assertion and
40692  * deassertion times for both TX and RX sequences for the SAR_ADC_TRIG_EN TSM signal or
40693  * signal group.
40694  */
40695 /*!
40696  * @name Constants and macros for entire XCVR_TSM_TIMING35 register
40697  */
40698 /*@{*/
40699 #define XCVR_RD_TSM_TIMING35(base) (XCVR_TSM_TIMING35_REG(base))
40700 #define XCVR_WR_TSM_TIMING35(base, value) (XCVR_TSM_TIMING35_REG(base) = (value))
40701 #define XCVR_RMW_TSM_TIMING35(base, mask, value) (XCVR_WR_TSM_TIMING35(base, (XCVR_RD_TSM_TIMING35(base) & ~(mask)) | (value)))
40702 #define XCVR_SET_TSM_TIMING35(base, value) (BME_OR32(&XCVR_TSM_TIMING35_REG(base), (uint32_t)(value)))
40703 #define XCVR_CLR_TSM_TIMING35(base, value) (BME_AND32(&XCVR_TSM_TIMING35_REG(base), (uint32_t)(~(value))))
40704 #define XCVR_TOG_TSM_TIMING35(base, value) (BME_XOR32(&XCVR_TSM_TIMING35_REG(base), (uint32_t)(value)))
40705 /*@}*/
40706 
40707 /*
40708  * Constants & macros for individual XCVR_TSM_TIMING35 bitfields
40709  */
40710 
40711 /*!
40712  * @name Register XCVR_TSM_TIMING35, field SAR_ADC_TRIG_EN_TX_HI[7:0] (RW)
40713  *
40714  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
40715  * at which the SAR_ADC_TRIG_EN signal or group will transition from LO to HI.
40716  */
40717 /*@{*/
40718 /*! @brief Read current value of the XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_HI field. */
40719 #define XCVR_RD_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_HI(base) ((XCVR_TSM_TIMING35_REG(base) & XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_HI_MASK) >> XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_HI_SHIFT)
40720 #define XCVR_BRD_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING35_REG(base), XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_HI_WIDTH))
40721 
40722 /*! @brief Set the SAR_ADC_TRIG_EN_TX_HI field to a new value. */
40723 #define XCVR_WR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING35(base, XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_HI_MASK, XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_HI(value)))
40724 #define XCVR_BWR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING35_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_HI_SHIFT), XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_HI_WIDTH))
40725 /*@}*/
40726 
40727 /*!
40728  * @name Register XCVR_TSM_TIMING35, field SAR_ADC_TRIG_EN_TX_LO[15:8] (RW)
40729  *
40730  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
40731  * at which the SAR_ADC_TRIG_EN signal or group will transition from HI to LO.
40732  */
40733 /*@{*/
40734 /*! @brief Read current value of the XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_LO field. */
40735 #define XCVR_RD_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_LO(base) ((XCVR_TSM_TIMING35_REG(base) & XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_LO_MASK) >> XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_LO_SHIFT)
40736 #define XCVR_BRD_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING35_REG(base), XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_LO_WIDTH))
40737 
40738 /*! @brief Set the SAR_ADC_TRIG_EN_TX_LO field to a new value. */
40739 #define XCVR_WR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING35(base, XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_LO_MASK, XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_LO(value)))
40740 #define XCVR_BWR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING35_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_LO_SHIFT), XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_TX_LO_WIDTH))
40741 /*@}*/
40742 
40743 /*!
40744  * @name Register XCVR_TSM_TIMING35, field SAR_ADC_TRIG_EN_RX_HI[23:16] (RW)
40745  *
40746  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40747  * at which the SAR_ADC_TRIG_EN signal or group will transition from LO to HI.
40748  */
40749 /*@{*/
40750 /*! @brief Read current value of the XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_HI field. */
40751 #define XCVR_RD_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_HI(base) ((XCVR_TSM_TIMING35_REG(base) & XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_HI_MASK) >> XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_HI_SHIFT)
40752 #define XCVR_BRD_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING35_REG(base), XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_HI_WIDTH))
40753 
40754 /*! @brief Set the SAR_ADC_TRIG_EN_RX_HI field to a new value. */
40755 #define XCVR_WR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING35(base, XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_HI_MASK, XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_HI(value)))
40756 #define XCVR_BWR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING35_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_HI_SHIFT), XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_HI_WIDTH))
40757 /*@}*/
40758 
40759 /*!
40760  * @name Register XCVR_TSM_TIMING35, field SAR_ADC_TRIG_EN_RX_LO[31:24] (RW)
40761  *
40762  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40763  * at which the SAR_ADC_TRIG_EN signal or group will transition from HI to LO.
40764  */
40765 /*@{*/
40766 /*! @brief Read current value of the XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_LO field. */
40767 #define XCVR_RD_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_LO(base) ((XCVR_TSM_TIMING35_REG(base) & XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_LO_MASK) >> XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_LO_SHIFT)
40768 #define XCVR_BRD_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING35_REG(base), XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_LO_WIDTH))
40769 
40770 /*! @brief Set the SAR_ADC_TRIG_EN_RX_LO field to a new value. */
40771 #define XCVR_WR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING35(base, XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_LO_MASK, XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_LO(value)))
40772 #define XCVR_BWR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING35_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_LO_SHIFT), XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING35_SAR_ADC_TRIG_EN_RX_LO_WIDTH))
40773 /*@}*/
40774 
40775 /*******************************************************************************
40776  * XCVR_TSM_TIMING36 - TSM_TIMING36
40777  ******************************************************************************/
40778 
40779 /*!
40780  * @brief XCVR_TSM_TIMING36 - TSM_TIMING36 (RW)
40781  *
40782  * Reset value: 0xFFFFFFFFU
40783  *
40784  * This register contains the timing values to control the assertion and
40785  * deassertion times for both TX and RX sequences for the TSM_SPARE0_EN TSM signal or
40786  * signal group.
40787  */
40788 /*!
40789  * @name Constants and macros for entire XCVR_TSM_TIMING36 register
40790  */
40791 /*@{*/
40792 #define XCVR_RD_TSM_TIMING36(base) (XCVR_TSM_TIMING36_REG(base))
40793 #define XCVR_WR_TSM_TIMING36(base, value) (XCVR_TSM_TIMING36_REG(base) = (value))
40794 #define XCVR_RMW_TSM_TIMING36(base, mask, value) (XCVR_WR_TSM_TIMING36(base, (XCVR_RD_TSM_TIMING36(base) & ~(mask)) | (value)))
40795 #define XCVR_SET_TSM_TIMING36(base, value) (BME_OR32(&XCVR_TSM_TIMING36_REG(base), (uint32_t)(value)))
40796 #define XCVR_CLR_TSM_TIMING36(base, value) (BME_AND32(&XCVR_TSM_TIMING36_REG(base), (uint32_t)(~(value))))
40797 #define XCVR_TOG_TSM_TIMING36(base, value) (BME_XOR32(&XCVR_TSM_TIMING36_REG(base), (uint32_t)(value)))
40798 /*@}*/
40799 
40800 /*
40801  * Constants & macros for individual XCVR_TSM_TIMING36 bitfields
40802  */
40803 
40804 /*!
40805  * @name Register XCVR_TSM_TIMING36, field TSM_SPARE0_EN_TX_HI[7:0] (RW)
40806  *
40807  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
40808  * at which the TSM_SPARE0_EN signal or group will transition from LO to HI.
40809  */
40810 /*@{*/
40811 /*! @brief Read current value of the XCVR_TSM_TIMING36_TSM_SPARE0_EN_TX_HI field. */
40812 #define XCVR_RD_TSM_TIMING36_TSM_SPARE0_EN_TX_HI(base) ((XCVR_TSM_TIMING36_REG(base) & XCVR_TSM_TIMING36_TSM_SPARE0_EN_TX_HI_MASK) >> XCVR_TSM_TIMING36_TSM_SPARE0_EN_TX_HI_SHIFT)
40813 #define XCVR_BRD_TSM_TIMING36_TSM_SPARE0_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING36_REG(base), XCVR_TSM_TIMING36_TSM_SPARE0_EN_TX_HI_SHIFT, XCVR_TSM_TIMING36_TSM_SPARE0_EN_TX_HI_WIDTH))
40814 
40815 /*! @brief Set the TSM_SPARE0_EN_TX_HI field to a new value. */
40816 #define XCVR_WR_TSM_TIMING36_TSM_SPARE0_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING36(base, XCVR_TSM_TIMING36_TSM_SPARE0_EN_TX_HI_MASK, XCVR_TSM_TIMING36_TSM_SPARE0_EN_TX_HI(value)))
40817 #define XCVR_BWR_TSM_TIMING36_TSM_SPARE0_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING36_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING36_TSM_SPARE0_EN_TX_HI_SHIFT), XCVR_TSM_TIMING36_TSM_SPARE0_EN_TX_HI_SHIFT, XCVR_TSM_TIMING36_TSM_SPARE0_EN_TX_HI_WIDTH))
40818 /*@}*/
40819 
40820 /*!
40821  * @name Register XCVR_TSM_TIMING36, field TSM_SPARE0_EN_TX_LO[15:8] (RW)
40822  *
40823  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
40824  * at which the TSM_SPARE0_EN signal or group will transition from HI to LO.
40825  */
40826 /*@{*/
40827 /*! @brief Read current value of the XCVR_TSM_TIMING36_TSM_SPARE0_EN_TX_LO field. */
40828 #define XCVR_RD_TSM_TIMING36_TSM_SPARE0_EN_TX_LO(base) ((XCVR_TSM_TIMING36_REG(base) & XCVR_TSM_TIMING36_TSM_SPARE0_EN_TX_LO_MASK) >> XCVR_TSM_TIMING36_TSM_SPARE0_EN_TX_LO_SHIFT)
40829 #define XCVR_BRD_TSM_TIMING36_TSM_SPARE0_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING36_REG(base), XCVR_TSM_TIMING36_TSM_SPARE0_EN_TX_LO_SHIFT, XCVR_TSM_TIMING36_TSM_SPARE0_EN_TX_LO_WIDTH))
40830 
40831 /*! @brief Set the TSM_SPARE0_EN_TX_LO field to a new value. */
40832 #define XCVR_WR_TSM_TIMING36_TSM_SPARE0_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING36(base, XCVR_TSM_TIMING36_TSM_SPARE0_EN_TX_LO_MASK, XCVR_TSM_TIMING36_TSM_SPARE0_EN_TX_LO(value)))
40833 #define XCVR_BWR_TSM_TIMING36_TSM_SPARE0_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING36_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING36_TSM_SPARE0_EN_TX_LO_SHIFT), XCVR_TSM_TIMING36_TSM_SPARE0_EN_TX_LO_SHIFT, XCVR_TSM_TIMING36_TSM_SPARE0_EN_TX_LO_WIDTH))
40834 /*@}*/
40835 
40836 /*!
40837  * @name Register XCVR_TSM_TIMING36, field TSM_SPARE0_EN_RX_HI[23:16] (RW)
40838  *
40839  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40840  * at which the TSM_SPARE0_EN signal or group will transition from LO to HI.
40841  */
40842 /*@{*/
40843 /*! @brief Read current value of the XCVR_TSM_TIMING36_TSM_SPARE0_EN_RX_HI field. */
40844 #define XCVR_RD_TSM_TIMING36_TSM_SPARE0_EN_RX_HI(base) ((XCVR_TSM_TIMING36_REG(base) & XCVR_TSM_TIMING36_TSM_SPARE0_EN_RX_HI_MASK) >> XCVR_TSM_TIMING36_TSM_SPARE0_EN_RX_HI_SHIFT)
40845 #define XCVR_BRD_TSM_TIMING36_TSM_SPARE0_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING36_REG(base), XCVR_TSM_TIMING36_TSM_SPARE0_EN_RX_HI_SHIFT, XCVR_TSM_TIMING36_TSM_SPARE0_EN_RX_HI_WIDTH))
40846 
40847 /*! @brief Set the TSM_SPARE0_EN_RX_HI field to a new value. */
40848 #define XCVR_WR_TSM_TIMING36_TSM_SPARE0_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING36(base, XCVR_TSM_TIMING36_TSM_SPARE0_EN_RX_HI_MASK, XCVR_TSM_TIMING36_TSM_SPARE0_EN_RX_HI(value)))
40849 #define XCVR_BWR_TSM_TIMING36_TSM_SPARE0_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING36_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING36_TSM_SPARE0_EN_RX_HI_SHIFT), XCVR_TSM_TIMING36_TSM_SPARE0_EN_RX_HI_SHIFT, XCVR_TSM_TIMING36_TSM_SPARE0_EN_RX_HI_WIDTH))
40850 /*@}*/
40851 
40852 /*!
40853  * @name Register XCVR_TSM_TIMING36, field TSM_SPARE0_EN_RX_LO[31:24] (RW)
40854  *
40855  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40856  * at which the TSM_SPARE0_EN signal or group will transition from HI to LO.
40857  */
40858 /*@{*/
40859 /*! @brief Read current value of the XCVR_TSM_TIMING36_TSM_SPARE0_EN_RX_LO field. */
40860 #define XCVR_RD_TSM_TIMING36_TSM_SPARE0_EN_RX_LO(base) ((XCVR_TSM_TIMING36_REG(base) & XCVR_TSM_TIMING36_TSM_SPARE0_EN_RX_LO_MASK) >> XCVR_TSM_TIMING36_TSM_SPARE0_EN_RX_LO_SHIFT)
40861 #define XCVR_BRD_TSM_TIMING36_TSM_SPARE0_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING36_REG(base), XCVR_TSM_TIMING36_TSM_SPARE0_EN_RX_LO_SHIFT, XCVR_TSM_TIMING36_TSM_SPARE0_EN_RX_LO_WIDTH))
40862 
40863 /*! @brief Set the TSM_SPARE0_EN_RX_LO field to a new value. */
40864 #define XCVR_WR_TSM_TIMING36_TSM_SPARE0_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING36(base, XCVR_TSM_TIMING36_TSM_SPARE0_EN_RX_LO_MASK, XCVR_TSM_TIMING36_TSM_SPARE0_EN_RX_LO(value)))
40865 #define XCVR_BWR_TSM_TIMING36_TSM_SPARE0_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING36_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING36_TSM_SPARE0_EN_RX_LO_SHIFT), XCVR_TSM_TIMING36_TSM_SPARE0_EN_RX_LO_SHIFT, XCVR_TSM_TIMING36_TSM_SPARE0_EN_RX_LO_WIDTH))
40866 /*@}*/
40867 
40868 /*******************************************************************************
40869  * XCVR_TSM_TIMING37 - TSM_TIMING37
40870  ******************************************************************************/
40871 
40872 /*!
40873  * @brief XCVR_TSM_TIMING37 - TSM_TIMING37 (RW)
40874  *
40875  * Reset value: 0xFFFFFFFFU
40876  *
40877  * This register contains the timing values to control the assertion and
40878  * deassertion times for both TX and RX sequences for the TSM_SPARE1_EN TSM signal or
40879  * signal group.
40880  */
40881 /*!
40882  * @name Constants and macros for entire XCVR_TSM_TIMING37 register
40883  */
40884 /*@{*/
40885 #define XCVR_RD_TSM_TIMING37(base) (XCVR_TSM_TIMING37_REG(base))
40886 #define XCVR_WR_TSM_TIMING37(base, value) (XCVR_TSM_TIMING37_REG(base) = (value))
40887 #define XCVR_RMW_TSM_TIMING37(base, mask, value) (XCVR_WR_TSM_TIMING37(base, (XCVR_RD_TSM_TIMING37(base) & ~(mask)) | (value)))
40888 #define XCVR_SET_TSM_TIMING37(base, value) (BME_OR32(&XCVR_TSM_TIMING37_REG(base), (uint32_t)(value)))
40889 #define XCVR_CLR_TSM_TIMING37(base, value) (BME_AND32(&XCVR_TSM_TIMING37_REG(base), (uint32_t)(~(value))))
40890 #define XCVR_TOG_TSM_TIMING37(base, value) (BME_XOR32(&XCVR_TSM_TIMING37_REG(base), (uint32_t)(value)))
40891 /*@}*/
40892 
40893 /*
40894  * Constants & macros for individual XCVR_TSM_TIMING37 bitfields
40895  */
40896 
40897 /*!
40898  * @name Register XCVR_TSM_TIMING37, field TSM_SPARE1_EN_TX_HI[7:0] (RW)
40899  *
40900  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
40901  * at which the TSM_SPARE1_EN signal or group will transition from LO to HI.
40902  */
40903 /*@{*/
40904 /*! @brief Read current value of the XCVR_TSM_TIMING37_TSM_SPARE1_EN_TX_HI field. */
40905 #define XCVR_RD_TSM_TIMING37_TSM_SPARE1_EN_TX_HI(base) ((XCVR_TSM_TIMING37_REG(base) & XCVR_TSM_TIMING37_TSM_SPARE1_EN_TX_HI_MASK) >> XCVR_TSM_TIMING37_TSM_SPARE1_EN_TX_HI_SHIFT)
40906 #define XCVR_BRD_TSM_TIMING37_TSM_SPARE1_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING37_REG(base), XCVR_TSM_TIMING37_TSM_SPARE1_EN_TX_HI_SHIFT, XCVR_TSM_TIMING37_TSM_SPARE1_EN_TX_HI_WIDTH))
40907 
40908 /*! @brief Set the TSM_SPARE1_EN_TX_HI field to a new value. */
40909 #define XCVR_WR_TSM_TIMING37_TSM_SPARE1_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING37(base, XCVR_TSM_TIMING37_TSM_SPARE1_EN_TX_HI_MASK, XCVR_TSM_TIMING37_TSM_SPARE1_EN_TX_HI(value)))
40910 #define XCVR_BWR_TSM_TIMING37_TSM_SPARE1_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING37_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING37_TSM_SPARE1_EN_TX_HI_SHIFT), XCVR_TSM_TIMING37_TSM_SPARE1_EN_TX_HI_SHIFT, XCVR_TSM_TIMING37_TSM_SPARE1_EN_TX_HI_WIDTH))
40911 /*@}*/
40912 
40913 /*!
40914  * @name Register XCVR_TSM_TIMING37, field TSM_SPARE1_EN_TX_LO[15:8] (RW)
40915  *
40916  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
40917  * at which the TSM_SPARE1_EN signal or group will transition from HI to LO.
40918  */
40919 /*@{*/
40920 /*! @brief Read current value of the XCVR_TSM_TIMING37_TSM_SPARE1_EN_TX_LO field. */
40921 #define XCVR_RD_TSM_TIMING37_TSM_SPARE1_EN_TX_LO(base) ((XCVR_TSM_TIMING37_REG(base) & XCVR_TSM_TIMING37_TSM_SPARE1_EN_TX_LO_MASK) >> XCVR_TSM_TIMING37_TSM_SPARE1_EN_TX_LO_SHIFT)
40922 #define XCVR_BRD_TSM_TIMING37_TSM_SPARE1_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING37_REG(base), XCVR_TSM_TIMING37_TSM_SPARE1_EN_TX_LO_SHIFT, XCVR_TSM_TIMING37_TSM_SPARE1_EN_TX_LO_WIDTH))
40923 
40924 /*! @brief Set the TSM_SPARE1_EN_TX_LO field to a new value. */
40925 #define XCVR_WR_TSM_TIMING37_TSM_SPARE1_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING37(base, XCVR_TSM_TIMING37_TSM_SPARE1_EN_TX_LO_MASK, XCVR_TSM_TIMING37_TSM_SPARE1_EN_TX_LO(value)))
40926 #define XCVR_BWR_TSM_TIMING37_TSM_SPARE1_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING37_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING37_TSM_SPARE1_EN_TX_LO_SHIFT), XCVR_TSM_TIMING37_TSM_SPARE1_EN_TX_LO_SHIFT, XCVR_TSM_TIMING37_TSM_SPARE1_EN_TX_LO_WIDTH))
40927 /*@}*/
40928 
40929 /*!
40930  * @name Register XCVR_TSM_TIMING37, field TSM_SPARE1_EN_RX_HI[23:16] (RW)
40931  *
40932  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40933  * at which the TSM_SPARE1_EN signal or group will transition from LO to HI.
40934  */
40935 /*@{*/
40936 /*! @brief Read current value of the XCVR_TSM_TIMING37_TSM_SPARE1_EN_RX_HI field. */
40937 #define XCVR_RD_TSM_TIMING37_TSM_SPARE1_EN_RX_HI(base) ((XCVR_TSM_TIMING37_REG(base) & XCVR_TSM_TIMING37_TSM_SPARE1_EN_RX_HI_MASK) >> XCVR_TSM_TIMING37_TSM_SPARE1_EN_RX_HI_SHIFT)
40938 #define XCVR_BRD_TSM_TIMING37_TSM_SPARE1_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING37_REG(base), XCVR_TSM_TIMING37_TSM_SPARE1_EN_RX_HI_SHIFT, XCVR_TSM_TIMING37_TSM_SPARE1_EN_RX_HI_WIDTH))
40939 
40940 /*! @brief Set the TSM_SPARE1_EN_RX_HI field to a new value. */
40941 #define XCVR_WR_TSM_TIMING37_TSM_SPARE1_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING37(base, XCVR_TSM_TIMING37_TSM_SPARE1_EN_RX_HI_MASK, XCVR_TSM_TIMING37_TSM_SPARE1_EN_RX_HI(value)))
40942 #define XCVR_BWR_TSM_TIMING37_TSM_SPARE1_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING37_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING37_TSM_SPARE1_EN_RX_HI_SHIFT), XCVR_TSM_TIMING37_TSM_SPARE1_EN_RX_HI_SHIFT, XCVR_TSM_TIMING37_TSM_SPARE1_EN_RX_HI_WIDTH))
40943 /*@}*/
40944 
40945 /*!
40946  * @name Register XCVR_TSM_TIMING37, field TSM_SPARE1_EN_RX_LO[31:24] (RW)
40947  *
40948  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
40949  * at which the TSM_SPARE1_EN signal or group will transition from HI to LO.
40950  */
40951 /*@{*/
40952 /*! @brief Read current value of the XCVR_TSM_TIMING37_TSM_SPARE1_EN_RX_LO field. */
40953 #define XCVR_RD_TSM_TIMING37_TSM_SPARE1_EN_RX_LO(base) ((XCVR_TSM_TIMING37_REG(base) & XCVR_TSM_TIMING37_TSM_SPARE1_EN_RX_LO_MASK) >> XCVR_TSM_TIMING37_TSM_SPARE1_EN_RX_LO_SHIFT)
40954 #define XCVR_BRD_TSM_TIMING37_TSM_SPARE1_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING37_REG(base), XCVR_TSM_TIMING37_TSM_SPARE1_EN_RX_LO_SHIFT, XCVR_TSM_TIMING37_TSM_SPARE1_EN_RX_LO_WIDTH))
40955 
40956 /*! @brief Set the TSM_SPARE1_EN_RX_LO field to a new value. */
40957 #define XCVR_WR_TSM_TIMING37_TSM_SPARE1_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING37(base, XCVR_TSM_TIMING37_TSM_SPARE1_EN_RX_LO_MASK, XCVR_TSM_TIMING37_TSM_SPARE1_EN_RX_LO(value)))
40958 #define XCVR_BWR_TSM_TIMING37_TSM_SPARE1_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING37_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING37_TSM_SPARE1_EN_RX_LO_SHIFT), XCVR_TSM_TIMING37_TSM_SPARE1_EN_RX_LO_SHIFT, XCVR_TSM_TIMING37_TSM_SPARE1_EN_RX_LO_WIDTH))
40959 /*@}*/
40960 
40961 /*******************************************************************************
40962  * XCVR_TSM_TIMING38 - TSM_TIMING38
40963  ******************************************************************************/
40964 
40965 /*!
40966  * @brief XCVR_TSM_TIMING38 - TSM_TIMING38 (RW)
40967  *
40968  * Reset value: 0xFFFFFFFFU
40969  *
40970  * This register contains the timing values to control the assertion and
40971  * deassertion times for both TX and RX sequences for the TSM_SPARE2_EN TSM signal or
40972  * signal group.
40973  */
40974 /*!
40975  * @name Constants and macros for entire XCVR_TSM_TIMING38 register
40976  */
40977 /*@{*/
40978 #define XCVR_RD_TSM_TIMING38(base) (XCVR_TSM_TIMING38_REG(base))
40979 #define XCVR_WR_TSM_TIMING38(base, value) (XCVR_TSM_TIMING38_REG(base) = (value))
40980 #define XCVR_RMW_TSM_TIMING38(base, mask, value) (XCVR_WR_TSM_TIMING38(base, (XCVR_RD_TSM_TIMING38(base) & ~(mask)) | (value)))
40981 #define XCVR_SET_TSM_TIMING38(base, value) (BME_OR32(&XCVR_TSM_TIMING38_REG(base), (uint32_t)(value)))
40982 #define XCVR_CLR_TSM_TIMING38(base, value) (BME_AND32(&XCVR_TSM_TIMING38_REG(base), (uint32_t)(~(value))))
40983 #define XCVR_TOG_TSM_TIMING38(base, value) (BME_XOR32(&XCVR_TSM_TIMING38_REG(base), (uint32_t)(value)))
40984 /*@}*/
40985 
40986 /*
40987  * Constants & macros for individual XCVR_TSM_TIMING38 bitfields
40988  */
40989 
40990 /*!
40991  * @name Register XCVR_TSM_TIMING38, field TSM_SPARE2_EN_TX_HI[7:0] (RW)
40992  *
40993  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
40994  * at which the TSM_SPARE2_EN signal or group will transition from LO to HI.
40995  */
40996 /*@{*/
40997 /*! @brief Read current value of the XCVR_TSM_TIMING38_TSM_SPARE2_EN_TX_HI field. */
40998 #define XCVR_RD_TSM_TIMING38_TSM_SPARE2_EN_TX_HI(base) ((XCVR_TSM_TIMING38_REG(base) & XCVR_TSM_TIMING38_TSM_SPARE2_EN_TX_HI_MASK) >> XCVR_TSM_TIMING38_TSM_SPARE2_EN_TX_HI_SHIFT)
40999 #define XCVR_BRD_TSM_TIMING38_TSM_SPARE2_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING38_REG(base), XCVR_TSM_TIMING38_TSM_SPARE2_EN_TX_HI_SHIFT, XCVR_TSM_TIMING38_TSM_SPARE2_EN_TX_HI_WIDTH))
41000 
41001 /*! @brief Set the TSM_SPARE2_EN_TX_HI field to a new value. */
41002 #define XCVR_WR_TSM_TIMING38_TSM_SPARE2_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING38(base, XCVR_TSM_TIMING38_TSM_SPARE2_EN_TX_HI_MASK, XCVR_TSM_TIMING38_TSM_SPARE2_EN_TX_HI(value)))
41003 #define XCVR_BWR_TSM_TIMING38_TSM_SPARE2_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING38_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING38_TSM_SPARE2_EN_TX_HI_SHIFT), XCVR_TSM_TIMING38_TSM_SPARE2_EN_TX_HI_SHIFT, XCVR_TSM_TIMING38_TSM_SPARE2_EN_TX_HI_WIDTH))
41004 /*@}*/
41005 
41006 /*!
41007  * @name Register XCVR_TSM_TIMING38, field TSM_SPARE2_EN_TX_LO[15:8] (RW)
41008  *
41009  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
41010  * at which the TSM_SPARE2_EN signal or group will transition from HI to LO.
41011  */
41012 /*@{*/
41013 /*! @brief Read current value of the XCVR_TSM_TIMING38_TSM_SPARE2_EN_TX_LO field. */
41014 #define XCVR_RD_TSM_TIMING38_TSM_SPARE2_EN_TX_LO(base) ((XCVR_TSM_TIMING38_REG(base) & XCVR_TSM_TIMING38_TSM_SPARE2_EN_TX_LO_MASK) >> XCVR_TSM_TIMING38_TSM_SPARE2_EN_TX_LO_SHIFT)
41015 #define XCVR_BRD_TSM_TIMING38_TSM_SPARE2_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING38_REG(base), XCVR_TSM_TIMING38_TSM_SPARE2_EN_TX_LO_SHIFT, XCVR_TSM_TIMING38_TSM_SPARE2_EN_TX_LO_WIDTH))
41016 
41017 /*! @brief Set the TSM_SPARE2_EN_TX_LO field to a new value. */
41018 #define XCVR_WR_TSM_TIMING38_TSM_SPARE2_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING38(base, XCVR_TSM_TIMING38_TSM_SPARE2_EN_TX_LO_MASK, XCVR_TSM_TIMING38_TSM_SPARE2_EN_TX_LO(value)))
41019 #define XCVR_BWR_TSM_TIMING38_TSM_SPARE2_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING38_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING38_TSM_SPARE2_EN_TX_LO_SHIFT), XCVR_TSM_TIMING38_TSM_SPARE2_EN_TX_LO_SHIFT, XCVR_TSM_TIMING38_TSM_SPARE2_EN_TX_LO_WIDTH))
41020 /*@}*/
41021 
41022 /*!
41023  * @name Register XCVR_TSM_TIMING38, field TSM_SPARE2_EN_RX_HI[23:16] (RW)
41024  *
41025  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
41026  * at which the TSM_SPARE2_EN signal or group will transition from LO to HI.
41027  */
41028 /*@{*/
41029 /*! @brief Read current value of the XCVR_TSM_TIMING38_TSM_SPARE2_EN_RX_HI field. */
41030 #define XCVR_RD_TSM_TIMING38_TSM_SPARE2_EN_RX_HI(base) ((XCVR_TSM_TIMING38_REG(base) & XCVR_TSM_TIMING38_TSM_SPARE2_EN_RX_HI_MASK) >> XCVR_TSM_TIMING38_TSM_SPARE2_EN_RX_HI_SHIFT)
41031 #define XCVR_BRD_TSM_TIMING38_TSM_SPARE2_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING38_REG(base), XCVR_TSM_TIMING38_TSM_SPARE2_EN_RX_HI_SHIFT, XCVR_TSM_TIMING38_TSM_SPARE2_EN_RX_HI_WIDTH))
41032 
41033 /*! @brief Set the TSM_SPARE2_EN_RX_HI field to a new value. */
41034 #define XCVR_WR_TSM_TIMING38_TSM_SPARE2_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING38(base, XCVR_TSM_TIMING38_TSM_SPARE2_EN_RX_HI_MASK, XCVR_TSM_TIMING38_TSM_SPARE2_EN_RX_HI(value)))
41035 #define XCVR_BWR_TSM_TIMING38_TSM_SPARE2_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING38_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING38_TSM_SPARE2_EN_RX_HI_SHIFT), XCVR_TSM_TIMING38_TSM_SPARE2_EN_RX_HI_SHIFT, XCVR_TSM_TIMING38_TSM_SPARE2_EN_RX_HI_WIDTH))
41036 /*@}*/
41037 
41038 /*!
41039  * @name Register XCVR_TSM_TIMING38, field TSM_SPARE2_EN_RX_LO[31:24] (RW)
41040  *
41041  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
41042  * at which the TSM_SPARE2_EN signal or group will transition from HI to LO.
41043  */
41044 /*@{*/
41045 /*! @brief Read current value of the XCVR_TSM_TIMING38_TSM_SPARE2_EN_RX_LO field. */
41046 #define XCVR_RD_TSM_TIMING38_TSM_SPARE2_EN_RX_LO(base) ((XCVR_TSM_TIMING38_REG(base) & XCVR_TSM_TIMING38_TSM_SPARE2_EN_RX_LO_MASK) >> XCVR_TSM_TIMING38_TSM_SPARE2_EN_RX_LO_SHIFT)
41047 #define XCVR_BRD_TSM_TIMING38_TSM_SPARE2_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING38_REG(base), XCVR_TSM_TIMING38_TSM_SPARE2_EN_RX_LO_SHIFT, XCVR_TSM_TIMING38_TSM_SPARE2_EN_RX_LO_WIDTH))
41048 
41049 /*! @brief Set the TSM_SPARE2_EN_RX_LO field to a new value. */
41050 #define XCVR_WR_TSM_TIMING38_TSM_SPARE2_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING38(base, XCVR_TSM_TIMING38_TSM_SPARE2_EN_RX_LO_MASK, XCVR_TSM_TIMING38_TSM_SPARE2_EN_RX_LO(value)))
41051 #define XCVR_BWR_TSM_TIMING38_TSM_SPARE2_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING38_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING38_TSM_SPARE2_EN_RX_LO_SHIFT), XCVR_TSM_TIMING38_TSM_SPARE2_EN_RX_LO_SHIFT, XCVR_TSM_TIMING38_TSM_SPARE2_EN_RX_LO_WIDTH))
41052 /*@}*/
41053 
41054 /*******************************************************************************
41055  * XCVR_TSM_TIMING39 - TSM_TIMING39
41056  ******************************************************************************/
41057 
41058 /*!
41059  * @brief XCVR_TSM_TIMING39 - TSM_TIMING39 (RW)
41060  *
41061  * Reset value: 0xFFFFFFFFU
41062  *
41063  * This register contains the timing values to control the assertion and
41064  * deassertion times for both TX and RX sequences for the TSM_SPARE3_EN TSM signal or
41065  * signal group.
41066  */
41067 /*!
41068  * @name Constants and macros for entire XCVR_TSM_TIMING39 register
41069  */
41070 /*@{*/
41071 #define XCVR_RD_TSM_TIMING39(base) (XCVR_TSM_TIMING39_REG(base))
41072 #define XCVR_WR_TSM_TIMING39(base, value) (XCVR_TSM_TIMING39_REG(base) = (value))
41073 #define XCVR_RMW_TSM_TIMING39(base, mask, value) (XCVR_WR_TSM_TIMING39(base, (XCVR_RD_TSM_TIMING39(base) & ~(mask)) | (value)))
41074 #define XCVR_SET_TSM_TIMING39(base, value) (BME_OR32(&XCVR_TSM_TIMING39_REG(base), (uint32_t)(value)))
41075 #define XCVR_CLR_TSM_TIMING39(base, value) (BME_AND32(&XCVR_TSM_TIMING39_REG(base), (uint32_t)(~(value))))
41076 #define XCVR_TOG_TSM_TIMING39(base, value) (BME_XOR32(&XCVR_TSM_TIMING39_REG(base), (uint32_t)(value)))
41077 /*@}*/
41078 
41079 /*
41080  * Constants & macros for individual XCVR_TSM_TIMING39 bitfields
41081  */
41082 
41083 /*!
41084  * @name Register XCVR_TSM_TIMING39, field TSM_SPARE3_EN_TX_HI[7:0] (RW)
41085  *
41086  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
41087  * at which the TSM_SPARE3_EN signal or group will transition from LO to HI.
41088  */
41089 /*@{*/
41090 /*! @brief Read current value of the XCVR_TSM_TIMING39_TSM_SPARE3_EN_TX_HI field. */
41091 #define XCVR_RD_TSM_TIMING39_TSM_SPARE3_EN_TX_HI(base) ((XCVR_TSM_TIMING39_REG(base) & XCVR_TSM_TIMING39_TSM_SPARE3_EN_TX_HI_MASK) >> XCVR_TSM_TIMING39_TSM_SPARE3_EN_TX_HI_SHIFT)
41092 #define XCVR_BRD_TSM_TIMING39_TSM_SPARE3_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING39_REG(base), XCVR_TSM_TIMING39_TSM_SPARE3_EN_TX_HI_SHIFT, XCVR_TSM_TIMING39_TSM_SPARE3_EN_TX_HI_WIDTH))
41093 
41094 /*! @brief Set the TSM_SPARE3_EN_TX_HI field to a new value. */
41095 #define XCVR_WR_TSM_TIMING39_TSM_SPARE3_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING39(base, XCVR_TSM_TIMING39_TSM_SPARE3_EN_TX_HI_MASK, XCVR_TSM_TIMING39_TSM_SPARE3_EN_TX_HI(value)))
41096 #define XCVR_BWR_TSM_TIMING39_TSM_SPARE3_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING39_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING39_TSM_SPARE3_EN_TX_HI_SHIFT), XCVR_TSM_TIMING39_TSM_SPARE3_EN_TX_HI_SHIFT, XCVR_TSM_TIMING39_TSM_SPARE3_EN_TX_HI_WIDTH))
41097 /*@}*/
41098 
41099 /*!
41100  * @name Register XCVR_TSM_TIMING39, field TSM_SPARE3_EN_TX_LO[15:8] (RW)
41101  *
41102  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
41103  * at which the TSM_SPARE3_EN signal or group will transition from HI to LO.
41104  */
41105 /*@{*/
41106 /*! @brief Read current value of the XCVR_TSM_TIMING39_TSM_SPARE3_EN_TX_LO field. */
41107 #define XCVR_RD_TSM_TIMING39_TSM_SPARE3_EN_TX_LO(base) ((XCVR_TSM_TIMING39_REG(base) & XCVR_TSM_TIMING39_TSM_SPARE3_EN_TX_LO_MASK) >> XCVR_TSM_TIMING39_TSM_SPARE3_EN_TX_LO_SHIFT)
41108 #define XCVR_BRD_TSM_TIMING39_TSM_SPARE3_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING39_REG(base), XCVR_TSM_TIMING39_TSM_SPARE3_EN_TX_LO_SHIFT, XCVR_TSM_TIMING39_TSM_SPARE3_EN_TX_LO_WIDTH))
41109 
41110 /*! @brief Set the TSM_SPARE3_EN_TX_LO field to a new value. */
41111 #define XCVR_WR_TSM_TIMING39_TSM_SPARE3_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING39(base, XCVR_TSM_TIMING39_TSM_SPARE3_EN_TX_LO_MASK, XCVR_TSM_TIMING39_TSM_SPARE3_EN_TX_LO(value)))
41112 #define XCVR_BWR_TSM_TIMING39_TSM_SPARE3_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING39_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING39_TSM_SPARE3_EN_TX_LO_SHIFT), XCVR_TSM_TIMING39_TSM_SPARE3_EN_TX_LO_SHIFT, XCVR_TSM_TIMING39_TSM_SPARE3_EN_TX_LO_WIDTH))
41113 /*@}*/
41114 
41115 /*!
41116  * @name Register XCVR_TSM_TIMING39, field TSM_SPARE3_EN_RX_HI[23:16] (RW)
41117  *
41118  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
41119  * at which the TSM_SPARE3_EN signal or group will transition from LO to HI.
41120  */
41121 /*@{*/
41122 /*! @brief Read current value of the XCVR_TSM_TIMING39_TSM_SPARE3_EN_RX_HI field. */
41123 #define XCVR_RD_TSM_TIMING39_TSM_SPARE3_EN_RX_HI(base) ((XCVR_TSM_TIMING39_REG(base) & XCVR_TSM_TIMING39_TSM_SPARE3_EN_RX_HI_MASK) >> XCVR_TSM_TIMING39_TSM_SPARE3_EN_RX_HI_SHIFT)
41124 #define XCVR_BRD_TSM_TIMING39_TSM_SPARE3_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING39_REG(base), XCVR_TSM_TIMING39_TSM_SPARE3_EN_RX_HI_SHIFT, XCVR_TSM_TIMING39_TSM_SPARE3_EN_RX_HI_WIDTH))
41125 
41126 /*! @brief Set the TSM_SPARE3_EN_RX_HI field to a new value. */
41127 #define XCVR_WR_TSM_TIMING39_TSM_SPARE3_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING39(base, XCVR_TSM_TIMING39_TSM_SPARE3_EN_RX_HI_MASK, XCVR_TSM_TIMING39_TSM_SPARE3_EN_RX_HI(value)))
41128 #define XCVR_BWR_TSM_TIMING39_TSM_SPARE3_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING39_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING39_TSM_SPARE3_EN_RX_HI_SHIFT), XCVR_TSM_TIMING39_TSM_SPARE3_EN_RX_HI_SHIFT, XCVR_TSM_TIMING39_TSM_SPARE3_EN_RX_HI_WIDTH))
41129 /*@}*/
41130 
41131 /*!
41132  * @name Register XCVR_TSM_TIMING39, field TSM_SPARE3_EN_RX_LO[31:24] (RW)
41133  *
41134  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
41135  * at which the TSM_SPARE3_EN signal or group will transition from HI to LO.
41136  */
41137 /*@{*/
41138 /*! @brief Read current value of the XCVR_TSM_TIMING39_TSM_SPARE3_EN_RX_LO field. */
41139 #define XCVR_RD_TSM_TIMING39_TSM_SPARE3_EN_RX_LO(base) ((XCVR_TSM_TIMING39_REG(base) & XCVR_TSM_TIMING39_TSM_SPARE3_EN_RX_LO_MASK) >> XCVR_TSM_TIMING39_TSM_SPARE3_EN_RX_LO_SHIFT)
41140 #define XCVR_BRD_TSM_TIMING39_TSM_SPARE3_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING39_REG(base), XCVR_TSM_TIMING39_TSM_SPARE3_EN_RX_LO_SHIFT, XCVR_TSM_TIMING39_TSM_SPARE3_EN_RX_LO_WIDTH))
41141 
41142 /*! @brief Set the TSM_SPARE3_EN_RX_LO field to a new value. */
41143 #define XCVR_WR_TSM_TIMING39_TSM_SPARE3_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING39(base, XCVR_TSM_TIMING39_TSM_SPARE3_EN_RX_LO_MASK, XCVR_TSM_TIMING39_TSM_SPARE3_EN_RX_LO(value)))
41144 #define XCVR_BWR_TSM_TIMING39_TSM_SPARE3_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING39_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING39_TSM_SPARE3_EN_RX_LO_SHIFT), XCVR_TSM_TIMING39_TSM_SPARE3_EN_RX_LO_SHIFT, XCVR_TSM_TIMING39_TSM_SPARE3_EN_RX_LO_WIDTH))
41145 /*@}*/
41146 
41147 /*******************************************************************************
41148  * XCVR_TSM_TIMING40 - TSM_TIMING40
41149  ******************************************************************************/
41150 
41151 /*!
41152  * @brief XCVR_TSM_TIMING40 - TSM_TIMING40 (RW)
41153  *
41154  * Reset value: 0xFFFFFFFFU
41155  *
41156  * This register contains the timing values to control the assertion and
41157  * deassertion times for both TX and RX sequences for the GPIO0_TRIG_EN TSM signal or
41158  * signal group.
41159  */
41160 /*!
41161  * @name Constants and macros for entire XCVR_TSM_TIMING40 register
41162  */
41163 /*@{*/
41164 #define XCVR_RD_TSM_TIMING40(base) (XCVR_TSM_TIMING40_REG(base))
41165 #define XCVR_WR_TSM_TIMING40(base, value) (XCVR_TSM_TIMING40_REG(base) = (value))
41166 #define XCVR_RMW_TSM_TIMING40(base, mask, value) (XCVR_WR_TSM_TIMING40(base, (XCVR_RD_TSM_TIMING40(base) & ~(mask)) | (value)))
41167 #define XCVR_SET_TSM_TIMING40(base, value) (BME_OR32(&XCVR_TSM_TIMING40_REG(base), (uint32_t)(value)))
41168 #define XCVR_CLR_TSM_TIMING40(base, value) (BME_AND32(&XCVR_TSM_TIMING40_REG(base), (uint32_t)(~(value))))
41169 #define XCVR_TOG_TSM_TIMING40(base, value) (BME_XOR32(&XCVR_TSM_TIMING40_REG(base), (uint32_t)(value)))
41170 /*@}*/
41171 
41172 /*
41173  * Constants & macros for individual XCVR_TSM_TIMING40 bitfields
41174  */
41175 
41176 /*!
41177  * @name Register XCVR_TSM_TIMING40, field GPIO0_TRIG_EN_TX_HI[7:0] (RW)
41178  *
41179  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
41180  * at which the GPIO0_TRIG_EN signal or group will transition from LO to HI.
41181  */
41182 /*@{*/
41183 /*! @brief Read current value of the XCVR_TSM_TIMING40_GPIO0_TRIG_EN_TX_HI field. */
41184 #define XCVR_RD_TSM_TIMING40_GPIO0_TRIG_EN_TX_HI(base) ((XCVR_TSM_TIMING40_REG(base) & XCVR_TSM_TIMING40_GPIO0_TRIG_EN_TX_HI_MASK) >> XCVR_TSM_TIMING40_GPIO0_TRIG_EN_TX_HI_SHIFT)
41185 #define XCVR_BRD_TSM_TIMING40_GPIO0_TRIG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING40_REG(base), XCVR_TSM_TIMING40_GPIO0_TRIG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING40_GPIO0_TRIG_EN_TX_HI_WIDTH))
41186 
41187 /*! @brief Set the GPIO0_TRIG_EN_TX_HI field to a new value. */
41188 #define XCVR_WR_TSM_TIMING40_GPIO0_TRIG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING40(base, XCVR_TSM_TIMING40_GPIO0_TRIG_EN_TX_HI_MASK, XCVR_TSM_TIMING40_GPIO0_TRIG_EN_TX_HI(value)))
41189 #define XCVR_BWR_TSM_TIMING40_GPIO0_TRIG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING40_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING40_GPIO0_TRIG_EN_TX_HI_SHIFT), XCVR_TSM_TIMING40_GPIO0_TRIG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING40_GPIO0_TRIG_EN_TX_HI_WIDTH))
41190 /*@}*/
41191 
41192 /*!
41193  * @name Register XCVR_TSM_TIMING40, field GPIO0_TRIG_EN_TX_LO[15:8] (RW)
41194  *
41195  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
41196  * at which the GPIO0_TRIG_EN signal or group will transition from HI to LO.
41197  */
41198 /*@{*/
41199 /*! @brief Read current value of the XCVR_TSM_TIMING40_GPIO0_TRIG_EN_TX_LO field. */
41200 #define XCVR_RD_TSM_TIMING40_GPIO0_TRIG_EN_TX_LO(base) ((XCVR_TSM_TIMING40_REG(base) & XCVR_TSM_TIMING40_GPIO0_TRIG_EN_TX_LO_MASK) >> XCVR_TSM_TIMING40_GPIO0_TRIG_EN_TX_LO_SHIFT)
41201 #define XCVR_BRD_TSM_TIMING40_GPIO0_TRIG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING40_REG(base), XCVR_TSM_TIMING40_GPIO0_TRIG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING40_GPIO0_TRIG_EN_TX_LO_WIDTH))
41202 
41203 /*! @brief Set the GPIO0_TRIG_EN_TX_LO field to a new value. */
41204 #define XCVR_WR_TSM_TIMING40_GPIO0_TRIG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING40(base, XCVR_TSM_TIMING40_GPIO0_TRIG_EN_TX_LO_MASK, XCVR_TSM_TIMING40_GPIO0_TRIG_EN_TX_LO(value)))
41205 #define XCVR_BWR_TSM_TIMING40_GPIO0_TRIG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING40_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING40_GPIO0_TRIG_EN_TX_LO_SHIFT), XCVR_TSM_TIMING40_GPIO0_TRIG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING40_GPIO0_TRIG_EN_TX_LO_WIDTH))
41206 /*@}*/
41207 
41208 /*!
41209  * @name Register XCVR_TSM_TIMING40, field GPIO0_TRIG_EN_RX_HI[23:16] (RW)
41210  *
41211  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
41212  * at which the GPIO0_TRIG_EN signal or group will transition from LO to HI.
41213  */
41214 /*@{*/
41215 /*! @brief Read current value of the XCVR_TSM_TIMING40_GPIO0_TRIG_EN_RX_HI field. */
41216 #define XCVR_RD_TSM_TIMING40_GPIO0_TRIG_EN_RX_HI(base) ((XCVR_TSM_TIMING40_REG(base) & XCVR_TSM_TIMING40_GPIO0_TRIG_EN_RX_HI_MASK) >> XCVR_TSM_TIMING40_GPIO0_TRIG_EN_RX_HI_SHIFT)
41217 #define XCVR_BRD_TSM_TIMING40_GPIO0_TRIG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING40_REG(base), XCVR_TSM_TIMING40_GPIO0_TRIG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING40_GPIO0_TRIG_EN_RX_HI_WIDTH))
41218 
41219 /*! @brief Set the GPIO0_TRIG_EN_RX_HI field to a new value. */
41220 #define XCVR_WR_TSM_TIMING40_GPIO0_TRIG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING40(base, XCVR_TSM_TIMING40_GPIO0_TRIG_EN_RX_HI_MASK, XCVR_TSM_TIMING40_GPIO0_TRIG_EN_RX_HI(value)))
41221 #define XCVR_BWR_TSM_TIMING40_GPIO0_TRIG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING40_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING40_GPIO0_TRIG_EN_RX_HI_SHIFT), XCVR_TSM_TIMING40_GPIO0_TRIG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING40_GPIO0_TRIG_EN_RX_HI_WIDTH))
41222 /*@}*/
41223 
41224 /*!
41225  * @name Register XCVR_TSM_TIMING40, field GPIO0_TRIG_EN_RX_LO[31:24] (RW)
41226  *
41227  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
41228  * at which the GPIO0_TRIG_EN signal or group will transition from HI to LO.
41229  */
41230 /*@{*/
41231 /*! @brief Read current value of the XCVR_TSM_TIMING40_GPIO0_TRIG_EN_RX_LO field. */
41232 #define XCVR_RD_TSM_TIMING40_GPIO0_TRIG_EN_RX_LO(base) ((XCVR_TSM_TIMING40_REG(base) & XCVR_TSM_TIMING40_GPIO0_TRIG_EN_RX_LO_MASK) >> XCVR_TSM_TIMING40_GPIO0_TRIG_EN_RX_LO_SHIFT)
41233 #define XCVR_BRD_TSM_TIMING40_GPIO0_TRIG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING40_REG(base), XCVR_TSM_TIMING40_GPIO0_TRIG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING40_GPIO0_TRIG_EN_RX_LO_WIDTH))
41234 
41235 /*! @brief Set the GPIO0_TRIG_EN_RX_LO field to a new value. */
41236 #define XCVR_WR_TSM_TIMING40_GPIO0_TRIG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING40(base, XCVR_TSM_TIMING40_GPIO0_TRIG_EN_RX_LO_MASK, XCVR_TSM_TIMING40_GPIO0_TRIG_EN_RX_LO(value)))
41237 #define XCVR_BWR_TSM_TIMING40_GPIO0_TRIG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING40_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING40_GPIO0_TRIG_EN_RX_LO_SHIFT), XCVR_TSM_TIMING40_GPIO0_TRIG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING40_GPIO0_TRIG_EN_RX_LO_WIDTH))
41238 /*@}*/
41239 
41240 /*******************************************************************************
41241  * XCVR_TSM_TIMING41 - TSM_TIMING41
41242  ******************************************************************************/
41243 
41244 /*!
41245  * @brief XCVR_TSM_TIMING41 - TSM_TIMING41 (RW)
41246  *
41247  * Reset value: 0xFFFFFFFFU
41248  *
41249  * This register contains the timing values to control the assertion and
41250  * deassertion times for both TX and RX sequences for the GPIO1_TRIG_EN TSM signal or
41251  * signal group.
41252  */
41253 /*!
41254  * @name Constants and macros for entire XCVR_TSM_TIMING41 register
41255  */
41256 /*@{*/
41257 #define XCVR_RD_TSM_TIMING41(base) (XCVR_TSM_TIMING41_REG(base))
41258 #define XCVR_WR_TSM_TIMING41(base, value) (XCVR_TSM_TIMING41_REG(base) = (value))
41259 #define XCVR_RMW_TSM_TIMING41(base, mask, value) (XCVR_WR_TSM_TIMING41(base, (XCVR_RD_TSM_TIMING41(base) & ~(mask)) | (value)))
41260 #define XCVR_SET_TSM_TIMING41(base, value) (BME_OR32(&XCVR_TSM_TIMING41_REG(base), (uint32_t)(value)))
41261 #define XCVR_CLR_TSM_TIMING41(base, value) (BME_AND32(&XCVR_TSM_TIMING41_REG(base), (uint32_t)(~(value))))
41262 #define XCVR_TOG_TSM_TIMING41(base, value) (BME_XOR32(&XCVR_TSM_TIMING41_REG(base), (uint32_t)(value)))
41263 /*@}*/
41264 
41265 /*
41266  * Constants & macros for individual XCVR_TSM_TIMING41 bitfields
41267  */
41268 
41269 /*!
41270  * @name Register XCVR_TSM_TIMING41, field GPIO1_TRIG_EN_TX_HI[7:0] (RW)
41271  *
41272  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
41273  * at which the GPIO1_TRIG_EN signal or group will transition from LO to HI.
41274  */
41275 /*@{*/
41276 /*! @brief Read current value of the XCVR_TSM_TIMING41_GPIO1_TRIG_EN_TX_HI field. */
41277 #define XCVR_RD_TSM_TIMING41_GPIO1_TRIG_EN_TX_HI(base) ((XCVR_TSM_TIMING41_REG(base) & XCVR_TSM_TIMING41_GPIO1_TRIG_EN_TX_HI_MASK) >> XCVR_TSM_TIMING41_GPIO1_TRIG_EN_TX_HI_SHIFT)
41278 #define XCVR_BRD_TSM_TIMING41_GPIO1_TRIG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING41_REG(base), XCVR_TSM_TIMING41_GPIO1_TRIG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING41_GPIO1_TRIG_EN_TX_HI_WIDTH))
41279 
41280 /*! @brief Set the GPIO1_TRIG_EN_TX_HI field to a new value. */
41281 #define XCVR_WR_TSM_TIMING41_GPIO1_TRIG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING41(base, XCVR_TSM_TIMING41_GPIO1_TRIG_EN_TX_HI_MASK, XCVR_TSM_TIMING41_GPIO1_TRIG_EN_TX_HI(value)))
41282 #define XCVR_BWR_TSM_TIMING41_GPIO1_TRIG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING41_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING41_GPIO1_TRIG_EN_TX_HI_SHIFT), XCVR_TSM_TIMING41_GPIO1_TRIG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING41_GPIO1_TRIG_EN_TX_HI_WIDTH))
41283 /*@}*/
41284 
41285 /*!
41286  * @name Register XCVR_TSM_TIMING41, field GPIO1_TRIG_EN_TX_LO[15:8] (RW)
41287  *
41288  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
41289  * at which the GPIO1_TRIG_EN signal or group will transition from HI to LO.
41290  */
41291 /*@{*/
41292 /*! @brief Read current value of the XCVR_TSM_TIMING41_GPIO1_TRIG_EN_TX_LO field. */
41293 #define XCVR_RD_TSM_TIMING41_GPIO1_TRIG_EN_TX_LO(base) ((XCVR_TSM_TIMING41_REG(base) & XCVR_TSM_TIMING41_GPIO1_TRIG_EN_TX_LO_MASK) >> XCVR_TSM_TIMING41_GPIO1_TRIG_EN_TX_LO_SHIFT)
41294 #define XCVR_BRD_TSM_TIMING41_GPIO1_TRIG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING41_REG(base), XCVR_TSM_TIMING41_GPIO1_TRIG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING41_GPIO1_TRIG_EN_TX_LO_WIDTH))
41295 
41296 /*! @brief Set the GPIO1_TRIG_EN_TX_LO field to a new value. */
41297 #define XCVR_WR_TSM_TIMING41_GPIO1_TRIG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING41(base, XCVR_TSM_TIMING41_GPIO1_TRIG_EN_TX_LO_MASK, XCVR_TSM_TIMING41_GPIO1_TRIG_EN_TX_LO(value)))
41298 #define XCVR_BWR_TSM_TIMING41_GPIO1_TRIG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING41_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING41_GPIO1_TRIG_EN_TX_LO_SHIFT), XCVR_TSM_TIMING41_GPIO1_TRIG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING41_GPIO1_TRIG_EN_TX_LO_WIDTH))
41299 /*@}*/
41300 
41301 /*!
41302  * @name Register XCVR_TSM_TIMING41, field GPIO1_TRIG_EN_RX_HI[23:16] (RW)
41303  *
41304  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
41305  * at which the GPIO1_TRIG_EN signal or group will transition from LO to HI.
41306  */
41307 /*@{*/
41308 /*! @brief Read current value of the XCVR_TSM_TIMING41_GPIO1_TRIG_EN_RX_HI field. */
41309 #define XCVR_RD_TSM_TIMING41_GPIO1_TRIG_EN_RX_HI(base) ((XCVR_TSM_TIMING41_REG(base) & XCVR_TSM_TIMING41_GPIO1_TRIG_EN_RX_HI_MASK) >> XCVR_TSM_TIMING41_GPIO1_TRIG_EN_RX_HI_SHIFT)
41310 #define XCVR_BRD_TSM_TIMING41_GPIO1_TRIG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING41_REG(base), XCVR_TSM_TIMING41_GPIO1_TRIG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING41_GPIO1_TRIG_EN_RX_HI_WIDTH))
41311 
41312 /*! @brief Set the GPIO1_TRIG_EN_RX_HI field to a new value. */
41313 #define XCVR_WR_TSM_TIMING41_GPIO1_TRIG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING41(base, XCVR_TSM_TIMING41_GPIO1_TRIG_EN_RX_HI_MASK, XCVR_TSM_TIMING41_GPIO1_TRIG_EN_RX_HI(value)))
41314 #define XCVR_BWR_TSM_TIMING41_GPIO1_TRIG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING41_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING41_GPIO1_TRIG_EN_RX_HI_SHIFT), XCVR_TSM_TIMING41_GPIO1_TRIG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING41_GPIO1_TRIG_EN_RX_HI_WIDTH))
41315 /*@}*/
41316 
41317 /*!
41318  * @name Register XCVR_TSM_TIMING41, field GPIO1_TRIG_EN_RX_LO[31:24] (RW)
41319  *
41320  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
41321  * at which the GPIO1_TRIG_EN signal or group will transition from HI to LO.
41322  */
41323 /*@{*/
41324 /*! @brief Read current value of the XCVR_TSM_TIMING41_GPIO1_TRIG_EN_RX_LO field. */
41325 #define XCVR_RD_TSM_TIMING41_GPIO1_TRIG_EN_RX_LO(base) ((XCVR_TSM_TIMING41_REG(base) & XCVR_TSM_TIMING41_GPIO1_TRIG_EN_RX_LO_MASK) >> XCVR_TSM_TIMING41_GPIO1_TRIG_EN_RX_LO_SHIFT)
41326 #define XCVR_BRD_TSM_TIMING41_GPIO1_TRIG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING41_REG(base), XCVR_TSM_TIMING41_GPIO1_TRIG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING41_GPIO1_TRIG_EN_RX_LO_WIDTH))
41327 
41328 /*! @brief Set the GPIO1_TRIG_EN_RX_LO field to a new value. */
41329 #define XCVR_WR_TSM_TIMING41_GPIO1_TRIG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING41(base, XCVR_TSM_TIMING41_GPIO1_TRIG_EN_RX_LO_MASK, XCVR_TSM_TIMING41_GPIO1_TRIG_EN_RX_LO(value)))
41330 #define XCVR_BWR_TSM_TIMING41_GPIO1_TRIG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING41_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING41_GPIO1_TRIG_EN_RX_LO_SHIFT), XCVR_TSM_TIMING41_GPIO1_TRIG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING41_GPIO1_TRIG_EN_RX_LO_WIDTH))
41331 /*@}*/
41332 
41333 /*******************************************************************************
41334  * XCVR_TSM_TIMING42 - TSM_TIMING42
41335  ******************************************************************************/
41336 
41337 /*!
41338  * @brief XCVR_TSM_TIMING42 - TSM_TIMING42 (RW)
41339  *
41340  * Reset value: 0xFFFFFFFFU
41341  *
41342  * This register contains the timing values to control the assertion and
41343  * deassertion times for both TX and RX sequences for the GPIO2_TRIG_EN TSM signal or
41344  * signal group.
41345  */
41346 /*!
41347  * @name Constants and macros for entire XCVR_TSM_TIMING42 register
41348  */
41349 /*@{*/
41350 #define XCVR_RD_TSM_TIMING42(base) (XCVR_TSM_TIMING42_REG(base))
41351 #define XCVR_WR_TSM_TIMING42(base, value) (XCVR_TSM_TIMING42_REG(base) = (value))
41352 #define XCVR_RMW_TSM_TIMING42(base, mask, value) (XCVR_WR_TSM_TIMING42(base, (XCVR_RD_TSM_TIMING42(base) & ~(mask)) | (value)))
41353 #define XCVR_SET_TSM_TIMING42(base, value) (BME_OR32(&XCVR_TSM_TIMING42_REG(base), (uint32_t)(value)))
41354 #define XCVR_CLR_TSM_TIMING42(base, value) (BME_AND32(&XCVR_TSM_TIMING42_REG(base), (uint32_t)(~(value))))
41355 #define XCVR_TOG_TSM_TIMING42(base, value) (BME_XOR32(&XCVR_TSM_TIMING42_REG(base), (uint32_t)(value)))
41356 /*@}*/
41357 
41358 /*
41359  * Constants & macros for individual XCVR_TSM_TIMING42 bitfields
41360  */
41361 
41362 /*!
41363  * @name Register XCVR_TSM_TIMING42, field GPIO2_TRIG_EN_TX_HI[7:0] (RW)
41364  *
41365  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
41366  * at which the GPIO2_TRIG_EN signal or group will transition from LO to HI.
41367  */
41368 /*@{*/
41369 /*! @brief Read current value of the XCVR_TSM_TIMING42_GPIO2_TRIG_EN_TX_HI field. */
41370 #define XCVR_RD_TSM_TIMING42_GPIO2_TRIG_EN_TX_HI(base) ((XCVR_TSM_TIMING42_REG(base) & XCVR_TSM_TIMING42_GPIO2_TRIG_EN_TX_HI_MASK) >> XCVR_TSM_TIMING42_GPIO2_TRIG_EN_TX_HI_SHIFT)
41371 #define XCVR_BRD_TSM_TIMING42_GPIO2_TRIG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING42_REG(base), XCVR_TSM_TIMING42_GPIO2_TRIG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING42_GPIO2_TRIG_EN_TX_HI_WIDTH))
41372 
41373 /*! @brief Set the GPIO2_TRIG_EN_TX_HI field to a new value. */
41374 #define XCVR_WR_TSM_TIMING42_GPIO2_TRIG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING42(base, XCVR_TSM_TIMING42_GPIO2_TRIG_EN_TX_HI_MASK, XCVR_TSM_TIMING42_GPIO2_TRIG_EN_TX_HI(value)))
41375 #define XCVR_BWR_TSM_TIMING42_GPIO2_TRIG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING42_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING42_GPIO2_TRIG_EN_TX_HI_SHIFT), XCVR_TSM_TIMING42_GPIO2_TRIG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING42_GPIO2_TRIG_EN_TX_HI_WIDTH))
41376 /*@}*/
41377 
41378 /*!
41379  * @name Register XCVR_TSM_TIMING42, field GPIO2_TRIG_EN_TX_LO[15:8] (RW)
41380  *
41381  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
41382  * at which the GPIO2_TRIG_EN signal or group will transition from HI to LO.
41383  */
41384 /*@{*/
41385 /*! @brief Read current value of the XCVR_TSM_TIMING42_GPIO2_TRIG_EN_TX_LO field. */
41386 #define XCVR_RD_TSM_TIMING42_GPIO2_TRIG_EN_TX_LO(base) ((XCVR_TSM_TIMING42_REG(base) & XCVR_TSM_TIMING42_GPIO2_TRIG_EN_TX_LO_MASK) >> XCVR_TSM_TIMING42_GPIO2_TRIG_EN_TX_LO_SHIFT)
41387 #define XCVR_BRD_TSM_TIMING42_GPIO2_TRIG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING42_REG(base), XCVR_TSM_TIMING42_GPIO2_TRIG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING42_GPIO2_TRIG_EN_TX_LO_WIDTH))
41388 
41389 /*! @brief Set the GPIO2_TRIG_EN_TX_LO field to a new value. */
41390 #define XCVR_WR_TSM_TIMING42_GPIO2_TRIG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING42(base, XCVR_TSM_TIMING42_GPIO2_TRIG_EN_TX_LO_MASK, XCVR_TSM_TIMING42_GPIO2_TRIG_EN_TX_LO(value)))
41391 #define XCVR_BWR_TSM_TIMING42_GPIO2_TRIG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING42_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING42_GPIO2_TRIG_EN_TX_LO_SHIFT), XCVR_TSM_TIMING42_GPIO2_TRIG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING42_GPIO2_TRIG_EN_TX_LO_WIDTH))
41392 /*@}*/
41393 
41394 /*!
41395  * @name Register XCVR_TSM_TIMING42, field GPIO2_TRIG_EN_RX_HI[23:16] (RW)
41396  *
41397  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
41398  * at which the GPIO2_TRIG_EN signal or group will transition from LO to HI.
41399  */
41400 /*@{*/
41401 /*! @brief Read current value of the XCVR_TSM_TIMING42_GPIO2_TRIG_EN_RX_HI field. */
41402 #define XCVR_RD_TSM_TIMING42_GPIO2_TRIG_EN_RX_HI(base) ((XCVR_TSM_TIMING42_REG(base) & XCVR_TSM_TIMING42_GPIO2_TRIG_EN_RX_HI_MASK) >> XCVR_TSM_TIMING42_GPIO2_TRIG_EN_RX_HI_SHIFT)
41403 #define XCVR_BRD_TSM_TIMING42_GPIO2_TRIG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING42_REG(base), XCVR_TSM_TIMING42_GPIO2_TRIG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING42_GPIO2_TRIG_EN_RX_HI_WIDTH))
41404 
41405 /*! @brief Set the GPIO2_TRIG_EN_RX_HI field to a new value. */
41406 #define XCVR_WR_TSM_TIMING42_GPIO2_TRIG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING42(base, XCVR_TSM_TIMING42_GPIO2_TRIG_EN_RX_HI_MASK, XCVR_TSM_TIMING42_GPIO2_TRIG_EN_RX_HI(value)))
41407 #define XCVR_BWR_TSM_TIMING42_GPIO2_TRIG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING42_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING42_GPIO2_TRIG_EN_RX_HI_SHIFT), XCVR_TSM_TIMING42_GPIO2_TRIG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING42_GPIO2_TRIG_EN_RX_HI_WIDTH))
41408 /*@}*/
41409 
41410 /*!
41411  * @name Register XCVR_TSM_TIMING42, field GPIO2_TRIG_EN_RX_LO[31:24] (RW)
41412  *
41413  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
41414  * at which the GPIO2_TRIG_EN signal or group will transition from HI to LO.
41415  */
41416 /*@{*/
41417 /*! @brief Read current value of the XCVR_TSM_TIMING42_GPIO2_TRIG_EN_RX_LO field. */
41418 #define XCVR_RD_TSM_TIMING42_GPIO2_TRIG_EN_RX_LO(base) ((XCVR_TSM_TIMING42_REG(base) & XCVR_TSM_TIMING42_GPIO2_TRIG_EN_RX_LO_MASK) >> XCVR_TSM_TIMING42_GPIO2_TRIG_EN_RX_LO_SHIFT)
41419 #define XCVR_BRD_TSM_TIMING42_GPIO2_TRIG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING42_REG(base), XCVR_TSM_TIMING42_GPIO2_TRIG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING42_GPIO2_TRIG_EN_RX_LO_WIDTH))
41420 
41421 /*! @brief Set the GPIO2_TRIG_EN_RX_LO field to a new value. */
41422 #define XCVR_WR_TSM_TIMING42_GPIO2_TRIG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING42(base, XCVR_TSM_TIMING42_GPIO2_TRIG_EN_RX_LO_MASK, XCVR_TSM_TIMING42_GPIO2_TRIG_EN_RX_LO(value)))
41423 #define XCVR_BWR_TSM_TIMING42_GPIO2_TRIG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING42_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING42_GPIO2_TRIG_EN_RX_LO_SHIFT), XCVR_TSM_TIMING42_GPIO2_TRIG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING42_GPIO2_TRIG_EN_RX_LO_WIDTH))
41424 /*@}*/
41425 
41426 /*******************************************************************************
41427  * XCVR_TSM_TIMING43 - TSM_TIMING43
41428  ******************************************************************************/
41429 
41430 /*!
41431  * @brief XCVR_TSM_TIMING43 - TSM_TIMING43 (RW)
41432  *
41433  * Reset value: 0xFFFFFFFFU
41434  *
41435  * This register contains the timing values to control the assertion and
41436  * deassertion times for both TX and RX sequences for the GPIO3_TRIG_EN TSM signal or
41437  * signal group.
41438  */
41439 /*!
41440  * @name Constants and macros for entire XCVR_TSM_TIMING43 register
41441  */
41442 /*@{*/
41443 #define XCVR_RD_TSM_TIMING43(base) (XCVR_TSM_TIMING43_REG(base))
41444 #define XCVR_WR_TSM_TIMING43(base, value) (XCVR_TSM_TIMING43_REG(base) = (value))
41445 #define XCVR_RMW_TSM_TIMING43(base, mask, value) (XCVR_WR_TSM_TIMING43(base, (XCVR_RD_TSM_TIMING43(base) & ~(mask)) | (value)))
41446 #define XCVR_SET_TSM_TIMING43(base, value) (BME_OR32(&XCVR_TSM_TIMING43_REG(base), (uint32_t)(value)))
41447 #define XCVR_CLR_TSM_TIMING43(base, value) (BME_AND32(&XCVR_TSM_TIMING43_REG(base), (uint32_t)(~(value))))
41448 #define XCVR_TOG_TSM_TIMING43(base, value) (BME_XOR32(&XCVR_TSM_TIMING43_REG(base), (uint32_t)(value)))
41449 /*@}*/
41450 
41451 /*
41452  * Constants & macros for individual XCVR_TSM_TIMING43 bitfields
41453  */
41454 
41455 /*!
41456  * @name Register XCVR_TSM_TIMING43, field GPIO3_TRIG_EN_TX_HI[7:0] (RW)
41457  *
41458  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
41459  * at which the GPIO3_TRIG_EN signal or group will transition from LO to HI.
41460  */
41461 /*@{*/
41462 /*! @brief Read current value of the XCVR_TSM_TIMING43_GPIO3_TRIG_EN_TX_HI field. */
41463 #define XCVR_RD_TSM_TIMING43_GPIO3_TRIG_EN_TX_HI(base) ((XCVR_TSM_TIMING43_REG(base) & XCVR_TSM_TIMING43_GPIO3_TRIG_EN_TX_HI_MASK) >> XCVR_TSM_TIMING43_GPIO3_TRIG_EN_TX_HI_SHIFT)
41464 #define XCVR_BRD_TSM_TIMING43_GPIO3_TRIG_EN_TX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING43_REG(base), XCVR_TSM_TIMING43_GPIO3_TRIG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING43_GPIO3_TRIG_EN_TX_HI_WIDTH))
41465 
41466 /*! @brief Set the GPIO3_TRIG_EN_TX_HI field to a new value. */
41467 #define XCVR_WR_TSM_TIMING43_GPIO3_TRIG_EN_TX_HI(base, value) (XCVR_RMW_TSM_TIMING43(base, XCVR_TSM_TIMING43_GPIO3_TRIG_EN_TX_HI_MASK, XCVR_TSM_TIMING43_GPIO3_TRIG_EN_TX_HI(value)))
41468 #define XCVR_BWR_TSM_TIMING43_GPIO3_TRIG_EN_TX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING43_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING43_GPIO3_TRIG_EN_TX_HI_SHIFT), XCVR_TSM_TIMING43_GPIO3_TRIG_EN_TX_HI_SHIFT, XCVR_TSM_TIMING43_GPIO3_TRIG_EN_TX_HI_WIDTH))
41469 /*@}*/
41470 
41471 /*!
41472  * @name Register XCVR_TSM_TIMING43, field GPIO3_TRIG_EN_TX_LO[15:8] (RW)
41473  *
41474  * This field sets the point during a TSM TX sequence (the tsm_count[7:0] value)
41475  * at which the GPIO3_TRIG_EN signal or group will transition from HI to LO.
41476  */
41477 /*@{*/
41478 /*! @brief Read current value of the XCVR_TSM_TIMING43_GPIO3_TRIG_EN_TX_LO field. */
41479 #define XCVR_RD_TSM_TIMING43_GPIO3_TRIG_EN_TX_LO(base) ((XCVR_TSM_TIMING43_REG(base) & XCVR_TSM_TIMING43_GPIO3_TRIG_EN_TX_LO_MASK) >> XCVR_TSM_TIMING43_GPIO3_TRIG_EN_TX_LO_SHIFT)
41480 #define XCVR_BRD_TSM_TIMING43_GPIO3_TRIG_EN_TX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING43_REG(base), XCVR_TSM_TIMING43_GPIO3_TRIG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING43_GPIO3_TRIG_EN_TX_LO_WIDTH))
41481 
41482 /*! @brief Set the GPIO3_TRIG_EN_TX_LO field to a new value. */
41483 #define XCVR_WR_TSM_TIMING43_GPIO3_TRIG_EN_TX_LO(base, value) (XCVR_RMW_TSM_TIMING43(base, XCVR_TSM_TIMING43_GPIO3_TRIG_EN_TX_LO_MASK, XCVR_TSM_TIMING43_GPIO3_TRIG_EN_TX_LO(value)))
41484 #define XCVR_BWR_TSM_TIMING43_GPIO3_TRIG_EN_TX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING43_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING43_GPIO3_TRIG_EN_TX_LO_SHIFT), XCVR_TSM_TIMING43_GPIO3_TRIG_EN_TX_LO_SHIFT, XCVR_TSM_TIMING43_GPIO3_TRIG_EN_TX_LO_WIDTH))
41485 /*@}*/
41486 
41487 /*!
41488  * @name Register XCVR_TSM_TIMING43, field GPIO3_TRIG_EN_RX_HI[23:16] (RW)
41489  *
41490  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
41491  * at which the GPIO3_TRIG_EN signal or group will transition from LO to HI.
41492  */
41493 /*@{*/
41494 /*! @brief Read current value of the XCVR_TSM_TIMING43_GPIO3_TRIG_EN_RX_HI field. */
41495 #define XCVR_RD_TSM_TIMING43_GPIO3_TRIG_EN_RX_HI(base) ((XCVR_TSM_TIMING43_REG(base) & XCVR_TSM_TIMING43_GPIO3_TRIG_EN_RX_HI_MASK) >> XCVR_TSM_TIMING43_GPIO3_TRIG_EN_RX_HI_SHIFT)
41496 #define XCVR_BRD_TSM_TIMING43_GPIO3_TRIG_EN_RX_HI(base) (BME_UBFX32(&XCVR_TSM_TIMING43_REG(base), XCVR_TSM_TIMING43_GPIO3_TRIG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING43_GPIO3_TRIG_EN_RX_HI_WIDTH))
41497 
41498 /*! @brief Set the GPIO3_TRIG_EN_RX_HI field to a new value. */
41499 #define XCVR_WR_TSM_TIMING43_GPIO3_TRIG_EN_RX_HI(base, value) (XCVR_RMW_TSM_TIMING43(base, XCVR_TSM_TIMING43_GPIO3_TRIG_EN_RX_HI_MASK, XCVR_TSM_TIMING43_GPIO3_TRIG_EN_RX_HI(value)))
41500 #define XCVR_BWR_TSM_TIMING43_GPIO3_TRIG_EN_RX_HI(base, value) (BME_BFI32(&XCVR_TSM_TIMING43_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING43_GPIO3_TRIG_EN_RX_HI_SHIFT), XCVR_TSM_TIMING43_GPIO3_TRIG_EN_RX_HI_SHIFT, XCVR_TSM_TIMING43_GPIO3_TRIG_EN_RX_HI_WIDTH))
41501 /*@}*/
41502 
41503 /*!
41504  * @name Register XCVR_TSM_TIMING43, field GPIO3_TRIG_EN_RX_LO[31:24] (RW)
41505  *
41506  * This field sets the point during a TSM RX sequence (the tsm_count[7:0] value)
41507  * at which the GPIO3_TRIG_EN signal or group will transition from HI to LO.
41508  */
41509 /*@{*/
41510 /*! @brief Read current value of the XCVR_TSM_TIMING43_GPIO3_TRIG_EN_RX_LO field. */
41511 #define XCVR_RD_TSM_TIMING43_GPIO3_TRIG_EN_RX_LO(base) ((XCVR_TSM_TIMING43_REG(base) & XCVR_TSM_TIMING43_GPIO3_TRIG_EN_RX_LO_MASK) >> XCVR_TSM_TIMING43_GPIO3_TRIG_EN_RX_LO_SHIFT)
41512 #define XCVR_BRD_TSM_TIMING43_GPIO3_TRIG_EN_RX_LO(base) (BME_UBFX32(&XCVR_TSM_TIMING43_REG(base), XCVR_TSM_TIMING43_GPIO3_TRIG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING43_GPIO3_TRIG_EN_RX_LO_WIDTH))
41513 
41514 /*! @brief Set the GPIO3_TRIG_EN_RX_LO field to a new value. */
41515 #define XCVR_WR_TSM_TIMING43_GPIO3_TRIG_EN_RX_LO(base, value) (XCVR_RMW_TSM_TIMING43(base, XCVR_TSM_TIMING43_GPIO3_TRIG_EN_RX_LO_MASK, XCVR_TSM_TIMING43_GPIO3_TRIG_EN_RX_LO(value)))
41516 #define XCVR_BWR_TSM_TIMING43_GPIO3_TRIG_EN_RX_LO(base, value) (BME_BFI32(&XCVR_TSM_TIMING43_REG(base), ((uint32_t)(value) << XCVR_TSM_TIMING43_GPIO3_TRIG_EN_RX_LO_SHIFT), XCVR_TSM_TIMING43_GPIO3_TRIG_EN_RX_LO_SHIFT, XCVR_TSM_TIMING43_GPIO3_TRIG_EN_RX_LO_WIDTH))
41517 /*@}*/
41518 
41519 /*******************************************************************************
41520  * XCVR_CORR_CTRL - CORR_CTRL
41521  ******************************************************************************/
41522 
41523 /*!
41524  * @brief XCVR_CORR_CTRL - CORR_CTRL (RW)
41525  *
41526  * Reset value: 0x00000482U
41527  */
41528 /*!
41529  * @name Constants and macros for entire XCVR_CORR_CTRL register
41530  */
41531 /*@{*/
41532 #define XCVR_RD_CORR_CTRL(base)  (XCVR_CORR_CTRL_REG(base))
41533 #define XCVR_WR_CORR_CTRL(base, value) (XCVR_CORR_CTRL_REG(base) = (value))
41534 #define XCVR_RMW_CORR_CTRL(base, mask, value) (XCVR_WR_CORR_CTRL(base, (XCVR_RD_CORR_CTRL(base) & ~(mask)) | (value)))
41535 #define XCVR_SET_CORR_CTRL(base, value) (BME_OR32(&XCVR_CORR_CTRL_REG(base), (uint32_t)(value)))
41536 #define XCVR_CLR_CORR_CTRL(base, value) (BME_AND32(&XCVR_CORR_CTRL_REG(base), (uint32_t)(~(value))))
41537 #define XCVR_TOG_CORR_CTRL(base, value) (BME_XOR32(&XCVR_CORR_CTRL_REG(base), (uint32_t)(value)))
41538 /*@}*/
41539 
41540 /*
41541  * Constants & macros for individual XCVR_CORR_CTRL bitfields
41542  */
41543 
41544 /*!
41545  * @name Register XCVR_CORR_CTRL, field CORR_VT[7:0] (RW)
41546  *
41547  * Correlator threshold, defines the sensitivity of demod during the preamble
41548  * search state
41549  */
41550 /*@{*/
41551 /*! @brief Read current value of the XCVR_CORR_CTRL_CORR_VT field. */
41552 #define XCVR_RD_CORR_CTRL_CORR_VT(base) ((XCVR_CORR_CTRL_REG(base) & XCVR_CORR_CTRL_CORR_VT_MASK) >> XCVR_CORR_CTRL_CORR_VT_SHIFT)
41553 #define XCVR_BRD_CORR_CTRL_CORR_VT(base) (BME_UBFX32(&XCVR_CORR_CTRL_REG(base), XCVR_CORR_CTRL_CORR_VT_SHIFT, XCVR_CORR_CTRL_CORR_VT_WIDTH))
41554 
41555 /*! @brief Set the CORR_VT field to a new value. */
41556 #define XCVR_WR_CORR_CTRL_CORR_VT(base, value) (XCVR_RMW_CORR_CTRL(base, XCVR_CORR_CTRL_CORR_VT_MASK, XCVR_CORR_CTRL_CORR_VT(value)))
41557 #define XCVR_BWR_CORR_CTRL_CORR_VT(base, value) (BME_BFI32(&XCVR_CORR_CTRL_REG(base), ((uint32_t)(value) << XCVR_CORR_CTRL_CORR_VT_SHIFT), XCVR_CORR_CTRL_CORR_VT_SHIFT, XCVR_CORR_CTRL_CORR_VT_WIDTH))
41558 /*@}*/
41559 
41560 /*!
41561  * @name Register XCVR_CORR_CTRL, field CORR_NVAL[10:8] (RW)
41562  *
41563  * Number of consecutively detected zero-symbols required to declare a preamble
41564  * detected
41565  */
41566 /*@{*/
41567 /*! @brief Read current value of the XCVR_CORR_CTRL_CORR_NVAL field. */
41568 #define XCVR_RD_CORR_CTRL_CORR_NVAL(base) ((XCVR_CORR_CTRL_REG(base) & XCVR_CORR_CTRL_CORR_NVAL_MASK) >> XCVR_CORR_CTRL_CORR_NVAL_SHIFT)
41569 #define XCVR_BRD_CORR_CTRL_CORR_NVAL(base) (BME_UBFX32(&XCVR_CORR_CTRL_REG(base), XCVR_CORR_CTRL_CORR_NVAL_SHIFT, XCVR_CORR_CTRL_CORR_NVAL_WIDTH))
41570 
41571 /*! @brief Set the CORR_NVAL field to a new value. */
41572 #define XCVR_WR_CORR_CTRL_CORR_NVAL(base, value) (XCVR_RMW_CORR_CTRL(base, XCVR_CORR_CTRL_CORR_NVAL_MASK, XCVR_CORR_CTRL_CORR_NVAL(value)))
41573 #define XCVR_BWR_CORR_CTRL_CORR_NVAL(base, value) (BME_BFI32(&XCVR_CORR_CTRL_REG(base), ((uint32_t)(value) << XCVR_CORR_CTRL_CORR_NVAL_SHIFT), XCVR_CORR_CTRL_CORR_NVAL_SHIFT, XCVR_CORR_CTRL_CORR_NVAL_WIDTH))
41574 /*@}*/
41575 
41576 /*!
41577  * @name Register XCVR_CORR_CTRL, field MAX_CORR_EN[11] (RW)
41578  *
41579  * Max correlator after preamble enable-- Enable the refresh of the max corr
41580  * register
41581  */
41582 /*@{*/
41583 /*! @brief Read current value of the XCVR_CORR_CTRL_MAX_CORR_EN field. */
41584 #define XCVR_RD_CORR_CTRL_MAX_CORR_EN(base) ((XCVR_CORR_CTRL_REG(base) & XCVR_CORR_CTRL_MAX_CORR_EN_MASK) >> XCVR_CORR_CTRL_MAX_CORR_EN_SHIFT)
41585 #define XCVR_BRD_CORR_CTRL_MAX_CORR_EN(base) (BME_UBFX32(&XCVR_CORR_CTRL_REG(base), XCVR_CORR_CTRL_MAX_CORR_EN_SHIFT, XCVR_CORR_CTRL_MAX_CORR_EN_WIDTH))
41586 
41587 /*! @brief Set the MAX_CORR_EN field to a new value. */
41588 #define XCVR_WR_CORR_CTRL_MAX_CORR_EN(base, value) (XCVR_RMW_CORR_CTRL(base, XCVR_CORR_CTRL_MAX_CORR_EN_MASK, XCVR_CORR_CTRL_MAX_CORR_EN(value)))
41589 #define XCVR_BWR_CORR_CTRL_MAX_CORR_EN(base, value) (BME_BFI32(&XCVR_CORR_CTRL_REG(base), ((uint32_t)(value) << XCVR_CORR_CTRL_MAX_CORR_EN_SHIFT), XCVR_CORR_CTRL_MAX_CORR_EN_SHIFT, XCVR_CORR_CTRL_MAX_CORR_EN_WIDTH))
41590 /*@}*/
41591 
41592 /*!
41593  * @name Register XCVR_CORR_CTRL, field RX_MAX_CORR[23:16] (RO)
41594  *
41595  * Max correlator after preamble-- max correlator value found in packet after
41596  * the preamble (refreshed every symbol rate if MAX_CORR_EN=1).
41597  */
41598 /*@{*/
41599 /*! @brief Read current value of the XCVR_CORR_CTRL_RX_MAX_CORR field. */
41600 #define XCVR_RD_CORR_CTRL_RX_MAX_CORR(base) ((XCVR_CORR_CTRL_REG(base) & XCVR_CORR_CTRL_RX_MAX_CORR_MASK) >> XCVR_CORR_CTRL_RX_MAX_CORR_SHIFT)
41601 #define XCVR_BRD_CORR_CTRL_RX_MAX_CORR(base) (BME_UBFX32(&XCVR_CORR_CTRL_REG(base), XCVR_CORR_CTRL_RX_MAX_CORR_SHIFT, XCVR_CORR_CTRL_RX_MAX_CORR_WIDTH))
41602 /*@}*/
41603 
41604 /*!
41605  * @name Register XCVR_CORR_CTRL, field RX_MAX_PREAMBLE[31:24] (RO)
41606  *
41607  * Max correlator during preamble-- max correlator value found during the
41608  * preamble.
41609  */
41610 /*@{*/
41611 /*! @brief Read current value of the XCVR_CORR_CTRL_RX_MAX_PREAMBLE field. */
41612 #define XCVR_RD_CORR_CTRL_RX_MAX_PREAMBLE(base) ((XCVR_CORR_CTRL_REG(base) & XCVR_CORR_CTRL_RX_MAX_PREAMBLE_MASK) >> XCVR_CORR_CTRL_RX_MAX_PREAMBLE_SHIFT)
41613 #define XCVR_BRD_CORR_CTRL_RX_MAX_PREAMBLE(base) (BME_UBFX32(&XCVR_CORR_CTRL_REG(base), XCVR_CORR_CTRL_RX_MAX_PREAMBLE_SHIFT, XCVR_CORR_CTRL_RX_MAX_PREAMBLE_WIDTH))
41614 /*@}*/
41615 
41616 /*******************************************************************************
41617  * XCVR_PN_TYPE - PN_TYPE
41618  ******************************************************************************/
41619 
41620 /*!
41621  * @brief XCVR_PN_TYPE - PN_TYPE (RW)
41622  *
41623  * Reset value: 0x00000001U
41624  */
41625 /*!
41626  * @name Constants and macros for entire XCVR_PN_TYPE register
41627  */
41628 /*@{*/
41629 #define XCVR_RD_PN_TYPE(base)    (XCVR_PN_TYPE_REG(base))
41630 #define XCVR_WR_PN_TYPE(base, value) (XCVR_PN_TYPE_REG(base) = (value))
41631 #define XCVR_RMW_PN_TYPE(base, mask, value) (XCVR_WR_PN_TYPE(base, (XCVR_RD_PN_TYPE(base) & ~(mask)) | (value)))
41632 #define XCVR_SET_PN_TYPE(base, value) (BME_OR32(&XCVR_PN_TYPE_REG(base), (uint32_t)(value)))
41633 #define XCVR_CLR_PN_TYPE(base, value) (BME_AND32(&XCVR_PN_TYPE_REG(base), (uint32_t)(~(value))))
41634 #define XCVR_TOG_PN_TYPE(base, value) (BME_XOR32(&XCVR_PN_TYPE_REG(base), (uint32_t)(value)))
41635 /*@}*/
41636 
41637 /*
41638  * Constants & macros for individual XCVR_PN_TYPE bitfields
41639  */
41640 
41641 /*!
41642  * @name Register XCVR_PN_TYPE, field PN_TYPE[0] (RW)
41643  *
41644  * PN Type - Pseudo Noise Chip Code Type (ZigBee=1)
41645  */
41646 /*@{*/
41647 /*! @brief Read current value of the XCVR_PN_TYPE_PN_TYPE field. */
41648 #define XCVR_RD_PN_TYPE_PN_TYPE(base) ((XCVR_PN_TYPE_REG(base) & XCVR_PN_TYPE_PN_TYPE_MASK) >> XCVR_PN_TYPE_PN_TYPE_SHIFT)
41649 #define XCVR_BRD_PN_TYPE_PN_TYPE(base) (BME_UBFX32(&XCVR_PN_TYPE_REG(base), XCVR_PN_TYPE_PN_TYPE_SHIFT, XCVR_PN_TYPE_PN_TYPE_WIDTH))
41650 
41651 /*! @brief Set the PN_TYPE field to a new value. */
41652 #define XCVR_WR_PN_TYPE_PN_TYPE(base, value) (XCVR_RMW_PN_TYPE(base, XCVR_PN_TYPE_PN_TYPE_MASK, XCVR_PN_TYPE_PN_TYPE(value)))
41653 #define XCVR_BWR_PN_TYPE_PN_TYPE(base, value) (BME_BFI32(&XCVR_PN_TYPE_REG(base), ((uint32_t)(value) << XCVR_PN_TYPE_PN_TYPE_SHIFT), XCVR_PN_TYPE_PN_TYPE_SHIFT, XCVR_PN_TYPE_PN_TYPE_WIDTH))
41654 /*@}*/
41655 
41656 /*!
41657  * @name Register XCVR_PN_TYPE, field TX_INV[1] (RW)
41658  *
41659  * test mode to invert the transmission
41660  */
41661 /*@{*/
41662 /*! @brief Read current value of the XCVR_PN_TYPE_TX_INV field. */
41663 #define XCVR_RD_PN_TYPE_TX_INV(base) ((XCVR_PN_TYPE_REG(base) & XCVR_PN_TYPE_TX_INV_MASK) >> XCVR_PN_TYPE_TX_INV_SHIFT)
41664 #define XCVR_BRD_PN_TYPE_TX_INV(base) (BME_UBFX32(&XCVR_PN_TYPE_REG(base), XCVR_PN_TYPE_TX_INV_SHIFT, XCVR_PN_TYPE_TX_INV_WIDTH))
41665 
41666 /*! @brief Set the TX_INV field to a new value. */
41667 #define XCVR_WR_PN_TYPE_TX_INV(base, value) (XCVR_RMW_PN_TYPE(base, XCVR_PN_TYPE_TX_INV_MASK, XCVR_PN_TYPE_TX_INV(value)))
41668 #define XCVR_BWR_PN_TYPE_TX_INV(base, value) (BME_BFI32(&XCVR_PN_TYPE_REG(base), ((uint32_t)(value) << XCVR_PN_TYPE_TX_INV_SHIFT), XCVR_PN_TYPE_TX_INV_SHIFT, XCVR_PN_TYPE_TX_INV_WIDTH))
41669 /*@}*/
41670 
41671 /*******************************************************************************
41672  * XCVR_PN_CODE - PN_CODE
41673  ******************************************************************************/
41674 
41675 /*!
41676  * @brief XCVR_PN_CODE - PN_CODE (RW)
41677  *
41678  * Reset value: 0x744AC39BU
41679  *
41680  * Pseudo Noise Chip Code Seed Value
41681  */
41682 /*!
41683  * @name Constants and macros for entire XCVR_PN_CODE register
41684  */
41685 /*@{*/
41686 #define XCVR_RD_PN_CODE(base)    (XCVR_PN_CODE_REG(base))
41687 #define XCVR_WR_PN_CODE(base, value) (XCVR_PN_CODE_REG(base) = (value))
41688 #define XCVR_RMW_PN_CODE(base, mask, value) (XCVR_WR_PN_CODE(base, (XCVR_RD_PN_CODE(base) & ~(mask)) | (value)))
41689 #define XCVR_SET_PN_CODE(base, value) (BME_OR32(&XCVR_PN_CODE_REG(base), (uint32_t)(value)))
41690 #define XCVR_CLR_PN_CODE(base, value) (BME_AND32(&XCVR_PN_CODE_REG(base), (uint32_t)(~(value))))
41691 #define XCVR_TOG_PN_CODE(base, value) (BME_XOR32(&XCVR_PN_CODE_REG(base), (uint32_t)(value)))
41692 /*@}*/
41693 
41694 /*
41695  * Constants & macros for individual XCVR_PN_CODE bitfields
41696  */
41697 
41698 /*!
41699  * @name Register XCVR_PN_CODE, field PN_LSB[15:0] (RW)
41700  *
41701  * PN_CODE LS half
41702  */
41703 /*@{*/
41704 /*! @brief Read current value of the XCVR_PN_CODE_PN_LSB field. */
41705 #define XCVR_RD_PN_CODE_PN_LSB(base) ((XCVR_PN_CODE_REG(base) & XCVR_PN_CODE_PN_LSB_MASK) >> XCVR_PN_CODE_PN_LSB_SHIFT)
41706 #define XCVR_BRD_PN_CODE_PN_LSB(base) (BME_UBFX32(&XCVR_PN_CODE_REG(base), XCVR_PN_CODE_PN_LSB_SHIFT, XCVR_PN_CODE_PN_LSB_WIDTH))
41707 
41708 /*! @brief Set the PN_LSB field to a new value. */
41709 #define XCVR_WR_PN_CODE_PN_LSB(base, value) (XCVR_RMW_PN_CODE(base, XCVR_PN_CODE_PN_LSB_MASK, XCVR_PN_CODE_PN_LSB(value)))
41710 #define XCVR_BWR_PN_CODE_PN_LSB(base, value) (BME_BFI32(&XCVR_PN_CODE_REG(base), ((uint32_t)(value) << XCVR_PN_CODE_PN_LSB_SHIFT), XCVR_PN_CODE_PN_LSB_SHIFT, XCVR_PN_CODE_PN_LSB_WIDTH))
41711 /*@}*/
41712 
41713 /*!
41714  * @name Register XCVR_PN_CODE, field PN_MSB[31:16] (RW)
41715  *
41716  * PN_CODE MS half
41717  */
41718 /*@{*/
41719 /*! @brief Read current value of the XCVR_PN_CODE_PN_MSB field. */
41720 #define XCVR_RD_PN_CODE_PN_MSB(base) ((XCVR_PN_CODE_REG(base) & XCVR_PN_CODE_PN_MSB_MASK) >> XCVR_PN_CODE_PN_MSB_SHIFT)
41721 #define XCVR_BRD_PN_CODE_PN_MSB(base) (BME_UBFX32(&XCVR_PN_CODE_REG(base), XCVR_PN_CODE_PN_MSB_SHIFT, XCVR_PN_CODE_PN_MSB_WIDTH))
41722 
41723 /*! @brief Set the PN_MSB field to a new value. */
41724 #define XCVR_WR_PN_CODE_PN_MSB(base, value) (XCVR_RMW_PN_CODE(base, XCVR_PN_CODE_PN_MSB_MASK, XCVR_PN_CODE_PN_MSB(value)))
41725 #define XCVR_BWR_PN_CODE_PN_MSB(base, value) (BME_BFI32(&XCVR_PN_CODE_REG(base), ((uint32_t)(value) << XCVR_PN_CODE_PN_MSB_SHIFT), XCVR_PN_CODE_PN_MSB_SHIFT, XCVR_PN_CODE_PN_MSB_WIDTH))
41726 /*@}*/
41727 
41728 /*******************************************************************************
41729  * XCVR_SYNC_CTRL - Sync Control
41730  ******************************************************************************/
41731 
41732 /*!
41733  * @brief XCVR_SYNC_CTRL - Sync Control (RW)
41734  *
41735  * Reset value: 0x00000008U
41736  */
41737 /*!
41738  * @name Constants and macros for entire XCVR_SYNC_CTRL register
41739  */
41740 /*@{*/
41741 #define XCVR_RD_SYNC_CTRL(base)  (XCVR_SYNC_CTRL_REG(base))
41742 #define XCVR_WR_SYNC_CTRL(base, value) (XCVR_SYNC_CTRL_REG(base) = (value))
41743 #define XCVR_RMW_SYNC_CTRL(base, mask, value) (XCVR_WR_SYNC_CTRL(base, (XCVR_RD_SYNC_CTRL(base) & ~(mask)) | (value)))
41744 #define XCVR_SET_SYNC_CTRL(base, value) (BME_OR32(&XCVR_SYNC_CTRL_REG(base), (uint32_t)(value)))
41745 #define XCVR_CLR_SYNC_CTRL(base, value) (BME_AND32(&XCVR_SYNC_CTRL_REG(base), (uint32_t)(~(value))))
41746 #define XCVR_TOG_SYNC_CTRL(base, value) (BME_XOR32(&XCVR_SYNC_CTRL_REG(base), (uint32_t)(value)))
41747 /*@}*/
41748 
41749 /*
41750  * Constants & macros for individual XCVR_SYNC_CTRL bitfields
41751  */
41752 
41753 /*!
41754  * @name Register XCVR_SYNC_CTRL, field SYNC_PER[2:0] (RW)
41755  *
41756  * determines update rate for symbol timing, per equation. An early/late
41757  * measurement is made every 2^SYNC_PER[2:0] symbols. Valid range of SYNC_PER[2:0] is 0
41758  * to 4.
41759  */
41760 /*@{*/
41761 /*! @brief Read current value of the XCVR_SYNC_CTRL_SYNC_PER field. */
41762 #define XCVR_RD_SYNC_CTRL_SYNC_PER(base) ((XCVR_SYNC_CTRL_REG(base) & XCVR_SYNC_CTRL_SYNC_PER_MASK) >> XCVR_SYNC_CTRL_SYNC_PER_SHIFT)
41763 #define XCVR_BRD_SYNC_CTRL_SYNC_PER(base) (BME_UBFX32(&XCVR_SYNC_CTRL_REG(base), XCVR_SYNC_CTRL_SYNC_PER_SHIFT, XCVR_SYNC_CTRL_SYNC_PER_WIDTH))
41764 
41765 /*! @brief Set the SYNC_PER field to a new value. */
41766 #define XCVR_WR_SYNC_CTRL_SYNC_PER(base, value) (XCVR_RMW_SYNC_CTRL(base, XCVR_SYNC_CTRL_SYNC_PER_MASK, XCVR_SYNC_CTRL_SYNC_PER(value)))
41767 #define XCVR_BWR_SYNC_CTRL_SYNC_PER(base, value) (BME_BFI32(&XCVR_SYNC_CTRL_REG(base), ((uint32_t)(value) << XCVR_SYNC_CTRL_SYNC_PER_SHIFT), XCVR_SYNC_CTRL_SYNC_PER_SHIFT, XCVR_SYNC_CTRL_SYNC_PER_WIDTH))
41768 /*@}*/
41769 
41770 /*!
41771  * @name Register XCVR_SYNC_CTRL, field TRACK_ENABLE[3] (RW)
41772  *
41773  * Values:
41774  * - 0b0 - symbol timing synchronization tracking disabled in Rx frontend
41775  * - 0b1 - symbol timing synchronization tracking enabled in Rx frontend
41776  *     (default)
41777  */
41778 /*@{*/
41779 /*! @brief Read current value of the XCVR_SYNC_CTRL_TRACK_ENABLE field. */
41780 #define XCVR_RD_SYNC_CTRL_TRACK_ENABLE(base) ((XCVR_SYNC_CTRL_REG(base) & XCVR_SYNC_CTRL_TRACK_ENABLE_MASK) >> XCVR_SYNC_CTRL_TRACK_ENABLE_SHIFT)
41781 #define XCVR_BRD_SYNC_CTRL_TRACK_ENABLE(base) (BME_UBFX32(&XCVR_SYNC_CTRL_REG(base), XCVR_SYNC_CTRL_TRACK_ENABLE_SHIFT, XCVR_SYNC_CTRL_TRACK_ENABLE_WIDTH))
41782 
41783 /*! @brief Set the TRACK_ENABLE field to a new value. */
41784 #define XCVR_WR_SYNC_CTRL_TRACK_ENABLE(base, value) (XCVR_RMW_SYNC_CTRL(base, XCVR_SYNC_CTRL_TRACK_ENABLE_MASK, XCVR_SYNC_CTRL_TRACK_ENABLE(value)))
41785 #define XCVR_BWR_SYNC_CTRL_TRACK_ENABLE(base, value) (BME_BFI32(&XCVR_SYNC_CTRL_REG(base), ((uint32_t)(value) << XCVR_SYNC_CTRL_TRACK_ENABLE_SHIFT), XCVR_SYNC_CTRL_TRACK_ENABLE_SHIFT, XCVR_SYNC_CTRL_TRACK_ENABLE_WIDTH))
41786 /*@}*/
41787 
41788 /*******************************************************************************
41789  * XCVR_SNF_THR - SNF_THR
41790  ******************************************************************************/
41791 
41792 /*!
41793  * @brief XCVR_SNF_THR - SNF_THR (RW)
41794  *
41795  * Reset value: 0x00000000U
41796  */
41797 /*!
41798  * @name Constants and macros for entire XCVR_SNF_THR register
41799  */
41800 /*@{*/
41801 #define XCVR_RD_SNF_THR(base)    (XCVR_SNF_THR_REG(base))
41802 #define XCVR_WR_SNF_THR(base, value) (XCVR_SNF_THR_REG(base) = (value))
41803 #define XCVR_RMW_SNF_THR(base, mask, value) (XCVR_WR_SNF_THR(base, (XCVR_RD_SNF_THR(base) & ~(mask)) | (value)))
41804 #define XCVR_SET_SNF_THR(base, value) (BME_OR32(&XCVR_SNF_THR_REG(base), (uint32_t)(value)))
41805 #define XCVR_CLR_SNF_THR(base, value) (BME_AND32(&XCVR_SNF_THR_REG(base), (uint32_t)(~(value))))
41806 #define XCVR_TOG_SNF_THR(base, value) (BME_XOR32(&XCVR_SNF_THR_REG(base), (uint32_t)(value)))
41807 /*@}*/
41808 
41809 /*
41810  * Constants & macros for individual XCVR_SNF_THR bitfields
41811  */
41812 
41813 /*!
41814  * @name Register XCVR_SNF_THR, field SNF_THR[7:0] (RW)
41815  *
41816  * RSSI level at which the symbol demodulator will be started when
41817  * SNF_CTRL[SNF_EN]=1. The control bit SNF_CTRL[SNF_EN] is in Zigbee address space. Note:
41818  * SNIFF Mode not currently supported. SNF_THR has no effect
41819  */
41820 /*@{*/
41821 /*! @brief Read current value of the XCVR_SNF_THR_SNF_THR field. */
41822 #define XCVR_RD_SNF_THR_SNF_THR(base) ((XCVR_SNF_THR_REG(base) & XCVR_SNF_THR_SNF_THR_MASK) >> XCVR_SNF_THR_SNF_THR_SHIFT)
41823 #define XCVR_BRD_SNF_THR_SNF_THR(base) (BME_UBFX32(&XCVR_SNF_THR_REG(base), XCVR_SNF_THR_SNF_THR_SHIFT, XCVR_SNF_THR_SNF_THR_WIDTH))
41824 
41825 /*! @brief Set the SNF_THR field to a new value. */
41826 #define XCVR_WR_SNF_THR_SNF_THR(base, value) (XCVR_RMW_SNF_THR(base, XCVR_SNF_THR_SNF_THR_MASK, XCVR_SNF_THR_SNF_THR(value)))
41827 #define XCVR_BWR_SNF_THR_SNF_THR(base, value) (BME_BFI32(&XCVR_SNF_THR_REG(base), ((uint32_t)(value) << XCVR_SNF_THR_SNF_THR_SHIFT), XCVR_SNF_THR_SNF_THR_SHIFT, XCVR_SNF_THR_SNF_THR_WIDTH))
41828 /*@}*/
41829 
41830 /*******************************************************************************
41831  * XCVR_FAD_THR - FAD_THR
41832  ******************************************************************************/
41833 
41834 /*!
41835  * @brief XCVR_FAD_THR - FAD_THR (RW)
41836  *
41837  * Reset value: 0x00000082U
41838  */
41839 /*!
41840  * @name Constants and macros for entire XCVR_FAD_THR register
41841  */
41842 /*@{*/
41843 #define XCVR_RD_FAD_THR(base)    (XCVR_FAD_THR_REG(base))
41844 #define XCVR_WR_FAD_THR(base, value) (XCVR_FAD_THR_REG(base) = (value))
41845 #define XCVR_RMW_FAD_THR(base, mask, value) (XCVR_WR_FAD_THR(base, (XCVR_RD_FAD_THR(base) & ~(mask)) | (value)))
41846 #define XCVR_SET_FAD_THR(base, value) (BME_OR32(&XCVR_FAD_THR_REG(base), (uint32_t)(value)))
41847 #define XCVR_CLR_FAD_THR(base, value) (BME_AND32(&XCVR_FAD_THR_REG(base), (uint32_t)(~(value))))
41848 #define XCVR_TOG_FAD_THR(base, value) (BME_XOR32(&XCVR_FAD_THR_REG(base), (uint32_t)(value)))
41849 /*@}*/
41850 
41851 /*
41852  * Constants & macros for individual XCVR_FAD_THR bitfields
41853  */
41854 
41855 /*!
41856  * @name Register XCVR_FAD_THR, field FAD_THR[7:0] (RW)
41857  *
41858  * Correlator threshold at which the FAD will select the antenna.
41859  */
41860 /*@{*/
41861 /*! @brief Read current value of the XCVR_FAD_THR_FAD_THR field. */
41862 #define XCVR_RD_FAD_THR_FAD_THR(base) ((XCVR_FAD_THR_REG(base) & XCVR_FAD_THR_FAD_THR_MASK) >> XCVR_FAD_THR_FAD_THR_SHIFT)
41863 #define XCVR_BRD_FAD_THR_FAD_THR(base) (BME_UBFX32(&XCVR_FAD_THR_REG(base), XCVR_FAD_THR_FAD_THR_SHIFT, XCVR_FAD_THR_FAD_THR_WIDTH))
41864 
41865 /*! @brief Set the FAD_THR field to a new value. */
41866 #define XCVR_WR_FAD_THR_FAD_THR(base, value) (XCVR_RMW_FAD_THR(base, XCVR_FAD_THR_FAD_THR_MASK, XCVR_FAD_THR_FAD_THR(value)))
41867 #define XCVR_BWR_FAD_THR_FAD_THR(base, value) (BME_BFI32(&XCVR_FAD_THR_REG(base), ((uint32_t)(value) << XCVR_FAD_THR_FAD_THR_SHIFT), XCVR_FAD_THR_FAD_THR_SHIFT, XCVR_FAD_THR_FAD_THR_WIDTH))
41868 /*@}*/
41869 
41870 /*******************************************************************************
41871  * XCVR_ZBDEM_AFC - ZBDEM_AFC
41872  ******************************************************************************/
41873 
41874 /*!
41875  * @brief XCVR_ZBDEM_AFC - ZBDEM_AFC (RW)
41876  *
41877  * Reset value: 0x00000001U
41878  */
41879 /*!
41880  * @name Constants and macros for entire XCVR_ZBDEM_AFC register
41881  */
41882 /*@{*/
41883 #define XCVR_RD_ZBDEM_AFC(base)  (XCVR_ZBDEM_AFC_REG(base))
41884 #define XCVR_WR_ZBDEM_AFC(base, value) (XCVR_ZBDEM_AFC_REG(base) = (value))
41885 #define XCVR_RMW_ZBDEM_AFC(base, mask, value) (XCVR_WR_ZBDEM_AFC(base, (XCVR_RD_ZBDEM_AFC(base) & ~(mask)) | (value)))
41886 #define XCVR_SET_ZBDEM_AFC(base, value) (BME_OR32(&XCVR_ZBDEM_AFC_REG(base), (uint32_t)(value)))
41887 #define XCVR_CLR_ZBDEM_AFC(base, value) (BME_AND32(&XCVR_ZBDEM_AFC_REG(base), (uint32_t)(~(value))))
41888 #define XCVR_TOG_ZBDEM_AFC(base, value) (BME_XOR32(&XCVR_ZBDEM_AFC_REG(base), (uint32_t)(value)))
41889 /*@}*/
41890 
41891 /*
41892  * Constants & macros for individual XCVR_ZBDEM_AFC bitfields
41893  */
41894 
41895 /*!
41896  * @name Register XCVR_ZBDEM_AFC, field AFC_EN[0] (RW)
41897  *
41898  * Enable the AFC Function
41899  */
41900 /*@{*/
41901 /*! @brief Read current value of the XCVR_ZBDEM_AFC_AFC_EN field. */
41902 #define XCVR_RD_ZBDEM_AFC_AFC_EN(base) ((XCVR_ZBDEM_AFC_REG(base) & XCVR_ZBDEM_AFC_AFC_EN_MASK) >> XCVR_ZBDEM_AFC_AFC_EN_SHIFT)
41903 #define XCVR_BRD_ZBDEM_AFC_AFC_EN(base) (BME_UBFX32(&XCVR_ZBDEM_AFC_REG(base), XCVR_ZBDEM_AFC_AFC_EN_SHIFT, XCVR_ZBDEM_AFC_AFC_EN_WIDTH))
41904 
41905 /*! @brief Set the AFC_EN field to a new value. */
41906 #define XCVR_WR_ZBDEM_AFC_AFC_EN(base, value) (XCVR_RMW_ZBDEM_AFC(base, XCVR_ZBDEM_AFC_AFC_EN_MASK, XCVR_ZBDEM_AFC_AFC_EN(value)))
41907 #define XCVR_BWR_ZBDEM_AFC_AFC_EN(base, value) (BME_BFI32(&XCVR_ZBDEM_AFC_REG(base), ((uint32_t)(value) << XCVR_ZBDEM_AFC_AFC_EN_SHIFT), XCVR_ZBDEM_AFC_AFC_EN_SHIFT, XCVR_ZBDEM_AFC_AFC_EN_WIDTH))
41908 /*@}*/
41909 
41910 /*!
41911  * @name Register XCVR_ZBDEM_AFC, field DCD_EN[1] (RW)
41912  *
41913  * Values:
41914  * - 0b0 - NCD Mode (default)
41915  * - 0b1 - DCD Mode
41916  */
41917 /*@{*/
41918 /*! @brief Read current value of the XCVR_ZBDEM_AFC_DCD_EN field. */
41919 #define XCVR_RD_ZBDEM_AFC_DCD_EN(base) ((XCVR_ZBDEM_AFC_REG(base) & XCVR_ZBDEM_AFC_DCD_EN_MASK) >> XCVR_ZBDEM_AFC_DCD_EN_SHIFT)
41920 #define XCVR_BRD_ZBDEM_AFC_DCD_EN(base) (BME_UBFX32(&XCVR_ZBDEM_AFC_REG(base), XCVR_ZBDEM_AFC_DCD_EN_SHIFT, XCVR_ZBDEM_AFC_DCD_EN_WIDTH))
41921 
41922 /*! @brief Set the DCD_EN field to a new value. */
41923 #define XCVR_WR_ZBDEM_AFC_DCD_EN(base, value) (XCVR_RMW_ZBDEM_AFC(base, XCVR_ZBDEM_AFC_DCD_EN_MASK, XCVR_ZBDEM_AFC_DCD_EN(value)))
41924 #define XCVR_BWR_ZBDEM_AFC_DCD_EN(base, value) (BME_BFI32(&XCVR_ZBDEM_AFC_REG(base), ((uint32_t)(value) << XCVR_ZBDEM_AFC_DCD_EN_SHIFT), XCVR_ZBDEM_AFC_DCD_EN_SHIFT, XCVR_ZBDEM_AFC_DCD_EN_WIDTH))
41925 /*@}*/
41926 
41927 /*!
41928  * @name Register XCVR_ZBDEM_AFC, field AFC_OUT[12:8] (RO)
41929  *
41930  * AFC Result, Signed Two's Complement
41931  */
41932 /*@{*/
41933 /*! @brief Read current value of the XCVR_ZBDEM_AFC_AFC_OUT field. */
41934 #define XCVR_RD_ZBDEM_AFC_AFC_OUT(base) ((XCVR_ZBDEM_AFC_REG(base) & XCVR_ZBDEM_AFC_AFC_OUT_MASK) >> XCVR_ZBDEM_AFC_AFC_OUT_SHIFT)
41935 #define XCVR_BRD_ZBDEM_AFC_AFC_OUT(base) (BME_UBFX32(&XCVR_ZBDEM_AFC_REG(base), XCVR_ZBDEM_AFC_AFC_OUT_SHIFT, XCVR_ZBDEM_AFC_AFC_OUT_WIDTH))
41936 /*@}*/
41937 
41938 /*******************************************************************************
41939  * XCVR_LPPS_CTRL - LPPS Control Register
41940  ******************************************************************************/
41941 
41942 /*!
41943  * @brief XCVR_LPPS_CTRL - LPPS Control Register (RW)
41944  *
41945  * Reset value: 0x00000000U
41946  */
41947 /*!
41948  * @name Constants and macros for entire XCVR_LPPS_CTRL register
41949  */
41950 /*@{*/
41951 #define XCVR_RD_LPPS_CTRL(base)  (XCVR_LPPS_CTRL_REG(base))
41952 #define XCVR_WR_LPPS_CTRL(base, value) (XCVR_LPPS_CTRL_REG(base) = (value))
41953 #define XCVR_RMW_LPPS_CTRL(base, mask, value) (XCVR_WR_LPPS_CTRL(base, (XCVR_RD_LPPS_CTRL(base) & ~(mask)) | (value)))
41954 #define XCVR_SET_LPPS_CTRL(base, value) (BME_OR32(&XCVR_LPPS_CTRL_REG(base), (uint32_t)(value)))
41955 #define XCVR_CLR_LPPS_CTRL(base, value) (BME_AND32(&XCVR_LPPS_CTRL_REG(base), (uint32_t)(~(value))))
41956 #define XCVR_TOG_LPPS_CTRL(base, value) (BME_XOR32(&XCVR_LPPS_CTRL_REG(base), (uint32_t)(value)))
41957 /*@}*/
41958 
41959 /*
41960  * Constants & macros for individual XCVR_LPPS_CTRL bitfields
41961  */
41962 
41963 /*!
41964  * @name Register XCVR_LPPS_CTRL, field LPPS_ENABLE[0] (RW)
41965  *
41966  * Master enable for LPPS mode. Allows Zigbee correlators to be duty-cycled
41967  * during Preamble Search, and selected RF/Analog blocks to be duty-cycled
41968  * simultaneously.
41969  *
41970  * Values:
41971  * - 0b0 - LPPS mode disabled
41972  * - 0b1 - LPPS mode enabled
41973  */
41974 /*@{*/
41975 /*! @brief Read current value of the XCVR_LPPS_CTRL_LPPS_ENABLE field. */
41976 #define XCVR_RD_LPPS_CTRL_LPPS_ENABLE(base) ((XCVR_LPPS_CTRL_REG(base) & XCVR_LPPS_CTRL_LPPS_ENABLE_MASK) >> XCVR_LPPS_CTRL_LPPS_ENABLE_SHIFT)
41977 #define XCVR_BRD_LPPS_CTRL_LPPS_ENABLE(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPPS_CTRL_LPPS_ENABLE_SHIFT, XCVR_LPPS_CTRL_LPPS_ENABLE_WIDTH))
41978 
41979 /*! @brief Set the LPPS_ENABLE field to a new value. */
41980 #define XCVR_WR_LPPS_CTRL_LPPS_ENABLE(base, value) (XCVR_RMW_LPPS_CTRL(base, XCVR_LPPS_CTRL_LPPS_ENABLE_MASK, XCVR_LPPS_CTRL_LPPS_ENABLE(value)))
41981 #define XCVR_BWR_LPPS_CTRL_LPPS_ENABLE(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((uint32_t)(value) << XCVR_LPPS_CTRL_LPPS_ENABLE_SHIFT), XCVR_LPPS_CTRL_LPPS_ENABLE_SHIFT, XCVR_LPPS_CTRL_LPPS_ENABLE_WIDTH))
41982 /*@}*/
41983 
41984 /*!
41985  * @name Register XCVR_LPPS_CTRL, field LPPS_QGEN25_ALLOW[1] (RW)
41986  *
41987  * Values:
41988  * - 0b0 - Disallow TSM output qgen25_en to be duty-cycled during LPPS
41989  * - 0b1 - Allow TSM output qgen25_en to be duty-cycled during LPPS
41990  */
41991 /*@{*/
41992 /*! @brief Read current value of the XCVR_LPPS_CTRL_LPPS_QGEN25_ALLOW field. */
41993 #define XCVR_RD_LPPS_CTRL_LPPS_QGEN25_ALLOW(base) ((XCVR_LPPS_CTRL_REG(base) & XCVR_LPPS_CTRL_LPPS_QGEN25_ALLOW_MASK) >> XCVR_LPPS_CTRL_LPPS_QGEN25_ALLOW_SHIFT)
41994 #define XCVR_BRD_LPPS_CTRL_LPPS_QGEN25_ALLOW(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPPS_CTRL_LPPS_QGEN25_ALLOW_SHIFT, XCVR_LPPS_CTRL_LPPS_QGEN25_ALLOW_WIDTH))
41995 
41996 /*! @brief Set the LPPS_QGEN25_ALLOW field to a new value. */
41997 #define XCVR_WR_LPPS_CTRL_LPPS_QGEN25_ALLOW(base, value) (XCVR_RMW_LPPS_CTRL(base, XCVR_LPPS_CTRL_LPPS_QGEN25_ALLOW_MASK, XCVR_LPPS_CTRL_LPPS_QGEN25_ALLOW(value)))
41998 #define XCVR_BWR_LPPS_CTRL_LPPS_QGEN25_ALLOW(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((uint32_t)(value) << XCVR_LPPS_CTRL_LPPS_QGEN25_ALLOW_SHIFT), XCVR_LPPS_CTRL_LPPS_QGEN25_ALLOW_SHIFT, XCVR_LPPS_CTRL_LPPS_QGEN25_ALLOW_WIDTH))
41999 /*@}*/
42000 
42001 /*!
42002  * @name Register XCVR_LPPS_CTRL, field LPPS_ADC_ALLOW[2] (RW)
42003  *
42004  * Values:
42005  * - 0b0 - Disallow ADC-related TSM outputs {adc_en, adc_bias_en} to be
42006  *     duty-cycled during LPPS.
42007  * - 0b1 - Allow ADC-related TSM outputs {adc_en, adc_bias_en} to be duty-cycled
42008  *     during LPPS.
42009  */
42010 /*@{*/
42011 /*! @brief Read current value of the XCVR_LPPS_CTRL_LPPS_ADC_ALLOW field. */
42012 #define XCVR_RD_LPPS_CTRL_LPPS_ADC_ALLOW(base) ((XCVR_LPPS_CTRL_REG(base) & XCVR_LPPS_CTRL_LPPS_ADC_ALLOW_MASK) >> XCVR_LPPS_CTRL_LPPS_ADC_ALLOW_SHIFT)
42013 #define XCVR_BRD_LPPS_CTRL_LPPS_ADC_ALLOW(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPPS_CTRL_LPPS_ADC_ALLOW_SHIFT, XCVR_LPPS_CTRL_LPPS_ADC_ALLOW_WIDTH))
42014 
42015 /*! @brief Set the LPPS_ADC_ALLOW field to a new value. */
42016 #define XCVR_WR_LPPS_CTRL_LPPS_ADC_ALLOW(base, value) (XCVR_RMW_LPPS_CTRL(base, XCVR_LPPS_CTRL_LPPS_ADC_ALLOW_MASK, XCVR_LPPS_CTRL_LPPS_ADC_ALLOW(value)))
42017 #define XCVR_BWR_LPPS_CTRL_LPPS_ADC_ALLOW(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((uint32_t)(value) << XCVR_LPPS_CTRL_LPPS_ADC_ALLOW_SHIFT), XCVR_LPPS_CTRL_LPPS_ADC_ALLOW_SHIFT, XCVR_LPPS_CTRL_LPPS_ADC_ALLOW_WIDTH))
42018 /*@}*/
42019 
42020 /*!
42021  * @name Register XCVR_LPPS_CTRL, field LPPS_ADC_CLK_ALLOW[3] (RW)
42022  *
42023  * Values:
42024  * - 0b0 - Disallow ADC-related TSM outputs {xtal_adc_ref_clk_en, adc_clk_en} to
42025  *     be duty-cycled during LPPS.
42026  * - 0b1 - Allow ADC_CLK-related TSM outputs {xtal_adc_ref_clk_en, adc_clk_en}
42027  *     to be duty-cycled during LPPS.
42028  */
42029 /*@{*/
42030 /*! @brief Read current value of the XCVR_LPPS_CTRL_LPPS_ADC_CLK_ALLOW field. */
42031 #define XCVR_RD_LPPS_CTRL_LPPS_ADC_CLK_ALLOW(base) ((XCVR_LPPS_CTRL_REG(base) & XCVR_LPPS_CTRL_LPPS_ADC_CLK_ALLOW_MASK) >> XCVR_LPPS_CTRL_LPPS_ADC_CLK_ALLOW_SHIFT)
42032 #define XCVR_BRD_LPPS_CTRL_LPPS_ADC_CLK_ALLOW(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPPS_CTRL_LPPS_ADC_CLK_ALLOW_SHIFT, XCVR_LPPS_CTRL_LPPS_ADC_CLK_ALLOW_WIDTH))
42033 
42034 /*! @brief Set the LPPS_ADC_CLK_ALLOW field to a new value. */
42035 #define XCVR_WR_LPPS_CTRL_LPPS_ADC_CLK_ALLOW(base, value) (XCVR_RMW_LPPS_CTRL(base, XCVR_LPPS_CTRL_LPPS_ADC_CLK_ALLOW_MASK, XCVR_LPPS_CTRL_LPPS_ADC_CLK_ALLOW(value)))
42036 #define XCVR_BWR_LPPS_CTRL_LPPS_ADC_CLK_ALLOW(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((uint32_t)(value) << XCVR_LPPS_CTRL_LPPS_ADC_CLK_ALLOW_SHIFT), XCVR_LPPS_CTRL_LPPS_ADC_CLK_ALLOW_SHIFT, XCVR_LPPS_CTRL_LPPS_ADC_CLK_ALLOW_WIDTH))
42037 /*@}*/
42038 
42039 /*!
42040  * @name Register XCVR_LPPS_CTRL, field LPPS_ADC_I_Q_ALLOW[4] (RW)
42041  *
42042  * Values:
42043  * - 0b0 - Disallow ADC_I/Q-related TSM outputs {adc_I_adc_en, adc_Q_adc_en} to
42044  *     be duty-cycled during LPPS.
42045  * - 0b1 - Allow ADC_I/Q-related TSM outputs {adc_I_adc_en, adc_Q_adc_en} to be
42046  *     duty-cycled during LPPS.
42047  */
42048 /*@{*/
42049 /*! @brief Read current value of the XCVR_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW field. */
42050 #define XCVR_RD_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW(base) ((XCVR_LPPS_CTRL_REG(base) & XCVR_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW_MASK) >> XCVR_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW_SHIFT)
42051 #define XCVR_BRD_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW_SHIFT, XCVR_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW_WIDTH))
42052 
42053 /*! @brief Set the LPPS_ADC_I_Q_ALLOW field to a new value. */
42054 #define XCVR_WR_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW(base, value) (XCVR_RMW_LPPS_CTRL(base, XCVR_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW_MASK, XCVR_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW(value)))
42055 #define XCVR_BWR_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((uint32_t)(value) << XCVR_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW_SHIFT), XCVR_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW_SHIFT, XCVR_LPPS_CTRL_LPPS_ADC_I_Q_ALLOW_WIDTH))
42056 /*@}*/
42057 
42058 /*!
42059  * @name Register XCVR_LPPS_CTRL, field LPPS_ADC_DAC_ALLOW[5] (RW)
42060  *
42061  * Values:
42062  * - 0b0 - Disallow ADC_DAC-related TSM outputs {adc_dac1_en, adc_dac2_en} to be
42063  *     duty-cycled during LPPS.
42064  * - 0b1 - Allow ADC_DAC-related TSM outputs {adc_dac1_en, adc_dac2_en} to be
42065  *     duty-cycled during LPPS.
42066  */
42067 /*@{*/
42068 /*! @brief Read current value of the XCVR_LPPS_CTRL_LPPS_ADC_DAC_ALLOW field. */
42069 #define XCVR_RD_LPPS_CTRL_LPPS_ADC_DAC_ALLOW(base) ((XCVR_LPPS_CTRL_REG(base) & XCVR_LPPS_CTRL_LPPS_ADC_DAC_ALLOW_MASK) >> XCVR_LPPS_CTRL_LPPS_ADC_DAC_ALLOW_SHIFT)
42070 #define XCVR_BRD_LPPS_CTRL_LPPS_ADC_DAC_ALLOW(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPPS_CTRL_LPPS_ADC_DAC_ALLOW_SHIFT, XCVR_LPPS_CTRL_LPPS_ADC_DAC_ALLOW_WIDTH))
42071 
42072 /*! @brief Set the LPPS_ADC_DAC_ALLOW field to a new value. */
42073 #define XCVR_WR_LPPS_CTRL_LPPS_ADC_DAC_ALLOW(base, value) (XCVR_RMW_LPPS_CTRL(base, XCVR_LPPS_CTRL_LPPS_ADC_DAC_ALLOW_MASK, XCVR_LPPS_CTRL_LPPS_ADC_DAC_ALLOW(value)))
42074 #define XCVR_BWR_LPPS_CTRL_LPPS_ADC_DAC_ALLOW(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((uint32_t)(value) << XCVR_LPPS_CTRL_LPPS_ADC_DAC_ALLOW_SHIFT), XCVR_LPPS_CTRL_LPPS_ADC_DAC_ALLOW_SHIFT, XCVR_LPPS_CTRL_LPPS_ADC_DAC_ALLOW_WIDTH))
42075 /*@}*/
42076 
42077 /*!
42078  * @name Register XCVR_LPPS_CTRL, field LPPS_BBF_ALLOW[6] (RW)
42079  *
42080  * Values:
42081  * - 0b0 - Disallow BBF-related TSM outputs {bbf_i_en, bbf_q_en, bbf_pdet_en,
42082  *     bbf_dcoc_en} to be duty-cycled during LPPS.
42083  * - 0b1 - Allow BBF-related TSM outputs {bbf_i_en, bbf_q_en, bbf_pdet_en,
42084  *     bbf_dcoc_en} to be duty-cycled during LPPS.
42085  */
42086 /*@{*/
42087 /*! @brief Read current value of the XCVR_LPPS_CTRL_LPPS_BBF_ALLOW field. */
42088 #define XCVR_RD_LPPS_CTRL_LPPS_BBF_ALLOW(base) ((XCVR_LPPS_CTRL_REG(base) & XCVR_LPPS_CTRL_LPPS_BBF_ALLOW_MASK) >> XCVR_LPPS_CTRL_LPPS_BBF_ALLOW_SHIFT)
42089 #define XCVR_BRD_LPPS_CTRL_LPPS_BBF_ALLOW(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPPS_CTRL_LPPS_BBF_ALLOW_SHIFT, XCVR_LPPS_CTRL_LPPS_BBF_ALLOW_WIDTH))
42090 
42091 /*! @brief Set the LPPS_BBF_ALLOW field to a new value. */
42092 #define XCVR_WR_LPPS_CTRL_LPPS_BBF_ALLOW(base, value) (XCVR_RMW_LPPS_CTRL(base, XCVR_LPPS_CTRL_LPPS_BBF_ALLOW_MASK, XCVR_LPPS_CTRL_LPPS_BBF_ALLOW(value)))
42093 #define XCVR_BWR_LPPS_CTRL_LPPS_BBF_ALLOW(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((uint32_t)(value) << XCVR_LPPS_CTRL_LPPS_BBF_ALLOW_SHIFT), XCVR_LPPS_CTRL_LPPS_BBF_ALLOW_SHIFT, XCVR_LPPS_CTRL_LPPS_BBF_ALLOW_WIDTH))
42094 /*@}*/
42095 
42096 /*!
42097  * @name Register XCVR_LPPS_CTRL, field LPPS_TCA_ALLOW[7] (RW)
42098  *
42099  * Values:
42100  * - 0b0 - Disallow TCA-related TSM outputs {tca_en, tza_i_en, tza_q_en,
42101  *     tza_pdet_en, tza_dcoc_en} to be duty-cycled during LPPS.
42102  * - 0b1 - Allow TCA-related TSM outputs {tca_en, tza_i_en, tza_q_en,
42103  *     tza_pdet_en, tza_dcoc_en} to be duty-cycled during LPPS.
42104  */
42105 /*@{*/
42106 /*! @brief Read current value of the XCVR_LPPS_CTRL_LPPS_TCA_ALLOW field. */
42107 #define XCVR_RD_LPPS_CTRL_LPPS_TCA_ALLOW(base) ((XCVR_LPPS_CTRL_REG(base) & XCVR_LPPS_CTRL_LPPS_TCA_ALLOW_MASK) >> XCVR_LPPS_CTRL_LPPS_TCA_ALLOW_SHIFT)
42108 #define XCVR_BRD_LPPS_CTRL_LPPS_TCA_ALLOW(base) (BME_UBFX32(&XCVR_LPPS_CTRL_REG(base), XCVR_LPPS_CTRL_LPPS_TCA_ALLOW_SHIFT, XCVR_LPPS_CTRL_LPPS_TCA_ALLOW_WIDTH))
42109 
42110 /*! @brief Set the LPPS_TCA_ALLOW field to a new value. */
42111 #define XCVR_WR_LPPS_CTRL_LPPS_TCA_ALLOW(base, value) (XCVR_RMW_LPPS_CTRL(base, XCVR_LPPS_CTRL_LPPS_TCA_ALLOW_MASK, XCVR_LPPS_CTRL_LPPS_TCA_ALLOW(value)))
42112 #define XCVR_BWR_LPPS_CTRL_LPPS_TCA_ALLOW(base, value) (BME_BFI32(&XCVR_LPPS_CTRL_REG(base), ((uint32_t)(value) << XCVR_LPPS_CTRL_LPPS_TCA_ALLOW_SHIFT), XCVR_LPPS_CTRL_LPPS_TCA_ALLOW_SHIFT, XCVR_LPPS_CTRL_LPPS_TCA_ALLOW_WIDTH))
42113 /*@}*/
42114 
42115 /*******************************************************************************
42116  * XCVR_ADC_CTRL - ADC Control
42117  ******************************************************************************/
42118 
42119 /*!
42120  * @brief XCVR_ADC_CTRL - ADC Control (RW)
42121  *
42122  * Reset value: 0xFFFF0001U
42123  */
42124 /*!
42125  * @name Constants and macros for entire XCVR_ADC_CTRL register
42126  */
42127 /*@{*/
42128 #define XCVR_RD_ADC_CTRL(base)   (XCVR_ADC_CTRL_REG(base))
42129 #define XCVR_WR_ADC_CTRL(base, value) (XCVR_ADC_CTRL_REG(base) = (value))
42130 #define XCVR_RMW_ADC_CTRL(base, mask, value) (XCVR_WR_ADC_CTRL(base, (XCVR_RD_ADC_CTRL(base) & ~(mask)) | (value)))
42131 #define XCVR_SET_ADC_CTRL(base, value) (BME_OR32(&XCVR_ADC_CTRL_REG(base), (uint32_t)(value)))
42132 #define XCVR_CLR_ADC_CTRL(base, value) (BME_AND32(&XCVR_ADC_CTRL_REG(base), (uint32_t)(~(value))))
42133 #define XCVR_TOG_ADC_CTRL(base, value) (BME_XOR32(&XCVR_ADC_CTRL_REG(base), (uint32_t)(value)))
42134 /*@}*/
42135 
42136 /*
42137  * Constants & macros for individual XCVR_ADC_CTRL bitfields
42138  */
42139 
42140 /*!
42141  * @name Register XCVR_ADC_CTRL, field ADC_32MHZ_SEL[0] (RW)
42142  *
42143  * Select settings for a 32MHz reference clock. If this bit is not set then
42144  * settings for a 36MHz clock is chosen. Only the 32Mhz option is enabled in this
42145  * version.
42146  */
42147 /*@{*/
42148 /*! @brief Read current value of the XCVR_ADC_CTRL_ADC_32MHZ_SEL field. */
42149 #define XCVR_RD_ADC_CTRL_ADC_32MHZ_SEL(base) ((XCVR_ADC_CTRL_REG(base) & XCVR_ADC_CTRL_ADC_32MHZ_SEL_MASK) >> XCVR_ADC_CTRL_ADC_32MHZ_SEL_SHIFT)
42150 #define XCVR_BRD_ADC_CTRL_ADC_32MHZ_SEL(base) (BME_UBFX32(&XCVR_ADC_CTRL_REG(base), XCVR_ADC_CTRL_ADC_32MHZ_SEL_SHIFT, XCVR_ADC_CTRL_ADC_32MHZ_SEL_WIDTH))
42151 
42152 /*! @brief Set the ADC_32MHZ_SEL field to a new value. */
42153 #define XCVR_WR_ADC_CTRL_ADC_32MHZ_SEL(base, value) (XCVR_RMW_ADC_CTRL(base, XCVR_ADC_CTRL_ADC_32MHZ_SEL_MASK, XCVR_ADC_CTRL_ADC_32MHZ_SEL(value)))
42154 #define XCVR_BWR_ADC_CTRL_ADC_32MHZ_SEL(base, value) (BME_BFI32(&XCVR_ADC_CTRL_REG(base), ((uint32_t)(value) << XCVR_ADC_CTRL_ADC_32MHZ_SEL_SHIFT), XCVR_ADC_CTRL_ADC_32MHZ_SEL_SHIFT, XCVR_ADC_CTRL_ADC_32MHZ_SEL_WIDTH))
42155 /*@}*/
42156 
42157 /*!
42158  * @name Register XCVR_ADC_CTRL, field ADC_2X_CLK_SEL[2] (RW)
42159  *
42160  * Select 2x Clock option in the ADC. When this bit is enabled a clock of 64Mhz
42161  * is assumed. This option is not used in this version and reserved for future
42162  * use.
42163  */
42164 /*@{*/
42165 /*! @brief Read current value of the XCVR_ADC_CTRL_ADC_2X_CLK_SEL field. */
42166 #define XCVR_RD_ADC_CTRL_ADC_2X_CLK_SEL(base) ((XCVR_ADC_CTRL_REG(base) & XCVR_ADC_CTRL_ADC_2X_CLK_SEL_MASK) >> XCVR_ADC_CTRL_ADC_2X_CLK_SEL_SHIFT)
42167 #define XCVR_BRD_ADC_CTRL_ADC_2X_CLK_SEL(base) (BME_UBFX32(&XCVR_ADC_CTRL_REG(base), XCVR_ADC_CTRL_ADC_2X_CLK_SEL_SHIFT, XCVR_ADC_CTRL_ADC_2X_CLK_SEL_WIDTH))
42168 
42169 /*! @brief Set the ADC_2X_CLK_SEL field to a new value. */
42170 #define XCVR_WR_ADC_CTRL_ADC_2X_CLK_SEL(base, value) (XCVR_RMW_ADC_CTRL(base, XCVR_ADC_CTRL_ADC_2X_CLK_SEL_MASK, XCVR_ADC_CTRL_ADC_2X_CLK_SEL(value)))
42171 #define XCVR_BWR_ADC_CTRL_ADC_2X_CLK_SEL(base, value) (BME_BFI32(&XCVR_ADC_CTRL_REG(base), ((uint32_t)(value) << XCVR_ADC_CTRL_ADC_2X_CLK_SEL_SHIFT), XCVR_ADC_CTRL_ADC_2X_CLK_SEL_SHIFT, XCVR_ADC_CTRL_ADC_2X_CLK_SEL_WIDTH))
42172 /*@}*/
42173 
42174 /*!
42175  * @name Register XCVR_ADC_CTRL, field ADC_DITHER_ON[9] (RW)
42176  *
42177  * Enables the dither circuit inside the ADC block. By enabling this bit
42178  * dithering of tones can be achieved.
42179  */
42180 /*@{*/
42181 /*! @brief Read current value of the XCVR_ADC_CTRL_ADC_DITHER_ON field. */
42182 #define XCVR_RD_ADC_CTRL_ADC_DITHER_ON(base) ((XCVR_ADC_CTRL_REG(base) & XCVR_ADC_CTRL_ADC_DITHER_ON_MASK) >> XCVR_ADC_CTRL_ADC_DITHER_ON_SHIFT)
42183 #define XCVR_BRD_ADC_CTRL_ADC_DITHER_ON(base) (BME_UBFX32(&XCVR_ADC_CTRL_REG(base), XCVR_ADC_CTRL_ADC_DITHER_ON_SHIFT, XCVR_ADC_CTRL_ADC_DITHER_ON_WIDTH))
42184 
42185 /*! @brief Set the ADC_DITHER_ON field to a new value. */
42186 #define XCVR_WR_ADC_CTRL_ADC_DITHER_ON(base, value) (XCVR_RMW_ADC_CTRL(base, XCVR_ADC_CTRL_ADC_DITHER_ON_MASK, XCVR_ADC_CTRL_ADC_DITHER_ON(value)))
42187 #define XCVR_BWR_ADC_CTRL_ADC_DITHER_ON(base, value) (BME_BFI32(&XCVR_ADC_CTRL_REG(base), ((uint32_t)(value) << XCVR_ADC_CTRL_ADC_DITHER_ON_SHIFT), XCVR_ADC_CTRL_ADC_DITHER_ON_SHIFT, XCVR_ADC_CTRL_ADC_DITHER_ON_WIDTH))
42188 /*@}*/
42189 
42190 /*!
42191  * @name Register XCVR_ADC_CTRL, field ADC_TEST_ON[10] (RW)
42192  *
42193  * When enabled (1) this bit puts the adc in test mode where different test
42194  * signals can be injected or measured. In normal mode this bit is diabled(0).
42195  */
42196 /*@{*/
42197 /*! @brief Read current value of the XCVR_ADC_CTRL_ADC_TEST_ON field. */
42198 #define XCVR_RD_ADC_CTRL_ADC_TEST_ON(base) ((XCVR_ADC_CTRL_REG(base) & XCVR_ADC_CTRL_ADC_TEST_ON_MASK) >> XCVR_ADC_CTRL_ADC_TEST_ON_SHIFT)
42199 #define XCVR_BRD_ADC_CTRL_ADC_TEST_ON(base) (BME_UBFX32(&XCVR_ADC_CTRL_REG(base), XCVR_ADC_CTRL_ADC_TEST_ON_SHIFT, XCVR_ADC_CTRL_ADC_TEST_ON_WIDTH))
42200 
42201 /*! @brief Set the ADC_TEST_ON field to a new value. */
42202 #define XCVR_WR_ADC_CTRL_ADC_TEST_ON(base, value) (XCVR_RMW_ADC_CTRL(base, XCVR_ADC_CTRL_ADC_TEST_ON_MASK, XCVR_ADC_CTRL_ADC_TEST_ON(value)))
42203 #define XCVR_BWR_ADC_CTRL_ADC_TEST_ON(base, value) (BME_BFI32(&XCVR_ADC_CTRL_REG(base), ((uint32_t)(value) << XCVR_ADC_CTRL_ADC_TEST_ON_SHIFT), XCVR_ADC_CTRL_ADC_TEST_ON_SHIFT, XCVR_ADC_CTRL_ADC_TEST_ON_WIDTH))
42204 /*@}*/
42205 
42206 /*!
42207  * @name Register XCVR_ADC_CTRL, field ADC_COMP_ON[31:16] (RW)
42208  *
42209  * These bits enable or disable the individual comparators in the quantizer. In
42210  * the normal mode all these bits should be enabled. The disables are used for
42211  * testing purposes only
42212  */
42213 /*@{*/
42214 /*! @brief Read current value of the XCVR_ADC_CTRL_ADC_COMP_ON field. */
42215 #define XCVR_RD_ADC_CTRL_ADC_COMP_ON(base) ((XCVR_ADC_CTRL_REG(base) & XCVR_ADC_CTRL_ADC_COMP_ON_MASK) >> XCVR_ADC_CTRL_ADC_COMP_ON_SHIFT)
42216 #define XCVR_BRD_ADC_CTRL_ADC_COMP_ON(base) (BME_UBFX32(&XCVR_ADC_CTRL_REG(base), XCVR_ADC_CTRL_ADC_COMP_ON_SHIFT, XCVR_ADC_CTRL_ADC_COMP_ON_WIDTH))
42217 
42218 /*! @brief Set the ADC_COMP_ON field to a new value. */
42219 #define XCVR_WR_ADC_CTRL_ADC_COMP_ON(base, value) (XCVR_RMW_ADC_CTRL(base, XCVR_ADC_CTRL_ADC_COMP_ON_MASK, XCVR_ADC_CTRL_ADC_COMP_ON(value)))
42220 #define XCVR_BWR_ADC_CTRL_ADC_COMP_ON(base, value) (BME_BFI32(&XCVR_ADC_CTRL_REG(base), ((uint32_t)(value) << XCVR_ADC_CTRL_ADC_COMP_ON_SHIFT), XCVR_ADC_CTRL_ADC_COMP_ON_SHIFT, XCVR_ADC_CTRL_ADC_COMP_ON_WIDTH))
42221 /*@}*/
42222 
42223 /*******************************************************************************
42224  * XCVR_ADC_TUNE - ADC Tuning
42225  ******************************************************************************/
42226 
42227 /*!
42228  * @brief XCVR_ADC_TUNE - ADC Tuning (RW)
42229  *
42230  * Reset value: 0x00880033U
42231  */
42232 /*!
42233  * @name Constants and macros for entire XCVR_ADC_TUNE register
42234  */
42235 /*@{*/
42236 #define XCVR_RD_ADC_TUNE(base)   (XCVR_ADC_TUNE_REG(base))
42237 #define XCVR_WR_ADC_TUNE(base, value) (XCVR_ADC_TUNE_REG(base) = (value))
42238 #define XCVR_RMW_ADC_TUNE(base, mask, value) (XCVR_WR_ADC_TUNE(base, (XCVR_RD_ADC_TUNE(base) & ~(mask)) | (value)))
42239 #define XCVR_SET_ADC_TUNE(base, value) (BME_OR32(&XCVR_ADC_TUNE_REG(base), (uint32_t)(value)))
42240 #define XCVR_CLR_ADC_TUNE(base, value) (BME_AND32(&XCVR_ADC_TUNE_REG(base), (uint32_t)(~(value))))
42241 #define XCVR_TOG_ADC_TUNE(base, value) (BME_XOR32(&XCVR_ADC_TUNE_REG(base), (uint32_t)(value)))
42242 /*@}*/
42243 
42244 /*
42245  * Constants & macros for individual XCVR_ADC_TUNE bitfields
42246  */
42247 
42248 /*!
42249  * @name Register XCVR_ADC_TUNE, field ADC_R1_TUNE[2:0] (RW)
42250  *
42251  * Allows to tune the resistor values of the first integrator +/- 15%. Default
42252  * setting is 0b011.
42253  */
42254 /*@{*/
42255 /*! @brief Read current value of the XCVR_ADC_TUNE_ADC_R1_TUNE field. */
42256 #define XCVR_RD_ADC_TUNE_ADC_R1_TUNE(base) ((XCVR_ADC_TUNE_REG(base) & XCVR_ADC_TUNE_ADC_R1_TUNE_MASK) >> XCVR_ADC_TUNE_ADC_R1_TUNE_SHIFT)
42257 #define XCVR_BRD_ADC_TUNE_ADC_R1_TUNE(base) (BME_UBFX32(&XCVR_ADC_TUNE_REG(base), XCVR_ADC_TUNE_ADC_R1_TUNE_SHIFT, XCVR_ADC_TUNE_ADC_R1_TUNE_WIDTH))
42258 
42259 /*! @brief Set the ADC_R1_TUNE field to a new value. */
42260 #define XCVR_WR_ADC_TUNE_ADC_R1_TUNE(base, value) (XCVR_RMW_ADC_TUNE(base, XCVR_ADC_TUNE_ADC_R1_TUNE_MASK, XCVR_ADC_TUNE_ADC_R1_TUNE(value)))
42261 #define XCVR_BWR_ADC_TUNE_ADC_R1_TUNE(base, value) (BME_BFI32(&XCVR_ADC_TUNE_REG(base), ((uint32_t)(value) << XCVR_ADC_TUNE_ADC_R1_TUNE_SHIFT), XCVR_ADC_TUNE_ADC_R1_TUNE_SHIFT, XCVR_ADC_TUNE_ADC_R1_TUNE_WIDTH))
42262 /*@}*/
42263 
42264 /*!
42265  * @name Register XCVR_ADC_TUNE, field ADC_R2_TUNE[6:4] (RW)
42266  *
42267  * Allows to tune the resistor values of the second integrator +/- 15%. Default
42268  * setting is 0b011.
42269  */
42270 /*@{*/
42271 /*! @brief Read current value of the XCVR_ADC_TUNE_ADC_R2_TUNE field. */
42272 #define XCVR_RD_ADC_TUNE_ADC_R2_TUNE(base) ((XCVR_ADC_TUNE_REG(base) & XCVR_ADC_TUNE_ADC_R2_TUNE_MASK) >> XCVR_ADC_TUNE_ADC_R2_TUNE_SHIFT)
42273 #define XCVR_BRD_ADC_TUNE_ADC_R2_TUNE(base) (BME_UBFX32(&XCVR_ADC_TUNE_REG(base), XCVR_ADC_TUNE_ADC_R2_TUNE_SHIFT, XCVR_ADC_TUNE_ADC_R2_TUNE_WIDTH))
42274 
42275 /*! @brief Set the ADC_R2_TUNE field to a new value. */
42276 #define XCVR_WR_ADC_TUNE_ADC_R2_TUNE(base, value) (XCVR_RMW_ADC_TUNE(base, XCVR_ADC_TUNE_ADC_R2_TUNE_MASK, XCVR_ADC_TUNE_ADC_R2_TUNE(value)))
42277 #define XCVR_BWR_ADC_TUNE_ADC_R2_TUNE(base, value) (BME_BFI32(&XCVR_ADC_TUNE_REG(base), ((uint32_t)(value) << XCVR_ADC_TUNE_ADC_R2_TUNE_SHIFT), XCVR_ADC_TUNE_ADC_R2_TUNE_SHIFT, XCVR_ADC_TUNE_ADC_R2_TUNE_WIDTH))
42278 /*@}*/
42279 
42280 /*!
42281  * @name Register XCVR_ADC_TUNE, field ADC_C1_TUNE[19:16] (RW)
42282  *
42283  * Allows to tune the capacitor values of the first integrator +/- 15%. Default
42284  * setting is 0b1000.
42285  */
42286 /*@{*/
42287 /*! @brief Read current value of the XCVR_ADC_TUNE_ADC_C1_TUNE field. */
42288 #define XCVR_RD_ADC_TUNE_ADC_C1_TUNE(base) ((XCVR_ADC_TUNE_REG(base) & XCVR_ADC_TUNE_ADC_C1_TUNE_MASK) >> XCVR_ADC_TUNE_ADC_C1_TUNE_SHIFT)
42289 #define XCVR_BRD_ADC_TUNE_ADC_C1_TUNE(base) (BME_UBFX32(&XCVR_ADC_TUNE_REG(base), XCVR_ADC_TUNE_ADC_C1_TUNE_SHIFT, XCVR_ADC_TUNE_ADC_C1_TUNE_WIDTH))
42290 
42291 /*! @brief Set the ADC_C1_TUNE field to a new value. */
42292 #define XCVR_WR_ADC_TUNE_ADC_C1_TUNE(base, value) (XCVR_RMW_ADC_TUNE(base, XCVR_ADC_TUNE_ADC_C1_TUNE_MASK, XCVR_ADC_TUNE_ADC_C1_TUNE(value)))
42293 #define XCVR_BWR_ADC_TUNE_ADC_C1_TUNE(base, value) (BME_BFI32(&XCVR_ADC_TUNE_REG(base), ((uint32_t)(value) << XCVR_ADC_TUNE_ADC_C1_TUNE_SHIFT), XCVR_ADC_TUNE_ADC_C1_TUNE_SHIFT, XCVR_ADC_TUNE_ADC_C1_TUNE_WIDTH))
42294 /*@}*/
42295 
42296 /*!
42297  * @name Register XCVR_ADC_TUNE, field ADC_C2_TUNE[23:20] (RW)
42298  *
42299  * Allows to tune the capacitor values of the second integrator +/- 15%. Default
42300  * setting is 0b1000.
42301  */
42302 /*@{*/
42303 /*! @brief Read current value of the XCVR_ADC_TUNE_ADC_C2_TUNE field. */
42304 #define XCVR_RD_ADC_TUNE_ADC_C2_TUNE(base) ((XCVR_ADC_TUNE_REG(base) & XCVR_ADC_TUNE_ADC_C2_TUNE_MASK) >> XCVR_ADC_TUNE_ADC_C2_TUNE_SHIFT)
42305 #define XCVR_BRD_ADC_TUNE_ADC_C2_TUNE(base) (BME_UBFX32(&XCVR_ADC_TUNE_REG(base), XCVR_ADC_TUNE_ADC_C2_TUNE_SHIFT, XCVR_ADC_TUNE_ADC_C2_TUNE_WIDTH))
42306 
42307 /*! @brief Set the ADC_C2_TUNE field to a new value. */
42308 #define XCVR_WR_ADC_TUNE_ADC_C2_TUNE(base, value) (XCVR_RMW_ADC_TUNE(base, XCVR_ADC_TUNE_ADC_C2_TUNE_MASK, XCVR_ADC_TUNE_ADC_C2_TUNE(value)))
42309 #define XCVR_BWR_ADC_TUNE_ADC_C2_TUNE(base, value) (BME_BFI32(&XCVR_ADC_TUNE_REG(base), ((uint32_t)(value) << XCVR_ADC_TUNE_ADC_C2_TUNE_SHIFT), XCVR_ADC_TUNE_ADC_C2_TUNE_SHIFT, XCVR_ADC_TUNE_ADC_C2_TUNE_WIDTH))
42310 /*@}*/
42311 
42312 /*******************************************************************************
42313  * XCVR_ADC_ADJ - ADC Adjustment
42314  ******************************************************************************/
42315 
42316 /*!
42317  * @brief XCVR_ADC_ADJ - ADC Adjustment (RW)
42318  *
42319  * Reset value: 0x43033033U
42320  */
42321 /*!
42322  * @name Constants and macros for entire XCVR_ADC_ADJ register
42323  */
42324 /*@{*/
42325 #define XCVR_RD_ADC_ADJ(base)    (XCVR_ADC_ADJ_REG(base))
42326 #define XCVR_WR_ADC_ADJ(base, value) (XCVR_ADC_ADJ_REG(base) = (value))
42327 #define XCVR_RMW_ADC_ADJ(base, mask, value) (XCVR_WR_ADC_ADJ(base, (XCVR_RD_ADC_ADJ(base) & ~(mask)) | (value)))
42328 #define XCVR_SET_ADC_ADJ(base, value) (BME_OR32(&XCVR_ADC_ADJ_REG(base), (uint32_t)(value)))
42329 #define XCVR_CLR_ADC_ADJ(base, value) (BME_AND32(&XCVR_ADC_ADJ_REG(base), (uint32_t)(~(value))))
42330 #define XCVR_TOG_ADC_ADJ(base, value) (BME_XOR32(&XCVR_ADC_ADJ_REG(base), (uint32_t)(value)))
42331 /*@}*/
42332 
42333 /*
42334  * Constants & macros for individual XCVR_ADC_ADJ bitfields
42335  */
42336 
42337 /*!
42338  * @name Register XCVR_ADC_ADJ, field ADC_IB_OPAMP1_ADJ[2:0] (RW)
42339  *
42340  * Adjusts the 1st integrator operational amplifier reference current +/-30%.
42341  * Default setting is 0b011.
42342  */
42343 /*@{*/
42344 /*! @brief Read current value of the XCVR_ADC_ADJ_ADC_IB_OPAMP1_ADJ field. */
42345 #define XCVR_RD_ADC_ADJ_ADC_IB_OPAMP1_ADJ(base) ((XCVR_ADC_ADJ_REG(base) & XCVR_ADC_ADJ_ADC_IB_OPAMP1_ADJ_MASK) >> XCVR_ADC_ADJ_ADC_IB_OPAMP1_ADJ_SHIFT)
42346 #define XCVR_BRD_ADC_ADJ_ADC_IB_OPAMP1_ADJ(base) (BME_UBFX32(&XCVR_ADC_ADJ_REG(base), XCVR_ADC_ADJ_ADC_IB_OPAMP1_ADJ_SHIFT, XCVR_ADC_ADJ_ADC_IB_OPAMP1_ADJ_WIDTH))
42347 
42348 /*! @brief Set the ADC_IB_OPAMP1_ADJ field to a new value. */
42349 #define XCVR_WR_ADC_ADJ_ADC_IB_OPAMP1_ADJ(base, value) (XCVR_RMW_ADC_ADJ(base, XCVR_ADC_ADJ_ADC_IB_OPAMP1_ADJ_MASK, XCVR_ADC_ADJ_ADC_IB_OPAMP1_ADJ(value)))
42350 #define XCVR_BWR_ADC_ADJ_ADC_IB_OPAMP1_ADJ(base, value) (BME_BFI32(&XCVR_ADC_ADJ_REG(base), ((uint32_t)(value) << XCVR_ADC_ADJ_ADC_IB_OPAMP1_ADJ_SHIFT), XCVR_ADC_ADJ_ADC_IB_OPAMP1_ADJ_SHIFT, XCVR_ADC_ADJ_ADC_IB_OPAMP1_ADJ_WIDTH))
42351 /*@}*/
42352 
42353 /*!
42354  * @name Register XCVR_ADC_ADJ, field ADC_IB_OPAMP2_ADJ[6:4] (RW)
42355  *
42356  * Adjusts the 2nd integrator operational amplifier reference current +/-30%.
42357  * Default setting is 0b011.
42358  */
42359 /*@{*/
42360 /*! @brief Read current value of the XCVR_ADC_ADJ_ADC_IB_OPAMP2_ADJ field. */
42361 #define XCVR_RD_ADC_ADJ_ADC_IB_OPAMP2_ADJ(base) ((XCVR_ADC_ADJ_REG(base) & XCVR_ADC_ADJ_ADC_IB_OPAMP2_ADJ_MASK) >> XCVR_ADC_ADJ_ADC_IB_OPAMP2_ADJ_SHIFT)
42362 #define XCVR_BRD_ADC_ADJ_ADC_IB_OPAMP2_ADJ(base) (BME_UBFX32(&XCVR_ADC_ADJ_REG(base), XCVR_ADC_ADJ_ADC_IB_OPAMP2_ADJ_SHIFT, XCVR_ADC_ADJ_ADC_IB_OPAMP2_ADJ_WIDTH))
42363 
42364 /*! @brief Set the ADC_IB_OPAMP2_ADJ field to a new value. */
42365 #define XCVR_WR_ADC_ADJ_ADC_IB_OPAMP2_ADJ(base, value) (XCVR_RMW_ADC_ADJ(base, XCVR_ADC_ADJ_ADC_IB_OPAMP2_ADJ_MASK, XCVR_ADC_ADJ_ADC_IB_OPAMP2_ADJ(value)))
42366 #define XCVR_BWR_ADC_ADJ_ADC_IB_OPAMP2_ADJ(base, value) (BME_BFI32(&XCVR_ADC_ADJ_REG(base), ((uint32_t)(value) << XCVR_ADC_ADJ_ADC_IB_OPAMP2_ADJ_SHIFT), XCVR_ADC_ADJ_ADC_IB_OPAMP2_ADJ_SHIFT, XCVR_ADC_ADJ_ADC_IB_OPAMP2_ADJ_WIDTH))
42367 /*@}*/
42368 
42369 /*!
42370  * @name Register XCVR_ADC_ADJ, field ADC_IB_DAC1_ADJ[14:12] (RW)
42371  *
42372  * Adjusts the DAC 1 current +/-30%. Default setting is 0b011.
42373  */
42374 /*@{*/
42375 /*! @brief Read current value of the XCVR_ADC_ADJ_ADC_IB_DAC1_ADJ field. */
42376 #define XCVR_RD_ADC_ADJ_ADC_IB_DAC1_ADJ(base) ((XCVR_ADC_ADJ_REG(base) & XCVR_ADC_ADJ_ADC_IB_DAC1_ADJ_MASK) >> XCVR_ADC_ADJ_ADC_IB_DAC1_ADJ_SHIFT)
42377 #define XCVR_BRD_ADC_ADJ_ADC_IB_DAC1_ADJ(base) (BME_UBFX32(&XCVR_ADC_ADJ_REG(base), XCVR_ADC_ADJ_ADC_IB_DAC1_ADJ_SHIFT, XCVR_ADC_ADJ_ADC_IB_DAC1_ADJ_WIDTH))
42378 
42379 /*! @brief Set the ADC_IB_DAC1_ADJ field to a new value. */
42380 #define XCVR_WR_ADC_ADJ_ADC_IB_DAC1_ADJ(base, value) (XCVR_RMW_ADC_ADJ(base, XCVR_ADC_ADJ_ADC_IB_DAC1_ADJ_MASK, XCVR_ADC_ADJ_ADC_IB_DAC1_ADJ(value)))
42381 #define XCVR_BWR_ADC_ADJ_ADC_IB_DAC1_ADJ(base, value) (BME_BFI32(&XCVR_ADC_ADJ_REG(base), ((uint32_t)(value) << XCVR_ADC_ADJ_ADC_IB_DAC1_ADJ_SHIFT), XCVR_ADC_ADJ_ADC_IB_DAC1_ADJ_SHIFT, XCVR_ADC_ADJ_ADC_IB_DAC1_ADJ_WIDTH))
42382 /*@}*/
42383 
42384 /*!
42385  * @name Register XCVR_ADC_ADJ, field ADC_IB_DAC2_ADJ[18:16] (RW)
42386  *
42387  * Adjusts the DAC 2 current +/-30%. Default setting is 0b011.
42388  */
42389 /*@{*/
42390 /*! @brief Read current value of the XCVR_ADC_ADJ_ADC_IB_DAC2_ADJ field. */
42391 #define XCVR_RD_ADC_ADJ_ADC_IB_DAC2_ADJ(base) ((XCVR_ADC_ADJ_REG(base) & XCVR_ADC_ADJ_ADC_IB_DAC2_ADJ_MASK) >> XCVR_ADC_ADJ_ADC_IB_DAC2_ADJ_SHIFT)
42392 #define XCVR_BRD_ADC_ADJ_ADC_IB_DAC2_ADJ(base) (BME_UBFX32(&XCVR_ADC_ADJ_REG(base), XCVR_ADC_ADJ_ADC_IB_DAC2_ADJ_SHIFT, XCVR_ADC_ADJ_ADC_IB_DAC2_ADJ_WIDTH))
42393 
42394 /*! @brief Set the ADC_IB_DAC2_ADJ field to a new value. */
42395 #define XCVR_WR_ADC_ADJ_ADC_IB_DAC2_ADJ(base, value) (XCVR_RMW_ADC_ADJ(base, XCVR_ADC_ADJ_ADC_IB_DAC2_ADJ_MASK, XCVR_ADC_ADJ_ADC_IB_DAC2_ADJ(value)))
42396 #define XCVR_BWR_ADC_ADJ_ADC_IB_DAC2_ADJ(base, value) (BME_BFI32(&XCVR_ADC_ADJ_REG(base), ((uint32_t)(value) << XCVR_ADC_ADJ_ADC_IB_DAC2_ADJ_SHIFT), XCVR_ADC_ADJ_ADC_IB_DAC2_ADJ_SHIFT, XCVR_ADC_ADJ_ADC_IB_DAC2_ADJ_WIDTH))
42397 /*@}*/
42398 
42399 /*!
42400  * @name Register XCVR_ADC_ADJ, field ADC_IB_FLSH_ADJ[26:24] (RW)
42401  *
42402  * Adjusts the quantizer preamplifier current plus/minus 30 percent. Default
42403  * setting is 0b011.
42404  */
42405 /*@{*/
42406 /*! @brief Read current value of the XCVR_ADC_ADJ_ADC_IB_FLSH_ADJ field. */
42407 #define XCVR_RD_ADC_ADJ_ADC_IB_FLSH_ADJ(base) ((XCVR_ADC_ADJ_REG(base) & XCVR_ADC_ADJ_ADC_IB_FLSH_ADJ_MASK) >> XCVR_ADC_ADJ_ADC_IB_FLSH_ADJ_SHIFT)
42408 #define XCVR_BRD_ADC_ADJ_ADC_IB_FLSH_ADJ(base) (BME_UBFX32(&XCVR_ADC_ADJ_REG(base), XCVR_ADC_ADJ_ADC_IB_FLSH_ADJ_SHIFT, XCVR_ADC_ADJ_ADC_IB_FLSH_ADJ_WIDTH))
42409 
42410 /*! @brief Set the ADC_IB_FLSH_ADJ field to a new value. */
42411 #define XCVR_WR_ADC_ADJ_ADC_IB_FLSH_ADJ(base, value) (XCVR_RMW_ADC_ADJ(base, XCVR_ADC_ADJ_ADC_IB_FLSH_ADJ_MASK, XCVR_ADC_ADJ_ADC_IB_FLSH_ADJ(value)))
42412 #define XCVR_BWR_ADC_ADJ_ADC_IB_FLSH_ADJ(base, value) (BME_BFI32(&XCVR_ADC_ADJ_REG(base), ((uint32_t)(value) << XCVR_ADC_ADJ_ADC_IB_FLSH_ADJ_SHIFT), XCVR_ADC_ADJ_ADC_IB_FLSH_ADJ_SHIFT, XCVR_ADC_ADJ_ADC_IB_FLSH_ADJ_WIDTH))
42413 /*@}*/
42414 
42415 /*!
42416  * @name Register XCVR_ADC_ADJ, field ADC_FLSH_RES_ADJ[30:28] (RW)
42417  *
42418  * Allows to adjust the value of the resistor ladder that is used to generate
42419  * the reference voltages for the quantizer. The defualt value is 100
42420  */
42421 /*@{*/
42422 /*! @brief Read current value of the XCVR_ADC_ADJ_ADC_FLSH_RES_ADJ field. */
42423 #define XCVR_RD_ADC_ADJ_ADC_FLSH_RES_ADJ(base) ((XCVR_ADC_ADJ_REG(base) & XCVR_ADC_ADJ_ADC_FLSH_RES_ADJ_MASK) >> XCVR_ADC_ADJ_ADC_FLSH_RES_ADJ_SHIFT)
42424 #define XCVR_BRD_ADC_ADJ_ADC_FLSH_RES_ADJ(base) (BME_UBFX32(&XCVR_ADC_ADJ_REG(base), XCVR_ADC_ADJ_ADC_FLSH_RES_ADJ_SHIFT, XCVR_ADC_ADJ_ADC_FLSH_RES_ADJ_WIDTH))
42425 
42426 /*! @brief Set the ADC_FLSH_RES_ADJ field to a new value. */
42427 #define XCVR_WR_ADC_ADJ_ADC_FLSH_RES_ADJ(base, value) (XCVR_RMW_ADC_ADJ(base, XCVR_ADC_ADJ_ADC_FLSH_RES_ADJ_MASK, XCVR_ADC_ADJ_ADC_FLSH_RES_ADJ(value)))
42428 #define XCVR_BWR_ADC_ADJ_ADC_FLSH_RES_ADJ(base, value) (BME_BFI32(&XCVR_ADC_ADJ_REG(base), ((uint32_t)(value) << XCVR_ADC_ADJ_ADC_FLSH_RES_ADJ_SHIFT), XCVR_ADC_ADJ_ADC_FLSH_RES_ADJ_SHIFT, XCVR_ADC_ADJ_ADC_FLSH_RES_ADJ_WIDTH))
42429 /*@}*/
42430 
42431 /*******************************************************************************
42432  * XCVR_ADC_REGS - ADC Regulators
42433  ******************************************************************************/
42434 
42435 /*!
42436  * @brief XCVR_ADC_REGS - ADC Regulators (RW)
42437  *
42438  * Reset value: 0x00000000U
42439  */
42440 /*!
42441  * @name Constants and macros for entire XCVR_ADC_REGS register
42442  */
42443 /*@{*/
42444 #define XCVR_RD_ADC_REGS(base)   (XCVR_ADC_REGS_REG(base))
42445 #define XCVR_WR_ADC_REGS(base, value) (XCVR_ADC_REGS_REG(base) = (value))
42446 #define XCVR_RMW_ADC_REGS(base, mask, value) (XCVR_WR_ADC_REGS(base, (XCVR_RD_ADC_REGS(base) & ~(mask)) | (value)))
42447 #define XCVR_SET_ADC_REGS(base, value) (BME_OR32(&XCVR_ADC_REGS_REG(base), (uint32_t)(value)))
42448 #define XCVR_CLR_ADC_REGS(base, value) (BME_AND32(&XCVR_ADC_REGS_REG(base), (uint32_t)(~(value))))
42449 #define XCVR_TOG_ADC_REGS(base, value) (BME_XOR32(&XCVR_ADC_REGS_REG(base), (uint32_t)(value)))
42450 /*@}*/
42451 
42452 /*
42453  * Constants & macros for individual XCVR_ADC_REGS bitfields
42454  */
42455 
42456 /*!
42457  * @name Register XCVR_ADC_REGS, field ADC_ANA_REG_SUPPLY[3:0] (RW)
42458  *
42459  * Regulator trim bits to change the output voltage from 1.05 to 1.4V
42460  *
42461  * Values:
42462  * - 0b0000 - 1.2V
42463  * - 0b0001 - 1.05V
42464  * - 0b0010 - 1.275V
42465  * - 0b0011 - 1.3V
42466  */
42467 /*@{*/
42468 /*! @brief Read current value of the XCVR_ADC_REGS_ADC_ANA_REG_SUPPLY field. */
42469 #define XCVR_RD_ADC_REGS_ADC_ANA_REG_SUPPLY(base) ((XCVR_ADC_REGS_REG(base) & XCVR_ADC_REGS_ADC_ANA_REG_SUPPLY_MASK) >> XCVR_ADC_REGS_ADC_ANA_REG_SUPPLY_SHIFT)
42470 #define XCVR_BRD_ADC_REGS_ADC_ANA_REG_SUPPLY(base) (BME_UBFX32(&XCVR_ADC_REGS_REG(base), XCVR_ADC_REGS_ADC_ANA_REG_SUPPLY_SHIFT, XCVR_ADC_REGS_ADC_ANA_REG_SUPPLY_WIDTH))
42471 
42472 /*! @brief Set the ADC_ANA_REG_SUPPLY field to a new value. */
42473 #define XCVR_WR_ADC_REGS_ADC_ANA_REG_SUPPLY(base, value) (XCVR_RMW_ADC_REGS(base, XCVR_ADC_REGS_ADC_ANA_REG_SUPPLY_MASK, XCVR_ADC_REGS_ADC_ANA_REG_SUPPLY(value)))
42474 #define XCVR_BWR_ADC_REGS_ADC_ANA_REG_SUPPLY(base, value) (BME_BFI32(&XCVR_ADC_REGS_REG(base), ((uint32_t)(value) << XCVR_ADC_REGS_ADC_ANA_REG_SUPPLY_SHIFT), XCVR_ADC_REGS_ADC_ANA_REG_SUPPLY_SHIFT, XCVR_ADC_REGS_ADC_ANA_REG_SUPPLY_WIDTH))
42475 /*@}*/
42476 
42477 /*!
42478  * @name Register XCVR_ADC_REGS, field ADC_REG_DIG_SUPPLY[7:4] (RW)
42479  *
42480  * Regulator trim bits to change the output voltage from 1.05 to 1.4V
42481  *
42482  * Values:
42483  * - 0b0000 - 1.2V
42484  * - 0b0001 - 1.05V
42485  * - 0b0010 - 1.275V
42486  * - 0b0011 - 1.3V
42487  */
42488 /*@{*/
42489 /*! @brief Read current value of the XCVR_ADC_REGS_ADC_REG_DIG_SUPPLY field. */
42490 #define XCVR_RD_ADC_REGS_ADC_REG_DIG_SUPPLY(base) ((XCVR_ADC_REGS_REG(base) & XCVR_ADC_REGS_ADC_REG_DIG_SUPPLY_MASK) >> XCVR_ADC_REGS_ADC_REG_DIG_SUPPLY_SHIFT)
42491 #define XCVR_BRD_ADC_REGS_ADC_REG_DIG_SUPPLY(base) (BME_UBFX32(&XCVR_ADC_REGS_REG(base), XCVR_ADC_REGS_ADC_REG_DIG_SUPPLY_SHIFT, XCVR_ADC_REGS_ADC_REG_DIG_SUPPLY_WIDTH))
42492 
42493 /*! @brief Set the ADC_REG_DIG_SUPPLY field to a new value. */
42494 #define XCVR_WR_ADC_REGS_ADC_REG_DIG_SUPPLY(base, value) (XCVR_RMW_ADC_REGS(base, XCVR_ADC_REGS_ADC_REG_DIG_SUPPLY_MASK, XCVR_ADC_REGS_ADC_REG_DIG_SUPPLY(value)))
42495 #define XCVR_BWR_ADC_REGS_ADC_REG_DIG_SUPPLY(base, value) (BME_BFI32(&XCVR_ADC_REGS_REG(base), ((uint32_t)(value) << XCVR_ADC_REGS_ADC_REG_DIG_SUPPLY_SHIFT), XCVR_ADC_REGS_ADC_REG_DIG_SUPPLY_SHIFT, XCVR_ADC_REGS_ADC_REG_DIG_SUPPLY_WIDTH))
42496 /*@}*/
42497 
42498 /*!
42499  * @name Register XCVR_ADC_REGS, field ADC_ANA_REG_BYPASS_ON[8] (RW)
42500  *
42501  * This register bit determines if the regulator is in bypass mode. When in
42502  * bypass mode, the external voltage applied to the input of the regulator is
42503  * presented at the regulator output.
42504  */
42505 /*@{*/
42506 /*! @brief Read current value of the XCVR_ADC_REGS_ADC_ANA_REG_BYPASS_ON field. */
42507 #define XCVR_RD_ADC_REGS_ADC_ANA_REG_BYPASS_ON(base) ((XCVR_ADC_REGS_REG(base) & XCVR_ADC_REGS_ADC_ANA_REG_BYPASS_ON_MASK) >> XCVR_ADC_REGS_ADC_ANA_REG_BYPASS_ON_SHIFT)
42508 #define XCVR_BRD_ADC_REGS_ADC_ANA_REG_BYPASS_ON(base) (BME_UBFX32(&XCVR_ADC_REGS_REG(base), XCVR_ADC_REGS_ADC_ANA_REG_BYPASS_ON_SHIFT, XCVR_ADC_REGS_ADC_ANA_REG_BYPASS_ON_WIDTH))
42509 
42510 /*! @brief Set the ADC_ANA_REG_BYPASS_ON field to a new value. */
42511 #define XCVR_WR_ADC_REGS_ADC_ANA_REG_BYPASS_ON(base, value) (XCVR_RMW_ADC_REGS(base, XCVR_ADC_REGS_ADC_ANA_REG_BYPASS_ON_MASK, XCVR_ADC_REGS_ADC_ANA_REG_BYPASS_ON(value)))
42512 #define XCVR_BWR_ADC_REGS_ADC_ANA_REG_BYPASS_ON(base, value) (BME_BFI32(&XCVR_ADC_REGS_REG(base), ((uint32_t)(value) << XCVR_ADC_REGS_ADC_ANA_REG_BYPASS_ON_SHIFT), XCVR_ADC_REGS_ADC_ANA_REG_BYPASS_ON_SHIFT, XCVR_ADC_REGS_ADC_ANA_REG_BYPASS_ON_WIDTH))
42513 /*@}*/
42514 
42515 /*!
42516  * @name Register XCVR_ADC_REGS, field ADC_DIG_REG_BYPASS_ON[9] (RW)
42517  *
42518  * This register bit determines if the regulator is in bypass mode. When in
42519  * bypass mode, the external voltage applied to the input of the regulator is
42520  * presented at the regulator output.
42521  */
42522 /*@{*/
42523 /*! @brief Read current value of the XCVR_ADC_REGS_ADC_DIG_REG_BYPASS_ON field. */
42524 #define XCVR_RD_ADC_REGS_ADC_DIG_REG_BYPASS_ON(base) ((XCVR_ADC_REGS_REG(base) & XCVR_ADC_REGS_ADC_DIG_REG_BYPASS_ON_MASK) >> XCVR_ADC_REGS_ADC_DIG_REG_BYPASS_ON_SHIFT)
42525 #define XCVR_BRD_ADC_REGS_ADC_DIG_REG_BYPASS_ON(base) (BME_UBFX32(&XCVR_ADC_REGS_REG(base), XCVR_ADC_REGS_ADC_DIG_REG_BYPASS_ON_SHIFT, XCVR_ADC_REGS_ADC_DIG_REG_BYPASS_ON_WIDTH))
42526 
42527 /*! @brief Set the ADC_DIG_REG_BYPASS_ON field to a new value. */
42528 #define XCVR_WR_ADC_REGS_ADC_DIG_REG_BYPASS_ON(base, value) (XCVR_RMW_ADC_REGS(base, XCVR_ADC_REGS_ADC_DIG_REG_BYPASS_ON_MASK, XCVR_ADC_REGS_ADC_DIG_REG_BYPASS_ON(value)))
42529 #define XCVR_BWR_ADC_REGS_ADC_DIG_REG_BYPASS_ON(base, value) (BME_BFI32(&XCVR_ADC_REGS_REG(base), ((uint32_t)(value) << XCVR_ADC_REGS_ADC_DIG_REG_BYPASS_ON_SHIFT), XCVR_ADC_REGS_ADC_DIG_REG_BYPASS_ON_SHIFT, XCVR_ADC_REGS_ADC_DIG_REG_BYPASS_ON_WIDTH))
42530 /*@}*/
42531 
42532 /*!
42533  * @name Register XCVR_ADC_REGS, field ADC_VCMREF_BYPASS_ON[15] (RW)
42534  *
42535  * Allows to use an external 0.6V reference instead of the internally generated
42536  * 0.6V. This mode should be used only in combination with analog test mode for
42537  * the ADC enabled and when supplying an external 0.6V reference voltage through
42538  * the test mux.This function is not used in this version of the chip
42539  */
42540 /*@{*/
42541 /*! @brief Read current value of the XCVR_ADC_REGS_ADC_VCMREF_BYPASS_ON field. */
42542 #define XCVR_RD_ADC_REGS_ADC_VCMREF_BYPASS_ON(base) ((XCVR_ADC_REGS_REG(base) & XCVR_ADC_REGS_ADC_VCMREF_BYPASS_ON_MASK) >> XCVR_ADC_REGS_ADC_VCMREF_BYPASS_ON_SHIFT)
42543 #define XCVR_BRD_ADC_REGS_ADC_VCMREF_BYPASS_ON(base) (BME_UBFX32(&XCVR_ADC_REGS_REG(base), XCVR_ADC_REGS_ADC_VCMREF_BYPASS_ON_SHIFT, XCVR_ADC_REGS_ADC_VCMREF_BYPASS_ON_WIDTH))
42544 
42545 /*! @brief Set the ADC_VCMREF_BYPASS_ON field to a new value. */
42546 #define XCVR_WR_ADC_REGS_ADC_VCMREF_BYPASS_ON(base, value) (XCVR_RMW_ADC_REGS(base, XCVR_ADC_REGS_ADC_VCMREF_BYPASS_ON_MASK, XCVR_ADC_REGS_ADC_VCMREF_BYPASS_ON(value)))
42547 #define XCVR_BWR_ADC_REGS_ADC_VCMREF_BYPASS_ON(base, value) (BME_BFI32(&XCVR_ADC_REGS_REG(base), ((uint32_t)(value) << XCVR_ADC_REGS_ADC_VCMREF_BYPASS_ON_SHIFT), XCVR_ADC_REGS_ADC_VCMREF_BYPASS_ON_SHIFT, XCVR_ADC_REGS_ADC_VCMREF_BYPASS_ON_WIDTH))
42548 /*@}*/
42549 
42550 /*!
42551  * @name Register XCVR_ADC_REGS, field ADC_INTERNAL_IREF_BYPASS_ON[17] (RW)
42552  *
42553  * Bypass the internally generated 5uA reference current that is used for the
42554  * ADC to generate all the other reference currents for the ADC and use an external
42555  * reference current. This mode should be used only in combination with analog
42556  * test mode for the ADC enabled and when supplying an external current reference
42557  * through the test mux. This function is not used in this version of the chip
42558  */
42559 /*@{*/
42560 /*! @brief Read current value of the XCVR_ADC_REGS_ADC_INTERNAL_IREF_BYPASS_ON field. */
42561 #define XCVR_RD_ADC_REGS_ADC_INTERNAL_IREF_BYPASS_ON(base) ((XCVR_ADC_REGS_REG(base) & XCVR_ADC_REGS_ADC_INTERNAL_IREF_BYPASS_ON_MASK) >> XCVR_ADC_REGS_ADC_INTERNAL_IREF_BYPASS_ON_SHIFT)
42562 #define XCVR_BRD_ADC_REGS_ADC_INTERNAL_IREF_BYPASS_ON(base) (BME_UBFX32(&XCVR_ADC_REGS_REG(base), XCVR_ADC_REGS_ADC_INTERNAL_IREF_BYPASS_ON_SHIFT, XCVR_ADC_REGS_ADC_INTERNAL_IREF_BYPASS_ON_WIDTH))
42563 
42564 /*! @brief Set the ADC_INTERNAL_IREF_BYPASS_ON field to a new value. */
42565 #define XCVR_WR_ADC_REGS_ADC_INTERNAL_IREF_BYPASS_ON(base, value) (XCVR_RMW_ADC_REGS(base, XCVR_ADC_REGS_ADC_INTERNAL_IREF_BYPASS_ON_MASK, XCVR_ADC_REGS_ADC_INTERNAL_IREF_BYPASS_ON(value)))
42566 #define XCVR_BWR_ADC_REGS_ADC_INTERNAL_IREF_BYPASS_ON(base, value) (BME_BFI32(&XCVR_ADC_REGS_REG(base), ((uint32_t)(value) << XCVR_ADC_REGS_ADC_INTERNAL_IREF_BYPASS_ON_SHIFT), XCVR_ADC_REGS_ADC_INTERNAL_IREF_BYPASS_ON_SHIFT, XCVR_ADC_REGS_ADC_INTERNAL_IREF_BYPASS_ON_WIDTH))
42567 /*@}*/
42568 
42569 /*******************************************************************************
42570  * XCVR_ADC_TRIMS - ADC Regulator Trims
42571  ******************************************************************************/
42572 
42573 /*!
42574  * @brief XCVR_ADC_TRIMS - ADC Regulator Trims (RW)
42575  *
42576  * Reset value: 0x00000444U
42577  */
42578 /*!
42579  * @name Constants and macros for entire XCVR_ADC_TRIMS register
42580  */
42581 /*@{*/
42582 #define XCVR_RD_ADC_TRIMS(base)  (XCVR_ADC_TRIMS_REG(base))
42583 #define XCVR_WR_ADC_TRIMS(base, value) (XCVR_ADC_TRIMS_REG(base) = (value))
42584 #define XCVR_RMW_ADC_TRIMS(base, mask, value) (XCVR_WR_ADC_TRIMS(base, (XCVR_RD_ADC_TRIMS(base) & ~(mask)) | (value)))
42585 #define XCVR_SET_ADC_TRIMS(base, value) (BME_OR32(&XCVR_ADC_TRIMS_REG(base), (uint32_t)(value)))
42586 #define XCVR_CLR_ADC_TRIMS(base, value) (BME_AND32(&XCVR_ADC_TRIMS_REG(base), (uint32_t)(~(value))))
42587 #define XCVR_TOG_ADC_TRIMS(base, value) (BME_XOR32(&XCVR_ADC_TRIMS_REG(base), (uint32_t)(value)))
42588 /*@}*/
42589 
42590 /*
42591  * Constants & macros for individual XCVR_ADC_TRIMS bitfields
42592  */
42593 
42594 /*!
42595  * @name Register XCVR_ADC_TRIMS, field ADC_IREF_OPAMPS_RES_TRIM[2:0] (RW)
42596  *
42597  * This allows to trim the resistor value used to generate the reference current
42598  * for the integrator's operational amplifiers. The resistor values can be
42599  * trimmed by plus/minus 15 percent.
42600  */
42601 /*@{*/
42602 /*! @brief Read current value of the XCVR_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM field. */
42603 #define XCVR_RD_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM(base) ((XCVR_ADC_TRIMS_REG(base) & XCVR_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM_MASK) >> XCVR_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM_SHIFT)
42604 #define XCVR_BRD_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM(base) (BME_UBFX32(&XCVR_ADC_TRIMS_REG(base), XCVR_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM_SHIFT, XCVR_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM_WIDTH))
42605 
42606 /*! @brief Set the ADC_IREF_OPAMPS_RES_TRIM field to a new value. */
42607 #define XCVR_WR_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM(base, value) (XCVR_RMW_ADC_TRIMS(base, XCVR_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM_MASK, XCVR_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM(value)))
42608 #define XCVR_BWR_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM(base, value) (BME_BFI32(&XCVR_ADC_TRIMS_REG(base), ((uint32_t)(value) << XCVR_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM_SHIFT), XCVR_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM_SHIFT, XCVR_ADC_TRIMS_ADC_IREF_OPAMPS_RES_TRIM_WIDTH))
42609 /*@}*/
42610 
42611 /*!
42612  * @name Register XCVR_ADC_TRIMS, field ADC_IREF_FLSH_RES_TRIM[6:4] (RW)
42613  *
42614  * This allows to trim the resistor value used to generate the reference current
42615  * for the quantizer. The resistor values can be trimmed by +/-15%.
42616  */
42617 /*@{*/
42618 /*! @brief Read current value of the XCVR_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM field. */
42619 #define XCVR_RD_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM(base) ((XCVR_ADC_TRIMS_REG(base) & XCVR_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM_MASK) >> XCVR_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM_SHIFT)
42620 #define XCVR_BRD_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM(base) (BME_UBFX32(&XCVR_ADC_TRIMS_REG(base), XCVR_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM_SHIFT, XCVR_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM_WIDTH))
42621 
42622 /*! @brief Set the ADC_IREF_FLSH_RES_TRIM field to a new value. */
42623 #define XCVR_WR_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM(base, value) (XCVR_RMW_ADC_TRIMS(base, XCVR_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM_MASK, XCVR_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM(value)))
42624 #define XCVR_BWR_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM(base, value) (BME_BFI32(&XCVR_ADC_TRIMS_REG(base), ((uint32_t)(value) << XCVR_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM_SHIFT), XCVR_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM_SHIFT, XCVR_ADC_TRIMS_ADC_IREF_FLSH_RES_TRIM_WIDTH))
42625 /*@}*/
42626 
42627 /*!
42628  * @name Register XCVR_ADC_TRIMS, field ADC_VCM_TRIM[10:8] (RW)
42629  *
42630  * This allows to trim the resistor value used to generate the reference current
42631  * for the DACs. These bits are mislabeled and should be called
42632  * ADC_IREF_DAC_RES_TRIM. The resistor values can be trimmed by +/-15%.
42633  */
42634 /*@{*/
42635 /*! @brief Read current value of the XCVR_ADC_TRIMS_ADC_VCM_TRIM field. */
42636 #define XCVR_RD_ADC_TRIMS_ADC_VCM_TRIM(base) ((XCVR_ADC_TRIMS_REG(base) & XCVR_ADC_TRIMS_ADC_VCM_TRIM_MASK) >> XCVR_ADC_TRIMS_ADC_VCM_TRIM_SHIFT)
42637 #define XCVR_BRD_ADC_TRIMS_ADC_VCM_TRIM(base) (BME_UBFX32(&XCVR_ADC_TRIMS_REG(base), XCVR_ADC_TRIMS_ADC_VCM_TRIM_SHIFT, XCVR_ADC_TRIMS_ADC_VCM_TRIM_WIDTH))
42638 
42639 /*! @brief Set the ADC_VCM_TRIM field to a new value. */
42640 #define XCVR_WR_ADC_TRIMS_ADC_VCM_TRIM(base, value) (XCVR_RMW_ADC_TRIMS(base, XCVR_ADC_TRIMS_ADC_VCM_TRIM_MASK, XCVR_ADC_TRIMS_ADC_VCM_TRIM(value)))
42641 #define XCVR_BWR_ADC_TRIMS_ADC_VCM_TRIM(base, value) (BME_BFI32(&XCVR_ADC_TRIMS_REG(base), ((uint32_t)(value) << XCVR_ADC_TRIMS_ADC_VCM_TRIM_SHIFT), XCVR_ADC_TRIMS_ADC_VCM_TRIM_SHIFT, XCVR_ADC_TRIMS_ADC_VCM_TRIM_WIDTH))
42642 /*@}*/
42643 
42644 /*******************************************************************************
42645  * XCVR_ADC_TEST_CTRL - ADC Test Control
42646  ******************************************************************************/
42647 
42648 /*!
42649  * @brief XCVR_ADC_TEST_CTRL - ADC Test Control (RW)
42650  *
42651  * Reset value: 0x00000000U
42652  */
42653 /*!
42654  * @name Constants and macros for entire XCVR_ADC_TEST_CTRL register
42655  */
42656 /*@{*/
42657 #define XCVR_RD_ADC_TEST_CTRL(base) (XCVR_ADC_TEST_CTRL_REG(base))
42658 #define XCVR_WR_ADC_TEST_CTRL(base, value) (XCVR_ADC_TEST_CTRL_REG(base) = (value))
42659 #define XCVR_RMW_ADC_TEST_CTRL(base, mask, value) (XCVR_WR_ADC_TEST_CTRL(base, (XCVR_RD_ADC_TEST_CTRL(base) & ~(mask)) | (value)))
42660 #define XCVR_SET_ADC_TEST_CTRL(base, value) (BME_OR32(&XCVR_ADC_TEST_CTRL_REG(base), (uint32_t)(value)))
42661 #define XCVR_CLR_ADC_TEST_CTRL(base, value) (BME_AND32(&XCVR_ADC_TEST_CTRL_REG(base), (uint32_t)(~(value))))
42662 #define XCVR_TOG_ADC_TEST_CTRL(base, value) (BME_XOR32(&XCVR_ADC_TEST_CTRL_REG(base), (uint32_t)(value)))
42663 /*@}*/
42664 
42665 /*
42666  * Constants & macros for individual XCVR_ADC_TEST_CTRL bitfields
42667  */
42668 
42669 /*!
42670  * @name Register XCVR_ADC_TEST_CTRL, field ADC_ATST_SEL[4:0] (RW)
42671  *
42672  * Allows to slect between the different ADC analog test modes.All other values
42673  * are reserved.
42674  *
42675  * Values:
42676  * - 0b00000 - Inject 5uA refrence current on ATST0 ,Inject 0.6V reference
42677  *     voltage on ATST1
42678  * - 0b00001 - Monitor Flash refrence currents on ATST3
42679  */
42680 /*@{*/
42681 /*! @brief Read current value of the XCVR_ADC_TEST_CTRL_ADC_ATST_SEL field. */
42682 #define XCVR_RD_ADC_TEST_CTRL_ADC_ATST_SEL(base) ((XCVR_ADC_TEST_CTRL_REG(base) & XCVR_ADC_TEST_CTRL_ADC_ATST_SEL_MASK) >> XCVR_ADC_TEST_CTRL_ADC_ATST_SEL_SHIFT)
42683 #define XCVR_BRD_ADC_TEST_CTRL_ADC_ATST_SEL(base) (BME_UBFX32(&XCVR_ADC_TEST_CTRL_REG(base), XCVR_ADC_TEST_CTRL_ADC_ATST_SEL_SHIFT, XCVR_ADC_TEST_CTRL_ADC_ATST_SEL_WIDTH))
42684 
42685 /*! @brief Set the ADC_ATST_SEL field to a new value. */
42686 #define XCVR_WR_ADC_TEST_CTRL_ADC_ATST_SEL(base, value) (XCVR_RMW_ADC_TEST_CTRL(base, XCVR_ADC_TEST_CTRL_ADC_ATST_SEL_MASK, XCVR_ADC_TEST_CTRL_ADC_ATST_SEL(value)))
42687 #define XCVR_BWR_ADC_TEST_CTRL_ADC_ATST_SEL(base, value) (BME_BFI32(&XCVR_ADC_TEST_CTRL_REG(base), ((uint32_t)(value) << XCVR_ADC_TEST_CTRL_ADC_ATST_SEL_SHIFT), XCVR_ADC_TEST_CTRL_ADC_ATST_SEL_SHIFT, XCVR_ADC_TEST_CTRL_ADC_ATST_SEL_WIDTH))
42688 /*@}*/
42689 
42690 /*!
42691  * @name Register XCVR_ADC_TEST_CTRL, field ADC_DIG_REG_ATST_SEL[9:8] (RW)
42692  *
42693  * These bits control the what internal regualtor signals are connected to the
42694  * ATST bus. register setting ATST0 00 No Connect 01 vout 10 vin feedback 11 vbias
42695  */
42696 /*@{*/
42697 /*! @brief Read current value of the XCVR_ADC_TEST_CTRL_ADC_DIG_REG_ATST_SEL field. */
42698 #define XCVR_RD_ADC_TEST_CTRL_ADC_DIG_REG_ATST_SEL(base) ((XCVR_ADC_TEST_CTRL_REG(base) & XCVR_ADC_TEST_CTRL_ADC_DIG_REG_ATST_SEL_MASK) >> XCVR_ADC_TEST_CTRL_ADC_DIG_REG_ATST_SEL_SHIFT)
42699 #define XCVR_BRD_ADC_TEST_CTRL_ADC_DIG_REG_ATST_SEL(base) (BME_UBFX32(&XCVR_ADC_TEST_CTRL_REG(base), XCVR_ADC_TEST_CTRL_ADC_DIG_REG_ATST_SEL_SHIFT, XCVR_ADC_TEST_CTRL_ADC_DIG_REG_ATST_SEL_WIDTH))
42700 
42701 /*! @brief Set the ADC_DIG_REG_ATST_SEL field to a new value. */
42702 #define XCVR_WR_ADC_TEST_CTRL_ADC_DIG_REG_ATST_SEL(base, value) (XCVR_RMW_ADC_TEST_CTRL(base, XCVR_ADC_TEST_CTRL_ADC_DIG_REG_ATST_SEL_MASK, XCVR_ADC_TEST_CTRL_ADC_DIG_REG_ATST_SEL(value)))
42703 #define XCVR_BWR_ADC_TEST_CTRL_ADC_DIG_REG_ATST_SEL(base, value) (BME_BFI32(&XCVR_ADC_TEST_CTRL_REG(base), ((uint32_t)(value) << XCVR_ADC_TEST_CTRL_ADC_DIG_REG_ATST_SEL_SHIFT), XCVR_ADC_TEST_CTRL_ADC_DIG_REG_ATST_SEL_SHIFT, XCVR_ADC_TEST_CTRL_ADC_DIG_REG_ATST_SEL_WIDTH))
42704 /*@}*/
42705 
42706 /*!
42707  * @name Register XCVR_ADC_TEST_CTRL, field ADC_ANA_REG_ATST_SEL[13:12] (RW)
42708  *
42709  * These bits control what internal signals are connected to the ATST bus.
42710  * register setting ATST0 00 No Connect 01 vout 10 vin feedback 11 vbias
42711  */
42712 /*@{*/
42713 /*! @brief Read current value of the XCVR_ADC_TEST_CTRL_ADC_ANA_REG_ATST_SEL field. */
42714 #define XCVR_RD_ADC_TEST_CTRL_ADC_ANA_REG_ATST_SEL(base) ((XCVR_ADC_TEST_CTRL_REG(base) & XCVR_ADC_TEST_CTRL_ADC_ANA_REG_ATST_SEL_MASK) >> XCVR_ADC_TEST_CTRL_ADC_ANA_REG_ATST_SEL_SHIFT)
42715 #define XCVR_BRD_ADC_TEST_CTRL_ADC_ANA_REG_ATST_SEL(base) (BME_UBFX32(&XCVR_ADC_TEST_CTRL_REG(base), XCVR_ADC_TEST_CTRL_ADC_ANA_REG_ATST_SEL_SHIFT, XCVR_ADC_TEST_CTRL_ADC_ANA_REG_ATST_SEL_WIDTH))
42716 
42717 /*! @brief Set the ADC_ANA_REG_ATST_SEL field to a new value. */
42718 #define XCVR_WR_ADC_TEST_CTRL_ADC_ANA_REG_ATST_SEL(base, value) (XCVR_RMW_ADC_TEST_CTRL(base, XCVR_ADC_TEST_CTRL_ADC_ANA_REG_ATST_SEL_MASK, XCVR_ADC_TEST_CTRL_ADC_ANA_REG_ATST_SEL(value)))
42719 #define XCVR_BWR_ADC_TEST_CTRL_ADC_ANA_REG_ATST_SEL(base, value) (BME_BFI32(&XCVR_ADC_TEST_CTRL_REG(base), ((uint32_t)(value) << XCVR_ADC_TEST_CTRL_ADC_ANA_REG_ATST_SEL_SHIFT), XCVR_ADC_TEST_CTRL_ADC_ANA_REG_ATST_SEL_SHIFT, XCVR_ADC_TEST_CTRL_ADC_ANA_REG_ATST_SEL_WIDTH))
42720 /*@}*/
42721 
42722 /*!
42723  * @name Register XCVR_ADC_TEST_CTRL, field DCOC_ALPHA_RADIUS_GS_IDX[26:24] (RW)
42724  *
42725  * DCOC Alpha-R Scaling. This has the same definition as DCOC_ALPHA_RADIUS_IDX.
42726  * The tracking estimator will switch from DCOC_ALPHA_RADIUS_IDX to
42727  * DCOC_ALPHA_RADIUS_GS_IDX at the time specified by the DCOC_TRK_EST_GS_CNT.
42728  *
42729  * Values:
42730  * - 0b000 - 1
42731  * - 0b001 - 1/2
42732  * - 0b010 - 1/4
42733  * - 0b011 - 1/8
42734  * - 0b100 - 1/16
42735  * - 0b101 - 1/32
42736  * - 0b110 - 1/64
42737  * - 0b111 - Reserved
42738  */
42739 /*@{*/
42740 /*! @brief Read current value of the XCVR_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX field. */
42741 #define XCVR_RD_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX(base) ((XCVR_ADC_TEST_CTRL_REG(base) & XCVR_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX_MASK) >> XCVR_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX_SHIFT)
42742 #define XCVR_BRD_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX(base) (BME_UBFX32(&XCVR_ADC_TEST_CTRL_REG(base), XCVR_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX_SHIFT, XCVR_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX_WIDTH))
42743 
42744 /*! @brief Set the DCOC_ALPHA_RADIUS_GS_IDX field to a new value. */
42745 #define XCVR_WR_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX(base, value) (XCVR_RMW_ADC_TEST_CTRL(base, XCVR_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX_MASK, XCVR_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX(value)))
42746 #define XCVR_BWR_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX(base, value) (BME_BFI32(&XCVR_ADC_TEST_CTRL_REG(base), ((uint32_t)(value) << XCVR_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX_SHIFT), XCVR_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX_SHIFT, XCVR_ADC_TEST_CTRL_DCOC_ALPHA_RADIUS_GS_IDX_WIDTH))
42747 /*@}*/
42748 
42749 /*!
42750  * @name Register XCVR_ADC_TEST_CTRL, field ADC_SPARE3[27] (RW)
42751  *
42752  * Spare Bit for future use
42753  */
42754 /*@{*/
42755 /*! @brief Read current value of the XCVR_ADC_TEST_CTRL_ADC_SPARE3 field. */
42756 #define XCVR_RD_ADC_TEST_CTRL_ADC_SPARE3(base) ((XCVR_ADC_TEST_CTRL_REG(base) & XCVR_ADC_TEST_CTRL_ADC_SPARE3_MASK) >> XCVR_ADC_TEST_CTRL_ADC_SPARE3_SHIFT)
42757 #define XCVR_BRD_ADC_TEST_CTRL_ADC_SPARE3(base) (BME_UBFX32(&XCVR_ADC_TEST_CTRL_REG(base), XCVR_ADC_TEST_CTRL_ADC_SPARE3_SHIFT, XCVR_ADC_TEST_CTRL_ADC_SPARE3_WIDTH))
42758 
42759 /*! @brief Set the ADC_SPARE3 field to a new value. */
42760 #define XCVR_WR_ADC_TEST_CTRL_ADC_SPARE3(base, value) (XCVR_RMW_ADC_TEST_CTRL(base, XCVR_ADC_TEST_CTRL_ADC_SPARE3_MASK, XCVR_ADC_TEST_CTRL_ADC_SPARE3(value)))
42761 #define XCVR_BWR_ADC_TEST_CTRL_ADC_SPARE3(base, value) (BME_BFI32(&XCVR_ADC_TEST_CTRL_REG(base), ((uint32_t)(value) << XCVR_ADC_TEST_CTRL_ADC_SPARE3_SHIFT), XCVR_ADC_TEST_CTRL_ADC_SPARE3_SHIFT, XCVR_ADC_TEST_CTRL_ADC_SPARE3_WIDTH))
42762 /*@}*/
42763 
42764 /*******************************************************************************
42765  * XCVR_BBF_CTRL - Baseband Filter Control
42766  ******************************************************************************/
42767 
42768 /*!
42769  * @brief XCVR_BBF_CTRL - Baseband Filter Control (RW)
42770  *
42771  * Reset value: 0x00000173U
42772  */
42773 /*!
42774  * @name Constants and macros for entire XCVR_BBF_CTRL register
42775  */
42776 /*@{*/
42777 #define XCVR_RD_BBF_CTRL(base)   (XCVR_BBF_CTRL_REG(base))
42778 #define XCVR_WR_BBF_CTRL(base, value) (XCVR_BBF_CTRL_REG(base) = (value))
42779 #define XCVR_RMW_BBF_CTRL(base, mask, value) (XCVR_WR_BBF_CTRL(base, (XCVR_RD_BBF_CTRL(base) & ~(mask)) | (value)))
42780 #define XCVR_SET_BBF_CTRL(base, value) (BME_OR32(&XCVR_BBF_CTRL_REG(base), (uint32_t)(value)))
42781 #define XCVR_CLR_BBF_CTRL(base, value) (BME_AND32(&XCVR_BBF_CTRL_REG(base), (uint32_t)(~(value))))
42782 #define XCVR_TOG_BBF_CTRL(base, value) (BME_XOR32(&XCVR_BBF_CTRL_REG(base), (uint32_t)(value)))
42783 /*@}*/
42784 
42785 /*
42786  * Constants & macros for individual XCVR_BBF_CTRL bitfields
42787  */
42788 
42789 /*!
42790  * @name Register XCVR_BBF_CTRL, field BBF_CAP_TUNE[3:0] (RW)
42791  *
42792  * This is programmbale capacitor values to change the corner frequency of the
42793  * first baseband filter. This bit in combination with bbf_res_tune and
42794  * tza_cap_tune determine the baseband filter response. The following table illustrates the
42795  * composite filter responces based on the bit settings tza_cap bba_cap bba_res2
42796  * f3db(KHz) 0 0 0 1180 0 0 2 1077 0 0 5 1007 0 0 7 873.1 0 2 0 1119 0 2 2 1030
42797  * 0 2 5 968 0 2 7 846.2 0 5 0 980.5 0 5 2 917.9 0 5 5 872.5 0 5 7 777.6 0 7 0
42798  * 836.8 0 7 2 795.8 0 7 5 764.3 0 7 7 695.3 2 0 0 1096 2 0 2 1009 2 0 5 949.8 2 0
42799  * 7 832.2 2 2 0 1044 2 2 2 968.6 2 2 5 915.7 2 2 7 808.3 2 5 0 924.9 2 5 2 871.2
42800  * 2 5 5 831.4 2 5 7 746.8 2 7 0 798.2 2 7 2 762.2 2 7 5 734.2 2 7 7 671.9 5 0 0
42801  * 934.5 5 0 2 875.7 5 0 5 833.6 5 0 7 745.9 5 2 0 898.9 5 2 2 846.7 5 2 5 808.5
42802  * 5 2 7 727.9 5 5 0 813.3 5 5 2 774.6 5 5 5 745 5 5 7 680 5 7 0 717.4 5 7 2
42803  * 690.4 5 7 5 669 5 7 7 619.7 7 0 0 788.5 7 0 2 750.1 7 0 5 721.3 7 0 7 658.5 7 2 0
42804  * 765 7 2 2 730.2 7 2 5 703.7 7 2 7 645.2 7 5 0 705.7 7 5 2 678.8 7 5 5 657.7 7
42805  * 5 7 609.4 7 7 0 635.6 7 7 2 616 7 7 5 600.2 7 7 7 562.6
42806  */
42807 /*@{*/
42808 /*! @brief Read current value of the XCVR_BBF_CTRL_BBF_CAP_TUNE field. */
42809 #define XCVR_RD_BBF_CTRL_BBF_CAP_TUNE(base) ((XCVR_BBF_CTRL_REG(base) & XCVR_BBF_CTRL_BBF_CAP_TUNE_MASK) >> XCVR_BBF_CTRL_BBF_CAP_TUNE_SHIFT)
42810 #define XCVR_BRD_BBF_CTRL_BBF_CAP_TUNE(base) (BME_UBFX32(&XCVR_BBF_CTRL_REG(base), XCVR_BBF_CTRL_BBF_CAP_TUNE_SHIFT, XCVR_BBF_CTRL_BBF_CAP_TUNE_WIDTH))
42811 
42812 /*! @brief Set the BBF_CAP_TUNE field to a new value. */
42813 #define XCVR_WR_BBF_CTRL_BBF_CAP_TUNE(base, value) (XCVR_RMW_BBF_CTRL(base, XCVR_BBF_CTRL_BBF_CAP_TUNE_MASK, XCVR_BBF_CTRL_BBF_CAP_TUNE(value)))
42814 #define XCVR_BWR_BBF_CTRL_BBF_CAP_TUNE(base, value) (BME_BFI32(&XCVR_BBF_CTRL_REG(base), ((uint32_t)(value) << XCVR_BBF_CTRL_BBF_CAP_TUNE_SHIFT), XCVR_BBF_CTRL_BBF_CAP_TUNE_SHIFT, XCVR_BBF_CTRL_BBF_CAP_TUNE_WIDTH))
42815 /*@}*/
42816 
42817 /*!
42818  * @name Register XCVR_BBF_CTRL, field BBF_RES_TUNE2[7:4] (RW)
42819  *
42820  * This is the programmable resistor to change the corner frquency of the
42821  * passive pole. The total f3db filter corner is determined by bbf_cap_tune and
42822  * tza_cap_tune.See the description for bbf_cap_tune BBF_CAP_TUNEBBF_CAP_TUNE for the
42823  * corner frequency values.
42824  */
42825 /*@{*/
42826 /*! @brief Read current value of the XCVR_BBF_CTRL_BBF_RES_TUNE2 field. */
42827 #define XCVR_RD_BBF_CTRL_BBF_RES_TUNE2(base) ((XCVR_BBF_CTRL_REG(base) & XCVR_BBF_CTRL_BBF_RES_TUNE2_MASK) >> XCVR_BBF_CTRL_BBF_RES_TUNE2_SHIFT)
42828 #define XCVR_BRD_BBF_CTRL_BBF_RES_TUNE2(base) (BME_UBFX32(&XCVR_BBF_CTRL_REG(base), XCVR_BBF_CTRL_BBF_RES_TUNE2_SHIFT, XCVR_BBF_CTRL_BBF_RES_TUNE2_WIDTH))
42829 
42830 /*! @brief Set the BBF_RES_TUNE2 field to a new value. */
42831 #define XCVR_WR_BBF_CTRL_BBF_RES_TUNE2(base, value) (XCVR_RMW_BBF_CTRL(base, XCVR_BBF_CTRL_BBF_RES_TUNE2_MASK, XCVR_BBF_CTRL_BBF_RES_TUNE2(value)))
42832 #define XCVR_BWR_BBF_CTRL_BBF_RES_TUNE2(base, value) (BME_BFI32(&XCVR_BBF_CTRL_REG(base), ((uint32_t)(value) << XCVR_BBF_CTRL_BBF_RES_TUNE2_SHIFT), XCVR_BBF_CTRL_BBF_RES_TUNE2_SHIFT, XCVR_BBF_CTRL_BBF_RES_TUNE2_WIDTH))
42833 /*@}*/
42834 
42835 /*!
42836  * @name Register XCVR_BBF_CTRL, field BBF_CUR_CNTL[8] (RW)
42837  *
42838  * This bit controls the current in the BBF and default is 1. When the bit is
42839  * unset the total BBF current decreases by 350uA.
42840  *
42841  * Values:
42842  * - 0b0 - Low current setting.
42843  * - 0b1 - High current setting.
42844  */
42845 /*@{*/
42846 /*! @brief Read current value of the XCVR_BBF_CTRL_BBF_CUR_CNTL field. */
42847 #define XCVR_RD_BBF_CTRL_BBF_CUR_CNTL(base) ((XCVR_BBF_CTRL_REG(base) & XCVR_BBF_CTRL_BBF_CUR_CNTL_MASK) >> XCVR_BBF_CTRL_BBF_CUR_CNTL_SHIFT)
42848 #define XCVR_BRD_BBF_CTRL_BBF_CUR_CNTL(base) (BME_UBFX32(&XCVR_BBF_CTRL_REG(base), XCVR_BBF_CTRL_BBF_CUR_CNTL_SHIFT, XCVR_BBF_CTRL_BBF_CUR_CNTL_WIDTH))
42849 
42850 /*! @brief Set the BBF_CUR_CNTL field to a new value. */
42851 #define XCVR_WR_BBF_CTRL_BBF_CUR_CNTL(base, value) (XCVR_RMW_BBF_CTRL(base, XCVR_BBF_CTRL_BBF_CUR_CNTL_MASK, XCVR_BBF_CTRL_BBF_CUR_CNTL(value)))
42852 #define XCVR_BWR_BBF_CTRL_BBF_CUR_CNTL(base, value) (BME_BFI32(&XCVR_BBF_CTRL_REG(base), ((uint32_t)(value) << XCVR_BBF_CTRL_BBF_CUR_CNTL_SHIFT), XCVR_BBF_CTRL_BBF_CUR_CNTL_SHIFT, XCVR_BBF_CTRL_BBF_CUR_CNTL_WIDTH))
42853 /*@}*/
42854 
42855 /*!
42856  * @name Register XCVR_BBF_CTRL, field BBF_DCOC_ON[9] (RW)
42857  *
42858  * Not currently connected. Was intended to enable the DCOC at the output of BBF
42859  */
42860 /*@{*/
42861 /*! @brief Read current value of the XCVR_BBF_CTRL_BBF_DCOC_ON field. */
42862 #define XCVR_RD_BBF_CTRL_BBF_DCOC_ON(base) ((XCVR_BBF_CTRL_REG(base) & XCVR_BBF_CTRL_BBF_DCOC_ON_MASK) >> XCVR_BBF_CTRL_BBF_DCOC_ON_SHIFT)
42863 #define XCVR_BRD_BBF_CTRL_BBF_DCOC_ON(base) (BME_UBFX32(&XCVR_BBF_CTRL_REG(base), XCVR_BBF_CTRL_BBF_DCOC_ON_SHIFT, XCVR_BBF_CTRL_BBF_DCOC_ON_WIDTH))
42864 
42865 /*! @brief Set the BBF_DCOC_ON field to a new value. */
42866 #define XCVR_WR_BBF_CTRL_BBF_DCOC_ON(base, value) (XCVR_RMW_BBF_CTRL(base, XCVR_BBF_CTRL_BBF_DCOC_ON_MASK, XCVR_BBF_CTRL_BBF_DCOC_ON(value)))
42867 #define XCVR_BWR_BBF_CTRL_BBF_DCOC_ON(base, value) (BME_BFI32(&XCVR_BBF_CTRL_REG(base), ((uint32_t)(value) << XCVR_BBF_CTRL_BBF_DCOC_ON_SHIFT), XCVR_BBF_CTRL_BBF_DCOC_ON_SHIFT, XCVR_BBF_CTRL_BBF_DCOC_ON_WIDTH))
42868 /*@}*/
42869 
42870 /*!
42871  * @name Register XCVR_BBF_CTRL, field BBF_TMUX_ON[11] (RW)
42872  *
42873  * This bit enables the test mode for the baseband filter block. The internal
42874  * signals are brought to the the ATST bus based on the values of the rx_atst_sel.
42875  * Refer to the description in the rx_atst_sel field.
42876  */
42877 /*@{*/
42878 /*! @brief Read current value of the XCVR_BBF_CTRL_BBF_TMUX_ON field. */
42879 #define XCVR_RD_BBF_CTRL_BBF_TMUX_ON(base) ((XCVR_BBF_CTRL_REG(base) & XCVR_BBF_CTRL_BBF_TMUX_ON_MASK) >> XCVR_BBF_CTRL_BBF_TMUX_ON_SHIFT)
42880 #define XCVR_BRD_BBF_CTRL_BBF_TMUX_ON(base) (BME_UBFX32(&XCVR_BBF_CTRL_REG(base), XCVR_BBF_CTRL_BBF_TMUX_ON_SHIFT, XCVR_BBF_CTRL_BBF_TMUX_ON_WIDTH))
42881 
42882 /*! @brief Set the BBF_TMUX_ON field to a new value. */
42883 #define XCVR_WR_BBF_CTRL_BBF_TMUX_ON(base, value) (XCVR_RMW_BBF_CTRL(base, XCVR_BBF_CTRL_BBF_TMUX_ON_MASK, XCVR_BBF_CTRL_BBF_TMUX_ON(value)))
42884 #define XCVR_BWR_BBF_CTRL_BBF_TMUX_ON(base, value) (BME_BFI32(&XCVR_BBF_CTRL_REG(base), ((uint32_t)(value) << XCVR_BBF_CTRL_BBF_TMUX_ON_SHIFT), XCVR_BBF_CTRL_BBF_TMUX_ON_SHIFT, XCVR_BBF_CTRL_BBF_TMUX_ON_WIDTH))
42885 /*@}*/
42886 
42887 /*!
42888  * @name Register XCVR_BBF_CTRL, field DCOC_ALPHAC_SCALE_GS_IDX[13:12] (RW)
42889  *
42890  * DCOC Alpha-C Scaling. This has the same definition as DCOC_ALPHAC_SCALE_IDX.
42891  * The tracking estimator will switch from DCOC_ALPHAC_SCALE_IDX to
42892  * DCOC_ALPHAC_SCALE_GS_IDX at the time specified by the DCOC_TRK_EST_GS_CNT.
42893  *
42894  * Values:
42895  * - 0b00 - 1/2
42896  * - 0b01 - 1/4
42897  * - 0b10 - 1/8
42898  * - 0b11 - 1/16
42899  */
42900 /*@{*/
42901 /*! @brief Read current value of the XCVR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX field. */
42902 #define XCVR_RD_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX(base) ((XCVR_BBF_CTRL_REG(base) & XCVR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX_MASK) >> XCVR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX_SHIFT)
42903 #define XCVR_BRD_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX(base) (BME_UBFX32(&XCVR_BBF_CTRL_REG(base), XCVR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX_SHIFT, XCVR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX_WIDTH))
42904 
42905 /*! @brief Set the DCOC_ALPHAC_SCALE_GS_IDX field to a new value. */
42906 #define XCVR_WR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX(base, value) (XCVR_RMW_BBF_CTRL(base, XCVR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX_MASK, XCVR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX(value)))
42907 #define XCVR_BWR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX(base, value) (BME_BFI32(&XCVR_BBF_CTRL_REG(base), ((uint32_t)(value) << XCVR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX_SHIFT), XCVR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX_SHIFT, XCVR_BBF_CTRL_DCOC_ALPHAC_SCALE_GS_IDX_WIDTH))
42908 /*@}*/
42909 
42910 /*!
42911  * @name Register XCVR_BBF_CTRL, field BBF_SPARE_3_2[15:14] (RW)
42912  *
42913  * Spare Bits for future use
42914  */
42915 /*@{*/
42916 /*! @brief Read current value of the XCVR_BBF_CTRL_BBF_SPARE_3_2 field. */
42917 #define XCVR_RD_BBF_CTRL_BBF_SPARE_3_2(base) ((XCVR_BBF_CTRL_REG(base) & XCVR_BBF_CTRL_BBF_SPARE_3_2_MASK) >> XCVR_BBF_CTRL_BBF_SPARE_3_2_SHIFT)
42918 #define XCVR_BRD_BBF_CTRL_BBF_SPARE_3_2(base) (BME_UBFX32(&XCVR_BBF_CTRL_REG(base), XCVR_BBF_CTRL_BBF_SPARE_3_2_SHIFT, XCVR_BBF_CTRL_BBF_SPARE_3_2_WIDTH))
42919 
42920 /*! @brief Set the BBF_SPARE_3_2 field to a new value. */
42921 #define XCVR_WR_BBF_CTRL_BBF_SPARE_3_2(base, value) (XCVR_RMW_BBF_CTRL(base, XCVR_BBF_CTRL_BBF_SPARE_3_2_MASK, XCVR_BBF_CTRL_BBF_SPARE_3_2(value)))
42922 #define XCVR_BWR_BBF_CTRL_BBF_SPARE_3_2(base, value) (BME_BFI32(&XCVR_BBF_CTRL_REG(base), ((uint32_t)(value) << XCVR_BBF_CTRL_BBF_SPARE_3_2_SHIFT), XCVR_BBF_CTRL_BBF_SPARE_3_2_SHIFT, XCVR_BBF_CTRL_BBF_SPARE_3_2_WIDTH))
42923 /*@}*/
42924 
42925 /*******************************************************************************
42926  * XCVR_RX_ANA_CTRL - RX Analog Control
42927  ******************************************************************************/
42928 
42929 /*!
42930  * @brief XCVR_RX_ANA_CTRL - RX Analog Control (RW)
42931  *
42932  * Reset value: 0x00000000U
42933  */
42934 /*!
42935  * @name Constants and macros for entire XCVR_RX_ANA_CTRL register
42936  */
42937 /*@{*/
42938 #define XCVR_RD_RX_ANA_CTRL(base) (XCVR_RX_ANA_CTRL_REG(base))
42939 #define XCVR_WR_RX_ANA_CTRL(base, value) (XCVR_RX_ANA_CTRL_REG(base) = (value))
42940 #define XCVR_RMW_RX_ANA_CTRL(base, mask, value) (XCVR_WR_RX_ANA_CTRL(base, (XCVR_RD_RX_ANA_CTRL(base) & ~(mask)) | (value)))
42941 #define XCVR_SET_RX_ANA_CTRL(base, value) (BME_OR32(&XCVR_RX_ANA_CTRL_REG(base), (uint32_t)(value)))
42942 #define XCVR_CLR_RX_ANA_CTRL(base, value) (BME_AND32(&XCVR_RX_ANA_CTRL_REG(base), (uint32_t)(~(value))))
42943 #define XCVR_TOG_RX_ANA_CTRL(base, value) (BME_XOR32(&XCVR_RX_ANA_CTRL_REG(base), (uint32_t)(value)))
42944 /*@}*/
42945 
42946 /*
42947  * Constants & macros for individual XCVR_RX_ANA_CTRL bitfields
42948  */
42949 
42950 /*!
42951  * @name Register XCVR_RX_ANA_CTRL, field RX_ATST_SEL[3:0] (RW)
42952  *
42953  * These bits select the different internal baseband signals to be made
42954  * available on the ATST bus. The following table indicates the specific connection. All
42955  * other combinations are not defined. The bit bbf_tmux_on BBF_TMUX_ONBBF_TMUX_ON
42956  * needs to be enabled for the test mode to work. rx_atst_sel ATST0 ATST1 ATST2
42957  * ATST3 0000 half supply voltage bbf opamp common mode voltatge bbf_I_out
42958  * bbf_I_ouxt 0001 bba_dcoc_I bba_dcoc_Ix bba_dcoc_Q bba_dcoc_Qx 0010 tza_out_I
42959  * tza_out_Ix tza_out_Q tza_out_Qx 0011 peak det ref hi peak det ref lo peak det bias
42960  * check tza common mode 0100 bbf_out_I bbf_out_Ix bbf_out_Q bbf_out_Qx 0101
42961  * tza_dcoc_I tza_dcoc_Ix tza_dcoc_Q tza_dcoc_Qx 0101 tza_in_I tza_in_Ix tza_out_I
42962  * tza_out_Ix
42963  */
42964 /*@{*/
42965 /*! @brief Read current value of the XCVR_RX_ANA_CTRL_RX_ATST_SEL field. */
42966 #define XCVR_RD_RX_ANA_CTRL_RX_ATST_SEL(base) ((XCVR_RX_ANA_CTRL_REG(base) & XCVR_RX_ANA_CTRL_RX_ATST_SEL_MASK) >> XCVR_RX_ANA_CTRL_RX_ATST_SEL_SHIFT)
42967 #define XCVR_BRD_RX_ANA_CTRL_RX_ATST_SEL(base) (BME_UBFX32(&XCVR_RX_ANA_CTRL_REG(base), XCVR_RX_ANA_CTRL_RX_ATST_SEL_SHIFT, XCVR_RX_ANA_CTRL_RX_ATST_SEL_WIDTH))
42968 
42969 /*! @brief Set the RX_ATST_SEL field to a new value. */
42970 #define XCVR_WR_RX_ANA_CTRL_RX_ATST_SEL(base, value) (XCVR_RMW_RX_ANA_CTRL(base, XCVR_RX_ANA_CTRL_RX_ATST_SEL_MASK, XCVR_RX_ANA_CTRL_RX_ATST_SEL(value)))
42971 #define XCVR_BWR_RX_ANA_CTRL_RX_ATST_SEL(base, value) (BME_BFI32(&XCVR_RX_ANA_CTRL_REG(base), ((uint32_t)(value) << XCVR_RX_ANA_CTRL_RX_ATST_SEL_SHIFT), XCVR_RX_ANA_CTRL_RX_ATST_SEL_SHIFT, XCVR_RX_ANA_CTRL_RX_ATST_SEL_WIDTH))
42972 /*@}*/
42973 
42974 /*!
42975  * @name Register XCVR_RX_ANA_CTRL, field IQMC_DC_GAIN_ADJ_EN[4] (RW)
42976  *
42977  * If set, the I/Q mismatch uses IQMC_DC_GAIN_ADJ during DCOC calibration. If
42978  * clear, the I/Q mismatch uses IQMC_GAIN_ADJ.
42979  */
42980 /*@{*/
42981 /*! @brief Read current value of the XCVR_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN field. */
42982 #define XCVR_RD_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN(base) ((XCVR_RX_ANA_CTRL_REG(base) & XCVR_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN_MASK) >> XCVR_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN_SHIFT)
42983 #define XCVR_BRD_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN(base) (BME_UBFX32(&XCVR_RX_ANA_CTRL_REG(base), XCVR_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN_SHIFT, XCVR_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN_WIDTH))
42984 
42985 /*! @brief Set the IQMC_DC_GAIN_ADJ_EN field to a new value. */
42986 #define XCVR_WR_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN(base, value) (XCVR_RMW_RX_ANA_CTRL(base, XCVR_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN_MASK, XCVR_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN(value)))
42987 #define XCVR_BWR_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN(base, value) (BME_BFI32(&XCVR_RX_ANA_CTRL_REG(base), ((uint32_t)(value) << XCVR_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN_SHIFT), XCVR_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN_SHIFT, XCVR_RX_ANA_CTRL_IQMC_DC_GAIN_ADJ_EN_WIDTH))
42988 /*@}*/
42989 
42990 /*!
42991  * @name Register XCVR_RX_ANA_CTRL, field LNM_SPARE_3_2_1[7:5] (RW)
42992  *
42993  * Spare Bits for future use
42994  */
42995 /*@{*/
42996 /*! @brief Read current value of the XCVR_RX_ANA_CTRL_LNM_SPARE_3_2_1 field. */
42997 #define XCVR_RD_RX_ANA_CTRL_LNM_SPARE_3_2_1(base) ((XCVR_RX_ANA_CTRL_REG(base) & XCVR_RX_ANA_CTRL_LNM_SPARE_3_2_1_MASK) >> XCVR_RX_ANA_CTRL_LNM_SPARE_3_2_1_SHIFT)
42998 #define XCVR_BRD_RX_ANA_CTRL_LNM_SPARE_3_2_1(base) (BME_UBFX32(&XCVR_RX_ANA_CTRL_REG(base), XCVR_RX_ANA_CTRL_LNM_SPARE_3_2_1_SHIFT, XCVR_RX_ANA_CTRL_LNM_SPARE_3_2_1_WIDTH))
42999 
43000 /*! @brief Set the LNM_SPARE_3_2_1 field to a new value. */
43001 #define XCVR_WR_RX_ANA_CTRL_LNM_SPARE_3_2_1(base, value) (XCVR_RMW_RX_ANA_CTRL(base, XCVR_RX_ANA_CTRL_LNM_SPARE_3_2_1_MASK, XCVR_RX_ANA_CTRL_LNM_SPARE_3_2_1(value)))
43002 #define XCVR_BWR_RX_ANA_CTRL_LNM_SPARE_3_2_1(base, value) (BME_BFI32(&XCVR_RX_ANA_CTRL_REG(base), ((uint32_t)(value) << XCVR_RX_ANA_CTRL_LNM_SPARE_3_2_1_SHIFT), XCVR_RX_ANA_CTRL_LNM_SPARE_3_2_1_SHIFT, XCVR_RX_ANA_CTRL_LNM_SPARE_3_2_1_WIDTH))
43003 /*@}*/
43004 
43005 /*******************************************************************************
43006  * XCVR_XTAL_CTRL - Crystal Oscillator Control Register 1
43007  ******************************************************************************/
43008 
43009 /*!
43010  * @brief XCVR_XTAL_CTRL - Crystal Oscillator Control Register 1 (RW)
43011  *
43012  * Reset value: 0x0ACAC177U
43013  */
43014 /*!
43015  * @name Constants and macros for entire XCVR_XTAL_CTRL register
43016  */
43017 /*@{*/
43018 #define XCVR_RD_XTAL_CTRL(base)  (XCVR_XTAL_CTRL_REG(base))
43019 #define XCVR_WR_XTAL_CTRL(base, value) (XCVR_XTAL_CTRL_REG(base) = (value))
43020 #define XCVR_RMW_XTAL_CTRL(base, mask, value) (XCVR_WR_XTAL_CTRL(base, (XCVR_RD_XTAL_CTRL(base) & ~(mask)) | (value)))
43021 #define XCVR_SET_XTAL_CTRL(base, value) (BME_OR32(&XCVR_XTAL_CTRL_REG(base), (uint32_t)(value)))
43022 #define XCVR_CLR_XTAL_CTRL(base, value) (BME_AND32(&XCVR_XTAL_CTRL_REG(base), (uint32_t)(~(value))))
43023 #define XCVR_TOG_XTAL_CTRL(base, value) (BME_XOR32(&XCVR_XTAL_CTRL_REG(base), (uint32_t)(value)))
43024 /*@}*/
43025 
43026 /*
43027  * Constants & macros for individual XCVR_XTAL_CTRL bitfields
43028  */
43029 
43030 /*!
43031  * @name Register XCVR_XTAL_CTRL, field XTAL_TRIM[7:0] (RW)
43032  *
43033  * Program the internal capacitor banks to trim the 32M Crytstal frequency. It
43034  * has a trim range of ~2Khz
43035  */
43036 /*@{*/
43037 /*! @brief Read current value of the XCVR_XTAL_CTRL_XTAL_TRIM field. */
43038 #define XCVR_RD_XTAL_CTRL_XTAL_TRIM(base) ((XCVR_XTAL_CTRL_REG(base) & XCVR_XTAL_CTRL_XTAL_TRIM_MASK) >> XCVR_XTAL_CTRL_XTAL_TRIM_SHIFT)
43039 #define XCVR_BRD_XTAL_CTRL_XTAL_TRIM(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL_CTRL_XTAL_TRIM_SHIFT, XCVR_XTAL_CTRL_XTAL_TRIM_WIDTH))
43040 
43041 /*! @brief Set the XTAL_TRIM field to a new value. */
43042 #define XCVR_WR_XTAL_CTRL_XTAL_TRIM(base, value) (XCVR_RMW_XTAL_CTRL(base, XCVR_XTAL_CTRL_XTAL_TRIM_MASK, XCVR_XTAL_CTRL_XTAL_TRIM(value)))
43043 #define XCVR_BWR_XTAL_CTRL_XTAL_TRIM(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), ((uint32_t)(value) << XCVR_XTAL_CTRL_XTAL_TRIM_SHIFT), XCVR_XTAL_CTRL_XTAL_TRIM_SHIFT, XCVR_XTAL_CTRL_XTAL_TRIM_WIDTH))
43044 /*@}*/
43045 
43046 /*!
43047  * @name Register XCVR_XTAL_CTRL, field XTAL_GM[12:8] (RW)
43048  *
43049  * This is used adjust the gm of the Crystal core. All 0's is minimum gm and all
43050  * 1's is maximum gm
43051  */
43052 /*@{*/
43053 /*! @brief Read current value of the XCVR_XTAL_CTRL_XTAL_GM field. */
43054 #define XCVR_RD_XTAL_CTRL_XTAL_GM(base) ((XCVR_XTAL_CTRL_REG(base) & XCVR_XTAL_CTRL_XTAL_GM_MASK) >> XCVR_XTAL_CTRL_XTAL_GM_SHIFT)
43055 #define XCVR_BRD_XTAL_CTRL_XTAL_GM(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL_CTRL_XTAL_GM_SHIFT, XCVR_XTAL_CTRL_XTAL_GM_WIDTH))
43056 
43057 /*! @brief Set the XTAL_GM field to a new value. */
43058 #define XCVR_WR_XTAL_CTRL_XTAL_GM(base, value) (XCVR_RMW_XTAL_CTRL(base, XCVR_XTAL_CTRL_XTAL_GM_MASK, XCVR_XTAL_CTRL_XTAL_GM(value)))
43059 #define XCVR_BWR_XTAL_CTRL_XTAL_GM(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), ((uint32_t)(value) << XCVR_XTAL_CTRL_XTAL_GM_SHIFT), XCVR_XTAL_CTRL_XTAL_GM_SHIFT, XCVR_XTAL_CTRL_XTAL_GM_WIDTH))
43060 /*@}*/
43061 
43062 /*!
43063  * @name Register XCVR_XTAL_CTRL, field XTAL_BYPASS[13] (RW)
43064  *
43065  * When this bit is set, the Crystal Oscillator is disabled and an external
43066  * clock signal applied on the EXTAL pin is selected as the clock source.
43067  */
43068 /*@{*/
43069 /*! @brief Read current value of the XCVR_XTAL_CTRL_XTAL_BYPASS field. */
43070 #define XCVR_RD_XTAL_CTRL_XTAL_BYPASS(base) ((XCVR_XTAL_CTRL_REG(base) & XCVR_XTAL_CTRL_XTAL_BYPASS_MASK) >> XCVR_XTAL_CTRL_XTAL_BYPASS_SHIFT)
43071 #define XCVR_BRD_XTAL_CTRL_XTAL_BYPASS(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL_CTRL_XTAL_BYPASS_SHIFT, XCVR_XTAL_CTRL_XTAL_BYPASS_WIDTH))
43072 
43073 /*! @brief Set the XTAL_BYPASS field to a new value. */
43074 #define XCVR_WR_XTAL_CTRL_XTAL_BYPASS(base, value) (XCVR_RMW_XTAL_CTRL(base, XCVR_XTAL_CTRL_XTAL_BYPASS_MASK, XCVR_XTAL_CTRL_XTAL_BYPASS(value)))
43075 #define XCVR_BWR_XTAL_CTRL_XTAL_BYPASS(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), ((uint32_t)(value) << XCVR_XTAL_CTRL_XTAL_BYPASS_SHIFT), XCVR_XTAL_CTRL_XTAL_BYPASS_SHIFT, XCVR_XTAL_CTRL_XTAL_BYPASS_WIDTH))
43076 /*@}*/
43077 
43078 /*!
43079  * @name Register XCVR_XTAL_CTRL, field XTAL_READY_COUNT_SEL[15:14] (RW)
43080  *
43081  * This selects the number of count cycles before xtal_ready goes high
43082  *
43083  * Values:
43084  * - 0b00 - 1024 clock cycles
43085  * - 0b01 - 2048 clock cycles
43086  * - 0b10 - 4096 clock cycles
43087  * - 0b11 - 8192 clock cycles
43088  */
43089 /*@{*/
43090 /*! @brief Read current value of the XCVR_XTAL_CTRL_XTAL_READY_COUNT_SEL field. */
43091 #define XCVR_RD_XTAL_CTRL_XTAL_READY_COUNT_SEL(base) ((XCVR_XTAL_CTRL_REG(base) & XCVR_XTAL_CTRL_XTAL_READY_COUNT_SEL_MASK) >> XCVR_XTAL_CTRL_XTAL_READY_COUNT_SEL_SHIFT)
43092 #define XCVR_BRD_XTAL_CTRL_XTAL_READY_COUNT_SEL(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL_CTRL_XTAL_READY_COUNT_SEL_SHIFT, XCVR_XTAL_CTRL_XTAL_READY_COUNT_SEL_WIDTH))
43093 
43094 /*! @brief Set the XTAL_READY_COUNT_SEL field to a new value. */
43095 #define XCVR_WR_XTAL_CTRL_XTAL_READY_COUNT_SEL(base, value) (XCVR_RMW_XTAL_CTRL(base, XCVR_XTAL_CTRL_XTAL_READY_COUNT_SEL_MASK, XCVR_XTAL_CTRL_XTAL_READY_COUNT_SEL(value)))
43096 #define XCVR_BWR_XTAL_CTRL_XTAL_READY_COUNT_SEL(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), ((uint32_t)(value) << XCVR_XTAL_CTRL_XTAL_READY_COUNT_SEL_SHIFT), XCVR_XTAL_CTRL_XTAL_READY_COUNT_SEL_SHIFT, XCVR_XTAL_CTRL_XTAL_READY_COUNT_SEL_WIDTH))
43097 /*@}*/
43098 
43099 /*!
43100  * @name Register XCVR_XTAL_CTRL, field XTAL_COMP_BIAS_LO[20:16] (RW)
43101  *
43102  * These bits used to adjust the bias of the crystal Comparator when the
43103  * transceiver is IDLE
43104  */
43105 /*@{*/
43106 /*! @brief Read current value of the XCVR_XTAL_CTRL_XTAL_COMP_BIAS_LO field. */
43107 #define XCVR_RD_XTAL_CTRL_XTAL_COMP_BIAS_LO(base) ((XCVR_XTAL_CTRL_REG(base) & XCVR_XTAL_CTRL_XTAL_COMP_BIAS_LO_MASK) >> XCVR_XTAL_CTRL_XTAL_COMP_BIAS_LO_SHIFT)
43108 #define XCVR_BRD_XTAL_CTRL_XTAL_COMP_BIAS_LO(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL_CTRL_XTAL_COMP_BIAS_LO_SHIFT, XCVR_XTAL_CTRL_XTAL_COMP_BIAS_LO_WIDTH))
43109 
43110 /*! @brief Set the XTAL_COMP_BIAS_LO field to a new value. */
43111 #define XCVR_WR_XTAL_CTRL_XTAL_COMP_BIAS_LO(base, value) (XCVR_RMW_XTAL_CTRL(base, XCVR_XTAL_CTRL_XTAL_COMP_BIAS_LO_MASK, XCVR_XTAL_CTRL_XTAL_COMP_BIAS_LO(value)))
43112 #define XCVR_BWR_XTAL_CTRL_XTAL_COMP_BIAS_LO(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), ((uint32_t)(value) << XCVR_XTAL_CTRL_XTAL_COMP_BIAS_LO_SHIFT), XCVR_XTAL_CTRL_XTAL_COMP_BIAS_LO_SHIFT, XCVR_XTAL_CTRL_XTAL_COMP_BIAS_LO_WIDTH))
43113 /*@}*/
43114 
43115 /*!
43116  * @name Register XCVR_XTAL_CTRL, field XTAL_ALC_START_512U[22] (RW)
43117  *
43118  * Values:
43119  * - 0b0 - Start XTAL ALC at 256usec
43120  * - 0b1 - Start XTAL ALC at 512usec
43121  */
43122 /*@{*/
43123 /*! @brief Read current value of the XCVR_XTAL_CTRL_XTAL_ALC_START_512U field. */
43124 #define XCVR_RD_XTAL_CTRL_XTAL_ALC_START_512U(base) ((XCVR_XTAL_CTRL_REG(base) & XCVR_XTAL_CTRL_XTAL_ALC_START_512U_MASK) >> XCVR_XTAL_CTRL_XTAL_ALC_START_512U_SHIFT)
43125 #define XCVR_BRD_XTAL_CTRL_XTAL_ALC_START_512U(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL_CTRL_XTAL_ALC_START_512U_SHIFT, XCVR_XTAL_CTRL_XTAL_ALC_START_512U_WIDTH))
43126 
43127 /*! @brief Set the XTAL_ALC_START_512U field to a new value. */
43128 #define XCVR_WR_XTAL_CTRL_XTAL_ALC_START_512U(base, value) (XCVR_RMW_XTAL_CTRL(base, XCVR_XTAL_CTRL_XTAL_ALC_START_512U_MASK, XCVR_XTAL_CTRL_XTAL_ALC_START_512U(value)))
43129 #define XCVR_BWR_XTAL_CTRL_XTAL_ALC_START_512U(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), ((uint32_t)(value) << XCVR_XTAL_CTRL_XTAL_ALC_START_512U_SHIFT), XCVR_XTAL_CTRL_XTAL_ALC_START_512U_SHIFT, XCVR_XTAL_CTRL_XTAL_ALC_START_512U_WIDTH))
43130 /*@}*/
43131 
43132 /*!
43133  * @name Register XCVR_XTAL_CTRL, field XTAL_ALC_ON[23] (RW)
43134  *
43135  * enable the ALC for the xtal
43136  */
43137 /*@{*/
43138 /*! @brief Read current value of the XCVR_XTAL_CTRL_XTAL_ALC_ON field. */
43139 #define XCVR_RD_XTAL_CTRL_XTAL_ALC_ON(base) ((XCVR_XTAL_CTRL_REG(base) & XCVR_XTAL_CTRL_XTAL_ALC_ON_MASK) >> XCVR_XTAL_CTRL_XTAL_ALC_ON_SHIFT)
43140 #define XCVR_BRD_XTAL_CTRL_XTAL_ALC_ON(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL_CTRL_XTAL_ALC_ON_SHIFT, XCVR_XTAL_CTRL_XTAL_ALC_ON_WIDTH))
43141 
43142 /*! @brief Set the XTAL_ALC_ON field to a new value. */
43143 #define XCVR_WR_XTAL_CTRL_XTAL_ALC_ON(base, value) (XCVR_RMW_XTAL_CTRL(base, XCVR_XTAL_CTRL_XTAL_ALC_ON_MASK, XCVR_XTAL_CTRL_XTAL_ALC_ON(value)))
43144 #define XCVR_BWR_XTAL_CTRL_XTAL_ALC_ON(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), ((uint32_t)(value) << XCVR_XTAL_CTRL_XTAL_ALC_ON_SHIFT), XCVR_XTAL_CTRL_XTAL_ALC_ON_SHIFT, XCVR_XTAL_CTRL_XTAL_ALC_ON_WIDTH))
43145 /*@}*/
43146 
43147 /*!
43148  * @name Register XCVR_XTAL_CTRL, field XTAL_COMP_BIAS_HI[28:24] (RW)
43149  *
43150  * These bits used to adjust the bias of the crystal Comparator when the
43151  * transceiver is ACTIVE
43152  */
43153 /*@{*/
43154 /*! @brief Read current value of the XCVR_XTAL_CTRL_XTAL_COMP_BIAS_HI field. */
43155 #define XCVR_RD_XTAL_CTRL_XTAL_COMP_BIAS_HI(base) ((XCVR_XTAL_CTRL_REG(base) & XCVR_XTAL_CTRL_XTAL_COMP_BIAS_HI_MASK) >> XCVR_XTAL_CTRL_XTAL_COMP_BIAS_HI_SHIFT)
43156 #define XCVR_BRD_XTAL_CTRL_XTAL_COMP_BIAS_HI(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL_CTRL_XTAL_COMP_BIAS_HI_SHIFT, XCVR_XTAL_CTRL_XTAL_COMP_BIAS_HI_WIDTH))
43157 
43158 /*! @brief Set the XTAL_COMP_BIAS_HI field to a new value. */
43159 #define XCVR_WR_XTAL_CTRL_XTAL_COMP_BIAS_HI(base, value) (XCVR_RMW_XTAL_CTRL(base, XCVR_XTAL_CTRL_XTAL_COMP_BIAS_HI_MASK, XCVR_XTAL_CTRL_XTAL_COMP_BIAS_HI(value)))
43160 #define XCVR_BWR_XTAL_CTRL_XTAL_COMP_BIAS_HI(base, value) (BME_BFI32(&XCVR_XTAL_CTRL_REG(base), ((uint32_t)(value) << XCVR_XTAL_CTRL_XTAL_COMP_BIAS_HI_SHIFT), XCVR_XTAL_CTRL_XTAL_COMP_BIAS_HI_SHIFT, XCVR_XTAL_CTRL_XTAL_COMP_BIAS_HI_WIDTH))
43161 /*@}*/
43162 
43163 /*!
43164  * @name Register XCVR_XTAL_CTRL, field XTAL_READY[31] (RO)
43165  *
43166  * The signal goes high after a number of cycles determined by
43167  * xtal_ready_count_sel
43168  */
43169 /*@{*/
43170 /*! @brief Read current value of the XCVR_XTAL_CTRL_XTAL_READY field. */
43171 #define XCVR_RD_XTAL_CTRL_XTAL_READY(base) ((XCVR_XTAL_CTRL_REG(base) & XCVR_XTAL_CTRL_XTAL_READY_MASK) >> XCVR_XTAL_CTRL_XTAL_READY_SHIFT)
43172 #define XCVR_BRD_XTAL_CTRL_XTAL_READY(base) (BME_UBFX32(&XCVR_XTAL_CTRL_REG(base), XCVR_XTAL_CTRL_XTAL_READY_SHIFT, XCVR_XTAL_CTRL_XTAL_READY_WIDTH))
43173 /*@}*/
43174 
43175 /*******************************************************************************
43176  * XCVR_XTAL_CTRL2 - Crystal Oscillator Control Register 2
43177  ******************************************************************************/
43178 
43179 /*!
43180  * @brief XCVR_XTAL_CTRL2 - Crystal Oscillator Control Register 2 (RW)
43181  *
43182  * Reset value: 0x00001000U
43183  */
43184 /*!
43185  * @name Constants and macros for entire XCVR_XTAL_CTRL2 register
43186  */
43187 /*@{*/
43188 #define XCVR_RD_XTAL_CTRL2(base) (XCVR_XTAL_CTRL2_REG(base))
43189 #define XCVR_WR_XTAL_CTRL2(base, value) (XCVR_XTAL_CTRL2_REG(base) = (value))
43190 #define XCVR_RMW_XTAL_CTRL2(base, mask, value) (XCVR_WR_XTAL_CTRL2(base, (XCVR_RD_XTAL_CTRL2(base) & ~(mask)) | (value)))
43191 #define XCVR_SET_XTAL_CTRL2(base, value) (BME_OR32(&XCVR_XTAL_CTRL2_REG(base), (uint32_t)(value)))
43192 #define XCVR_CLR_XTAL_CTRL2(base, value) (BME_AND32(&XCVR_XTAL_CTRL2_REG(base), (uint32_t)(~(value))))
43193 #define XCVR_TOG_XTAL_CTRL2(base, value) (BME_XOR32(&XCVR_XTAL_CTRL2_REG(base), (uint32_t)(value)))
43194 /*@}*/
43195 
43196 /*
43197  * Constants & macros for individual XCVR_XTAL_CTRL2 bitfields
43198  */
43199 
43200 /*!
43201  * @name Register XCVR_XTAL_CTRL2, field XTAL_REG_SUPPLY[3:0] (RW)
43202  *
43203  * Regulator trim bit to change the outputvoltage from 1.05 to 1.4V
43204  *
43205  * Values:
43206  * - 0b0000 - 1.2V
43207  * - 0b0001 - 1.05V
43208  * - 0b0010 - 1.275V
43209  * - 0b0011 - 1.3V
43210  */
43211 /*@{*/
43212 /*! @brief Read current value of the XCVR_XTAL_CTRL2_XTAL_REG_SUPPLY field. */
43213 #define XCVR_RD_XTAL_CTRL2_XTAL_REG_SUPPLY(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_XTAL_REG_SUPPLY_MASK) >> XCVR_XTAL_CTRL2_XTAL_REG_SUPPLY_SHIFT)
43214 #define XCVR_BRD_XTAL_CTRL2_XTAL_REG_SUPPLY(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL_CTRL2_XTAL_REG_SUPPLY_SHIFT, XCVR_XTAL_CTRL2_XTAL_REG_SUPPLY_WIDTH))
43215 
43216 /*! @brief Set the XTAL_REG_SUPPLY field to a new value. */
43217 #define XCVR_WR_XTAL_CTRL2_XTAL_REG_SUPPLY(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CTRL2_XTAL_REG_SUPPLY_MASK, XCVR_XTAL_CTRL2_XTAL_REG_SUPPLY(value)))
43218 #define XCVR_BWR_XTAL_CTRL2_XTAL_REG_SUPPLY(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((uint32_t)(value) << XCVR_XTAL_CTRL2_XTAL_REG_SUPPLY_SHIFT), XCVR_XTAL_CTRL2_XTAL_REG_SUPPLY_SHIFT, XCVR_XTAL_CTRL2_XTAL_REG_SUPPLY_WIDTH))
43219 /*@}*/
43220 
43221 /*!
43222  * @name Register XCVR_XTAL_CTRL2, field XTAL_REG_BYPASS_ON[4] (RW)
43223  *
43224  * This register bit determines if the regulator is in bypass mode. When in
43225  * bypass mode, the external voltage applied to the input of the regulator is
43226  * presented at the regulator output.
43227  */
43228 /*@{*/
43229 /*! @brief Read current value of the XCVR_XTAL_CTRL2_XTAL_REG_BYPASS_ON field. */
43230 #define XCVR_RD_XTAL_CTRL2_XTAL_REG_BYPASS_ON(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_XTAL_REG_BYPASS_ON_MASK) >> XCVR_XTAL_CTRL2_XTAL_REG_BYPASS_ON_SHIFT)
43231 #define XCVR_BRD_XTAL_CTRL2_XTAL_REG_BYPASS_ON(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL_CTRL2_XTAL_REG_BYPASS_ON_SHIFT, XCVR_XTAL_CTRL2_XTAL_REG_BYPASS_ON_WIDTH))
43232 
43233 /*! @brief Set the XTAL_REG_BYPASS_ON field to a new value. */
43234 #define XCVR_WR_XTAL_CTRL2_XTAL_REG_BYPASS_ON(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CTRL2_XTAL_REG_BYPASS_ON_MASK, XCVR_XTAL_CTRL2_XTAL_REG_BYPASS_ON(value)))
43235 #define XCVR_BWR_XTAL_CTRL2_XTAL_REG_BYPASS_ON(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((uint32_t)(value) << XCVR_XTAL_CTRL2_XTAL_REG_BYPASS_ON_SHIFT), XCVR_XTAL_CTRL2_XTAL_REG_BYPASS_ON_SHIFT, XCVR_XTAL_CTRL2_XTAL_REG_BYPASS_ON_WIDTH))
43236 /*@}*/
43237 
43238 /*!
43239  * @name Register XCVR_XTAL_CTRL2, field XTAL_REG_ON_OVRD_ON[8] (RW)
43240  *
43241  * Mux select for the crystal regulator enable between normal operation (0) and
43242  * test mode (1). The test signal is called xtal_reg_on_ovrd
43243  */
43244 /*@{*/
43245 /*! @brief Read current value of the XCVR_XTAL_CTRL2_XTAL_REG_ON_OVRD_ON field. */
43246 #define XCVR_RD_XTAL_CTRL2_XTAL_REG_ON_OVRD_ON(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_XTAL_REG_ON_OVRD_ON_MASK) >> XCVR_XTAL_CTRL2_XTAL_REG_ON_OVRD_ON_SHIFT)
43247 #define XCVR_BRD_XTAL_CTRL2_XTAL_REG_ON_OVRD_ON(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL_CTRL2_XTAL_REG_ON_OVRD_ON_SHIFT, XCVR_XTAL_CTRL2_XTAL_REG_ON_OVRD_ON_WIDTH))
43248 
43249 /*! @brief Set the XTAL_REG_ON_OVRD_ON field to a new value. */
43250 #define XCVR_WR_XTAL_CTRL2_XTAL_REG_ON_OVRD_ON(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CTRL2_XTAL_REG_ON_OVRD_ON_MASK, XCVR_XTAL_CTRL2_XTAL_REG_ON_OVRD_ON(value)))
43251 #define XCVR_BWR_XTAL_CTRL2_XTAL_REG_ON_OVRD_ON(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((uint32_t)(value) << XCVR_XTAL_CTRL2_XTAL_REG_ON_OVRD_ON_SHIFT), XCVR_XTAL_CTRL2_XTAL_REG_ON_OVRD_ON_SHIFT, XCVR_XTAL_CTRL2_XTAL_REG_ON_OVRD_ON_WIDTH))
43252 /*@}*/
43253 
43254 /*!
43255  * @name Register XCVR_XTAL_CTRL2, field XTAL_REG_ON_OVRD[9] (RW)
43256  *
43257  * Enable for the xtal regulator in test mode (XTAL_REG_ON_OVRD_ON=1)
43258  */
43259 /*@{*/
43260 /*! @brief Read current value of the XCVR_XTAL_CTRL2_XTAL_REG_ON_OVRD field. */
43261 #define XCVR_RD_XTAL_CTRL2_XTAL_REG_ON_OVRD(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_XTAL_REG_ON_OVRD_MASK) >> XCVR_XTAL_CTRL2_XTAL_REG_ON_OVRD_SHIFT)
43262 #define XCVR_BRD_XTAL_CTRL2_XTAL_REG_ON_OVRD(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL_CTRL2_XTAL_REG_ON_OVRD_SHIFT, XCVR_XTAL_CTRL2_XTAL_REG_ON_OVRD_WIDTH))
43263 
43264 /*! @brief Set the XTAL_REG_ON_OVRD field to a new value. */
43265 #define XCVR_WR_XTAL_CTRL2_XTAL_REG_ON_OVRD(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CTRL2_XTAL_REG_ON_OVRD_MASK, XCVR_XTAL_CTRL2_XTAL_REG_ON_OVRD(value)))
43266 #define XCVR_BWR_XTAL_CTRL2_XTAL_REG_ON_OVRD(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((uint32_t)(value) << XCVR_XTAL_CTRL2_XTAL_REG_ON_OVRD_SHIFT), XCVR_XTAL_CTRL2_XTAL_REG_ON_OVRD_SHIFT, XCVR_XTAL_CTRL2_XTAL_REG_ON_OVRD_WIDTH))
43267 /*@}*/
43268 
43269 /*!
43270  * @name Register XCVR_XTAL_CTRL2, field XTAL_ON_OVRD_ON[10] (RW)
43271  *
43272  * mux select for the crystal enable between normal operation (0) and test mode
43273  * (1)
43274  */
43275 /*@{*/
43276 /*! @brief Read current value of the XCVR_XTAL_CTRL2_XTAL_ON_OVRD_ON field. */
43277 #define XCVR_RD_XTAL_CTRL2_XTAL_ON_OVRD_ON(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_XTAL_ON_OVRD_ON_MASK) >> XCVR_XTAL_CTRL2_XTAL_ON_OVRD_ON_SHIFT)
43278 #define XCVR_BRD_XTAL_CTRL2_XTAL_ON_OVRD_ON(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL_CTRL2_XTAL_ON_OVRD_ON_SHIFT, XCVR_XTAL_CTRL2_XTAL_ON_OVRD_ON_WIDTH))
43279 
43280 /*! @brief Set the XTAL_ON_OVRD_ON field to a new value. */
43281 #define XCVR_WR_XTAL_CTRL2_XTAL_ON_OVRD_ON(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CTRL2_XTAL_ON_OVRD_ON_MASK, XCVR_XTAL_CTRL2_XTAL_ON_OVRD_ON(value)))
43282 #define XCVR_BWR_XTAL_CTRL2_XTAL_ON_OVRD_ON(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((uint32_t)(value) << XCVR_XTAL_CTRL2_XTAL_ON_OVRD_ON_SHIFT), XCVR_XTAL_CTRL2_XTAL_ON_OVRD_ON_SHIFT, XCVR_XTAL_CTRL2_XTAL_ON_OVRD_ON_WIDTH))
43283 /*@}*/
43284 
43285 /*!
43286  * @name Register XCVR_XTAL_CTRL2, field XTAL_ON_OVRD[11] (RW)
43287  *
43288  * enable for the xtal in test mode (XTAL_ON_OVRD_ON=1)
43289  */
43290 /*@{*/
43291 /*! @brief Read current value of the XCVR_XTAL_CTRL2_XTAL_ON_OVRD field. */
43292 #define XCVR_RD_XTAL_CTRL2_XTAL_ON_OVRD(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_XTAL_ON_OVRD_MASK) >> XCVR_XTAL_CTRL2_XTAL_ON_OVRD_SHIFT)
43293 #define XCVR_BRD_XTAL_CTRL2_XTAL_ON_OVRD(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL_CTRL2_XTAL_ON_OVRD_SHIFT, XCVR_XTAL_CTRL2_XTAL_ON_OVRD_WIDTH))
43294 
43295 /*! @brief Set the XTAL_ON_OVRD field to a new value. */
43296 #define XCVR_WR_XTAL_CTRL2_XTAL_ON_OVRD(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CTRL2_XTAL_ON_OVRD_MASK, XCVR_XTAL_CTRL2_XTAL_ON_OVRD(value)))
43297 #define XCVR_BWR_XTAL_CTRL2_XTAL_ON_OVRD(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((uint32_t)(value) << XCVR_XTAL_CTRL2_XTAL_ON_OVRD_SHIFT), XCVR_XTAL_CTRL2_XTAL_ON_OVRD_SHIFT, XCVR_XTAL_CTRL2_XTAL_ON_OVRD_WIDTH))
43298 /*@}*/
43299 
43300 /*!
43301  * @name Register XCVR_XTAL_CTRL2, field XTAL_DIG_CLK_OUT_ON[12] (RW)
43302  *
43303  * This bit gates the Crystal clock output
43304  */
43305 /*@{*/
43306 /*! @brief Read current value of the XCVR_XTAL_CTRL2_XTAL_DIG_CLK_OUT_ON field. */
43307 #define XCVR_RD_XTAL_CTRL2_XTAL_DIG_CLK_OUT_ON(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_XTAL_DIG_CLK_OUT_ON_MASK) >> XCVR_XTAL_CTRL2_XTAL_DIG_CLK_OUT_ON_SHIFT)
43308 #define XCVR_BRD_XTAL_CTRL2_XTAL_DIG_CLK_OUT_ON(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL_CTRL2_XTAL_DIG_CLK_OUT_ON_SHIFT, XCVR_XTAL_CTRL2_XTAL_DIG_CLK_OUT_ON_WIDTH))
43309 
43310 /*! @brief Set the XTAL_DIG_CLK_OUT_ON field to a new value. */
43311 #define XCVR_WR_XTAL_CTRL2_XTAL_DIG_CLK_OUT_ON(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CTRL2_XTAL_DIG_CLK_OUT_ON_MASK, XCVR_XTAL_CTRL2_XTAL_DIG_CLK_OUT_ON(value)))
43312 #define XCVR_BWR_XTAL_CTRL2_XTAL_DIG_CLK_OUT_ON(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((uint32_t)(value) << XCVR_XTAL_CTRL2_XTAL_DIG_CLK_OUT_ON_SHIFT), XCVR_XTAL_CTRL2_XTAL_DIG_CLK_OUT_ON_SHIFT, XCVR_XTAL_CTRL2_XTAL_DIG_CLK_OUT_ON_WIDTH))
43313 /*@}*/
43314 
43315 /*!
43316  * @name Register XCVR_XTAL_CTRL2, field XTAL_REG_ATST_SEL[17:16] (RW)
43317  *
43318  * These bits control the what internal regualtor signals are connected to the
43319  * ATST bus. register setting ATST0 00 No Connect 01 vout 10 vin feedback 11 vbias
43320  */
43321 /*@{*/
43322 /*! @brief Read current value of the XCVR_XTAL_CTRL2_XTAL_REG_ATST_SEL field. */
43323 #define XCVR_RD_XTAL_CTRL2_XTAL_REG_ATST_SEL(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_XTAL_REG_ATST_SEL_MASK) >> XCVR_XTAL_CTRL2_XTAL_REG_ATST_SEL_SHIFT)
43324 #define XCVR_BRD_XTAL_CTRL2_XTAL_REG_ATST_SEL(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL_CTRL2_XTAL_REG_ATST_SEL_SHIFT, XCVR_XTAL_CTRL2_XTAL_REG_ATST_SEL_WIDTH))
43325 
43326 /*! @brief Set the XTAL_REG_ATST_SEL field to a new value. */
43327 #define XCVR_WR_XTAL_CTRL2_XTAL_REG_ATST_SEL(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CTRL2_XTAL_REG_ATST_SEL_MASK, XCVR_XTAL_CTRL2_XTAL_REG_ATST_SEL(value)))
43328 #define XCVR_BWR_XTAL_CTRL2_XTAL_REG_ATST_SEL(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((uint32_t)(value) << XCVR_XTAL_CTRL2_XTAL_REG_ATST_SEL_SHIFT), XCVR_XTAL_CTRL2_XTAL_REG_ATST_SEL_SHIFT, XCVR_XTAL_CTRL2_XTAL_REG_ATST_SEL_WIDTH))
43329 /*@}*/
43330 
43331 /*!
43332  * @name Register XCVR_XTAL_CTRL2, field XTAL_ATST_SEL[25:24] (RW)
43333  *
43334  * These bits are not used in this version of the chip. Since only one signal is
43335  * brought out for test purposes, xtal_atst_on is used as the enable and sel
43336  * signal
43337  */
43338 /*@{*/
43339 /*! @brief Read current value of the XCVR_XTAL_CTRL2_XTAL_ATST_SEL field. */
43340 #define XCVR_RD_XTAL_CTRL2_XTAL_ATST_SEL(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_XTAL_ATST_SEL_MASK) >> XCVR_XTAL_CTRL2_XTAL_ATST_SEL_SHIFT)
43341 #define XCVR_BRD_XTAL_CTRL2_XTAL_ATST_SEL(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL_CTRL2_XTAL_ATST_SEL_SHIFT, XCVR_XTAL_CTRL2_XTAL_ATST_SEL_WIDTH))
43342 
43343 /*! @brief Set the XTAL_ATST_SEL field to a new value. */
43344 #define XCVR_WR_XTAL_CTRL2_XTAL_ATST_SEL(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CTRL2_XTAL_ATST_SEL_MASK, XCVR_XTAL_CTRL2_XTAL_ATST_SEL(value)))
43345 #define XCVR_BWR_XTAL_CTRL2_XTAL_ATST_SEL(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((uint32_t)(value) << XCVR_XTAL_CTRL2_XTAL_ATST_SEL_SHIFT), XCVR_XTAL_CTRL2_XTAL_ATST_SEL_SHIFT, XCVR_XTAL_CTRL2_XTAL_ATST_SEL_WIDTH))
43346 /*@}*/
43347 
43348 /*!
43349  * @name Register XCVR_XTAL_CTRL2, field XTAL_ATST_ON[26] (RW)
43350  *
43351  * This is the test mode for the xtal block. When this bit is set 32M clock is
43352  * put on ATST2
43353  */
43354 /*@{*/
43355 /*! @brief Read current value of the XCVR_XTAL_CTRL2_XTAL_ATST_ON field. */
43356 #define XCVR_RD_XTAL_CTRL2_XTAL_ATST_ON(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_XTAL_ATST_ON_MASK) >> XCVR_XTAL_CTRL2_XTAL_ATST_ON_SHIFT)
43357 #define XCVR_BRD_XTAL_CTRL2_XTAL_ATST_ON(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL_CTRL2_XTAL_ATST_ON_SHIFT, XCVR_XTAL_CTRL2_XTAL_ATST_ON_WIDTH))
43358 
43359 /*! @brief Set the XTAL_ATST_ON field to a new value. */
43360 #define XCVR_WR_XTAL_CTRL2_XTAL_ATST_ON(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CTRL2_XTAL_ATST_ON_MASK, XCVR_XTAL_CTRL2_XTAL_ATST_ON(value)))
43361 #define XCVR_BWR_XTAL_CTRL2_XTAL_ATST_ON(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((uint32_t)(value) << XCVR_XTAL_CTRL2_XTAL_ATST_ON_SHIFT), XCVR_XTAL_CTRL2_XTAL_ATST_ON_SHIFT, XCVR_XTAL_CTRL2_XTAL_ATST_ON_WIDTH))
43362 /*@}*/
43363 
43364 /*!
43365  * @name Register XCVR_XTAL_CTRL2, field XTAL_SPARE[31:28] (RW)
43366  *
43367  * Spare Bits for future use
43368  */
43369 /*@{*/
43370 /*! @brief Read current value of the XCVR_XTAL_CTRL2_XTAL_SPARE field. */
43371 #define XCVR_RD_XTAL_CTRL2_XTAL_SPARE(base) ((XCVR_XTAL_CTRL2_REG(base) & XCVR_XTAL_CTRL2_XTAL_SPARE_MASK) >> XCVR_XTAL_CTRL2_XTAL_SPARE_SHIFT)
43372 #define XCVR_BRD_XTAL_CTRL2_XTAL_SPARE(base) (BME_UBFX32(&XCVR_XTAL_CTRL2_REG(base), XCVR_XTAL_CTRL2_XTAL_SPARE_SHIFT, XCVR_XTAL_CTRL2_XTAL_SPARE_WIDTH))
43373 
43374 /*! @brief Set the XTAL_SPARE field to a new value. */
43375 #define XCVR_WR_XTAL_CTRL2_XTAL_SPARE(base, value) (XCVR_RMW_XTAL_CTRL2(base, XCVR_XTAL_CTRL2_XTAL_SPARE_MASK, XCVR_XTAL_CTRL2_XTAL_SPARE(value)))
43376 #define XCVR_BWR_XTAL_CTRL2_XTAL_SPARE(base, value) (BME_BFI32(&XCVR_XTAL_CTRL2_REG(base), ((uint32_t)(value) << XCVR_XTAL_CTRL2_XTAL_SPARE_SHIFT), XCVR_XTAL_CTRL2_XTAL_SPARE_SHIFT, XCVR_XTAL_CTRL2_XTAL_SPARE_WIDTH))
43377 /*@}*/
43378 
43379 /*******************************************************************************
43380  * XCVR_BGAP_CTRL - Bandgap Control
43381  ******************************************************************************/
43382 
43383 /*!
43384  * @brief XCVR_BGAP_CTRL - Bandgap Control (RW)
43385  *
43386  * Reset value: 0x00000087U
43387  */
43388 /*!
43389  * @name Constants and macros for entire XCVR_BGAP_CTRL register
43390  */
43391 /*@{*/
43392 #define XCVR_RD_BGAP_CTRL(base)  (XCVR_BGAP_CTRL_REG(base))
43393 #define XCVR_WR_BGAP_CTRL(base, value) (XCVR_BGAP_CTRL_REG(base) = (value))
43394 #define XCVR_RMW_BGAP_CTRL(base, mask, value) (XCVR_WR_BGAP_CTRL(base, (XCVR_RD_BGAP_CTRL(base) & ~(mask)) | (value)))
43395 #define XCVR_SET_BGAP_CTRL(base, value) (BME_OR32(&XCVR_BGAP_CTRL_REG(base), (uint32_t)(value)))
43396 #define XCVR_CLR_BGAP_CTRL(base, value) (BME_AND32(&XCVR_BGAP_CTRL_REG(base), (uint32_t)(~(value))))
43397 #define XCVR_TOG_BGAP_CTRL(base, value) (BME_XOR32(&XCVR_BGAP_CTRL_REG(base), (uint32_t)(value)))
43398 /*@}*/
43399 
43400 /*
43401  * Constants & macros for individual XCVR_BGAP_CTRL bitfields
43402  */
43403 
43404 /*!
43405  * @name Register XCVR_BGAP_CTRL, field BGAP_CURRENT_TRIM[3:0] (RW)
43406  *
43407  * Trim the 1uA bandgap current
43408  */
43409 /*@{*/
43410 /*! @brief Read current value of the XCVR_BGAP_CTRL_BGAP_CURRENT_TRIM field. */
43411 #define XCVR_RD_BGAP_CTRL_BGAP_CURRENT_TRIM(base) ((XCVR_BGAP_CTRL_REG(base) & XCVR_BGAP_CTRL_BGAP_CURRENT_TRIM_MASK) >> XCVR_BGAP_CTRL_BGAP_CURRENT_TRIM_SHIFT)
43412 #define XCVR_BRD_BGAP_CTRL_BGAP_CURRENT_TRIM(base) (BME_UBFX32(&XCVR_BGAP_CTRL_REG(base), XCVR_BGAP_CTRL_BGAP_CURRENT_TRIM_SHIFT, XCVR_BGAP_CTRL_BGAP_CURRENT_TRIM_WIDTH))
43413 
43414 /*! @brief Set the BGAP_CURRENT_TRIM field to a new value. */
43415 #define XCVR_WR_BGAP_CTRL_BGAP_CURRENT_TRIM(base, value) (XCVR_RMW_BGAP_CTRL(base, XCVR_BGAP_CTRL_BGAP_CURRENT_TRIM_MASK, XCVR_BGAP_CTRL_BGAP_CURRENT_TRIM(value)))
43416 #define XCVR_BWR_BGAP_CTRL_BGAP_CURRENT_TRIM(base, value) (BME_BFI32(&XCVR_BGAP_CTRL_REG(base), ((uint32_t)(value) << XCVR_BGAP_CTRL_BGAP_CURRENT_TRIM_SHIFT), XCVR_BGAP_CTRL_BGAP_CURRENT_TRIM_SHIFT, XCVR_BGAP_CTRL_BGAP_CURRENT_TRIM_WIDTH))
43417 /*@}*/
43418 
43419 /*!
43420  * @name Register XCVR_BGAP_CTRL, field BGAP_VOLTAGE_TRIM[7:4] (RW)
43421  *
43422  * Trim the bandgap voltage to 1V in 4mV steps
43423  */
43424 /*@{*/
43425 /*! @brief Read current value of the XCVR_BGAP_CTRL_BGAP_VOLTAGE_TRIM field. */
43426 #define XCVR_RD_BGAP_CTRL_BGAP_VOLTAGE_TRIM(base) ((XCVR_BGAP_CTRL_REG(base) & XCVR_BGAP_CTRL_BGAP_VOLTAGE_TRIM_MASK) >> XCVR_BGAP_CTRL_BGAP_VOLTAGE_TRIM_SHIFT)
43427 #define XCVR_BRD_BGAP_CTRL_BGAP_VOLTAGE_TRIM(base) (BME_UBFX32(&XCVR_BGAP_CTRL_REG(base), XCVR_BGAP_CTRL_BGAP_VOLTAGE_TRIM_SHIFT, XCVR_BGAP_CTRL_BGAP_VOLTAGE_TRIM_WIDTH))
43428 
43429 /*! @brief Set the BGAP_VOLTAGE_TRIM field to a new value. */
43430 #define XCVR_WR_BGAP_CTRL_BGAP_VOLTAGE_TRIM(base, value) (XCVR_RMW_BGAP_CTRL(base, XCVR_BGAP_CTRL_BGAP_VOLTAGE_TRIM_MASK, XCVR_BGAP_CTRL_BGAP_VOLTAGE_TRIM(value)))
43431 #define XCVR_BWR_BGAP_CTRL_BGAP_VOLTAGE_TRIM(base, value) (BME_BFI32(&XCVR_BGAP_CTRL_REG(base), ((uint32_t)(value) << XCVR_BGAP_CTRL_BGAP_VOLTAGE_TRIM_SHIFT), XCVR_BGAP_CTRL_BGAP_VOLTAGE_TRIM_SHIFT, XCVR_BGAP_CTRL_BGAP_VOLTAGE_TRIM_WIDTH))
43432 /*@}*/
43433 
43434 /*!
43435  * @name Register XCVR_BGAP_CTRL, field BGAP_ATST_SEL[11:8] (RW)
43436  *
43437  * Select what internal signals to bring out to ATST bus. bgap_atst_sel ATST2
43438  * ATST3 0000 1ua Unfiltered bgap Output 0001 2uA Internal X1 node of Bgap 0010 5uA
43439  * Internal X2 node of Bgap 0011 10uA No Connect 0100 1uA ptat No Connect
43440  */
43441 /*@{*/
43442 /*! @brief Read current value of the XCVR_BGAP_CTRL_BGAP_ATST_SEL field. */
43443 #define XCVR_RD_BGAP_CTRL_BGAP_ATST_SEL(base) ((XCVR_BGAP_CTRL_REG(base) & XCVR_BGAP_CTRL_BGAP_ATST_SEL_MASK) >> XCVR_BGAP_CTRL_BGAP_ATST_SEL_SHIFT)
43444 #define XCVR_BRD_BGAP_CTRL_BGAP_ATST_SEL(base) (BME_UBFX32(&XCVR_BGAP_CTRL_REG(base), XCVR_BGAP_CTRL_BGAP_ATST_SEL_SHIFT, XCVR_BGAP_CTRL_BGAP_ATST_SEL_WIDTH))
43445 
43446 /*! @brief Set the BGAP_ATST_SEL field to a new value. */
43447 #define XCVR_WR_BGAP_CTRL_BGAP_ATST_SEL(base, value) (XCVR_RMW_BGAP_CTRL(base, XCVR_BGAP_CTRL_BGAP_ATST_SEL_MASK, XCVR_BGAP_CTRL_BGAP_ATST_SEL(value)))
43448 #define XCVR_BWR_BGAP_CTRL_BGAP_ATST_SEL(base, value) (BME_BFI32(&XCVR_BGAP_CTRL_REG(base), ((uint32_t)(value) << XCVR_BGAP_CTRL_BGAP_ATST_SEL_SHIFT), XCVR_BGAP_CTRL_BGAP_ATST_SEL_SHIFT, XCVR_BGAP_CTRL_BGAP_ATST_SEL_WIDTH))
43449 /*@}*/
43450 
43451 /*!
43452  * @name Register XCVR_BGAP_CTRL, field BGAP_ATST_ON[12] (RW)
43453  *
43454  * This bit enables the test mux for the bangap block. The different internal
43455  * nodes of bandgap are connected to the ATST bus based on bgap_atst_sel bits.
43456  */
43457 /*@{*/
43458 /*! @brief Read current value of the XCVR_BGAP_CTRL_BGAP_ATST_ON field. */
43459 #define XCVR_RD_BGAP_CTRL_BGAP_ATST_ON(base) ((XCVR_BGAP_CTRL_REG(base) & XCVR_BGAP_CTRL_BGAP_ATST_ON_MASK) >> XCVR_BGAP_CTRL_BGAP_ATST_ON_SHIFT)
43460 #define XCVR_BRD_BGAP_CTRL_BGAP_ATST_ON(base) (BME_UBFX32(&XCVR_BGAP_CTRL_REG(base), XCVR_BGAP_CTRL_BGAP_ATST_ON_SHIFT, XCVR_BGAP_CTRL_BGAP_ATST_ON_WIDTH))
43461 
43462 /*! @brief Set the BGAP_ATST_ON field to a new value. */
43463 #define XCVR_WR_BGAP_CTRL_BGAP_ATST_ON(base, value) (XCVR_RMW_BGAP_CTRL(base, XCVR_BGAP_CTRL_BGAP_ATST_ON_MASK, XCVR_BGAP_CTRL_BGAP_ATST_ON(value)))
43464 #define XCVR_BWR_BGAP_CTRL_BGAP_ATST_ON(base, value) (BME_BFI32(&XCVR_BGAP_CTRL_REG(base), ((uint32_t)(value) << XCVR_BGAP_CTRL_BGAP_ATST_ON_SHIFT), XCVR_BGAP_CTRL_BGAP_ATST_ON_SHIFT, XCVR_BGAP_CTRL_BGAP_ATST_ON_WIDTH))
43465 /*@}*/
43466 
43467 /*******************************************************************************
43468  * XCVR_PLL_CTRL - PLL Control Register
43469  ******************************************************************************/
43470 
43471 /*!
43472  * @brief XCVR_PLL_CTRL - PLL Control Register (RW)
43473  *
43474  * Reset value: 0x00000023U
43475  */
43476 /*!
43477  * @name Constants and macros for entire XCVR_PLL_CTRL register
43478  */
43479 /*@{*/
43480 #define XCVR_RD_PLL_CTRL(base)   (XCVR_PLL_CTRL_REG(base))
43481 #define XCVR_WR_PLL_CTRL(base, value) (XCVR_PLL_CTRL_REG(base) = (value))
43482 #define XCVR_RMW_PLL_CTRL(base, mask, value) (XCVR_WR_PLL_CTRL(base, (XCVR_RD_PLL_CTRL(base) & ~(mask)) | (value)))
43483 #define XCVR_SET_PLL_CTRL(base, value) (BME_OR32(&XCVR_PLL_CTRL_REG(base), (uint32_t)(value)))
43484 #define XCVR_CLR_PLL_CTRL(base, value) (BME_AND32(&XCVR_PLL_CTRL_REG(base), (uint32_t)(~(value))))
43485 #define XCVR_TOG_PLL_CTRL(base, value) (BME_XOR32(&XCVR_PLL_CTRL_REG(base), (uint32_t)(value)))
43486 /*@}*/
43487 
43488 /*
43489  * Constants & macros for individual XCVR_PLL_CTRL bitfields
43490  */
43491 
43492 /*!
43493  * @name Register XCVR_PLL_CTRL, field PLL_VCO_BIAS[2:0] (RW)
43494  *
43495  * Progammable current control for the VCO. The VCO current varies from 1.5mA to
43496  * 2.1mA
43497  */
43498 /*@{*/
43499 /*! @brief Read current value of the XCVR_PLL_CTRL_PLL_VCO_BIAS field. */
43500 #define XCVR_RD_PLL_CTRL_PLL_VCO_BIAS(base) ((XCVR_PLL_CTRL_REG(base) & XCVR_PLL_CTRL_PLL_VCO_BIAS_MASK) >> XCVR_PLL_CTRL_PLL_VCO_BIAS_SHIFT)
43501 #define XCVR_BRD_PLL_CTRL_PLL_VCO_BIAS(base) (BME_UBFX32(&XCVR_PLL_CTRL_REG(base), XCVR_PLL_CTRL_PLL_VCO_BIAS_SHIFT, XCVR_PLL_CTRL_PLL_VCO_BIAS_WIDTH))
43502 
43503 /*! @brief Set the PLL_VCO_BIAS field to a new value. */
43504 #define XCVR_WR_PLL_CTRL_PLL_VCO_BIAS(base, value) (XCVR_RMW_PLL_CTRL(base, XCVR_PLL_CTRL_PLL_VCO_BIAS_MASK, XCVR_PLL_CTRL_PLL_VCO_BIAS(value)))
43505 #define XCVR_BWR_PLL_CTRL_PLL_VCO_BIAS(base, value) (BME_BFI32(&XCVR_PLL_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_CTRL_PLL_VCO_BIAS_SHIFT), XCVR_PLL_CTRL_PLL_VCO_BIAS_SHIFT, XCVR_PLL_CTRL_PLL_VCO_BIAS_WIDTH))
43506 /*@}*/
43507 
43508 /*!
43509  * @name Register XCVR_PLL_CTRL, field PLL_LFILT_CNTL[6:4] (RW)
43510  *
43511  * Program the resistors in the loop filter to control the bandwith.
43512  * Pll_lfilt_cntl First Pole Resistor Second Pole Resistor 000 25.6K 26K 001 20.8K 26K 010
43513  * 15.4K 26K 011 10.3K 26K 100 25.6K 100 101 20.8K 100 110 15.4K 100 111 10.3K 100
43514  */
43515 /*@{*/
43516 /*! @brief Read current value of the XCVR_PLL_CTRL_PLL_LFILT_CNTL field. */
43517 #define XCVR_RD_PLL_CTRL_PLL_LFILT_CNTL(base) ((XCVR_PLL_CTRL_REG(base) & XCVR_PLL_CTRL_PLL_LFILT_CNTL_MASK) >> XCVR_PLL_CTRL_PLL_LFILT_CNTL_SHIFT)
43518 #define XCVR_BRD_PLL_CTRL_PLL_LFILT_CNTL(base) (BME_UBFX32(&XCVR_PLL_CTRL_REG(base), XCVR_PLL_CTRL_PLL_LFILT_CNTL_SHIFT, XCVR_PLL_CTRL_PLL_LFILT_CNTL_WIDTH))
43519 
43520 /*! @brief Set the PLL_LFILT_CNTL field to a new value. */
43521 #define XCVR_WR_PLL_CTRL_PLL_LFILT_CNTL(base, value) (XCVR_RMW_PLL_CTRL(base, XCVR_PLL_CTRL_PLL_LFILT_CNTL_MASK, XCVR_PLL_CTRL_PLL_LFILT_CNTL(value)))
43522 #define XCVR_BWR_PLL_CTRL_PLL_LFILT_CNTL(base, value) (BME_BFI32(&XCVR_PLL_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_CTRL_PLL_LFILT_CNTL_SHIFT), XCVR_PLL_CTRL_PLL_LFILT_CNTL_SHIFT, XCVR_PLL_CTRL_PLL_LFILT_CNTL_WIDTH))
43523 /*@}*/
43524 
43525 /*!
43526  * @name Register XCVR_PLL_CTRL, field PLL_REG_SUPPLY[11:8] (RW)
43527  *
43528  * Regulator trim bit to change the outputvoltage from 1.05 to 1.4V
43529  *
43530  * Values:
43531  * - 0b0000 - 1.2V
43532  * - 0b0001 - 1.05V
43533  * - 0b0010 - 1.275V
43534  * - 0b0011 - 1.3V
43535  */
43536 /*@{*/
43537 /*! @brief Read current value of the XCVR_PLL_CTRL_PLL_REG_SUPPLY field. */
43538 #define XCVR_RD_PLL_CTRL_PLL_REG_SUPPLY(base) ((XCVR_PLL_CTRL_REG(base) & XCVR_PLL_CTRL_PLL_REG_SUPPLY_MASK) >> XCVR_PLL_CTRL_PLL_REG_SUPPLY_SHIFT)
43539 #define XCVR_BRD_PLL_CTRL_PLL_REG_SUPPLY(base) (BME_UBFX32(&XCVR_PLL_CTRL_REG(base), XCVR_PLL_CTRL_PLL_REG_SUPPLY_SHIFT, XCVR_PLL_CTRL_PLL_REG_SUPPLY_WIDTH))
43540 
43541 /*! @brief Set the PLL_REG_SUPPLY field to a new value. */
43542 #define XCVR_WR_PLL_CTRL_PLL_REG_SUPPLY(base, value) (XCVR_RMW_PLL_CTRL(base, XCVR_PLL_CTRL_PLL_REG_SUPPLY_MASK, XCVR_PLL_CTRL_PLL_REG_SUPPLY(value)))
43543 #define XCVR_BWR_PLL_CTRL_PLL_REG_SUPPLY(base, value) (BME_BFI32(&XCVR_PLL_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_CTRL_PLL_REG_SUPPLY_SHIFT), XCVR_PLL_CTRL_PLL_REG_SUPPLY_SHIFT, XCVR_PLL_CTRL_PLL_REG_SUPPLY_WIDTH))
43544 /*@}*/
43545 
43546 /*!
43547  * @name Register XCVR_PLL_CTRL, field PLL_REG_BYPASS_ON[16] (RW)
43548  *
43549  * This register bit determines if the regulator is in bypass mode. When in
43550  * bypass mode, the external voltage applied to the input of the regulator is
43551  * presented at the regulator output.
43552  */
43553 /*@{*/
43554 /*! @brief Read current value of the XCVR_PLL_CTRL_PLL_REG_BYPASS_ON field. */
43555 #define XCVR_RD_PLL_CTRL_PLL_REG_BYPASS_ON(base) ((XCVR_PLL_CTRL_REG(base) & XCVR_PLL_CTRL_PLL_REG_BYPASS_ON_MASK) >> XCVR_PLL_CTRL_PLL_REG_BYPASS_ON_SHIFT)
43556 #define XCVR_BRD_PLL_CTRL_PLL_REG_BYPASS_ON(base) (BME_UBFX32(&XCVR_PLL_CTRL_REG(base), XCVR_PLL_CTRL_PLL_REG_BYPASS_ON_SHIFT, XCVR_PLL_CTRL_PLL_REG_BYPASS_ON_WIDTH))
43557 
43558 /*! @brief Set the PLL_REG_BYPASS_ON field to a new value. */
43559 #define XCVR_WR_PLL_CTRL_PLL_REG_BYPASS_ON(base, value) (XCVR_RMW_PLL_CTRL(base, XCVR_PLL_CTRL_PLL_REG_BYPASS_ON_MASK, XCVR_PLL_CTRL_PLL_REG_BYPASS_ON(value)))
43560 #define XCVR_BWR_PLL_CTRL_PLL_REG_BYPASS_ON(base, value) (BME_BFI32(&XCVR_PLL_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_CTRL_PLL_REG_BYPASS_ON_SHIFT), XCVR_PLL_CTRL_PLL_REG_BYPASS_ON_SHIFT, XCVR_PLL_CTRL_PLL_REG_BYPASS_ON_WIDTH))
43561 /*@}*/
43562 
43563 /*!
43564  * @name Register XCVR_PLL_CTRL, field PLL_VCO_LDO_BYPASS[17] (RW)
43565  *
43566  * This register bit determines if the regulator is in bypass mode. When in
43567  * bypass mode, the external voltage applied to the input of the regulator is
43568  * presented at the regulator output.
43569  */
43570 /*@{*/
43571 /*! @brief Read current value of the XCVR_PLL_CTRL_PLL_VCO_LDO_BYPASS field. */
43572 #define XCVR_RD_PLL_CTRL_PLL_VCO_LDO_BYPASS(base) ((XCVR_PLL_CTRL_REG(base) & XCVR_PLL_CTRL_PLL_VCO_LDO_BYPASS_MASK) >> XCVR_PLL_CTRL_PLL_VCO_LDO_BYPASS_SHIFT)
43573 #define XCVR_BRD_PLL_CTRL_PLL_VCO_LDO_BYPASS(base) (BME_UBFX32(&XCVR_PLL_CTRL_REG(base), XCVR_PLL_CTRL_PLL_VCO_LDO_BYPASS_SHIFT, XCVR_PLL_CTRL_PLL_VCO_LDO_BYPASS_WIDTH))
43574 
43575 /*! @brief Set the PLL_VCO_LDO_BYPASS field to a new value. */
43576 #define XCVR_WR_PLL_CTRL_PLL_VCO_LDO_BYPASS(base, value) (XCVR_RMW_PLL_CTRL(base, XCVR_PLL_CTRL_PLL_VCO_LDO_BYPASS_MASK, XCVR_PLL_CTRL_PLL_VCO_LDO_BYPASS(value)))
43577 #define XCVR_BWR_PLL_CTRL_PLL_VCO_LDO_BYPASS(base, value) (BME_BFI32(&XCVR_PLL_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_CTRL_PLL_VCO_LDO_BYPASS_SHIFT), XCVR_PLL_CTRL_PLL_VCO_LDO_BYPASS_SHIFT, XCVR_PLL_CTRL_PLL_VCO_LDO_BYPASS_WIDTH))
43578 /*@}*/
43579 
43580 /*!
43581  * @name Register XCVR_PLL_CTRL, field HPM_BIAS[30:24] (RW)
43582  *
43583  * Provides a (-64/+63 x 976.56 Hz) range of steps to adjust the HPM Array
43584  * Mid-Point during modulation
43585  */
43586 /*@{*/
43587 /*! @brief Read current value of the XCVR_PLL_CTRL_HPM_BIAS field. */
43588 #define XCVR_RD_PLL_CTRL_HPM_BIAS(base) ((XCVR_PLL_CTRL_REG(base) & XCVR_PLL_CTRL_HPM_BIAS_MASK) >> XCVR_PLL_CTRL_HPM_BIAS_SHIFT)
43589 #define XCVR_BRD_PLL_CTRL_HPM_BIAS(base) (BME_UBFX32(&XCVR_PLL_CTRL_REG(base), XCVR_PLL_CTRL_HPM_BIAS_SHIFT, XCVR_PLL_CTRL_HPM_BIAS_WIDTH))
43590 
43591 /*! @brief Set the HPM_BIAS field to a new value. */
43592 #define XCVR_WR_PLL_CTRL_HPM_BIAS(base, value) (XCVR_RMW_PLL_CTRL(base, XCVR_PLL_CTRL_HPM_BIAS_MASK, XCVR_PLL_CTRL_HPM_BIAS(value)))
43593 #define XCVR_BWR_PLL_CTRL_HPM_BIAS(base, value) (BME_BFI32(&XCVR_PLL_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_CTRL_HPM_BIAS_SHIFT), XCVR_PLL_CTRL_HPM_BIAS_SHIFT, XCVR_PLL_CTRL_HPM_BIAS_WIDTH))
43594 /*@}*/
43595 
43596 /*!
43597  * @name Register XCVR_PLL_CTRL, field PLL_VCO_SPARE7[31] (RW)
43598  *
43599  * Spare Bit for future use
43600  */
43601 /*@{*/
43602 /*! @brief Read current value of the XCVR_PLL_CTRL_PLL_VCO_SPARE7 field. */
43603 #define XCVR_RD_PLL_CTRL_PLL_VCO_SPARE7(base) ((XCVR_PLL_CTRL_REG(base) & XCVR_PLL_CTRL_PLL_VCO_SPARE7_MASK) >> XCVR_PLL_CTRL_PLL_VCO_SPARE7_SHIFT)
43604 #define XCVR_BRD_PLL_CTRL_PLL_VCO_SPARE7(base) (BME_UBFX32(&XCVR_PLL_CTRL_REG(base), XCVR_PLL_CTRL_PLL_VCO_SPARE7_SHIFT, XCVR_PLL_CTRL_PLL_VCO_SPARE7_WIDTH))
43605 
43606 /*! @brief Set the PLL_VCO_SPARE7 field to a new value. */
43607 #define XCVR_WR_PLL_CTRL_PLL_VCO_SPARE7(base, value) (XCVR_RMW_PLL_CTRL(base, XCVR_PLL_CTRL_PLL_VCO_SPARE7_MASK, XCVR_PLL_CTRL_PLL_VCO_SPARE7(value)))
43608 #define XCVR_BWR_PLL_CTRL_PLL_VCO_SPARE7(base, value) (BME_BFI32(&XCVR_PLL_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_CTRL_PLL_VCO_SPARE7_SHIFT), XCVR_PLL_CTRL_PLL_VCO_SPARE7_SHIFT, XCVR_PLL_CTRL_PLL_VCO_SPARE7_WIDTH))
43609 /*@}*/
43610 
43611 /*******************************************************************************
43612  * XCVR_PLL_CTRL2 - PLL Control Register 2
43613  ******************************************************************************/
43614 
43615 /*!
43616  * @brief XCVR_PLL_CTRL2 - PLL Control Register 2 (RW)
43617  *
43618  * Reset value: 0x00000004U
43619  */
43620 /*!
43621  * @name Constants and macros for entire XCVR_PLL_CTRL2 register
43622  */
43623 /*@{*/
43624 #define XCVR_RD_PLL_CTRL2(base)  (XCVR_PLL_CTRL2_REG(base))
43625 #define XCVR_WR_PLL_CTRL2(base, value) (XCVR_PLL_CTRL2_REG(base) = (value))
43626 #define XCVR_RMW_PLL_CTRL2(base, mask, value) (XCVR_WR_PLL_CTRL2(base, (XCVR_RD_PLL_CTRL2(base) & ~(mask)) | (value)))
43627 #define XCVR_SET_PLL_CTRL2(base, value) (BME_OR32(&XCVR_PLL_CTRL2_REG(base), (uint32_t)(value)))
43628 #define XCVR_CLR_PLL_CTRL2(base, value) (BME_AND32(&XCVR_PLL_CTRL2_REG(base), (uint32_t)(~(value))))
43629 #define XCVR_TOG_PLL_CTRL2(base, value) (BME_XOR32(&XCVR_PLL_CTRL2_REG(base), (uint32_t)(value)))
43630 /*@}*/
43631 
43632 /*
43633  * Constants & macros for individual XCVR_PLL_CTRL2 bitfields
43634  */
43635 
43636 /*!
43637  * @name Register XCVR_PLL_CTRL2, field PLL_VCO_KV[2:0] (RW)
43638  *
43639  * These bits control the gain of the VCO. This is an additioanl knob to control
43640  * the loop bandwitch of the PLL. All 0's correspond to minimum KV and all 1's
43641  * correspond to max KV programmable
43642  */
43643 /*@{*/
43644 /*! @brief Read current value of the XCVR_PLL_CTRL2_PLL_VCO_KV field. */
43645 #define XCVR_RD_PLL_CTRL2_PLL_VCO_KV(base) ((XCVR_PLL_CTRL2_REG(base) & XCVR_PLL_CTRL2_PLL_VCO_KV_MASK) >> XCVR_PLL_CTRL2_PLL_VCO_KV_SHIFT)
43646 #define XCVR_BRD_PLL_CTRL2_PLL_VCO_KV(base) (BME_UBFX32(&XCVR_PLL_CTRL2_REG(base), XCVR_PLL_CTRL2_PLL_VCO_KV_SHIFT, XCVR_PLL_CTRL2_PLL_VCO_KV_WIDTH))
43647 
43648 /*! @brief Set the PLL_VCO_KV field to a new value. */
43649 #define XCVR_WR_PLL_CTRL2_PLL_VCO_KV(base, value) (XCVR_RMW_PLL_CTRL2(base, XCVR_PLL_CTRL2_PLL_VCO_KV_MASK, XCVR_PLL_CTRL2_PLL_VCO_KV(value)))
43650 #define XCVR_BWR_PLL_CTRL2_PLL_VCO_KV(base, value) (BME_BFI32(&XCVR_PLL_CTRL2_REG(base), ((uint32_t)(value) << XCVR_PLL_CTRL2_PLL_VCO_KV_SHIFT), XCVR_PLL_CTRL2_PLL_VCO_KV_SHIFT, XCVR_PLL_CTRL2_PLL_VCO_KV_WIDTH))
43651 /*@}*/
43652 
43653 /*!
43654  * @name Register XCVR_PLL_CTRL2, field PLL_KMOD_SLOPE[3] (RW)
43655  *
43656  * This bit controls the slope of the highport capacitor bank. When this bit is
43657  * set the Kmod slope changes from 10Khz to 15Khz
43658  */
43659 /*@{*/
43660 /*! @brief Read current value of the XCVR_PLL_CTRL2_PLL_KMOD_SLOPE field. */
43661 #define XCVR_RD_PLL_CTRL2_PLL_KMOD_SLOPE(base) ((XCVR_PLL_CTRL2_REG(base) & XCVR_PLL_CTRL2_PLL_KMOD_SLOPE_MASK) >> XCVR_PLL_CTRL2_PLL_KMOD_SLOPE_SHIFT)
43662 #define XCVR_BRD_PLL_CTRL2_PLL_KMOD_SLOPE(base) (BME_UBFX32(&XCVR_PLL_CTRL2_REG(base), XCVR_PLL_CTRL2_PLL_KMOD_SLOPE_SHIFT, XCVR_PLL_CTRL2_PLL_KMOD_SLOPE_WIDTH))
43663 
43664 /*! @brief Set the PLL_KMOD_SLOPE field to a new value. */
43665 #define XCVR_WR_PLL_CTRL2_PLL_KMOD_SLOPE(base, value) (XCVR_RMW_PLL_CTRL2(base, XCVR_PLL_CTRL2_PLL_KMOD_SLOPE_MASK, XCVR_PLL_CTRL2_PLL_KMOD_SLOPE(value)))
43666 #define XCVR_BWR_PLL_CTRL2_PLL_KMOD_SLOPE(base, value) (BME_BFI32(&XCVR_PLL_CTRL2_REG(base), ((uint32_t)(value) << XCVR_PLL_CTRL2_PLL_KMOD_SLOPE_SHIFT), XCVR_PLL_CTRL2_PLL_KMOD_SLOPE_SHIFT, XCVR_PLL_CTRL2_PLL_KMOD_SLOPE_WIDTH))
43667 /*@}*/
43668 
43669 /*!
43670  * @name Register XCVR_PLL_CTRL2, field PLL_VCO_REG_SUPPLY[5:4] (RW)
43671  *
43672  * Regulator trim bits to change the outputvoltage from 1.15 to 1.3V
43673  *
43674  * Values:
43675  * - 0b00 - 1.15V
43676  * - 0b01 - 1.2V
43677  */
43678 /*@{*/
43679 /*! @brief Read current value of the XCVR_PLL_CTRL2_PLL_VCO_REG_SUPPLY field. */
43680 #define XCVR_RD_PLL_CTRL2_PLL_VCO_REG_SUPPLY(base) ((XCVR_PLL_CTRL2_REG(base) & XCVR_PLL_CTRL2_PLL_VCO_REG_SUPPLY_MASK) >> XCVR_PLL_CTRL2_PLL_VCO_REG_SUPPLY_SHIFT)
43681 #define XCVR_BRD_PLL_CTRL2_PLL_VCO_REG_SUPPLY(base) (BME_UBFX32(&XCVR_PLL_CTRL2_REG(base), XCVR_PLL_CTRL2_PLL_VCO_REG_SUPPLY_SHIFT, XCVR_PLL_CTRL2_PLL_VCO_REG_SUPPLY_WIDTH))
43682 
43683 /*! @brief Set the PLL_VCO_REG_SUPPLY field to a new value. */
43684 #define XCVR_WR_PLL_CTRL2_PLL_VCO_REG_SUPPLY(base, value) (XCVR_RMW_PLL_CTRL2(base, XCVR_PLL_CTRL2_PLL_VCO_REG_SUPPLY_MASK, XCVR_PLL_CTRL2_PLL_VCO_REG_SUPPLY(value)))
43685 #define XCVR_BWR_PLL_CTRL2_PLL_VCO_REG_SUPPLY(base, value) (BME_BFI32(&XCVR_PLL_CTRL2_REG(base), ((uint32_t)(value) << XCVR_PLL_CTRL2_PLL_VCO_REG_SUPPLY_SHIFT), XCVR_PLL_CTRL2_PLL_VCO_REG_SUPPLY_SHIFT, XCVR_PLL_CTRL2_PLL_VCO_REG_SUPPLY_WIDTH))
43686 /*@}*/
43687 
43688 /*!
43689  * @name Register XCVR_PLL_CTRL2, field PLL_TMUX_ON[8] (RW)
43690  *
43691  * This bit enables the testmux inside the PLL and the different internal nodes
43692  * are connected to ATST bus based on the pll_tmux_sel settings
43693  */
43694 /*@{*/
43695 /*! @brief Read current value of the XCVR_PLL_CTRL2_PLL_TMUX_ON field. */
43696 #define XCVR_RD_PLL_CTRL2_PLL_TMUX_ON(base) ((XCVR_PLL_CTRL2_REG(base) & XCVR_PLL_CTRL2_PLL_TMUX_ON_MASK) >> XCVR_PLL_CTRL2_PLL_TMUX_ON_SHIFT)
43697 #define XCVR_BRD_PLL_CTRL2_PLL_TMUX_ON(base) (BME_UBFX32(&XCVR_PLL_CTRL2_REG(base), XCVR_PLL_CTRL2_PLL_TMUX_ON_SHIFT, XCVR_PLL_CTRL2_PLL_TMUX_ON_WIDTH))
43698 
43699 /*! @brief Set the PLL_TMUX_ON field to a new value. */
43700 #define XCVR_WR_PLL_CTRL2_PLL_TMUX_ON(base, value) (XCVR_RMW_PLL_CTRL2(base, XCVR_PLL_CTRL2_PLL_TMUX_ON_MASK, XCVR_PLL_CTRL2_PLL_TMUX_ON(value)))
43701 #define XCVR_BWR_PLL_CTRL2_PLL_TMUX_ON(base, value) (BME_BFI32(&XCVR_PLL_CTRL2_REG(base), ((uint32_t)(value) << XCVR_PLL_CTRL2_PLL_TMUX_ON_SHIFT), XCVR_PLL_CTRL2_PLL_TMUX_ON_SHIFT, XCVR_PLL_CTRL2_PLL_TMUX_ON_WIDTH))
43702 /*@}*/
43703 
43704 /*******************************************************************************
43705  * XCVR_PLL_TEST_CTRL - PLL Test Control
43706  ******************************************************************************/
43707 
43708 /*!
43709  * @brief XCVR_PLL_TEST_CTRL - PLL Test Control (RW)
43710  *
43711  * Reset value: 0x00000000U
43712  */
43713 /*!
43714  * @name Constants and macros for entire XCVR_PLL_TEST_CTRL register
43715  */
43716 /*@{*/
43717 #define XCVR_RD_PLL_TEST_CTRL(base) (XCVR_PLL_TEST_CTRL_REG(base))
43718 #define XCVR_WR_PLL_TEST_CTRL(base, value) (XCVR_PLL_TEST_CTRL_REG(base) = (value))
43719 #define XCVR_RMW_PLL_TEST_CTRL(base, mask, value) (XCVR_WR_PLL_TEST_CTRL(base, (XCVR_RD_PLL_TEST_CTRL(base) & ~(mask)) | (value)))
43720 #define XCVR_SET_PLL_TEST_CTRL(base, value) (BME_OR32(&XCVR_PLL_TEST_CTRL_REG(base), (uint32_t)(value)))
43721 #define XCVR_CLR_PLL_TEST_CTRL(base, value) (BME_AND32(&XCVR_PLL_TEST_CTRL_REG(base), (uint32_t)(~(value))))
43722 #define XCVR_TOG_PLL_TEST_CTRL(base, value) (BME_XOR32(&XCVR_PLL_TEST_CTRL_REG(base), (uint32_t)(value)))
43723 /*@}*/
43724 
43725 /*
43726  * Constants & macros for individual XCVR_PLL_TEST_CTRL bitfields
43727  */
43728 
43729 /*!
43730  * @name Register XCVR_PLL_TEST_CTRL, field PLL_TMUX_SEL[1:0] (RW)
43731  *
43732  * Select what internal signals to bring out to ATST pins. PLL_TMUX_ON needs to
43733  * be set. register setting ATST0 ATST1 ATST2 ATST3 00 precharge_filt xor_out
43734  * pll_ref_xtal pll_ref_xtal_b 01 pll_sigma_delta_clk pll_loop_div_count[0]
43735  * pll_loop_div_count[1] pll_loop_div_count[2] 10 pll_loop_div_count[3]
43736  * pll_loop_div_count[4] pll_loop_div_count[8] No Connect 11 pll_ripple_counter_override_clk No
43737  * Connect No Connect No Connect
43738  */
43739 /*@{*/
43740 /*! @brief Read current value of the XCVR_PLL_TEST_CTRL_PLL_TMUX_SEL field. */
43741 #define XCVR_RD_PLL_TEST_CTRL_PLL_TMUX_SEL(base) ((XCVR_PLL_TEST_CTRL_REG(base) & XCVR_PLL_TEST_CTRL_PLL_TMUX_SEL_MASK) >> XCVR_PLL_TEST_CTRL_PLL_TMUX_SEL_SHIFT)
43742 #define XCVR_BRD_PLL_TEST_CTRL_PLL_TMUX_SEL(base) (BME_UBFX32(&XCVR_PLL_TEST_CTRL_REG(base), XCVR_PLL_TEST_CTRL_PLL_TMUX_SEL_SHIFT, XCVR_PLL_TEST_CTRL_PLL_TMUX_SEL_WIDTH))
43743 
43744 /*! @brief Set the PLL_TMUX_SEL field to a new value. */
43745 #define XCVR_WR_PLL_TEST_CTRL_PLL_TMUX_SEL(base, value) (XCVR_RMW_PLL_TEST_CTRL(base, XCVR_PLL_TEST_CTRL_PLL_TMUX_SEL_MASK, XCVR_PLL_TEST_CTRL_PLL_TMUX_SEL(value)))
43746 #define XCVR_BWR_PLL_TEST_CTRL_PLL_TMUX_SEL(base, value) (BME_BFI32(&XCVR_PLL_TEST_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_TEST_CTRL_PLL_TMUX_SEL_SHIFT), XCVR_PLL_TEST_CTRL_PLL_TMUX_SEL_SHIFT, XCVR_PLL_TEST_CTRL_PLL_TMUX_SEL_WIDTH))
43747 /*@}*/
43748 
43749 /*!
43750  * @name Register XCVR_PLL_TEST_CTRL, field PLL_VCO_REG_ATST[5:4] (RW)
43751  *
43752  * These bits determine what internal signals are connected to the ATST bus
43753  * register setting ATST0 00 No Connect 01 vout 10 vin feedback 11 vbias
43754  */
43755 /*@{*/
43756 /*! @brief Read current value of the XCVR_PLL_TEST_CTRL_PLL_VCO_REG_ATST field. */
43757 #define XCVR_RD_PLL_TEST_CTRL_PLL_VCO_REG_ATST(base) ((XCVR_PLL_TEST_CTRL_REG(base) & XCVR_PLL_TEST_CTRL_PLL_VCO_REG_ATST_MASK) >> XCVR_PLL_TEST_CTRL_PLL_VCO_REG_ATST_SHIFT)
43758 #define XCVR_BRD_PLL_TEST_CTRL_PLL_VCO_REG_ATST(base) (BME_UBFX32(&XCVR_PLL_TEST_CTRL_REG(base), XCVR_PLL_TEST_CTRL_PLL_VCO_REG_ATST_SHIFT, XCVR_PLL_TEST_CTRL_PLL_VCO_REG_ATST_WIDTH))
43759 
43760 /*! @brief Set the PLL_VCO_REG_ATST field to a new value. */
43761 #define XCVR_WR_PLL_TEST_CTRL_PLL_VCO_REG_ATST(base, value) (XCVR_RMW_PLL_TEST_CTRL(base, XCVR_PLL_TEST_CTRL_PLL_VCO_REG_ATST_MASK, XCVR_PLL_TEST_CTRL_PLL_VCO_REG_ATST(value)))
43762 #define XCVR_BWR_PLL_TEST_CTRL_PLL_VCO_REG_ATST(base, value) (BME_BFI32(&XCVR_PLL_TEST_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_TEST_CTRL_PLL_VCO_REG_ATST_SHIFT), XCVR_PLL_TEST_CTRL_PLL_VCO_REG_ATST_SHIFT, XCVR_PLL_TEST_CTRL_PLL_VCO_REG_ATST_WIDTH))
43763 /*@}*/
43764 
43765 /*!
43766  * @name Register XCVR_PLL_TEST_CTRL, field PLL_REG_ATST_SEL[9:8] (RW)
43767  *
43768  * These bits control the what internal regualtor signals are connected to the
43769  * ATST bus. register setting ATST0 00 No Connect 01 vout 10 vin feedback 11 vbias
43770  */
43771 /*@{*/
43772 /*! @brief Read current value of the XCVR_PLL_TEST_CTRL_PLL_REG_ATST_SEL field. */
43773 #define XCVR_RD_PLL_TEST_CTRL_PLL_REG_ATST_SEL(base) ((XCVR_PLL_TEST_CTRL_REG(base) & XCVR_PLL_TEST_CTRL_PLL_REG_ATST_SEL_MASK) >> XCVR_PLL_TEST_CTRL_PLL_REG_ATST_SEL_SHIFT)
43774 #define XCVR_BRD_PLL_TEST_CTRL_PLL_REG_ATST_SEL(base) (BME_UBFX32(&XCVR_PLL_TEST_CTRL_REG(base), XCVR_PLL_TEST_CTRL_PLL_REG_ATST_SEL_SHIFT, XCVR_PLL_TEST_CTRL_PLL_REG_ATST_SEL_WIDTH))
43775 
43776 /*! @brief Set the PLL_REG_ATST_SEL field to a new value. */
43777 #define XCVR_WR_PLL_TEST_CTRL_PLL_REG_ATST_SEL(base, value) (XCVR_RMW_PLL_TEST_CTRL(base, XCVR_PLL_TEST_CTRL_PLL_REG_ATST_SEL_MASK, XCVR_PLL_TEST_CTRL_PLL_REG_ATST_SEL(value)))
43778 #define XCVR_BWR_PLL_TEST_CTRL_PLL_REG_ATST_SEL(base, value) (BME_BFI32(&XCVR_PLL_TEST_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_TEST_CTRL_PLL_REG_ATST_SEL_SHIFT), XCVR_PLL_TEST_CTRL_PLL_REG_ATST_SEL_SHIFT, XCVR_PLL_TEST_CTRL_PLL_REG_ATST_SEL_WIDTH))
43779 /*@}*/
43780 
43781 /*!
43782  * @name Register XCVR_PLL_TEST_CTRL, field PLL_VCO_TEST_CLK_MODE[12] (RW)
43783  *
43784  * test mode for the VCO
43785  */
43786 /*@{*/
43787 /*! @brief Read current value of the XCVR_PLL_TEST_CTRL_PLL_VCO_TEST_CLK_MODE field. */
43788 #define XCVR_RD_PLL_TEST_CTRL_PLL_VCO_TEST_CLK_MODE(base) ((XCVR_PLL_TEST_CTRL_REG(base) & XCVR_PLL_TEST_CTRL_PLL_VCO_TEST_CLK_MODE_MASK) >> XCVR_PLL_TEST_CTRL_PLL_VCO_TEST_CLK_MODE_SHIFT)
43789 #define XCVR_BRD_PLL_TEST_CTRL_PLL_VCO_TEST_CLK_MODE(base) (BME_UBFX32(&XCVR_PLL_TEST_CTRL_REG(base), XCVR_PLL_TEST_CTRL_PLL_VCO_TEST_CLK_MODE_SHIFT, XCVR_PLL_TEST_CTRL_PLL_VCO_TEST_CLK_MODE_WIDTH))
43790 
43791 /*! @brief Set the PLL_VCO_TEST_CLK_MODE field to a new value. */
43792 #define XCVR_WR_PLL_TEST_CTRL_PLL_VCO_TEST_CLK_MODE(base, value) (XCVR_RMW_PLL_TEST_CTRL(base, XCVR_PLL_TEST_CTRL_PLL_VCO_TEST_CLK_MODE_MASK, XCVR_PLL_TEST_CTRL_PLL_VCO_TEST_CLK_MODE(value)))
43793 #define XCVR_BWR_PLL_TEST_CTRL_PLL_VCO_TEST_CLK_MODE(base, value) (BME_BFI32(&XCVR_PLL_TEST_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_TEST_CTRL_PLL_VCO_TEST_CLK_MODE_SHIFT), XCVR_PLL_TEST_CTRL_PLL_VCO_TEST_CLK_MODE_SHIFT, XCVR_PLL_TEST_CTRL_PLL_VCO_TEST_CLK_MODE_WIDTH))
43794 /*@}*/
43795 
43796 /*!
43797  * @name Register XCVR_PLL_TEST_CTRL, field PLL_FORCE_VTUNE_EXTERNALLY[13] (RW)
43798  *
43799  * Force VTUNE externally
43800  */
43801 /*@{*/
43802 /*! @brief Read current value of the XCVR_PLL_TEST_CTRL_PLL_FORCE_VTUNE_EXTERNALLY field. */
43803 #define XCVR_RD_PLL_TEST_CTRL_PLL_FORCE_VTUNE_EXTERNALLY(base) ((XCVR_PLL_TEST_CTRL_REG(base) & XCVR_PLL_TEST_CTRL_PLL_FORCE_VTUNE_EXTERNALLY_MASK) >> XCVR_PLL_TEST_CTRL_PLL_FORCE_VTUNE_EXTERNALLY_SHIFT)
43804 #define XCVR_BRD_PLL_TEST_CTRL_PLL_FORCE_VTUNE_EXTERNALLY(base) (BME_UBFX32(&XCVR_PLL_TEST_CTRL_REG(base), XCVR_PLL_TEST_CTRL_PLL_FORCE_VTUNE_EXTERNALLY_SHIFT, XCVR_PLL_TEST_CTRL_PLL_FORCE_VTUNE_EXTERNALLY_WIDTH))
43805 
43806 /*! @brief Set the PLL_FORCE_VTUNE_EXTERNALLY field to a new value. */
43807 #define XCVR_WR_PLL_TEST_CTRL_PLL_FORCE_VTUNE_EXTERNALLY(base, value) (XCVR_RMW_PLL_TEST_CTRL(base, XCVR_PLL_TEST_CTRL_PLL_FORCE_VTUNE_EXTERNALLY_MASK, XCVR_PLL_TEST_CTRL_PLL_FORCE_VTUNE_EXTERNALLY(value)))
43808 #define XCVR_BWR_PLL_TEST_CTRL_PLL_FORCE_VTUNE_EXTERNALLY(base, value) (BME_BFI32(&XCVR_PLL_TEST_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_TEST_CTRL_PLL_FORCE_VTUNE_EXTERNALLY_SHIFT), XCVR_PLL_TEST_CTRL_PLL_FORCE_VTUNE_EXTERNALLY_SHIFT, XCVR_PLL_TEST_CTRL_PLL_FORCE_VTUNE_EXTERNALLY_WIDTH))
43809 /*@}*/
43810 
43811 /*!
43812  * @name Register XCVR_PLL_TEST_CTRL, field PLL_RIPPLE_COUNTER_TEST_MODE[14] (RW)
43813  *
43814  * PLL Ripple Counter Test Mode
43815  */
43816 /*@{*/
43817 /*! @brief Read current value of the XCVR_PLL_TEST_CTRL_PLL_RIPPLE_COUNTER_TEST_MODE field. */
43818 #define XCVR_RD_PLL_TEST_CTRL_PLL_RIPPLE_COUNTER_TEST_MODE(base) ((XCVR_PLL_TEST_CTRL_REG(base) & XCVR_PLL_TEST_CTRL_PLL_RIPPLE_COUNTER_TEST_MODE_MASK) >> XCVR_PLL_TEST_CTRL_PLL_RIPPLE_COUNTER_TEST_MODE_SHIFT)
43819 #define XCVR_BRD_PLL_TEST_CTRL_PLL_RIPPLE_COUNTER_TEST_MODE(base) (BME_UBFX32(&XCVR_PLL_TEST_CTRL_REG(base), XCVR_PLL_TEST_CTRL_PLL_RIPPLE_COUNTER_TEST_MODE_SHIFT, XCVR_PLL_TEST_CTRL_PLL_RIPPLE_COUNTER_TEST_MODE_WIDTH))
43820 
43821 /*! @brief Set the PLL_RIPPLE_COUNTER_TEST_MODE field to a new value. */
43822 #define XCVR_WR_PLL_TEST_CTRL_PLL_RIPPLE_COUNTER_TEST_MODE(base, value) (XCVR_RMW_PLL_TEST_CTRL(base, XCVR_PLL_TEST_CTRL_PLL_RIPPLE_COUNTER_TEST_MODE_MASK, XCVR_PLL_TEST_CTRL_PLL_RIPPLE_COUNTER_TEST_MODE(value)))
43823 #define XCVR_BWR_PLL_TEST_CTRL_PLL_RIPPLE_COUNTER_TEST_MODE(base, value) (BME_BFI32(&XCVR_PLL_TEST_CTRL_REG(base), ((uint32_t)(value) << XCVR_PLL_TEST_CTRL_PLL_RIPPLE_COUNTER_TEST_MODE_SHIFT), XCVR_PLL_TEST_CTRL_PLL_RIPPLE_COUNTER_TEST_MODE_SHIFT, XCVR_PLL_TEST_CTRL_PLL_RIPPLE_COUNTER_TEST_MODE_WIDTH))
43824 /*@}*/
43825 
43826 /*******************************************************************************
43827  * XCVR_QGEN_CTRL - QGEN Control
43828  ******************************************************************************/
43829 
43830 /*!
43831  * @brief XCVR_QGEN_CTRL - QGEN Control (RW)
43832  *
43833  * Reset value: 0x00000000U
43834  */
43835 /*!
43836  * @name Constants and macros for entire XCVR_QGEN_CTRL register
43837  */
43838 /*@{*/
43839 #define XCVR_RD_QGEN_CTRL(base)  (XCVR_QGEN_CTRL_REG(base))
43840 #define XCVR_WR_QGEN_CTRL(base, value) (XCVR_QGEN_CTRL_REG(base) = (value))
43841 #define XCVR_RMW_QGEN_CTRL(base, mask, value) (XCVR_WR_QGEN_CTRL(base, (XCVR_RD_QGEN_CTRL(base) & ~(mask)) | (value)))
43842 #define XCVR_SET_QGEN_CTRL(base, value) (BME_OR32(&XCVR_QGEN_CTRL_REG(base), (uint32_t)(value)))
43843 #define XCVR_CLR_QGEN_CTRL(base, value) (BME_AND32(&XCVR_QGEN_CTRL_REG(base), (uint32_t)(~(value))))
43844 #define XCVR_TOG_QGEN_CTRL(base, value) (BME_XOR32(&XCVR_QGEN_CTRL_REG(base), (uint32_t)(value)))
43845 /*@}*/
43846 
43847 /*
43848  * Constants & macros for individual XCVR_QGEN_CTRL bitfields
43849  */
43850 
43851 /*!
43852  * @name Register XCVR_QGEN_CTRL, field QGEN_REG_SUPPLY[3:0] (RW)
43853  *
43854  * Regulator trim bits to change the output voltage from 1.05 to 1.4V
43855  *
43856  * Values:
43857  * - 0b0000 - 1.2V
43858  * - 0b0001 - 1.05V
43859  * - 0b0010 - 1.275V
43860  * - 0b0011 - 1.3V
43861  */
43862 /*@{*/
43863 /*! @brief Read current value of the XCVR_QGEN_CTRL_QGEN_REG_SUPPLY field. */
43864 #define XCVR_RD_QGEN_CTRL_QGEN_REG_SUPPLY(base) ((XCVR_QGEN_CTRL_REG(base) & XCVR_QGEN_CTRL_QGEN_REG_SUPPLY_MASK) >> XCVR_QGEN_CTRL_QGEN_REG_SUPPLY_SHIFT)
43865 #define XCVR_BRD_QGEN_CTRL_QGEN_REG_SUPPLY(base) (BME_UBFX32(&XCVR_QGEN_CTRL_REG(base), XCVR_QGEN_CTRL_QGEN_REG_SUPPLY_SHIFT, XCVR_QGEN_CTRL_QGEN_REG_SUPPLY_WIDTH))
43866 
43867 /*! @brief Set the QGEN_REG_SUPPLY field to a new value. */
43868 #define XCVR_WR_QGEN_CTRL_QGEN_REG_SUPPLY(base, value) (XCVR_RMW_QGEN_CTRL(base, XCVR_QGEN_CTRL_QGEN_REG_SUPPLY_MASK, XCVR_QGEN_CTRL_QGEN_REG_SUPPLY(value)))
43869 #define XCVR_BWR_QGEN_CTRL_QGEN_REG_SUPPLY(base, value) (BME_BFI32(&XCVR_QGEN_CTRL_REG(base), ((uint32_t)(value) << XCVR_QGEN_CTRL_QGEN_REG_SUPPLY_SHIFT), XCVR_QGEN_CTRL_QGEN_REG_SUPPLY_SHIFT, XCVR_QGEN_CTRL_QGEN_REG_SUPPLY_WIDTH))
43870 /*@}*/
43871 
43872 /*!
43873  * @name Register XCVR_QGEN_CTRL, field QGEN_REG_ATST_SEL[7:4] (RW)
43874  *
43875  * These bits control the what internal regualtor signals are connected to the
43876  * ATST bus. register setting ATST0 00 No Connect 01 vout 10 vin feedback 11 vbias
43877  */
43878 /*@{*/
43879 /*! @brief Read current value of the XCVR_QGEN_CTRL_QGEN_REG_ATST_SEL field. */
43880 #define XCVR_RD_QGEN_CTRL_QGEN_REG_ATST_SEL(base) ((XCVR_QGEN_CTRL_REG(base) & XCVR_QGEN_CTRL_QGEN_REG_ATST_SEL_MASK) >> XCVR_QGEN_CTRL_QGEN_REG_ATST_SEL_SHIFT)
43881 #define XCVR_BRD_QGEN_CTRL_QGEN_REG_ATST_SEL(base) (BME_UBFX32(&XCVR_QGEN_CTRL_REG(base), XCVR_QGEN_CTRL_QGEN_REG_ATST_SEL_SHIFT, XCVR_QGEN_CTRL_QGEN_REG_ATST_SEL_WIDTH))
43882 
43883 /*! @brief Set the QGEN_REG_ATST_SEL field to a new value. */
43884 #define XCVR_WR_QGEN_CTRL_QGEN_REG_ATST_SEL(base, value) (XCVR_RMW_QGEN_CTRL(base, XCVR_QGEN_CTRL_QGEN_REG_ATST_SEL_MASK, XCVR_QGEN_CTRL_QGEN_REG_ATST_SEL(value)))
43885 #define XCVR_BWR_QGEN_CTRL_QGEN_REG_ATST_SEL(base, value) (BME_BFI32(&XCVR_QGEN_CTRL_REG(base), ((uint32_t)(value) << XCVR_QGEN_CTRL_QGEN_REG_ATST_SEL_SHIFT), XCVR_QGEN_CTRL_QGEN_REG_ATST_SEL_SHIFT, XCVR_QGEN_CTRL_QGEN_REG_ATST_SEL_WIDTH))
43886 /*@}*/
43887 
43888 /*!
43889  * @name Register XCVR_QGEN_CTRL, field QGEN_REG_BYPASS_ON[8] (RW)
43890  *
43891  * This register bit determines if the regulator is in bypass mode. When in
43892  * bypass mode, the external voltage applied to the input of the regulator is
43893  * presented at the regulator output.
43894  */
43895 /*@{*/
43896 /*! @brief Read current value of the XCVR_QGEN_CTRL_QGEN_REG_BYPASS_ON field. */
43897 #define XCVR_RD_QGEN_CTRL_QGEN_REG_BYPASS_ON(base) ((XCVR_QGEN_CTRL_REG(base) & XCVR_QGEN_CTRL_QGEN_REG_BYPASS_ON_MASK) >> XCVR_QGEN_CTRL_QGEN_REG_BYPASS_ON_SHIFT)
43898 #define XCVR_BRD_QGEN_CTRL_QGEN_REG_BYPASS_ON(base) (BME_UBFX32(&XCVR_QGEN_CTRL_REG(base), XCVR_QGEN_CTRL_QGEN_REG_BYPASS_ON_SHIFT, XCVR_QGEN_CTRL_QGEN_REG_BYPASS_ON_WIDTH))
43899 
43900 /*! @brief Set the QGEN_REG_BYPASS_ON field to a new value. */
43901 #define XCVR_WR_QGEN_CTRL_QGEN_REG_BYPASS_ON(base, value) (XCVR_RMW_QGEN_CTRL(base, XCVR_QGEN_CTRL_QGEN_REG_BYPASS_ON_MASK, XCVR_QGEN_CTRL_QGEN_REG_BYPASS_ON(value)))
43902 #define XCVR_BWR_QGEN_CTRL_QGEN_REG_BYPASS_ON(base, value) (BME_BFI32(&XCVR_QGEN_CTRL_REG(base), ((uint32_t)(value) << XCVR_QGEN_CTRL_QGEN_REG_BYPASS_ON_SHIFT), XCVR_QGEN_CTRL_QGEN_REG_BYPASS_ON_SHIFT, XCVR_QGEN_CTRL_QGEN_REG_BYPASS_ON_WIDTH))
43903 /*@}*/
43904 
43905 /*******************************************************************************
43906  * XCVR_TCA_CTRL - TCA Control
43907  ******************************************************************************/
43908 
43909 /*!
43910  * @brief XCVR_TCA_CTRL - TCA Control (RW)
43911  *
43912  * Reset value: 0x00000000U
43913  */
43914 /*!
43915  * @name Constants and macros for entire XCVR_TCA_CTRL register
43916  */
43917 /*@{*/
43918 #define XCVR_RD_TCA_CTRL(base)   (XCVR_TCA_CTRL_REG(base))
43919 #define XCVR_WR_TCA_CTRL(base, value) (XCVR_TCA_CTRL_REG(base) = (value))
43920 #define XCVR_RMW_TCA_CTRL(base, mask, value) (XCVR_WR_TCA_CTRL(base, (XCVR_RD_TCA_CTRL(base) & ~(mask)) | (value)))
43921 #define XCVR_SET_TCA_CTRL(base, value) (BME_OR32(&XCVR_TCA_CTRL_REG(base), (uint32_t)(value)))
43922 #define XCVR_CLR_TCA_CTRL(base, value) (BME_AND32(&XCVR_TCA_CTRL_REG(base), (uint32_t)(~(value))))
43923 #define XCVR_TOG_TCA_CTRL(base, value) (BME_XOR32(&XCVR_TCA_CTRL_REG(base), (uint32_t)(value)))
43924 /*@}*/
43925 
43926 /*
43927  * Constants & macros for individual XCVR_TCA_CTRL bitfields
43928  */
43929 
43930 /*!
43931  * @name Register XCVR_TCA_CTRL, field TCA_BIAS_CURR[1:0] (RW)
43932  *
43933  * Programmable bias currrent for the TCA
43934  */
43935 /*@{*/
43936 /*! @brief Read current value of the XCVR_TCA_CTRL_TCA_BIAS_CURR field. */
43937 #define XCVR_RD_TCA_CTRL_TCA_BIAS_CURR(base) ((XCVR_TCA_CTRL_REG(base) & XCVR_TCA_CTRL_TCA_BIAS_CURR_MASK) >> XCVR_TCA_CTRL_TCA_BIAS_CURR_SHIFT)
43938 #define XCVR_BRD_TCA_CTRL_TCA_BIAS_CURR(base) (BME_UBFX32(&XCVR_TCA_CTRL_REG(base), XCVR_TCA_CTRL_TCA_BIAS_CURR_SHIFT, XCVR_TCA_CTRL_TCA_BIAS_CURR_WIDTH))
43939 
43940 /*! @brief Set the TCA_BIAS_CURR field to a new value. */
43941 #define XCVR_WR_TCA_CTRL_TCA_BIAS_CURR(base, value) (XCVR_RMW_TCA_CTRL(base, XCVR_TCA_CTRL_TCA_BIAS_CURR_MASK, XCVR_TCA_CTRL_TCA_BIAS_CURR(value)))
43942 #define XCVR_BWR_TCA_CTRL_TCA_BIAS_CURR(base, value) (BME_BFI32(&XCVR_TCA_CTRL_REG(base), ((uint32_t)(value) << XCVR_TCA_CTRL_TCA_BIAS_CURR_SHIFT), XCVR_TCA_CTRL_TCA_BIAS_CURR_SHIFT, XCVR_TCA_CTRL_TCA_BIAS_CURR_WIDTH))
43943 /*@}*/
43944 
43945 /*!
43946  * @name Register XCVR_TCA_CTRL, field TCA_LOW_PWR_ON[2] (RW)
43947  *
43948  * Enable the tca low power mode
43949  */
43950 /*@{*/
43951 /*! @brief Read current value of the XCVR_TCA_CTRL_TCA_LOW_PWR_ON field. */
43952 #define XCVR_RD_TCA_CTRL_TCA_LOW_PWR_ON(base) ((XCVR_TCA_CTRL_REG(base) & XCVR_TCA_CTRL_TCA_LOW_PWR_ON_MASK) >> XCVR_TCA_CTRL_TCA_LOW_PWR_ON_SHIFT)
43953 #define XCVR_BRD_TCA_CTRL_TCA_LOW_PWR_ON(base) (BME_UBFX32(&XCVR_TCA_CTRL_REG(base), XCVR_TCA_CTRL_TCA_LOW_PWR_ON_SHIFT, XCVR_TCA_CTRL_TCA_LOW_PWR_ON_WIDTH))
43954 
43955 /*! @brief Set the TCA_LOW_PWR_ON field to a new value. */
43956 #define XCVR_WR_TCA_CTRL_TCA_LOW_PWR_ON(base, value) (XCVR_RMW_TCA_CTRL(base, XCVR_TCA_CTRL_TCA_LOW_PWR_ON_MASK, XCVR_TCA_CTRL_TCA_LOW_PWR_ON(value)))
43957 #define XCVR_BWR_TCA_CTRL_TCA_LOW_PWR_ON(base, value) (BME_BFI32(&XCVR_TCA_CTRL_REG(base), ((uint32_t)(value) << XCVR_TCA_CTRL_TCA_LOW_PWR_ON_SHIFT), XCVR_TCA_CTRL_TCA_LOW_PWR_ON_SHIFT, XCVR_TCA_CTRL_TCA_LOW_PWR_ON_WIDTH))
43958 /*@}*/
43959 
43960 /*!
43961  * @name Register XCVR_TCA_CTRL, field TCA_TX_REG_BYPASS_ON[3] (RW)
43962  *
43963  * This register bit determines if the regulator is in bypass mode. When in
43964  * bypass mode, the external voltage applied to the input of the regulator is
43965  * presented at the regulator output.
43966  */
43967 /*@{*/
43968 /*! @brief Read current value of the XCVR_TCA_CTRL_TCA_TX_REG_BYPASS_ON field. */
43969 #define XCVR_RD_TCA_CTRL_TCA_TX_REG_BYPASS_ON(base) ((XCVR_TCA_CTRL_REG(base) & XCVR_TCA_CTRL_TCA_TX_REG_BYPASS_ON_MASK) >> XCVR_TCA_CTRL_TCA_TX_REG_BYPASS_ON_SHIFT)
43970 #define XCVR_BRD_TCA_CTRL_TCA_TX_REG_BYPASS_ON(base) (BME_UBFX32(&XCVR_TCA_CTRL_REG(base), XCVR_TCA_CTRL_TCA_TX_REG_BYPASS_ON_SHIFT, XCVR_TCA_CTRL_TCA_TX_REG_BYPASS_ON_WIDTH))
43971 
43972 /*! @brief Set the TCA_TX_REG_BYPASS_ON field to a new value. */
43973 #define XCVR_WR_TCA_CTRL_TCA_TX_REG_BYPASS_ON(base, value) (XCVR_RMW_TCA_CTRL(base, XCVR_TCA_CTRL_TCA_TX_REG_BYPASS_ON_MASK, XCVR_TCA_CTRL_TCA_TX_REG_BYPASS_ON(value)))
43974 #define XCVR_BWR_TCA_CTRL_TCA_TX_REG_BYPASS_ON(base, value) (BME_BFI32(&XCVR_TCA_CTRL_REG(base), ((uint32_t)(value) << XCVR_TCA_CTRL_TCA_TX_REG_BYPASS_ON_SHIFT), XCVR_TCA_CTRL_TCA_TX_REG_BYPASS_ON_SHIFT, XCVR_TCA_CTRL_TCA_TX_REG_BYPASS_ON_WIDTH))
43975 /*@}*/
43976 
43977 /*!
43978  * @name Register XCVR_TCA_CTRL, field TCA_TX_REG_SUPPLY[7:4] (RW)
43979  *
43980  * Regulator trim bit to change the outputvoltage from 1.05 to 1.4V
43981  *
43982  * Values:
43983  * - 0b0000 - 1.2V
43984  * - 0b0001 - 1.05V
43985  * - 0b0010 - 1.275V
43986  * - 0b0011 - 1.3V
43987  */
43988 /*@{*/
43989 /*! @brief Read current value of the XCVR_TCA_CTRL_TCA_TX_REG_SUPPLY field. */
43990 #define XCVR_RD_TCA_CTRL_TCA_TX_REG_SUPPLY(base) ((XCVR_TCA_CTRL_REG(base) & XCVR_TCA_CTRL_TCA_TX_REG_SUPPLY_MASK) >> XCVR_TCA_CTRL_TCA_TX_REG_SUPPLY_SHIFT)
43991 #define XCVR_BRD_TCA_CTRL_TCA_TX_REG_SUPPLY(base) (BME_UBFX32(&XCVR_TCA_CTRL_REG(base), XCVR_TCA_CTRL_TCA_TX_REG_SUPPLY_SHIFT, XCVR_TCA_CTRL_TCA_TX_REG_SUPPLY_WIDTH))
43992 
43993 /*! @brief Set the TCA_TX_REG_SUPPLY field to a new value. */
43994 #define XCVR_WR_TCA_CTRL_TCA_TX_REG_SUPPLY(base, value) (XCVR_RMW_TCA_CTRL(base, XCVR_TCA_CTRL_TCA_TX_REG_SUPPLY_MASK, XCVR_TCA_CTRL_TCA_TX_REG_SUPPLY(value)))
43995 #define XCVR_BWR_TCA_CTRL_TCA_TX_REG_SUPPLY(base, value) (BME_BFI32(&XCVR_TCA_CTRL_REG(base), ((uint32_t)(value) << XCVR_TCA_CTRL_TCA_TX_REG_SUPPLY_SHIFT), XCVR_TCA_CTRL_TCA_TX_REG_SUPPLY_SHIFT, XCVR_TCA_CTRL_TCA_TX_REG_SUPPLY_WIDTH))
43996 /*@}*/
43997 
43998 /*!
43999  * @name Register XCVR_TCA_CTRL, field TCA_TX_REG_ATST_SEL[9:8] (RW)
44000  *
44001  * These bits determine what internal signals to connect to ATST bus register
44002  * setting ATST0 00 No Connect 01 vout 10 vin feedback 11 vbias
44003  */
44004 /*@{*/
44005 /*! @brief Read current value of the XCVR_TCA_CTRL_TCA_TX_REG_ATST_SEL field. */
44006 #define XCVR_RD_TCA_CTRL_TCA_TX_REG_ATST_SEL(base) ((XCVR_TCA_CTRL_REG(base) & XCVR_TCA_CTRL_TCA_TX_REG_ATST_SEL_MASK) >> XCVR_TCA_CTRL_TCA_TX_REG_ATST_SEL_SHIFT)
44007 #define XCVR_BRD_TCA_CTRL_TCA_TX_REG_ATST_SEL(base) (BME_UBFX32(&XCVR_TCA_CTRL_REG(base), XCVR_TCA_CTRL_TCA_TX_REG_ATST_SEL_SHIFT, XCVR_TCA_CTRL_TCA_TX_REG_ATST_SEL_WIDTH))
44008 
44009 /*! @brief Set the TCA_TX_REG_ATST_SEL field to a new value. */
44010 #define XCVR_WR_TCA_CTRL_TCA_TX_REG_ATST_SEL(base, value) (XCVR_RMW_TCA_CTRL(base, XCVR_TCA_CTRL_TCA_TX_REG_ATST_SEL_MASK, XCVR_TCA_CTRL_TCA_TX_REG_ATST_SEL(value)))
44011 #define XCVR_BWR_TCA_CTRL_TCA_TX_REG_ATST_SEL(base, value) (BME_BFI32(&XCVR_TCA_CTRL_REG(base), ((uint32_t)(value) << XCVR_TCA_CTRL_TCA_TX_REG_ATST_SEL_SHIFT), XCVR_TCA_CTRL_TCA_TX_REG_ATST_SEL_SHIFT, XCVR_TCA_CTRL_TCA_TX_REG_ATST_SEL_WIDTH))
44012 /*@}*/
44013 
44014 /*******************************************************************************
44015  * XCVR_TZA_CTRL - TZA Control
44016  ******************************************************************************/
44017 
44018 /*!
44019  * @brief XCVR_TZA_CTRL - TZA Control (RW)
44020  *
44021  * Reset value: 0x00000044U
44022  */
44023 /*!
44024  * @name Constants and macros for entire XCVR_TZA_CTRL register
44025  */
44026 /*@{*/
44027 #define XCVR_RD_TZA_CTRL(base)   (XCVR_TZA_CTRL_REG(base))
44028 #define XCVR_WR_TZA_CTRL(base, value) (XCVR_TZA_CTRL_REG(base) = (value))
44029 #define XCVR_RMW_TZA_CTRL(base, mask, value) (XCVR_WR_TZA_CTRL(base, (XCVR_RD_TZA_CTRL(base) & ~(mask)) | (value)))
44030 #define XCVR_SET_TZA_CTRL(base, value) (BME_OR32(&XCVR_TZA_CTRL_REG(base), (uint32_t)(value)))
44031 #define XCVR_CLR_TZA_CTRL(base, value) (BME_AND32(&XCVR_TZA_CTRL_REG(base), (uint32_t)(~(value))))
44032 #define XCVR_TOG_TZA_CTRL(base, value) (BME_XOR32(&XCVR_TZA_CTRL_REG(base), (uint32_t)(value)))
44033 /*@}*/
44034 
44035 /*
44036  * Constants & macros for individual XCVR_TZA_CTRL bitfields
44037  */
44038 
44039 /*!
44040  * @name Register XCVR_TZA_CTRL, field TZA_CAP_TUNE[3:0] (RW)
44041  *
44042  * The bits sets the f3dB filter corner for the TZA block. This in combination
44043  * with bbf_cap_tune and bbf_res_tune2 determine the baseband filter response.Look
44044  * for the f3db corner here BBF_CAP_TUNEBBF_CAP_TUNE
44045  */
44046 /*@{*/
44047 /*! @brief Read current value of the XCVR_TZA_CTRL_TZA_CAP_TUNE field. */
44048 #define XCVR_RD_TZA_CTRL_TZA_CAP_TUNE(base) ((XCVR_TZA_CTRL_REG(base) & XCVR_TZA_CTRL_TZA_CAP_TUNE_MASK) >> XCVR_TZA_CTRL_TZA_CAP_TUNE_SHIFT)
44049 #define XCVR_BRD_TZA_CTRL_TZA_CAP_TUNE(base) (BME_UBFX32(&XCVR_TZA_CTRL_REG(base), XCVR_TZA_CTRL_TZA_CAP_TUNE_SHIFT, XCVR_TZA_CTRL_TZA_CAP_TUNE_WIDTH))
44050 
44051 /*! @brief Set the TZA_CAP_TUNE field to a new value. */
44052 #define XCVR_WR_TZA_CTRL_TZA_CAP_TUNE(base, value) (XCVR_RMW_TZA_CTRL(base, XCVR_TZA_CTRL_TZA_CAP_TUNE_MASK, XCVR_TZA_CTRL_TZA_CAP_TUNE(value)))
44053 #define XCVR_BWR_TZA_CTRL_TZA_CAP_TUNE(base, value) (BME_BFI32(&XCVR_TZA_CTRL_REG(base), ((uint32_t)(value) << XCVR_TZA_CTRL_TZA_CAP_TUNE_SHIFT), XCVR_TZA_CTRL_TZA_CAP_TUNE_SHIFT, XCVR_TZA_CTRL_TZA_CAP_TUNE_WIDTH))
44054 /*@}*/
44055 
44056 /*!
44057  * @name Register XCVR_TZA_CTRL, field TZA_GAIN[4] (RW)
44058  *
44059  * Change the TZA gain. It is not used in this version of silicon.
44060  */
44061 /*@{*/
44062 /*! @brief Read current value of the XCVR_TZA_CTRL_TZA_GAIN field. */
44063 #define XCVR_RD_TZA_CTRL_TZA_GAIN(base) ((XCVR_TZA_CTRL_REG(base) & XCVR_TZA_CTRL_TZA_GAIN_MASK) >> XCVR_TZA_CTRL_TZA_GAIN_SHIFT)
44064 #define XCVR_BRD_TZA_CTRL_TZA_GAIN(base) (BME_UBFX32(&XCVR_TZA_CTRL_REG(base), XCVR_TZA_CTRL_TZA_GAIN_SHIFT, XCVR_TZA_CTRL_TZA_GAIN_WIDTH))
44065 
44066 /*! @brief Set the TZA_GAIN field to a new value. */
44067 #define XCVR_WR_TZA_CTRL_TZA_GAIN(base, value) (XCVR_RMW_TZA_CTRL(base, XCVR_TZA_CTRL_TZA_GAIN_MASK, XCVR_TZA_CTRL_TZA_GAIN(value)))
44068 #define XCVR_BWR_TZA_CTRL_TZA_GAIN(base, value) (BME_BFI32(&XCVR_TZA_CTRL_REG(base), ((uint32_t)(value) << XCVR_TZA_CTRL_TZA_GAIN_SHIFT), XCVR_TZA_CTRL_TZA_GAIN_SHIFT, XCVR_TZA_CTRL_TZA_GAIN_WIDTH))
44069 /*@}*/
44070 
44071 /*!
44072  * @name Register XCVR_TZA_CTRL, field TZA_DCOC_ON[5] (RW)
44073  *
44074  * Not currently connected. Was intended to enable the DCOC DAC at the output of
44075  * the TZA
44076  */
44077 /*@{*/
44078 /*! @brief Read current value of the XCVR_TZA_CTRL_TZA_DCOC_ON field. */
44079 #define XCVR_RD_TZA_CTRL_TZA_DCOC_ON(base) ((XCVR_TZA_CTRL_REG(base) & XCVR_TZA_CTRL_TZA_DCOC_ON_MASK) >> XCVR_TZA_CTRL_TZA_DCOC_ON_SHIFT)
44080 #define XCVR_BRD_TZA_CTRL_TZA_DCOC_ON(base) (BME_UBFX32(&XCVR_TZA_CTRL_REG(base), XCVR_TZA_CTRL_TZA_DCOC_ON_SHIFT, XCVR_TZA_CTRL_TZA_DCOC_ON_WIDTH))
44081 
44082 /*! @brief Set the TZA_DCOC_ON field to a new value. */
44083 #define XCVR_WR_TZA_CTRL_TZA_DCOC_ON(base, value) (XCVR_RMW_TZA_CTRL(base, XCVR_TZA_CTRL_TZA_DCOC_ON_MASK, XCVR_TZA_CTRL_TZA_DCOC_ON(value)))
44084 #define XCVR_BWR_TZA_CTRL_TZA_DCOC_ON(base, value) (BME_BFI32(&XCVR_TZA_CTRL_REG(base), ((uint32_t)(value) << XCVR_TZA_CTRL_TZA_DCOC_ON_SHIFT), XCVR_TZA_CTRL_TZA_DCOC_ON_SHIFT, XCVR_TZA_CTRL_TZA_DCOC_ON_WIDTH))
44085 /*@}*/
44086 
44087 /*!
44088  * @name Register XCVR_TZA_CTRL, field TZA_CUR_CNTL[7:6] (RW)
44089  *
44090  * Program the current in TZA. The TZA current is varied from 510uA to 2.1mA
44091  */
44092 /*@{*/
44093 /*! @brief Read current value of the XCVR_TZA_CTRL_TZA_CUR_CNTL field. */
44094 #define XCVR_RD_TZA_CTRL_TZA_CUR_CNTL(base) ((XCVR_TZA_CTRL_REG(base) & XCVR_TZA_CTRL_TZA_CUR_CNTL_MASK) >> XCVR_TZA_CTRL_TZA_CUR_CNTL_SHIFT)
44095 #define XCVR_BRD_TZA_CTRL_TZA_CUR_CNTL(base) (BME_UBFX32(&XCVR_TZA_CTRL_REG(base), XCVR_TZA_CTRL_TZA_CUR_CNTL_SHIFT, XCVR_TZA_CTRL_TZA_CUR_CNTL_WIDTH))
44096 
44097 /*! @brief Set the TZA_CUR_CNTL field to a new value. */
44098 #define XCVR_WR_TZA_CTRL_TZA_CUR_CNTL(base, value) (XCVR_RMW_TZA_CTRL(base, XCVR_TZA_CTRL_TZA_CUR_CNTL_MASK, XCVR_TZA_CTRL_TZA_CUR_CNTL(value)))
44099 #define XCVR_BWR_TZA_CTRL_TZA_CUR_CNTL(base, value) (BME_BFI32(&XCVR_TZA_CTRL_REG(base), ((uint32_t)(value) << XCVR_TZA_CTRL_TZA_CUR_CNTL_SHIFT), XCVR_TZA_CTRL_TZA_CUR_CNTL_SHIFT, XCVR_TZA_CTRL_TZA_CUR_CNTL_WIDTH))
44100 /*@}*/
44101 
44102 /*!
44103  * @name Register XCVR_TZA_CTRL, field TZA_SPARE[23:20] (RW)
44104  *
44105  * Spare Bits for future use
44106  */
44107 /*@{*/
44108 /*! @brief Read current value of the XCVR_TZA_CTRL_TZA_SPARE field. */
44109 #define XCVR_RD_TZA_CTRL_TZA_SPARE(base) ((XCVR_TZA_CTRL_REG(base) & XCVR_TZA_CTRL_TZA_SPARE_MASK) >> XCVR_TZA_CTRL_TZA_SPARE_SHIFT)
44110 #define XCVR_BRD_TZA_CTRL_TZA_SPARE(base) (BME_UBFX32(&XCVR_TZA_CTRL_REG(base), XCVR_TZA_CTRL_TZA_SPARE_SHIFT, XCVR_TZA_CTRL_TZA_SPARE_WIDTH))
44111 
44112 /*! @brief Set the TZA_SPARE field to a new value. */
44113 #define XCVR_WR_TZA_CTRL_TZA_SPARE(base, value) (XCVR_RMW_TZA_CTRL(base, XCVR_TZA_CTRL_TZA_SPARE_MASK, XCVR_TZA_CTRL_TZA_SPARE(value)))
44114 #define XCVR_BWR_TZA_CTRL_TZA_SPARE(base, value) (BME_BFI32(&XCVR_TZA_CTRL_REG(base), ((uint32_t)(value) << XCVR_TZA_CTRL_TZA_SPARE_SHIFT), XCVR_TZA_CTRL_TZA_SPARE_SHIFT, XCVR_TZA_CTRL_TZA_SPARE_WIDTH))
44115 /*@}*/
44116 
44117 /*******************************************************************************
44118  * XCVR_TX_ANA_CTRL - TX Analog Control
44119  ******************************************************************************/
44120 
44121 /*!
44122  * @brief XCVR_TX_ANA_CTRL - TX Analog Control (RW)
44123  *
44124  * Reset value: 0x00000000U
44125  */
44126 /*!
44127  * @name Constants and macros for entire XCVR_TX_ANA_CTRL register
44128  */
44129 /*@{*/
44130 #define XCVR_RD_TX_ANA_CTRL(base) (XCVR_TX_ANA_CTRL_REG(base))
44131 #define XCVR_WR_TX_ANA_CTRL(base, value) (XCVR_TX_ANA_CTRL_REG(base) = (value))
44132 #define XCVR_RMW_TX_ANA_CTRL(base, mask, value) (XCVR_WR_TX_ANA_CTRL(base, (XCVR_RD_TX_ANA_CTRL(base) & ~(mask)) | (value)))
44133 #define XCVR_SET_TX_ANA_CTRL(base, value) (BME_OR32(&XCVR_TX_ANA_CTRL_REG(base), (uint32_t)(value)))
44134 #define XCVR_CLR_TX_ANA_CTRL(base, value) (BME_AND32(&XCVR_TX_ANA_CTRL_REG(base), (uint32_t)(~(value))))
44135 #define XCVR_TOG_TX_ANA_CTRL(base, value) (BME_XOR32(&XCVR_TX_ANA_CTRL_REG(base), (uint32_t)(value)))
44136 /*@}*/
44137 
44138 /*
44139  * Constants & macros for individual XCVR_TX_ANA_CTRL bitfields
44140  */
44141 
44142 /*!
44143  * @name Register XCVR_TX_ANA_CTRL, field HPM_CAL_ADJUST[3:0] (RW)
44144  *
44145  * Provides a (-8/+7) range of adjustment to the HPM Calibration Count
44146  * Difference for the HPM Calibration lookup table
44147  */
44148 /*@{*/
44149 /*! @brief Read current value of the XCVR_TX_ANA_CTRL_HPM_CAL_ADJUST field. */
44150 #define XCVR_RD_TX_ANA_CTRL_HPM_CAL_ADJUST(base) ((XCVR_TX_ANA_CTRL_REG(base) & XCVR_TX_ANA_CTRL_HPM_CAL_ADJUST_MASK) >> XCVR_TX_ANA_CTRL_HPM_CAL_ADJUST_SHIFT)
44151 #define XCVR_BRD_TX_ANA_CTRL_HPM_CAL_ADJUST(base) (BME_UBFX32(&XCVR_TX_ANA_CTRL_REG(base), XCVR_TX_ANA_CTRL_HPM_CAL_ADJUST_SHIFT, XCVR_TX_ANA_CTRL_HPM_CAL_ADJUST_WIDTH))
44152 
44153 /*! @brief Set the HPM_CAL_ADJUST field to a new value. */
44154 #define XCVR_WR_TX_ANA_CTRL_HPM_CAL_ADJUST(base, value) (XCVR_RMW_TX_ANA_CTRL(base, XCVR_TX_ANA_CTRL_HPM_CAL_ADJUST_MASK, XCVR_TX_ANA_CTRL_HPM_CAL_ADJUST(value)))
44155 #define XCVR_BWR_TX_ANA_CTRL_HPM_CAL_ADJUST(base, value) (BME_BFI32(&XCVR_TX_ANA_CTRL_REG(base), ((uint32_t)(value) << XCVR_TX_ANA_CTRL_HPM_CAL_ADJUST_SHIFT), XCVR_TX_ANA_CTRL_HPM_CAL_ADJUST_SHIFT, XCVR_TX_ANA_CTRL_HPM_CAL_ADJUST_WIDTH))
44156 /*@}*/
44157 
44158 /*******************************************************************************
44159  * XCVR_ANA_SPARE - Analog Spare
44160  ******************************************************************************/
44161 
44162 /*!
44163  * @brief XCVR_ANA_SPARE - Analog Spare (RW)
44164  *
44165  * Reset value: 0x00000000U
44166  */
44167 /*!
44168  * @name Constants and macros for entire XCVR_ANA_SPARE register
44169  */
44170 /*@{*/
44171 #define XCVR_RD_ANA_SPARE(base)  (XCVR_ANA_SPARE_REG(base))
44172 #define XCVR_WR_ANA_SPARE(base, value) (XCVR_ANA_SPARE_REG(base) = (value))
44173 #define XCVR_RMW_ANA_SPARE(base, mask, value) (XCVR_WR_ANA_SPARE(base, (XCVR_RD_ANA_SPARE(base) & ~(mask)) | (value)))
44174 #define XCVR_SET_ANA_SPARE(base, value) (BME_OR32(&XCVR_ANA_SPARE_REG(base), (uint32_t)(value)))
44175 #define XCVR_CLR_ANA_SPARE(base, value) (BME_AND32(&XCVR_ANA_SPARE_REG(base), (uint32_t)(~(value))))
44176 #define XCVR_TOG_ANA_SPARE(base, value) (BME_XOR32(&XCVR_ANA_SPARE_REG(base), (uint32_t)(value)))
44177 /*@}*/
44178 
44179 /*
44180  * Constants & macros for individual XCVR_ANA_SPARE bitfields
44181  */
44182 
44183 /*!
44184  * @name Register XCVR_ANA_SPARE, field IQMC_DC_GAIN_ADJ[10:0] (RW)
44185  *
44186  * I/Q mismatch correction DC gain coefficient. This is the value by which the Q
44187  * channel data is multiplied during DCOC calibration if the IQMC_DC_GAIN_ADJ_EN
44188  * bit is set; otherwise IQMC_GAIN_ADJ is used during DCOC calibration. Format
44189  * is u1.10 so e.g. 11'h400 (the reset value) corresponds to a value of 1.0,
44190  * 11'h200 corresponds to 0.5, 11'h600 corresponds to 1.5.
44191  */
44192 /*@{*/
44193 /*! @brief Read current value of the XCVR_ANA_SPARE_IQMC_DC_GAIN_ADJ field. */
44194 #define XCVR_RD_ANA_SPARE_IQMC_DC_GAIN_ADJ(base) ((XCVR_ANA_SPARE_REG(base) & XCVR_ANA_SPARE_IQMC_DC_GAIN_ADJ_MASK) >> XCVR_ANA_SPARE_IQMC_DC_GAIN_ADJ_SHIFT)
44195 #define XCVR_BRD_ANA_SPARE_IQMC_DC_GAIN_ADJ(base) (BME_UBFX32(&XCVR_ANA_SPARE_REG(base), XCVR_ANA_SPARE_IQMC_DC_GAIN_ADJ_SHIFT, XCVR_ANA_SPARE_IQMC_DC_GAIN_ADJ_WIDTH))
44196 
44197 /*! @brief Set the IQMC_DC_GAIN_ADJ field to a new value. */
44198 #define XCVR_WR_ANA_SPARE_IQMC_DC_GAIN_ADJ(base, value) (XCVR_RMW_ANA_SPARE(base, XCVR_ANA_SPARE_IQMC_DC_GAIN_ADJ_MASK, XCVR_ANA_SPARE_IQMC_DC_GAIN_ADJ(value)))
44199 #define XCVR_BWR_ANA_SPARE_IQMC_DC_GAIN_ADJ(base, value) (BME_BFI32(&XCVR_ANA_SPARE_REG(base), ((uint32_t)(value) << XCVR_ANA_SPARE_IQMC_DC_GAIN_ADJ_SHIFT), XCVR_ANA_SPARE_IQMC_DC_GAIN_ADJ_SHIFT, XCVR_ANA_SPARE_IQMC_DC_GAIN_ADJ_WIDTH))
44200 /*@}*/
44201 
44202 /*!
44203  * @name Register XCVR_ANA_SPARE, field DCOC_TRK_EST_GS_CNT[13:11] (RW)
44204  *
44205  * Indicates the number of tracking update corrections after an AGC gain change
44206  * before the tracking estimator switches from parameters {dcoc_alpha_radius_idx,
44207  * dcoc_alphac_scaling_idx, dcoc_sign_scaling_idx} to the set of gearshift
44208  * parameters {dcoc_alpha_radius_gs_idx, dcoc_alphac_scaling_gs_idx,
44209  * dcoc_sign_scaling_idx}. Note that dcoc_sign_scaling_idx is used in both configurations.
44210  *
44211  * Values:
44212  * - 0b000 - Only use {dcoc_alpha_radius_idx, dcoc_alphac_scaling_idx,
44213  *     dcoc_sign_scaling_idx}
44214  * - 0b001 - Switch from {dcoc_alpha_radius_idx, dcoc_alphac_scaling_idx,
44215  *     dcoc_sign_scaling_idx} to {dcoc_alpha_radius_gs_idx, dcoc_alphac_scaling_gs_idx,
44216  *     dcoc_sign_scaling_idx} after the 1 update correction.
44217  */
44218 /*@{*/
44219 /*! @brief Read current value of the XCVR_ANA_SPARE_DCOC_TRK_EST_GS_CNT field. */
44220 #define XCVR_RD_ANA_SPARE_DCOC_TRK_EST_GS_CNT(base) ((XCVR_ANA_SPARE_REG(base) & XCVR_ANA_SPARE_DCOC_TRK_EST_GS_CNT_MASK) >> XCVR_ANA_SPARE_DCOC_TRK_EST_GS_CNT_SHIFT)
44221 #define XCVR_BRD_ANA_SPARE_DCOC_TRK_EST_GS_CNT(base) (BME_UBFX32(&XCVR_ANA_SPARE_REG(base), XCVR_ANA_SPARE_DCOC_TRK_EST_GS_CNT_SHIFT, XCVR_ANA_SPARE_DCOC_TRK_EST_GS_CNT_WIDTH))
44222 
44223 /*! @brief Set the DCOC_TRK_EST_GS_CNT field to a new value. */
44224 #define XCVR_WR_ANA_SPARE_DCOC_TRK_EST_GS_CNT(base, value) (XCVR_RMW_ANA_SPARE(base, XCVR_ANA_SPARE_DCOC_TRK_EST_GS_CNT_MASK, XCVR_ANA_SPARE_DCOC_TRK_EST_GS_CNT(value)))
44225 #define XCVR_BWR_ANA_SPARE_DCOC_TRK_EST_GS_CNT(base, value) (BME_BFI32(&XCVR_ANA_SPARE_REG(base), ((uint32_t)(value) << XCVR_ANA_SPARE_DCOC_TRK_EST_GS_CNT_SHIFT), XCVR_ANA_SPARE_DCOC_TRK_EST_GS_CNT_SHIFT, XCVR_ANA_SPARE_DCOC_TRK_EST_GS_CNT_WIDTH))
44226 /*@}*/
44227 
44228 /*!
44229  * @name Register XCVR_ANA_SPARE, field HPM_LSB_INVERT[15:14] (RW)
44230  *
44231  * Provides individual inversion settings for the two HPM LSB Array Units
44232  */
44233 /*@{*/
44234 /*! @brief Read current value of the XCVR_ANA_SPARE_HPM_LSB_INVERT field. */
44235 #define XCVR_RD_ANA_SPARE_HPM_LSB_INVERT(base) ((XCVR_ANA_SPARE_REG(base) & XCVR_ANA_SPARE_HPM_LSB_INVERT_MASK) >> XCVR_ANA_SPARE_HPM_LSB_INVERT_SHIFT)
44236 #define XCVR_BRD_ANA_SPARE_HPM_LSB_INVERT(base) (BME_UBFX32(&XCVR_ANA_SPARE_REG(base), XCVR_ANA_SPARE_HPM_LSB_INVERT_SHIFT, XCVR_ANA_SPARE_HPM_LSB_INVERT_WIDTH))
44237 
44238 /*! @brief Set the HPM_LSB_INVERT field to a new value. */
44239 #define XCVR_WR_ANA_SPARE_HPM_LSB_INVERT(base, value) (XCVR_RMW_ANA_SPARE(base, XCVR_ANA_SPARE_HPM_LSB_INVERT_MASK, XCVR_ANA_SPARE_HPM_LSB_INVERT(value)))
44240 #define XCVR_BWR_ANA_SPARE_HPM_LSB_INVERT(base, value) (BME_BFI32(&XCVR_ANA_SPARE_REG(base), ((uint32_t)(value) << XCVR_ANA_SPARE_HPM_LSB_INVERT_SHIFT), XCVR_ANA_SPARE_HPM_LSB_INVERT_SHIFT, XCVR_ANA_SPARE_HPM_LSB_INVERT_WIDTH))
44241 /*@}*/
44242 
44243 /*!
44244  * @name Register XCVR_ANA_SPARE, field ANA_DTEST[21:16] (RO)
44245  *
44246  * Not currently implemented, reads back zero.
44247  */
44248 /*@{*/
44249 /*! @brief Read current value of the XCVR_ANA_SPARE_ANA_DTEST field. */
44250 #define XCVR_RD_ANA_SPARE_ANA_DTEST(base) ((XCVR_ANA_SPARE_REG(base) & XCVR_ANA_SPARE_ANA_DTEST_MASK) >> XCVR_ANA_SPARE_ANA_DTEST_SHIFT)
44251 #define XCVR_BRD_ANA_SPARE_ANA_DTEST(base) (BME_UBFX32(&XCVR_ANA_SPARE_REG(base), XCVR_ANA_SPARE_ANA_DTEST_SHIFT, XCVR_ANA_SPARE_ANA_DTEST_WIDTH))
44252 /*@}*/
44253 
44254 /*
44255  * MKW40Z4 ZLL
44256  *
44257  * Zigbee Link Layer
44258  *
44259  * Registers defined in this header file:
44260  * - ZLL_IRQSTS - INTERRUPT REQUEST STATUS
44261  * - ZLL_PHY_CTRL - PHY CONTROL
44262  * - ZLL_EVENT_TMR - EVENT TIMER
44263  * - ZLL_TIMESTAMP - TIMESTAMP
44264  * - ZLL_T1CMP - T1 COMPARE
44265  * - ZLL_T2CMP - T2 COMPARE
44266  * - ZLL_T2PRIMECMP - T2 PRIME COMPARE
44267  * - ZLL_T3CMP - T3 COMPARE
44268  * - ZLL_T4CMP - T4 COMPARE
44269  * - ZLL_PA_PWR - PA POWER
44270  * - ZLL_CHANNEL_NUM0 - CHANNEL NUMBER 0
44271  * - ZLL_LQI_AND_RSSI - LQI AND RSSI
44272  * - ZLL_MACSHORTADDRS0 - MAC SHORT ADDRESS 0
44273  * - ZLL_MACLONGADDRS0_LSB - MAC LONG ADDRESS 0 LSB
44274  * - ZLL_MACLONGADDRS0_MSB - MAC LONG ADDRESS 0 MSB
44275  * - ZLL_RX_FRAME_FILTER - RECEIVE FRAME FILTER
44276  * - ZLL_CCA_LQI_CTRL - CCA AND LQI CONTROL
44277  * - ZLL_CCA2_CTRL - CCA2 CONTROL
44278  * - ZLL_FAD_CTRL - FAD CONTROL
44279  * - ZLL_SNF_CTRL - SNF CONTROL
44280  * - ZLL_BSM_CTRL - BSM CONTROL
44281  * - ZLL_MACSHORTADDRS1 - MAC SHORT ADDRESS 1
44282  * - ZLL_MACLONGADDRS1_LSB - MAC LONG ADDRESS 1 LSB
44283  * - ZLL_MACLONGADDRS1_MSB - MAC LONG ADDRESS 1 MSB
44284  * - ZLL_DUAL_PAN_CTRL - DUAL PAN CONTROL
44285  * - ZLL_CHANNEL_NUM1 - CHANNEL NUMBER 1
44286  * - ZLL_SAM_CTRL - SAM CONTROL
44287  * - ZLL_SAM_TABLE - SOURCE ADDRESS MANAGEMENT TABLE
44288  * - ZLL_SAM_MATCH - SAM MATCH
44289  * - ZLL_SAM_FREE_IDX - SAM FREE INDEX
44290  * - ZLL_SEQ_CTRL_STS - SEQUENCE CONTROL AND STATUS
44291  * - ZLL_ACKDELAY - ACK DELAY
44292  * - ZLL_FILTERFAIL_CODE - FILTER FAIL CODE
44293  * - ZLL_RX_WTR_MARK - RECEIVE WATER MARK
44294  * - ZLL_SLOT_PRELOAD - SLOT PRELOAD
44295  * - ZLL_SEQ_STATE - ZIGBEE SEQUENCE STATE
44296  * - ZLL_TMR_PRESCALE - TIMER PRESCALER
44297  * - ZLL_LENIENCY_LSB - LENIENCY LSB
44298  * - ZLL_LENIENCY_MSB - LENIENCY MSB
44299  * - ZLL_PART_ID - PART ID
44300  * - ZLL_PKT_BUFFER - PACKET BUFFER
44301  */
44302 
44303 #define ZLL_INSTANCE_COUNT (1U) /*!< Number of instances of the ZLL module. */
44304 #define ZLL_IDX (0U) /*!< Instance number for ZLL. */
44305 
44306 /*******************************************************************************
44307  * ZLL_IRQSTS - INTERRUPT REQUEST STATUS
44308  ******************************************************************************/
44309 
44310 /*!
44311  * @brief ZLL_IRQSTS - INTERRUPT REQUEST STATUS (RW)
44312  *
44313  * Reset value: 0x00F00000U
44314  *
44315  * Zigbee Interrupt Request Status
44316  */
44317 /*!
44318  * @name Constants and macros for entire ZLL_IRQSTS register
44319  */
44320 /*@{*/
44321 #define ZLL_RD_IRQSTS(base)      (ZLL_IRQSTS_REG(base))
44322 #define ZLL_WR_IRQSTS(base, value) (ZLL_IRQSTS_REG(base) = (value))
44323 #define ZLL_RMW_IRQSTS(base, mask, value) (ZLL_WR_IRQSTS(base, (ZLL_RD_IRQSTS(base) & ~(mask)) | (value)))
44324 #define ZLL_SET_IRQSTS(base, value) (BME_OR32(&ZLL_IRQSTS_REG(base), (uint32_t)(value)))
44325 #define ZLL_CLR_IRQSTS(base, value) (BME_AND32(&ZLL_IRQSTS_REG(base), (uint32_t)(~(value))))
44326 #define ZLL_TOG_IRQSTS(base, value) (BME_XOR32(&ZLL_IRQSTS_REG(base), (uint32_t)(value)))
44327 /*@}*/
44328 
44329 /*
44330  * Constants & macros for individual ZLL_IRQSTS bitfields
44331  */
44332 
44333 /*!
44334  * @name Register ZLL_IRQSTS, field SEQIRQ[0] (W1C)
44335  *
44336  * Values:
44337  * - 0b0 - A Sequencer Interrupt has not occurred
44338  * - 0b1 - A Sequencer Interrupt has occurred
44339  */
44340 /*@{*/
44341 /*! @brief Read current value of the ZLL_IRQSTS_SEQIRQ field. */
44342 #define ZLL_RD_IRQSTS_SEQIRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_SEQIRQ_MASK) >> ZLL_IRQSTS_SEQIRQ_SHIFT)
44343 #define ZLL_BRD_IRQSTS_SEQIRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_SEQIRQ_SHIFT, ZLL_IRQSTS_SEQIRQ_WIDTH))
44344 
44345 /*! @brief Set the SEQIRQ field to a new value. */
44346 #define ZLL_WR_IRQSTS_SEQIRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_SEQIRQ_MASK | ZLL_IRQSTS_TXIRQ_MASK | ZLL_IRQSTS_RXIRQ_MASK | ZLL_IRQSTS_CCAIRQ_MASK | ZLL_IRQSTS_RXWTRMRKIRQ_MASK | ZLL_IRQSTS_FILTERFAIL_IRQ_MASK | ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK | ZLL_IRQSTS_PB_ERR_IRQ_MASK | ZLL_IRQSTS_TMR1IRQ_MASK | ZLL_IRQSTS_TMR2IRQ_MASK | ZLL_IRQSTS_TMR3IRQ_MASK | ZLL_IRQSTS_TMR4IRQ_MASK), ZLL_IRQSTS_SEQIRQ(value)))
44347 #define ZLL_BWR_IRQSTS_SEQIRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << ZLL_IRQSTS_SEQIRQ_SHIFT), ZLL_IRQSTS_SEQIRQ_SHIFT, ZLL_IRQSTS_SEQIRQ_WIDTH))
44348 /*@}*/
44349 
44350 /*!
44351  * @name Register ZLL_IRQSTS, field TXIRQ[1] (W1C)
44352  *
44353  * Values:
44354  * - 0b0 - A TX Interrupt has not occurred
44355  * - 0b1 - A TX Interrupt has occurred
44356  */
44357 /*@{*/
44358 /*! @brief Read current value of the ZLL_IRQSTS_TXIRQ field. */
44359 #define ZLL_RD_IRQSTS_TXIRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_TXIRQ_MASK) >> ZLL_IRQSTS_TXIRQ_SHIFT)
44360 #define ZLL_BRD_IRQSTS_TXIRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TXIRQ_SHIFT, ZLL_IRQSTS_TXIRQ_WIDTH))
44361 
44362 /*! @brief Set the TXIRQ field to a new value. */
44363 #define ZLL_WR_IRQSTS_TXIRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_TXIRQ_MASK | ZLL_IRQSTS_SEQIRQ_MASK | ZLL_IRQSTS_RXIRQ_MASK | ZLL_IRQSTS_CCAIRQ_MASK | ZLL_IRQSTS_RXWTRMRKIRQ_MASK | ZLL_IRQSTS_FILTERFAIL_IRQ_MASK | ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK | ZLL_IRQSTS_PB_ERR_IRQ_MASK | ZLL_IRQSTS_TMR1IRQ_MASK | ZLL_IRQSTS_TMR2IRQ_MASK | ZLL_IRQSTS_TMR3IRQ_MASK | ZLL_IRQSTS_TMR4IRQ_MASK), ZLL_IRQSTS_TXIRQ(value)))
44364 #define ZLL_BWR_IRQSTS_TXIRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << ZLL_IRQSTS_TXIRQ_SHIFT), ZLL_IRQSTS_TXIRQ_SHIFT, ZLL_IRQSTS_TXIRQ_WIDTH))
44365 /*@}*/
44366 
44367 /*!
44368  * @name Register ZLL_IRQSTS, field RXIRQ[2] (W1C)
44369  *
44370  * Values:
44371  * - 0b0 - A RX Interrupt has not occurred
44372  * - 0b1 - A RX Interrupt has occurred
44373  */
44374 /*@{*/
44375 /*! @brief Read current value of the ZLL_IRQSTS_RXIRQ field. */
44376 #define ZLL_RD_IRQSTS_RXIRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_RXIRQ_MASK) >> ZLL_IRQSTS_RXIRQ_SHIFT)
44377 #define ZLL_BRD_IRQSTS_RXIRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_RXIRQ_SHIFT, ZLL_IRQSTS_RXIRQ_WIDTH))
44378 
44379 /*! @brief Set the RXIRQ field to a new value. */
44380 #define ZLL_WR_IRQSTS_RXIRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_RXIRQ_MASK | ZLL_IRQSTS_SEQIRQ_MASK | ZLL_IRQSTS_TXIRQ_MASK | ZLL_IRQSTS_CCAIRQ_MASK | ZLL_IRQSTS_RXWTRMRKIRQ_MASK | ZLL_IRQSTS_FILTERFAIL_IRQ_MASK | ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK | ZLL_IRQSTS_PB_ERR_IRQ_MASK | ZLL_IRQSTS_TMR1IRQ_MASK | ZLL_IRQSTS_TMR2IRQ_MASK | ZLL_IRQSTS_TMR3IRQ_MASK | ZLL_IRQSTS_TMR4IRQ_MASK), ZLL_IRQSTS_RXIRQ(value)))
44381 #define ZLL_BWR_IRQSTS_RXIRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << ZLL_IRQSTS_RXIRQ_SHIFT), ZLL_IRQSTS_RXIRQ_SHIFT, ZLL_IRQSTS_RXIRQ_WIDTH))
44382 /*@}*/
44383 
44384 /*!
44385  * @name Register ZLL_IRQSTS, field CCAIRQ[3] (W1C)
44386  *
44387  * Values:
44388  * - 0b0 - A CCA Interrupt has not occurred
44389  * - 0b1 - A CCA Interrupt has occurred
44390  */
44391 /*@{*/
44392 /*! @brief Read current value of the ZLL_IRQSTS_CCAIRQ field. */
44393 #define ZLL_RD_IRQSTS_CCAIRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_CCAIRQ_MASK) >> ZLL_IRQSTS_CCAIRQ_SHIFT)
44394 #define ZLL_BRD_IRQSTS_CCAIRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_CCAIRQ_SHIFT, ZLL_IRQSTS_CCAIRQ_WIDTH))
44395 
44396 /*! @brief Set the CCAIRQ field to a new value. */
44397 #define ZLL_WR_IRQSTS_CCAIRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_CCAIRQ_MASK | ZLL_IRQSTS_SEQIRQ_MASK | ZLL_IRQSTS_TXIRQ_MASK | ZLL_IRQSTS_RXIRQ_MASK | ZLL_IRQSTS_RXWTRMRKIRQ_MASK | ZLL_IRQSTS_FILTERFAIL_IRQ_MASK | ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK | ZLL_IRQSTS_PB_ERR_IRQ_MASK | ZLL_IRQSTS_TMR1IRQ_MASK | ZLL_IRQSTS_TMR2IRQ_MASK | ZLL_IRQSTS_TMR3IRQ_MASK | ZLL_IRQSTS_TMR4IRQ_MASK), ZLL_IRQSTS_CCAIRQ(value)))
44398 #define ZLL_BWR_IRQSTS_CCAIRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << ZLL_IRQSTS_CCAIRQ_SHIFT), ZLL_IRQSTS_CCAIRQ_SHIFT, ZLL_IRQSTS_CCAIRQ_WIDTH))
44399 /*@}*/
44400 
44401 /*!
44402  * @name Register ZLL_IRQSTS, field RXWTRMRKIRQ[4] (W1C)
44403  *
44404  * Values:
44405  * - 0b0 - A RX Watermark Interrupt has not occurred
44406  * - 0b1 - A RX Watermark Interrupt has occurred
44407  */
44408 /*@{*/
44409 /*! @brief Read current value of the ZLL_IRQSTS_RXWTRMRKIRQ field. */
44410 #define ZLL_RD_IRQSTS_RXWTRMRKIRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_RXWTRMRKIRQ_MASK) >> ZLL_IRQSTS_RXWTRMRKIRQ_SHIFT)
44411 #define ZLL_BRD_IRQSTS_RXWTRMRKIRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_RXWTRMRKIRQ_SHIFT, ZLL_IRQSTS_RXWTRMRKIRQ_WIDTH))
44412 
44413 /*! @brief Set the RXWTRMRKIRQ field to a new value. */
44414 #define ZLL_WR_IRQSTS_RXWTRMRKIRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_RXWTRMRKIRQ_MASK | ZLL_IRQSTS_SEQIRQ_MASK | ZLL_IRQSTS_TXIRQ_MASK | ZLL_IRQSTS_RXIRQ_MASK | ZLL_IRQSTS_CCAIRQ_MASK | ZLL_IRQSTS_FILTERFAIL_IRQ_MASK | ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK | ZLL_IRQSTS_PB_ERR_IRQ_MASK | ZLL_IRQSTS_TMR1IRQ_MASK | ZLL_IRQSTS_TMR2IRQ_MASK | ZLL_IRQSTS_TMR3IRQ_MASK | ZLL_IRQSTS_TMR4IRQ_MASK), ZLL_IRQSTS_RXWTRMRKIRQ(value)))
44415 #define ZLL_BWR_IRQSTS_RXWTRMRKIRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << ZLL_IRQSTS_RXWTRMRKIRQ_SHIFT), ZLL_IRQSTS_RXWTRMRKIRQ_SHIFT, ZLL_IRQSTS_RXWTRMRKIRQ_WIDTH))
44416 /*@}*/
44417 
44418 /*!
44419  * @name Register ZLL_IRQSTS, field FILTERFAIL_IRQ[5] (W1C)
44420  *
44421  * Values:
44422  * - 0b0 - A Filter Fail Interrupt has not occurred
44423  * - 0b1 - A Filter Fail Interrupt has occurred
44424  */
44425 /*@{*/
44426 /*! @brief Read current value of the ZLL_IRQSTS_FILTERFAIL_IRQ field. */
44427 #define ZLL_RD_IRQSTS_FILTERFAIL_IRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_FILTERFAIL_IRQ_MASK) >> ZLL_IRQSTS_FILTERFAIL_IRQ_SHIFT)
44428 #define ZLL_BRD_IRQSTS_FILTERFAIL_IRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_FILTERFAIL_IRQ_SHIFT, ZLL_IRQSTS_FILTERFAIL_IRQ_WIDTH))
44429 
44430 /*! @brief Set the FILTERFAIL_IRQ field to a new value. */
44431 #define ZLL_WR_IRQSTS_FILTERFAIL_IRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_FILTERFAIL_IRQ_MASK | ZLL_IRQSTS_SEQIRQ_MASK | ZLL_IRQSTS_TXIRQ_MASK | ZLL_IRQSTS_RXIRQ_MASK | ZLL_IRQSTS_CCAIRQ_MASK | ZLL_IRQSTS_RXWTRMRKIRQ_MASK | ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK | ZLL_IRQSTS_PB_ERR_IRQ_MASK | ZLL_IRQSTS_TMR1IRQ_MASK | ZLL_IRQSTS_TMR2IRQ_MASK | ZLL_IRQSTS_TMR3IRQ_MASK | ZLL_IRQSTS_TMR4IRQ_MASK), ZLL_IRQSTS_FILTERFAIL_IRQ(value)))
44432 #define ZLL_BWR_IRQSTS_FILTERFAIL_IRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << ZLL_IRQSTS_FILTERFAIL_IRQ_SHIFT), ZLL_IRQSTS_FILTERFAIL_IRQ_SHIFT, ZLL_IRQSTS_FILTERFAIL_IRQ_WIDTH))
44433 /*@}*/
44434 
44435 /*!
44436  * @name Register ZLL_IRQSTS, field PLL_UNLOCK_IRQ[6] (W1C)
44437  *
44438  * Values:
44439  * - 0b0 - A PLL Unlock Interrupt has not occurred
44440  * - 0b1 - A PLL Unlock Interrupt has occurred
44441  */
44442 /*@{*/
44443 /*! @brief Read current value of the ZLL_IRQSTS_PLL_UNLOCK_IRQ field. */
44444 #define ZLL_RD_IRQSTS_PLL_UNLOCK_IRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK) >> ZLL_IRQSTS_PLL_UNLOCK_IRQ_SHIFT)
44445 #define ZLL_BRD_IRQSTS_PLL_UNLOCK_IRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_PLL_UNLOCK_IRQ_SHIFT, ZLL_IRQSTS_PLL_UNLOCK_IRQ_WIDTH))
44446 
44447 /*! @brief Set the PLL_UNLOCK_IRQ field to a new value. */
44448 #define ZLL_WR_IRQSTS_PLL_UNLOCK_IRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK | ZLL_IRQSTS_SEQIRQ_MASK | ZLL_IRQSTS_TXIRQ_MASK | ZLL_IRQSTS_RXIRQ_MASK | ZLL_IRQSTS_CCAIRQ_MASK | ZLL_IRQSTS_RXWTRMRKIRQ_MASK | ZLL_IRQSTS_FILTERFAIL_IRQ_MASK | ZLL_IRQSTS_PB_ERR_IRQ_MASK | ZLL_IRQSTS_TMR1IRQ_MASK | ZLL_IRQSTS_TMR2IRQ_MASK | ZLL_IRQSTS_TMR3IRQ_MASK | ZLL_IRQSTS_TMR4IRQ_MASK), ZLL_IRQSTS_PLL_UNLOCK_IRQ(value)))
44449 #define ZLL_BWR_IRQSTS_PLL_UNLOCK_IRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << ZLL_IRQSTS_PLL_UNLOCK_IRQ_SHIFT), ZLL_IRQSTS_PLL_UNLOCK_IRQ_SHIFT, ZLL_IRQSTS_PLL_UNLOCK_IRQ_WIDTH))
44450 /*@}*/
44451 
44452 /*!
44453  * @name Register ZLL_IRQSTS, field RX_FRM_PEND[7] (RO)
44454  */
44455 /*@{*/
44456 /*! @brief Read current value of the ZLL_IRQSTS_RX_FRM_PEND field. */
44457 #define ZLL_RD_IRQSTS_RX_FRM_PEND(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_RX_FRM_PEND_MASK) >> ZLL_IRQSTS_RX_FRM_PEND_SHIFT)
44458 #define ZLL_BRD_IRQSTS_RX_FRM_PEND(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_RX_FRM_PEND_SHIFT, ZLL_IRQSTS_RX_FRM_PEND_WIDTH))
44459 /*@}*/
44460 
44461 /*!
44462  * @name Register ZLL_IRQSTS, field PB_ERR_IRQ[9] (W1C)
44463  *
44464  * Values:
44465  * - 0b0 - A Packet Buffer Underrun Error Interrupt has not occurred
44466  * - 0b1 - A Packet Buffer Underrun Error Interrupt has occurred
44467  */
44468 /*@{*/
44469 /*! @brief Read current value of the ZLL_IRQSTS_PB_ERR_IRQ field. */
44470 #define ZLL_RD_IRQSTS_PB_ERR_IRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_PB_ERR_IRQ_MASK) >> ZLL_IRQSTS_PB_ERR_IRQ_SHIFT)
44471 #define ZLL_BRD_IRQSTS_PB_ERR_IRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_PB_ERR_IRQ_SHIFT, ZLL_IRQSTS_PB_ERR_IRQ_WIDTH))
44472 
44473 /*! @brief Set the PB_ERR_IRQ field to a new value. */
44474 #define ZLL_WR_IRQSTS_PB_ERR_IRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_PB_ERR_IRQ_MASK | ZLL_IRQSTS_SEQIRQ_MASK | ZLL_IRQSTS_TXIRQ_MASK | ZLL_IRQSTS_RXIRQ_MASK | ZLL_IRQSTS_CCAIRQ_MASK | ZLL_IRQSTS_RXWTRMRKIRQ_MASK | ZLL_IRQSTS_FILTERFAIL_IRQ_MASK | ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK | ZLL_IRQSTS_TMR1IRQ_MASK | ZLL_IRQSTS_TMR2IRQ_MASK | ZLL_IRQSTS_TMR3IRQ_MASK | ZLL_IRQSTS_TMR4IRQ_MASK), ZLL_IRQSTS_PB_ERR_IRQ(value)))
44475 #define ZLL_BWR_IRQSTS_PB_ERR_IRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << ZLL_IRQSTS_PB_ERR_IRQ_SHIFT), ZLL_IRQSTS_PB_ERR_IRQ_SHIFT, ZLL_IRQSTS_PB_ERR_IRQ_WIDTH))
44476 /*@}*/
44477 
44478 /*!
44479  * @name Register ZLL_IRQSTS, field TMRSTATUS[11] (RO)
44480  *
44481  * Values:
44482  * - 0b0 - no TMRxIRQ is asserted
44483  * - 0b1 - At least one of the TMRxIRQ is asserted (TMR1IRQ, TMR2IRQ, TMR3IRQ,
44484  *     or TMR4IRQ)
44485  */
44486 /*@{*/
44487 /*! @brief Read current value of the ZLL_IRQSTS_TMRSTATUS field. */
44488 #define ZLL_RD_IRQSTS_TMRSTATUS(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_TMRSTATUS_MASK) >> ZLL_IRQSTS_TMRSTATUS_SHIFT)
44489 #define ZLL_BRD_IRQSTS_TMRSTATUS(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMRSTATUS_SHIFT, ZLL_IRQSTS_TMRSTATUS_WIDTH))
44490 /*@}*/
44491 
44492 /*!
44493  * @name Register ZLL_IRQSTS, field PI[12] (RO)
44494  *
44495  * Values:
44496  * - 0b0 - the received packet was not a data request
44497  * - 0b1 - the received packet was a data request, regardless of whether a
44498  *     Source Address table match occurred, or whether Source Address Management is
44499  *     enabled or not
44500  */
44501 /*@{*/
44502 /*! @brief Read current value of the ZLL_IRQSTS_PI field. */
44503 #define ZLL_RD_IRQSTS_PI(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_PI_MASK) >> ZLL_IRQSTS_PI_SHIFT)
44504 #define ZLL_BRD_IRQSTS_PI(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_PI_SHIFT, ZLL_IRQSTS_PI_WIDTH))
44505 /*@}*/
44506 
44507 /*!
44508  * @name Register ZLL_IRQSTS, field SRCADDR[13] (RO)
44509  *
44510  * If Source Address Management is engaged, meaning at least one of the
44511  * following bits is set: SAP0_EN SAA0_EN SAP1_EN SAA1_EN Then SRCADDR will be set to 1
44512  * if the packet just received is a poll request (PI=1), and at least one of the
44513  * following conditions is met: SAP0_EN and SAP0_ADDR_PRESENT SAA0_EN and
44514  * SAA0_ADDR_ABSENT SAP1_EN and SAP1_ADDR_PRESENT SAA1_EN and SAA1_ADDR_ABSENT If
44515  * SRCADDR=1, this indicates to SW that the Packet Processor has determined that an
44516  * auto-TxACK frame must be transmitted with the FramePending subfield of the
44517  * FrameControlField set to 1. HW will assemble and transmit this Ack packet. If the
44518  * above conditions are not met, SRCADDR will be cleared to 0.
44519  */
44520 /*@{*/
44521 /*! @brief Read current value of the ZLL_IRQSTS_SRCADDR field. */
44522 #define ZLL_RD_IRQSTS_SRCADDR(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_SRCADDR_MASK) >> ZLL_IRQSTS_SRCADDR_SHIFT)
44523 #define ZLL_BRD_IRQSTS_SRCADDR(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_SRCADDR_SHIFT, ZLL_IRQSTS_SRCADDR_WIDTH))
44524 /*@}*/
44525 
44526 /*!
44527  * @name Register ZLL_IRQSTS, field CCA[14] (RO)
44528  *
44529  * Channel IDLE/BUSY indicator. This indicator is valid at CCAIRQ and also at
44530  * SEQIRQ. This flag is cleared at next receiver warm up.
44531  *
44532  * Values:
44533  * - 0b0 - IDLE
44534  * - 0b1 - BUSY
44535  */
44536 /*@{*/
44537 /*! @brief Read current value of the ZLL_IRQSTS_CCA field. */
44538 #define ZLL_RD_IRQSTS_CCA(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_CCA_MASK) >> ZLL_IRQSTS_CCA_SHIFT)
44539 #define ZLL_BRD_IRQSTS_CCA(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_CCA_SHIFT, ZLL_IRQSTS_CCA_WIDTH))
44540 /*@}*/
44541 
44542 /*!
44543  * @name Register ZLL_IRQSTS, field CRCVALID[15] (RO)
44544  *
44545  * Code Redundancy Check Valid: This flag indicates the compare result between
44546  * the FCS field, in the most-recently received frame, and the internally
44547  * calculated CRC value. This flag is cleared at next receiver warm up.
44548  *
44549  * Values:
44550  * - 0b0 - Rx FCS != calculated CRC (incorrect)
44551  * - 0b1 - Rx FCS = calculated CRC (correct)
44552  */
44553 /*@{*/
44554 /*! @brief Read current value of the ZLL_IRQSTS_CRCVALID field. */
44555 #define ZLL_RD_IRQSTS_CRCVALID(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_CRCVALID_MASK) >> ZLL_IRQSTS_CRCVALID_SHIFT)
44556 #define ZLL_BRD_IRQSTS_CRCVALID(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_CRCVALID_SHIFT, ZLL_IRQSTS_CRCVALID_WIDTH))
44557 /*@}*/
44558 
44559 /*!
44560  * @name Register ZLL_IRQSTS, field TMR1IRQ[16] (W1C)
44561  *
44562  * Timer Comparator 1 Interrupt Status bit: Indiates T1CMP comparator value
44563  * matched event timer counter. This is write '1' to clear bit
44564  */
44565 /*@{*/
44566 /*! @brief Read current value of the ZLL_IRQSTS_TMR1IRQ field. */
44567 #define ZLL_RD_IRQSTS_TMR1IRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_TMR1IRQ_MASK) >> ZLL_IRQSTS_TMR1IRQ_SHIFT)
44568 #define ZLL_BRD_IRQSTS_TMR1IRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR1IRQ_SHIFT, ZLL_IRQSTS_TMR1IRQ_WIDTH))
44569 
44570 /*! @brief Set the TMR1IRQ field to a new value. */
44571 #define ZLL_WR_IRQSTS_TMR1IRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_TMR1IRQ_MASK | ZLL_IRQSTS_SEQIRQ_MASK | ZLL_IRQSTS_TXIRQ_MASK | ZLL_IRQSTS_RXIRQ_MASK | ZLL_IRQSTS_CCAIRQ_MASK | ZLL_IRQSTS_RXWTRMRKIRQ_MASK | ZLL_IRQSTS_FILTERFAIL_IRQ_MASK | ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK | ZLL_IRQSTS_PB_ERR_IRQ_MASK | ZLL_IRQSTS_TMR2IRQ_MASK | ZLL_IRQSTS_TMR3IRQ_MASK | ZLL_IRQSTS_TMR4IRQ_MASK), ZLL_IRQSTS_TMR1IRQ(value)))
44572 #define ZLL_BWR_IRQSTS_TMR1IRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << ZLL_IRQSTS_TMR1IRQ_SHIFT), ZLL_IRQSTS_TMR1IRQ_SHIFT, ZLL_IRQSTS_TMR1IRQ_WIDTH))
44573 /*@}*/
44574 
44575 /*!
44576  * @name Register ZLL_IRQSTS, field TMR2IRQ[17] (W1C)
44577  *
44578  * Timer Comparator 2 Interrupt Status bit: Indiates comparator value matched
44579  * event timer counter. This flag is shared between the T2CMP (24-bit) and
44580  * T2PRIMECMP (16-bit) compare registers. This is write '1' to clear bit
44581  */
44582 /*@{*/
44583 /*! @brief Read current value of the ZLL_IRQSTS_TMR2IRQ field. */
44584 #define ZLL_RD_IRQSTS_TMR2IRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_TMR2IRQ_MASK) >> ZLL_IRQSTS_TMR2IRQ_SHIFT)
44585 #define ZLL_BRD_IRQSTS_TMR2IRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR2IRQ_SHIFT, ZLL_IRQSTS_TMR2IRQ_WIDTH))
44586 
44587 /*! @brief Set the TMR2IRQ field to a new value. */
44588 #define ZLL_WR_IRQSTS_TMR2IRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_TMR2IRQ_MASK | ZLL_IRQSTS_SEQIRQ_MASK | ZLL_IRQSTS_TXIRQ_MASK | ZLL_IRQSTS_RXIRQ_MASK | ZLL_IRQSTS_CCAIRQ_MASK | ZLL_IRQSTS_RXWTRMRKIRQ_MASK | ZLL_IRQSTS_FILTERFAIL_IRQ_MASK | ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK | ZLL_IRQSTS_PB_ERR_IRQ_MASK | ZLL_IRQSTS_TMR1IRQ_MASK | ZLL_IRQSTS_TMR3IRQ_MASK | ZLL_IRQSTS_TMR4IRQ_MASK), ZLL_IRQSTS_TMR2IRQ(value)))
44589 #define ZLL_BWR_IRQSTS_TMR2IRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << ZLL_IRQSTS_TMR2IRQ_SHIFT), ZLL_IRQSTS_TMR2IRQ_SHIFT, ZLL_IRQSTS_TMR2IRQ_WIDTH))
44590 /*@}*/
44591 
44592 /*!
44593  * @name Register ZLL_IRQSTS, field TMR3IRQ[18] (W1C)
44594  *
44595  * Timer Comparator 3 Interrupt Status bit: Indiates T3CMP comparator value
44596  * matched event timer counter. This is write '1' to clear bit
44597  */
44598 /*@{*/
44599 /*! @brief Read current value of the ZLL_IRQSTS_TMR3IRQ field. */
44600 #define ZLL_RD_IRQSTS_TMR3IRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_TMR3IRQ_MASK) >> ZLL_IRQSTS_TMR3IRQ_SHIFT)
44601 #define ZLL_BRD_IRQSTS_TMR3IRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR3IRQ_SHIFT, ZLL_IRQSTS_TMR3IRQ_WIDTH))
44602 
44603 /*! @brief Set the TMR3IRQ field to a new value. */
44604 #define ZLL_WR_IRQSTS_TMR3IRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_TMR3IRQ_MASK | ZLL_IRQSTS_SEQIRQ_MASK | ZLL_IRQSTS_TXIRQ_MASK | ZLL_IRQSTS_RXIRQ_MASK | ZLL_IRQSTS_CCAIRQ_MASK | ZLL_IRQSTS_RXWTRMRKIRQ_MASK | ZLL_IRQSTS_FILTERFAIL_IRQ_MASK | ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK | ZLL_IRQSTS_PB_ERR_IRQ_MASK | ZLL_IRQSTS_TMR1IRQ_MASK | ZLL_IRQSTS_TMR2IRQ_MASK | ZLL_IRQSTS_TMR4IRQ_MASK), ZLL_IRQSTS_TMR3IRQ(value)))
44605 #define ZLL_BWR_IRQSTS_TMR3IRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << ZLL_IRQSTS_TMR3IRQ_SHIFT), ZLL_IRQSTS_TMR3IRQ_SHIFT, ZLL_IRQSTS_TMR3IRQ_WIDTH))
44606 /*@}*/
44607 
44608 /*!
44609  * @name Register ZLL_IRQSTS, field TMR4IRQ[19] (W1C)
44610  *
44611  * Timer Comparator 4 Interrupt Status bit: Indiates T4CMP comparator value
44612  * matched event timer counter. This is write '1' to clear bit
44613  */
44614 /*@{*/
44615 /*! @brief Read current value of the ZLL_IRQSTS_TMR4IRQ field. */
44616 #define ZLL_RD_IRQSTS_TMR4IRQ(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_TMR4IRQ_MASK) >> ZLL_IRQSTS_TMR4IRQ_SHIFT)
44617 #define ZLL_BRD_IRQSTS_TMR4IRQ(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR4IRQ_SHIFT, ZLL_IRQSTS_TMR4IRQ_WIDTH))
44618 
44619 /*! @brief Set the TMR4IRQ field to a new value. */
44620 #define ZLL_WR_IRQSTS_TMR4IRQ(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_TMR4IRQ_MASK | ZLL_IRQSTS_SEQIRQ_MASK | ZLL_IRQSTS_TXIRQ_MASK | ZLL_IRQSTS_RXIRQ_MASK | ZLL_IRQSTS_CCAIRQ_MASK | ZLL_IRQSTS_RXWTRMRKIRQ_MASK | ZLL_IRQSTS_FILTERFAIL_IRQ_MASK | ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK | ZLL_IRQSTS_PB_ERR_IRQ_MASK | ZLL_IRQSTS_TMR1IRQ_MASK | ZLL_IRQSTS_TMR2IRQ_MASK | ZLL_IRQSTS_TMR3IRQ_MASK), ZLL_IRQSTS_TMR4IRQ(value)))
44621 #define ZLL_BWR_IRQSTS_TMR4IRQ(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << ZLL_IRQSTS_TMR4IRQ_SHIFT), ZLL_IRQSTS_TMR4IRQ_SHIFT, ZLL_IRQSTS_TMR4IRQ_WIDTH))
44622 /*@}*/
44623 
44624 /*!
44625  * @name Register ZLL_IRQSTS, field TMR1MSK[20] (RW)
44626  *
44627  * Values:
44628  * - 0b0 - allows interrupt when comparator matches event timer count
44629  * - 0b1 - Interrupt generation is disabled, but a TMR1IRQ flag can be set
44630  */
44631 /*@{*/
44632 /*! @brief Read current value of the ZLL_IRQSTS_TMR1MSK field. */
44633 #define ZLL_RD_IRQSTS_TMR1MSK(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_TMR1MSK_MASK) >> ZLL_IRQSTS_TMR1MSK_SHIFT)
44634 #define ZLL_BRD_IRQSTS_TMR1MSK(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR1MSK_SHIFT, ZLL_IRQSTS_TMR1MSK_WIDTH))
44635 
44636 /*! @brief Set the TMR1MSK field to a new value. */
44637 #define ZLL_WR_IRQSTS_TMR1MSK(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_TMR1MSK_MASK | ZLL_IRQSTS_SEQIRQ_MASK | ZLL_IRQSTS_TXIRQ_MASK | ZLL_IRQSTS_RXIRQ_MASK | ZLL_IRQSTS_CCAIRQ_MASK | ZLL_IRQSTS_RXWTRMRKIRQ_MASK | ZLL_IRQSTS_FILTERFAIL_IRQ_MASK | ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK | ZLL_IRQSTS_PB_ERR_IRQ_MASK | ZLL_IRQSTS_TMR1IRQ_MASK | ZLL_IRQSTS_TMR2IRQ_MASK | ZLL_IRQSTS_TMR3IRQ_MASK | ZLL_IRQSTS_TMR4IRQ_MASK), ZLL_IRQSTS_TMR1MSK(value)))
44638 #define ZLL_BWR_IRQSTS_TMR1MSK(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << ZLL_IRQSTS_TMR1MSK_SHIFT), ZLL_IRQSTS_TMR1MSK_SHIFT, ZLL_IRQSTS_TMR1MSK_WIDTH))
44639 /*@}*/
44640 
44641 /*!
44642  * @name Register ZLL_IRQSTS, field TMR2MSK[21] (RW)
44643  *
44644  * Values:
44645  * - 0b0 - allows interrupt when comparator matches event timer count
44646  * - 0b1 - Interrupt generation is disabled, but a TMR2IRQ flag can be set
44647  */
44648 /*@{*/
44649 /*! @brief Read current value of the ZLL_IRQSTS_TMR2MSK field. */
44650 #define ZLL_RD_IRQSTS_TMR2MSK(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_TMR2MSK_MASK) >> ZLL_IRQSTS_TMR2MSK_SHIFT)
44651 #define ZLL_BRD_IRQSTS_TMR2MSK(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR2MSK_SHIFT, ZLL_IRQSTS_TMR2MSK_WIDTH))
44652 
44653 /*! @brief Set the TMR2MSK field to a new value. */
44654 #define ZLL_WR_IRQSTS_TMR2MSK(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_TMR2MSK_MASK | ZLL_IRQSTS_SEQIRQ_MASK | ZLL_IRQSTS_TXIRQ_MASK | ZLL_IRQSTS_RXIRQ_MASK | ZLL_IRQSTS_CCAIRQ_MASK | ZLL_IRQSTS_RXWTRMRKIRQ_MASK | ZLL_IRQSTS_FILTERFAIL_IRQ_MASK | ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK | ZLL_IRQSTS_PB_ERR_IRQ_MASK | ZLL_IRQSTS_TMR1IRQ_MASK | ZLL_IRQSTS_TMR2IRQ_MASK | ZLL_IRQSTS_TMR3IRQ_MASK | ZLL_IRQSTS_TMR4IRQ_MASK), ZLL_IRQSTS_TMR2MSK(value)))
44655 #define ZLL_BWR_IRQSTS_TMR2MSK(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << ZLL_IRQSTS_TMR2MSK_SHIFT), ZLL_IRQSTS_TMR2MSK_SHIFT, ZLL_IRQSTS_TMR2MSK_WIDTH))
44656 /*@}*/
44657 
44658 /*!
44659  * @name Register ZLL_IRQSTS, field TMR3MSK[22] (RW)
44660  *
44661  * Values:
44662  * - 0b0 - allows interrupt when comparator matches event timer count
44663  * - 0b1 - Interrupt generation is disabled, but a TMR3IRQ flag can be set
44664  */
44665 /*@{*/
44666 /*! @brief Read current value of the ZLL_IRQSTS_TMR3MSK field. */
44667 #define ZLL_RD_IRQSTS_TMR3MSK(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_TMR3MSK_MASK) >> ZLL_IRQSTS_TMR3MSK_SHIFT)
44668 #define ZLL_BRD_IRQSTS_TMR3MSK(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR3MSK_SHIFT, ZLL_IRQSTS_TMR3MSK_WIDTH))
44669 
44670 /*! @brief Set the TMR3MSK field to a new value. */
44671 #define ZLL_WR_IRQSTS_TMR3MSK(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_TMR3MSK_MASK | ZLL_IRQSTS_SEQIRQ_MASK | ZLL_IRQSTS_TXIRQ_MASK | ZLL_IRQSTS_RXIRQ_MASK | ZLL_IRQSTS_CCAIRQ_MASK | ZLL_IRQSTS_RXWTRMRKIRQ_MASK | ZLL_IRQSTS_FILTERFAIL_IRQ_MASK | ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK | ZLL_IRQSTS_PB_ERR_IRQ_MASK | ZLL_IRQSTS_TMR1IRQ_MASK | ZLL_IRQSTS_TMR2IRQ_MASK | ZLL_IRQSTS_TMR3IRQ_MASK | ZLL_IRQSTS_TMR4IRQ_MASK), ZLL_IRQSTS_TMR3MSK(value)))
44672 #define ZLL_BWR_IRQSTS_TMR3MSK(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << ZLL_IRQSTS_TMR3MSK_SHIFT), ZLL_IRQSTS_TMR3MSK_SHIFT, ZLL_IRQSTS_TMR3MSK_WIDTH))
44673 /*@}*/
44674 
44675 /*!
44676  * @name Register ZLL_IRQSTS, field TMR4MSK[23] (RW)
44677  *
44678  * Values:
44679  * - 0b0 - allows interrupt when comparator matches event timer count
44680  * - 0b1 - Interrupt generation is disabled, but a TMR4IRQ flag can be set
44681  */
44682 /*@{*/
44683 /*! @brief Read current value of the ZLL_IRQSTS_TMR4MSK field. */
44684 #define ZLL_RD_IRQSTS_TMR4MSK(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_TMR4MSK_MASK) >> ZLL_IRQSTS_TMR4MSK_SHIFT)
44685 #define ZLL_BRD_IRQSTS_TMR4MSK(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_TMR4MSK_SHIFT, ZLL_IRQSTS_TMR4MSK_WIDTH))
44686 
44687 /*! @brief Set the TMR4MSK field to a new value. */
44688 #define ZLL_WR_IRQSTS_TMR4MSK(base, value) (ZLL_RMW_IRQSTS(base, (ZLL_IRQSTS_TMR4MSK_MASK | ZLL_IRQSTS_SEQIRQ_MASK | ZLL_IRQSTS_TXIRQ_MASK | ZLL_IRQSTS_RXIRQ_MASK | ZLL_IRQSTS_CCAIRQ_MASK | ZLL_IRQSTS_RXWTRMRKIRQ_MASK | ZLL_IRQSTS_FILTERFAIL_IRQ_MASK | ZLL_IRQSTS_PLL_UNLOCK_IRQ_MASK | ZLL_IRQSTS_PB_ERR_IRQ_MASK | ZLL_IRQSTS_TMR1IRQ_MASK | ZLL_IRQSTS_TMR2IRQ_MASK | ZLL_IRQSTS_TMR3IRQ_MASK | ZLL_IRQSTS_TMR4IRQ_MASK), ZLL_IRQSTS_TMR4MSK(value)))
44689 #define ZLL_BWR_IRQSTS_TMR4MSK(base, value) (BME_BFI32(&ZLL_IRQSTS_REG(base), ((uint32_t)(value) << ZLL_IRQSTS_TMR4MSK_SHIFT), ZLL_IRQSTS_TMR4MSK_SHIFT, ZLL_IRQSTS_TMR4MSK_WIDTH))
44690 /*@}*/
44691 
44692 /*!
44693  * @name Register ZLL_IRQSTS, field RX_FRAME_LENGTH[30:24] (RO)
44694  *
44695  * Contents of the PHR (PHY header), or FrameLength field, of the most recently
44696  * received packet. Read-only.
44697  */
44698 /*@{*/
44699 /*! @brief Read current value of the ZLL_IRQSTS_RX_FRAME_LENGTH field. */
44700 #define ZLL_RD_IRQSTS_RX_FRAME_LENGTH(base) ((ZLL_IRQSTS_REG(base) & ZLL_IRQSTS_RX_FRAME_LENGTH_MASK) >> ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT)
44701 #define ZLL_BRD_IRQSTS_RX_FRAME_LENGTH(base) (BME_UBFX32(&ZLL_IRQSTS_REG(base), ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT, ZLL_IRQSTS_RX_FRAME_LENGTH_WIDTH))
44702 /*@}*/
44703 
44704 /*******************************************************************************
44705  * ZLL_PHY_CTRL - PHY CONTROL
44706  ******************************************************************************/
44707 
44708 /*!
44709  * @brief ZLL_PHY_CTRL - PHY CONTROL (RW)
44710  *
44711  * Reset value: 0x0802FF00U
44712  *
44713  * PHY Control Register
44714  */
44715 /*!
44716  * @name Constants and macros for entire ZLL_PHY_CTRL register
44717  */
44718 /*@{*/
44719 #define ZLL_RD_PHY_CTRL(base)    (ZLL_PHY_CTRL_REG(base))
44720 #define ZLL_WR_PHY_CTRL(base, value) (ZLL_PHY_CTRL_REG(base) = (value))
44721 #define ZLL_RMW_PHY_CTRL(base, mask, value) (ZLL_WR_PHY_CTRL(base, (ZLL_RD_PHY_CTRL(base) & ~(mask)) | (value)))
44722 #define ZLL_SET_PHY_CTRL(base, value) (BME_OR32(&ZLL_PHY_CTRL_REG(base), (uint32_t)(value)))
44723 #define ZLL_CLR_PHY_CTRL(base, value) (BME_AND32(&ZLL_PHY_CTRL_REG(base), (uint32_t)(~(value))))
44724 #define ZLL_TOG_PHY_CTRL(base, value) (BME_XOR32(&ZLL_PHY_CTRL_REG(base), (uint32_t)(value)))
44725 /*@}*/
44726 
44727 /*
44728  * Constants & macros for individual ZLL_PHY_CTRL bitfields
44729  */
44730 
44731 /*!
44732  * @name Register ZLL_PHY_CTRL, field XCVSEQ[2:0] (RW)
44733  *
44734  * The Transceiver Sequence Selector register selects an autosequence for the
44735  * sequence manager to execute. Sequence initiation can be immediate, or scheduled
44736  * (see TMRTRIGEN). A write of XCVSEQ=IDLE will abort any ongoing sequence. A
44737  * write of XCVSEQ=IDLE must always be performed after a sequence is complete, and
44738  * before a new sequence is programmed. Any write to XCVSEQ other than XCVSEQ=IDLE
44739  * during an ongoing sequence, shall be ignored. The mapping of XCVSEQ to
44740  * sequence types is as follows:
44741  *
44742  * Values:
44743  * - 0b000 - I (IDLE)
44744  * - 0b001 - R (RECEIVE)
44745  */
44746 /*@{*/
44747 /*! @brief Read current value of the ZLL_PHY_CTRL_XCVSEQ field. */
44748 #define ZLL_RD_PHY_CTRL_XCVSEQ(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_XCVSEQ_MASK) >> ZLL_PHY_CTRL_XCVSEQ_SHIFT)
44749 #define ZLL_BRD_PHY_CTRL_XCVSEQ(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_XCVSEQ_SHIFT, ZLL_PHY_CTRL_XCVSEQ_WIDTH))
44750 
44751 /*! @brief Set the XCVSEQ field to a new value. */
44752 #define ZLL_WR_PHY_CTRL_XCVSEQ(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_XCVSEQ_MASK, ZLL_PHY_CTRL_XCVSEQ(value)))
44753 #define ZLL_BWR_PHY_CTRL_XCVSEQ(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_XCVSEQ_SHIFT), ZLL_PHY_CTRL_XCVSEQ_SHIFT, ZLL_PHY_CTRL_XCVSEQ_WIDTH))
44754 /*@}*/
44755 
44756 /*!
44757  * @name Register ZLL_PHY_CTRL, field AUTOACK[3] (RW)
44758  *
44759  * Applies only to Sequence R and Sequence TR, ignored during other sequences
44760  *
44761  * Values:
44762  * - 0b0 - sequence manager will not follow a receive frame with a Tx Ack frame,
44763  *     under any conditions; the autosequence will terminate after the receive
44764  *     frame.
44765  * - 0b1 - sequence manager will follow a receive frame with an automatic
44766  *     hardware-generated Tx Ack frame, assuming other necessary conditions are met.
44767  */
44768 /*@{*/
44769 /*! @brief Read current value of the ZLL_PHY_CTRL_AUTOACK field. */
44770 #define ZLL_RD_PHY_CTRL_AUTOACK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_AUTOACK_MASK) >> ZLL_PHY_CTRL_AUTOACK_SHIFT)
44771 #define ZLL_BRD_PHY_CTRL_AUTOACK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_AUTOACK_SHIFT, ZLL_PHY_CTRL_AUTOACK_WIDTH))
44772 
44773 /*! @brief Set the AUTOACK field to a new value. */
44774 #define ZLL_WR_PHY_CTRL_AUTOACK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_AUTOACK_MASK, ZLL_PHY_CTRL_AUTOACK(value)))
44775 #define ZLL_BWR_PHY_CTRL_AUTOACK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_AUTOACK_SHIFT), ZLL_PHY_CTRL_AUTOACK_SHIFT, ZLL_PHY_CTRL_AUTOACK_WIDTH))
44776 /*@}*/
44777 
44778 /*!
44779  * @name Register ZLL_PHY_CTRL, field RXACKRQD[4] (RW)
44780  *
44781  * Applies only to Sequence TR, ignored during all other sequences.
44782  *
44783  * Values:
44784  * - 0b0 - An ordinary receive frame (any type of frame) follows the transmit
44785  *     frame.
44786  * - 0b1 - A receive Ack frame is expected to follow the transmit frame (non-Ack
44787  *     frames are rejected).
44788  */
44789 /*@{*/
44790 /*! @brief Read current value of the ZLL_PHY_CTRL_RXACKRQD field. */
44791 #define ZLL_RD_PHY_CTRL_RXACKRQD(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_RXACKRQD_MASK) >> ZLL_PHY_CTRL_RXACKRQD_SHIFT)
44792 #define ZLL_BRD_PHY_CTRL_RXACKRQD(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_RXACKRQD_SHIFT, ZLL_PHY_CTRL_RXACKRQD_WIDTH))
44793 
44794 /*! @brief Set the RXACKRQD field to a new value. */
44795 #define ZLL_WR_PHY_CTRL_RXACKRQD(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_RXACKRQD_MASK, ZLL_PHY_CTRL_RXACKRQD(value)))
44796 #define ZLL_BWR_PHY_CTRL_RXACKRQD(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_RXACKRQD_SHIFT), ZLL_PHY_CTRL_RXACKRQD_SHIFT, ZLL_PHY_CTRL_RXACKRQD_WIDTH))
44797 /*@}*/
44798 
44799 /*!
44800  * @name Register ZLL_PHY_CTRL, field CCABFRTX[5] (RW)
44801  *
44802  * Applies only to Sequences T and TR, ignored during all other sequences.
44803  *
44804  * Values:
44805  * - 0b0 - no CCA required, transmit operation begins immediately.
44806  * - 0b1 - at least one CCA measurement is required prior to the transmit
44807  *     operation (see also SLOTTED).
44808  */
44809 /*@{*/
44810 /*! @brief Read current value of the ZLL_PHY_CTRL_CCABFRTX field. */
44811 #define ZLL_RD_PHY_CTRL_CCABFRTX(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_CCABFRTX_MASK) >> ZLL_PHY_CTRL_CCABFRTX_SHIFT)
44812 #define ZLL_BRD_PHY_CTRL_CCABFRTX(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_CCABFRTX_SHIFT, ZLL_PHY_CTRL_CCABFRTX_WIDTH))
44813 
44814 /*! @brief Set the CCABFRTX field to a new value. */
44815 #define ZLL_WR_PHY_CTRL_CCABFRTX(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_CCABFRTX_MASK, ZLL_PHY_CTRL_CCABFRTX(value)))
44816 #define ZLL_BWR_PHY_CTRL_CCABFRTX(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_CCABFRTX_SHIFT), ZLL_PHY_CTRL_CCABFRTX_SHIFT, ZLL_PHY_CTRL_CCABFRTX_WIDTH))
44817 /*@}*/
44818 
44819 /*!
44820  * @name Register ZLL_PHY_CTRL, field SLOTTED[6] (RW)
44821  *
44822  * Slotted Mode, for beacon-enabled networks. Applies only to Sequences T, TR,
44823  * and R, ignored during all other sequences. Used, in concert with CCABFRTX, to
44824  * determine how many CCA measurements are required prior to a transmit operation.
44825  * Also used during R sequence to determine whether the ensuing transmit
44826  * acknowledge frame (if any) needs to be synchronized to a backoff slot boundary.
44827  */
44828 /*@{*/
44829 /*! @brief Read current value of the ZLL_PHY_CTRL_SLOTTED field. */
44830 #define ZLL_RD_PHY_CTRL_SLOTTED(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_SLOTTED_MASK) >> ZLL_PHY_CTRL_SLOTTED_SHIFT)
44831 #define ZLL_BRD_PHY_CTRL_SLOTTED(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_SLOTTED_SHIFT, ZLL_PHY_CTRL_SLOTTED_WIDTH))
44832 
44833 /*! @brief Set the SLOTTED field to a new value. */
44834 #define ZLL_WR_PHY_CTRL_SLOTTED(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_SLOTTED_MASK, ZLL_PHY_CTRL_SLOTTED(value)))
44835 #define ZLL_BWR_PHY_CTRL_SLOTTED(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_SLOTTED_SHIFT), ZLL_PHY_CTRL_SLOTTED_SHIFT, ZLL_PHY_CTRL_SLOTTED_WIDTH))
44836 /*@}*/
44837 
44838 /*!
44839  * @name Register ZLL_PHY_CTRL, field TMRTRIGEN[7] (RW)
44840  *
44841  * Values:
44842  * - 0b0 - programmed sequence initiates immediately upon write to XCVSEQ.
44843  * - 0b1 - allow timer TC2 (or TC2') to initiate a preprogrammed sequence (see
44844  *     XCVSEQ register).
44845  */
44846 /*@{*/
44847 /*! @brief Read current value of the ZLL_PHY_CTRL_TMRTRIGEN field. */
44848 #define ZLL_RD_PHY_CTRL_TMRTRIGEN(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_TMRTRIGEN_MASK) >> ZLL_PHY_CTRL_TMRTRIGEN_SHIFT)
44849 #define ZLL_BRD_PHY_CTRL_TMRTRIGEN(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TMRTRIGEN_SHIFT, ZLL_PHY_CTRL_TMRTRIGEN_WIDTH))
44850 
44851 /*! @brief Set the TMRTRIGEN field to a new value. */
44852 #define ZLL_WR_PHY_CTRL_TMRTRIGEN(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_TMRTRIGEN_MASK, ZLL_PHY_CTRL_TMRTRIGEN(value)))
44853 #define ZLL_BWR_PHY_CTRL_TMRTRIGEN(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_TMRTRIGEN_SHIFT), ZLL_PHY_CTRL_TMRTRIGEN_SHIFT, ZLL_PHY_CTRL_TMRTRIGEN_WIDTH))
44854 /*@}*/
44855 
44856 /*!
44857  * @name Register ZLL_PHY_CTRL, field SEQMSK[8] (RW)
44858  *
44859  * Values:
44860  * - 0b0 - allows completion of an autosequence to generate a zigbee interrupt
44861  * - 0b1 - Completion of an autosequence will set the SEQIRQ status bit, but a
44862  *     zigbee interrupt is not generated
44863  */
44864 /*@{*/
44865 /*! @brief Read current value of the ZLL_PHY_CTRL_SEQMSK field. */
44866 #define ZLL_RD_PHY_CTRL_SEQMSK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_SEQMSK_MASK) >> ZLL_PHY_CTRL_SEQMSK_SHIFT)
44867 #define ZLL_BRD_PHY_CTRL_SEQMSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_SEQMSK_SHIFT, ZLL_PHY_CTRL_SEQMSK_WIDTH))
44868 
44869 /*! @brief Set the SEQMSK field to a new value. */
44870 #define ZLL_WR_PHY_CTRL_SEQMSK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_SEQMSK_MASK, ZLL_PHY_CTRL_SEQMSK(value)))
44871 #define ZLL_BWR_PHY_CTRL_SEQMSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_SEQMSK_SHIFT), ZLL_PHY_CTRL_SEQMSK_SHIFT, ZLL_PHY_CTRL_SEQMSK_WIDTH))
44872 /*@}*/
44873 
44874 /*!
44875  * @name Register ZLL_PHY_CTRL, field TXMSK[9] (RW)
44876  *
44877  * Values:
44878  * - 0b0 - allows completion of a TX operation to generate a zigbee interrupt
44879  * - 0b1 - Completion of a TX operation will set the TXIRQ status bit, but a
44880  *     zigbee interrupt is not generated
44881  */
44882 /*@{*/
44883 /*! @brief Read current value of the ZLL_PHY_CTRL_TXMSK field. */
44884 #define ZLL_RD_PHY_CTRL_TXMSK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_TXMSK_MASK) >> ZLL_PHY_CTRL_TXMSK_SHIFT)
44885 #define ZLL_BRD_PHY_CTRL_TXMSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TXMSK_SHIFT, ZLL_PHY_CTRL_TXMSK_WIDTH))
44886 
44887 /*! @brief Set the TXMSK field to a new value. */
44888 #define ZLL_WR_PHY_CTRL_TXMSK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_TXMSK_MASK, ZLL_PHY_CTRL_TXMSK(value)))
44889 #define ZLL_BWR_PHY_CTRL_TXMSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_TXMSK_SHIFT), ZLL_PHY_CTRL_TXMSK_SHIFT, ZLL_PHY_CTRL_TXMSK_WIDTH))
44890 /*@}*/
44891 
44892 /*!
44893  * @name Register ZLL_PHY_CTRL, field RXMSK[10] (RW)
44894  *
44895  * Values:
44896  * - 0b0 - allows completion of a RX operation to generate a zigbee interrupt
44897  * - 0b1 - Completion of a RX operation will set the RXIRQ status bit, but a
44898  *     zigbee interrupt is not generated
44899  */
44900 /*@{*/
44901 /*! @brief Read current value of the ZLL_PHY_CTRL_RXMSK field. */
44902 #define ZLL_RD_PHY_CTRL_RXMSK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_RXMSK_MASK) >> ZLL_PHY_CTRL_RXMSK_SHIFT)
44903 #define ZLL_BRD_PHY_CTRL_RXMSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_RXMSK_SHIFT, ZLL_PHY_CTRL_RXMSK_WIDTH))
44904 
44905 /*! @brief Set the RXMSK field to a new value. */
44906 #define ZLL_WR_PHY_CTRL_RXMSK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_RXMSK_MASK, ZLL_PHY_CTRL_RXMSK(value)))
44907 #define ZLL_BWR_PHY_CTRL_RXMSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_RXMSK_SHIFT), ZLL_PHY_CTRL_RXMSK_SHIFT, ZLL_PHY_CTRL_RXMSK_WIDTH))
44908 /*@}*/
44909 
44910 /*!
44911  * @name Register ZLL_PHY_CTRL, field CCAMSK[11] (RW)
44912  *
44913  * CCA Interrupt Mask
44914  *
44915  * Values:
44916  * - 0b0 - allows completion of a CCA operation to generate a zigbee interrupt
44917  * - 0b1 - Completion of a CCA operation will set the CCAIRQ status bit, but an
44918  *     zigbee interrupt
44919  */
44920 /*@{*/
44921 /*! @brief Read current value of the ZLL_PHY_CTRL_CCAMSK field. */
44922 #define ZLL_RD_PHY_CTRL_CCAMSK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_CCAMSK_MASK) >> ZLL_PHY_CTRL_CCAMSK_SHIFT)
44923 #define ZLL_BRD_PHY_CTRL_CCAMSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_CCAMSK_SHIFT, ZLL_PHY_CTRL_CCAMSK_WIDTH))
44924 
44925 /*! @brief Set the CCAMSK field to a new value. */
44926 #define ZLL_WR_PHY_CTRL_CCAMSK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_CCAMSK_MASK, ZLL_PHY_CTRL_CCAMSK(value)))
44927 #define ZLL_BWR_PHY_CTRL_CCAMSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_CCAMSK_SHIFT), ZLL_PHY_CTRL_CCAMSK_SHIFT, ZLL_PHY_CTRL_CCAMSK_WIDTH))
44928 /*@}*/
44929 
44930 /*!
44931  * @name Register ZLL_PHY_CTRL, field RX_WMRK_MSK[12] (RW)
44932  *
44933  * RX Watermark Interrupt Mask
44934  *
44935  * Values:
44936  * - 0b0 - allows a Received Byte Count match to the RX_WTR_MARK threshold
44937  *     register to generate a zigbee interrupt
44938  * - 0b1 - A Received Byte Count match to the RX_WTR_MARK threshold register
44939  *     will set the RXWTRMRKIRQ status bit, but a zigbee interrupt is not generated
44940  */
44941 /*@{*/
44942 /*! @brief Read current value of the ZLL_PHY_CTRL_RX_WMRK_MSK field. */
44943 #define ZLL_RD_PHY_CTRL_RX_WMRK_MSK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_RX_WMRK_MSK_MASK) >> ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT)
44944 #define ZLL_BRD_PHY_CTRL_RX_WMRK_MSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT, ZLL_PHY_CTRL_RX_WMRK_MSK_WIDTH))
44945 
44946 /*! @brief Set the RX_WMRK_MSK field to a new value. */
44947 #define ZLL_WR_PHY_CTRL_RX_WMRK_MSK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_RX_WMRK_MSK_MASK, ZLL_PHY_CTRL_RX_WMRK_MSK(value)))
44948 #define ZLL_BWR_PHY_CTRL_RX_WMRK_MSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT), ZLL_PHY_CTRL_RX_WMRK_MSK_SHIFT, ZLL_PHY_CTRL_RX_WMRK_MSK_WIDTH))
44949 /*@}*/
44950 
44951 /*!
44952  * @name Register ZLL_PHY_CTRL, field FILTERFAIL_MSK[13] (RW)
44953  *
44954  * FilterFail Interrupt Mask
44955  *
44956  * Values:
44957  * - 0b0 - allows Packet Processor Filtering Failure to generate a zigbee
44958  *     interrupt
44959  * - 0b1 - A Packet Processor Filtering Failure will set the FILTERFAIL_IRQ
44960  *     status bit, but a zigbee interrupt is not generated
44961  */
44962 /*@{*/
44963 /*! @brief Read current value of the ZLL_PHY_CTRL_FILTERFAIL_MSK field. */
44964 #define ZLL_RD_PHY_CTRL_FILTERFAIL_MSK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK) >> ZLL_PHY_CTRL_FILTERFAIL_MSK_SHIFT)
44965 #define ZLL_BRD_PHY_CTRL_FILTERFAIL_MSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_FILTERFAIL_MSK_SHIFT, ZLL_PHY_CTRL_FILTERFAIL_MSK_WIDTH))
44966 
44967 /*! @brief Set the FILTERFAIL_MSK field to a new value. */
44968 #define ZLL_WR_PHY_CTRL_FILTERFAIL_MSK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK, ZLL_PHY_CTRL_FILTERFAIL_MSK(value)))
44969 #define ZLL_BWR_PHY_CTRL_FILTERFAIL_MSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_FILTERFAIL_MSK_SHIFT), ZLL_PHY_CTRL_FILTERFAIL_MSK_SHIFT, ZLL_PHY_CTRL_FILTERFAIL_MSK_WIDTH))
44970 /*@}*/
44971 
44972 /*!
44973  * @name Register ZLL_PHY_CTRL, field PLL_UNLOCK_MSK[14] (RW)
44974  *
44975  * Values:
44976  * - 0b0 - allows PLL unlock event to generate a zigbee interrupt
44977  * - 0b1 - A PLL unlock event will set the PLL_UNLOCK_IRQ status bit, but a
44978  *     zigbee interrupt is not generated
44979  */
44980 /*@{*/
44981 /*! @brief Read current value of the ZLL_PHY_CTRL_PLL_UNLOCK_MSK field. */
44982 #define ZLL_RD_PHY_CTRL_PLL_UNLOCK_MSK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK) >> ZLL_PHY_CTRL_PLL_UNLOCK_MSK_SHIFT)
44983 #define ZLL_BRD_PHY_CTRL_PLL_UNLOCK_MSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_PLL_UNLOCK_MSK_SHIFT, ZLL_PHY_CTRL_PLL_UNLOCK_MSK_WIDTH))
44984 
44985 /*! @brief Set the PLL_UNLOCK_MSK field to a new value. */
44986 #define ZLL_WR_PHY_CTRL_PLL_UNLOCK_MSK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK, ZLL_PHY_CTRL_PLL_UNLOCK_MSK(value)))
44987 #define ZLL_BWR_PHY_CTRL_PLL_UNLOCK_MSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_PLL_UNLOCK_MSK_SHIFT), ZLL_PHY_CTRL_PLL_UNLOCK_MSK_SHIFT, ZLL_PHY_CTRL_PLL_UNLOCK_MSK_WIDTH))
44988 /*@}*/
44989 
44990 /*!
44991  * @name Register ZLL_PHY_CTRL, field CRC_MSK[15] (RW)
44992  *
44993  * CRC Mask
44994  *
44995  * Values:
44996  * - 0b0 - sequence manager ignores CRCVALID and considers the receive operation
44997  *     complete after the last octet of the frame has been received.
44998  * - 0b1 - sequence manager requires CRCVALID=1 at the end of the received frame
44999  *     in order for the receive operation to complete successfully; if
45000  *     CRCVALID=0, sequence manager will return to preamble-detect mode after the last
45001  *     octet of the frame has been received.
45002  */
45003 /*@{*/
45004 /*! @brief Read current value of the ZLL_PHY_CTRL_CRC_MSK field. */
45005 #define ZLL_RD_PHY_CTRL_CRC_MSK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_CRC_MSK_MASK) >> ZLL_PHY_CTRL_CRC_MSK_SHIFT)
45006 #define ZLL_BRD_PHY_CTRL_CRC_MSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_CRC_MSK_SHIFT, ZLL_PHY_CTRL_CRC_MSK_WIDTH))
45007 
45008 /*! @brief Set the CRC_MSK field to a new value. */
45009 #define ZLL_WR_PHY_CTRL_CRC_MSK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_CRC_MSK_MASK, ZLL_PHY_CTRL_CRC_MSK(value)))
45010 #define ZLL_BWR_PHY_CTRL_CRC_MSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_CRC_MSK_SHIFT), ZLL_PHY_CTRL_CRC_MSK_SHIFT, ZLL_PHY_CTRL_CRC_MSK_WIDTH))
45011 /*@}*/
45012 
45013 /*!
45014  * @name Register ZLL_PHY_CTRL, field PB_ERR_MSK[17] (RW)
45015  *
45016  * Values:
45017  * - 0b0 - Enable Packet Buffer Error to assert a zigbee interrupt
45018  * - 0b1 - Mask Packet Buffer Error from generating a zigbee interrupt
45019  */
45020 /*@{*/
45021 /*! @brief Read current value of the ZLL_PHY_CTRL_PB_ERR_MSK field. */
45022 #define ZLL_RD_PHY_CTRL_PB_ERR_MSK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_PB_ERR_MSK_MASK) >> ZLL_PHY_CTRL_PB_ERR_MSK_SHIFT)
45023 #define ZLL_BRD_PHY_CTRL_PB_ERR_MSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_PB_ERR_MSK_SHIFT, ZLL_PHY_CTRL_PB_ERR_MSK_WIDTH))
45024 
45025 /*! @brief Set the PB_ERR_MSK field to a new value. */
45026 #define ZLL_WR_PHY_CTRL_PB_ERR_MSK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_PB_ERR_MSK_MASK, ZLL_PHY_CTRL_PB_ERR_MSK(value)))
45027 #define ZLL_BWR_PHY_CTRL_PB_ERR_MSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_PB_ERR_MSK_SHIFT), ZLL_PHY_CTRL_PB_ERR_MSK_SHIFT, ZLL_PHY_CTRL_PB_ERR_MSK_WIDTH))
45028 /*@}*/
45029 
45030 /*!
45031  * @name Register ZLL_PHY_CTRL, field TMR1CMP_EN[20] (RW)
45032  *
45033  * Values:
45034  * - 0b0 - Don't allow an Event Timer Match to T1CMP to set TMR1IRQ
45035  * - 0b1 - Allow an Event Timer Match to T1CMP to set TMR1IRQ
45036  */
45037 /*@{*/
45038 /*! @brief Read current value of the ZLL_PHY_CTRL_TMR1CMP_EN field. */
45039 #define ZLL_RD_PHY_CTRL_TMR1CMP_EN(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_TMR1CMP_EN_MASK) >> ZLL_PHY_CTRL_TMR1CMP_EN_SHIFT)
45040 #define ZLL_BRD_PHY_CTRL_TMR1CMP_EN(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TMR1CMP_EN_SHIFT, ZLL_PHY_CTRL_TMR1CMP_EN_WIDTH))
45041 
45042 /*! @brief Set the TMR1CMP_EN field to a new value. */
45043 #define ZLL_WR_PHY_CTRL_TMR1CMP_EN(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_TMR1CMP_EN_MASK, ZLL_PHY_CTRL_TMR1CMP_EN(value)))
45044 #define ZLL_BWR_PHY_CTRL_TMR1CMP_EN(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_TMR1CMP_EN_SHIFT), ZLL_PHY_CTRL_TMR1CMP_EN_SHIFT, ZLL_PHY_CTRL_TMR1CMP_EN_WIDTH))
45045 /*@}*/
45046 
45047 /*!
45048  * @name Register ZLL_PHY_CTRL, field TMR2CMP_EN[21] (RW)
45049  *
45050  * Values:
45051  * - 0b0 - Don't allow an Event Timer Match to T2CMP or T2PRIMECMP to set TMR2IRQ
45052  * - 0b1 - Allow an Event Timer Match to T2CMP or T2PRIMECMP to set TMR2IRQ
45053  */
45054 /*@{*/
45055 /*! @brief Read current value of the ZLL_PHY_CTRL_TMR2CMP_EN field. */
45056 #define ZLL_RD_PHY_CTRL_TMR2CMP_EN(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_TMR2CMP_EN_MASK) >> ZLL_PHY_CTRL_TMR2CMP_EN_SHIFT)
45057 #define ZLL_BRD_PHY_CTRL_TMR2CMP_EN(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TMR2CMP_EN_SHIFT, ZLL_PHY_CTRL_TMR2CMP_EN_WIDTH))
45058 
45059 /*! @brief Set the TMR2CMP_EN field to a new value. */
45060 #define ZLL_WR_PHY_CTRL_TMR2CMP_EN(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_TMR2CMP_EN_MASK, ZLL_PHY_CTRL_TMR2CMP_EN(value)))
45061 #define ZLL_BWR_PHY_CTRL_TMR2CMP_EN(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_TMR2CMP_EN_SHIFT), ZLL_PHY_CTRL_TMR2CMP_EN_SHIFT, ZLL_PHY_CTRL_TMR2CMP_EN_WIDTH))
45062 /*@}*/
45063 
45064 /*!
45065  * @name Register ZLL_PHY_CTRL, field TMR3CMP_EN[22] (RW)
45066  *
45067  * Values:
45068  * - 0b0 - Don't allow an Event Timer Match to T3CMP to set TMR3IRQ
45069  * - 0b1 - Allow an Event Timer Match to T3CMP to set TMR3IRQ
45070  */
45071 /*@{*/
45072 /*! @brief Read current value of the ZLL_PHY_CTRL_TMR3CMP_EN field. */
45073 #define ZLL_RD_PHY_CTRL_TMR3CMP_EN(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_TMR3CMP_EN_MASK) >> ZLL_PHY_CTRL_TMR3CMP_EN_SHIFT)
45074 #define ZLL_BRD_PHY_CTRL_TMR3CMP_EN(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TMR3CMP_EN_SHIFT, ZLL_PHY_CTRL_TMR3CMP_EN_WIDTH))
45075 
45076 /*! @brief Set the TMR3CMP_EN field to a new value. */
45077 #define ZLL_WR_PHY_CTRL_TMR3CMP_EN(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_TMR3CMP_EN_MASK, ZLL_PHY_CTRL_TMR3CMP_EN(value)))
45078 #define ZLL_BWR_PHY_CTRL_TMR3CMP_EN(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_TMR3CMP_EN_SHIFT), ZLL_PHY_CTRL_TMR3CMP_EN_SHIFT, ZLL_PHY_CTRL_TMR3CMP_EN_WIDTH))
45079 /*@}*/
45080 
45081 /*!
45082  * @name Register ZLL_PHY_CTRL, field TMR4CMP_EN[23] (RW)
45083  *
45084  * Values:
45085  * - 0b0 - Don't allow an Event Timer Match to T4CMP to set TMR4IRQ
45086  * - 0b1 - Allow an Event Timer Match to T4CMP to set TMR4IRQ
45087  */
45088 /*@{*/
45089 /*! @brief Read current value of the ZLL_PHY_CTRL_TMR4CMP_EN field. */
45090 #define ZLL_RD_PHY_CTRL_TMR4CMP_EN(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_TMR4CMP_EN_MASK) >> ZLL_PHY_CTRL_TMR4CMP_EN_SHIFT)
45091 #define ZLL_BRD_PHY_CTRL_TMR4CMP_EN(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TMR4CMP_EN_SHIFT, ZLL_PHY_CTRL_TMR4CMP_EN_WIDTH))
45092 
45093 /*! @brief Set the TMR4CMP_EN field to a new value. */
45094 #define ZLL_WR_PHY_CTRL_TMR4CMP_EN(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_TMR4CMP_EN_MASK, ZLL_PHY_CTRL_TMR4CMP_EN(value)))
45095 #define ZLL_BWR_PHY_CTRL_TMR4CMP_EN(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_TMR4CMP_EN_SHIFT), ZLL_PHY_CTRL_TMR4CMP_EN_SHIFT, ZLL_PHY_CTRL_TMR4CMP_EN_WIDTH))
45096 /*@}*/
45097 
45098 /*!
45099  * @name Register ZLL_PHY_CTRL, field TC2PRIME_EN[24] (RW)
45100  *
45101  * Values:
45102  * - 0b0 - Don't allow a match of the lower 16 bits of Event Timer to T2PRIMECMP
45103  *     to set TMR2IRQ
45104  * - 0b1 - Allow a match of the lower 16 bits of Event Timer to T2PRIMECMP to
45105  *     set TMR2IRQ
45106  */
45107 /*@{*/
45108 /*! @brief Read current value of the ZLL_PHY_CTRL_TC2PRIME_EN field. */
45109 #define ZLL_RD_PHY_CTRL_TC2PRIME_EN(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_TC2PRIME_EN_MASK) >> ZLL_PHY_CTRL_TC2PRIME_EN_SHIFT)
45110 #define ZLL_BRD_PHY_CTRL_TC2PRIME_EN(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TC2PRIME_EN_SHIFT, ZLL_PHY_CTRL_TC2PRIME_EN_WIDTH))
45111 
45112 /*! @brief Set the TC2PRIME_EN field to a new value. */
45113 #define ZLL_WR_PHY_CTRL_TC2PRIME_EN(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_TC2PRIME_EN_MASK, ZLL_PHY_CTRL_TC2PRIME_EN(value)))
45114 #define ZLL_BWR_PHY_CTRL_TC2PRIME_EN(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_TC2PRIME_EN_SHIFT), ZLL_PHY_CTRL_TC2PRIME_EN_SHIFT, ZLL_PHY_CTRL_TC2PRIME_EN_WIDTH))
45115 /*@}*/
45116 
45117 /*!
45118  * @name Register ZLL_PHY_CTRL, field PROMISCUOUS[25] (RW)
45119  *
45120  * Bypasses most packet filtering.
45121  *
45122  * Values:
45123  * - 0b0 - normal mode
45124  * - 0b1 - all packet filtering except frame length checking (FrameLength>=5 and
45125  *     FrameLength<=127) is bypassed.
45126  */
45127 /*@{*/
45128 /*! @brief Read current value of the ZLL_PHY_CTRL_PROMISCUOUS field. */
45129 #define ZLL_RD_PHY_CTRL_PROMISCUOUS(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_PROMISCUOUS_MASK) >> ZLL_PHY_CTRL_PROMISCUOUS_SHIFT)
45130 #define ZLL_BRD_PHY_CTRL_PROMISCUOUS(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_PROMISCUOUS_SHIFT, ZLL_PHY_CTRL_PROMISCUOUS_WIDTH))
45131 
45132 /*! @brief Set the PROMISCUOUS field to a new value. */
45133 #define ZLL_WR_PHY_CTRL_PROMISCUOUS(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_PROMISCUOUS_MASK, ZLL_PHY_CTRL_PROMISCUOUS(value)))
45134 #define ZLL_BWR_PHY_CTRL_PROMISCUOUS(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_PROMISCUOUS_SHIFT), ZLL_PHY_CTRL_PROMISCUOUS_SHIFT, ZLL_PHY_CTRL_PROMISCUOUS_WIDTH))
45135 /*@}*/
45136 
45137 /*!
45138  * @name Register ZLL_PHY_CTRL, field TMRLOAD[26] (WO)
45139  *
45140  * A low to high transition of this bit causes the contents of register
45141  * T1CMP[23:0] to be loaded into the Event Timer.This is a self clearing bit, always
45142  * reads zero. Note: the TMRLOAD feature requires the Apache RF Oscillator to be
45143  * running; TMRLOAD should not be attempted in the Apache radio gasket-bypass mode.
45144  */
45145 /*@{*/
45146 /*! @brief Set the TMRLOAD field to a new value. */
45147 #define ZLL_WR_PHY_CTRL_TMRLOAD(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_TMRLOAD_MASK, ZLL_PHY_CTRL_TMRLOAD(value)))
45148 #define ZLL_BWR_PHY_CTRL_TMRLOAD(base, value) (ZLL_WR_PHY_CTRL_TMRLOAD(base, value))
45149 /*@}*/
45150 
45151 /*!
45152  * @name Register ZLL_PHY_CTRL, field CCATYPE[28:27] (RW)
45153  *
45154  * Clear Channel Assessment Type. Selects one of four possible functions for CCA
45155  * or Energy Detect, per below.
45156  *
45157  * Values:
45158  * - 0b00 - ENERGY DETECT
45159  * - 0b01 - CCA MODE 1
45160  */
45161 /*@{*/
45162 /*! @brief Read current value of the ZLL_PHY_CTRL_CCATYPE field. */
45163 #define ZLL_RD_PHY_CTRL_CCATYPE(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_CCATYPE_MASK) >> ZLL_PHY_CTRL_CCATYPE_SHIFT)
45164 #define ZLL_BRD_PHY_CTRL_CCATYPE(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_CCATYPE_SHIFT, ZLL_PHY_CTRL_CCATYPE_WIDTH))
45165 
45166 /*! @brief Set the CCATYPE field to a new value. */
45167 #define ZLL_WR_PHY_CTRL_CCATYPE(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_CCATYPE_MASK, ZLL_PHY_CTRL_CCATYPE(value)))
45168 #define ZLL_BWR_PHY_CTRL_CCATYPE(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_CCATYPE_SHIFT), ZLL_PHY_CTRL_CCATYPE_SHIFT, ZLL_PHY_CTRL_CCATYPE_WIDTH))
45169 /*@}*/
45170 
45171 /*!
45172  * @name Register ZLL_PHY_CTRL, field PANCORDNTR0[29] (RW)
45173  *
45174  * Device is a PAN Coordinator on PAN0. Allows device to receive packets with no
45175  * destination address, if Source PAN ID matches.
45176  */
45177 /*@{*/
45178 /*! @brief Read current value of the ZLL_PHY_CTRL_PANCORDNTR0 field. */
45179 #define ZLL_RD_PHY_CTRL_PANCORDNTR0(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_PANCORDNTR0_MASK) >> ZLL_PHY_CTRL_PANCORDNTR0_SHIFT)
45180 #define ZLL_BRD_PHY_CTRL_PANCORDNTR0(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_PANCORDNTR0_SHIFT, ZLL_PHY_CTRL_PANCORDNTR0_WIDTH))
45181 
45182 /*! @brief Set the PANCORDNTR0 field to a new value. */
45183 #define ZLL_WR_PHY_CTRL_PANCORDNTR0(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_PANCORDNTR0_MASK, ZLL_PHY_CTRL_PANCORDNTR0(value)))
45184 #define ZLL_BWR_PHY_CTRL_PANCORDNTR0(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_PANCORDNTR0_SHIFT), ZLL_PHY_CTRL_PANCORDNTR0_SHIFT, ZLL_PHY_CTRL_PANCORDNTR0_WIDTH))
45185 /*@}*/
45186 
45187 /*!
45188  * @name Register ZLL_PHY_CTRL, field TC3TMOUT[30] (RW)
45189  *
45190  * TMR3 Timeout Enable
45191  *
45192  * Values:
45193  * - 0b0 - TMR3 is a software timer only
45194  * - 0b1 - Enable TMR3 to abort Rx or CCCA operations.
45195  */
45196 /*@{*/
45197 /*! @brief Read current value of the ZLL_PHY_CTRL_TC3TMOUT field. */
45198 #define ZLL_RD_PHY_CTRL_TC3TMOUT(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_TC3TMOUT_MASK) >> ZLL_PHY_CTRL_TC3TMOUT_SHIFT)
45199 #define ZLL_BRD_PHY_CTRL_TC3TMOUT(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TC3TMOUT_SHIFT, ZLL_PHY_CTRL_TC3TMOUT_WIDTH))
45200 
45201 /*! @brief Set the TC3TMOUT field to a new value. */
45202 #define ZLL_WR_PHY_CTRL_TC3TMOUT(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_TC3TMOUT_MASK, ZLL_PHY_CTRL_TC3TMOUT(value)))
45203 #define ZLL_BWR_PHY_CTRL_TC3TMOUT(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_TC3TMOUT_SHIFT), ZLL_PHY_CTRL_TC3TMOUT_SHIFT, ZLL_PHY_CTRL_TC3TMOUT_WIDTH))
45204 /*@}*/
45205 
45206 /*!
45207  * @name Register ZLL_PHY_CTRL, field TRCV_MSK[31] (RW)
45208  *
45209  * Transceiver Global Interrupt Mask
45210  *
45211  * Values:
45212  * - 0b0 - Enable any unmasked interrupt source to assert zigbee interrupt
45213  * - 0b1 - Mask all interrupt sources from asserting zigbee interrupt
45214  */
45215 /*@{*/
45216 /*! @brief Read current value of the ZLL_PHY_CTRL_TRCV_MSK field. */
45217 #define ZLL_RD_PHY_CTRL_TRCV_MSK(base) ((ZLL_PHY_CTRL_REG(base) & ZLL_PHY_CTRL_TRCV_MSK_MASK) >> ZLL_PHY_CTRL_TRCV_MSK_SHIFT)
45218 #define ZLL_BRD_PHY_CTRL_TRCV_MSK(base) (BME_UBFX32(&ZLL_PHY_CTRL_REG(base), ZLL_PHY_CTRL_TRCV_MSK_SHIFT, ZLL_PHY_CTRL_TRCV_MSK_WIDTH))
45219 
45220 /*! @brief Set the TRCV_MSK field to a new value. */
45221 #define ZLL_WR_PHY_CTRL_TRCV_MSK(base, value) (ZLL_RMW_PHY_CTRL(base, ZLL_PHY_CTRL_TRCV_MSK_MASK, ZLL_PHY_CTRL_TRCV_MSK(value)))
45222 #define ZLL_BWR_PHY_CTRL_TRCV_MSK(base, value) (BME_BFI32(&ZLL_PHY_CTRL_REG(base), ((uint32_t)(value) << ZLL_PHY_CTRL_TRCV_MSK_SHIFT), ZLL_PHY_CTRL_TRCV_MSK_SHIFT, ZLL_PHY_CTRL_TRCV_MSK_WIDTH))
45223 /*@}*/
45224 
45225 /*******************************************************************************
45226  * ZLL_EVENT_TMR - EVENT TIMER
45227  ******************************************************************************/
45228 
45229 /*!
45230  * @brief ZLL_EVENT_TMR - EVENT TIMER (RO)
45231  *
45232  * Reset value: 0x00000000U
45233  *
45234  * Holds the current value of the 24-bit event timer. The hardware latches the
45235  * upper 2 bytes of EVENT_TMR on each read of least signficant byte.
45236  */
45237 /*!
45238  * @name Constants and macros for entire ZLL_EVENT_TMR register
45239  */
45240 /*@{*/
45241 #define ZLL_RD_EVENT_TMR(base)   (ZLL_EVENT_TMR_REG(base))
45242 /*@}*/
45243 
45244 /*
45245  * Constants & macros for individual ZLL_EVENT_TMR bitfields
45246  */
45247 
45248 /*!
45249  * @name Register ZLL_EVENT_TMR, field EVENT_TMR[23:0] (RO)
45250  */
45251 /*@{*/
45252 /*! @brief Read current value of the ZLL_EVENT_TMR_EVENT_TMR field. */
45253 #define ZLL_RD_EVENT_TMR_EVENT_TMR(base) ((ZLL_EVENT_TMR_REG(base) & ZLL_EVENT_TMR_EVENT_TMR_MASK) >> ZLL_EVENT_TMR_EVENT_TMR_SHIFT)
45254 #define ZLL_BRD_EVENT_TMR_EVENT_TMR(base) (ZLL_RD_EVENT_TMR_EVENT_TMR(base))
45255 /*@}*/
45256 
45257 /*******************************************************************************
45258  * ZLL_TIMESTAMP - TIMESTAMP
45259  ******************************************************************************/
45260 
45261 /*!
45262  * @brief ZLL_TIMESTAMP - TIMESTAMP (RO)
45263  *
45264  * Reset value: 0x00000000U
45265  *
45266  * Holds the latched value of the Event Timer current time corresponding to the
45267  * beginning of the just received Rx packet, at SFD detect.
45268  */
45269 /*!
45270  * @name Constants and macros for entire ZLL_TIMESTAMP register
45271  */
45272 /*@{*/
45273 #define ZLL_RD_TIMESTAMP(base)   (ZLL_TIMESTAMP_REG(base))
45274 /*@}*/
45275 
45276 /*
45277  * Constants & macros for individual ZLL_TIMESTAMP bitfields
45278  */
45279 
45280 /*!
45281  * @name Register ZLL_TIMESTAMP, field TIMESTAMP[23:0] (RO)
45282  */
45283 /*@{*/
45284 /*! @brief Read current value of the ZLL_TIMESTAMP_TIMESTAMP field. */
45285 #define ZLL_RD_TIMESTAMP_TIMESTAMP(base) ((ZLL_TIMESTAMP_REG(base) & ZLL_TIMESTAMP_TIMESTAMP_MASK) >> ZLL_TIMESTAMP_TIMESTAMP_SHIFT)
45286 #define ZLL_BRD_TIMESTAMP_TIMESTAMP(base) (ZLL_RD_TIMESTAMP_TIMESTAMP(base))
45287 /*@}*/
45288 
45289 /*******************************************************************************
45290  * ZLL_T1CMP - T1 COMPARE
45291  ******************************************************************************/
45292 
45293 /*!
45294  * @brief ZLL_T1CMP - T1 COMPARE (RW)
45295  *
45296  * Reset value: 0x00FFFFFFU
45297  *
45298  * TMR1 compare value. If TMR1CMP_EN=1 and the Event Timer matches this value,
45299  * TMR1IRQ is set.
45300  */
45301 /*!
45302  * @name Constants and macros for entire ZLL_T1CMP register
45303  */
45304 /*@{*/
45305 #define ZLL_RD_T1CMP(base)       (ZLL_T1CMP_REG(base))
45306 #define ZLL_WR_T1CMP(base, value) (ZLL_T1CMP_REG(base) = (value))
45307 #define ZLL_RMW_T1CMP(base, mask, value) (ZLL_WR_T1CMP(base, (ZLL_RD_T1CMP(base) & ~(mask)) | (value)))
45308 #define ZLL_SET_T1CMP(base, value) (BME_OR32(&ZLL_T1CMP_REG(base), (uint32_t)(value)))
45309 #define ZLL_CLR_T1CMP(base, value) (BME_AND32(&ZLL_T1CMP_REG(base), (uint32_t)(~(value))))
45310 #define ZLL_TOG_T1CMP(base, value) (BME_XOR32(&ZLL_T1CMP_REG(base), (uint32_t)(value)))
45311 /*@}*/
45312 
45313 /*
45314  * Constants & macros for individual ZLL_T1CMP bitfields
45315  */
45316 
45317 /*!
45318  * @name Register ZLL_T1CMP, field T1CMP[23:0] (RW)
45319  */
45320 /*@{*/
45321 /*! @brief Read current value of the ZLL_T1CMP_T1CMP field. */
45322 #define ZLL_RD_T1CMP_T1CMP(base) ((ZLL_T1CMP_REG(base) & ZLL_T1CMP_T1CMP_MASK) >> ZLL_T1CMP_T1CMP_SHIFT)
45323 #define ZLL_BRD_T1CMP_T1CMP(base) (ZLL_RD_T1CMP_T1CMP(base))
45324 
45325 /*! @brief Set the T1CMP field to a new value. */
45326 #define ZLL_WR_T1CMP_T1CMP(base, value) (ZLL_RMW_T1CMP(base, ZLL_T1CMP_T1CMP_MASK, ZLL_T1CMP_T1CMP(value)))
45327 #define ZLL_BWR_T1CMP_T1CMP(base, value) (ZLL_WR_T1CMP_T1CMP(base, value))
45328 /*@}*/
45329 
45330 /*******************************************************************************
45331  * ZLL_T2CMP - T2 COMPARE
45332  ******************************************************************************/
45333 
45334 /*!
45335  * @brief ZLL_T2CMP - T2 COMPARE (RW)
45336  *
45337  * Reset value: 0x00FFFFFFU
45338  *
45339  * TMR2 compare value. If TMR2CMP_EN=1 and TC2PRIME_EN=0 and the Event Timer
45340  * matches this value, TMR2IRQ is set.
45341  */
45342 /*!
45343  * @name Constants and macros for entire ZLL_T2CMP register
45344  */
45345 /*@{*/
45346 #define ZLL_RD_T2CMP(base)       (ZLL_T2CMP_REG(base))
45347 #define ZLL_WR_T2CMP(base, value) (ZLL_T2CMP_REG(base) = (value))
45348 #define ZLL_RMW_T2CMP(base, mask, value) (ZLL_WR_T2CMP(base, (ZLL_RD_T2CMP(base) & ~(mask)) | (value)))
45349 #define ZLL_SET_T2CMP(base, value) (BME_OR32(&ZLL_T2CMP_REG(base), (uint32_t)(value)))
45350 #define ZLL_CLR_T2CMP(base, value) (BME_AND32(&ZLL_T2CMP_REG(base), (uint32_t)(~(value))))
45351 #define ZLL_TOG_T2CMP(base, value) (BME_XOR32(&ZLL_T2CMP_REG(base), (uint32_t)(value)))
45352 /*@}*/
45353 
45354 /*
45355  * Constants & macros for individual ZLL_T2CMP bitfields
45356  */
45357 
45358 /*!
45359  * @name Register ZLL_T2CMP, field T2CMP[23:0] (RW)
45360  */
45361 /*@{*/
45362 /*! @brief Read current value of the ZLL_T2CMP_T2CMP field. */
45363 #define ZLL_RD_T2CMP_T2CMP(base) ((ZLL_T2CMP_REG(base) & ZLL_T2CMP_T2CMP_MASK) >> ZLL_T2CMP_T2CMP_SHIFT)
45364 #define ZLL_BRD_T2CMP_T2CMP(base) (ZLL_RD_T2CMP_T2CMP(base))
45365 
45366 /*! @brief Set the T2CMP field to a new value. */
45367 #define ZLL_WR_T2CMP_T2CMP(base, value) (ZLL_RMW_T2CMP(base, ZLL_T2CMP_T2CMP_MASK, ZLL_T2CMP_T2CMP(value)))
45368 #define ZLL_BWR_T2CMP_T2CMP(base, value) (ZLL_WR_T2CMP_T2CMP(base, value))
45369 /*@}*/
45370 
45371 /*******************************************************************************
45372  * ZLL_T2PRIMECMP - T2 PRIME COMPARE
45373  ******************************************************************************/
45374 
45375 /*!
45376  * @brief ZLL_T2PRIMECMP - T2 PRIME COMPARE (RW)
45377  *
45378  * Reset value: 0x0000FFFFU
45379  *
45380  * TMR2 compare value. If TMR2CMP_EN=1 and TC2PRIME_EN=1 and the Event Timer
45381  * matches this value, TMR2IRQ is set.
45382  */
45383 /*!
45384  * @name Constants and macros for entire ZLL_T2PRIMECMP register
45385  */
45386 /*@{*/
45387 #define ZLL_RD_T2PRIMECMP(base)  (ZLL_T2PRIMECMP_REG(base))
45388 #define ZLL_WR_T2PRIMECMP(base, value) (ZLL_T2PRIMECMP_REG(base) = (value))
45389 #define ZLL_RMW_T2PRIMECMP(base, mask, value) (ZLL_WR_T2PRIMECMP(base, (ZLL_RD_T2PRIMECMP(base) & ~(mask)) | (value)))
45390 #define ZLL_SET_T2PRIMECMP(base, value) (BME_OR32(&ZLL_T2PRIMECMP_REG(base), (uint32_t)(value)))
45391 #define ZLL_CLR_T2PRIMECMP(base, value) (BME_AND32(&ZLL_T2PRIMECMP_REG(base), (uint32_t)(~(value))))
45392 #define ZLL_TOG_T2PRIMECMP(base, value) (BME_XOR32(&ZLL_T2PRIMECMP_REG(base), (uint32_t)(value)))
45393 /*@}*/
45394 
45395 /*
45396  * Constants & macros for individual ZLL_T2PRIMECMP bitfields
45397  */
45398 
45399 /*!
45400  * @name Register ZLL_T2PRIMECMP, field T2PRIMECMP[15:0] (RW)
45401  */
45402 /*@{*/
45403 /*! @brief Read current value of the ZLL_T2PRIMECMP_T2PRIMECMP field. */
45404 #define ZLL_RD_T2PRIMECMP_T2PRIMECMP(base) ((ZLL_T2PRIMECMP_REG(base) & ZLL_T2PRIMECMP_T2PRIMECMP_MASK) >> ZLL_T2PRIMECMP_T2PRIMECMP_SHIFT)
45405 #define ZLL_BRD_T2PRIMECMP_T2PRIMECMP(base) (BME_UBFX32(&ZLL_T2PRIMECMP_REG(base), ZLL_T2PRIMECMP_T2PRIMECMP_SHIFT, ZLL_T2PRIMECMP_T2PRIMECMP_WIDTH))
45406 
45407 /*! @brief Set the T2PRIMECMP field to a new value. */
45408 #define ZLL_WR_T2PRIMECMP_T2PRIMECMP(base, value) (ZLL_RMW_T2PRIMECMP(base, ZLL_T2PRIMECMP_T2PRIMECMP_MASK, ZLL_T2PRIMECMP_T2PRIMECMP(value)))
45409 #define ZLL_BWR_T2PRIMECMP_T2PRIMECMP(base, value) (BME_BFI32(&ZLL_T2PRIMECMP_REG(base), ((uint32_t)(value) << ZLL_T2PRIMECMP_T2PRIMECMP_SHIFT), ZLL_T2PRIMECMP_T2PRIMECMP_SHIFT, ZLL_T2PRIMECMP_T2PRIMECMP_WIDTH))
45410 /*@}*/
45411 
45412 /*******************************************************************************
45413  * ZLL_T3CMP - T3 COMPARE
45414  ******************************************************************************/
45415 
45416 /*!
45417  * @brief ZLL_T3CMP - T3 COMPARE (RW)
45418  *
45419  * Reset value: 0x00FFFFFFU
45420  *
45421  * TMR3 compare value. If TMR3CMP_EN=1 and the Event Timer matches this value,
45422  * TMR3IRQ is set.
45423  */
45424 /*!
45425  * @name Constants and macros for entire ZLL_T3CMP register
45426  */
45427 /*@{*/
45428 #define ZLL_RD_T3CMP(base)       (ZLL_T3CMP_REG(base))
45429 #define ZLL_WR_T3CMP(base, value) (ZLL_T3CMP_REG(base) = (value))
45430 #define ZLL_RMW_T3CMP(base, mask, value) (ZLL_WR_T3CMP(base, (ZLL_RD_T3CMP(base) & ~(mask)) | (value)))
45431 #define ZLL_SET_T3CMP(base, value) (BME_OR32(&ZLL_T3CMP_REG(base), (uint32_t)(value)))
45432 #define ZLL_CLR_T3CMP(base, value) (BME_AND32(&ZLL_T3CMP_REG(base), (uint32_t)(~(value))))
45433 #define ZLL_TOG_T3CMP(base, value) (BME_XOR32(&ZLL_T3CMP_REG(base), (uint32_t)(value)))
45434 /*@}*/
45435 
45436 /*
45437  * Constants & macros for individual ZLL_T3CMP bitfields
45438  */
45439 
45440 /*!
45441  * @name Register ZLL_T3CMP, field T3CMP[23:0] (RW)
45442  */
45443 /*@{*/
45444 /*! @brief Read current value of the ZLL_T3CMP_T3CMP field. */
45445 #define ZLL_RD_T3CMP_T3CMP(base) ((ZLL_T3CMP_REG(base) & ZLL_T3CMP_T3CMP_MASK) >> ZLL_T3CMP_T3CMP_SHIFT)
45446 #define ZLL_BRD_T3CMP_T3CMP(base) (ZLL_RD_T3CMP_T3CMP(base))
45447 
45448 /*! @brief Set the T3CMP field to a new value. */
45449 #define ZLL_WR_T3CMP_T3CMP(base, value) (ZLL_RMW_T3CMP(base, ZLL_T3CMP_T3CMP_MASK, ZLL_T3CMP_T3CMP(value)))
45450 #define ZLL_BWR_T3CMP_T3CMP(base, value) (ZLL_WR_T3CMP_T3CMP(base, value))
45451 /*@}*/
45452 
45453 /*******************************************************************************
45454  * ZLL_T4CMP - T4 COMPARE
45455  ******************************************************************************/
45456 
45457 /*!
45458  * @brief ZLL_T4CMP - T4 COMPARE (RW)
45459  *
45460  * Reset value: 0x00FFFFFFU
45461  *
45462  * TMR4 compare value. If TMR4CMP_EN=1 and the Event Timer matches this value,
45463  * TMR4IRQ is set.
45464  */
45465 /*!
45466  * @name Constants and macros for entire ZLL_T4CMP register
45467  */
45468 /*@{*/
45469 #define ZLL_RD_T4CMP(base)       (ZLL_T4CMP_REG(base))
45470 #define ZLL_WR_T4CMP(base, value) (ZLL_T4CMP_REG(base) = (value))
45471 #define ZLL_RMW_T4CMP(base, mask, value) (ZLL_WR_T4CMP(base, (ZLL_RD_T4CMP(base) & ~(mask)) | (value)))
45472 #define ZLL_SET_T4CMP(base, value) (BME_OR32(&ZLL_T4CMP_REG(base), (uint32_t)(value)))
45473 #define ZLL_CLR_T4CMP(base, value) (BME_AND32(&ZLL_T4CMP_REG(base), (uint32_t)(~(value))))
45474 #define ZLL_TOG_T4CMP(base, value) (BME_XOR32(&ZLL_T4CMP_REG(base), (uint32_t)(value)))
45475 /*@}*/
45476 
45477 /*
45478  * Constants & macros for individual ZLL_T4CMP bitfields
45479  */
45480 
45481 /*!
45482  * @name Register ZLL_T4CMP, field T4CMP[23:0] (RW)
45483  */
45484 /*@{*/
45485 /*! @brief Read current value of the ZLL_T4CMP_T4CMP field. */
45486 #define ZLL_RD_T4CMP_T4CMP(base) ((ZLL_T4CMP_REG(base) & ZLL_T4CMP_T4CMP_MASK) >> ZLL_T4CMP_T4CMP_SHIFT)
45487 #define ZLL_BRD_T4CMP_T4CMP(base) (ZLL_RD_T4CMP_T4CMP(base))
45488 
45489 /*! @brief Set the T4CMP field to a new value. */
45490 #define ZLL_WR_T4CMP_T4CMP(base, value) (ZLL_RMW_T4CMP(base, ZLL_T4CMP_T4CMP_MASK, ZLL_T4CMP_T4CMP(value)))
45491 #define ZLL_BWR_T4CMP_T4CMP(base, value) (ZLL_WR_T4CMP_T4CMP(base, value))
45492 /*@}*/
45493 
45494 /*******************************************************************************
45495  * ZLL_PA_PWR - PA POWER
45496  ******************************************************************************/
45497 
45498 /*!
45499  * @brief ZLL_PA_PWR - PA POWER (RW)
45500  *
45501  * Reset value: 0x00000008U
45502  *
45503  * PA Target Power used to transmit Zigbee packets
45504  */
45505 /*!
45506  * @name Constants and macros for entire ZLL_PA_PWR register
45507  */
45508 /*@{*/
45509 #define ZLL_RD_PA_PWR(base)      (ZLL_PA_PWR_REG(base))
45510 #define ZLL_WR_PA_PWR(base, value) (ZLL_PA_PWR_REG(base) = (value))
45511 #define ZLL_RMW_PA_PWR(base, mask, value) (ZLL_WR_PA_PWR(base, (ZLL_RD_PA_PWR(base) & ~(mask)) | (value)))
45512 #define ZLL_SET_PA_PWR(base, value) (BME_OR32(&ZLL_PA_PWR_REG(base), (uint32_t)(value)))
45513 #define ZLL_CLR_PA_PWR(base, value) (BME_AND32(&ZLL_PA_PWR_REG(base), (uint32_t)(~(value))))
45514 #define ZLL_TOG_PA_PWR(base, value) (BME_XOR32(&ZLL_PA_PWR_REG(base), (uint32_t)(value)))
45515 /*@}*/
45516 
45517 /*
45518  * Constants & macros for individual ZLL_PA_PWR bitfields
45519  */
45520 
45521 /*!
45522  * @name Register ZLL_PA_PWR, field PA_PWR[3:0] (RW)
45523  */
45524 /*@{*/
45525 /*! @brief Read current value of the ZLL_PA_PWR_PA_PWR field. */
45526 #define ZLL_RD_PA_PWR_PA_PWR(base) ((ZLL_PA_PWR_REG(base) & ZLL_PA_PWR_PA_PWR_MASK) >> ZLL_PA_PWR_PA_PWR_SHIFT)
45527 #define ZLL_BRD_PA_PWR_PA_PWR(base) (BME_UBFX32(&ZLL_PA_PWR_REG(base), ZLL_PA_PWR_PA_PWR_SHIFT, ZLL_PA_PWR_PA_PWR_WIDTH))
45528 
45529 /*! @brief Set the PA_PWR field to a new value. */
45530 #define ZLL_WR_PA_PWR_PA_PWR(base, value) (ZLL_RMW_PA_PWR(base, ZLL_PA_PWR_PA_PWR_MASK, ZLL_PA_PWR_PA_PWR(value)))
45531 #define ZLL_BWR_PA_PWR_PA_PWR(base, value) (BME_BFI32(&ZLL_PA_PWR_REG(base), ((uint32_t)(value) << ZLL_PA_PWR_PA_PWR_SHIFT), ZLL_PA_PWR_PA_PWR_SHIFT, ZLL_PA_PWR_PA_PWR_WIDTH))
45532 /*@}*/
45533 
45534 /*******************************************************************************
45535  * ZLL_CHANNEL_NUM0 - CHANNEL NUMBER 0
45536  ******************************************************************************/
45537 
45538 /*!
45539  * @brief ZLL_CHANNEL_NUM0 - CHANNEL NUMBER 0 (RW)
45540  *
45541  * Reset value: 0x00000012U
45542  *
45543  * This is the mapped channel number used to transmit and receive Zigbee
45544  * packets. If Dual PAN is engaged, this register applies to PAN0. CHANNEL_NUM0 should
45545  * be in the range: 11 <= CHANNEL_NUM0 <= 26
45546  */
45547 /*!
45548  * @name Constants and macros for entire ZLL_CHANNEL_NUM0 register
45549  */
45550 /*@{*/
45551 #define ZLL_RD_CHANNEL_NUM0(base) (ZLL_CHANNEL_NUM0_REG(base))
45552 #define ZLL_WR_CHANNEL_NUM0(base, value) (ZLL_CHANNEL_NUM0_REG(base) = (value))
45553 #define ZLL_RMW_CHANNEL_NUM0(base, mask, value) (ZLL_WR_CHANNEL_NUM0(base, (ZLL_RD_CHANNEL_NUM0(base) & ~(mask)) | (value)))
45554 #define ZLL_SET_CHANNEL_NUM0(base, value) (BME_OR32(&ZLL_CHANNEL_NUM0_REG(base), (uint32_t)(value)))
45555 #define ZLL_CLR_CHANNEL_NUM0(base, value) (BME_AND32(&ZLL_CHANNEL_NUM0_REG(base), (uint32_t)(~(value))))
45556 #define ZLL_TOG_CHANNEL_NUM0(base, value) (BME_XOR32(&ZLL_CHANNEL_NUM0_REG(base), (uint32_t)(value)))
45557 /*@}*/
45558 
45559 /*
45560  * Constants & macros for individual ZLL_CHANNEL_NUM0 bitfields
45561  */
45562 
45563 /*!
45564  * @name Register ZLL_CHANNEL_NUM0, field CHANNEL_NUM0[6:0] (RW)
45565  */
45566 /*@{*/
45567 /*! @brief Read current value of the ZLL_CHANNEL_NUM0_CHANNEL_NUM0 field. */
45568 #define ZLL_RD_CHANNEL_NUM0_CHANNEL_NUM0(base) ((ZLL_CHANNEL_NUM0_REG(base) & ZLL_CHANNEL_NUM0_CHANNEL_NUM0_MASK) >> ZLL_CHANNEL_NUM0_CHANNEL_NUM0_SHIFT)
45569 #define ZLL_BRD_CHANNEL_NUM0_CHANNEL_NUM0(base) (BME_UBFX32(&ZLL_CHANNEL_NUM0_REG(base), ZLL_CHANNEL_NUM0_CHANNEL_NUM0_SHIFT, ZLL_CHANNEL_NUM0_CHANNEL_NUM0_WIDTH))
45570 
45571 /*! @brief Set the CHANNEL_NUM0 field to a new value. */
45572 #define ZLL_WR_CHANNEL_NUM0_CHANNEL_NUM0(base, value) (ZLL_RMW_CHANNEL_NUM0(base, ZLL_CHANNEL_NUM0_CHANNEL_NUM0_MASK, ZLL_CHANNEL_NUM0_CHANNEL_NUM0(value)))
45573 #define ZLL_BWR_CHANNEL_NUM0_CHANNEL_NUM0(base, value) (BME_BFI32(&ZLL_CHANNEL_NUM0_REG(base), ((uint32_t)(value) << ZLL_CHANNEL_NUM0_CHANNEL_NUM0_SHIFT), ZLL_CHANNEL_NUM0_CHANNEL_NUM0_SHIFT, ZLL_CHANNEL_NUM0_CHANNEL_NUM0_WIDTH))
45574 /*@}*/
45575 
45576 /*******************************************************************************
45577  * ZLL_LQI_AND_RSSI - LQI AND RSSI
45578  ******************************************************************************/
45579 
45580 /*!
45581  * @brief ZLL_LQI_AND_RSSI - LQI AND RSSI (RO)
45582  *
45583  * Reset value: 0x00000000U
45584  */
45585 /*!
45586  * @name Constants and macros for entire ZLL_LQI_AND_RSSI register
45587  */
45588 /*@{*/
45589 #define ZLL_RD_LQI_AND_RSSI(base) (ZLL_LQI_AND_RSSI_REG(base))
45590 /*@}*/
45591 
45592 /*
45593  * Constants & macros for individual ZLL_LQI_AND_RSSI bitfields
45594  */
45595 
45596 /*!
45597  * @name Register ZLL_LQI_AND_RSSI, field LQI_VALUE[7:0] (RO)
45598  *
45599  * Link Quality Indicator for the most recently received packet. (LQI is also
45600  * available in the Packet Buffer, at the end of the received packet data)
45601  */
45602 /*@{*/
45603 /*! @brief Read current value of the ZLL_LQI_AND_RSSI_LQI_VALUE field. */
45604 #define ZLL_RD_LQI_AND_RSSI_LQI_VALUE(base) ((ZLL_LQI_AND_RSSI_REG(base) & ZLL_LQI_AND_RSSI_LQI_VALUE_MASK) >> ZLL_LQI_AND_RSSI_LQI_VALUE_SHIFT)
45605 #define ZLL_BRD_LQI_AND_RSSI_LQI_VALUE(base) (BME_UBFX32(&ZLL_LQI_AND_RSSI_REG(base), ZLL_LQI_AND_RSSI_LQI_VALUE_SHIFT, ZLL_LQI_AND_RSSI_LQI_VALUE_WIDTH))
45606 /*@}*/
45607 
45608 /*!
45609  * @name Register ZLL_LQI_AND_RSSI, field RSSI[15:8] (RO)
45610  *
45611  * RSSI Output
45612  */
45613 /*@{*/
45614 /*! @brief Read current value of the ZLL_LQI_AND_RSSI_RSSI field. */
45615 #define ZLL_RD_LQI_AND_RSSI_RSSI(base) ((ZLL_LQI_AND_RSSI_REG(base) & ZLL_LQI_AND_RSSI_RSSI_MASK) >> ZLL_LQI_AND_RSSI_RSSI_SHIFT)
45616 #define ZLL_BRD_LQI_AND_RSSI_RSSI(base) (BME_UBFX32(&ZLL_LQI_AND_RSSI_REG(base), ZLL_LQI_AND_RSSI_RSSI_SHIFT, ZLL_LQI_AND_RSSI_RSSI_WIDTH))
45617 /*@}*/
45618 
45619 /*!
45620  * @name Register ZLL_LQI_AND_RSSI, field CCA1_ED_FNL[23:16] (RO)
45621  *
45622  * Output register to show final averaged RSSI value or compensated value of the
45623  * same at the end of a CCA Mode1 or Energy Detect computation.
45624  */
45625 /*@{*/
45626 /*! @brief Read current value of the ZLL_LQI_AND_RSSI_CCA1_ED_FNL field. */
45627 #define ZLL_RD_LQI_AND_RSSI_CCA1_ED_FNL(base) ((ZLL_LQI_AND_RSSI_REG(base) & ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK) >> ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT)
45628 #define ZLL_BRD_LQI_AND_RSSI_CCA1_ED_FNL(base) (BME_UBFX32(&ZLL_LQI_AND_RSSI_REG(base), ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT, ZLL_LQI_AND_RSSI_CCA1_ED_FNL_WIDTH))
45629 /*@}*/
45630 
45631 /*******************************************************************************
45632  * ZLL_MACSHORTADDRS0 - MAC SHORT ADDRESS 0
45633  ******************************************************************************/
45634 
45635 /*!
45636  * @brief ZLL_MACSHORTADDRS0 - MAC SHORT ADDRESS 0 (RW)
45637  *
45638  * Reset value: 0xFFFFFFFFU
45639  */
45640 /*!
45641  * @name Constants and macros for entire ZLL_MACSHORTADDRS0 register
45642  */
45643 /*@{*/
45644 #define ZLL_RD_MACSHORTADDRS0(base) (ZLL_MACSHORTADDRS0_REG(base))
45645 #define ZLL_WR_MACSHORTADDRS0(base, value) (ZLL_MACSHORTADDRS0_REG(base) = (value))
45646 #define ZLL_RMW_MACSHORTADDRS0(base, mask, value) (ZLL_WR_MACSHORTADDRS0(base, (ZLL_RD_MACSHORTADDRS0(base) & ~(mask)) | (value)))
45647 #define ZLL_SET_MACSHORTADDRS0(base, value) (BME_OR32(&ZLL_MACSHORTADDRS0_REG(base), (uint32_t)(value)))
45648 #define ZLL_CLR_MACSHORTADDRS0(base, value) (BME_AND32(&ZLL_MACSHORTADDRS0_REG(base), (uint32_t)(~(value))))
45649 #define ZLL_TOG_MACSHORTADDRS0(base, value) (BME_XOR32(&ZLL_MACSHORTADDRS0_REG(base), (uint32_t)(value)))
45650 /*@}*/
45651 
45652 /*
45653  * Constants & macros for individual ZLL_MACSHORTADDRS0 bitfields
45654  */
45655 
45656 /*!
45657  * @name Register ZLL_MACSHORTADDRS0, field MACPANID0[15:0] (RW)
45658  *
45659  * MAC PAN ID for PAN0. The packet processor compares the incoming packet's
45660  * Destination PAN ID against the contents of this register to determine if the
45661  * packet is addressed to this device; or if the incoming packet is a Beacon frame,
45662  * the packet processor compares the incoming packet Source PAN ID against this
45663  * register. Also, if PANCORDNTR0=1, and the incoming packet has no Destination
45664  * Address field, and if the incoming packet is a Data or MAC Command frame, the
45665  * packet processor compares the incoming packet Source PAN ID against this register.
45666  */
45667 /*@{*/
45668 /*! @brief Read current value of the ZLL_MACSHORTADDRS0_MACPANID0 field. */
45669 #define ZLL_RD_MACSHORTADDRS0_MACPANID0(base) ((ZLL_MACSHORTADDRS0_REG(base) & ZLL_MACSHORTADDRS0_MACPANID0_MASK) >> ZLL_MACSHORTADDRS0_MACPANID0_SHIFT)
45670 #define ZLL_BRD_MACSHORTADDRS0_MACPANID0(base) (BME_UBFX32(&ZLL_MACSHORTADDRS0_REG(base), ZLL_MACSHORTADDRS0_MACPANID0_SHIFT, ZLL_MACSHORTADDRS0_MACPANID0_WIDTH))
45671 
45672 /*! @brief Set the MACPANID0 field to a new value. */
45673 #define ZLL_WR_MACSHORTADDRS0_MACPANID0(base, value) (ZLL_RMW_MACSHORTADDRS0(base, ZLL_MACSHORTADDRS0_MACPANID0_MASK, ZLL_MACSHORTADDRS0_MACPANID0(value)))
45674 #define ZLL_BWR_MACSHORTADDRS0_MACPANID0(base, value) (BME_BFI32(&ZLL_MACSHORTADDRS0_REG(base), ((uint32_t)(value) << ZLL_MACSHORTADDRS0_MACPANID0_SHIFT), ZLL_MACSHORTADDRS0_MACPANID0_SHIFT, ZLL_MACSHORTADDRS0_MACPANID0_WIDTH))
45675 /*@}*/
45676 
45677 /*!
45678  * @name Register ZLL_MACSHORTADDRS0, field MACSHORTADDRS0[31:16] (RW)
45679  *
45680  * MAC Short Address for PAN0, for 16-bit destination addressing mode. The
45681  * packet processor compares the incoming packet's Destination Address against the
45682  * contents of this register to determine if the packet is addressed to this device.
45683  */
45684 /*@{*/
45685 /*! @brief Read current value of the ZLL_MACSHORTADDRS0_MACSHORTADDRS0 field. */
45686 #define ZLL_RD_MACSHORTADDRS0_MACSHORTADDRS0(base) ((ZLL_MACSHORTADDRS0_REG(base) & ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK) >> ZLL_MACSHORTADDRS0_MACSHORTADDRS0_SHIFT)
45687 #define ZLL_BRD_MACSHORTADDRS0_MACSHORTADDRS0(base) (BME_UBFX32(&ZLL_MACSHORTADDRS0_REG(base), ZLL_MACSHORTADDRS0_MACSHORTADDRS0_SHIFT, ZLL_MACSHORTADDRS0_MACSHORTADDRS0_WIDTH))
45688 
45689 /*! @brief Set the MACSHORTADDRS0 field to a new value. */
45690 #define ZLL_WR_MACSHORTADDRS0_MACSHORTADDRS0(base, value) (ZLL_RMW_MACSHORTADDRS0(base, ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK, ZLL_MACSHORTADDRS0_MACSHORTADDRS0(value)))
45691 #define ZLL_BWR_MACSHORTADDRS0_MACSHORTADDRS0(base, value) (BME_BFI32(&ZLL_MACSHORTADDRS0_REG(base), ((uint32_t)(value) << ZLL_MACSHORTADDRS0_MACSHORTADDRS0_SHIFT), ZLL_MACSHORTADDRS0_MACSHORTADDRS0_SHIFT, ZLL_MACSHORTADDRS0_MACSHORTADDRS0_WIDTH))
45692 /*@}*/
45693 
45694 /*******************************************************************************
45695  * ZLL_MACLONGADDRS0_LSB - MAC LONG ADDRESS 0 LSB
45696  ******************************************************************************/
45697 
45698 /*!
45699  * @brief ZLL_MACLONGADDRS0_LSB - MAC LONG ADDRESS 0 LSB (RW)
45700  *
45701  * Reset value: 0xFFFFFFFFU
45702  *
45703  * MAC Long Address for PAN0, for 64-bit destination addressing mode. The packet
45704  * processor compares the incoming packet's Destination Address against the
45705  * contents of this register to determine if the packet is addressed to this device.
45706  */
45707 /*!
45708  * @name Constants and macros for entire ZLL_MACLONGADDRS0_LSB register
45709  */
45710 /*@{*/
45711 #define ZLL_RD_MACLONGADDRS0_LSB(base) (ZLL_MACLONGADDRS0_LSB_REG(base))
45712 #define ZLL_WR_MACLONGADDRS0_LSB(base, value) (ZLL_MACLONGADDRS0_LSB_REG(base) = (value))
45713 #define ZLL_RMW_MACLONGADDRS0_LSB(base, mask, value) (ZLL_WR_MACLONGADDRS0_LSB(base, (ZLL_RD_MACLONGADDRS0_LSB(base) & ~(mask)) | (value)))
45714 #define ZLL_SET_MACLONGADDRS0_LSB(base, value) (BME_OR32(&ZLL_MACLONGADDRS0_LSB_REG(base), (uint32_t)(value)))
45715 #define ZLL_CLR_MACLONGADDRS0_LSB(base, value) (BME_AND32(&ZLL_MACLONGADDRS0_LSB_REG(base), (uint32_t)(~(value))))
45716 #define ZLL_TOG_MACLONGADDRS0_LSB(base, value) (BME_XOR32(&ZLL_MACLONGADDRS0_LSB_REG(base), (uint32_t)(value)))
45717 /*@}*/
45718 
45719 /*******************************************************************************
45720  * ZLL_MACLONGADDRS0_MSB - MAC LONG ADDRESS 0 MSB
45721  ******************************************************************************/
45722 
45723 /*!
45724  * @brief ZLL_MACLONGADDRS0_MSB - MAC LONG ADDRESS 0 MSB (RW)
45725  *
45726  * Reset value: 0xFFFFFFFFU
45727  *
45728  * MAC Long Address for PAN0, for 64-bit destination addressing mode. The packet
45729  * processor compares the incoming packet's Destination Address against the
45730  * contents of this register to determine if the packet is addressed to this device.
45731  */
45732 /*!
45733  * @name Constants and macros for entire ZLL_MACLONGADDRS0_MSB register
45734  */
45735 /*@{*/
45736 #define ZLL_RD_MACLONGADDRS0_MSB(base) (ZLL_MACLONGADDRS0_MSB_REG(base))
45737 #define ZLL_WR_MACLONGADDRS0_MSB(base, value) (ZLL_MACLONGADDRS0_MSB_REG(base) = (value))
45738 #define ZLL_RMW_MACLONGADDRS0_MSB(base, mask, value) (ZLL_WR_MACLONGADDRS0_MSB(base, (ZLL_RD_MACLONGADDRS0_MSB(base) & ~(mask)) | (value)))
45739 #define ZLL_SET_MACLONGADDRS0_MSB(base, value) (BME_OR32(&ZLL_MACLONGADDRS0_MSB_REG(base), (uint32_t)(value)))
45740 #define ZLL_CLR_MACLONGADDRS0_MSB(base, value) (BME_AND32(&ZLL_MACLONGADDRS0_MSB_REG(base), (uint32_t)(~(value))))
45741 #define ZLL_TOG_MACLONGADDRS0_MSB(base, value) (BME_XOR32(&ZLL_MACLONGADDRS0_MSB_REG(base), (uint32_t)(value)))
45742 /*@}*/
45743 
45744 /*******************************************************************************
45745  * ZLL_RX_FRAME_FILTER - RECEIVE FRAME FILTER
45746  ******************************************************************************/
45747 
45748 /*!
45749  * @brief ZLL_RX_FRAME_FILTER - RECEIVE FRAME FILTER (RW)
45750  *
45751  * Reset value: 0x0000000FU
45752  */
45753 /*!
45754  * @name Constants and macros for entire ZLL_RX_FRAME_FILTER register
45755  */
45756 /*@{*/
45757 #define ZLL_RD_RX_FRAME_FILTER(base) (ZLL_RX_FRAME_FILTER_REG(base))
45758 #define ZLL_WR_RX_FRAME_FILTER(base, value) (ZLL_RX_FRAME_FILTER_REG(base) = (value))
45759 #define ZLL_RMW_RX_FRAME_FILTER(base, mask, value) (ZLL_WR_RX_FRAME_FILTER(base, (ZLL_RD_RX_FRAME_FILTER(base) & ~(mask)) | (value)))
45760 #define ZLL_SET_RX_FRAME_FILTER(base, value) (BME_OR32(&ZLL_RX_FRAME_FILTER_REG(base), (uint32_t)(value)))
45761 #define ZLL_CLR_RX_FRAME_FILTER(base, value) (BME_AND32(&ZLL_RX_FRAME_FILTER_REG(base), (uint32_t)(~(value))))
45762 #define ZLL_TOG_RX_FRAME_FILTER(base, value) (BME_XOR32(&ZLL_RX_FRAME_FILTER_REG(base), (uint32_t)(value)))
45763 /*@}*/
45764 
45765 /*
45766  * Constants & macros for individual ZLL_RX_FRAME_FILTER bitfields
45767  */
45768 
45769 /*!
45770  * @name Register ZLL_RX_FRAME_FILTER, field BEACON_FT[0] (RW)
45771  *
45772  * Values:
45773  * - 0b0 - reject all Beacon frames
45774  * - 0b1 - Beacon frame type enabled.
45775  */
45776 /*@{*/
45777 /*! @brief Read current value of the ZLL_RX_FRAME_FILTER_BEACON_FT field. */
45778 #define ZLL_RD_RX_FRAME_FILTER_BEACON_FT(base) ((ZLL_RX_FRAME_FILTER_REG(base) & ZLL_RX_FRAME_FILTER_BEACON_FT_MASK) >> ZLL_RX_FRAME_FILTER_BEACON_FT_SHIFT)
45779 #define ZLL_BRD_RX_FRAME_FILTER_BEACON_FT(base) (BME_UBFX32(&ZLL_RX_FRAME_FILTER_REG(base), ZLL_RX_FRAME_FILTER_BEACON_FT_SHIFT, ZLL_RX_FRAME_FILTER_BEACON_FT_WIDTH))
45780 
45781 /*! @brief Set the BEACON_FT field to a new value. */
45782 #define ZLL_WR_RX_FRAME_FILTER_BEACON_FT(base, value) (ZLL_RMW_RX_FRAME_FILTER(base, ZLL_RX_FRAME_FILTER_BEACON_FT_MASK, ZLL_RX_FRAME_FILTER_BEACON_FT(value)))
45783 #define ZLL_BWR_RX_FRAME_FILTER_BEACON_FT(base, value) (BME_BFI32(&ZLL_RX_FRAME_FILTER_REG(base), ((uint32_t)(value) << ZLL_RX_FRAME_FILTER_BEACON_FT_SHIFT), ZLL_RX_FRAME_FILTER_BEACON_FT_SHIFT, ZLL_RX_FRAME_FILTER_BEACON_FT_WIDTH))
45784 /*@}*/
45785 
45786 /*!
45787  * @name Register ZLL_RX_FRAME_FILTER, field DATA_FT[1] (RW)
45788  *
45789  * Values:
45790  * - 0b0 - reject all Data frames
45791  * - 0b1 - Data frame type enabled.
45792  */
45793 /*@{*/
45794 /*! @brief Read current value of the ZLL_RX_FRAME_FILTER_DATA_FT field. */
45795 #define ZLL_RD_RX_FRAME_FILTER_DATA_FT(base) ((ZLL_RX_FRAME_FILTER_REG(base) & ZLL_RX_FRAME_FILTER_DATA_FT_MASK) >> ZLL_RX_FRAME_FILTER_DATA_FT_SHIFT)
45796 #define ZLL_BRD_RX_FRAME_FILTER_DATA_FT(base) (BME_UBFX32(&ZLL_RX_FRAME_FILTER_REG(base), ZLL_RX_FRAME_FILTER_DATA_FT_SHIFT, ZLL_RX_FRAME_FILTER_DATA_FT_WIDTH))
45797 
45798 /*! @brief Set the DATA_FT field to a new value. */
45799 #define ZLL_WR_RX_FRAME_FILTER_DATA_FT(base, value) (ZLL_RMW_RX_FRAME_FILTER(base, ZLL_RX_FRAME_FILTER_DATA_FT_MASK, ZLL_RX_FRAME_FILTER_DATA_FT(value)))
45800 #define ZLL_BWR_RX_FRAME_FILTER_DATA_FT(base, value) (BME_BFI32(&ZLL_RX_FRAME_FILTER_REG(base), ((uint32_t)(value) << ZLL_RX_FRAME_FILTER_DATA_FT_SHIFT), ZLL_RX_FRAME_FILTER_DATA_FT_SHIFT, ZLL_RX_FRAME_FILTER_DATA_FT_WIDTH))
45801 /*@}*/
45802 
45803 /*!
45804  * @name Register ZLL_RX_FRAME_FILTER, field ACK_FT[2] (RW)
45805  *
45806  * Values:
45807  * - 0b0 - reject all Acknowledge frames
45808  * - 0b1 - Acknowledge frame type enabled.
45809  */
45810 /*@{*/
45811 /*! @brief Read current value of the ZLL_RX_FRAME_FILTER_ACK_FT field. */
45812 #define ZLL_RD_RX_FRAME_FILTER_ACK_FT(base) ((ZLL_RX_FRAME_FILTER_REG(base) & ZLL_RX_FRAME_FILTER_ACK_FT_MASK) >> ZLL_RX_FRAME_FILTER_ACK_FT_SHIFT)
45813 #define ZLL_BRD_RX_FRAME_FILTER_ACK_FT(base) (BME_UBFX32(&ZLL_RX_FRAME_FILTER_REG(base), ZLL_RX_FRAME_FILTER_ACK_FT_SHIFT, ZLL_RX_FRAME_FILTER_ACK_FT_WIDTH))
45814 
45815 /*! @brief Set the ACK_FT field to a new value. */
45816 #define ZLL_WR_RX_FRAME_FILTER_ACK_FT(base, value) (ZLL_RMW_RX_FRAME_FILTER(base, ZLL_RX_FRAME_FILTER_ACK_FT_MASK, ZLL_RX_FRAME_FILTER_ACK_FT(value)))
45817 #define ZLL_BWR_RX_FRAME_FILTER_ACK_FT(base, value) (BME_BFI32(&ZLL_RX_FRAME_FILTER_REG(base), ((uint32_t)(value) << ZLL_RX_FRAME_FILTER_ACK_FT_SHIFT), ZLL_RX_FRAME_FILTER_ACK_FT_SHIFT, ZLL_RX_FRAME_FILTER_ACK_FT_WIDTH))
45818 /*@}*/
45819 
45820 /*!
45821  * @name Register ZLL_RX_FRAME_FILTER, field CMD_FT[3] (RW)
45822  *
45823  * Values:
45824  * - 0b0 - reject all MAC Command frames
45825  * - 0b1 - MAC Command frame type enabled.
45826  */
45827 /*@{*/
45828 /*! @brief Read current value of the ZLL_RX_FRAME_FILTER_CMD_FT field. */
45829 #define ZLL_RD_RX_FRAME_FILTER_CMD_FT(base) ((ZLL_RX_FRAME_FILTER_REG(base) & ZLL_RX_FRAME_FILTER_CMD_FT_MASK) >> ZLL_RX_FRAME_FILTER_CMD_FT_SHIFT)
45830 #define ZLL_BRD_RX_FRAME_FILTER_CMD_FT(base) (BME_UBFX32(&ZLL_RX_FRAME_FILTER_REG(base), ZLL_RX_FRAME_FILTER_CMD_FT_SHIFT, ZLL_RX_FRAME_FILTER_CMD_FT_WIDTH))
45831 
45832 /*! @brief Set the CMD_FT field to a new value. */
45833 #define ZLL_WR_RX_FRAME_FILTER_CMD_FT(base, value) (ZLL_RMW_RX_FRAME_FILTER(base, ZLL_RX_FRAME_FILTER_CMD_FT_MASK, ZLL_RX_FRAME_FILTER_CMD_FT(value)))
45834 #define ZLL_BWR_RX_FRAME_FILTER_CMD_FT(base, value) (BME_BFI32(&ZLL_RX_FRAME_FILTER_REG(base), ((uint32_t)(value) << ZLL_RX_FRAME_FILTER_CMD_FT_SHIFT), ZLL_RX_FRAME_FILTER_CMD_FT_SHIFT, ZLL_RX_FRAME_FILTER_CMD_FT_WIDTH))
45835 /*@}*/
45836 
45837 /*!
45838  * @name Register ZLL_RX_FRAME_FILTER, field NS_FT[4] (RW)
45839  *
45840  * Values:
45841  * - 0b0 - reject all reserved frame types
45842  * - 0b1 - Not-specified (reserved) frame type enabled. No packet filtering is
45843  *     performed, except for frame length checking (FrameLength>=5 and
45844  *     FrameLength<=127).
45845  */
45846 /*@{*/
45847 /*! @brief Read current value of the ZLL_RX_FRAME_FILTER_NS_FT field. */
45848 #define ZLL_RD_RX_FRAME_FILTER_NS_FT(base) ((ZLL_RX_FRAME_FILTER_REG(base) & ZLL_RX_FRAME_FILTER_NS_FT_MASK) >> ZLL_RX_FRAME_FILTER_NS_FT_SHIFT)
45849 #define ZLL_BRD_RX_FRAME_FILTER_NS_FT(base) (BME_UBFX32(&ZLL_RX_FRAME_FILTER_REG(base), ZLL_RX_FRAME_FILTER_NS_FT_SHIFT, ZLL_RX_FRAME_FILTER_NS_FT_WIDTH))
45850 
45851 /*! @brief Set the NS_FT field to a new value. */
45852 #define ZLL_WR_RX_FRAME_FILTER_NS_FT(base, value) (ZLL_RMW_RX_FRAME_FILTER(base, ZLL_RX_FRAME_FILTER_NS_FT_MASK, ZLL_RX_FRAME_FILTER_NS_FT(value)))
45853 #define ZLL_BWR_RX_FRAME_FILTER_NS_FT(base, value) (BME_BFI32(&ZLL_RX_FRAME_FILTER_REG(base), ((uint32_t)(value) << ZLL_RX_FRAME_FILTER_NS_FT_SHIFT), ZLL_RX_FRAME_FILTER_NS_FT_SHIFT, ZLL_RX_FRAME_FILTER_NS_FT_WIDTH))
45854 /*@}*/
45855 
45856 /*!
45857  * @name Register ZLL_RX_FRAME_FILTER, field ACTIVE_PROMISCUOUS[5] (RW)
45858  *
45859  * Values:
45860  * - 0b0 - normal operation
45861  * - 0b1 - Provide Data Indication on all received packets under the same rules
45862  *     which apply in PROMISCUOUS mode, however acknowledge those packets under
45863  *     rules which apply in non-PROMISCUOUS mode
45864  */
45865 /*@{*/
45866 /*! @brief Read current value of the ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS field. */
45867 #define ZLL_RD_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS(base) ((ZLL_RX_FRAME_FILTER_REG(base) & ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_MASK) >> ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_SHIFT)
45868 #define ZLL_BRD_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS(base) (BME_UBFX32(&ZLL_RX_FRAME_FILTER_REG(base), ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_SHIFT, ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_WIDTH))
45869 
45870 /*! @brief Set the ACTIVE_PROMISCUOUS field to a new value. */
45871 #define ZLL_WR_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS(base, value) (ZLL_RMW_RX_FRAME_FILTER(base, ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_MASK, ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS(value)))
45872 #define ZLL_BWR_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS(base, value) (BME_BFI32(&ZLL_RX_FRAME_FILTER_REG(base), ((uint32_t)(value) << ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_SHIFT), ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_SHIFT, ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_WIDTH))
45873 /*@}*/
45874 
45875 /*!
45876  * @name Register ZLL_RX_FRAME_FILTER, field FRM_VER[7:6] (RW)
45877  *
45878  * Frame Version selector. The incoming packet's Frame Control Field is parsed
45879  * to obtain the FrameVersion subfield, and that value is compared against this
45880  * register, in accordance with the following: 00: Any FrameVersion accepted (0,1,2
45881  * or 3) 01: Only accept FrameVersion 0 packets (2003 compliant) 10: Only accept
45882  * FrameVersion 1 packets (2006 compliant) 11: Accept FrameVersion 0 and 1
45883  * packets, reject all others Frames received with FrameVersion 2 or 3 will be treated
45884  * identically to FrameVersion 1, with respect to parsing of the Auxiliary
45885  * Security Header. Other than this Header, all 4 frame versions will be treated
45886  * identically
45887  */
45888 /*@{*/
45889 /*! @brief Read current value of the ZLL_RX_FRAME_FILTER_FRM_VER field. */
45890 #define ZLL_RD_RX_FRAME_FILTER_FRM_VER(base) ((ZLL_RX_FRAME_FILTER_REG(base) & ZLL_RX_FRAME_FILTER_FRM_VER_MASK) >> ZLL_RX_FRAME_FILTER_FRM_VER_SHIFT)
45891 #define ZLL_BRD_RX_FRAME_FILTER_FRM_VER(base) (BME_UBFX32(&ZLL_RX_FRAME_FILTER_REG(base), ZLL_RX_FRAME_FILTER_FRM_VER_SHIFT, ZLL_RX_FRAME_FILTER_FRM_VER_WIDTH))
45892 
45893 /*! @brief Set the FRM_VER field to a new value. */
45894 #define ZLL_WR_RX_FRAME_FILTER_FRM_VER(base, value) (ZLL_RMW_RX_FRAME_FILTER(base, ZLL_RX_FRAME_FILTER_FRM_VER_MASK, ZLL_RX_FRAME_FILTER_FRM_VER(value)))
45895 #define ZLL_BWR_RX_FRAME_FILTER_FRM_VER(base, value) (BME_BFI32(&ZLL_RX_FRAME_FILTER_REG(base), ((uint32_t)(value) << ZLL_RX_FRAME_FILTER_FRM_VER_SHIFT), ZLL_RX_FRAME_FILTER_FRM_VER_SHIFT, ZLL_RX_FRAME_FILTER_FRM_VER_WIDTH))
45896 /*@}*/
45897 
45898 /*******************************************************************************
45899  * ZLL_CCA_LQI_CTRL - CCA AND LQI CONTROL
45900  ******************************************************************************/
45901 
45902 /*!
45903  * @brief ZLL_CCA_LQI_CTRL - CCA AND LQI CONTROL (RW)
45904  *
45905  * Reset value: 0x0866004BU
45906  */
45907 /*!
45908  * @name Constants and macros for entire ZLL_CCA_LQI_CTRL register
45909  */
45910 /*@{*/
45911 #define ZLL_RD_CCA_LQI_CTRL(base) (ZLL_CCA_LQI_CTRL_REG(base))
45912 #define ZLL_WR_CCA_LQI_CTRL(base, value) (ZLL_CCA_LQI_CTRL_REG(base) = (value))
45913 #define ZLL_RMW_CCA_LQI_CTRL(base, mask, value) (ZLL_WR_CCA_LQI_CTRL(base, (ZLL_RD_CCA_LQI_CTRL(base) & ~(mask)) | (value)))
45914 #define ZLL_SET_CCA_LQI_CTRL(base, value) (BME_OR32(&ZLL_CCA_LQI_CTRL_REG(base), (uint32_t)(value)))
45915 #define ZLL_CLR_CCA_LQI_CTRL(base, value) (BME_AND32(&ZLL_CCA_LQI_CTRL_REG(base), (uint32_t)(~(value))))
45916 #define ZLL_TOG_CCA_LQI_CTRL(base, value) (BME_XOR32(&ZLL_CCA_LQI_CTRL_REG(base), (uint32_t)(value)))
45917 /*@}*/
45918 
45919 /*
45920  * Constants & macros for individual ZLL_CCA_LQI_CTRL bitfields
45921  */
45922 
45923 /*!
45924  * @name Register ZLL_CCA_LQI_CTRL, field CCA1_THRESH[7:0] (RW)
45925  *
45926  * Programmable energy threshold register for CCA mode 1.
45927  */
45928 /*@{*/
45929 /*! @brief Read current value of the ZLL_CCA_LQI_CTRL_CCA1_THRESH field. */
45930 #define ZLL_RD_CCA_LQI_CTRL_CCA1_THRESH(base) ((ZLL_CCA_LQI_CTRL_REG(base) & ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK) >> ZLL_CCA_LQI_CTRL_CCA1_THRESH_SHIFT)
45931 #define ZLL_BRD_CCA_LQI_CTRL_CCA1_THRESH(base) (BME_UBFX32(&ZLL_CCA_LQI_CTRL_REG(base), ZLL_CCA_LQI_CTRL_CCA1_THRESH_SHIFT, ZLL_CCA_LQI_CTRL_CCA1_THRESH_WIDTH))
45932 
45933 /*! @brief Set the CCA1_THRESH field to a new value. */
45934 #define ZLL_WR_CCA_LQI_CTRL_CCA1_THRESH(base, value) (ZLL_RMW_CCA_LQI_CTRL(base, ZLL_CCA_LQI_CTRL_CCA1_THRESH_MASK, ZLL_CCA_LQI_CTRL_CCA1_THRESH(value)))
45935 #define ZLL_BWR_CCA_LQI_CTRL_CCA1_THRESH(base, value) (BME_BFI32(&ZLL_CCA_LQI_CTRL_REG(base), ((uint32_t)(value) << ZLL_CCA_LQI_CTRL_CCA1_THRESH_SHIFT), ZLL_CCA_LQI_CTRL_CCA1_THRESH_SHIFT, ZLL_CCA_LQI_CTRL_CCA1_THRESH_WIDTH))
45936 /*@}*/
45937 
45938 /*!
45939  * @name Register ZLL_CCA_LQI_CTRL, field LQI_OFFSET_COMP[23:16] (RW)
45940  *
45941  * Programmable amount to offset RSSI based LQI value
45942  */
45943 /*@{*/
45944 /*! @brief Read current value of the ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP field. */
45945 #define ZLL_RD_CCA_LQI_CTRL_LQI_OFFSET_COMP(base) ((ZLL_CCA_LQI_CTRL_REG(base) & ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_MASK) >> ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_SHIFT)
45946 #define ZLL_BRD_CCA_LQI_CTRL_LQI_OFFSET_COMP(base) (BME_UBFX32(&ZLL_CCA_LQI_CTRL_REG(base), ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_SHIFT, ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_WIDTH))
45947 
45948 /*! @brief Set the LQI_OFFSET_COMP field to a new value. */
45949 #define ZLL_WR_CCA_LQI_CTRL_LQI_OFFSET_COMP(base, value) (ZLL_RMW_CCA_LQI_CTRL(base, ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_MASK, ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP(value)))
45950 #define ZLL_BWR_CCA_LQI_CTRL_LQI_OFFSET_COMP(base, value) (BME_BFI32(&ZLL_CCA_LQI_CTRL_REG(base), ((uint32_t)(value) << ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_SHIFT), ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_SHIFT, ZLL_CCA_LQI_CTRL_LQI_OFFSET_COMP_WIDTH))
45951 /*@}*/
45952 
45953 /*!
45954  * @name Register ZLL_CCA_LQI_CTRL, field CCA3_AND_NOT_OR[27] (RW)
45955  *
45956  * Determines the way CCA3 is required to be detected
45957  *
45958  * Values:
45959  * - 0b0 - CCA1 or CCA2
45960  * - 0b1 - CCA1 and CCA2
45961  */
45962 /*@{*/
45963 /*! @brief Read current value of the ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR field. */
45964 #define ZLL_RD_CCA_LQI_CTRL_CCA3_AND_NOT_OR(base) ((ZLL_CCA_LQI_CTRL_REG(base) & ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_MASK) >> ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_SHIFT)
45965 #define ZLL_BRD_CCA_LQI_CTRL_CCA3_AND_NOT_OR(base) (BME_UBFX32(&ZLL_CCA_LQI_CTRL_REG(base), ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_SHIFT, ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_WIDTH))
45966 
45967 /*! @brief Set the CCA3_AND_NOT_OR field to a new value. */
45968 #define ZLL_WR_CCA_LQI_CTRL_CCA3_AND_NOT_OR(base, value) (ZLL_RMW_CCA_LQI_CTRL(base, ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_MASK, ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR(value)))
45969 #define ZLL_BWR_CCA_LQI_CTRL_CCA3_AND_NOT_OR(base, value) (BME_BFI32(&ZLL_CCA_LQI_CTRL_REG(base), ((uint32_t)(value) << ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_SHIFT), ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_SHIFT, ZLL_CCA_LQI_CTRL_CCA3_AND_NOT_OR_WIDTH))
45970 /*@}*/
45971 
45972 /*******************************************************************************
45973  * ZLL_CCA2_CTRL - CCA2 CONTROL
45974  ******************************************************************************/
45975 
45976 /*!
45977  * @brief ZLL_CCA2_CTRL - CCA2 CONTROL (RW)
45978  *
45979  * Reset value: 0x00008230U
45980  *
45981  * CCA Mode 2 Control Register
45982  */
45983 /*!
45984  * @name Constants and macros for entire ZLL_CCA2_CTRL register
45985  */
45986 /*@{*/
45987 #define ZLL_RD_CCA2_CTRL(base)   (ZLL_CCA2_CTRL_REG(base))
45988 #define ZLL_WR_CCA2_CTRL(base, value) (ZLL_CCA2_CTRL_REG(base) = (value))
45989 #define ZLL_RMW_CCA2_CTRL(base, mask, value) (ZLL_WR_CCA2_CTRL(base, (ZLL_RD_CCA2_CTRL(base) & ~(mask)) | (value)))
45990 #define ZLL_SET_CCA2_CTRL(base, value) (BME_OR32(&ZLL_CCA2_CTRL_REG(base), (uint32_t)(value)))
45991 #define ZLL_CLR_CCA2_CTRL(base, value) (BME_AND32(&ZLL_CCA2_CTRL_REG(base), (uint32_t)(~(value))))
45992 #define ZLL_TOG_CCA2_CTRL(base, value) (BME_XOR32(&ZLL_CCA2_CTRL_REG(base), (uint32_t)(value)))
45993 /*@}*/
45994 
45995 /*
45996  * Constants & macros for individual ZLL_CCA2_CTRL bitfields
45997  */
45998 
45999 /*!
46000  * @name Register ZLL_CCA2_CTRL, field CCA2_NUM_CORR_PEAKS[3:0] (RO)
46001  *
46002  * Counts of number of peaks that crossed cca2_corr_thresh in CCA Mode 2
46003  * operation
46004  */
46005 /*@{*/
46006 /*! @brief Read current value of the ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS field. */
46007 #define ZLL_RD_CCA2_CTRL_CCA2_NUM_CORR_PEAKS(base) ((ZLL_CCA2_CTRL_REG(base) & ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_MASK) >> ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_SHIFT)
46008 #define ZLL_BRD_CCA2_CTRL_CCA2_NUM_CORR_PEAKS(base) (BME_UBFX32(&ZLL_CCA2_CTRL_REG(base), ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_SHIFT, ZLL_CCA2_CTRL_CCA2_NUM_CORR_PEAKS_WIDTH))
46009 /*@}*/
46010 
46011 /*!
46012  * @name Register ZLL_CCA2_CTRL, field CCA2_MIN_NUM_CORR_TH[6:4] (RW)
46013  *
46014  * Programmable threshold to be compared against number of correlation peaks
46015  * that exceeded cca2_corr_thresh for detecting CCA mode 2. Number of peaks detected
46016  * = cca2_min_num_corr_th + 1; Example: If it is programmed to 3, CCA2 logic
46017  * looks for at least 4 correlation peaks that crossed the threshold, to indicate
46018  * channel is idle or busy.
46019  */
46020 /*@{*/
46021 /*! @brief Read current value of the ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH field. */
46022 #define ZLL_RD_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH(base) ((ZLL_CCA2_CTRL_REG(base) & ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_MASK) >> ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_SHIFT)
46023 #define ZLL_BRD_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH(base) (BME_UBFX32(&ZLL_CCA2_CTRL_REG(base), ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_SHIFT, ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_WIDTH))
46024 
46025 /*! @brief Set the CCA2_MIN_NUM_CORR_TH field to a new value. */
46026 #define ZLL_WR_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH(base, value) (ZLL_RMW_CCA2_CTRL(base, ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_MASK, ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH(value)))
46027 #define ZLL_BWR_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH(base, value) (BME_BFI32(&ZLL_CCA2_CTRL_REG(base), ((uint32_t)(value) << ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_SHIFT), ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_SHIFT, ZLL_CCA2_CTRL_CCA2_MIN_NUM_CORR_TH_WIDTH))
46028 /*@}*/
46029 
46030 /*!
46031  * @name Register ZLL_CCA2_CTRL, field CCA2_CORR_THRESH[15:8] (RW)
46032  *
46033  * Programmable threshold to be compared against number of correlation peaks
46034  * that exceeded cca2_corr_thresh for detecting CCA mode 2. Number of peaks detected
46035  * = cca2_min_num_corr_th + 1; Example: If it is programmed to 3, CCA2 logic
46036  * looks for at least 4 correlation peaks that crossed the threshold, to indicate
46037  * channel is idle or busy.
46038  */
46039 /*@{*/
46040 /*! @brief Read current value of the ZLL_CCA2_CTRL_CCA2_CORR_THRESH field. */
46041 #define ZLL_RD_CCA2_CTRL_CCA2_CORR_THRESH(base) ((ZLL_CCA2_CTRL_REG(base) & ZLL_CCA2_CTRL_CCA2_CORR_THRESH_MASK) >> ZLL_CCA2_CTRL_CCA2_CORR_THRESH_SHIFT)
46042 #define ZLL_BRD_CCA2_CTRL_CCA2_CORR_THRESH(base) (BME_UBFX32(&ZLL_CCA2_CTRL_REG(base), ZLL_CCA2_CTRL_CCA2_CORR_THRESH_SHIFT, ZLL_CCA2_CTRL_CCA2_CORR_THRESH_WIDTH))
46043 
46044 /*! @brief Set the CCA2_CORR_THRESH field to a new value. */
46045 #define ZLL_WR_CCA2_CTRL_CCA2_CORR_THRESH(base, value) (ZLL_RMW_CCA2_CTRL(base, ZLL_CCA2_CTRL_CCA2_CORR_THRESH_MASK, ZLL_CCA2_CTRL_CCA2_CORR_THRESH(value)))
46046 #define ZLL_BWR_CCA2_CTRL_CCA2_CORR_THRESH(base, value) (BME_BFI32(&ZLL_CCA2_CTRL_REG(base), ((uint32_t)(value) << ZLL_CCA2_CTRL_CCA2_CORR_THRESH_SHIFT), ZLL_CCA2_CTRL_CCA2_CORR_THRESH_SHIFT, ZLL_CCA2_CTRL_CCA2_CORR_THRESH_WIDTH))
46047 /*@}*/
46048 
46049 /*******************************************************************************
46050  * ZLL_FAD_CTRL - FAD CONTROL
46051  ******************************************************************************/
46052 
46053 /*!
46054  * @brief ZLL_FAD_CTRL - FAD CONTROL (RW)
46055  *
46056  * Reset value: 0x00000804U
46057  *
46058  * Fast Antenna Diversity Control Register
46059  */
46060 /*!
46061  * @name Constants and macros for entire ZLL_FAD_CTRL register
46062  */
46063 /*@{*/
46064 #define ZLL_RD_FAD_CTRL(base)    (ZLL_FAD_CTRL_REG(base))
46065 #define ZLL_WR_FAD_CTRL(base, value) (ZLL_FAD_CTRL_REG(base) = (value))
46066 #define ZLL_RMW_FAD_CTRL(base, mask, value) (ZLL_WR_FAD_CTRL(base, (ZLL_RD_FAD_CTRL(base) & ~(mask)) | (value)))
46067 #define ZLL_SET_FAD_CTRL(base, value) (BME_OR32(&ZLL_FAD_CTRL_REG(base), (uint32_t)(value)))
46068 #define ZLL_CLR_FAD_CTRL(base, value) (BME_AND32(&ZLL_FAD_CTRL_REG(base), (uint32_t)(~(value))))
46069 #define ZLL_TOG_FAD_CTRL(base, value) (BME_XOR32(&ZLL_FAD_CTRL_REG(base), (uint32_t)(value)))
46070 /*@}*/
46071 
46072 /*
46073  * Constants & macros for individual ZLL_FAD_CTRL bitfields
46074  */
46075 
46076 /*!
46077  * @name Register ZLL_FAD_CTRL, field FAD_EN[0] (RW)
46078  *
46079  * Enable Fast Antenna Diversity for Zigbee
46080  */
46081 /*@{*/
46082 /*! @brief Read current value of the ZLL_FAD_CTRL_FAD_EN field. */
46083 #define ZLL_RD_FAD_CTRL_FAD_EN(base) ((ZLL_FAD_CTRL_REG(base) & ZLL_FAD_CTRL_FAD_EN_MASK) >> ZLL_FAD_CTRL_FAD_EN_SHIFT)
46084 #define ZLL_BRD_FAD_CTRL_FAD_EN(base) (BME_UBFX32(&ZLL_FAD_CTRL_REG(base), ZLL_FAD_CTRL_FAD_EN_SHIFT, ZLL_FAD_CTRL_FAD_EN_WIDTH))
46085 
46086 /*! @brief Set the FAD_EN field to a new value. */
46087 #define ZLL_WR_FAD_CTRL_FAD_EN(base, value) (ZLL_RMW_FAD_CTRL(base, ZLL_FAD_CTRL_FAD_EN_MASK, ZLL_FAD_CTRL_FAD_EN(value)))
46088 #define ZLL_BWR_FAD_CTRL_FAD_EN(base, value) (BME_BFI32(&ZLL_FAD_CTRL_REG(base), ((uint32_t)(value) << ZLL_FAD_CTRL_FAD_EN_SHIFT), ZLL_FAD_CTRL_FAD_EN_SHIFT, ZLL_FAD_CTRL_FAD_EN_WIDTH))
46089 /*@}*/
46090 
46091 /*!
46092  * @name Register ZLL_FAD_CTRL, field ANTX[1] (RW)
46093  *
46094  * If FAD_EN=0, the ANTX bit is used to take manual (software) control of the
46095  * antenna selection, overriding the FAD state machine; in this case, the readback
46096  * value of ANTX is whatever was last written by the host. If FAD_EN=1, the FAD
46097  * state machine controls antenna selection, and the readback value of ANTX
46098  * reflects the machine-selected antenna.
46099  */
46100 /*@{*/
46101 /*! @brief Read current value of the ZLL_FAD_CTRL_ANTX field. */
46102 #define ZLL_RD_FAD_CTRL_ANTX(base) ((ZLL_FAD_CTRL_REG(base) & ZLL_FAD_CTRL_ANTX_MASK) >> ZLL_FAD_CTRL_ANTX_SHIFT)
46103 #define ZLL_BRD_FAD_CTRL_ANTX(base) (BME_UBFX32(&ZLL_FAD_CTRL_REG(base), ZLL_FAD_CTRL_ANTX_SHIFT, ZLL_FAD_CTRL_ANTX_WIDTH))
46104 
46105 /*! @brief Set the ANTX field to a new value. */
46106 #define ZLL_WR_FAD_CTRL_ANTX(base, value) (ZLL_RMW_FAD_CTRL(base, ZLL_FAD_CTRL_ANTX_MASK, ZLL_FAD_CTRL_ANTX(value)))
46107 #define ZLL_BWR_FAD_CTRL_ANTX(base, value) (BME_BFI32(&ZLL_FAD_CTRL_REG(base), ((uint32_t)(value) << ZLL_FAD_CTRL_ANTX_SHIFT), ZLL_FAD_CTRL_ANTX_SHIFT, ZLL_FAD_CTRL_ANTX_WIDTH))
46108 /*@}*/
46109 
46110 /*!
46111  * @name Register ZLL_FAD_CTRL, field FAD_NOT_GPIO[2] (RW)
46112  *
46113  * This bit FAD_NOT_GPIO determines whether the 4 FAD-related pads function in
46114  * FAD mode or in TSM/GPIO mode. The 4 FAD-related pads are: ANT_A, ANT_B,
46115  * TX_SWITCH, and RX_SWITCH. If FAD_NOT_GPIO=1, these pads assume their Zigbee FAD
46116  * functionality If FAD_NOT_GPIO=0, these pads are assigned as TSM GPIO outputs, as
46117  * shown: ANT_A -> GPIO0_TRIG_EN ANT_B -> GPIO1_TRIG_EN TX_SWITCH -> GPIO2_TRIG_EN
46118  * RX_SWITCH -> GPIO3_TRIG_EN To use these pads in TSM GPIO mode, the TSM timing
46119  * registers associated with GPIO0-3 should be programmed with the desired
46120  * timings.
46121  */
46122 /*@{*/
46123 /*! @brief Read current value of the ZLL_FAD_CTRL_FAD_NOT_GPIO field. */
46124 #define ZLL_RD_FAD_CTRL_FAD_NOT_GPIO(base) ((ZLL_FAD_CTRL_REG(base) & ZLL_FAD_CTRL_FAD_NOT_GPIO_MASK) >> ZLL_FAD_CTRL_FAD_NOT_GPIO_SHIFT)
46125 #define ZLL_BRD_FAD_CTRL_FAD_NOT_GPIO(base) (BME_UBFX32(&ZLL_FAD_CTRL_REG(base), ZLL_FAD_CTRL_FAD_NOT_GPIO_SHIFT, ZLL_FAD_CTRL_FAD_NOT_GPIO_WIDTH))
46126 
46127 /*! @brief Set the FAD_NOT_GPIO field to a new value. */
46128 #define ZLL_WR_FAD_CTRL_FAD_NOT_GPIO(base, value) (ZLL_RMW_FAD_CTRL(base, ZLL_FAD_CTRL_FAD_NOT_GPIO_MASK, ZLL_FAD_CTRL_FAD_NOT_GPIO(value)))
46129 #define ZLL_BWR_FAD_CTRL_FAD_NOT_GPIO(base, value) (BME_BFI32(&ZLL_FAD_CTRL_REG(base), ((uint32_t)(value) << ZLL_FAD_CTRL_FAD_NOT_GPIO_SHIFT), ZLL_FAD_CTRL_FAD_NOT_GPIO_SHIFT, ZLL_FAD_CTRL_FAD_NOT_GPIO_WIDTH))
46130 /*@}*/
46131 
46132 /*!
46133  * @name Register ZLL_FAD_CTRL, field ANTX_EN[9:8] (RW)
46134  *
46135  * When FAD_NOT_GPIO=1, ANTX_EN[1:0] determines which pairs of FAD related
46136  * outputs are enabled:
46137  *
46138  * Values:
46139  * - 0b00 - all disabled (held low)
46140  * - 0b01 - only RX/TX_SWITCH enabled
46141  * - 0b10 - only ANT_A/B enabled
46142  * - 0b11 - all enabled
46143  */
46144 /*@{*/
46145 /*! @brief Read current value of the ZLL_FAD_CTRL_ANTX_EN field. */
46146 #define ZLL_RD_FAD_CTRL_ANTX_EN(base) ((ZLL_FAD_CTRL_REG(base) & ZLL_FAD_CTRL_ANTX_EN_MASK) >> ZLL_FAD_CTRL_ANTX_EN_SHIFT)
46147 #define ZLL_BRD_FAD_CTRL_ANTX_EN(base) (BME_UBFX32(&ZLL_FAD_CTRL_REG(base), ZLL_FAD_CTRL_ANTX_EN_SHIFT, ZLL_FAD_CTRL_ANTX_EN_WIDTH))
46148 
46149 /*! @brief Set the ANTX_EN field to a new value. */
46150 #define ZLL_WR_FAD_CTRL_ANTX_EN(base, value) (ZLL_RMW_FAD_CTRL(base, ZLL_FAD_CTRL_ANTX_EN_MASK, ZLL_FAD_CTRL_ANTX_EN(value)))
46151 #define ZLL_BWR_FAD_CTRL_ANTX_EN(base, value) (BME_BFI32(&ZLL_FAD_CTRL_REG(base), ((uint32_t)(value) << ZLL_FAD_CTRL_ANTX_EN_SHIFT), ZLL_FAD_CTRL_ANTX_EN_SHIFT, ZLL_FAD_CTRL_ANTX_EN_WIDTH))
46152 /*@}*/
46153 
46154 /*!
46155  * @name Register ZLL_FAD_CTRL, field ANTX_HZ[10] (RW)
46156  *
46157  * Values:
46158  * - 0b0 - ANT_A, ANT_B, RX_SWITCH and TX_SWITCH are actively driven outputs.
46159  * - 0b1 - Antenna controls high impedance- Set ANT_A, ANT_B, RX_SWITCH and
46160  *     TX_SWITCH in high impedance.
46161  */
46162 /*@{*/
46163 /*! @brief Read current value of the ZLL_FAD_CTRL_ANTX_HZ field. */
46164 #define ZLL_RD_FAD_CTRL_ANTX_HZ(base) ((ZLL_FAD_CTRL_REG(base) & ZLL_FAD_CTRL_ANTX_HZ_MASK) >> ZLL_FAD_CTRL_ANTX_HZ_SHIFT)
46165 #define ZLL_BRD_FAD_CTRL_ANTX_HZ(base) (BME_UBFX32(&ZLL_FAD_CTRL_REG(base), ZLL_FAD_CTRL_ANTX_HZ_SHIFT, ZLL_FAD_CTRL_ANTX_HZ_WIDTH))
46166 
46167 /*! @brief Set the ANTX_HZ field to a new value. */
46168 #define ZLL_WR_FAD_CTRL_ANTX_HZ(base, value) (ZLL_RMW_FAD_CTRL(base, ZLL_FAD_CTRL_ANTX_HZ_MASK, ZLL_FAD_CTRL_ANTX_HZ(value)))
46169 #define ZLL_BWR_FAD_CTRL_ANTX_HZ(base, value) (BME_BFI32(&ZLL_FAD_CTRL_REG(base), ((uint32_t)(value) << ZLL_FAD_CTRL_ANTX_HZ_SHIFT), ZLL_FAD_CTRL_ANTX_HZ_SHIFT, ZLL_FAD_CTRL_ANTX_HZ_WIDTH))
46170 /*@}*/
46171 
46172 /*!
46173  * @name Register ZLL_FAD_CTRL, field ANTX_CTRLMODE[11] (RW)
46174  *
46175  * When ANTX_CTRLMODE=1 (dual mode): ANT_A=NOT(ANTX) AND (GPIO3_TRIG_EN OR
46176  * GPIO2_TRIG_EN) ANT_B=ANTX AND (GPIO3_TRIG_EN OR GPIO2_TRIG_EN)
46177  * TX_SWITCH=GPIO2_TRIG_EN RX_SWITCH=GPIO3_TRIG_EN When ANTX_CTRLMODE=0 (single mode):
46178  * ANT_A=NOT(ANTX) AND (GPIO3_TRIG_EN OR GPIO2_TRIG_EN) ANT_B=ANTX AND (GPIO3_TRIG_EN OR
46179  * GPIO2_TRIG_EN) TX_SWITCH=GPIO2_TRIG_EN RX_SWITCH=(GPIO3_TRIG_EN OR GPIO2_TRIG_EN)
46180  * GPIO2_TRIG_EN and GPIO3_TRIG_EN are outputs of the Transceiver Sequence Manager
46181  * (TSM). The TSM timing registers associated with GPIO2_TRIG_EN and
46182  * GPIO3_TRIG_EN should be programmed with the desired TX_SWITCH and RX_SWITCH timing, before
46183  * enabling Fast Antenna Diversity.
46184  */
46185 /*@{*/
46186 /*! @brief Read current value of the ZLL_FAD_CTRL_ANTX_CTRLMODE field. */
46187 #define ZLL_RD_FAD_CTRL_ANTX_CTRLMODE(base) ((ZLL_FAD_CTRL_REG(base) & ZLL_FAD_CTRL_ANTX_CTRLMODE_MASK) >> ZLL_FAD_CTRL_ANTX_CTRLMODE_SHIFT)
46188 #define ZLL_BRD_FAD_CTRL_ANTX_CTRLMODE(base) (BME_UBFX32(&ZLL_FAD_CTRL_REG(base), ZLL_FAD_CTRL_ANTX_CTRLMODE_SHIFT, ZLL_FAD_CTRL_ANTX_CTRLMODE_WIDTH))
46189 
46190 /*! @brief Set the ANTX_CTRLMODE field to a new value. */
46191 #define ZLL_WR_FAD_CTRL_ANTX_CTRLMODE(base, value) (ZLL_RMW_FAD_CTRL(base, ZLL_FAD_CTRL_ANTX_CTRLMODE_MASK, ZLL_FAD_CTRL_ANTX_CTRLMODE(value)))
46192 #define ZLL_BWR_FAD_CTRL_ANTX_CTRLMODE(base, value) (BME_BFI32(&ZLL_FAD_CTRL_REG(base), ((uint32_t)(value) << ZLL_FAD_CTRL_ANTX_CTRLMODE_SHIFT), ZLL_FAD_CTRL_ANTX_CTRLMODE_SHIFT, ZLL_FAD_CTRL_ANTX_CTRLMODE_WIDTH))
46193 /*@}*/
46194 
46195 /*!
46196  * @name Register ZLL_FAD_CTRL, field ANTX_POL[15:12] (RW)
46197  *
46198  * Control the polarity of the Antenna or Switch control pins: ANTX_POL[0]=0 :
46199  * don't invert the ANT_A output ANTX_POL[1]=0 : don't invert the ANT_B output
46200  * ANTX_POL[2]=0 : don't invert the TX_SWITCH output ANTX_POL[3]=0 : don't invert
46201  * the RX_SWITCH output ANTX_POL[0]=1 : invert the ANT_A output ANTX_POL[1]=1 :
46202  * invert the ANT_B output ANTX_POL[2]=1 : invert the TX_SWITCH output ANTX_POL[3]=1
46203  * : invert the RX_SWITCH output
46204  */
46205 /*@{*/
46206 /*! @brief Read current value of the ZLL_FAD_CTRL_ANTX_POL field. */
46207 #define ZLL_RD_FAD_CTRL_ANTX_POL(base) ((ZLL_FAD_CTRL_REG(base) & ZLL_FAD_CTRL_ANTX_POL_MASK) >> ZLL_FAD_CTRL_ANTX_POL_SHIFT)
46208 #define ZLL_BRD_FAD_CTRL_ANTX_POL(base) (BME_UBFX32(&ZLL_FAD_CTRL_REG(base), ZLL_FAD_CTRL_ANTX_POL_SHIFT, ZLL_FAD_CTRL_ANTX_POL_WIDTH))
46209 
46210 /*! @brief Set the ANTX_POL field to a new value. */
46211 #define ZLL_WR_FAD_CTRL_ANTX_POL(base, value) (ZLL_RMW_FAD_CTRL(base, ZLL_FAD_CTRL_ANTX_POL_MASK, ZLL_FAD_CTRL_ANTX_POL(value)))
46212 #define ZLL_BWR_FAD_CTRL_ANTX_POL(base, value) (BME_BFI32(&ZLL_FAD_CTRL_REG(base), ((uint32_t)(value) << ZLL_FAD_CTRL_ANTX_POL_SHIFT), ZLL_FAD_CTRL_ANTX_POL_SHIFT, ZLL_FAD_CTRL_ANTX_POL_WIDTH))
46213 /*@}*/
46214 
46215 /*******************************************************************************
46216  * ZLL_SNF_CTRL - SNF CONTROL
46217  ******************************************************************************/
46218 
46219 /*!
46220  * @brief ZLL_SNF_CTRL - SNF CONTROL (RW)
46221  *
46222  * Reset value: 0x00000000U
46223  *
46224  * SNIFF Mode Control Register
46225  */
46226 /*!
46227  * @name Constants and macros for entire ZLL_SNF_CTRL register
46228  */
46229 /*@{*/
46230 #define ZLL_RD_SNF_CTRL(base)    (ZLL_SNF_CTRL_REG(base))
46231 #define ZLL_WR_SNF_CTRL(base, value) (ZLL_SNF_CTRL_REG(base) = (value))
46232 #define ZLL_RMW_SNF_CTRL(base, mask, value) (ZLL_WR_SNF_CTRL(base, (ZLL_RD_SNF_CTRL(base) & ~(mask)) | (value)))
46233 #define ZLL_SET_SNF_CTRL(base, value) (BME_OR32(&ZLL_SNF_CTRL_REG(base), (uint32_t)(value)))
46234 #define ZLL_CLR_SNF_CTRL(base, value) (BME_AND32(&ZLL_SNF_CTRL_REG(base), (uint32_t)(~(value))))
46235 #define ZLL_TOG_SNF_CTRL(base, value) (BME_XOR32(&ZLL_SNF_CTRL_REG(base), (uint32_t)(value)))
46236 /*@}*/
46237 
46238 /*
46239  * Constants & macros for individual ZLL_SNF_CTRL bitfields
46240  */
46241 
46242 /*!
46243  * @name Register ZLL_SNF_CTRL, field SNF_EN[0] (RW)
46244  *
46245  * SNIFF Mode Enable. Note: SNIFF Mode not currently supported. SNF_EN has no
46246  * effect
46247  */
46248 /*@{*/
46249 /*! @brief Read current value of the ZLL_SNF_CTRL_SNF_EN field. */
46250 #define ZLL_RD_SNF_CTRL_SNF_EN(base) ((ZLL_SNF_CTRL_REG(base) & ZLL_SNF_CTRL_SNF_EN_MASK) >> ZLL_SNF_CTRL_SNF_EN_SHIFT)
46251 #define ZLL_BRD_SNF_CTRL_SNF_EN(base) (BME_UBFX32(&ZLL_SNF_CTRL_REG(base), ZLL_SNF_CTRL_SNF_EN_SHIFT, ZLL_SNF_CTRL_SNF_EN_WIDTH))
46252 
46253 /*! @brief Set the SNF_EN field to a new value. */
46254 #define ZLL_WR_SNF_CTRL_SNF_EN(base, value) (ZLL_RMW_SNF_CTRL(base, ZLL_SNF_CTRL_SNF_EN_MASK, ZLL_SNF_CTRL_SNF_EN(value)))
46255 #define ZLL_BWR_SNF_CTRL_SNF_EN(base, value) (BME_BFI32(&ZLL_SNF_CTRL_REG(base), ((uint32_t)(value) << ZLL_SNF_CTRL_SNF_EN_SHIFT), ZLL_SNF_CTRL_SNF_EN_SHIFT, ZLL_SNF_CTRL_SNF_EN_WIDTH))
46256 /*@}*/
46257 
46258 /*******************************************************************************
46259  * ZLL_BSM_CTRL - BSM CONTROL
46260  ******************************************************************************/
46261 
46262 /*!
46263  * @brief ZLL_BSM_CTRL - BSM CONTROL (RW)
46264  *
46265  * Reset value: 0x00000000U
46266  *
46267  * Bit Streaming Mode Control Register
46268  */
46269 /*!
46270  * @name Constants and macros for entire ZLL_BSM_CTRL register
46271  */
46272 /*@{*/
46273 #define ZLL_RD_BSM_CTRL(base)    (ZLL_BSM_CTRL_REG(base))
46274 #define ZLL_WR_BSM_CTRL(base, value) (ZLL_BSM_CTRL_REG(base) = (value))
46275 #define ZLL_RMW_BSM_CTRL(base, mask, value) (ZLL_WR_BSM_CTRL(base, (ZLL_RD_BSM_CTRL(base) & ~(mask)) | (value)))
46276 #define ZLL_SET_BSM_CTRL(base, value) (BME_OR32(&ZLL_BSM_CTRL_REG(base), (uint32_t)(value)))
46277 #define ZLL_CLR_BSM_CTRL(base, value) (BME_AND32(&ZLL_BSM_CTRL_REG(base), (uint32_t)(~(value))))
46278 #define ZLL_TOG_BSM_CTRL(base, value) (BME_XOR32(&ZLL_BSM_CTRL_REG(base), (uint32_t)(value)))
46279 /*@}*/
46280 
46281 /*
46282  * Constants & macros for individual ZLL_BSM_CTRL bitfields
46283  */
46284 
46285 /*!
46286  * @name Register ZLL_BSM_CTRL, field BSM_EN[0] (RW)
46287  *
46288  * Values:
46289  * - 0b0 - Zigbee Bit Streaming Mode Disabled
46290  * - 0b1 - Zigbee Bit Streaming Mode Enabled
46291  */
46292 /*@{*/
46293 /*! @brief Read current value of the ZLL_BSM_CTRL_BSM_EN field. */
46294 #define ZLL_RD_BSM_CTRL_BSM_EN(base) ((ZLL_BSM_CTRL_REG(base) & ZLL_BSM_CTRL_BSM_EN_MASK) >> ZLL_BSM_CTRL_BSM_EN_SHIFT)
46295 #define ZLL_BRD_BSM_CTRL_BSM_EN(base) (BME_UBFX32(&ZLL_BSM_CTRL_REG(base), ZLL_BSM_CTRL_BSM_EN_SHIFT, ZLL_BSM_CTRL_BSM_EN_WIDTH))
46296 
46297 /*! @brief Set the BSM_EN field to a new value. */
46298 #define ZLL_WR_BSM_CTRL_BSM_EN(base, value) (ZLL_RMW_BSM_CTRL(base, ZLL_BSM_CTRL_BSM_EN_MASK, ZLL_BSM_CTRL_BSM_EN(value)))
46299 #define ZLL_BWR_BSM_CTRL_BSM_EN(base, value) (BME_BFI32(&ZLL_BSM_CTRL_REG(base), ((uint32_t)(value) << ZLL_BSM_CTRL_BSM_EN_SHIFT), ZLL_BSM_CTRL_BSM_EN_SHIFT, ZLL_BSM_CTRL_BSM_EN_WIDTH))
46300 /*@}*/
46301 
46302 /*******************************************************************************
46303  * ZLL_MACSHORTADDRS1 - MAC SHORT ADDRESS 1
46304  ******************************************************************************/
46305 
46306 /*!
46307  * @brief ZLL_MACSHORTADDRS1 - MAC SHORT ADDRESS 1 (RW)
46308  *
46309  * Reset value: 0xFFFFFFFFU
46310  */
46311 /*!
46312  * @name Constants and macros for entire ZLL_MACSHORTADDRS1 register
46313  */
46314 /*@{*/
46315 #define ZLL_RD_MACSHORTADDRS1(base) (ZLL_MACSHORTADDRS1_REG(base))
46316 #define ZLL_WR_MACSHORTADDRS1(base, value) (ZLL_MACSHORTADDRS1_REG(base) = (value))
46317 #define ZLL_RMW_MACSHORTADDRS1(base, mask, value) (ZLL_WR_MACSHORTADDRS1(base, (ZLL_RD_MACSHORTADDRS1(base) & ~(mask)) | (value)))
46318 #define ZLL_SET_MACSHORTADDRS1(base, value) (BME_OR32(&ZLL_MACSHORTADDRS1_REG(base), (uint32_t)(value)))
46319 #define ZLL_CLR_MACSHORTADDRS1(base, value) (BME_AND32(&ZLL_MACSHORTADDRS1_REG(base), (uint32_t)(~(value))))
46320 #define ZLL_TOG_MACSHORTADDRS1(base, value) (BME_XOR32(&ZLL_MACSHORTADDRS1_REG(base), (uint32_t)(value)))
46321 /*@}*/
46322 
46323 /*
46324  * Constants & macros for individual ZLL_MACSHORTADDRS1 bitfields
46325  */
46326 
46327 /*!
46328  * @name Register ZLL_MACSHORTADDRS1, field MACPANID1[15:0] (RW)
46329  *
46330  * MAC PAN ID for PAN1. The packet processor compares the incoming packet's
46331  * Destination PAN ID against the contents of this register to determine if the
46332  * packet is addressed to this device; or if the incoming packet is a Beacon frame,
46333  * the packet processor compares the incoming packet Source PAN ID against this
46334  * register. Also, if PANCORDNTR1=1, and the incoming packet has no Destination
46335  * Address field, and if the incoming packet is a Data or MAC Command frame, the
46336  * packet processor compares the incoming packet Source PAN ID against this register.
46337  */
46338 /*@{*/
46339 /*! @brief Read current value of the ZLL_MACSHORTADDRS1_MACPANID1 field. */
46340 #define ZLL_RD_MACSHORTADDRS1_MACPANID1(base) ((ZLL_MACSHORTADDRS1_REG(base) & ZLL_MACSHORTADDRS1_MACPANID1_MASK) >> ZLL_MACSHORTADDRS1_MACPANID1_SHIFT)
46341 #define ZLL_BRD_MACSHORTADDRS1_MACPANID1(base) (BME_UBFX32(&ZLL_MACSHORTADDRS1_REG(base), ZLL_MACSHORTADDRS1_MACPANID1_SHIFT, ZLL_MACSHORTADDRS1_MACPANID1_WIDTH))
46342 
46343 /*! @brief Set the MACPANID1 field to a new value. */
46344 #define ZLL_WR_MACSHORTADDRS1_MACPANID1(base, value) (ZLL_RMW_MACSHORTADDRS1(base, ZLL_MACSHORTADDRS1_MACPANID1_MASK, ZLL_MACSHORTADDRS1_MACPANID1(value)))
46345 #define ZLL_BWR_MACSHORTADDRS1_MACPANID1(base, value) (BME_BFI32(&ZLL_MACSHORTADDRS1_REG(base), ((uint32_t)(value) << ZLL_MACSHORTADDRS1_MACPANID1_SHIFT), ZLL_MACSHORTADDRS1_MACPANID1_SHIFT, ZLL_MACSHORTADDRS1_MACPANID1_WIDTH))
46346 /*@}*/
46347 
46348 /*!
46349  * @name Register ZLL_MACSHORTADDRS1, field MACSHORTADDRS1[31:16] (RW)
46350  *
46351  * MAC Short Address for PAN1, for 16-bit destination addressing mode. The
46352  * packet processor compares the incoming packet's Destination Address against the
46353  * contents of this register to determine if the packet is addressed to this device.
46354  */
46355 /*@{*/
46356 /*! @brief Read current value of the ZLL_MACSHORTADDRS1_MACSHORTADDRS1 field. */
46357 #define ZLL_RD_MACSHORTADDRS1_MACSHORTADDRS1(base) ((ZLL_MACSHORTADDRS1_REG(base) & ZLL_MACSHORTADDRS1_MACSHORTADDRS1_MASK) >> ZLL_MACSHORTADDRS1_MACSHORTADDRS1_SHIFT)
46358 #define ZLL_BRD_MACSHORTADDRS1_MACSHORTADDRS1(base) (BME_UBFX32(&ZLL_MACSHORTADDRS1_REG(base), ZLL_MACSHORTADDRS1_MACSHORTADDRS1_SHIFT, ZLL_MACSHORTADDRS1_MACSHORTADDRS1_WIDTH))
46359 
46360 /*! @brief Set the MACSHORTADDRS1 field to a new value. */
46361 #define ZLL_WR_MACSHORTADDRS1_MACSHORTADDRS1(base, value) (ZLL_RMW_MACSHORTADDRS1(base, ZLL_MACSHORTADDRS1_MACSHORTADDRS1_MASK, ZLL_MACSHORTADDRS1_MACSHORTADDRS1(value)))
46362 #define ZLL_BWR_MACSHORTADDRS1_MACSHORTADDRS1(base, value) (BME_BFI32(&ZLL_MACSHORTADDRS1_REG(base), ((uint32_t)(value) << ZLL_MACSHORTADDRS1_MACSHORTADDRS1_SHIFT), ZLL_MACSHORTADDRS1_MACSHORTADDRS1_SHIFT, ZLL_MACSHORTADDRS1_MACSHORTADDRS1_WIDTH))
46363 /*@}*/
46364 
46365 /*******************************************************************************
46366  * ZLL_MACLONGADDRS1_LSB - MAC LONG ADDRESS 1 LSB
46367  ******************************************************************************/
46368 
46369 /*!
46370  * @brief ZLL_MACLONGADDRS1_LSB - MAC LONG ADDRESS 1 LSB (RW)
46371  *
46372  * Reset value: 0xFFFFFFFFU
46373  *
46374  * MAC Long Address for PAN1, for 64-bit destination addressing mode. The packet
46375  * processor compares the incoming packet's Destination Address against the
46376  * contents of this register to determine if the packet is addressed to this device.
46377  */
46378 /*!
46379  * @name Constants and macros for entire ZLL_MACLONGADDRS1_LSB register
46380  */
46381 /*@{*/
46382 #define ZLL_RD_MACLONGADDRS1_LSB(base) (ZLL_MACLONGADDRS1_LSB_REG(base))
46383 #define ZLL_WR_MACLONGADDRS1_LSB(base, value) (ZLL_MACLONGADDRS1_LSB_REG(base) = (value))
46384 #define ZLL_RMW_MACLONGADDRS1_LSB(base, mask, value) (ZLL_WR_MACLONGADDRS1_LSB(base, (ZLL_RD_MACLONGADDRS1_LSB(base) & ~(mask)) | (value)))
46385 #define ZLL_SET_MACLONGADDRS1_LSB(base, value) (BME_OR32(&ZLL_MACLONGADDRS1_LSB_REG(base), (uint32_t)(value)))
46386 #define ZLL_CLR_MACLONGADDRS1_LSB(base, value) (BME_AND32(&ZLL_MACLONGADDRS1_LSB_REG(base), (uint32_t)(~(value))))
46387 #define ZLL_TOG_MACLONGADDRS1_LSB(base, value) (BME_XOR32(&ZLL_MACLONGADDRS1_LSB_REG(base), (uint32_t)(value)))
46388 /*@}*/
46389 
46390 /*******************************************************************************
46391  * ZLL_MACLONGADDRS1_MSB - MAC LONG ADDRESS 1 MSB
46392  ******************************************************************************/
46393 
46394 /*!
46395  * @brief ZLL_MACLONGADDRS1_MSB - MAC LONG ADDRESS 1 MSB (RW)
46396  *
46397  * Reset value: 0xFFFFFFFFU
46398  *
46399  * MAC Long Address for PAN1, for 64-bit destination addressing mode. The packet
46400  * processor compares the incoming packet's Destination Address against the
46401  * contents of this register to determine if the packet is addressed to this device.
46402  */
46403 /*!
46404  * @name Constants and macros for entire ZLL_MACLONGADDRS1_MSB register
46405  */
46406 /*@{*/
46407 #define ZLL_RD_MACLONGADDRS1_MSB(base) (ZLL_MACLONGADDRS1_MSB_REG(base))
46408 #define ZLL_WR_MACLONGADDRS1_MSB(base, value) (ZLL_MACLONGADDRS1_MSB_REG(base) = (value))
46409 #define ZLL_RMW_MACLONGADDRS1_MSB(base, mask, value) (ZLL_WR_MACLONGADDRS1_MSB(base, (ZLL_RD_MACLONGADDRS1_MSB(base) & ~(mask)) | (value)))
46410 #define ZLL_SET_MACLONGADDRS1_MSB(base, value) (BME_OR32(&ZLL_MACLONGADDRS1_MSB_REG(base), (uint32_t)(value)))
46411 #define ZLL_CLR_MACLONGADDRS1_MSB(base, value) (BME_AND32(&ZLL_MACLONGADDRS1_MSB_REG(base), (uint32_t)(~(value))))
46412 #define ZLL_TOG_MACLONGADDRS1_MSB(base, value) (BME_XOR32(&ZLL_MACLONGADDRS1_MSB_REG(base), (uint32_t)(value)))
46413 /*@}*/
46414 
46415 /*******************************************************************************
46416  * ZLL_DUAL_PAN_CTRL - DUAL PAN CONTROL
46417  ******************************************************************************/
46418 
46419 /*!
46420  * @brief ZLL_DUAL_PAN_CTRL - DUAL PAN CONTROL (RW)
46421  *
46422  * Reset value: 0x00000000U
46423  */
46424 /*!
46425  * @name Constants and macros for entire ZLL_DUAL_PAN_CTRL register
46426  */
46427 /*@{*/
46428 #define ZLL_RD_DUAL_PAN_CTRL(base) (ZLL_DUAL_PAN_CTRL_REG(base))
46429 #define ZLL_WR_DUAL_PAN_CTRL(base, value) (ZLL_DUAL_PAN_CTRL_REG(base) = (value))
46430 #define ZLL_RMW_DUAL_PAN_CTRL(base, mask, value) (ZLL_WR_DUAL_PAN_CTRL(base, (ZLL_RD_DUAL_PAN_CTRL(base) & ~(mask)) | (value)))
46431 #define ZLL_SET_DUAL_PAN_CTRL(base, value) (BME_OR32(&ZLL_DUAL_PAN_CTRL_REG(base), (uint32_t)(value)))
46432 #define ZLL_CLR_DUAL_PAN_CTRL(base, value) (BME_AND32(&ZLL_DUAL_PAN_CTRL_REG(base), (uint32_t)(~(value))))
46433 #define ZLL_TOG_DUAL_PAN_CTRL(base, value) (BME_XOR32(&ZLL_DUAL_PAN_CTRL_REG(base), (uint32_t)(value)))
46434 /*@}*/
46435 
46436 /*
46437  * Constants & macros for individual ZLL_DUAL_PAN_CTRL bitfields
46438  */
46439 
46440 /*!
46441  * @name Register ZLL_DUAL_PAN_CTRL, field ACTIVE_NETWORK[0] (RW)
46442  *
46443  * Selects the PAN on which to transceive, by activating a PAN parameter set
46444  * (PAN0 or PAN1). In Manual Dual PAN mode (or Single PAN mode), this bit selects
46445  * the active PAN parameter set (channel and addressing parameters) which governs
46446  * all autosequences. In Auto Dual PAN mode, this bit selects the PAN on which to
46447  * begin transceiving, latched at the point at which DUAL_PAN_DWELL register is
46448  * written.
46449  *
46450  * Values:
46451  * - 0b0 - Select PAN0
46452  * - 0b1 - Select PAN1
46453  */
46454 /*@{*/
46455 /*! @brief Read current value of the ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK field. */
46456 #define ZLL_RD_DUAL_PAN_CTRL_ACTIVE_NETWORK(base) ((ZLL_DUAL_PAN_CTRL_REG(base) & ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_MASK) >> ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_SHIFT)
46457 #define ZLL_BRD_DUAL_PAN_CTRL_ACTIVE_NETWORK(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_SHIFT, ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_WIDTH))
46458 
46459 /*! @brief Set the ACTIVE_NETWORK field to a new value. */
46460 #define ZLL_WR_DUAL_PAN_CTRL_ACTIVE_NETWORK(base, value) (ZLL_RMW_DUAL_PAN_CTRL(base, ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_MASK, ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK(value)))
46461 #define ZLL_BWR_DUAL_PAN_CTRL_ACTIVE_NETWORK(base, value) (BME_BFI32(&ZLL_DUAL_PAN_CTRL_REG(base), ((uint32_t)(value) << ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_SHIFT), ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_SHIFT, ZLL_DUAL_PAN_CTRL_ACTIVE_NETWORK_WIDTH))
46462 /*@}*/
46463 
46464 /*!
46465  * @name Register ZLL_DUAL_PAN_CTRL, field DUAL_PAN_AUTO[1] (RW)
46466  *
46467  * Activates automatic Dual PAN operating mode. In this mode, PAN-switching is
46468  * controlled by hardware at a pre-programmed rate, determined by DUAL_PAN_DWELL.
46469  * 0: Manual Dual PAN mode (or Single PAN mode). 1: Auto Dual PAN Mode Whenever
46470  * DUAL_PAN_AUTO=0, CURRENT_NETWORK=ACTIVE_NETWORK at all times. In other words,
46471  * software directly controls which PAN is selected. Whenever DUAL_PAN_AUTO=1,
46472  * CURRENT_NETWORK is controlled by hardware.
46473  */
46474 /*@{*/
46475 /*! @brief Read current value of the ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO field. */
46476 #define ZLL_RD_DUAL_PAN_CTRL_DUAL_PAN_AUTO(base) ((ZLL_DUAL_PAN_CTRL_REG(base) & ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_MASK) >> ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_SHIFT)
46477 #define ZLL_BRD_DUAL_PAN_CTRL_DUAL_PAN_AUTO(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_SHIFT, ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_WIDTH))
46478 
46479 /*! @brief Set the DUAL_PAN_AUTO field to a new value. */
46480 #define ZLL_WR_DUAL_PAN_CTRL_DUAL_PAN_AUTO(base, value) (ZLL_RMW_DUAL_PAN_CTRL(base, ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_MASK, ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO(value)))
46481 #define ZLL_BWR_DUAL_PAN_CTRL_DUAL_PAN_AUTO(base, value) (BME_BFI32(&ZLL_DUAL_PAN_CTRL_REG(base), ((uint32_t)(value) << ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_SHIFT), ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_SHIFT, ZLL_DUAL_PAN_CTRL_DUAL_PAN_AUTO_WIDTH))
46482 /*@}*/
46483 
46484 /*!
46485  * @name Register ZLL_DUAL_PAN_CTRL, field PANCORDNTR1[2] (RW)
46486  *
46487  * Device is a PAN Coordinator on PAN1. Allows device to receive packets with no
46488  * destination address, if Source PAN ID matches.
46489  */
46490 /*@{*/
46491 /*! @brief Read current value of the ZLL_DUAL_PAN_CTRL_PANCORDNTR1 field. */
46492 #define ZLL_RD_DUAL_PAN_CTRL_PANCORDNTR1(base) ((ZLL_DUAL_PAN_CTRL_REG(base) & ZLL_DUAL_PAN_CTRL_PANCORDNTR1_MASK) >> ZLL_DUAL_PAN_CTRL_PANCORDNTR1_SHIFT)
46493 #define ZLL_BRD_DUAL_PAN_CTRL_PANCORDNTR1(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DUAL_PAN_CTRL_PANCORDNTR1_SHIFT, ZLL_DUAL_PAN_CTRL_PANCORDNTR1_WIDTH))
46494 
46495 /*! @brief Set the PANCORDNTR1 field to a new value. */
46496 #define ZLL_WR_DUAL_PAN_CTRL_PANCORDNTR1(base, value) (ZLL_RMW_DUAL_PAN_CTRL(base, ZLL_DUAL_PAN_CTRL_PANCORDNTR1_MASK, ZLL_DUAL_PAN_CTRL_PANCORDNTR1(value)))
46497 #define ZLL_BWR_DUAL_PAN_CTRL_PANCORDNTR1(base, value) (BME_BFI32(&ZLL_DUAL_PAN_CTRL_REG(base), ((uint32_t)(value) << ZLL_DUAL_PAN_CTRL_PANCORDNTR1_SHIFT), ZLL_DUAL_PAN_CTRL_PANCORDNTR1_SHIFT, ZLL_DUAL_PAN_CTRL_PANCORDNTR1_WIDTH))
46498 /*@}*/
46499 
46500 /*!
46501  * @name Register ZLL_DUAL_PAN_CTRL, field CURRENT_NETWORK[3] (RO)
46502  *
46503  * This read-only bit indicates which PAN is currently selected by hardware in
46504  * automatic Dual PAN mode
46505  *
46506  * Values:
46507  * - 0b0 - PAN0 is selected
46508  * - 0b1 - PAN1 is selected
46509  */
46510 /*@{*/
46511 /*! @brief Read current value of the ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK field. */
46512 #define ZLL_RD_DUAL_PAN_CTRL_CURRENT_NETWORK(base) ((ZLL_DUAL_PAN_CTRL_REG(base) & ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_MASK) >> ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_SHIFT)
46513 #define ZLL_BRD_DUAL_PAN_CTRL_CURRENT_NETWORK(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_SHIFT, ZLL_DUAL_PAN_CTRL_CURRENT_NETWORK_WIDTH))
46514 /*@}*/
46515 
46516 /*!
46517  * @name Register ZLL_DUAL_PAN_CTRL, field ZB_DP_CHAN_OVRD_EN[4] (RW)
46518  *
46519  * In Dual PAN mode, in case there is a need to generate a frequency which may
46520  * be offset from the 16 prescribed 5MHz-spaced channels, to, for example, avoid
46521  * interference on one of the Dual PAN channels, a method has been provided to do
46522  * that on Apache, by designating one of the two PAN channels to use the Apache
46523  * transceiver's set of direct frequency-programming registers, instead of
46524  * CHANNEL_NUMx. Programming the direct frequency-programming registers -- integer,
46525  * numerator, and denominator, allows an RF frequency to be selected with much more
46526  * precision than the 5MHz granularity of the Zigbee mapped-channel registers,
46527  * CHANNEL_NUM0 and CHANNEL_NUM1. Two bits have been provided in Zigbee space to
46528  * realize this feature: ZB_DP_CHAN_OVRD_SEL and ZB_DP_CHAN_OVRD_EN. When
46529  * ZB_DP_CHAN_OVRD_EN=1, this enables one of the Dual PAN channels to use the direct
46530  * frequency programming. The ZB_DP_CHAN_OVRD_SEL bit determines which channel uses the
46531  * direct programming, according to the following table: ZB_DP_CHAN_OVRD_EN
46532  * ZB_DP_CHAN_OVRD_SEL PAN0 Frequency Determined by … PAN1 Frequency Determined by
46533  * … 0 X CHANNEL_NUM0[6:0] CHANNEL_NUM1[6:0] 1 0 DIRECT FREQUENCY PROGRAMMING
46534  * CHANNEL_NUM1[6:0] 1 1 CHANNEL_NUM0[6:0] DIRECT FREQUENCY PROGRAMMING Direct
46535  * Frequency Programming is accomplished by setting the PLL's Integer, Numerator,
46536  * and Denominator registers to the appropriate values for the desired RF frequency.
46537  */
46538 /*@{*/
46539 /*! @brief Read current value of the ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN field. */
46540 #define ZLL_RD_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN(base) ((ZLL_DUAL_PAN_CTRL_REG(base) & ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_MASK) >> ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_SHIFT)
46541 #define ZLL_BRD_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_SHIFT, ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_WIDTH))
46542 
46543 /*! @brief Set the ZB_DP_CHAN_OVRD_EN field to a new value. */
46544 #define ZLL_WR_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN(base, value) (ZLL_RMW_DUAL_PAN_CTRL(base, ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_MASK, ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN(value)))
46545 #define ZLL_BWR_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN(base, value) (BME_BFI32(&ZLL_DUAL_PAN_CTRL_REG(base), ((uint32_t)(value) << ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_SHIFT), ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_SHIFT, ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_EN_WIDTH))
46546 /*@}*/
46547 
46548 /*!
46549  * @name Register ZLL_DUAL_PAN_CTRL, field ZB_DP_CHAN_OVRD_SEL[5] (RW)
46550  *
46551  * This bit works with ZB_DP_CHAN_OVRD_EN to allow one of the two Dual PAN
46552  * channels to use Direct Frequency programming. See description for
46553  * ZB_DP_CHAN_OVRD_EN.
46554  */
46555 /*@{*/
46556 /*! @brief Read current value of the ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL field. */
46557 #define ZLL_RD_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL(base) ((ZLL_DUAL_PAN_CTRL_REG(base) & ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_MASK) >> ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_SHIFT)
46558 #define ZLL_BRD_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_SHIFT, ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_WIDTH))
46559 
46560 /*! @brief Set the ZB_DP_CHAN_OVRD_SEL field to a new value. */
46561 #define ZLL_WR_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL(base, value) (ZLL_RMW_DUAL_PAN_CTRL(base, ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_MASK, ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL(value)))
46562 #define ZLL_BWR_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL(base, value) (BME_BFI32(&ZLL_DUAL_PAN_CTRL_REG(base), ((uint32_t)(value) << ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_SHIFT), ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_SHIFT, ZLL_DUAL_PAN_CTRL_ZB_DP_CHAN_OVRD_SEL_WIDTH))
46563 /*@}*/
46564 
46565 /*!
46566  * @name Register ZLL_DUAL_PAN_CTRL, field DUAL_PAN_DWELL[15:8] (RW)
46567  *
46568  * Channel Frequency Dwell Time. In Auto Dual PAN mode, hardware will toggle the
46569  * PAN, after dwelling on the current PAN for the interval described below
46570  * (assuming Preamble/SFD not detected). A write to DUAL_PAN_DWELL, always
46571  * re-initilizes the DWELL TIMER to the programmed value. If a write to DUAL_PAN_DWELL
46572  * occurs during an autosequence, the DWELL TIMER will begin counting down
46573  * immediately. If a write to DUAL_PAN_DWELL occurs when there is no autosequence underway,
46574  * the DWELL TIMER will not begin counting until the next autosequence begins; it
46575  * will begin counting at the start of the sequence warmup. PRESCALER (bits
46576  * [1:0]) TIMEBASE (bits [7:2]) RANGE (min) - (max) 00 0.5ms 0.5 - 32ms 01 2.5ms 2.5
46577  * - 160ms 10 10ms 10 - 640ms 11 50ms 50ms - 3.2seconds A write to DUAL_PAN_DWELL
46578  * also causes the value of ACTIVE_NETWORK to get latched into the hardware.
46579  * This latched value will be the starting point for the automatic dual-pan mode
46580  * (i.e., start on PAN0 or on PAN1). The starting value takes effect immediately (if
46581  * sequence is underway and DUAL_PAN_AUTO=1), or is otherwise delayed until
46582  * sequence starts and DUAL_PAN_AUTO=1.
46583  */
46584 /*@{*/
46585 /*! @brief Read current value of the ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL field. */
46586 #define ZLL_RD_DUAL_PAN_CTRL_DUAL_PAN_DWELL(base) ((ZLL_DUAL_PAN_CTRL_REG(base) & ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_MASK) >> ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_SHIFT)
46587 #define ZLL_BRD_DUAL_PAN_CTRL_DUAL_PAN_DWELL(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_SHIFT, ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_WIDTH))
46588 
46589 /*! @brief Set the DUAL_PAN_DWELL field to a new value. */
46590 #define ZLL_WR_DUAL_PAN_CTRL_DUAL_PAN_DWELL(base, value) (ZLL_RMW_DUAL_PAN_CTRL(base, ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_MASK, ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL(value)))
46591 #define ZLL_BWR_DUAL_PAN_CTRL_DUAL_PAN_DWELL(base, value) (BME_BFI32(&ZLL_DUAL_PAN_CTRL_REG(base), ((uint32_t)(value) << ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_SHIFT), ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_SHIFT, ZLL_DUAL_PAN_CTRL_DUAL_PAN_DWELL_WIDTH))
46592 /*@}*/
46593 
46594 /*!
46595  * @name Register ZLL_DUAL_PAN_CTRL, field DUAL_PAN_REMAIN[21:16] (RO)
46596  *
46597  * This read-only register indicates time remaining before next PAN switch in
46598  * auto Dual PAN mode. The units for this register, depend on the PRESCALER setting
46599  * (bits [1:0]) in the DUAL_PAN_DWELL register, according to the following
46600  * table: DUAL_PAN_DWELL PRESCALER DUAL_PAN_REMAIN UNITS 00 0.5ms 01 2.5ms 10 10ms 11
46601  * 50ms The readback value indicates that between N-1 and N timebase units remain
46602  * until the next PAN switch. For example, a DUAL_PAN_REMAIN readback value of
46603  * 3, with a DUAL_PAN_DWELL PRESCALER setting of 2 (10ms), indicates that between
46604  * 20ms (2*10ms) and 30ms (3*10ms), remain until the next automatic PAN switch.
46605  */
46606 /*@{*/
46607 /*! @brief Read current value of the ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN field. */
46608 #define ZLL_RD_DUAL_PAN_CTRL_DUAL_PAN_REMAIN(base) ((ZLL_DUAL_PAN_CTRL_REG(base) & ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_MASK) >> ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_SHIFT)
46609 #define ZLL_BRD_DUAL_PAN_CTRL_DUAL_PAN_REMAIN(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_SHIFT, ZLL_DUAL_PAN_CTRL_DUAL_PAN_REMAIN_WIDTH))
46610 /*@}*/
46611 
46612 /*!
46613  * @name Register ZLL_DUAL_PAN_CTRL, field RECD_ON_PAN0[22] (RO)
46614  *
46615  * Indicates the packet which was just received, was received on PAN0. In Dual
46616  * PAN mode operating on 2 different channels, RECD_ON_PAN0 will be set if
46617  * CURRENT_NETWORK=0 when the packet was received, regardless of FILTERFAIL status. In
46618  * DUAL PAN mode operating with same channel on both networks, CURRENT_NETWORK
46619  * will be ignored and RECD_ON_PAN0 will be set only if a valid packet was received
46620  * on PAN0 (PAN0's FILTERFAIL_FLAG is deasserted). RECD_ON_PAN0 remains valid
46621  * until the start of the next autoseqeuence.
46622  */
46623 /*@{*/
46624 /*! @brief Read current value of the ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0 field. */
46625 #define ZLL_RD_DUAL_PAN_CTRL_RECD_ON_PAN0(base) ((ZLL_DUAL_PAN_CTRL_REG(base) & ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_MASK) >> ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_SHIFT)
46626 #define ZLL_BRD_DUAL_PAN_CTRL_RECD_ON_PAN0(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_SHIFT, ZLL_DUAL_PAN_CTRL_RECD_ON_PAN0_WIDTH))
46627 /*@}*/
46628 
46629 /*!
46630  * @name Register ZLL_DUAL_PAN_CTRL, field RECD_ON_PAN1[23] (RO)
46631  *
46632  * Indicates the packet which was just received, was received on PAN1. In Dual
46633  * PAN mode operating on 2 different channels, RECD_ON_PAN1 will be set if
46634  * CURRENT_NETWORK=1 when the packet was received, regardless of FILTERFAIL status. In
46635  * DUAL PAN mode operating with same channel on both networks, CURRENT_NETWORK
46636  * will be ignored and RECD_ON_PAN1 will be set only if a valid packet was received
46637  * on PAN1 (PAN1's FILTERFAIL_FLAG is deasserted). RECD_ON_PAN1 remains valid
46638  * until the start of the next autoseqeuence.
46639  */
46640 /*@{*/
46641 /*! @brief Read current value of the ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1 field. */
46642 #define ZLL_RD_DUAL_PAN_CTRL_RECD_ON_PAN1(base) ((ZLL_DUAL_PAN_CTRL_REG(base) & ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_MASK) >> ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_SHIFT)
46643 #define ZLL_BRD_DUAL_PAN_CTRL_RECD_ON_PAN1(base) (BME_UBFX32(&ZLL_DUAL_PAN_CTRL_REG(base), ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_SHIFT, ZLL_DUAL_PAN_CTRL_RECD_ON_PAN1_WIDTH))
46644 /*@}*/
46645 
46646 /*******************************************************************************
46647  * ZLL_CHANNEL_NUM1 - CHANNEL NUMBER 1
46648  ******************************************************************************/
46649 
46650 /*!
46651  * @brief ZLL_CHANNEL_NUM1 - CHANNEL NUMBER 1 (RW)
46652  *
46653  * Reset value: 0x0000007FU
46654  *
46655  * This is the mapped channel number used to transmit and receive Zigbee
46656  * packets. This register applies to PAN1 only. CHANNEL_NUM1 should be in the range: 11
46657  * <= CHANNEL_NUM1 <= 26 Note: This register should not be programmed, and left
46658  * in its default state, if Dual PAN mode is not in use.
46659  */
46660 /*!
46661  * @name Constants and macros for entire ZLL_CHANNEL_NUM1 register
46662  */
46663 /*@{*/
46664 #define ZLL_RD_CHANNEL_NUM1(base) (ZLL_CHANNEL_NUM1_REG(base))
46665 #define ZLL_WR_CHANNEL_NUM1(base, value) (ZLL_CHANNEL_NUM1_REG(base) = (value))
46666 #define ZLL_RMW_CHANNEL_NUM1(base, mask, value) (ZLL_WR_CHANNEL_NUM1(base, (ZLL_RD_CHANNEL_NUM1(base) & ~(mask)) | (value)))
46667 #define ZLL_SET_CHANNEL_NUM1(base, value) (BME_OR32(&ZLL_CHANNEL_NUM1_REG(base), (uint32_t)(value)))
46668 #define ZLL_CLR_CHANNEL_NUM1(base, value) (BME_AND32(&ZLL_CHANNEL_NUM1_REG(base), (uint32_t)(~(value))))
46669 #define ZLL_TOG_CHANNEL_NUM1(base, value) (BME_XOR32(&ZLL_CHANNEL_NUM1_REG(base), (uint32_t)(value)))
46670 /*@}*/
46671 
46672 /*
46673  * Constants & macros for individual ZLL_CHANNEL_NUM1 bitfields
46674  */
46675 
46676 /*!
46677  * @name Register ZLL_CHANNEL_NUM1, field CHANNEL_NUM1[6:0] (RW)
46678  */
46679 /*@{*/
46680 /*! @brief Read current value of the ZLL_CHANNEL_NUM1_CHANNEL_NUM1 field. */
46681 #define ZLL_RD_CHANNEL_NUM1_CHANNEL_NUM1(base) ((ZLL_CHANNEL_NUM1_REG(base) & ZLL_CHANNEL_NUM1_CHANNEL_NUM1_MASK) >> ZLL_CHANNEL_NUM1_CHANNEL_NUM1_SHIFT)
46682 #define ZLL_BRD_CHANNEL_NUM1_CHANNEL_NUM1(base) (BME_UBFX32(&ZLL_CHANNEL_NUM1_REG(base), ZLL_CHANNEL_NUM1_CHANNEL_NUM1_SHIFT, ZLL_CHANNEL_NUM1_CHANNEL_NUM1_WIDTH))
46683 
46684 /*! @brief Set the CHANNEL_NUM1 field to a new value. */
46685 #define ZLL_WR_CHANNEL_NUM1_CHANNEL_NUM1(base, value) (ZLL_RMW_CHANNEL_NUM1(base, ZLL_CHANNEL_NUM1_CHANNEL_NUM1_MASK, ZLL_CHANNEL_NUM1_CHANNEL_NUM1(value)))
46686 #define ZLL_BWR_CHANNEL_NUM1_CHANNEL_NUM1(base, value) (BME_BFI32(&ZLL_CHANNEL_NUM1_REG(base), ((uint32_t)(value) << ZLL_CHANNEL_NUM1_CHANNEL_NUM1_SHIFT), ZLL_CHANNEL_NUM1_CHANNEL_NUM1_SHIFT, ZLL_CHANNEL_NUM1_CHANNEL_NUM1_WIDTH))
46687 /*@}*/
46688 
46689 /*******************************************************************************
46690  * ZLL_SAM_CTRL - SAM CONTROL
46691  ******************************************************************************/
46692 
46693 /*!
46694  * @brief ZLL_SAM_CTRL - SAM CONTROL (RW)
46695  *
46696  * Reset value: 0x80804000U
46697  *
46698  * Source Address Management Control Register
46699  */
46700 /*!
46701  * @name Constants and macros for entire ZLL_SAM_CTRL register
46702  */
46703 /*@{*/
46704 #define ZLL_RD_SAM_CTRL(base)    (ZLL_SAM_CTRL_REG(base))
46705 #define ZLL_WR_SAM_CTRL(base, value) (ZLL_SAM_CTRL_REG(base) = (value))
46706 #define ZLL_RMW_SAM_CTRL(base, mask, value) (ZLL_WR_SAM_CTRL(base, (ZLL_RD_SAM_CTRL(base) & ~(mask)) | (value)))
46707 #define ZLL_SET_SAM_CTRL(base, value) (BME_OR32(&ZLL_SAM_CTRL_REG(base), (uint32_t)(value)))
46708 #define ZLL_CLR_SAM_CTRL(base, value) (BME_AND32(&ZLL_SAM_CTRL_REG(base), (uint32_t)(~(value))))
46709 #define ZLL_TOG_SAM_CTRL(base, value) (BME_XOR32(&ZLL_SAM_CTRL_REG(base), (uint32_t)(value)))
46710 /*@}*/
46711 
46712 /*
46713  * Constants & macros for individual ZLL_SAM_CTRL bitfields
46714  */
46715 
46716 /*!
46717  * @name Register ZLL_SAM_CTRL, field SAP0_EN[0] (RW)
46718  *
46719  * Values:
46720  * - 0b0 - Disables SAP0 Partition
46721  * - 0b1 - Enables SAP0 Partition
46722  */
46723 /*@{*/
46724 /*! @brief Read current value of the ZLL_SAM_CTRL_SAP0_EN field. */
46725 #define ZLL_RD_SAM_CTRL_SAP0_EN(base) ((ZLL_SAM_CTRL_REG(base) & ZLL_SAM_CTRL_SAP0_EN_MASK) >> ZLL_SAM_CTRL_SAP0_EN_SHIFT)
46726 #define ZLL_BRD_SAM_CTRL_SAP0_EN(base) (BME_UBFX32(&ZLL_SAM_CTRL_REG(base), ZLL_SAM_CTRL_SAP0_EN_SHIFT, ZLL_SAM_CTRL_SAP0_EN_WIDTH))
46727 
46728 /*! @brief Set the SAP0_EN field to a new value. */
46729 #define ZLL_WR_SAM_CTRL_SAP0_EN(base, value) (ZLL_RMW_SAM_CTRL(base, ZLL_SAM_CTRL_SAP0_EN_MASK, ZLL_SAM_CTRL_SAP0_EN(value)))
46730 #define ZLL_BWR_SAM_CTRL_SAP0_EN(base, value) (BME_BFI32(&ZLL_SAM_CTRL_REG(base), ((uint32_t)(value) << ZLL_SAM_CTRL_SAP0_EN_SHIFT), ZLL_SAM_CTRL_SAP0_EN_SHIFT, ZLL_SAM_CTRL_SAP0_EN_WIDTH))
46731 /*@}*/
46732 
46733 /*!
46734  * @name Register ZLL_SAM_CTRL, field SAA0_EN[1] (RW)
46735  *
46736  * Values:
46737  * - 0b0 - Disables SAA0 Partition
46738  * - 0b1 - Enables SAA0 Partition
46739  */
46740 /*@{*/
46741 /*! @brief Read current value of the ZLL_SAM_CTRL_SAA0_EN field. */
46742 #define ZLL_RD_SAM_CTRL_SAA0_EN(base) ((ZLL_SAM_CTRL_REG(base) & ZLL_SAM_CTRL_SAA0_EN_MASK) >> ZLL_SAM_CTRL_SAA0_EN_SHIFT)
46743 #define ZLL_BRD_SAM_CTRL_SAA0_EN(base) (BME_UBFX32(&ZLL_SAM_CTRL_REG(base), ZLL_SAM_CTRL_SAA0_EN_SHIFT, ZLL_SAM_CTRL_SAA0_EN_WIDTH))
46744 
46745 /*! @brief Set the SAA0_EN field to a new value. */
46746 #define ZLL_WR_SAM_CTRL_SAA0_EN(base, value) (ZLL_RMW_SAM_CTRL(base, ZLL_SAM_CTRL_SAA0_EN_MASK, ZLL_SAM_CTRL_SAA0_EN(value)))
46747 #define ZLL_BWR_SAM_CTRL_SAA0_EN(base, value) (BME_BFI32(&ZLL_SAM_CTRL_REG(base), ((uint32_t)(value) << ZLL_SAM_CTRL_SAA0_EN_SHIFT), ZLL_SAM_CTRL_SAA0_EN_SHIFT, ZLL_SAM_CTRL_SAA0_EN_WIDTH))
46748 /*@}*/
46749 
46750 /*!
46751  * @name Register ZLL_SAM_CTRL, field SAP1_EN[2] (RW)
46752  *
46753  * Values:
46754  * - 0b0 - Disables SAP1 Partition
46755  * - 0b1 - Enables SAP1 Partition
46756  */
46757 /*@{*/
46758 /*! @brief Read current value of the ZLL_SAM_CTRL_SAP1_EN field. */
46759 #define ZLL_RD_SAM_CTRL_SAP1_EN(base) ((ZLL_SAM_CTRL_REG(base) & ZLL_SAM_CTRL_SAP1_EN_MASK) >> ZLL_SAM_CTRL_SAP1_EN_SHIFT)
46760 #define ZLL_BRD_SAM_CTRL_SAP1_EN(base) (BME_UBFX32(&ZLL_SAM_CTRL_REG(base), ZLL_SAM_CTRL_SAP1_EN_SHIFT, ZLL_SAM_CTRL_SAP1_EN_WIDTH))
46761 
46762 /*! @brief Set the SAP1_EN field to a new value. */
46763 #define ZLL_WR_SAM_CTRL_SAP1_EN(base, value) (ZLL_RMW_SAM_CTRL(base, ZLL_SAM_CTRL_SAP1_EN_MASK, ZLL_SAM_CTRL_SAP1_EN(value)))
46764 #define ZLL_BWR_SAM_CTRL_SAP1_EN(base, value) (BME_BFI32(&ZLL_SAM_CTRL_REG(base), ((uint32_t)(value) << ZLL_SAM_CTRL_SAP1_EN_SHIFT), ZLL_SAM_CTRL_SAP1_EN_SHIFT, ZLL_SAM_CTRL_SAP1_EN_WIDTH))
46765 /*@}*/
46766 
46767 /*!
46768  * @name Register ZLL_SAM_CTRL, field SAA1_EN[3] (RW)
46769  *
46770  * Values:
46771  * - 0b0 - Disables SAA1 Partition
46772  * - 0b1 - Enables SAA1 Partition
46773  */
46774 /*@{*/
46775 /*! @brief Read current value of the ZLL_SAM_CTRL_SAA1_EN field. */
46776 #define ZLL_RD_SAM_CTRL_SAA1_EN(base) ((ZLL_SAM_CTRL_REG(base) & ZLL_SAM_CTRL_SAA1_EN_MASK) >> ZLL_SAM_CTRL_SAA1_EN_SHIFT)
46777 #define ZLL_BRD_SAM_CTRL_SAA1_EN(base) (BME_UBFX32(&ZLL_SAM_CTRL_REG(base), ZLL_SAM_CTRL_SAA1_EN_SHIFT, ZLL_SAM_CTRL_SAA1_EN_WIDTH))
46778 
46779 /*! @brief Set the SAA1_EN field to a new value. */
46780 #define ZLL_WR_SAM_CTRL_SAA1_EN(base, value) (ZLL_RMW_SAM_CTRL(base, ZLL_SAM_CTRL_SAA1_EN_MASK, ZLL_SAM_CTRL_SAA1_EN(value)))
46781 #define ZLL_BWR_SAM_CTRL_SAA1_EN(base, value) (BME_BFI32(&ZLL_SAM_CTRL_REG(base), ((uint32_t)(value) << ZLL_SAM_CTRL_SAA1_EN_SHIFT), ZLL_SAM_CTRL_SAA1_EN_SHIFT, ZLL_SAM_CTRL_SAA1_EN_WIDTH))
46782 /*@}*/
46783 
46784 /*!
46785  * @name Register ZLL_SAM_CTRL, field SAA0_START[15:8] (RW)
46786  */
46787 /*@{*/
46788 /*! @brief Read current value of the ZLL_SAM_CTRL_SAA0_START field. */
46789 #define ZLL_RD_SAM_CTRL_SAA0_START(base) ((ZLL_SAM_CTRL_REG(base) & ZLL_SAM_CTRL_SAA0_START_MASK) >> ZLL_SAM_CTRL_SAA0_START_SHIFT)
46790 #define ZLL_BRD_SAM_CTRL_SAA0_START(base) (BME_UBFX32(&ZLL_SAM_CTRL_REG(base), ZLL_SAM_CTRL_SAA0_START_SHIFT, ZLL_SAM_CTRL_SAA0_START_WIDTH))
46791 
46792 /*! @brief Set the SAA0_START field to a new value. */
46793 #define ZLL_WR_SAM_CTRL_SAA0_START(base, value) (ZLL_RMW_SAM_CTRL(base, ZLL_SAM_CTRL_SAA0_START_MASK, ZLL_SAM_CTRL_SAA0_START(value)))
46794 #define ZLL_BWR_SAM_CTRL_SAA0_START(base, value) (BME_BFI32(&ZLL_SAM_CTRL_REG(base), ((uint32_t)(value) << ZLL_SAM_CTRL_SAA0_START_SHIFT), ZLL_SAM_CTRL_SAA0_START_SHIFT, ZLL_SAM_CTRL_SAA0_START_WIDTH))
46795 /*@}*/
46796 
46797 /*!
46798  * @name Register ZLL_SAM_CTRL, field SAP1_START[23:16] (RW)
46799  */
46800 /*@{*/
46801 /*! @brief Read current value of the ZLL_SAM_CTRL_SAP1_START field. */
46802 #define ZLL_RD_SAM_CTRL_SAP1_START(base) ((ZLL_SAM_CTRL_REG(base) & ZLL_SAM_CTRL_SAP1_START_MASK) >> ZLL_SAM_CTRL_SAP1_START_SHIFT)
46803 #define ZLL_BRD_SAM_CTRL_SAP1_START(base) (BME_UBFX32(&ZLL_SAM_CTRL_REG(base), ZLL_SAM_CTRL_SAP1_START_SHIFT, ZLL_SAM_CTRL_SAP1_START_WIDTH))
46804 
46805 /*! @brief Set the SAP1_START field to a new value. */
46806 #define ZLL_WR_SAM_CTRL_SAP1_START(base, value) (ZLL_RMW_SAM_CTRL(base, ZLL_SAM_CTRL_SAP1_START_MASK, ZLL_SAM_CTRL_SAP1_START(value)))
46807 #define ZLL_BWR_SAM_CTRL_SAP1_START(base, value) (BME_BFI32(&ZLL_SAM_CTRL_REG(base), ((uint32_t)(value) << ZLL_SAM_CTRL_SAP1_START_SHIFT), ZLL_SAM_CTRL_SAP1_START_SHIFT, ZLL_SAM_CTRL_SAP1_START_WIDTH))
46808 /*@}*/
46809 
46810 /*!
46811  * @name Register ZLL_SAM_CTRL, field SAA1_START[31:24] (RW)
46812  */
46813 /*@{*/
46814 /*! @brief Read current value of the ZLL_SAM_CTRL_SAA1_START field. */
46815 #define ZLL_RD_SAM_CTRL_SAA1_START(base) ((ZLL_SAM_CTRL_REG(base) & ZLL_SAM_CTRL_SAA1_START_MASK) >> ZLL_SAM_CTRL_SAA1_START_SHIFT)
46816 #define ZLL_BRD_SAM_CTRL_SAA1_START(base) (BME_UBFX32(&ZLL_SAM_CTRL_REG(base), ZLL_SAM_CTRL_SAA1_START_SHIFT, ZLL_SAM_CTRL_SAA1_START_WIDTH))
46817 
46818 /*! @brief Set the SAA1_START field to a new value. */
46819 #define ZLL_WR_SAM_CTRL_SAA1_START(base, value) (ZLL_RMW_SAM_CTRL(base, ZLL_SAM_CTRL_SAA1_START_MASK, ZLL_SAM_CTRL_SAA1_START(value)))
46820 #define ZLL_BWR_SAM_CTRL_SAA1_START(base, value) (BME_BFI32(&ZLL_SAM_CTRL_REG(base), ((uint32_t)(value) << ZLL_SAM_CTRL_SAA1_START_SHIFT), ZLL_SAM_CTRL_SAA1_START_SHIFT, ZLL_SAM_CTRL_SAA1_START_WIDTH))
46821 /*@}*/
46822 
46823 /*******************************************************************************
46824  * ZLL_SAM_TABLE - SOURCE ADDRESS MANAGEMENT TABLE
46825  ******************************************************************************/
46826 
46827 /*!
46828  * @brief ZLL_SAM_TABLE - SOURCE ADDRESS MANAGEMENT TABLE (RW)
46829  *
46830  * Reset value: 0x00000000U
46831  *
46832  * Source Address Management Table
46833  */
46834 /*!
46835  * @name Constants and macros for entire ZLL_SAM_TABLE register
46836  */
46837 /*@{*/
46838 #define ZLL_RD_SAM_TABLE(base)   (ZLL_SAM_TABLE_REG(base))
46839 #define ZLL_WR_SAM_TABLE(base, value) (ZLL_SAM_TABLE_REG(base) = (value))
46840 #define ZLL_RMW_SAM_TABLE(base, mask, value) (ZLL_WR_SAM_TABLE(base, (ZLL_RD_SAM_TABLE(base) & ~(mask)) | (value)))
46841 #define ZLL_SET_SAM_TABLE(base, value) (BME_OR32(&ZLL_SAM_TABLE_REG(base), (uint32_t)(value)))
46842 #define ZLL_CLR_SAM_TABLE(base, value) (BME_AND32(&ZLL_SAM_TABLE_REG(base), (uint32_t)(~(value))))
46843 #define ZLL_TOG_SAM_TABLE(base, value) (BME_XOR32(&ZLL_SAM_TABLE_REG(base), (uint32_t)(value)))
46844 /*@}*/
46845 
46846 /*
46847  * Constants & macros for individual ZLL_SAM_TABLE bitfields
46848  */
46849 
46850 /*!
46851  * @name Register ZLL_SAM_TABLE, field SAM_INDEX[6:0] (RW)
46852  *
46853  * Contains the table index to be enabled or invalidated. Software must ensure
46854  * that the index is within the range of the desired partition.
46855  */
46856 /*@{*/
46857 /*! @brief Read current value of the ZLL_SAM_TABLE_SAM_INDEX field. */
46858 #define ZLL_RD_SAM_TABLE_SAM_INDEX(base) ((ZLL_SAM_TABLE_REG(base) & ZLL_SAM_TABLE_SAM_INDEX_MASK) >> ZLL_SAM_TABLE_SAM_INDEX_SHIFT)
46859 #define ZLL_BRD_SAM_TABLE_SAM_INDEX(base) (BME_UBFX32(&ZLL_SAM_TABLE_REG(base), ZLL_SAM_TABLE_SAM_INDEX_SHIFT, ZLL_SAM_TABLE_SAM_INDEX_WIDTH))
46860 
46861 /*! @brief Set the SAM_INDEX field to a new value. */
46862 #define ZLL_WR_SAM_TABLE_SAM_INDEX(base, value) (ZLL_RMW_SAM_TABLE(base, ZLL_SAM_TABLE_SAM_INDEX_MASK, ZLL_SAM_TABLE_SAM_INDEX(value)))
46863 #define ZLL_BWR_SAM_TABLE_SAM_INDEX(base, value) (BME_BFI32(&ZLL_SAM_TABLE_REG(base), ((uint32_t)(value) << ZLL_SAM_TABLE_SAM_INDEX_SHIFT), ZLL_SAM_TABLE_SAM_INDEX_SHIFT, ZLL_SAM_TABLE_SAM_INDEX_WIDTH))
46864 /*@}*/
46865 
46866 /*!
46867  * @name Register ZLL_SAM_TABLE, field SAM_INDEX_WR[7] (WO)
46868  *
46869  * For 32-bit writes, SAM_INDEX_WR must be set to indicate that the table entry
46870  * specified by SAM_INDEX[6:0] is to be written; if SAM_INDEX_WR=0, the table
46871  * entry is not written, but the SAM_INDEX[6:0] register is updated. For 8-bit
46872  * writes, this bit is ignored.
46873  */
46874 /*@{*/
46875 /*! @brief Set the SAM_INDEX_WR field to a new value. */
46876 #define ZLL_WR_SAM_TABLE_SAM_INDEX_WR(base, value) (ZLL_RMW_SAM_TABLE(base, ZLL_SAM_TABLE_SAM_INDEX_WR_MASK, ZLL_SAM_TABLE_SAM_INDEX_WR(value)))
46877 #define ZLL_BWR_SAM_TABLE_SAM_INDEX_WR(base, value) (ZLL_WR_SAM_TABLE_SAM_INDEX_WR(base, value))
46878 /*@}*/
46879 
46880 /*!
46881  * @name Register ZLL_SAM_TABLE, field SAM_CHECKSUM[23:8] (RW)
46882  *
46883  * Software-computed source address checksum, to be installed into a table
46884  * index. The value on SAM_CHECKSUM[15:0] can be installed into the table with a
46885  * single, atomic 32-bit write; in that case, the write data would contain the desired
46886  * SAM_INDEX[6:0] and SAM_CHECKSUM[15:0], and SAM_INDEX_WR=1.If SAM_INDEX_WR=0,
46887  * then the SAM_INDEX[6:0] register is written, but the checksum is not written
46888  * to the table.The readback value of SAM_CHECKSUM[15:0] is the contents of the
46889  * SAM Table at the location pointed to by SAM_INDEX[6:0]. To readback from a
46890  * specific table index, software should first write the desired index to
46891  * SAM_INDEX[6:0], and then read back the checksum from the table on SAM_CHECKSUM[15:0].
46892  */
46893 /*@{*/
46894 /*! @brief Read current value of the ZLL_SAM_TABLE_SAM_CHECKSUM field. */
46895 #define ZLL_RD_SAM_TABLE_SAM_CHECKSUM(base) ((ZLL_SAM_TABLE_REG(base) & ZLL_SAM_TABLE_SAM_CHECKSUM_MASK) >> ZLL_SAM_TABLE_SAM_CHECKSUM_SHIFT)
46896 #define ZLL_BRD_SAM_TABLE_SAM_CHECKSUM(base) (BME_UBFX32(&ZLL_SAM_TABLE_REG(base), ZLL_SAM_TABLE_SAM_CHECKSUM_SHIFT, ZLL_SAM_TABLE_SAM_CHECKSUM_WIDTH))
46897 
46898 /*! @brief Set the SAM_CHECKSUM field to a new value. */
46899 #define ZLL_WR_SAM_TABLE_SAM_CHECKSUM(base, value) (ZLL_RMW_SAM_TABLE(base, ZLL_SAM_TABLE_SAM_CHECKSUM_MASK, ZLL_SAM_TABLE_SAM_CHECKSUM(value)))
46900 #define ZLL_BWR_SAM_TABLE_SAM_CHECKSUM(base, value) (BME_BFI32(&ZLL_SAM_TABLE_REG(base), ((uint32_t)(value) << ZLL_SAM_TABLE_SAM_CHECKSUM_SHIFT), ZLL_SAM_TABLE_SAM_CHECKSUM_SHIFT, ZLL_SAM_TABLE_SAM_CHECKSUM_WIDTH))
46901 /*@}*/
46902 
46903 /*!
46904  * @name Register ZLL_SAM_TABLE, field SAM_INDEX_INV[24] (WO)
46905  */
46906 /*@{*/
46907 /*! @brief Set the SAM_INDEX_INV field to a new value. */
46908 #define ZLL_WR_SAM_TABLE_SAM_INDEX_INV(base, value) (ZLL_RMW_SAM_TABLE(base, ZLL_SAM_TABLE_SAM_INDEX_INV_MASK, ZLL_SAM_TABLE_SAM_INDEX_INV(value)))
46909 #define ZLL_BWR_SAM_TABLE_SAM_INDEX_INV(base, value) (ZLL_WR_SAM_TABLE_SAM_INDEX_INV(base, value))
46910 /*@}*/
46911 
46912 /*!
46913  * @name Register ZLL_SAM_TABLE, field SAM_INDEX_EN[25] (WO)
46914  */
46915 /*@{*/
46916 /*! @brief Set the SAM_INDEX_EN field to a new value. */
46917 #define ZLL_WR_SAM_TABLE_SAM_INDEX_EN(base, value) (ZLL_RMW_SAM_TABLE(base, ZLL_SAM_TABLE_SAM_INDEX_EN_MASK, ZLL_SAM_TABLE_SAM_INDEX_EN(value)))
46918 #define ZLL_BWR_SAM_TABLE_SAM_INDEX_EN(base, value) (ZLL_WR_SAM_TABLE_SAM_INDEX_EN(base, value))
46919 /*@}*/
46920 
46921 /*!
46922  * @name Register ZLL_SAM_TABLE, field ACK_FRM_PND[26] (RW)
46923  *
46924  * Software can take manual control of the FramePending field of the Frame
46925  * Control Field of the next automatic TX acknowledge packet, by setting
46926  * ACK_FRM_PND_CTRL=1; in that case FramePending will track the state of this bit. The
46927  * FramePending field also tracks this bit if Source Address Management is comletely
46928  * disabled, i.e., SAP0_EN=SAA0_EN=SAP1_EN=SAA1_EN=0 Otherwise, the FramePending
46929  * field is determined by Source Address Management (SAM) hardware.
46930  */
46931 /*@{*/
46932 /*! @brief Read current value of the ZLL_SAM_TABLE_ACK_FRM_PND field. */
46933 #define ZLL_RD_SAM_TABLE_ACK_FRM_PND(base) ((ZLL_SAM_TABLE_REG(base) & ZLL_SAM_TABLE_ACK_FRM_PND_MASK) >> ZLL_SAM_TABLE_ACK_FRM_PND_SHIFT)
46934 #define ZLL_BRD_SAM_TABLE_ACK_FRM_PND(base) (BME_UBFX32(&ZLL_SAM_TABLE_REG(base), ZLL_SAM_TABLE_ACK_FRM_PND_SHIFT, ZLL_SAM_TABLE_ACK_FRM_PND_WIDTH))
46935 
46936 /*! @brief Set the ACK_FRM_PND field to a new value. */
46937 #define ZLL_WR_SAM_TABLE_ACK_FRM_PND(base, value) (ZLL_RMW_SAM_TABLE(base, ZLL_SAM_TABLE_ACK_FRM_PND_MASK, ZLL_SAM_TABLE_ACK_FRM_PND(value)))
46938 #define ZLL_BWR_SAM_TABLE_ACK_FRM_PND(base, value) (BME_BFI32(&ZLL_SAM_TABLE_REG(base), ((uint32_t)(value) << ZLL_SAM_TABLE_ACK_FRM_PND_SHIFT), ZLL_SAM_TABLE_ACK_FRM_PND_SHIFT, ZLL_SAM_TABLE_ACK_FRM_PND_WIDTH))
46939 /*@}*/
46940 
46941 /*!
46942  * @name Register ZLL_SAM_TABLE, field ACK_FRM_PND_CTRL[27] (RW)
46943  *
46944  * Values:
46945  * - 0b0 - the FramePending field of the Frame Control Field of the next
46946  *     automatic TX acknowledge packet is determined by hardware
46947  * - 0b1 - the FramePending field of the Frame Control Field of the next
46948  *     automatic TX acknowledge packet tracks ACK_FRM_PEND
46949  */
46950 /*@{*/
46951 /*! @brief Read current value of the ZLL_SAM_TABLE_ACK_FRM_PND_CTRL field. */
46952 #define ZLL_RD_SAM_TABLE_ACK_FRM_PND_CTRL(base) ((ZLL_SAM_TABLE_REG(base) & ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_MASK) >> ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_SHIFT)
46953 #define ZLL_BRD_SAM_TABLE_ACK_FRM_PND_CTRL(base) (BME_UBFX32(&ZLL_SAM_TABLE_REG(base), ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_SHIFT, ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_WIDTH))
46954 
46955 /*! @brief Set the ACK_FRM_PND_CTRL field to a new value. */
46956 #define ZLL_WR_SAM_TABLE_ACK_FRM_PND_CTRL(base, value) (ZLL_RMW_SAM_TABLE(base, ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_MASK, ZLL_SAM_TABLE_ACK_FRM_PND_CTRL(value)))
46957 #define ZLL_BWR_SAM_TABLE_ACK_FRM_PND_CTRL(base, value) (BME_BFI32(&ZLL_SAM_TABLE_REG(base), ((uint32_t)(value) << ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_SHIFT), ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_SHIFT, ZLL_SAM_TABLE_ACK_FRM_PND_CTRL_WIDTH))
46958 /*@}*/
46959 
46960 /*!
46961  * @name Register ZLL_SAM_TABLE, field FIND_FREE_IDX[28] (WO)
46962  *
46963  * After modifying Valid bits (enabling or invalidating), write this bit to 1 to
46964  * force hardware to update the "First Free Index" registers to account for the
46965  * changed Valid bits. This hardware update process takes 4us. Software can poll
46966  * SAM_BUSY to determine when the table update is complete. Write-only bit.
46967  * Writing 0 to this bit has no effect. Readback value is indeterminate.
46968  */
46969 /*@{*/
46970 /*! @brief Set the FIND_FREE_IDX field to a new value. */
46971 #define ZLL_WR_SAM_TABLE_FIND_FREE_IDX(base, value) (ZLL_RMW_SAM_TABLE(base, ZLL_SAM_TABLE_FIND_FREE_IDX_MASK, ZLL_SAM_TABLE_FIND_FREE_IDX(value)))
46972 #define ZLL_BWR_SAM_TABLE_FIND_FREE_IDX(base, value) (ZLL_WR_SAM_TABLE_FIND_FREE_IDX(base, value))
46973 /*@}*/
46974 
46975 /*!
46976  * @name Register ZLL_SAM_TABLE, field INVALIDATE_ALL[29] (WO)
46977  *
46978  * Writing a 1 to this bit clears all 128 Valid bits. Invalidates the entire
46979  * table. Write-only bit. Writing 0 to this bit has no effect. Readback value is
46980  * indeterminate.
46981  */
46982 /*@{*/
46983 /*! @brief Set the INVALIDATE_ALL field to a new value. */
46984 #define ZLL_WR_SAM_TABLE_INVALIDATE_ALL(base, value) (ZLL_RMW_SAM_TABLE(base, ZLL_SAM_TABLE_INVALIDATE_ALL_MASK, ZLL_SAM_TABLE_INVALIDATE_ALL(value)))
46985 #define ZLL_BWR_SAM_TABLE_INVALIDATE_ALL(base, value) (ZLL_WR_SAM_TABLE_INVALIDATE_ALL(base, value))
46986 /*@}*/
46987 
46988 /*!
46989  * @name Register ZLL_SAM_TABLE, field SAM_BUSY[31] (RO)
46990  *
46991  * Hardware is in the process of updating the Source Address table, either in
46992  * response to a poll indication from the packet processor, or due to software
46993  * setting FIND_FREE_IDX=1. In the latter case, software should poll SAM_BUSY until
46994  * low before accessing the "First Free Index" registers. Read-only bit.
46995  */
46996 /*@{*/
46997 /*! @brief Read current value of the ZLL_SAM_TABLE_SAM_BUSY field. */
46998 #define ZLL_RD_SAM_TABLE_SAM_BUSY(base) ((ZLL_SAM_TABLE_REG(base) & ZLL_SAM_TABLE_SAM_BUSY_MASK) >> ZLL_SAM_TABLE_SAM_BUSY_SHIFT)
46999 #define ZLL_BRD_SAM_TABLE_SAM_BUSY(base) (BME_UBFX32(&ZLL_SAM_TABLE_REG(base), ZLL_SAM_TABLE_SAM_BUSY_SHIFT, ZLL_SAM_TABLE_SAM_BUSY_WIDTH))
47000 /*@}*/
47001 
47002 /*******************************************************************************
47003  * ZLL_SAM_MATCH - SAM MATCH
47004  ******************************************************************************/
47005 
47006 /*!
47007  * @brief ZLL_SAM_MATCH - SAM MATCH (RO)
47008  *
47009  * Reset value: 0x00000000U
47010  *
47011  * Source Address Management Match Register
47012  */
47013 /*!
47014  * @name Constants and macros for entire ZLL_SAM_MATCH register
47015  */
47016 /*@{*/
47017 #define ZLL_RD_SAM_MATCH(base)   (ZLL_SAM_MATCH_REG(base))
47018 /*@}*/
47019 
47020 /*
47021  * Constants & macros for individual ZLL_SAM_MATCH bitfields
47022  */
47023 
47024 /*!
47025  * @name Register ZLL_SAM_MATCH, field SAP0_MATCH[6:0] (RO)
47026  */
47027 /*@{*/
47028 /*! @brief Read current value of the ZLL_SAM_MATCH_SAP0_MATCH field. */
47029 #define ZLL_RD_SAM_MATCH_SAP0_MATCH(base) ((ZLL_SAM_MATCH_REG(base) & ZLL_SAM_MATCH_SAP0_MATCH_MASK) >> ZLL_SAM_MATCH_SAP0_MATCH_SHIFT)
47030 #define ZLL_BRD_SAM_MATCH_SAP0_MATCH(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MATCH_SAP0_MATCH_SHIFT, ZLL_SAM_MATCH_SAP0_MATCH_WIDTH))
47031 /*@}*/
47032 
47033 /*!
47034  * @name Register ZLL_SAM_MATCH, field SAP0_ADDR_PRESENT[7] (RO)
47035  */
47036 /*@{*/
47037 /*! @brief Read current value of the ZLL_SAM_MATCH_SAP0_ADDR_PRESENT field. */
47038 #define ZLL_RD_SAM_MATCH_SAP0_ADDR_PRESENT(base) ((ZLL_SAM_MATCH_REG(base) & ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_MASK) >> ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_SHIFT)
47039 #define ZLL_BRD_SAM_MATCH_SAP0_ADDR_PRESENT(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_SHIFT, ZLL_SAM_MATCH_SAP0_ADDR_PRESENT_WIDTH))
47040 /*@}*/
47041 
47042 /*!
47043  * @name Register ZLL_SAM_MATCH, field SAA0_MATCH[14:8] (RO)
47044  */
47045 /*@{*/
47046 /*! @brief Read current value of the ZLL_SAM_MATCH_SAA0_MATCH field. */
47047 #define ZLL_RD_SAM_MATCH_SAA0_MATCH(base) ((ZLL_SAM_MATCH_REG(base) & ZLL_SAM_MATCH_SAA0_MATCH_MASK) >> ZLL_SAM_MATCH_SAA0_MATCH_SHIFT)
47048 #define ZLL_BRD_SAM_MATCH_SAA0_MATCH(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MATCH_SAA0_MATCH_SHIFT, ZLL_SAM_MATCH_SAA0_MATCH_WIDTH))
47049 /*@}*/
47050 
47051 /*!
47052  * @name Register ZLL_SAM_MATCH, field SAA0_ADDR_ABSENT[15] (RO)
47053  */
47054 /*@{*/
47055 /*! @brief Read current value of the ZLL_SAM_MATCH_SAA0_ADDR_ABSENT field. */
47056 #define ZLL_RD_SAM_MATCH_SAA0_ADDR_ABSENT(base) ((ZLL_SAM_MATCH_REG(base) & ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_MASK) >> ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_SHIFT)
47057 #define ZLL_BRD_SAM_MATCH_SAA0_ADDR_ABSENT(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_SHIFT, ZLL_SAM_MATCH_SAA0_ADDR_ABSENT_WIDTH))
47058 /*@}*/
47059 
47060 /*!
47061  * @name Register ZLL_SAM_MATCH, field SAP1_MATCH[22:16] (RO)
47062  */
47063 /*@{*/
47064 /*! @brief Read current value of the ZLL_SAM_MATCH_SAP1_MATCH field. */
47065 #define ZLL_RD_SAM_MATCH_SAP1_MATCH(base) ((ZLL_SAM_MATCH_REG(base) & ZLL_SAM_MATCH_SAP1_MATCH_MASK) >> ZLL_SAM_MATCH_SAP1_MATCH_SHIFT)
47066 #define ZLL_BRD_SAM_MATCH_SAP1_MATCH(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MATCH_SAP1_MATCH_SHIFT, ZLL_SAM_MATCH_SAP1_MATCH_WIDTH))
47067 /*@}*/
47068 
47069 /*!
47070  * @name Register ZLL_SAM_MATCH, field SAP1_ADDR_PRESENT[23] (RO)
47071  */
47072 /*@{*/
47073 /*! @brief Read current value of the ZLL_SAM_MATCH_SAP1_ADDR_PRESENT field. */
47074 #define ZLL_RD_SAM_MATCH_SAP1_ADDR_PRESENT(base) ((ZLL_SAM_MATCH_REG(base) & ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_MASK) >> ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_SHIFT)
47075 #define ZLL_BRD_SAM_MATCH_SAP1_ADDR_PRESENT(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_SHIFT, ZLL_SAM_MATCH_SAP1_ADDR_PRESENT_WIDTH))
47076 /*@}*/
47077 
47078 /*!
47079  * @name Register ZLL_SAM_MATCH, field SAA1_MATCH[30:24] (RO)
47080  */
47081 /*@{*/
47082 /*! @brief Read current value of the ZLL_SAM_MATCH_SAA1_MATCH field. */
47083 #define ZLL_RD_SAM_MATCH_SAA1_MATCH(base) ((ZLL_SAM_MATCH_REG(base) & ZLL_SAM_MATCH_SAA1_MATCH_MASK) >> ZLL_SAM_MATCH_SAA1_MATCH_SHIFT)
47084 #define ZLL_BRD_SAM_MATCH_SAA1_MATCH(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MATCH_SAA1_MATCH_SHIFT, ZLL_SAM_MATCH_SAA1_MATCH_WIDTH))
47085 /*@}*/
47086 
47087 /*!
47088  * @name Register ZLL_SAM_MATCH, field SAA1_ADDR_ABSENT[31] (RO)
47089  */
47090 /*@{*/
47091 /*! @brief Read current value of the ZLL_SAM_MATCH_SAA1_ADDR_ABSENT field. */
47092 #define ZLL_RD_SAM_MATCH_SAA1_ADDR_ABSENT(base) ((ZLL_SAM_MATCH_REG(base) & ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_MASK) >> ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_SHIFT)
47093 #define ZLL_BRD_SAM_MATCH_SAA1_ADDR_ABSENT(base) (BME_UBFX32(&ZLL_SAM_MATCH_REG(base), ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_SHIFT, ZLL_SAM_MATCH_SAA1_ADDR_ABSENT_WIDTH))
47094 /*@}*/
47095 
47096 /*******************************************************************************
47097  * ZLL_SAM_FREE_IDX - SAM FREE INDEX
47098  ******************************************************************************/
47099 
47100 /*!
47101  * @brief ZLL_SAM_FREE_IDX - SAM FREE INDEX (RO)
47102  *
47103  * Reset value: 0x00000000U
47104  *
47105  * Source Address Management Free Index Register
47106  */
47107 /*!
47108  * @name Constants and macros for entire ZLL_SAM_FREE_IDX register
47109  */
47110 /*@{*/
47111 #define ZLL_RD_SAM_FREE_IDX(base) (ZLL_SAM_FREE_IDX_REG(base))
47112 /*@}*/
47113 
47114 /*
47115  * Constants & macros for individual ZLL_SAM_FREE_IDX bitfields
47116  */
47117 
47118 /*!
47119  * @name Register ZLL_SAM_FREE_IDX, field SAP0_1ST_FREE_IDX[7:0] (RO)
47120  */
47121 /*@{*/
47122 /*! @brief Read current value of the ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX field. */
47123 #define ZLL_RD_SAM_FREE_IDX_SAP0_1ST_FREE_IDX(base) ((ZLL_SAM_FREE_IDX_REG(base) & ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_MASK) >> ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_SHIFT)
47124 #define ZLL_BRD_SAM_FREE_IDX_SAP0_1ST_FREE_IDX(base) (BME_UBFX32(&ZLL_SAM_FREE_IDX_REG(base), ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_SHIFT, ZLL_SAM_FREE_IDX_SAP0_1ST_FREE_IDX_WIDTH))
47125 /*@}*/
47126 
47127 /*!
47128  * @name Register ZLL_SAM_FREE_IDX, field SAA0_1ST_FREE_IDX[15:8] (RO)
47129  */
47130 /*@{*/
47131 /*! @brief Read current value of the ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX field. */
47132 #define ZLL_RD_SAM_FREE_IDX_SAA0_1ST_FREE_IDX(base) ((ZLL_SAM_FREE_IDX_REG(base) & ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_MASK) >> ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_SHIFT)
47133 #define ZLL_BRD_SAM_FREE_IDX_SAA0_1ST_FREE_IDX(base) (BME_UBFX32(&ZLL_SAM_FREE_IDX_REG(base), ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_SHIFT, ZLL_SAM_FREE_IDX_SAA0_1ST_FREE_IDX_WIDTH))
47134 /*@}*/
47135 
47136 /*!
47137  * @name Register ZLL_SAM_FREE_IDX, field SAP1_1ST_FREE_IDX[23:16] (RO)
47138  */
47139 /*@{*/
47140 /*! @brief Read current value of the ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX field. */
47141 #define ZLL_RD_SAM_FREE_IDX_SAP1_1ST_FREE_IDX(base) ((ZLL_SAM_FREE_IDX_REG(base) & ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_MASK) >> ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_SHIFT)
47142 #define ZLL_BRD_SAM_FREE_IDX_SAP1_1ST_FREE_IDX(base) (BME_UBFX32(&ZLL_SAM_FREE_IDX_REG(base), ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_SHIFT, ZLL_SAM_FREE_IDX_SAP1_1ST_FREE_IDX_WIDTH))
47143 /*@}*/
47144 
47145 /*!
47146  * @name Register ZLL_SAM_FREE_IDX, field SAA1_1ST_FREE_IDX[31:24] (RO)
47147  */
47148 /*@{*/
47149 /*! @brief Read current value of the ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX field. */
47150 #define ZLL_RD_SAM_FREE_IDX_SAA1_1ST_FREE_IDX(base) ((ZLL_SAM_FREE_IDX_REG(base) & ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_MASK) >> ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_SHIFT)
47151 #define ZLL_BRD_SAM_FREE_IDX_SAA1_1ST_FREE_IDX(base) (BME_UBFX32(&ZLL_SAM_FREE_IDX_REG(base), ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_SHIFT, ZLL_SAM_FREE_IDX_SAA1_1ST_FREE_IDX_WIDTH))
47152 /*@}*/
47153 
47154 /*******************************************************************************
47155  * ZLL_SEQ_CTRL_STS - SEQUENCE CONTROL AND STATUS
47156  ******************************************************************************/
47157 
47158 /*!
47159  * @brief ZLL_SEQ_CTRL_STS - SEQUENCE CONTROL AND STATUS (RW)
47160  *
47161  * Reset value: 0x00000008U
47162  */
47163 /*!
47164  * @name Constants and macros for entire ZLL_SEQ_CTRL_STS register
47165  */
47166 /*@{*/
47167 #define ZLL_RD_SEQ_CTRL_STS(base) (ZLL_SEQ_CTRL_STS_REG(base))
47168 #define ZLL_WR_SEQ_CTRL_STS(base, value) (ZLL_SEQ_CTRL_STS_REG(base) = (value))
47169 #define ZLL_RMW_SEQ_CTRL_STS(base, mask, value) (ZLL_WR_SEQ_CTRL_STS(base, (ZLL_RD_SEQ_CTRL_STS(base) & ~(mask)) | (value)))
47170 #define ZLL_SET_SEQ_CTRL_STS(base, value) (BME_OR32(&ZLL_SEQ_CTRL_STS_REG(base), (uint32_t)(value)))
47171 #define ZLL_CLR_SEQ_CTRL_STS(base, value) (BME_AND32(&ZLL_SEQ_CTRL_STS_REG(base), (uint32_t)(~(value))))
47172 #define ZLL_TOG_SEQ_CTRL_STS(base, value) (BME_XOR32(&ZLL_SEQ_CTRL_STS_REG(base), (uint32_t)(value)))
47173 /*@}*/
47174 
47175 /*
47176  * Constants & macros for individual ZLL_SEQ_CTRL_STS bitfields
47177  */
47178 
47179 /*!
47180  * @name Register ZLL_SEQ_CTRL_STS, field CLR_NEW_SEQ_INHIBIT[2] (RW)
47181  *
47182  * when asserted, overrides the automatic hardware locking of the programmed
47183  * XCVSEQ while an autosequence is underway. Asserting this feature will allow
47184  * software to change the programmed autosequence "on-the-fly", without aborting and
47185  * returning to idle between sequences. Overriding the hardware lockout of XCVSEQ
47186  * should be used with caution, since the Sequence Manager is not designed (or
47187  * verified) for manual state transitions between one type of autosequence and
47188  * other (i.e., Sequence T -> Sequence R).
47189  */
47190 /*@{*/
47191 /*! @brief Read current value of the ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT field. */
47192 #define ZLL_RD_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_MASK) >> ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_SHIFT)
47193 #define ZLL_BRD_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_SHIFT, ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_WIDTH))
47194 
47195 /*! @brief Set the CLR_NEW_SEQ_INHIBIT field to a new value. */
47196 #define ZLL_WR_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT(base, value) (ZLL_RMW_SEQ_CTRL_STS(base, ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_MASK, ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT(value)))
47197 #define ZLL_BWR_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT(base, value) (BME_BFI32(&ZLL_SEQ_CTRL_STS_REG(base), ((uint32_t)(value) << ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_SHIFT), ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_SHIFT, ZLL_SEQ_CTRL_STS_CLR_NEW_SEQ_INHIBIT_WIDTH))
47198 /*@}*/
47199 
47200 /*!
47201  * @name Register ZLL_SEQ_CTRL_STS, field EVENT_TMR_DO_NOT_LATCH[3] (RW)
47202  *
47203  * when asserted, overrides the automatic hardware latching of the Event Timer
47204  * that prevents the timer from updating while software reads the 3 Event Timer
47205  * bytes. This allows the Event Timer LS byte to continue to update without reading
47206  * the upper 2 bytes. Overriding the automatic latching of the Event Timer
47207  * should be used with caution, as it can allow the Event Timer lower bytes to get
47208  * out-of-sync with the upper bytes. However, it can be useful when polling the
47209  * Event Timer LS byte for a value that is just a few counts in the future.
47210  */
47211 /*@{*/
47212 /*! @brief Read current value of the ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH field. */
47213 #define ZLL_RD_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_MASK) >> ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_SHIFT)
47214 #define ZLL_BRD_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_SHIFT, ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_WIDTH))
47215 
47216 /*! @brief Set the EVENT_TMR_DO_NOT_LATCH field to a new value. */
47217 #define ZLL_WR_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH(base, value) (ZLL_RMW_SEQ_CTRL_STS(base, ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_MASK, ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH(value)))
47218 #define ZLL_BWR_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH(base, value) (BME_BFI32(&ZLL_SEQ_CTRL_STS_REG(base), ((uint32_t)(value) << ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_SHIFT), ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_SHIFT, ZLL_SEQ_CTRL_STS_EVENT_TMR_DO_NOT_LATCH_WIDTH))
47219 /*@}*/
47220 
47221 /*!
47222  * @name Register ZLL_SEQ_CTRL_STS, field LATCH_PREAMBLE[4] (RW)
47223  *
47224  * Values:
47225  * - 0b0 - Don't make PREAMBLE_DET and SFD_DET bits of PHY_STS (SEQ_STATE)
47226  *     Register "sticky", i.e, these status bits reflect the realtime, dynamic state
47227  *     of preamble_detect and sfd_detect
47228  * - 0b1 - Make PREAMBLE_DET and SFD_DET bits of PHY_STS (SEQ_STATE) Register
47229  *     "sticky", i.e.,occurrences of preamble and SFD detection are latched and
47230  *     held until the start of the next autosequence
47231  */
47232 /*@{*/
47233 /*! @brief Read current value of the ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE field. */
47234 #define ZLL_RD_SEQ_CTRL_STS_LATCH_PREAMBLE(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_MASK) >> ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_SHIFT)
47235 #define ZLL_BRD_SEQ_CTRL_STS_LATCH_PREAMBLE(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_SHIFT, ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_WIDTH))
47236 
47237 /*! @brief Set the LATCH_PREAMBLE field to a new value. */
47238 #define ZLL_WR_SEQ_CTRL_STS_LATCH_PREAMBLE(base, value) (ZLL_RMW_SEQ_CTRL_STS(base, ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_MASK, ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE(value)))
47239 #define ZLL_BWR_SEQ_CTRL_STS_LATCH_PREAMBLE(base, value) (BME_BFI32(&ZLL_SEQ_CTRL_STS_REG(base), ((uint32_t)(value) << ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_SHIFT), ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_SHIFT, ZLL_SEQ_CTRL_STS_LATCH_PREAMBLE_WIDTH))
47240 /*@}*/
47241 
47242 /*!
47243  * @name Register ZLL_SEQ_CTRL_STS, field NO_RX_RECYCLE[5] (RW)
47244  *
47245  * when asserted, prevents the Zigbee Sequence Manager (ZSM) from automatically
47246  * re-starting (recycling) the receiver when a packet is received which results
47247  * in a FilterFail or CRC failure. Normally, on a RX recycle, the ZSM returns to
47248  * the RX_WU (warmup) state, and then resumes from there with a new,
47249  * foreshortened, Rx warmup, in search of a new preamble. When this bit is set, the Sequence
47250  * Manager will instead return to idle state, and issue a SEQIRQ, after a
47251  * FilterFail or CRC failure.
47252  */
47253 /*@{*/
47254 /*! @brief Read current value of the ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE field. */
47255 #define ZLL_RD_SEQ_CTRL_STS_NO_RX_RECYCLE(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_MASK) >> ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_SHIFT)
47256 #define ZLL_BRD_SEQ_CTRL_STS_NO_RX_RECYCLE(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_SHIFT, ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_WIDTH))
47257 
47258 /*! @brief Set the NO_RX_RECYCLE field to a new value. */
47259 #define ZLL_WR_SEQ_CTRL_STS_NO_RX_RECYCLE(base, value) (ZLL_RMW_SEQ_CTRL_STS(base, ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_MASK, ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE(value)))
47260 #define ZLL_BWR_SEQ_CTRL_STS_NO_RX_RECYCLE(base, value) (BME_BFI32(&ZLL_SEQ_CTRL_STS_REG(base), ((uint32_t)(value) << ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_SHIFT), ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_SHIFT, ZLL_SEQ_CTRL_STS_NO_RX_RECYCLE_WIDTH))
47261 /*@}*/
47262 
47263 /*!
47264  * @name Register ZLL_SEQ_CTRL_STS, field FORCE_CRC_ERROR[6] (RW)
47265  *
47266  * Values:
47267  * - 0b0 - normal operation
47268  * - 0b1 - Force the next transmitted packet to have a CRC error
47269  */
47270 /*@{*/
47271 /*! @brief Read current value of the ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR field. */
47272 #define ZLL_RD_SEQ_CTRL_STS_FORCE_CRC_ERROR(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_MASK) >> ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_SHIFT)
47273 #define ZLL_BRD_SEQ_CTRL_STS_FORCE_CRC_ERROR(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_SHIFT, ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_WIDTH))
47274 
47275 /*! @brief Set the FORCE_CRC_ERROR field to a new value. */
47276 #define ZLL_WR_SEQ_CTRL_STS_FORCE_CRC_ERROR(base, value) (ZLL_RMW_SEQ_CTRL_STS(base, ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_MASK, ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR(value)))
47277 #define ZLL_BWR_SEQ_CTRL_STS_FORCE_CRC_ERROR(base, value) (BME_BFI32(&ZLL_SEQ_CTRL_STS_REG(base), ((uint32_t)(value) << ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_SHIFT), ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_SHIFT, ZLL_SEQ_CTRL_STS_FORCE_CRC_ERROR_WIDTH))
47278 /*@}*/
47279 
47280 /*!
47281  * @name Register ZLL_SEQ_CTRL_STS, field CONTINUOUS_EN[7] (RW)
47282  *
47283  * Continuous Mode Enable (Continuous TX or RX). Note: Dual PAN mode should not
47284  * be engaged in Continuous TX or RX modes.
47285  *
47286  * Values:
47287  * - 0b0 - normal operation
47288  * - 0b1 - Continuous TX or RX mode is enabled (depending on XCVSEQ setting).
47289  */
47290 /*@{*/
47291 /*! @brief Read current value of the ZLL_SEQ_CTRL_STS_CONTINUOUS_EN field. */
47292 #define ZLL_RD_SEQ_CTRL_STS_CONTINUOUS_EN(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_MASK) >> ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_SHIFT)
47293 #define ZLL_BRD_SEQ_CTRL_STS_CONTINUOUS_EN(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_SHIFT, ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_WIDTH))
47294 
47295 /*! @brief Set the CONTINUOUS_EN field to a new value. */
47296 #define ZLL_WR_SEQ_CTRL_STS_CONTINUOUS_EN(base, value) (ZLL_RMW_SEQ_CTRL_STS(base, ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_MASK, ZLL_SEQ_CTRL_STS_CONTINUOUS_EN(value)))
47297 #define ZLL_BWR_SEQ_CTRL_STS_CONTINUOUS_EN(base, value) (BME_BFI32(&ZLL_SEQ_CTRL_STS_REG(base), ((uint32_t)(value) << ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_SHIFT), ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_SHIFT, ZLL_SEQ_CTRL_STS_CONTINUOUS_EN_WIDTH))
47298 /*@}*/
47299 
47300 /*!
47301  * @name Register ZLL_SEQ_CTRL_STS, field XCVSEQ_ACTUAL[10:8] (RO)
47302  *
47303  * Reflects the programmed sequence that has been recognized by the Zigbee
47304  * Sequence Manager. Takes into account the fact that sequence-change commands from
47305  * software are ignored while a sequence is underway (see NEW_SEQ_INHIBIT).
47306  * Read-only bits.
47307  */
47308 /*@{*/
47309 /*! @brief Read current value of the ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL field. */
47310 #define ZLL_RD_SEQ_CTRL_STS_XCVSEQ_ACTUAL(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_MASK) >> ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_SHIFT)
47311 #define ZLL_BRD_SEQ_CTRL_STS_XCVSEQ_ACTUAL(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_SHIFT, ZLL_SEQ_CTRL_STS_XCVSEQ_ACTUAL_WIDTH))
47312 /*@}*/
47313 
47314 /*!
47315  * @name Register ZLL_SEQ_CTRL_STS, field SEQ_IDLE[11] (RO)
47316  */
47317 /*@{*/
47318 /*! @brief Read current value of the ZLL_SEQ_CTRL_STS_SEQ_IDLE field. */
47319 #define ZLL_RD_SEQ_CTRL_STS_SEQ_IDLE(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_SEQ_IDLE_MASK) >> ZLL_SEQ_CTRL_STS_SEQ_IDLE_SHIFT)
47320 #define ZLL_BRD_SEQ_CTRL_STS_SEQ_IDLE(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL_STS_SEQ_IDLE_SHIFT, ZLL_SEQ_CTRL_STS_SEQ_IDLE_WIDTH))
47321 /*@}*/
47322 
47323 /*!
47324  * @name Register ZLL_SEQ_CTRL_STS, field NEW_SEQ_INHIBIT[12] (RO)
47325  *
47326  * When asserted, indicates that a new programmed autosequence has commenced
47327  * (TMR2 match has occurred if TMRTRIGEN=1). Once this bit is asserted, software is
47328  * blocked from commanding any "new" autosequences (other than Sequence I to
47329  * abort the current sequence), until the current sequence completes. Hardware will
47330  * ignore a sequence-change command from software while this bit is asserted.
47331  * Hardware will automatically deassert this bit once the sequence completes.
47332  * Read-only bit.
47333  */
47334 /*@{*/
47335 /*! @brief Read current value of the ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT field. */
47336 #define ZLL_RD_SEQ_CTRL_STS_NEW_SEQ_INHIBIT(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_MASK) >> ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_SHIFT)
47337 #define ZLL_BRD_SEQ_CTRL_STS_NEW_SEQ_INHIBIT(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_SHIFT, ZLL_SEQ_CTRL_STS_NEW_SEQ_INHIBIT_WIDTH))
47338 /*@}*/
47339 
47340 /*!
47341  * @name Register ZLL_SEQ_CTRL_STS, field RX_TIMEOUT_PENDING[13] (RO)
47342  *
47343  * when asserted, indicates that a TMR3 timeout (RX timeout) flag has been set
47344  * by Hardware, but the Sequence Manager has not yet aborted because an RX
47345  * operation is not currently underway. This would be the case, for example, during a
47346  * Sequence TR, if a TMR3 timeout were to occur during the transmit operation of
47347  * this sequence; the sequence would not be aborted by Hardware until the receive
47348  * operation begins. This bit will always be 0 if TC3TMOUT=0. Read-only bit.
47349  */
47350 /*@{*/
47351 /*! @brief Read current value of the ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING field. */
47352 #define ZLL_RD_SEQ_CTRL_STS_RX_TIMEOUT_PENDING(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_MASK) >> ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_SHIFT)
47353 #define ZLL_BRD_SEQ_CTRL_STS_RX_TIMEOUT_PENDING(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_SHIFT, ZLL_SEQ_CTRL_STS_RX_TIMEOUT_PENDING_WIDTH))
47354 /*@}*/
47355 
47356 /*!
47357  * @name Register ZLL_SEQ_CTRL_STS, field RX_MODE[14] (RO)
47358  *
47359  * when asserted, this Sequence Manager Output indicates that an RX operation is
47360  * in progress. An RX operation can be part of a complex transmit autosequence
47361  * such as a Sequence TR. CCA and ED operations are considered RX operations,
47362  * during which rx_mode is asserted. Read-only bit.
47363  */
47364 /*@{*/
47365 /*! @brief Read current value of the ZLL_SEQ_CTRL_STS_RX_MODE field. */
47366 #define ZLL_RD_SEQ_CTRL_STS_RX_MODE(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_RX_MODE_MASK) >> ZLL_SEQ_CTRL_STS_RX_MODE_SHIFT)
47367 #define ZLL_BRD_SEQ_CTRL_STS_RX_MODE(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL_STS_RX_MODE_SHIFT, ZLL_SEQ_CTRL_STS_RX_MODE_WIDTH))
47368 /*@}*/
47369 
47370 /*!
47371  * @name Register ZLL_SEQ_CTRL_STS, field TMR2_SEQ_TRIG_ARMED[15] (RO)
47372  *
47373  * when asserted, indicates that TMR2 has been programmed and is "armed" to
47374  * trigger a new autosequence, when Zigbee Sequence Manager timer-triggering mode is
47375  * selected (i.e., TMRTRIGEN=1). When timer-triggering mode is selected, TMR2
47376  * must be re-programmed (using either T2CMP or T2PRIMECMP), in advance of each new
47377  * sequence. Once TMR2 is programmed, this bit will be asserted, and will remain
47378  * asserted until the new sequence commences (at TMR2 match). Hardware will
47379  * deassert this bit when the new sequence starts. When TMRTRIGEN=0, this bit should
47380  * be ignored. Read-only bit.
47381  */
47382 /*@{*/
47383 /*! @brief Read current value of the ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED field. */
47384 #define ZLL_RD_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_MASK) >> ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_SHIFT)
47385 #define ZLL_BRD_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_SHIFT, ZLL_SEQ_CTRL_STS_TMR2_SEQ_TRIG_ARMED_WIDTH))
47386 /*@}*/
47387 
47388 /*!
47389  * @name Register ZLL_SEQ_CTRL_STS, field SEQ_T_STATUS[21:16] (RO)
47390  *
47391  * Status of the just-completed (or ongoing) Sequence T or Sequence TR
47392  * autosequence. This register is valid at all times during, and after, the Sequence T or
47393  * Sequence TR. Not valid for other types of autosequences. This is a read-only
47394  * register. The bits of this register map to status, according to the following
47395  * table: [0] 1st CCA complete (CCABFRTX=1) [1] 2nd CCA complete (SLOTTED=1) [2]
47396  * Tx operation complete [3] Rx Rec ycle occurred (Sequence TR only) [4] Rx
47397  * operation complete (Sequence TR only) [5] TxAck operation complete(Sequence TR only)
47398  */
47399 /*@{*/
47400 /*! @brief Read current value of the ZLL_SEQ_CTRL_STS_SEQ_T_STATUS field. */
47401 #define ZLL_RD_SEQ_CTRL_STS_SEQ_T_STATUS(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_MASK) >> ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_SHIFT)
47402 #define ZLL_BRD_SEQ_CTRL_STS_SEQ_T_STATUS(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_SHIFT, ZLL_SEQ_CTRL_STS_SEQ_T_STATUS_WIDTH))
47403 /*@}*/
47404 
47405 /*!
47406  * @name Register ZLL_SEQ_CTRL_STS, field SW_ABORTED[24] (RO)
47407  *
47408  * when asserted, indicates that the autosequence has terminated due to an
47409  * Software abort. Software can abort any programmed autosequence by writing Sequence
47410  * I to XCVSEQ. This bit is valid at the SEQIRQ interrupt. Hardware will maintain
47411  * this bit asserted until the next autosequence commences. Read-only bit.
47412  */
47413 /*@{*/
47414 /*! @brief Read current value of the ZLL_SEQ_CTRL_STS_SW_ABORTED field. */
47415 #define ZLL_RD_SEQ_CTRL_STS_SW_ABORTED(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_SW_ABORTED_MASK) >> ZLL_SEQ_CTRL_STS_SW_ABORTED_SHIFT)
47416 #define ZLL_BRD_SEQ_CTRL_STS_SW_ABORTED(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL_STS_SW_ABORTED_SHIFT, ZLL_SEQ_CTRL_STS_SW_ABORTED_WIDTH))
47417 /*@}*/
47418 
47419 /*!
47420  * @name Register ZLL_SEQ_CTRL_STS, field TC3_ABORTED[25] (RO)
47421  *
47422  * when asserted, indicates that the autosequence has terminated due to an TC3
47423  * (TMR3) timeout during a receive operation. This bit is valid at the SEQIRQ
47424  * interrupt. Hardware will maintain this bit asserted until the next autosequence
47425  * commences. Read-only bit.
47426  */
47427 /*@{*/
47428 /*! @brief Read current value of the ZLL_SEQ_CTRL_STS_TC3_ABORTED field. */
47429 #define ZLL_RD_SEQ_CTRL_STS_TC3_ABORTED(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_TC3_ABORTED_MASK) >> ZLL_SEQ_CTRL_STS_TC3_ABORTED_SHIFT)
47430 #define ZLL_BRD_SEQ_CTRL_STS_TC3_ABORTED(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL_STS_TC3_ABORTED_SHIFT, ZLL_SEQ_CTRL_STS_TC3_ABORTED_WIDTH))
47431 /*@}*/
47432 
47433 /*!
47434  * @name Register ZLL_SEQ_CTRL_STS, field PLL_ABORTED[26] (RO)
47435  *
47436  * when asserted, indicates that the autosequence has terminated due to an PLL
47437  * unlock event. This bit is valid at the SEQIRQ interrupt. Hardware will maintain
47438  * this bit asserted until the next autosequence commences. Read-only bit.
47439  */
47440 /*@{*/
47441 /*! @brief Read current value of the ZLL_SEQ_CTRL_STS_PLL_ABORTED field. */
47442 #define ZLL_RD_SEQ_CTRL_STS_PLL_ABORTED(base) ((ZLL_SEQ_CTRL_STS_REG(base) & ZLL_SEQ_CTRL_STS_PLL_ABORTED_MASK) >> ZLL_SEQ_CTRL_STS_PLL_ABORTED_SHIFT)
47443 #define ZLL_BRD_SEQ_CTRL_STS_PLL_ABORTED(base) (BME_UBFX32(&ZLL_SEQ_CTRL_STS_REG(base), ZLL_SEQ_CTRL_STS_PLL_ABORTED_SHIFT, ZLL_SEQ_CTRL_STS_PLL_ABORTED_WIDTH))
47444 /*@}*/
47445 
47446 /*******************************************************************************
47447  * ZLL_ACKDELAY - ACK DELAY
47448  ******************************************************************************/
47449 
47450 /*!
47451  * @brief ZLL_ACKDELAY - ACK DELAY (RW)
47452  *
47453  * Reset value: 0x00000007U
47454  */
47455 /*!
47456  * @name Constants and macros for entire ZLL_ACKDELAY register
47457  */
47458 /*@{*/
47459 #define ZLL_RD_ACKDELAY(base)    (ZLL_ACKDELAY_REG(base))
47460 #define ZLL_WR_ACKDELAY(base, value) (ZLL_ACKDELAY_REG(base) = (value))
47461 #define ZLL_RMW_ACKDELAY(base, mask, value) (ZLL_WR_ACKDELAY(base, (ZLL_RD_ACKDELAY(base) & ~(mask)) | (value)))
47462 #define ZLL_SET_ACKDELAY(base, value) (BME_OR32(&ZLL_ACKDELAY_REG(base), (uint32_t)(value)))
47463 #define ZLL_CLR_ACKDELAY(base, value) (BME_AND32(&ZLL_ACKDELAY_REG(base), (uint32_t)(~(value))))
47464 #define ZLL_TOG_ACKDELAY(base, value) (BME_XOR32(&ZLL_ACKDELAY_REG(base), (uint32_t)(value)))
47465 /*@}*/
47466 
47467 /*
47468  * Constants & macros for individual ZLL_ACKDELAY bitfields
47469  */
47470 
47471 /*!
47472  * @name Register ZLL_ACKDELAY, field ACKDELAY[5:0] (RW)
47473  *
47474  * Provides a fine-tune adjustment of the time delay between Rx warmdown and the
47475  * beginning of Tx warmup for an Tx Acknowledge packet. ACKDELAY register will
47476  * apply to both SLOTTED and UNSLOTTED TxAck, but only to TxAck (not T sequences).
47477  * This is a two's complement value. The minimum permissible value is -19
47478  * (0x2D). Values less than -19 will lead to unexpected results. Resolution = 2us.
47479  * Range = +/- 62us. Max ACKDELAY = 0x1F.Min ACKDELAY = 0x2D.
47480  */
47481 /*@{*/
47482 /*! @brief Read current value of the ZLL_ACKDELAY_ACKDELAY field. */
47483 #define ZLL_RD_ACKDELAY_ACKDELAY(base) ((ZLL_ACKDELAY_REG(base) & ZLL_ACKDELAY_ACKDELAY_MASK) >> ZLL_ACKDELAY_ACKDELAY_SHIFT)
47484 #define ZLL_BRD_ACKDELAY_ACKDELAY(base) (BME_UBFX32(&ZLL_ACKDELAY_REG(base), ZLL_ACKDELAY_ACKDELAY_SHIFT, ZLL_ACKDELAY_ACKDELAY_WIDTH))
47485 
47486 /*! @brief Set the ACKDELAY field to a new value. */
47487 #define ZLL_WR_ACKDELAY_ACKDELAY(base, value) (ZLL_RMW_ACKDELAY(base, ZLL_ACKDELAY_ACKDELAY_MASK, ZLL_ACKDELAY_ACKDELAY(value)))
47488 #define ZLL_BWR_ACKDELAY_ACKDELAY(base, value) (BME_BFI32(&ZLL_ACKDELAY_REG(base), ((uint32_t)(value) << ZLL_ACKDELAY_ACKDELAY_SHIFT), ZLL_ACKDELAY_ACKDELAY_SHIFT, ZLL_ACKDELAY_ACKDELAY_WIDTH))
47489 /*@}*/
47490 
47491 /*!
47492  * @name Register ZLL_ACKDELAY, field TXDELAY[13:8] (RW)
47493  *
47494  * Provides a fine-tune adjustment of the time delay between post-CCA Rx
47495  * warm-down and the beginning of Tx warm-up for an Tx (non-Ack) packet. TXDELAY
47496  * register will apply in both SLOTTED and UNSLOTTED modes, but only to T sequences
47497  * (e.g., T, TR, and T(R) ), not TxAck operations. This is a two's complement value.
47498  * The minimum permissible value is -19 (0x2D). Values less than -19 will lead to
47499  * unexpected results. Resolution = 2us. Range = +/- 62us. Max TXDELAY =
47500  * 0x1F.Min TXDELAY = 0x2D.
47501  */
47502 /*@{*/
47503 /*! @brief Read current value of the ZLL_ACKDELAY_TXDELAY field. */
47504 #define ZLL_RD_ACKDELAY_TXDELAY(base) ((ZLL_ACKDELAY_REG(base) & ZLL_ACKDELAY_TXDELAY_MASK) >> ZLL_ACKDELAY_TXDELAY_SHIFT)
47505 #define ZLL_BRD_ACKDELAY_TXDELAY(base) (BME_UBFX32(&ZLL_ACKDELAY_REG(base), ZLL_ACKDELAY_TXDELAY_SHIFT, ZLL_ACKDELAY_TXDELAY_WIDTH))
47506 
47507 /*! @brief Set the TXDELAY field to a new value. */
47508 #define ZLL_WR_ACKDELAY_TXDELAY(base, value) (ZLL_RMW_ACKDELAY(base, ZLL_ACKDELAY_TXDELAY_MASK, ZLL_ACKDELAY_TXDELAY(value)))
47509 #define ZLL_BWR_ACKDELAY_TXDELAY(base, value) (BME_BFI32(&ZLL_ACKDELAY_REG(base), ((uint32_t)(value) << ZLL_ACKDELAY_TXDELAY_SHIFT), ZLL_ACKDELAY_TXDELAY_SHIFT, ZLL_ACKDELAY_TXDELAY_WIDTH))
47510 /*@}*/
47511 
47512 /*******************************************************************************
47513  * ZLL_FILTERFAIL_CODE - FILTER FAIL CODE
47514  ******************************************************************************/
47515 
47516 /*!
47517  * @brief ZLL_FILTERFAIL_CODE - FILTER FAIL CODE (RW)
47518  *
47519  * Reset value: 0x00000000U
47520  */
47521 /*!
47522  * @name Constants and macros for entire ZLL_FILTERFAIL_CODE register
47523  */
47524 /*@{*/
47525 #define ZLL_RD_FILTERFAIL_CODE(base) (ZLL_FILTERFAIL_CODE_REG(base))
47526 #define ZLL_WR_FILTERFAIL_CODE(base, value) (ZLL_FILTERFAIL_CODE_REG(base) = (value))
47527 #define ZLL_RMW_FILTERFAIL_CODE(base, mask, value) (ZLL_WR_FILTERFAIL_CODE(base, (ZLL_RD_FILTERFAIL_CODE(base) & ~(mask)) | (value)))
47528 #define ZLL_SET_FILTERFAIL_CODE(base, value) (BME_OR32(&ZLL_FILTERFAIL_CODE_REG(base), (uint32_t)(value)))
47529 #define ZLL_CLR_FILTERFAIL_CODE(base, value) (BME_AND32(&ZLL_FILTERFAIL_CODE_REG(base), (uint32_t)(~(value))))
47530 #define ZLL_TOG_FILTERFAIL_CODE(base, value) (BME_XOR32(&ZLL_FILTERFAIL_CODE_REG(base), (uint32_t)(value)))
47531 /*@}*/
47532 
47533 /*
47534  * Constants & macros for individual ZLL_FILTERFAIL_CODE bitfields
47535  */
47536 
47537 /*!
47538  * @name Register ZLL_FILTERFAIL_CODE, field FILTERFAIL_CODE[9:0] (RO)
47539  *
47540  * Code inidicating what condition, or conditions, caused the Packet Processor
47541  * to reject the just-received packet. The bits of FILTERFAIL_CODE indicate the
47542  * reason for packet rejection according to the table below: FILTERFAIL CODE BIT
47543  * REASON FOR FILTERFAIL [0] Fails Stage 1 Frame Length Checking (FL < 5 or FL >
47544  * MAXFRAMELENGTH) Note: FL < 3 will not generate an SFD, so this bit will not be
47545  * set [1] Fails Stage 1 Section 7.2.1.1.6 or Section 7.2.1.1.8 Checking
47546  * (DST_ADDR_MODE or SRC_ADDR_MODE = 1) [2] Fails Stage 1 Section 7.2.1.1.5 Checking
47547  * (Illegal PAN_ID_COMPRESSION Usage) [3] Fails Stage 1 Frame Version Checking [4]
47548  * Fails Stage 2 Auto-RxAck Checking (Illegal Ack Frame Format in Sequence TR) [5]
47549  * Fails Stage 2 Frame Type Checking (Incorrect Frame Filter Bit setting) [6]
47550  * Fails Stage 2 Frame Length Checking (Illegal Beacon, Data, or Cmd FL) [7] Fails
47551  * Stage 2 Addressing Mode Checking (Illegal Addressing Mode for Beacon, Data, OR
47552  * Cmd) [8] Fails Stage 2 Sequence Number Matching (Sequence TR Only) [9] Fails
47553  * Stage 2 PAN ID or Address Checking (Beacon, Data, or Cmd)
47554  */
47555 /*@{*/
47556 /*! @brief Read current value of the ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE field. */
47557 #define ZLL_RD_FILTERFAIL_CODE_FILTERFAIL_CODE(base) ((ZLL_FILTERFAIL_CODE_REG(base) & ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_MASK) >> ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_SHIFT)
47558 #define ZLL_BRD_FILTERFAIL_CODE_FILTERFAIL_CODE(base) (BME_UBFX32(&ZLL_FILTERFAIL_CODE_REG(base), ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_SHIFT, ZLL_FILTERFAIL_CODE_FILTERFAIL_CODE_WIDTH))
47559 /*@}*/
47560 
47561 /*!
47562  * @name Register ZLL_FILTERFAIL_CODE, field FILTERFAIL_PAN_SEL[15] (RW)
47563  *
47564  * Values:
47565  * - 0b0 - FILTERFAIL_CODE[9:0] will report the FILTERFAIL status of PAN0
47566  * - 0b1 - FILTERFAIL_CODE[9:0] will report the FILTERFAIL status of PAN1
47567  */
47568 /*@{*/
47569 /*! @brief Read current value of the ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL field. */
47570 #define ZLL_RD_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL(base) ((ZLL_FILTERFAIL_CODE_REG(base) & ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_MASK) >> ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_SHIFT)
47571 #define ZLL_BRD_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL(base) (BME_UBFX32(&ZLL_FILTERFAIL_CODE_REG(base), ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_SHIFT, ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_WIDTH))
47572 
47573 /*! @brief Set the FILTERFAIL_PAN_SEL field to a new value. */
47574 #define ZLL_WR_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL(base, value) (ZLL_RMW_FILTERFAIL_CODE(base, ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_MASK, ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL(value)))
47575 #define ZLL_BWR_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL(base, value) (BME_BFI32(&ZLL_FILTERFAIL_CODE_REG(base), ((uint32_t)(value) << ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_SHIFT), ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_SHIFT, ZLL_FILTERFAIL_CODE_FILTERFAIL_PAN_SEL_WIDTH))
47576 /*@}*/
47577 
47578 /*******************************************************************************
47579  * ZLL_RX_WTR_MARK - RECEIVE WATER MARK
47580  ******************************************************************************/
47581 
47582 /*!
47583  * @brief ZLL_RX_WTR_MARK - RECEIVE WATER MARK (RW)
47584  *
47585  * Reset value: 0x000000FFU
47586  *
47587  * Receive byte count (octets) needed to trigger a RXWTRMRKIRQ interrupt . A
47588  * setting of 0 generates an interrupt at end of the Frame Length field (first byte
47589  * after SFD). A setting of 1 generates an interrupt after the first byte of
47590  * Frame Control Field, etc.
47591  */
47592 /*!
47593  * @name Constants and macros for entire ZLL_RX_WTR_MARK register
47594  */
47595 /*@{*/
47596 #define ZLL_RD_RX_WTR_MARK(base) (ZLL_RX_WTR_MARK_REG(base))
47597 #define ZLL_WR_RX_WTR_MARK(base, value) (ZLL_RX_WTR_MARK_REG(base) = (value))
47598 #define ZLL_RMW_RX_WTR_MARK(base, mask, value) (ZLL_WR_RX_WTR_MARK(base, (ZLL_RD_RX_WTR_MARK(base) & ~(mask)) | (value)))
47599 #define ZLL_SET_RX_WTR_MARK(base, value) (BME_OR32(&ZLL_RX_WTR_MARK_REG(base), (uint32_t)(value)))
47600 #define ZLL_CLR_RX_WTR_MARK(base, value) (BME_AND32(&ZLL_RX_WTR_MARK_REG(base), (uint32_t)(~(value))))
47601 #define ZLL_TOG_RX_WTR_MARK(base, value) (BME_XOR32(&ZLL_RX_WTR_MARK_REG(base), (uint32_t)(value)))
47602 /*@}*/
47603 
47604 /*
47605  * Constants & macros for individual ZLL_RX_WTR_MARK bitfields
47606  */
47607 
47608 /*!
47609  * @name Register ZLL_RX_WTR_MARK, field RX_WTR_MARK[7:0] (RW)
47610  */
47611 /*@{*/
47612 /*! @brief Read current value of the ZLL_RX_WTR_MARK_RX_WTR_MARK field. */
47613 #define ZLL_RD_RX_WTR_MARK_RX_WTR_MARK(base) ((ZLL_RX_WTR_MARK_REG(base) & ZLL_RX_WTR_MARK_RX_WTR_MARK_MASK) >> ZLL_RX_WTR_MARK_RX_WTR_MARK_SHIFT)
47614 #define ZLL_BRD_RX_WTR_MARK_RX_WTR_MARK(base) (BME_UBFX32(&ZLL_RX_WTR_MARK_REG(base), ZLL_RX_WTR_MARK_RX_WTR_MARK_SHIFT, ZLL_RX_WTR_MARK_RX_WTR_MARK_WIDTH))
47615 
47616 /*! @brief Set the RX_WTR_MARK field to a new value. */
47617 #define ZLL_WR_RX_WTR_MARK_RX_WTR_MARK(base, value) (ZLL_RMW_RX_WTR_MARK(base, ZLL_RX_WTR_MARK_RX_WTR_MARK_MASK, ZLL_RX_WTR_MARK_RX_WTR_MARK(value)))
47618 #define ZLL_BWR_RX_WTR_MARK_RX_WTR_MARK(base, value) (BME_BFI32(&ZLL_RX_WTR_MARK_REG(base), ((uint32_t)(value) << ZLL_RX_WTR_MARK_RX_WTR_MARK_SHIFT), ZLL_RX_WTR_MARK_RX_WTR_MARK_SHIFT, ZLL_RX_WTR_MARK_RX_WTR_MARK_WIDTH))
47619 /*@}*/
47620 
47621 /*******************************************************************************
47622  * ZLL_SLOT_PRELOAD - SLOT PRELOAD
47623  ******************************************************************************/
47624 
47625 /*!
47626  * @brief ZLL_SLOT_PRELOAD - SLOT PRELOAD (RW)
47627  *
47628  * Reset value: 0x00000074U
47629  *
47630  * This register represents the number that gets loaded into the slot_timer at
47631  * SFD detect, which ultimately determines when the next slot boundary will occur.
47632  * Due to processing delays within the analog front-end and digital modem, the
47633  * point at which SFD is detected by the modem, is delayed relative to
47634  * over-the-air timing. Since this timing may not be known for coconino until actual
47635  * silicon, and since this is such a critical timing parameter for slotted operations,
47636  * it has been made programmable. This timing parameter is critical for the
47637  * Sequence R autosequence in slotted mode, when an automatic TxAck is required.
47638  */
47639 /*!
47640  * @name Constants and macros for entire ZLL_SLOT_PRELOAD register
47641  */
47642 /*@{*/
47643 #define ZLL_RD_SLOT_PRELOAD(base) (ZLL_SLOT_PRELOAD_REG(base))
47644 #define ZLL_WR_SLOT_PRELOAD(base, value) (ZLL_SLOT_PRELOAD_REG(base) = (value))
47645 #define ZLL_RMW_SLOT_PRELOAD(base, mask, value) (ZLL_WR_SLOT_PRELOAD(base, (ZLL_RD_SLOT_PRELOAD(base) & ~(mask)) | (value)))
47646 #define ZLL_SET_SLOT_PRELOAD(base, value) (BME_OR32(&ZLL_SLOT_PRELOAD_REG(base), (uint32_t)(value)))
47647 #define ZLL_CLR_SLOT_PRELOAD(base, value) (BME_AND32(&ZLL_SLOT_PRELOAD_REG(base), (uint32_t)(~(value))))
47648 #define ZLL_TOG_SLOT_PRELOAD(base, value) (BME_XOR32(&ZLL_SLOT_PRELOAD_REG(base), (uint32_t)(value)))
47649 /*@}*/
47650 
47651 /*
47652  * Constants & macros for individual ZLL_SLOT_PRELOAD bitfields
47653  */
47654 
47655 /*!
47656  * @name Register ZLL_SLOT_PRELOAD, field SLOT_PRELOAD[7:0] (RW)
47657  */
47658 /*@{*/
47659 /*! @brief Read current value of the ZLL_SLOT_PRELOAD_SLOT_PRELOAD field. */
47660 #define ZLL_RD_SLOT_PRELOAD_SLOT_PRELOAD(base) ((ZLL_SLOT_PRELOAD_REG(base) & ZLL_SLOT_PRELOAD_SLOT_PRELOAD_MASK) >> ZLL_SLOT_PRELOAD_SLOT_PRELOAD_SHIFT)
47661 #define ZLL_BRD_SLOT_PRELOAD_SLOT_PRELOAD(base) (BME_UBFX32(&ZLL_SLOT_PRELOAD_REG(base), ZLL_SLOT_PRELOAD_SLOT_PRELOAD_SHIFT, ZLL_SLOT_PRELOAD_SLOT_PRELOAD_WIDTH))
47662 
47663 /*! @brief Set the SLOT_PRELOAD field to a new value. */
47664 #define ZLL_WR_SLOT_PRELOAD_SLOT_PRELOAD(base, value) (ZLL_RMW_SLOT_PRELOAD(base, ZLL_SLOT_PRELOAD_SLOT_PRELOAD_MASK, ZLL_SLOT_PRELOAD_SLOT_PRELOAD(value)))
47665 #define ZLL_BWR_SLOT_PRELOAD_SLOT_PRELOAD(base, value) (BME_BFI32(&ZLL_SLOT_PRELOAD_REG(base), ((uint32_t)(value) << ZLL_SLOT_PRELOAD_SLOT_PRELOAD_SHIFT), ZLL_SLOT_PRELOAD_SLOT_PRELOAD_SHIFT, ZLL_SLOT_PRELOAD_SLOT_PRELOAD_WIDTH))
47666 /*@}*/
47667 
47668 /*******************************************************************************
47669  * ZLL_SEQ_STATE - ZIGBEE SEQUENCE STATE
47670  ******************************************************************************/
47671 
47672 /*!
47673  * @brief ZLL_SEQ_STATE - ZIGBEE SEQUENCE STATE (RO)
47674  *
47675  * Reset value: 0x00000000U
47676  *
47677  * Zigbee Sequence State Register
47678  */
47679 /*!
47680  * @name Constants and macros for entire ZLL_SEQ_STATE register
47681  */
47682 /*@{*/
47683 #define ZLL_RD_SEQ_STATE(base)   (ZLL_SEQ_STATE_REG(base))
47684 /*@}*/
47685 
47686 /*
47687  * Constants & macros for individual ZLL_SEQ_STATE bitfields
47688  */
47689 
47690 /*!
47691  * @name Register ZLL_SEQ_STATE, field SEQ_STATE[4:0] (RO)
47692  *
47693  * This read-only register reflects the instantaneous state of the Zigbee
47694  * Sequence Manager
47695  */
47696 /*@{*/
47697 /*! @brief Read current value of the ZLL_SEQ_STATE_SEQ_STATE field. */
47698 #define ZLL_RD_SEQ_STATE_SEQ_STATE(base) ((ZLL_SEQ_STATE_REG(base) & ZLL_SEQ_STATE_SEQ_STATE_MASK) >> ZLL_SEQ_STATE_SEQ_STATE_SHIFT)
47699 #define ZLL_BRD_SEQ_STATE_SEQ_STATE(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_SEQ_STATE_SHIFT, ZLL_SEQ_STATE_SEQ_STATE_WIDTH))
47700 /*@}*/
47701 
47702 /*!
47703  * @name Register ZLL_SEQ_STATE, field PREAMBLE_DET[8] (RO)
47704  *
47705  * 0: an 802.15.4 preamble has not been detected. 1: An 802.15.4 preamble has
47706  * been detected. The function of this read-only bit depends on the setting of the
47707  * LATCH_PREAMBLE bit of the SEQ_MGR_CTRL register. If LATCH_PREAMBLE=1, any
47708  * preamble detection during a Sequence R (even false detections), will set this bit,
47709  * and it will remain set (sticky) until the start of the next autosequence. If
47710  * LATCH_PREAMBLE=0, this bit is not sticky, and reflects the instantaneous state
47711  * of the preamble-detection circuit; for false preambles, the bit will clear
47712  * when the false nature of the preamble is recognized. When LATCH_PREAMBLE=0,
47713  * PREAMBLE_DET should be considered valid only while an autosequence is underway.
47714  */
47715 /*@{*/
47716 /*! @brief Read current value of the ZLL_SEQ_STATE_PREAMBLE_DET field. */
47717 #define ZLL_RD_SEQ_STATE_PREAMBLE_DET(base) ((ZLL_SEQ_STATE_REG(base) & ZLL_SEQ_STATE_PREAMBLE_DET_MASK) >> ZLL_SEQ_STATE_PREAMBLE_DET_SHIFT)
47718 #define ZLL_BRD_SEQ_STATE_PREAMBLE_DET(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_PREAMBLE_DET_SHIFT, ZLL_SEQ_STATE_PREAMBLE_DET_WIDTH))
47719 /*@}*/
47720 
47721 /*!
47722  * @name Register ZLL_SEQ_STATE, field SFD_DET[9] (RO)
47723  *
47724  * 0: an 802.15.4 preamble-and-SFD have not been detected. 1: An 802.15.4
47725  * preamble-and-SFD have been detected. The function of this read-only bit depends on
47726  * the setting of the LATCH_PREAMBLE bit of the SEQ_MGR_CTRL register. If
47727  * LATCH_PREAMBLE=1, any preamble-and-SFD detection during a Sequence R (even false
47728  * detections), will set this bit, and it will remain set (sticky) until the start of
47729  * the next autosequence. If LATCH_PREAMBLE=0, this bit is not sticky, and
47730  * reflects the instantaneous state of the SFD-detection circuit; for false SFD, the
47731  * bit will clear when the false nature of the SFD is recognized (i.e., an RX
47732  * recycle). When LATCH_PREAMBLE=0, SFD_DET should be considered valid only while an
47733  * autosequence is underway.
47734  */
47735 /*@{*/
47736 /*! @brief Read current value of the ZLL_SEQ_STATE_SFD_DET field. */
47737 #define ZLL_RD_SEQ_STATE_SFD_DET(base) ((ZLL_SEQ_STATE_REG(base) & ZLL_SEQ_STATE_SFD_DET_MASK) >> ZLL_SEQ_STATE_SFD_DET_SHIFT)
47738 #define ZLL_BRD_SEQ_STATE_SFD_DET(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_SFD_DET_SHIFT, ZLL_SEQ_STATE_SFD_DET_WIDTH))
47739 /*@}*/
47740 
47741 /*!
47742  * @name Register ZLL_SEQ_STATE, field FILTERFAIL_FLAG_SEL[10] (RO)
47743  *
47744  * 0: The incoming, or just-received packet, passed packet filtering rules. 1:
47745  * The incoming, or just-received packet, failed packet filtering rules When
47746  * FILTERFAIL_FLAG_SEL=1, a non-zero FILTERFAIL_CODE is present (see FILTERFAIL_CODE
47747  * registers). In Dual PAN mode, FILTERFAIL_FLAG_SEL applies to either or both
47748  * networks, as follows: A: If PAN0 and PAN1 occupy different channels and
47749  * CURRENT_NETWORK=0, FILTERFAIL_FLAG_SEL applies to PAN0. B: If PAN0 and PAN1 occupy
47750  * different channels and CURRENT_NETWORK=1, FILTERFAIL_FLAG_SEL applies to PAN1. C:
47751  * If PAN0 and PAN1 occupy the same channel, FILTERFAIL_FLAG_SEL is the logical
47752  * 'AND' of the individual PANs' FILTERFAIL_FLAG bits.
47753  */
47754 /*@{*/
47755 /*! @brief Read current value of the ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL field. */
47756 #define ZLL_RD_SEQ_STATE_FILTERFAIL_FLAG_SEL(base) ((ZLL_SEQ_STATE_REG(base) & ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_MASK) >> ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_SHIFT)
47757 #define ZLL_BRD_SEQ_STATE_FILTERFAIL_FLAG_SEL(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_SHIFT, ZLL_SEQ_STATE_FILTERFAIL_FLAG_SEL_WIDTH))
47758 /*@}*/
47759 
47760 /*!
47761  * @name Register ZLL_SEQ_STATE, field CRCVALID[11] (RO)
47762  *
47763  * Code Redundancy Check Valid: This flag indicates the compare result between
47764  * the FCS field, in the most-recently received frame, and the internally
47765  * calculated CRC value. This flag is cleared at next receiver warm up.
47766  *
47767  * Values:
47768  * - 0b0 - Rx FCS != calculated CRC (incorrect)
47769  * - 0b1 - Rx FCS = calculated CRC (correct)
47770  */
47771 /*@{*/
47772 /*! @brief Read current value of the ZLL_SEQ_STATE_CRCVALID field. */
47773 #define ZLL_RD_SEQ_STATE_CRCVALID(base) ((ZLL_SEQ_STATE_REG(base) & ZLL_SEQ_STATE_CRCVALID_MASK) >> ZLL_SEQ_STATE_CRCVALID_SHIFT)
47774 #define ZLL_BRD_SEQ_STATE_CRCVALID(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_CRCVALID_SHIFT, ZLL_SEQ_STATE_CRCVALID_WIDTH))
47775 /*@}*/
47776 
47777 /*!
47778  * @name Register ZLL_SEQ_STATE, field PLL_ABORT[12] (RO)
47779  *
47780  * This bit reflects the instantaneous, consolidated status of the PLL unlock
47781  * detection circuits; if asserted high, indicates that at least one of the three
47782  * PLL unlock detect mechanisms is currently reporting an unlocked condition.
47783  */
47784 /*@{*/
47785 /*! @brief Read current value of the ZLL_SEQ_STATE_PLL_ABORT field. */
47786 #define ZLL_RD_SEQ_STATE_PLL_ABORT(base) ((ZLL_SEQ_STATE_REG(base) & ZLL_SEQ_STATE_PLL_ABORT_MASK) >> ZLL_SEQ_STATE_PLL_ABORT_SHIFT)
47787 #define ZLL_BRD_SEQ_STATE_PLL_ABORT(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_PLL_ABORT_SHIFT, ZLL_SEQ_STATE_PLL_ABORT_WIDTH))
47788 /*@}*/
47789 
47790 /*!
47791  * @name Register ZLL_SEQ_STATE, field PLL_ABORTED[13] (RO)
47792  *
47793  * when asserted, indicates that the autosequence has terminated due to an PLL
47794  * unlock event. This bit is valid at the SEQIRQ interrupt. Hardware will maintain
47795  * this bit asserted until the next autosequence commences. This bit is a
47796  * read-only mirror of the register bit of the same name in the ABORT_STS
47797  * (SEQ_CTRL_STS) register.
47798  */
47799 /*@{*/
47800 /*! @brief Read current value of the ZLL_SEQ_STATE_PLL_ABORTED field. */
47801 #define ZLL_RD_SEQ_STATE_PLL_ABORTED(base) ((ZLL_SEQ_STATE_REG(base) & ZLL_SEQ_STATE_PLL_ABORTED_MASK) >> ZLL_SEQ_STATE_PLL_ABORTED_SHIFT)
47802 #define ZLL_BRD_SEQ_STATE_PLL_ABORTED(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_PLL_ABORTED_SHIFT, ZLL_SEQ_STATE_PLL_ABORTED_WIDTH))
47803 /*@}*/
47804 
47805 /*!
47806  * @name Register ZLL_SEQ_STATE, field RX_BYTE_COUNT[23:16] (RO)
47807  *
47808  * During packet reception, this read-only register is a real-time indicator of
47809  * the number of bytes that have been received. This register will read 0 until
47810  * SFD and PHR have been received. It will read 1 after the first byte of Frame
47811  * Control Field has been received, etc.
47812  */
47813 /*@{*/
47814 /*! @brief Read current value of the ZLL_SEQ_STATE_RX_BYTE_COUNT field. */
47815 #define ZLL_RD_SEQ_STATE_RX_BYTE_COUNT(base) ((ZLL_SEQ_STATE_REG(base) & ZLL_SEQ_STATE_RX_BYTE_COUNT_MASK) >> ZLL_SEQ_STATE_RX_BYTE_COUNT_SHIFT)
47816 #define ZLL_BRD_SEQ_STATE_RX_BYTE_COUNT(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_RX_BYTE_COUNT_SHIFT, ZLL_SEQ_STATE_RX_BYTE_COUNT_WIDTH))
47817 /*@}*/
47818 
47819 /*!
47820  * @name Register ZLL_SEQ_STATE, field CCCA_BUSY_CNT[29:24] (RO)
47821  *
47822  * For Sequence CCCA mode only, this register indicates the number of "busy" CCA
47823  * attempts which occurred during the autosequence, before the channel was
47824  * detected to be idle. This register can also be read in real-time (during the
47825  * autosequence) to determine how many busy CCA attempts have occurred to that point.
47826  * The register saturates at 63 (i.e, if there are more than 63 busy attempts, the
47827  * register will continue to read 63). This register is automatically cleared to
47828  * zero by hardware when the next autosequence commences. Read-only register.
47829  */
47830 /*@{*/
47831 /*! @brief Read current value of the ZLL_SEQ_STATE_CCCA_BUSY_CNT field. */
47832 #define ZLL_RD_SEQ_STATE_CCCA_BUSY_CNT(base) ((ZLL_SEQ_STATE_REG(base) & ZLL_SEQ_STATE_CCCA_BUSY_CNT_MASK) >> ZLL_SEQ_STATE_CCCA_BUSY_CNT_SHIFT)
47833 #define ZLL_BRD_SEQ_STATE_CCCA_BUSY_CNT(base) (BME_UBFX32(&ZLL_SEQ_STATE_REG(base), ZLL_SEQ_STATE_CCCA_BUSY_CNT_SHIFT, ZLL_SEQ_STATE_CCCA_BUSY_CNT_WIDTH))
47834 /*@}*/
47835 
47836 /*******************************************************************************
47837  * ZLL_TMR_PRESCALE - TIMER PRESCALER
47838  ******************************************************************************/
47839 
47840 /*!
47841  * @brief ZLL_TMR_PRESCALE - TIMER PRESCALER (RW)
47842  *
47843  * Reset value: 0x00000003U
47844  *
47845  * Timer Prescaler
47846  */
47847 /*!
47848  * @name Constants and macros for entire ZLL_TMR_PRESCALE register
47849  */
47850 /*@{*/
47851 #define ZLL_RD_TMR_PRESCALE(base) (ZLL_TMR_PRESCALE_REG(base))
47852 #define ZLL_WR_TMR_PRESCALE(base, value) (ZLL_TMR_PRESCALE_REG(base) = (value))
47853 #define ZLL_RMW_TMR_PRESCALE(base, mask, value) (ZLL_WR_TMR_PRESCALE(base, (ZLL_RD_TMR_PRESCALE(base) & ~(mask)) | (value)))
47854 #define ZLL_SET_TMR_PRESCALE(base, value) (BME_OR32(&ZLL_TMR_PRESCALE_REG(base), (uint32_t)(value)))
47855 #define ZLL_CLR_TMR_PRESCALE(base, value) (BME_AND32(&ZLL_TMR_PRESCALE_REG(base), (uint32_t)(~(value))))
47856 #define ZLL_TOG_TMR_PRESCALE(base, value) (BME_XOR32(&ZLL_TMR_PRESCALE_REG(base), (uint32_t)(value)))
47857 /*@}*/
47858 
47859 /*
47860  * Constants & macros for individual ZLL_TMR_PRESCALE bitfields
47861  */
47862 
47863 /*!
47864  * @name Register ZLL_TMR_PRESCALE, field TMR_PRESCALE[2:0] (RW)
47865  *
47866  * Timer Prescaler. Establishes the Event Timer clock rate, (maximum timer
47867  * duration)
47868  *
47869  * Values:
47870  * - 0b000 - Reserved
47871  * - 0b001 - Reserved
47872  * - 0b010 - 500kHz (33.55 S)
47873  * - 0b011 - 250kHz (67.11 S) -- default
47874  * - 0b100 - 125kHz (134.22 S)
47875  * - 0b101 - 62.5kHz (268.44 S)
47876  * - 0b110 - 31.25kHz (536.87 S)
47877  * - 0b111 - 15.625kHz (1073.74 S)
47878  */
47879 /*@{*/
47880 /*! @brief Read current value of the ZLL_TMR_PRESCALE_TMR_PRESCALE field. */
47881 #define ZLL_RD_TMR_PRESCALE_TMR_PRESCALE(base) ((ZLL_TMR_PRESCALE_REG(base) & ZLL_TMR_PRESCALE_TMR_PRESCALE_MASK) >> ZLL_TMR_PRESCALE_TMR_PRESCALE_SHIFT)
47882 #define ZLL_BRD_TMR_PRESCALE_TMR_PRESCALE(base) (BME_UBFX32(&ZLL_TMR_PRESCALE_REG(base), ZLL_TMR_PRESCALE_TMR_PRESCALE_SHIFT, ZLL_TMR_PRESCALE_TMR_PRESCALE_WIDTH))
47883 
47884 /*! @brief Set the TMR_PRESCALE field to a new value. */
47885 #define ZLL_WR_TMR_PRESCALE_TMR_PRESCALE(base, value) (ZLL_RMW_TMR_PRESCALE(base, ZLL_TMR_PRESCALE_TMR_PRESCALE_MASK, ZLL_TMR_PRESCALE_TMR_PRESCALE(value)))
47886 #define ZLL_BWR_TMR_PRESCALE_TMR_PRESCALE(base, value) (BME_BFI32(&ZLL_TMR_PRESCALE_REG(base), ((uint32_t)(value) << ZLL_TMR_PRESCALE_TMR_PRESCALE_SHIFT), ZLL_TMR_PRESCALE_TMR_PRESCALE_SHIFT, ZLL_TMR_PRESCALE_TMR_PRESCALE_WIDTH))
47887 /*@}*/
47888 
47889 /*******************************************************************************
47890  * ZLL_LENIENCY_LSB - LENIENCY LSB
47891  ******************************************************************************/
47892 
47893 /*!
47894  * @brief ZLL_LENIENCY_LSB - LENIENCY LSB (RW)
47895  *
47896  * Reset value: 0x00000000U
47897  *
47898  * The Packet Processor performs filtering on all received packets, in order to
47899  * determine whether the packet is intended for the device. The packet filtering
47900  * is based on rules. In case any of the packet filtering rules need to be
47901  * overriden, a 40-bit "leniency register" has been provided. When the leniency
47902  * register is programmed to its default value (0), all hardware packet filtering rules
47903  * are in effect, and if an incoming packet violates any rule, a "Filter Fail"
47904  * will occur (packet will be rejected). When a given leniency register bit is
47905  * asserted, the packet filtering rule assigned to that bit will not be in effect,
47906  * and if any incoming packet violates that rule (but no other rules), then a
47907  * "Filter Fail" will not occur, the packet will not be rejected, the packet will be
47908  * treated as "intended for the device", and software will be notified of the
47909  * incoming packet. The table below shows the assignment of leniency bits to packet
47910  * filtering rules.
47911  */
47912 /*!
47913  * @name Constants and macros for entire ZLL_LENIENCY_LSB register
47914  */
47915 /*@{*/
47916 #define ZLL_RD_LENIENCY_LSB(base) (ZLL_LENIENCY_LSB_REG(base))
47917 #define ZLL_WR_LENIENCY_LSB(base, value) (ZLL_LENIENCY_LSB_REG(base) = (value))
47918 #define ZLL_RMW_LENIENCY_LSB(base, mask, value) (ZLL_WR_LENIENCY_LSB(base, (ZLL_RD_LENIENCY_LSB(base) & ~(mask)) | (value)))
47919 #define ZLL_SET_LENIENCY_LSB(base, value) (BME_OR32(&ZLL_LENIENCY_LSB_REG(base), (uint32_t)(value)))
47920 #define ZLL_CLR_LENIENCY_LSB(base, value) (BME_AND32(&ZLL_LENIENCY_LSB_REG(base), (uint32_t)(~(value))))
47921 #define ZLL_TOG_LENIENCY_LSB(base, value) (BME_XOR32(&ZLL_LENIENCY_LSB_REG(base), (uint32_t)(value)))
47922 /*@}*/
47923 
47924 /*******************************************************************************
47925  * ZLL_LENIENCY_MSB - LENIENCY MSB
47926  ******************************************************************************/
47927 
47928 /*!
47929  * @brief ZLL_LENIENCY_MSB - LENIENCY MSB (RW)
47930  *
47931  * Reset value: 0x00000000U
47932  *
47933  * The Packet Processor performs filtering on all received packets, in order to
47934  * determine whether the packet is intended for the device. The packet filtering
47935  * is based on rules. In case any of the packet filtering rules need to be
47936  * overriden, a 40-bit "leniency register" has been provided. When the leniency
47937  * register is programmed to its default value (0), all hardware packet filtering rules
47938  * are in effect, and if an incoming packet violates any rule, a "Filter Fail"
47939  * will occur (packet will be rejected). When a given leniency register bit is
47940  * asserted, the packet filtering rule assigned to that bit will not be in effect,
47941  * and if any incoming packet violates that rule (but no other rules), then a
47942  * "Filter Fail" will not occur, the packet will not be rejected, the packet will be
47943  * treated as "intended for the device", and software will be notified of the
47944  * incoming packet. The table below shows the assignment of leniency bits to packet
47945  * filtering rules.
47946  */
47947 /*!
47948  * @name Constants and macros for entire ZLL_LENIENCY_MSB register
47949  */
47950 /*@{*/
47951 #define ZLL_RD_LENIENCY_MSB(base) (ZLL_LENIENCY_MSB_REG(base))
47952 #define ZLL_WR_LENIENCY_MSB(base, value) (ZLL_LENIENCY_MSB_REG(base) = (value))
47953 #define ZLL_RMW_LENIENCY_MSB(base, mask, value) (ZLL_WR_LENIENCY_MSB(base, (ZLL_RD_LENIENCY_MSB(base) & ~(mask)) | (value)))
47954 #define ZLL_SET_LENIENCY_MSB(base, value) (BME_OR32(&ZLL_LENIENCY_MSB_REG(base), (uint32_t)(value)))
47955 #define ZLL_CLR_LENIENCY_MSB(base, value) (BME_AND32(&ZLL_LENIENCY_MSB_REG(base), (uint32_t)(~(value))))
47956 #define ZLL_TOG_LENIENCY_MSB(base, value) (BME_XOR32(&ZLL_LENIENCY_MSB_REG(base), (uint32_t)(value)))
47957 /*@}*/
47958 
47959 /*
47960  * Constants & macros for individual ZLL_LENIENCY_MSB bitfields
47961  */
47962 
47963 /*!
47964  * @name Register ZLL_LENIENCY_MSB, field LENIENCY_REGISTER[7:0] (RW)
47965  *
47966  * LENIENCY BIT PACKET FILTERING RULE OVERRIDDEN leniency[32] Override Stage 2
47967  * Short Addr Filter for
47968  * DST_ADDR_MODE_SHORT/SRC_ADDR_MODE_LONG/NO_PAN_ID_COMPRESSION (Data and MAC Command Only) leniency[33] Override Stage 2 PAN ID Filter
47969  * for DST_ADDR_MODE_LONG/SRC_ADDR_MODE_SHORT/NO_PAN_ID_COMPRESSION (Beacon Only)
47970  * leniency[34] Override Stage 2 PAN ID Filter for
47971  * DST_ADDR_MODE_LONG/SRC_ADDR_MODE_SHORT/NO_PAN_ID_COMPRESSI ON (Data and MAC Command Only) leniency[35]
47972  * Override Stage 2 Long Addr Filter for
47973  * DST_ADDR_MODE_LONG/SRC_ADDR_MODE_SHORT/NO_PAN_ID_COMPRESSION (Data and MAC Command Only) leniency[36] Override Stage 2 PAN
47974  * ID Filter for DST_ADDR_MODE_LONG/SRC_ADDR_MODE_LONG (Beacon Only) leniency[37]
47975  * Override Stage 2 PAN ID Filter for DST_ADDR_MODE_LONG/SRC_ADDR_MODE_LONG (Data
47976  * and MAC Command Only) leniency[38] Override Stage 2 Long Addr Filter for
47977  * DST_ADDR_MODE_LONG/SRC_ADDR_MODE_LONG (Data and MAC Command Only) leniency[39]
47978  * Allow an auto-TxAck frame to be sent, after a receive frame which has all of the
47979  * following parameters: 1. Destination PAN ID = Broadcast (0xFFFF) 2.
47980  * Destination Address = !Broadcast (not 0xFFFF) 3. Destination Address Mode = Short
47981  * Nominally, the SEQ_MGR inhibits auto-TxAck on such frames.
47982  */
47983 /*@{*/
47984 /*! @brief Read current value of the ZLL_LENIENCY_MSB_LENIENCY_REGISTER field. */
47985 #define ZLL_RD_LENIENCY_MSB_LENIENCY_REGISTER(base) ((ZLL_LENIENCY_MSB_REG(base) & ZLL_LENIENCY_MSB_LENIENCY_REGISTER_MASK) >> ZLL_LENIENCY_MSB_LENIENCY_REGISTER_SHIFT)
47986 #define ZLL_BRD_LENIENCY_MSB_LENIENCY_REGISTER(base) (BME_UBFX32(&ZLL_LENIENCY_MSB_REG(base), ZLL_LENIENCY_MSB_LENIENCY_REGISTER_SHIFT, ZLL_LENIENCY_MSB_LENIENCY_REGISTER_WIDTH))
47987 
47988 /*! @brief Set the LENIENCY_REGISTER field to a new value. */
47989 #define ZLL_WR_LENIENCY_MSB_LENIENCY_REGISTER(base, value) (ZLL_RMW_LENIENCY_MSB(base, ZLL_LENIENCY_MSB_LENIENCY_REGISTER_MASK, ZLL_LENIENCY_MSB_LENIENCY_REGISTER(value)))
47990 #define ZLL_BWR_LENIENCY_MSB_LENIENCY_REGISTER(base, value) (BME_BFI32(&ZLL_LENIENCY_MSB_REG(base), ((uint32_t)(value) << ZLL_LENIENCY_MSB_LENIENCY_REGISTER_SHIFT), ZLL_LENIENCY_MSB_LENIENCY_REGISTER_SHIFT, ZLL_LENIENCY_MSB_LENIENCY_REGISTER_WIDTH))
47991 /*@}*/
47992 
47993 /*******************************************************************************
47994  * ZLL_PART_ID - PART ID
47995  ******************************************************************************/
47996 
47997 /*!
47998  * @brief ZLL_PART_ID - PART ID (RO)
47999  *
48000  * Reset value: 0x00000000U
48001  *
48002  * Zigbee Part ID
48003  */
48004 /*!
48005  * @name Constants and macros for entire ZLL_PART_ID register
48006  */
48007 /*@{*/
48008 #define ZLL_RD_PART_ID(base)     (ZLL_PART_ID_REG(base))
48009 /*@}*/
48010 
48011 /*
48012  * Constants & macros for individual ZLL_PART_ID bitfields
48013  */
48014 
48015 /*!
48016  * @name Register ZLL_PART_ID, field PART_ID[7:0] (RO)
48017  */
48018 /*@{*/
48019 /*! @brief Read current value of the ZLL_PART_ID_PART_ID field. */
48020 #define ZLL_RD_PART_ID_PART_ID(base) ((ZLL_PART_ID_REG(base) & ZLL_PART_ID_PART_ID_MASK) >> ZLL_PART_ID_PART_ID_SHIFT)
48021 #define ZLL_BRD_PART_ID_PART_ID(base) (BME_UBFX32(&ZLL_PART_ID_REG(base), ZLL_PART_ID_PART_ID_SHIFT, ZLL_PART_ID_PART_ID_WIDTH))
48022 /*@}*/
48023 
48024 /*******************************************************************************
48025  * ZLL_PKT_BUFFER - PACKET BUFFER
48026  ******************************************************************************/
48027 
48028 /*!
48029  * @brief ZLL_PKT_BUFFER - PACKET BUFFER (RW)
48030  *
48031  * Reset value: 0x00000000U
48032  *
48033  * Packet Buffer
48034  */
48035 /*!
48036  * @name Constants and macros for entire ZLL_PKT_BUFFER register
48037  */
48038 /*@{*/
48039 #define ZLL_RD_PKT_BUFFER(base, index) (ZLL_PKT_BUFFER_REG(base, index))
48040 #define ZLL_WR_PKT_BUFFER(base, index, value) (ZLL_PKT_BUFFER_REG(base, index) = (value))
48041 #define ZLL_RMW_PKT_BUFFER(base, index, mask, value) (ZLL_WR_PKT_BUFFER(base, index, (ZLL_RD_PKT_BUFFER(base, index) & ~(mask)) | (value)))
48042 #define ZLL_SET_PKT_BUFFER(base, index, value) (BME_OR32(&ZLL_PKT_BUFFER_REG(base, index), (uint32_t)(value)))
48043 #define ZLL_CLR_PKT_BUFFER(base, index, value) (BME_AND32(&ZLL_PKT_BUFFER_REG(base, index), (uint32_t)(~(value))))
48044 #define ZLL_TOG_PKT_BUFFER(base, index, value) (BME_XOR32(&ZLL_PKT_BUFFER_REG(base, index), (uint32_t)(value)))
48045 /*@}*/
48046 
48047 /* Instance numbers for core modules */
48048 #define JTAG_IDX (0) /*!< Instance number for JTAG. */
48049 #define TPIU_IDX (0) /*!< Instance number for TPIU. */
48050 #define SCB_IDX (0) /*!< Instance number for SCB. */
48051 #define SWD_IDX (0) /*!< Instance number for SWD. */
48052 #define RADIO_IDX (0) /*!< Instance number for RADIO. */
48053 #define ZigBee_IDX (0) /*!< Instance number for ZigBee. */
48054 #define CoreDebug_IDX (0) /*!< Instance number for CoreDebug. */
48055 
48056 #if defined(__IAR_SYSTEMS_ICC__)
48057   /* Restore checking of "Error[Pm008]: sections of code should not be 'commented out' (MISRA C 2004 rule 2.4)" */
48058   #pragma diag_default=pm008
48059 #endif
48060 
48061 #endif /* __MKW40Z4_EXTENSION_H__ */
48062 /* EOF */
48063