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Searched refs:LTC_MD_ICV_TEST_MASK (Results 1 – 15 of 15) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/drivers/ltc/
Dfsl_ltc.c1009 modeReg |= (uint32_t)kLTC_ModeUpdate | LTC_MD_ICV_TEST_MASK; in ltc_aes_received_mac_compare()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW31Z4/
DMKW31Z4.h4082 #define LTC_MD_ICV_TEST_MASK (0x2U) macro
4084 … (((uint32_t)(((uint32_t)(x)) << LTC_MD_ICV_TEST_SHIFT)) & LTC_MD_ICV_TEST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW30Z4/
DMKW30Z4.h4015 #define LTC_MD_ICV_TEST_MASK 0x2u macro
4018 …) (((uint32_t)(((uint32_t)(x))<<LTC_MD_ICV_TEST_SHIFT))&LTC_MD_ICV_TEST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW21Z4/
DMKW21Z4.h4011 #define LTC_MD_ICV_TEST_MASK (0x2U) macro
4013 … (((uint32_t)(((uint32_t)(x)) << LTC_MD_ICV_TEST_SHIFT)) & LTC_MD_ICV_TEST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW20Z4/
DMKW20Z4.h4015 #define LTC_MD_ICV_TEST_MASK 0x2u macro
4018 …) (((uint32_t)(((uint32_t)(x))<<LTC_MD_ICV_TEST_SHIFT))&LTC_MD_ICV_TEST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW41Z4/
DMKW41Z4.h4082 #define LTC_MD_ICV_TEST_MASK (0x2U) macro
4084 … (((uint32_t)(((uint32_t)(x)) << LTC_MD_ICV_TEST_SHIFT)) & LTC_MD_ICV_TEST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW40Z4/
DMKW40Z4.h4015 #define LTC_MD_ICV_TEST_MASK 0x2u macro
4018 …) (((uint32_t)(((uint32_t)(x))<<LTC_MD_ICV_TEST_SHIFT))&LTC_MD_ICV_TEST_MASK)
DMKW40Z4_extension.h12202 #define LTC_RD_MD_ICV_TEST(base) ((LTC_MD_REG(base) & LTC_MD_ICV_TEST_MASK) >> LTC_MD_ICV_TEST_SHIF…
12206 #define LTC_WR_MD_ICV_TEST(base, value) (LTC_RMW_MD(base, LTC_MD_ICV_TEST_MASK, LTC_MD_ICV_TEST(val…
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h16418 #define LTC_MD_ICV_TEST_MASK (0x2U) macro
16420 … (((uint32_t)(((uint32_t)(x)) << LTC_MD_ICV_TEST_SHIFT)) & LTC_MD_ICV_TEST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h16497 #define LTC_MD_ICV_TEST_MASK (0x2U) macro
16500 … (((uint32_t)(((uint32_t)(x)) << LTC_MD_ICV_TEST_SHIFT)) & LTC_MD_ICV_TEST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h16498 #define LTC_MD_ICV_TEST_MASK (0x2U) macro
16501 … (((uint32_t)(((uint32_t)(x)) << LTC_MD_ICV_TEST_SHIFT)) & LTC_MD_ICV_TEST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/
DMCXW716A.h22611 #define LTC_MD_ICV_TEST_MASK (0x2U) macro
22614 … (((uint32_t)(((uint32_t)(x)) << LTC_MD_ICV_TEST_SHIFT)) & LTC_MD_ICV_TEST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/
DMCXW716C.h24780 #define LTC_MD_ICV_TEST_MASK (0x2U) macro
24783 … (((uint32_t)(((uint32_t)(x)) << LTC_MD_ICV_TEST_SHIFT)) & LTC_MD_ICV_TEST_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/
DMCXW727C_cm33_core0.h25684 #define LTC_MD_ICV_TEST_MASK (0x2U) macro
25687 … (((uint32_t)(((uint32_t)(x)) << LTC_MD_ICV_TEST_SHIFT)) & LTC_MD_ICV_TEST_MASK)
DMCXW727C_cm33_core1.h33985 #define LTC_MD_ICV_TEST_MASK (0x2U) macro
33988 … (((uint32_t)(((uint32_t)(x)) << LTC_MD_ICV_TEST_SHIFT)) & LTC_MD_ICV_TEST_MASK)