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Searched refs:LTC_CTL_IFR_MASK (Results 1 – 15 of 15) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/drivers/ltc/
Dfsl_ltc_edma.c1587 base->CTL &= ~LTC_CTL_IFR_MASK; /* 1 entry */ in ltc_symmetric_process_EDMA()
1667 base->CTL &= ~LTC_CTL_IFR_MASK; in LTC_CreateHandleEDMA()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW31Z4/
DMKW31Z4.h4125 #define LTC_CTL_IFR_MASK (0x200U) macro
4127 …) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFR_SHIFT)) & LTC_CTL_IFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW30Z4/
DMKW30Z4.h4064 #define LTC_CTL_IFR_MASK 0x200u macro
4067 …FR(x) (((uint32_t)(((uint32_t)(x))<<LTC_CTL_IFR_SHIFT))&LTC_CTL_IFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW21Z4/
DMKW21Z4.h4054 #define LTC_CTL_IFR_MASK (0x200U) macro
4056 …) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFR_SHIFT)) & LTC_CTL_IFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW20Z4/
DMKW20Z4.h4064 #define LTC_CTL_IFR_MASK 0x200u macro
4067 …FR(x) (((uint32_t)(((uint32_t)(x))<<LTC_CTL_IFR_SHIFT))&LTC_CTL_IFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW41Z4/
DMKW41Z4.h4125 #define LTC_CTL_IFR_MASK (0x200U) macro
4127 …) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFR_SHIFT)) & LTC_CTL_IFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW40Z4/
DMKW40Z4.h4064 #define LTC_CTL_IFR_MASK 0x200u macro
4067 …FR(x) (((uint32_t)(((uint32_t)(x))<<LTC_CTL_IFR_SHIFT))&LTC_CTL_IFR_MASK)
DMKW40Z4_extension.h12548 #define LTC_RD_CTL_IFR(base) ((LTC_CTL_REG(base) & LTC_CTL_IFR_MASK) >> LTC_CTL_IFR_SHIFT)
12552 #define LTC_WR_CTL_IFR(base, value) (LTC_RMW_CTL(base, LTC_CTL_IFR_MASK, LTC_CTL_IFR(value)))
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h16535 #define LTC_CTL_IFR_MASK (0x200U) macro
16541 …) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFR_SHIFT)) & LTC_CTL_IFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h16591 #define LTC_CTL_IFR_MASK (0x200U) macro
16597 …) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFR_SHIFT)) & LTC_CTL_IFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h16592 #define LTC_CTL_IFR_MASK (0x200U) macro
16598 …) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFR_SHIFT)) & LTC_CTL_IFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/
DMCXW716A.h22705 #define LTC_CTL_IFR_MASK (0x200U) macro
22711 …) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFR_SHIFT)) & LTC_CTL_IFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/
DMCXW716C.h24874 #define LTC_CTL_IFR_MASK (0x200U) macro
24880 …) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFR_SHIFT)) & LTC_CTL_IFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/
DMCXW727C_cm33_core0.h25779 #define LTC_CTL_IFR_MASK (0x200U) macro
25785 …) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFR_SHIFT)) & LTC_CTL_IFR_MASK)
DMCXW727C_cm33_core1.h34080 #define LTC_CTL_IFR_MASK (0x200U) macro
34086 …) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFR_SHIFT)) & LTC_CTL_IFR_MASK)