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Searched refs:LTC_CHAVID_AESVID_MASK (Results 1 – 14 of 14) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MKW31Z4/
DMKW31Z4.h4245 #define LTC_CHAVID_AESVID_MASK (0xF0U) macro
4247 … (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESVID_SHIFT)) & LTC_CHAVID_AESVID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW30Z4/
DMKW30Z4.h4219 #define LTC_CHAVID_AESVID_MASK 0xF0u macro
4222 … (((uint32_t)(((uint32_t)(x))<<LTC_CHAVID_AESVID_SHIFT))&LTC_CHAVID_AESVID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW21Z4/
DMKW21Z4.h4174 #define LTC_CHAVID_AESVID_MASK (0xF0U) macro
4176 … (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESVID_SHIFT)) & LTC_CHAVID_AESVID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW20Z4/
DMKW20Z4.h4219 #define LTC_CHAVID_AESVID_MASK 0xF0u macro
4222 … (((uint32_t)(((uint32_t)(x))<<LTC_CHAVID_AESVID_SHIFT))&LTC_CHAVID_AESVID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW41Z4/
DMKW41Z4.h4245 #define LTC_CHAVID_AESVID_MASK (0xF0U) macro
4247 … (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESVID_SHIFT)) & LTC_CHAVID_AESVID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW40Z4/
DMKW40Z4.h4219 #define LTC_CHAVID_AESVID_MASK 0xF0u macro
4222 … (((uint32_t)(((uint32_t)(x))<<LTC_CHAVID_AESVID_SHIFT))&LTC_CHAVID_AESVID_MASK)
DMKW40Z4_extension.h13342 #define LTC_RD_CHAVID_AESVID(base) ((LTC_CHAVID_REG(base) & LTC_CHAVID_AESVID_MASK) >> LTC_CHAVID_A…
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h16812 #define LTC_CHAVID_AESVID_MASK (0xF0U) macro
16814 … (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESVID_SHIFT)) & LTC_CHAVID_AESVID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h16849 #define LTC_CHAVID_AESVID_MASK (0xF0U) macro
16852 … (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESVID_SHIFT)) & LTC_CHAVID_AESVID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h16850 #define LTC_CHAVID_AESVID_MASK (0xF0U) macro
16853 … (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESVID_SHIFT)) & LTC_CHAVID_AESVID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/
DMCXW716A.h22955 #define LTC_CHAVID_AESVID_MASK (0xF0U) macro
22958 … (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESVID_SHIFT)) & LTC_CHAVID_AESVID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/
DMCXW716C.h25124 #define LTC_CHAVID_AESVID_MASK (0xF0U) macro
25127 … (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESVID_SHIFT)) & LTC_CHAVID_AESVID_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/
DMCXW727C_cm33_core0.h26035 #define LTC_CHAVID_AESVID_MASK (0xF0U) macro
26038 … (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESVID_SHIFT)) & LTC_CHAVID_AESVID_MASK)
DMCXW727C_cm33_core1.h34336 #define LTC_CHAVID_AESVID_MASK (0xF0U) macro
34339 … (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESVID_SHIFT)) & LTC_CHAVID_AESVID_MASK)