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Searched refs:LSR (Results 1 – 25 of 34) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/CMSIS/DSP/Source/TransformFunctions/
Darm_bitreversal2.S195 ADD r8,r0,r8,LSR #1
196 ADD r9,r0,r9,LSR #1
197 ADD r2,r0,r2,LSR #1
198 ADD r12,r0,r12,LSR #1
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Include/
Dcore_armv8mml.h1023 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ member
1180 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ member
1306 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ member
Dcore_cm35p.h1023 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ member
1180 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ member
Dcore_cm7.h1048 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ member
1146 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ member
Dcore_cm33.h1023 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ member
1180 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ member
Dcore_armv81mml.h1107 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ member
1276 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ member
Dcore_armv8mbl.h739 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ member
Dcore_sc300.h755 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ member
Dcore_cm3.h770 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ member
Dcore_cm4.h828 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ member
/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core/Include/
Dcore_cm7.h1057 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ member
1155 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ member
Dcore_cm33.h1031 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ member
1188 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ member
Dcore_cm4.h833 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ member
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_ATP.h101 __I uint32_t LSR; /**< Lock Status Register, offset: 0xFB4 */ member
DS32Z2_RTU_PMC.h149 uint32_t LSR; /**< Lock Status Register, offset: 0xFB4 */ member
/hal_nxp-latest/mcux/mcux-sdk/drivers/smartcard/
Dfsl_smartcard_usim.c514 while ((base->LSR & USIM_LSR_TX_WORKING_MASK) != 0u) in SMARTCARD_USIM_Deinit()
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54607/
DLPC54607.h11020 __I uint32_t LSR; /**< Line Status Register, offset: 0x14 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54S005/
DLPC54S005.h11038 __I uint32_t LSR; /**< Line Status Register, offset: 0x14 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54005/
DLPC54005.h10246 __I uint32_t LSR; /**< Line Status Register, offset: 0x14 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54605/
DLPC54605.h10376 __I uint32_t LSR; /**< Line Status Register, offset: 0x14 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54606/
DLPC54606.h14524 __I uint32_t LSR; /**< Line Status Register, offset: 0x14 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54016/
DLPC54016.h13662 __I uint32_t LSR; /**< Line Status Register, offset: 0x14 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54616/
DLPC54616.h14599 __I uint32_t LSR; /**< Line Status Register, offset: 0x14 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54018M/
DLPC54018M.h15139 __I uint32_t LSR; /**< Line Status Register, offset: 0x14 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC54628/
DLPC54628.h15445 __I uint32_t LSR; /**< Line Status Register, offset: 0x14 */ member

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