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Searched refs:LSIO__LPCG_QSPI0_BASE (Results 1 – 25 of 34) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX3/drivers/
Dfsl_clock.h345 kCLOCK_LSIO_Flexspi0 = LPCG_TUPLE(SC_R_FSPI_0, LSIO__LPCG_QSPI0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX6/drivers/
Dfsl_clock.h345 kCLOCK_LSIO_Flexspi0 = LPCG_TUPLE(SC_R_FSPI_0, LSIO__LPCG_QSPI0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX2/drivers/
Dfsl_clock.h345 kCLOCK_LSIO_Flexspi0 = LPCG_TUPLE(SC_R_FSPI_0, LSIO__LPCG_QSPI0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX6/drivers/
Dfsl_clock.h345 kCLOCK_LSIO_Flexspi0 = LPCG_TUPLE(SC_R_FSPI_0, LSIO__LPCG_QSPI0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX5/drivers/
Dfsl_clock.h345 kCLOCK_LSIO_Flexspi0 = LPCG_TUPLE(SC_R_FSPI_0, LSIO__LPCG_QSPI0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX1/drivers/
Dfsl_clock.h345 kCLOCK_LSIO_Flexspi0 = LPCG_TUPLE(SC_R_FSPI_0, LSIO__LPCG_QSPI0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX4/drivers/
Dfsl_clock.h345 kCLOCK_LSIO_Flexspi0 = LPCG_TUPLE(SC_R_FSPI_0, LSIO__LPCG_QSPI0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX2/drivers/
Dfsl_clock.h345 kCLOCK_LSIO_Flexspi0 = LPCG_TUPLE(SC_R_FSPI_0, LSIO__LPCG_QSPI0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX3/drivers/
Dfsl_clock.h345 kCLOCK_LSIO_Flexspi0 = LPCG_TUPLE(SC_R_FSPI_0, LSIO__LPCG_QSPI0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX4/drivers/
Dfsl_clock.h345 kCLOCK_LSIO_Flexspi0 = LPCG_TUPLE(SC_R_FSPI_0, LSIO__LPCG_QSPI0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX5/drivers/
Dfsl_clock.h345 kCLOCK_LSIO_Flexspi0 = LPCG_TUPLE(SC_R_FSPI_0, LSIO__LPCG_QSPI0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX5/drivers/
Dfsl_clock.h345 kCLOCK_LSIO_Flexspi0 = LPCG_TUPLE(SC_R_FSPI_0, LSIO__LPCG_QSPI0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX6/drivers/
Dfsl_clock.h345 kCLOCK_LSIO_Flexspi0 = LPCG_TUPLE(SC_R_FSPI_0, LSIO__LPCG_QSPI0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX1/drivers/
Dfsl_clock.h345 kCLOCK_LSIO_Flexspi0 = LPCG_TUPLE(SC_R_FSPI_0, LSIO__LPCG_QSPI0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/drivers/
Dfsl_clock.h341 kCLOCK_LSIO_Flexspi0 = LPCG_TUPLE(SC_R_FSPI_0, LSIO__LPCG_QSPI0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_ca53.h69335 #define LSIO__LPCG_QSPI0_BASE (0x5D520000u) macro
69337 #define LSIO__LPCG_QSPI0 ((LSIO_LPCG_QSPI0_Type *)LSIO__LPCG_QSPI0_BASE)
69339 #define LSIO_LPCG_QSPI0_BASE_ADDRS { LSIO__LPCG_QSPI0_BASE }
DMIMX8QM6_dsp.h73354 #define LSIO__LPCG_QSPI0_BASE (0x5D520000u) macro
73356 #define LSIO__LPCG_QSPI0 ((LSIO_LPCG_QSPI0_Type *)LSIO__LPCG_QSPI0_BASE)
73358 #define LSIO_LPCG_QSPI0_BASE_ADDRS { LSIO__LPCG_QSPI0_BASE }
DMIMX8QM6_cm4_core1.h82312 #define LSIO__LPCG_QSPI0_BASE (0x5D520000u) macro
82314 #define LSIO__LPCG_QSPI0 ((LSIO_LPCG_QSPI0_Type *)LSIO__LPCG_QSPI0_BASE)
82316 #define LSIO_LPCG_QSPI0_BASE_ADDRS { LSIO__LPCG_QSPI0_BASE }
DMIMX8QM6_cm4_core0.h82312 #define LSIO__LPCG_QSPI0_BASE (0x5D520000u) macro
82314 #define LSIO__LPCG_QSPI0 ((LSIO_LPCG_QSPI0_Type *)LSIO__LPCG_QSPI0_BASE)
82316 #define LSIO_LPCG_QSPI0_BASE_ADDRS { LSIO__LPCG_QSPI0_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX2/
DMIMX8QX2_cm4.h89514 #define LSIO__LPCG_QSPI0_BASE (0x5D520000u) macro
89516 #define LSIO__LPCG_QSPI0 ((LSIO_LPCG_QSPI0_Type *)LSIO__LPCG_QSPI0_BASE)
89518 #define LSIO_LPCG_QSPI0_BASE_ADDRS { LSIO__LPCG_QSPI0_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX1/
DMIMX8QX1_cm4.h89514 #define LSIO__LPCG_QSPI0_BASE (0x5D520000u) macro
89516 #define LSIO__LPCG_QSPI0 ((LSIO_LPCG_QSPI0_Type *)LSIO__LPCG_QSPI0_BASE)
89518 #define LSIO_LPCG_QSPI0_BASE_ADDRS { LSIO__LPCG_QSPI0_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX1/
DMIMX8DX1_cm4.h89514 #define LSIO__LPCG_QSPI0_BASE (0x5D520000u) macro
89516 #define LSIO__LPCG_QSPI0 ((LSIO_LPCG_QSPI0_Type *)LSIO__LPCG_QSPI0_BASE)
89518 #define LSIO_LPCG_QSPI0_BASE_ADDRS { LSIO__LPCG_QSPI0_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX2/
DMIMX8DX2_cm4.h89514 #define LSIO__LPCG_QSPI0_BASE (0x5D520000u) macro
89516 #define LSIO__LPCG_QSPI0 ((LSIO_LPCG_QSPI0_Type *)LSIO__LPCG_QSPI0_BASE)
89518 #define LSIO_LPCG_QSPI0_BASE_ADDRS { LSIO__LPCG_QSPI0_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX3/
DMIMX8QX3_cm4.h119323 #define LSIO__LPCG_QSPI0_BASE (0x5D520000u) macro
119325 #define LSIO__LPCG_QSPI0 ((LSIO_LPCG_QSPI0_Type *)LSIO__LPCG_QSPI0_BASE)
119327 #define LSIO_LPCG_QSPI0_BASE_ADDRS { LSIO__LPCG_QSPI0_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX4/
DMIMX8DX4_cm4.h119323 #define LSIO__LPCG_QSPI0_BASE (0x5D520000u) macro
119325 #define LSIO__LPCG_QSPI0 ((LSIO_LPCG_QSPI0_Type *)LSIO__LPCG_QSPI0_BASE)
119327 #define LSIO_LPCG_QSPI0_BASE_ADDRS { LSIO__LPCG_QSPI0_BASE }

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