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Searched refs:LSIO__LPCG_GPT1_BASE (Results 1 – 25 of 34) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX3/drivers/
Dfsl_clock.h312 kCLOCK_LSIO_Gpt1 = LPCG_TUPLE(SC_R_GPT_1, LSIO__LPCG_GPT1_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX6/drivers/
Dfsl_clock.h312 kCLOCK_LSIO_Gpt1 = LPCG_TUPLE(SC_R_GPT_1, LSIO__LPCG_GPT1_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX2/drivers/
Dfsl_clock.h312 kCLOCK_LSIO_Gpt1 = LPCG_TUPLE(SC_R_GPT_1, LSIO__LPCG_GPT1_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX6/drivers/
Dfsl_clock.h312 kCLOCK_LSIO_Gpt1 = LPCG_TUPLE(SC_R_GPT_1, LSIO__LPCG_GPT1_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX5/drivers/
Dfsl_clock.h312 kCLOCK_LSIO_Gpt1 = LPCG_TUPLE(SC_R_GPT_1, LSIO__LPCG_GPT1_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX1/drivers/
Dfsl_clock.h312 kCLOCK_LSIO_Gpt1 = LPCG_TUPLE(SC_R_GPT_1, LSIO__LPCG_GPT1_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX4/drivers/
Dfsl_clock.h312 kCLOCK_LSIO_Gpt1 = LPCG_TUPLE(SC_R_GPT_1, LSIO__LPCG_GPT1_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX2/drivers/
Dfsl_clock.h312 kCLOCK_LSIO_Gpt1 = LPCG_TUPLE(SC_R_GPT_1, LSIO__LPCG_GPT1_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX3/drivers/
Dfsl_clock.h312 kCLOCK_LSIO_Gpt1 = LPCG_TUPLE(SC_R_GPT_1, LSIO__LPCG_GPT1_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX4/drivers/
Dfsl_clock.h312 kCLOCK_LSIO_Gpt1 = LPCG_TUPLE(SC_R_GPT_1, LSIO__LPCG_GPT1_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX5/drivers/
Dfsl_clock.h312 kCLOCK_LSIO_Gpt1 = LPCG_TUPLE(SC_R_GPT_1, LSIO__LPCG_GPT1_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX5/drivers/
Dfsl_clock.h312 kCLOCK_LSIO_Gpt1 = LPCG_TUPLE(SC_R_GPT_1, LSIO__LPCG_GPT1_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX6/drivers/
Dfsl_clock.h312 kCLOCK_LSIO_Gpt1 = LPCG_TUPLE(SC_R_GPT_1, LSIO__LPCG_GPT1_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX1/drivers/
Dfsl_clock.h312 kCLOCK_LSIO_Gpt1 = LPCG_TUPLE(SC_R_GPT_1, LSIO__LPCG_GPT1_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/drivers/
Dfsl_clock.h314 kCLOCK_LSIO_Gpt1 = LPCG_TUPLE(SC_R_GPT_1, LSIO__LPCG_GPT1_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_ca53.h64800 #define LSIO__LPCG_GPT1_BASE (0x5D550000u) macro
64802 #define LSIO__LPCG_GPT1 ((LSIO_LPCG_GPT1_Type *)LSIO__LPCG_GPT1_BASE)
64804 #define LSIO_LPCG_GPT1_BASE_ADDRS { LSIO__LPCG_GPT1_BASE }
DMIMX8QM6_dsp.h68819 #define LSIO__LPCG_GPT1_BASE (0x5D550000u) macro
68821 #define LSIO__LPCG_GPT1 ((LSIO_LPCG_GPT1_Type *)LSIO__LPCG_GPT1_BASE)
68823 #define LSIO_LPCG_GPT1_BASE_ADDRS { LSIO__LPCG_GPT1_BASE }
DMIMX8QM6_cm4_core1.h79270 #define LSIO__LPCG_GPT1_BASE (0x5D550000u) macro
79272 #define LSIO__LPCG_GPT1 ((LSIO_LPCG_GPT1_Type *)LSIO__LPCG_GPT1_BASE)
79274 #define LSIO_LPCG_GPT1_BASE_ADDRS { LSIO__LPCG_GPT1_BASE }
DMIMX8QM6_cm4_core0.h79270 #define LSIO__LPCG_GPT1_BASE (0x5D550000u) macro
79272 #define LSIO__LPCG_GPT1 ((LSIO_LPCG_GPT1_Type *)LSIO__LPCG_GPT1_BASE)
79274 #define LSIO_LPCG_GPT1_BASE_ADDRS { LSIO__LPCG_GPT1_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX2/
DMIMX8QX2_cm4.h85142 #define LSIO__LPCG_GPT1_BASE (0x5D550000u) macro
85144 #define LSIO__LPCG_GPT1 ((LSIO_LPCG_GPT1_Type *)LSIO__LPCG_GPT1_BASE)
85146 #define LSIO_LPCG_GPT1_BASE_ADDRS { LSIO__LPCG_GPT1_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX1/
DMIMX8QX1_cm4.h85142 #define LSIO__LPCG_GPT1_BASE (0x5D550000u) macro
85144 #define LSIO__LPCG_GPT1 ((LSIO_LPCG_GPT1_Type *)LSIO__LPCG_GPT1_BASE)
85146 #define LSIO_LPCG_GPT1_BASE_ADDRS { LSIO__LPCG_GPT1_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX1/
DMIMX8DX1_cm4.h85142 #define LSIO__LPCG_GPT1_BASE (0x5D550000u) macro
85144 #define LSIO__LPCG_GPT1 ((LSIO_LPCG_GPT1_Type *)LSIO__LPCG_GPT1_BASE)
85146 #define LSIO_LPCG_GPT1_BASE_ADDRS { LSIO__LPCG_GPT1_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX2/
DMIMX8DX2_cm4.h85142 #define LSIO__LPCG_GPT1_BASE (0x5D550000u) macro
85144 #define LSIO__LPCG_GPT1 ((LSIO_LPCG_GPT1_Type *)LSIO__LPCG_GPT1_BASE)
85146 #define LSIO_LPCG_GPT1_BASE_ADDRS { LSIO__LPCG_GPT1_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX3/
DMIMX8QX3_cm4.h114951 #define LSIO__LPCG_GPT1_BASE (0x5D550000u) macro
114953 #define LSIO__LPCG_GPT1 ((LSIO_LPCG_GPT1_Type *)LSIO__LPCG_GPT1_BASE)
114955 #define LSIO_LPCG_GPT1_BASE_ADDRS { LSIO__LPCG_GPT1_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX4/
DMIMX8DX4_cm4.h114951 #define LSIO__LPCG_GPT1_BASE (0x5D550000u) macro
114953 #define LSIO__LPCG_GPT1 ((LSIO_LPCG_GPT1_Type *)LSIO__LPCG_GPT1_BASE)
114955 #define LSIO_LPCG_GPT1_BASE_ADDRS { LSIO__LPCG_GPT1_BASE }

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