Home
last modified time | relevance | path

Searched refs:LSIO__LPCG_GPIO0_BASE (Results 1 – 25 of 34) sorted by relevance

12

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX3/drivers/
Dfsl_clock.h297 kCLOCK_LSIO_Gpio0 = LPCG_TUPLE(SC_R_GPIO_0, LSIO__LPCG_GPIO0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX6/drivers/
Dfsl_clock.h297 kCLOCK_LSIO_Gpio0 = LPCG_TUPLE(SC_R_GPIO_0, LSIO__LPCG_GPIO0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX2/drivers/
Dfsl_clock.h297 kCLOCK_LSIO_Gpio0 = LPCG_TUPLE(SC_R_GPIO_0, LSIO__LPCG_GPIO0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX6/drivers/
Dfsl_clock.h297 kCLOCK_LSIO_Gpio0 = LPCG_TUPLE(SC_R_GPIO_0, LSIO__LPCG_GPIO0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX5/drivers/
Dfsl_clock.h297 kCLOCK_LSIO_Gpio0 = LPCG_TUPLE(SC_R_GPIO_0, LSIO__LPCG_GPIO0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX1/drivers/
Dfsl_clock.h297 kCLOCK_LSIO_Gpio0 = LPCG_TUPLE(SC_R_GPIO_0, LSIO__LPCG_GPIO0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX4/drivers/
Dfsl_clock.h297 kCLOCK_LSIO_Gpio0 = LPCG_TUPLE(SC_R_GPIO_0, LSIO__LPCG_GPIO0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX2/drivers/
Dfsl_clock.h297 kCLOCK_LSIO_Gpio0 = LPCG_TUPLE(SC_R_GPIO_0, LSIO__LPCG_GPIO0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX3/drivers/
Dfsl_clock.h297 kCLOCK_LSIO_Gpio0 = LPCG_TUPLE(SC_R_GPIO_0, LSIO__LPCG_GPIO0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX4/drivers/
Dfsl_clock.h297 kCLOCK_LSIO_Gpio0 = LPCG_TUPLE(SC_R_GPIO_0, LSIO__LPCG_GPIO0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX5/drivers/
Dfsl_clock.h297 kCLOCK_LSIO_Gpio0 = LPCG_TUPLE(SC_R_GPIO_0, LSIO__LPCG_GPIO0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX5/drivers/
Dfsl_clock.h297 kCLOCK_LSIO_Gpio0 = LPCG_TUPLE(SC_R_GPIO_0, LSIO__LPCG_GPIO0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX6/drivers/
Dfsl_clock.h297 kCLOCK_LSIO_Gpio0 = LPCG_TUPLE(SC_R_GPIO_0, LSIO__LPCG_GPIO0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX1/drivers/
Dfsl_clock.h297 kCLOCK_LSIO_Gpio0 = LPCG_TUPLE(SC_R_GPIO_0, LSIO__LPCG_GPIO0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/drivers/
Dfsl_clock.h299 kCLOCK_LSIO_Gpio0 = LPCG_TUPLE(SC_R_GPIO_0, LSIO__LPCG_GPIO0_BASE),
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_ca53.h63802 #define LSIO__LPCG_GPIO0_BASE (0x5D480000u) macro
63804 #define LSIO__LPCG_GPIO0 ((LSIO_LPCG_GPIO0_Type *)LSIO__LPCG_GPIO0_BASE)
63806 #define LSIO_LPCG_GPIO0_BASE_ADDRS { LSIO__LPCG_GPIO0_BASE }
DMIMX8QM6_dsp.h67821 #define LSIO__LPCG_GPIO0_BASE (0x5D480000u) macro
67823 #define LSIO__LPCG_GPIO0 ((LSIO_LPCG_GPIO0_Type *)LSIO__LPCG_GPIO0_BASE)
67825 #define LSIO_LPCG_GPIO0_BASE_ADDRS { LSIO__LPCG_GPIO0_BASE }
DMIMX8QM6_cm4_core1.h78556 #define LSIO__LPCG_GPIO0_BASE (0x5D480000u) macro
78558 #define LSIO__LPCG_GPIO0 ((LSIO_LPCG_GPIO0_Type *)LSIO__LPCG_GPIO0_BASE)
78560 #define LSIO_LPCG_GPIO0_BASE_ADDRS { LSIO__LPCG_GPIO0_BASE }
DMIMX8QM6_cm4_core0.h78556 #define LSIO__LPCG_GPIO0_BASE (0x5D480000u) macro
78558 #define LSIO__LPCG_GPIO0 ((LSIO_LPCG_GPIO0_Type *)LSIO__LPCG_GPIO0_BASE)
78560 #define LSIO_LPCG_GPIO0_BASE_ADDRS { LSIO__LPCG_GPIO0_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX2/
DMIMX8QX2_cm4.h84176 #define LSIO__LPCG_GPIO0_BASE (0x5D480000u) macro
84178 #define LSIO__LPCG_GPIO0 ((LSIO_LPCG_GPIO0_Type *)LSIO__LPCG_GPIO0_BASE)
84180 #define LSIO_LPCG_GPIO0_BASE_ADDRS { LSIO__LPCG_GPIO0_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX1/
DMIMX8QX1_cm4.h84176 #define LSIO__LPCG_GPIO0_BASE (0x5D480000u) macro
84178 #define LSIO__LPCG_GPIO0 ((LSIO_LPCG_GPIO0_Type *)LSIO__LPCG_GPIO0_BASE)
84180 #define LSIO_LPCG_GPIO0_BASE_ADDRS { LSIO__LPCG_GPIO0_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX1/
DMIMX8DX1_cm4.h84176 #define LSIO__LPCG_GPIO0_BASE (0x5D480000u) macro
84178 #define LSIO__LPCG_GPIO0 ((LSIO_LPCG_GPIO0_Type *)LSIO__LPCG_GPIO0_BASE)
84180 #define LSIO_LPCG_GPIO0_BASE_ADDRS { LSIO__LPCG_GPIO0_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX2/
DMIMX8DX2_cm4.h84176 #define LSIO__LPCG_GPIO0_BASE (0x5D480000u) macro
84178 #define LSIO__LPCG_GPIO0 ((LSIO_LPCG_GPIO0_Type *)LSIO__LPCG_GPIO0_BASE)
84180 #define LSIO_LPCG_GPIO0_BASE_ADDRS { LSIO__LPCG_GPIO0_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX3/
DMIMX8QX3_cm4.h113985 #define LSIO__LPCG_GPIO0_BASE (0x5D480000u) macro
113987 #define LSIO__LPCG_GPIO0 ((LSIO_LPCG_GPIO0_Type *)LSIO__LPCG_GPIO0_BASE)
113989 #define LSIO_LPCG_GPIO0_BASE_ADDRS { LSIO__LPCG_GPIO0_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX4/
DMIMX8DX4_cm4.h113985 #define LSIO__LPCG_GPIO0_BASE (0x5D480000u) macro
113987 #define LSIO__LPCG_GPIO0 ((LSIO_LPCG_GPIO0_Type *)LSIO__LPCG_GPIO0_BASE)
113989 #define LSIO_LPCG_GPIO0_BASE_ADDRS { LSIO__LPCG_GPIO0_BASE }

12