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Searched refs:LPSPI_CFGR1_PCSPOL_MASK (Results 1 – 25 of 132) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K116_LPSPI.h345 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
348 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
DS32K148_LPSPI.h353 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
356 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
DS32K118_LPSPI.h349 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
352 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
DS32K144_LPSPI.h353 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
356 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
DS32K146_LPSPI.h353 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
356 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
DS32K142W_LPSPI.h353 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
356 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
DS32K142_LPSPI.h349 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
352 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
DS32K144W_LPSPI.h353 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
356 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_LPSPI.h385 #define LPSPI_CFGR1_PCSPOL_MASK (0xFF00U) /* Merged from fields with different po… macro
388 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) /* Merg…
/hal_nxp-latest/mcux/mcux-sdk/drivers/lpflexcomm/lpspi/
Dfsl_lpspi.h847 base->CFGR1 = (base->CFGR1 & ~LPSPI_CFGR1_PCSPOL_MASK) | LPSPI_CFGR1_PCSPOL(~mask); in LPSPI_SetAllPcsPolarity()
/hal_nxp-latest/mcux/mcux-sdk/drivers/lpspi/
Dfsl_lpspi.h893 base->CFGR1 = (base->CFGR1 & ~LPSPI_CFGR1_PCSPOL_MASK) | LPSPI_CFGR1_PCSPOL(~mask); in LPSPI_SetAllPcsPolarity()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/
DMKE14Z4.h5221 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
5227 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/
DMKE15Z4.h5222 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
5228 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/
DMKE16Z4.h5220 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
5226 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z7/
DMKE12Z7.h8249 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
8255 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/
DMKE12Z9.h8137 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
8140 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/
DMKE17Z7.h8253 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
8259 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/
DMKE13Z7.h8251 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
8257 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/
DMKE14Z7.h7785 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
7791 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/
DMKE17Z9.h8139 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
8142 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/
DMKE15Z7.h7787 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
7793 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/
DMKE13Z9.h8138 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
8141 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/
DMKE14F16.h10433 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
10439 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h9476 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
9482 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h9476 #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) macro
9482 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)

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