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Searched refs:LPSPI_CFGR1_MATCFG_MASK (Results 1 – 25 of 130) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K116_LPSPI.h350 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
353 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
DS32K148_LPSPI.h358 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
361 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
DS32K118_LPSPI.h354 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
357 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
DS32K144_LPSPI.h358 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
361 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
DS32K146_LPSPI.h358 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
361 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
DS32K142W_LPSPI.h358 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
361 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
DS32K142_LPSPI.h354 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
357 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
DS32K144W_LPSPI.h358 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
361 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_LPSPI.h390 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
393 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/
DMKE14Z4.h5228 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
5240 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/
DMKE15Z4.h5229 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
5241 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/
DMKE16Z4.h5227 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
5239 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z7/
DMKE12Z7.h8257 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
8269 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/
DMKE12Z9.h8142 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
8154 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/
DMKE17Z7.h8261 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
8273 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/
DMKE13Z7.h8259 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
8271 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/
DMKE14Z7.h7792 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
7804 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/
DMKE17Z9.h8144 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
8156 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/
DMKE15Z7.h7794 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
7806 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/
DMKE13Z9.h8143 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
8155 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/
DMKE14F16.h10441 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
10453 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h9484 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
9496 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h9484 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
9496 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/
DMKE18F16.h11445 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
11457 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/
DMKE16F16.h11440 #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) macro
11452 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)

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