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Searched refs:LPSPI_CFGR1_MASTER_MASK (Results 1 – 25 of 132) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/lpflexcomm/lpspi/
Dfsl_lpspi.h755 base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode); in LPSPI_SetMasterSlaveMode()
800 return (bool)((base->CFGR1) & LPSPI_CFGR1_MASTER_MASK); in LPSPI_IsMaster()
/hal_nxp-latest/mcux/mcux-sdk/drivers/lpspi/
Dfsl_lpspi.h768 base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode); in LPSPI_SetMasterSlaveMode()
813 return (bool)((base->CFGR1) & LPSPI_CFGR1_MASTER_MASK); in LPSPI_IsMaster()
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K116_LPSPI.h325 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
328 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
DS32K148_LPSPI.h333 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
336 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
DS32K118_LPSPI.h329 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
332 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
DS32K144_LPSPI.h333 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
336 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
DS32K146_LPSPI.h333 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
336 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
DS32K142W_LPSPI.h333 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
336 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
DS32K142_LPSPI.h329 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
332 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
DS32K144W_LPSPI.h333 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
336 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_LPSPI.h360 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
363 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/
DMKE14Z4.h5193 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
5199 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/
DMKE15Z4.h5194 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
5200 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/
DMKE16Z4.h5192 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
5198 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z7/
DMKE12Z7.h8217 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
8223 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/
DMKE12Z9.h8105 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
8111 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/
DMKE17Z7.h8221 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
8227 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/
DMKE13Z7.h8219 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
8225 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/
DMKE14Z7.h7757 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
7763 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/
DMKE17Z9.h8107 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
8113 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/
DMKE15Z7.h7759 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
7765 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/
DMKE13Z9.h8106 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
8112 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/
DMKE14F16.h10401 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
10407 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h9444 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
9450 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h9444 #define LPSPI_CFGR1_MASTER_MASK (0x1U) macro
9450 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)

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