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Searched refs:LPSPI_CFGR0_HRPOL_MASK (Results 1 – 25 of 113) sorted by relevance

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/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K116_LPSPI.h301 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
304 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
DS32K148_LPSPI.h309 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
312 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
DS32K118_LPSPI.h305 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
308 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
DS32K144_LPSPI.h309 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
312 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
DS32K146_LPSPI.h309 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
312 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
DS32K142W_LPSPI.h309 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
312 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
DS32K142_LPSPI.h305 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
308 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
DS32K144W_LPSPI.h309 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
312 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_LPSPI.h331 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
334 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/
DMKE14Z4.h5161 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
5167 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/
DMKE15Z4.h5162 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
5168 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/
DMKE16Z4.h5160 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
5166 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z7/
DMKE12Z7.h8181 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
8187 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/
DMKE12Z9.h8069 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
8075 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/
DMKE17Z7.h8185 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
8191 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/
DMKE13Z7.h8183 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
8189 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/
DMKE14Z7.h7725 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
7731 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/
DMKE17Z9.h8071 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
8077 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/
DMKE15Z7.h7727 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
7733 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/
DMKE13Z9.h8070 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
8076 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/
DMKE14F16.h10365 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
10371 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h9408 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
9414 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h9408 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
9414 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/
DMKE18F16.h11369 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
11375 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/
DMKE16F16.h11364 #define LPSPI_CFGR0_HRPOL_MASK (0x2U) macro
11370 … (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK)

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