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Searched refs:LPM_CSR1 (Results 1 – 14 of 14) sorted by relevance

/hal_nxp-latest/mcux/middleware/mcux-sdk-middleware-usb/device/
Dusb_device_ehci.c227 ehciState->registerNcBase->LPM_CSR1 |= USBNC_LPM_CSR1_LPM_DEV_RES_MASK; in USB_DeviceEhciSetDefaultState()
1032 (uint8_t)((ehciState->registerNcBase->LPM_CSR1 & USBNC_LPM_CSR1_LPM_DEV_RWKENRCVD_MASK) >>
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h57269 …__IO uint32_t LPM_CSR1; /**< USB LPM Control and Status 1, offset: 0xA4 */ member
DMIMXRT735S_cm33_core1.h57331 …__IO uint32_t LPM_CSR1; /**< USB LPM Control and Status 1, offset: 0xA4 */ member
DMIMXRT735S_ezhv.h86010 …__IO uint32_t LPM_CSR1; /**< USB LPM Control and Status 1, offset: 0xA4 */ member
DMIMXRT735S_cm33_core0.h81239 …__IO uint32_t LPM_CSR1; /**< USB LPM Control and Status 1, offset: 0xA4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h60554 …__IO uint32_t LPM_CSR1; /**< USB LPM Control and Status 1, offset: 0xA4 */ member
DMIMXRT758S_hifi1.h60490 …__IO uint32_t LPM_CSR1; /**< USB LPM Control and Status 1, offset: 0xA4 */ member
DMIMXRT758S_cm33_core0.h84464 …__IO uint32_t LPM_CSR1; /**< USB LPM Control and Status 1, offset: 0xA4 */ member
DMIMXRT758S_ezhv.h89155 …__IO uint32_t LPM_CSR1; /**< USB LPM Control and Status 1, offset: 0xA4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h60490 …__IO uint32_t LPM_CSR1; /**< USB LPM Control and Status 1, offset: 0xA4 */ member
DMIMXRT798S_cm33_core1.h60554 …__IO uint32_t LPM_CSR1; /**< USB LPM Control and Status 1, offset: 0xA4 */ member
DMIMXRT798S_hifi4.h84375 …__IO uint32_t LPM_CSR1; /**< USB LPM Control and Status 1, offset: 0xA4 */ member
DMIMXRT798S_cm33_core0.h84464 …__IO uint32_t LPM_CSR1; /**< USB LPM Control and Status 1, offset: 0xA4 */ member
DMIMXRT798S_ezhv.h89179 …__IO uint32_t LPM_CSR1; /**< USB LPM Control and Status 1, offset: 0xA4 */ member