Home
last modified time | relevance | path

Searched refs:LPIT_CVAL_TMR_CUR_VAL_MASK (Results 1 – 25 of 65) sorted by relevance

123

/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/
DMKE14Z4.h4783 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
4787 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/
DMKE15Z4.h4784 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
4788 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/
DMKE16Z4.h4782 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
4786 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z7/
DMKE12Z7.h7763 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
7767 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/
DMKE12Z9.h7657 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
7660 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/
DMKE17Z7.h7767 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
7771 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/
DMKE13Z7.h7765 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
7769 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/
DMKE14Z7.h7347 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
7351 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/
DMKE17Z9.h7659 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
7662 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/
DMKE15Z7.h7349 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
7353 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/
DMKE13Z9.h7658 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
7661 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/
DMKE14F16.h9947 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
9951 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h8995 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
8998 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h8995 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
8998 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/
DMKE18F16.h10951 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
10955 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/
DMKE16F16.h10946 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
10950 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/
DK32L3A60_cm4.h12505 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
12508 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
DK32L3A60_cm0plus.h11797 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
11800 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h14443 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
14446 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h14444 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
14447 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/
DMCXW716A.h20378 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
20381 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/
DMCXW716C.h22547 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
22550 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/
DMCXW727C_cm33_core0.h23411 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
23414 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
DMCXW727C_cm33_core1.h31719 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
31722 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_ca53.h61920 #define LPIT_CVAL_TMR_CUR_VAL_MASK (0xFFFFFFFFU) macro
61923 … (((uint32_t)(((uint32_t)(x)) << LPIT_CVAL_TMR_CUR_VAL_SHIFT)) & LPIT_CVAL_TMR_CUR_VAL_MASK)

123