1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_LPI2C.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_LPI2C 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_LPI2C_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_LPI2C_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LPI2C Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LPI2C - Size of Registers Arrays */ 72 #define LPI2C_MTCBR_COUNT 128u 73 #define LPI2C_MTDBR_COUNT 256u 74 75 /** LPI2C - Register Layout Typedef */ 76 typedef struct { 77 __I uint32_t VERID; /**< Version ID, offset: 0x0 */ 78 __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ 79 uint8_t RESERVED_0[8]; 80 __IO uint32_t MCR; /**< Controller Control, offset: 0x10 */ 81 __IO uint32_t MSR; /**< Controller Status, offset: 0x14 */ 82 __IO uint32_t MIER; /**< Controller Interrupt Enable, offset: 0x18 */ 83 __IO uint32_t MDER; /**< Controller DMA Enable, offset: 0x1C */ 84 __IO uint32_t MCFGR0; /**< Controller Configuration 0, offset: 0x20 */ 85 __IO uint32_t MCFGR1; /**< Controller Configuration 1, offset: 0x24 */ 86 __IO uint32_t MCFGR2; /**< Controller Configuration 2, offset: 0x28 */ 87 __IO uint32_t MCFGR3; /**< Controller Configuration 3, offset: 0x2C */ 88 uint8_t RESERVED_1[16]; 89 __IO uint32_t MDMR; /**< Controller Data Match, offset: 0x40 */ 90 uint8_t RESERVED_2[4]; 91 __IO uint32_t MCCR0; /**< Controller Clock Configuration 0, offset: 0x48 */ 92 uint8_t RESERVED_3[4]; 93 __IO uint32_t MCCR1; /**< Controller Clock Configuration 1, offset: 0x50 */ 94 uint8_t RESERVED_4[4]; 95 __IO uint32_t MFCR; /**< Controller FIFO Control, offset: 0x58 */ 96 __I uint32_t MFSR; /**< Controller FIFO Status, offset: 0x5C */ 97 __O uint32_t MTDR; /**< Controller Transmit Data, offset: 0x60 */ 98 uint8_t RESERVED_5[12]; 99 __I uint32_t MRDR; /**< Controller Receive Data, offset: 0x70 */ 100 uint8_t RESERVED_6[4]; 101 __I uint32_t MRDROR; /**< Controller Receive Data Read Only, offset: 0x78 */ 102 uint8_t RESERVED_7[148]; 103 __IO uint32_t SCR; /**< Target Control, offset: 0x110 */ 104 __IO uint32_t SSR; /**< Target Status, offset: 0x114 */ 105 __IO uint32_t SIER; /**< Target Interrupt Enable, offset: 0x118 */ 106 __IO uint32_t SDER; /**< Target DMA Enable, offset: 0x11C */ 107 __IO uint32_t SCFGR0; /**< Target Configuration 0, offset: 0x120 */ 108 __IO uint32_t SCFGR1; /**< Target Configuration 1, offset: 0x124 */ 109 __IO uint32_t SCFGR2; /**< Target Configuration 2, offset: 0x128 */ 110 uint8_t RESERVED_8[20]; 111 __IO uint32_t SAMR; /**< Target Address Match, offset: 0x140 */ 112 uint8_t RESERVED_9[12]; 113 __I uint32_t SASR; /**< Target Address Status, offset: 0x150 */ 114 __IO uint32_t STAR; /**< Target Transmit ACK, offset: 0x154 */ 115 uint8_t RESERVED_10[8]; 116 __O uint32_t STDR; /**< Target Transmit Data, offset: 0x160 */ 117 uint8_t RESERVED_11[12]; 118 __I uint32_t SRDR; /**< Target Receive Data, offset: 0x170 */ 119 uint8_t RESERVED_12[4]; 120 __I uint32_t SRDROR; /**< Target Receive Data Read Only, offset: 0x178 */ 121 uint8_t RESERVED_13[132]; 122 __O uint32_t MTCBR[LPI2C_MTCBR_COUNT]; /**< Controller Transmit Command Burst, array offset: 0x200, array step: 0x4 */ 123 __O uint32_t MTDBR[LPI2C_MTDBR_COUNT]; /**< Transmit Data Burst, array offset: 0x400, array step: 0x4 */ 124 } LPI2C_Type, *LPI2C_MemMapPtr; 125 126 /** Number of instances of the LPI2C module. */ 127 #define LPI2C_INSTANCE_COUNT (2u) 128 129 /* LPI2C - Peripheral instance base addresses */ 130 /** Peripheral LPI2C_1 base address */ 131 #define IP_LPI2C_1_BASE (0x409D0000u) 132 /** Peripheral LPI2C_1 base pointer */ 133 #define IP_LPI2C_1 ((LPI2C_Type *)IP_LPI2C_1_BASE) 134 /** Peripheral LPI2C_2 base address */ 135 #define IP_LPI2C_2_BASE (0x421D0000u) 136 /** Peripheral LPI2C_2 base pointer */ 137 #define IP_LPI2C_2 ((LPI2C_Type *)IP_LPI2C_2_BASE) 138 /** Array initializer of LPI2C peripheral base addresses */ 139 #define IP_LPI2C_BASE_ADDRS { IP_LPI2C_1_BASE, IP_LPI2C_2_BASE } 140 /** Array initializer of LPI2C peripheral base pointers */ 141 #define IP_LPI2C_BASE_PTRS { IP_LPI2C_1, IP_LPI2C_2 } 142 143 /* ---------------------------------------------------------------------------- 144 -- LPI2C Register Masks 145 ---------------------------------------------------------------------------- */ 146 147 /*! 148 * @addtogroup LPI2C_Register_Masks LPI2C Register Masks 149 * @{ 150 */ 151 152 /*! @name VERID - Version ID */ 153 /*! @{ */ 154 155 #define LPI2C_VERID_FEATURE_MASK (0xFFFFU) 156 #define LPI2C_VERID_FEATURE_SHIFT (0U) 157 #define LPI2C_VERID_FEATURE_WIDTH (16U) 158 #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) 159 160 #define LPI2C_VERID_MINOR_MASK (0xFF0000U) 161 #define LPI2C_VERID_MINOR_SHIFT (16U) 162 #define LPI2C_VERID_MINOR_WIDTH (8U) 163 #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) 164 165 #define LPI2C_VERID_MAJOR_MASK (0xFF000000U) 166 #define LPI2C_VERID_MAJOR_SHIFT (24U) 167 #define LPI2C_VERID_MAJOR_WIDTH (8U) 168 #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) 169 /*! @} */ 170 171 /*! @name PARAM - Parameter */ 172 /*! @{ */ 173 174 #define LPI2C_PARAM_MTXFIFO_MASK (0xFU) 175 #define LPI2C_PARAM_MTXFIFO_SHIFT (0U) 176 #define LPI2C_PARAM_MTXFIFO_WIDTH (4U) 177 #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) 178 179 #define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) 180 #define LPI2C_PARAM_MRXFIFO_SHIFT (8U) 181 #define LPI2C_PARAM_MRXFIFO_WIDTH (4U) 182 #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) 183 /*! @} */ 184 185 /*! @name MCR - Controller Control */ 186 /*! @{ */ 187 188 #define LPI2C_MCR_MEN_MASK (0x1U) 189 #define LPI2C_MCR_MEN_SHIFT (0U) 190 #define LPI2C_MCR_MEN_WIDTH (1U) 191 #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) 192 193 #define LPI2C_MCR_RST_MASK (0x2U) 194 #define LPI2C_MCR_RST_SHIFT (1U) 195 #define LPI2C_MCR_RST_WIDTH (1U) 196 #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) 197 198 #define LPI2C_MCR_DOZEN_MASK (0x4U) 199 #define LPI2C_MCR_DOZEN_SHIFT (2U) 200 #define LPI2C_MCR_DOZEN_WIDTH (1U) 201 #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) 202 203 #define LPI2C_MCR_DBGEN_MASK (0x8U) 204 #define LPI2C_MCR_DBGEN_SHIFT (3U) 205 #define LPI2C_MCR_DBGEN_WIDTH (1U) 206 #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) 207 208 #define LPI2C_MCR_RTF_MASK (0x100U) 209 #define LPI2C_MCR_RTF_SHIFT (8U) 210 #define LPI2C_MCR_RTF_WIDTH (1U) 211 #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) 212 213 #define LPI2C_MCR_RRF_MASK (0x200U) 214 #define LPI2C_MCR_RRF_SHIFT (9U) 215 #define LPI2C_MCR_RRF_WIDTH (1U) 216 #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) 217 /*! @} */ 218 219 /*! @name MSR - Controller Status */ 220 /*! @{ */ 221 222 #define LPI2C_MSR_TDF_MASK (0x1U) 223 #define LPI2C_MSR_TDF_SHIFT (0U) 224 #define LPI2C_MSR_TDF_WIDTH (1U) 225 #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) 226 227 #define LPI2C_MSR_RDF_MASK (0x2U) 228 #define LPI2C_MSR_RDF_SHIFT (1U) 229 #define LPI2C_MSR_RDF_WIDTH (1U) 230 #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) 231 232 #define LPI2C_MSR_EPF_MASK (0x100U) 233 #define LPI2C_MSR_EPF_SHIFT (8U) 234 #define LPI2C_MSR_EPF_WIDTH (1U) 235 #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) 236 237 #define LPI2C_MSR_SDF_MASK (0x200U) 238 #define LPI2C_MSR_SDF_SHIFT (9U) 239 #define LPI2C_MSR_SDF_WIDTH (1U) 240 #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) 241 242 #define LPI2C_MSR_NDF_MASK (0x400U) 243 #define LPI2C_MSR_NDF_SHIFT (10U) 244 #define LPI2C_MSR_NDF_WIDTH (1U) 245 #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) 246 247 #define LPI2C_MSR_ALF_MASK (0x800U) 248 #define LPI2C_MSR_ALF_SHIFT (11U) 249 #define LPI2C_MSR_ALF_WIDTH (1U) 250 #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) 251 252 #define LPI2C_MSR_FEF_MASK (0x1000U) 253 #define LPI2C_MSR_FEF_SHIFT (12U) 254 #define LPI2C_MSR_FEF_WIDTH (1U) 255 #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) 256 257 #define LPI2C_MSR_PLTF_MASK (0x2000U) 258 #define LPI2C_MSR_PLTF_SHIFT (13U) 259 #define LPI2C_MSR_PLTF_WIDTH (1U) 260 #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) 261 262 #define LPI2C_MSR_DMF_MASK (0x4000U) 263 #define LPI2C_MSR_DMF_SHIFT (14U) 264 #define LPI2C_MSR_DMF_WIDTH (1U) 265 #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) 266 267 #define LPI2C_MSR_STF_MASK (0x8000U) 268 #define LPI2C_MSR_STF_SHIFT (15U) 269 #define LPI2C_MSR_STF_WIDTH (1U) 270 #define LPI2C_MSR_STF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_STF_SHIFT)) & LPI2C_MSR_STF_MASK) 271 272 #define LPI2C_MSR_MBF_MASK (0x1000000U) 273 #define LPI2C_MSR_MBF_SHIFT (24U) 274 #define LPI2C_MSR_MBF_WIDTH (1U) 275 #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) 276 277 #define LPI2C_MSR_BBF_MASK (0x2000000U) 278 #define LPI2C_MSR_BBF_SHIFT (25U) 279 #define LPI2C_MSR_BBF_WIDTH (1U) 280 #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) 281 /*! @} */ 282 283 /*! @name MIER - Controller Interrupt Enable */ 284 /*! @{ */ 285 286 #define LPI2C_MIER_TDIE_MASK (0x1U) 287 #define LPI2C_MIER_TDIE_SHIFT (0U) 288 #define LPI2C_MIER_TDIE_WIDTH (1U) 289 #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) 290 291 #define LPI2C_MIER_RDIE_MASK (0x2U) 292 #define LPI2C_MIER_RDIE_SHIFT (1U) 293 #define LPI2C_MIER_RDIE_WIDTH (1U) 294 #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) 295 296 #define LPI2C_MIER_EPIE_MASK (0x100U) 297 #define LPI2C_MIER_EPIE_SHIFT (8U) 298 #define LPI2C_MIER_EPIE_WIDTH (1U) 299 #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) 300 301 #define LPI2C_MIER_SDIE_MASK (0x200U) 302 #define LPI2C_MIER_SDIE_SHIFT (9U) 303 #define LPI2C_MIER_SDIE_WIDTH (1U) 304 #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) 305 306 #define LPI2C_MIER_NDIE_MASK (0x400U) 307 #define LPI2C_MIER_NDIE_SHIFT (10U) 308 #define LPI2C_MIER_NDIE_WIDTH (1U) 309 #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) 310 311 #define LPI2C_MIER_ALIE_MASK (0x800U) 312 #define LPI2C_MIER_ALIE_SHIFT (11U) 313 #define LPI2C_MIER_ALIE_WIDTH (1U) 314 #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) 315 316 #define LPI2C_MIER_FEIE_MASK (0x1000U) 317 #define LPI2C_MIER_FEIE_SHIFT (12U) 318 #define LPI2C_MIER_FEIE_WIDTH (1U) 319 #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) 320 321 #define LPI2C_MIER_PLTIE_MASK (0x2000U) 322 #define LPI2C_MIER_PLTIE_SHIFT (13U) 323 #define LPI2C_MIER_PLTIE_WIDTH (1U) 324 #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) 325 326 #define LPI2C_MIER_DMIE_MASK (0x4000U) 327 #define LPI2C_MIER_DMIE_SHIFT (14U) 328 #define LPI2C_MIER_DMIE_WIDTH (1U) 329 #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) 330 331 #define LPI2C_MIER_STIE_MASK (0x8000U) 332 #define LPI2C_MIER_STIE_SHIFT (15U) 333 #define LPI2C_MIER_STIE_WIDTH (1U) 334 #define LPI2C_MIER_STIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_STIE_SHIFT)) & LPI2C_MIER_STIE_MASK) 335 /*! @} */ 336 337 /*! @name MDER - Controller DMA Enable */ 338 /*! @{ */ 339 340 #define LPI2C_MDER_TDDE_MASK (0x1U) 341 #define LPI2C_MDER_TDDE_SHIFT (0U) 342 #define LPI2C_MDER_TDDE_WIDTH (1U) 343 #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) 344 345 #define LPI2C_MDER_RDDE_MASK (0x2U) 346 #define LPI2C_MDER_RDDE_SHIFT (1U) 347 #define LPI2C_MDER_RDDE_WIDTH (1U) 348 #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) 349 /*! @} */ 350 351 /*! @name MCFGR0 - Controller Configuration 0 */ 352 /*! @{ */ 353 354 #define LPI2C_MCFGR0_HREN_MASK (0x1U) 355 #define LPI2C_MCFGR0_HREN_SHIFT (0U) 356 #define LPI2C_MCFGR0_HREN_WIDTH (1U) 357 #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) 358 359 #define LPI2C_MCFGR0_HRPOL_MASK (0x2U) 360 #define LPI2C_MCFGR0_HRPOL_SHIFT (1U) 361 #define LPI2C_MCFGR0_HRPOL_WIDTH (1U) 362 #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) 363 364 #define LPI2C_MCFGR0_HRSEL_MASK (0x4U) 365 #define LPI2C_MCFGR0_HRSEL_SHIFT (2U) 366 #define LPI2C_MCFGR0_HRSEL_WIDTH (1U) 367 #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) 368 369 #define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) 370 #define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) 371 #define LPI2C_MCFGR0_CIRFIFO_WIDTH (1U) 372 #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) 373 374 #define LPI2C_MCFGR0_RDMO_MASK (0x200U) 375 #define LPI2C_MCFGR0_RDMO_SHIFT (9U) 376 #define LPI2C_MCFGR0_RDMO_WIDTH (1U) 377 #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) 378 379 #define LPI2C_MCFGR0_RELAX_MASK (0x10000U) 380 #define LPI2C_MCFGR0_RELAX_SHIFT (16U) 381 #define LPI2C_MCFGR0_RELAX_WIDTH (1U) 382 #define LPI2C_MCFGR0_RELAX(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RELAX_SHIFT)) & LPI2C_MCFGR0_RELAX_MASK) 383 384 #define LPI2C_MCFGR0_ABORT_MASK (0x20000U) 385 #define LPI2C_MCFGR0_ABORT_SHIFT (17U) 386 #define LPI2C_MCFGR0_ABORT_WIDTH (1U) 387 #define LPI2C_MCFGR0_ABORT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_ABORT_SHIFT)) & LPI2C_MCFGR0_ABORT_MASK) 388 /*! @} */ 389 390 /*! @name MCFGR1 - Controller Configuration 1 */ 391 /*! @{ */ 392 393 #define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) 394 #define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) 395 #define LPI2C_MCFGR1_PRESCALE_WIDTH (3U) 396 #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) 397 398 #define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) 399 #define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) 400 #define LPI2C_MCFGR1_AUTOSTOP_WIDTH (1U) 401 #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) 402 403 #define LPI2C_MCFGR1_IGNACK_MASK (0x200U) 404 #define LPI2C_MCFGR1_IGNACK_SHIFT (9U) 405 #define LPI2C_MCFGR1_IGNACK_WIDTH (1U) 406 #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) 407 408 #define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) 409 #define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) 410 #define LPI2C_MCFGR1_TIMECFG_WIDTH (1U) 411 #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) 412 413 #define LPI2C_MCFGR1_STOPCFG_MASK (0x800U) 414 #define LPI2C_MCFGR1_STOPCFG_SHIFT (11U) 415 #define LPI2C_MCFGR1_STOPCFG_WIDTH (1U) 416 #define LPI2C_MCFGR1_STOPCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STOPCFG_SHIFT)) & LPI2C_MCFGR1_STOPCFG_MASK) 417 418 #define LPI2C_MCFGR1_STARTCFG_MASK (0x1000U) 419 #define LPI2C_MCFGR1_STARTCFG_SHIFT (12U) 420 #define LPI2C_MCFGR1_STARTCFG_WIDTH (1U) 421 #define LPI2C_MCFGR1_STARTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_STARTCFG_SHIFT)) & LPI2C_MCFGR1_STARTCFG_MASK) 422 423 #define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) 424 #define LPI2C_MCFGR1_MATCFG_SHIFT (16U) 425 #define LPI2C_MCFGR1_MATCFG_WIDTH (3U) 426 #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) 427 428 #define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) 429 #define LPI2C_MCFGR1_PINCFG_SHIFT (24U) 430 #define LPI2C_MCFGR1_PINCFG_WIDTH (3U) 431 #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) 432 /*! @} */ 433 434 /*! @name MCFGR2 - Controller Configuration 2 */ 435 /*! @{ */ 436 437 #define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) 438 #define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) 439 #define LPI2C_MCFGR2_BUSIDLE_WIDTH (12U) 440 #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) 441 442 #define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) 443 #define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) 444 #define LPI2C_MCFGR2_FILTSCL_WIDTH (4U) 445 #define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) 446 447 #define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) 448 #define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) 449 #define LPI2C_MCFGR2_FILTSDA_WIDTH (4U) 450 #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) 451 /*! @} */ 452 453 /*! @name MCFGR3 - Controller Configuration 3 */ 454 /*! @{ */ 455 456 #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) 457 #define LPI2C_MCFGR3_PINLOW_SHIFT (8U) 458 #define LPI2C_MCFGR3_PINLOW_WIDTH (12U) 459 #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) 460 /*! @} */ 461 462 /*! @name MDMR - Controller Data Match */ 463 /*! @{ */ 464 465 #define LPI2C_MDMR_MATCH0_MASK (0xFFU) 466 #define LPI2C_MDMR_MATCH0_SHIFT (0U) 467 #define LPI2C_MDMR_MATCH0_WIDTH (8U) 468 #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) 469 470 #define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) 471 #define LPI2C_MDMR_MATCH1_SHIFT (16U) 472 #define LPI2C_MDMR_MATCH1_WIDTH (8U) 473 #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) 474 /*! @} */ 475 476 /*! @name MCCR0 - Controller Clock Configuration 0 */ 477 /*! @{ */ 478 479 #define LPI2C_MCCR0_CLKLO_MASK (0x3FU) 480 #define LPI2C_MCCR0_CLKLO_SHIFT (0U) 481 #define LPI2C_MCCR0_CLKLO_WIDTH (6U) 482 #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) 483 484 #define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) 485 #define LPI2C_MCCR0_CLKHI_SHIFT (8U) 486 #define LPI2C_MCCR0_CLKHI_WIDTH (6U) 487 #define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) 488 489 #define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) 490 #define LPI2C_MCCR0_SETHOLD_SHIFT (16U) 491 #define LPI2C_MCCR0_SETHOLD_WIDTH (6U) 492 #define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) 493 494 #define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) 495 #define LPI2C_MCCR0_DATAVD_SHIFT (24U) 496 #define LPI2C_MCCR0_DATAVD_WIDTH (6U) 497 #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) 498 /*! @} */ 499 500 /*! @name MCCR1 - Controller Clock Configuration 1 */ 501 /*! @{ */ 502 503 #define LPI2C_MCCR1_CLKLO_MASK (0x3FU) 504 #define LPI2C_MCCR1_CLKLO_SHIFT (0U) 505 #define LPI2C_MCCR1_CLKLO_WIDTH (6U) 506 #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) 507 508 #define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) 509 #define LPI2C_MCCR1_CLKHI_SHIFT (8U) 510 #define LPI2C_MCCR1_CLKHI_WIDTH (6U) 511 #define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) 512 513 #define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) 514 #define LPI2C_MCCR1_SETHOLD_SHIFT (16U) 515 #define LPI2C_MCCR1_SETHOLD_WIDTH (6U) 516 #define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) 517 518 #define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) 519 #define LPI2C_MCCR1_DATAVD_SHIFT (24U) 520 #define LPI2C_MCCR1_DATAVD_WIDTH (6U) 521 #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) 522 /*! @} */ 523 524 /*! @name MFCR - Controller FIFO Control */ 525 /*! @{ */ 526 527 #define LPI2C_MFCR_TXWATER_MASK (0x7U) 528 #define LPI2C_MFCR_TXWATER_SHIFT (0U) 529 #define LPI2C_MFCR_TXWATER_WIDTH (3U) 530 #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) 531 532 #define LPI2C_MFCR_RXWATER_MASK (0x70000U) 533 #define LPI2C_MFCR_RXWATER_SHIFT (16U) 534 #define LPI2C_MFCR_RXWATER_WIDTH (3U) 535 #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) 536 /*! @} */ 537 538 /*! @name MFSR - Controller FIFO Status */ 539 /*! @{ */ 540 541 #define LPI2C_MFSR_TXCOUNT_MASK (0xFU) 542 #define LPI2C_MFSR_TXCOUNT_SHIFT (0U) 543 #define LPI2C_MFSR_TXCOUNT_WIDTH (4U) 544 #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) 545 546 #define LPI2C_MFSR_RXCOUNT_MASK (0xF0000U) 547 #define LPI2C_MFSR_RXCOUNT_SHIFT (16U) 548 #define LPI2C_MFSR_RXCOUNT_WIDTH (4U) 549 #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) 550 /*! @} */ 551 552 /*! @name MTDR - Controller Transmit Data */ 553 /*! @{ */ 554 555 #define LPI2C_MTDR_DATA_MASK (0xFFU) 556 #define LPI2C_MTDR_DATA_SHIFT (0U) 557 #define LPI2C_MTDR_DATA_WIDTH (8U) 558 #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) 559 560 #define LPI2C_MTDR_CMD_MASK (0x700U) 561 #define LPI2C_MTDR_CMD_SHIFT (8U) 562 #define LPI2C_MTDR_CMD_WIDTH (3U) 563 #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) 564 /*! @} */ 565 566 /*! @name MRDR - Controller Receive Data */ 567 /*! @{ */ 568 569 #define LPI2C_MRDR_DATA_MASK (0xFFU) 570 #define LPI2C_MRDR_DATA_SHIFT (0U) 571 #define LPI2C_MRDR_DATA_WIDTH (8U) 572 #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) 573 574 #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) 575 #define LPI2C_MRDR_RXEMPTY_SHIFT (14U) 576 #define LPI2C_MRDR_RXEMPTY_WIDTH (1U) 577 #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) 578 /*! @} */ 579 580 /*! @name MRDROR - Controller Receive Data Read Only */ 581 /*! @{ */ 582 583 #define LPI2C_MRDROR_DATA_MASK (0xFFU) 584 #define LPI2C_MRDROR_DATA_SHIFT (0U) 585 #define LPI2C_MRDROR_DATA_WIDTH (8U) 586 #define LPI2C_MRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_DATA_SHIFT)) & LPI2C_MRDROR_DATA_MASK) 587 588 #define LPI2C_MRDROR_RXEMPTY_MASK (0x4000U) 589 #define LPI2C_MRDROR_RXEMPTY_SHIFT (14U) 590 #define LPI2C_MRDROR_RXEMPTY_WIDTH (1U) 591 #define LPI2C_MRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDROR_RXEMPTY_SHIFT)) & LPI2C_MRDROR_RXEMPTY_MASK) 592 /*! @} */ 593 594 /*! @name SCR - Target Control */ 595 /*! @{ */ 596 597 #define LPI2C_SCR_SEN_MASK (0x1U) 598 #define LPI2C_SCR_SEN_SHIFT (0U) 599 #define LPI2C_SCR_SEN_WIDTH (1U) 600 #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) 601 602 #define LPI2C_SCR_RST_MASK (0x2U) 603 #define LPI2C_SCR_RST_SHIFT (1U) 604 #define LPI2C_SCR_RST_WIDTH (1U) 605 #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) 606 607 #define LPI2C_SCR_FILTEN_MASK (0x10U) 608 #define LPI2C_SCR_FILTEN_SHIFT (4U) 609 #define LPI2C_SCR_FILTEN_WIDTH (1U) 610 #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) 611 612 #define LPI2C_SCR_FILTDZ_MASK (0x20U) 613 #define LPI2C_SCR_FILTDZ_SHIFT (5U) 614 #define LPI2C_SCR_FILTDZ_WIDTH (1U) 615 #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) 616 617 #define LPI2C_SCR_RTF_MASK (0x100U) 618 #define LPI2C_SCR_RTF_SHIFT (8U) 619 #define LPI2C_SCR_RTF_WIDTH (1U) 620 #define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) 621 622 #define LPI2C_SCR_RRF_MASK (0x200U) 623 #define LPI2C_SCR_RRF_SHIFT (9U) 624 #define LPI2C_SCR_RRF_WIDTH (1U) 625 #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) 626 /*! @} */ 627 628 /*! @name SSR - Target Status */ 629 /*! @{ */ 630 631 #define LPI2C_SSR_TDF_MASK (0x1U) 632 #define LPI2C_SSR_TDF_SHIFT (0U) 633 #define LPI2C_SSR_TDF_WIDTH (1U) 634 #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) 635 636 #define LPI2C_SSR_RDF_MASK (0x2U) 637 #define LPI2C_SSR_RDF_SHIFT (1U) 638 #define LPI2C_SSR_RDF_WIDTH (1U) 639 #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) 640 641 #define LPI2C_SSR_AVF_MASK (0x4U) 642 #define LPI2C_SSR_AVF_SHIFT (2U) 643 #define LPI2C_SSR_AVF_WIDTH (1U) 644 #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) 645 646 #define LPI2C_SSR_TAF_MASK (0x8U) 647 #define LPI2C_SSR_TAF_SHIFT (3U) 648 #define LPI2C_SSR_TAF_WIDTH (1U) 649 #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) 650 651 #define LPI2C_SSR_RSF_MASK (0x100U) 652 #define LPI2C_SSR_RSF_SHIFT (8U) 653 #define LPI2C_SSR_RSF_WIDTH (1U) 654 #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) 655 656 #define LPI2C_SSR_SDF_MASK (0x200U) 657 #define LPI2C_SSR_SDF_SHIFT (9U) 658 #define LPI2C_SSR_SDF_WIDTH (1U) 659 #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) 660 661 #define LPI2C_SSR_BEF_MASK (0x400U) 662 #define LPI2C_SSR_BEF_SHIFT (10U) 663 #define LPI2C_SSR_BEF_WIDTH (1U) 664 #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) 665 666 #define LPI2C_SSR_FEF_MASK (0x800U) 667 #define LPI2C_SSR_FEF_SHIFT (11U) 668 #define LPI2C_SSR_FEF_WIDTH (1U) 669 #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) 670 671 #define LPI2C_SSR_AM0F_MASK (0x1000U) 672 #define LPI2C_SSR_AM0F_SHIFT (12U) 673 #define LPI2C_SSR_AM0F_WIDTH (1U) 674 #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) 675 676 #define LPI2C_SSR_AM1F_MASK (0x2000U) 677 #define LPI2C_SSR_AM1F_SHIFT (13U) 678 #define LPI2C_SSR_AM1F_WIDTH (1U) 679 #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) 680 681 #define LPI2C_SSR_GCF_MASK (0x4000U) 682 #define LPI2C_SSR_GCF_SHIFT (14U) 683 #define LPI2C_SSR_GCF_WIDTH (1U) 684 #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) 685 686 #define LPI2C_SSR_SARF_MASK (0x8000U) 687 #define LPI2C_SSR_SARF_SHIFT (15U) 688 #define LPI2C_SSR_SARF_WIDTH (1U) 689 #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) 690 691 #define LPI2C_SSR_SBF_MASK (0x1000000U) 692 #define LPI2C_SSR_SBF_SHIFT (24U) 693 #define LPI2C_SSR_SBF_WIDTH (1U) 694 #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) 695 696 #define LPI2C_SSR_BBF_MASK (0x2000000U) 697 #define LPI2C_SSR_BBF_SHIFT (25U) 698 #define LPI2C_SSR_BBF_WIDTH (1U) 699 #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) 700 /*! @} */ 701 702 /*! @name SIER - Target Interrupt Enable */ 703 /*! @{ */ 704 705 #define LPI2C_SIER_TDIE_MASK (0x1U) 706 #define LPI2C_SIER_TDIE_SHIFT (0U) 707 #define LPI2C_SIER_TDIE_WIDTH (1U) 708 #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) 709 710 #define LPI2C_SIER_RDIE_MASK (0x2U) 711 #define LPI2C_SIER_RDIE_SHIFT (1U) 712 #define LPI2C_SIER_RDIE_WIDTH (1U) 713 #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) 714 715 #define LPI2C_SIER_AVIE_MASK (0x4U) 716 #define LPI2C_SIER_AVIE_SHIFT (2U) 717 #define LPI2C_SIER_AVIE_WIDTH (1U) 718 #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) 719 720 #define LPI2C_SIER_TAIE_MASK (0x8U) 721 #define LPI2C_SIER_TAIE_SHIFT (3U) 722 #define LPI2C_SIER_TAIE_WIDTH (1U) 723 #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) 724 725 #define LPI2C_SIER_RSIE_MASK (0x100U) 726 #define LPI2C_SIER_RSIE_SHIFT (8U) 727 #define LPI2C_SIER_RSIE_WIDTH (1U) 728 #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) 729 730 #define LPI2C_SIER_SDIE_MASK (0x200U) 731 #define LPI2C_SIER_SDIE_SHIFT (9U) 732 #define LPI2C_SIER_SDIE_WIDTH (1U) 733 #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) 734 735 #define LPI2C_SIER_BEIE_MASK (0x400U) 736 #define LPI2C_SIER_BEIE_SHIFT (10U) 737 #define LPI2C_SIER_BEIE_WIDTH (1U) 738 #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) 739 740 #define LPI2C_SIER_FEIE_MASK (0x800U) 741 #define LPI2C_SIER_FEIE_SHIFT (11U) 742 #define LPI2C_SIER_FEIE_WIDTH (1U) 743 #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) 744 745 #define LPI2C_SIER_AM0IE_MASK (0x1000U) 746 #define LPI2C_SIER_AM0IE_SHIFT (12U) 747 #define LPI2C_SIER_AM0IE_WIDTH (1U) 748 #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) 749 750 #define LPI2C_SIER_AM1IE_MASK (0x2000U) 751 #define LPI2C_SIER_AM1IE_SHIFT (13U) 752 #define LPI2C_SIER_AM1IE_WIDTH (1U) 753 #define LPI2C_SIER_AM1IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK) 754 755 #define LPI2C_SIER_GCIE_MASK (0x4000U) 756 #define LPI2C_SIER_GCIE_SHIFT (14U) 757 #define LPI2C_SIER_GCIE_WIDTH (1U) 758 #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) 759 760 #define LPI2C_SIER_SARIE_MASK (0x8000U) 761 #define LPI2C_SIER_SARIE_SHIFT (15U) 762 #define LPI2C_SIER_SARIE_WIDTH (1U) 763 #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) 764 /*! @} */ 765 766 /*! @name SDER - Target DMA Enable */ 767 /*! @{ */ 768 769 #define LPI2C_SDER_TDDE_MASK (0x1U) 770 #define LPI2C_SDER_TDDE_SHIFT (0U) 771 #define LPI2C_SDER_TDDE_WIDTH (1U) 772 #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) 773 774 #define LPI2C_SDER_RDDE_MASK (0x2U) 775 #define LPI2C_SDER_RDDE_SHIFT (1U) 776 #define LPI2C_SDER_RDDE_WIDTH (1U) 777 #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) 778 779 #define LPI2C_SDER_AVDE_MASK (0x4U) 780 #define LPI2C_SDER_AVDE_SHIFT (2U) 781 #define LPI2C_SDER_AVDE_WIDTH (1U) 782 #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) 783 /*! @} */ 784 785 /*! @name SCFGR0 - Target Configuration 0 */ 786 /*! @{ */ 787 788 #define LPI2C_SCFGR0_RDREQ_MASK (0x1U) 789 #define LPI2C_SCFGR0_RDREQ_SHIFT (0U) 790 #define LPI2C_SCFGR0_RDREQ_WIDTH (1U) 791 #define LPI2C_SCFGR0_RDREQ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDREQ_SHIFT)) & LPI2C_SCFGR0_RDREQ_MASK) 792 793 #define LPI2C_SCFGR0_RDACK_MASK (0x2U) 794 #define LPI2C_SCFGR0_RDACK_SHIFT (1U) 795 #define LPI2C_SCFGR0_RDACK_WIDTH (1U) 796 #define LPI2C_SCFGR0_RDACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR0_RDACK_SHIFT)) & LPI2C_SCFGR0_RDACK_MASK) 797 /*! @} */ 798 799 /*! @name SCFGR1 - Target Configuration 1 */ 800 /*! @{ */ 801 802 #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) 803 #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) 804 #define LPI2C_SCFGR1_ADRSTALL_WIDTH (1U) 805 #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) 806 807 #define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) 808 #define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) 809 #define LPI2C_SCFGR1_RXSTALL_WIDTH (1U) 810 #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) 811 812 #define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) 813 #define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) 814 #define LPI2C_SCFGR1_TXDSTALL_WIDTH (1U) 815 #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) 816 817 #define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) 818 #define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) 819 #define LPI2C_SCFGR1_ACKSTALL_WIDTH (1U) 820 #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) 821 822 #define LPI2C_SCFGR1_RXNACK_MASK (0x10U) 823 #define LPI2C_SCFGR1_RXNACK_SHIFT (4U) 824 #define LPI2C_SCFGR1_RXNACK_WIDTH (1U) 825 #define LPI2C_SCFGR1_RXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXNACK_SHIFT)) & LPI2C_SCFGR1_RXNACK_MASK) 826 827 #define LPI2C_SCFGR1_GCEN_MASK (0x100U) 828 #define LPI2C_SCFGR1_GCEN_SHIFT (8U) 829 #define LPI2C_SCFGR1_GCEN_WIDTH (1U) 830 #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) 831 832 #define LPI2C_SCFGR1_SAEN_MASK (0x200U) 833 #define LPI2C_SCFGR1_SAEN_SHIFT (9U) 834 #define LPI2C_SCFGR1_SAEN_WIDTH (1U) 835 #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) 836 837 #define LPI2C_SCFGR1_TXCFG_MASK (0x400U) 838 #define LPI2C_SCFGR1_TXCFG_SHIFT (10U) 839 #define LPI2C_SCFGR1_TXCFG_WIDTH (1U) 840 #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) 841 842 #define LPI2C_SCFGR1_RXCFG_MASK (0x800U) 843 #define LPI2C_SCFGR1_RXCFG_SHIFT (11U) 844 #define LPI2C_SCFGR1_RXCFG_WIDTH (1U) 845 #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) 846 847 #define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) 848 #define LPI2C_SCFGR1_IGNACK_SHIFT (12U) 849 #define LPI2C_SCFGR1_IGNACK_WIDTH (1U) 850 #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) 851 852 #define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) 853 #define LPI2C_SCFGR1_HSMEN_SHIFT (13U) 854 #define LPI2C_SCFGR1_HSMEN_WIDTH (1U) 855 #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) 856 857 #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) 858 #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) 859 #define LPI2C_SCFGR1_ADDRCFG_WIDTH (3U) 860 #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) 861 862 #define LPI2C_SCFGR1_RXALL_MASK (0x1000000U) 863 #define LPI2C_SCFGR1_RXALL_SHIFT (24U) 864 #define LPI2C_SCFGR1_RXALL_WIDTH (1U) 865 #define LPI2C_SCFGR1_RXALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXALL_SHIFT)) & LPI2C_SCFGR1_RXALL_MASK) 866 867 #define LPI2C_SCFGR1_RSCFG_MASK (0x2000000U) 868 #define LPI2C_SCFGR1_RSCFG_SHIFT (25U) 869 #define LPI2C_SCFGR1_RSCFG_WIDTH (1U) 870 #define LPI2C_SCFGR1_RSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RSCFG_SHIFT)) & LPI2C_SCFGR1_RSCFG_MASK) 871 872 #define LPI2C_SCFGR1_SDCFG_MASK (0x4000000U) 873 #define LPI2C_SCFGR1_SDCFG_SHIFT (26U) 874 #define LPI2C_SCFGR1_SDCFG_WIDTH (1U) 875 #define LPI2C_SCFGR1_SDCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SDCFG_SHIFT)) & LPI2C_SCFGR1_SDCFG_MASK) 876 /*! @} */ 877 878 /*! @name SCFGR2 - Target Configuration 2 */ 879 /*! @{ */ 880 881 #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) 882 #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) 883 #define LPI2C_SCFGR2_CLKHOLD_WIDTH (4U) 884 #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) 885 886 #define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) 887 #define LPI2C_SCFGR2_DATAVD_SHIFT (8U) 888 #define LPI2C_SCFGR2_DATAVD_WIDTH (6U) 889 #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) 890 891 #define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) 892 #define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) 893 #define LPI2C_SCFGR2_FILTSCL_WIDTH (4U) 894 #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) 895 896 #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) 897 #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) 898 #define LPI2C_SCFGR2_FILTSDA_WIDTH (4U) 899 #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) 900 /*! @} */ 901 902 /*! @name SAMR - Target Address Match */ 903 /*! @{ */ 904 905 #define LPI2C_SAMR_ADDR0_MASK (0x7FEU) 906 #define LPI2C_SAMR_ADDR0_SHIFT (1U) 907 #define LPI2C_SAMR_ADDR0_WIDTH (10U) 908 #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) 909 910 #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) 911 #define LPI2C_SAMR_ADDR1_SHIFT (17U) 912 #define LPI2C_SAMR_ADDR1_WIDTH (10U) 913 #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) 914 /*! @} */ 915 916 /*! @name SASR - Target Address Status */ 917 /*! @{ */ 918 919 #define LPI2C_SASR_RADDR_MASK (0x7FFU) 920 #define LPI2C_SASR_RADDR_SHIFT (0U) 921 #define LPI2C_SASR_RADDR_WIDTH (11U) 922 #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) 923 924 #define LPI2C_SASR_ANV_MASK (0x4000U) 925 #define LPI2C_SASR_ANV_SHIFT (14U) 926 #define LPI2C_SASR_ANV_WIDTH (1U) 927 #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) 928 /*! @} */ 929 930 /*! @name STAR - Target Transmit ACK */ 931 /*! @{ */ 932 933 #define LPI2C_STAR_TXNACK_MASK (0x1U) 934 #define LPI2C_STAR_TXNACK_SHIFT (0U) 935 #define LPI2C_STAR_TXNACK_WIDTH (1U) 936 #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) 937 /*! @} */ 938 939 /*! @name STDR - Target Transmit Data */ 940 /*! @{ */ 941 942 #define LPI2C_STDR_DATA_MASK (0xFFU) 943 #define LPI2C_STDR_DATA_SHIFT (0U) 944 #define LPI2C_STDR_DATA_WIDTH (8U) 945 #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) 946 /*! @} */ 947 948 /*! @name SRDR - Target Receive Data */ 949 /*! @{ */ 950 951 #define LPI2C_SRDR_DATA_MASK (0xFFU) 952 #define LPI2C_SRDR_DATA_SHIFT (0U) 953 #define LPI2C_SRDR_DATA_WIDTH (8U) 954 #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) 955 956 #define LPI2C_SRDR_RADDR_MASK (0x700U) 957 #define LPI2C_SRDR_RADDR_SHIFT (8U) 958 #define LPI2C_SRDR_RADDR_WIDTH (3U) 959 #define LPI2C_SRDR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RADDR_SHIFT)) & LPI2C_SRDR_RADDR_MASK) 960 961 #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) 962 #define LPI2C_SRDR_RXEMPTY_SHIFT (14U) 963 #define LPI2C_SRDR_RXEMPTY_WIDTH (1U) 964 #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) 965 966 #define LPI2C_SRDR_SOF_MASK (0x8000U) 967 #define LPI2C_SRDR_SOF_SHIFT (15U) 968 #define LPI2C_SRDR_SOF_WIDTH (1U) 969 #define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK) 970 /*! @} */ 971 972 /*! @name SRDROR - Target Receive Data Read Only */ 973 /*! @{ */ 974 975 #define LPI2C_SRDROR_DATA_MASK (0xFFU) 976 #define LPI2C_SRDROR_DATA_SHIFT (0U) 977 #define LPI2C_SRDROR_DATA_WIDTH (8U) 978 #define LPI2C_SRDROR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_DATA_SHIFT)) & LPI2C_SRDROR_DATA_MASK) 979 980 #define LPI2C_SRDROR_RADDR_MASK (0x700U) 981 #define LPI2C_SRDROR_RADDR_SHIFT (8U) 982 #define LPI2C_SRDROR_RADDR_WIDTH (3U) 983 #define LPI2C_SRDROR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RADDR_SHIFT)) & LPI2C_SRDROR_RADDR_MASK) 984 985 #define LPI2C_SRDROR_RXEMPTY_MASK (0x4000U) 986 #define LPI2C_SRDROR_RXEMPTY_SHIFT (14U) 987 #define LPI2C_SRDROR_RXEMPTY_WIDTH (1U) 988 #define LPI2C_SRDROR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_RXEMPTY_SHIFT)) & LPI2C_SRDROR_RXEMPTY_MASK) 989 990 #define LPI2C_SRDROR_SOF_MASK (0x8000U) 991 #define LPI2C_SRDROR_SOF_SHIFT (15U) 992 #define LPI2C_SRDROR_SOF_WIDTH (1U) 993 #define LPI2C_SRDROR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDROR_SOF_SHIFT)) & LPI2C_SRDROR_SOF_MASK) 994 /*! @} */ 995 996 /*! @name MTCBR - Controller Transmit Command Burst */ 997 /*! @{ */ 998 999 #define LPI2C_MTCBR_DATA_MASK (0xFFU) 1000 #define LPI2C_MTCBR_DATA_SHIFT (0U) 1001 #define LPI2C_MTCBR_DATA_WIDTH (8U) 1002 #define LPI2C_MTCBR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_DATA_SHIFT)) & LPI2C_MTCBR_DATA_MASK) 1003 1004 #define LPI2C_MTCBR_CMD_MASK (0x700U) 1005 #define LPI2C_MTCBR_CMD_SHIFT (8U) 1006 #define LPI2C_MTCBR_CMD_WIDTH (3U) 1007 #define LPI2C_MTCBR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTCBR_CMD_SHIFT)) & LPI2C_MTCBR_CMD_MASK) 1008 /*! @} */ 1009 1010 /*! @name MTDBR - Transmit Data Burst */ 1011 /*! @{ */ 1012 1013 #define LPI2C_MTDBR_DATA0_MASK (0xFFU) 1014 #define LPI2C_MTDBR_DATA0_SHIFT (0U) 1015 #define LPI2C_MTDBR_DATA0_WIDTH (8U) 1016 #define LPI2C_MTDBR_DATA0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA0_SHIFT)) & LPI2C_MTDBR_DATA0_MASK) 1017 1018 #define LPI2C_MTDBR_DATA1_MASK (0xFF00U) 1019 #define LPI2C_MTDBR_DATA1_SHIFT (8U) 1020 #define LPI2C_MTDBR_DATA1_WIDTH (8U) 1021 #define LPI2C_MTDBR_DATA1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA1_SHIFT)) & LPI2C_MTDBR_DATA1_MASK) 1022 1023 #define LPI2C_MTDBR_DATA2_MASK (0xFF0000U) 1024 #define LPI2C_MTDBR_DATA2_SHIFT (16U) 1025 #define LPI2C_MTDBR_DATA2_WIDTH (8U) 1026 #define LPI2C_MTDBR_DATA2(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA2_SHIFT)) & LPI2C_MTDBR_DATA2_MASK) 1027 1028 #define LPI2C_MTDBR_DATA3_MASK (0xFF000000U) 1029 #define LPI2C_MTDBR_DATA3_SHIFT (24U) 1030 #define LPI2C_MTDBR_DATA3_WIDTH (8U) 1031 #define LPI2C_MTDBR_DATA3(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDBR_DATA3_SHIFT)) & LPI2C_MTDBR_DATA3_MASK) 1032 /*! @} */ 1033 1034 /*! 1035 * @} 1036 */ /* end of group LPI2C_Register_Masks */ 1037 1038 /*! 1039 * @} 1040 */ /* end of group LPI2C_Peripheral_Access_Layer */ 1041 1042 #endif /* #if !defined(S32Z2_LPI2C_H_) */ 1043
