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Searched refs:LPFLLDIV (Results 1 – 25 of 37) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/drivers/
Dfsl_clock.c43 #define SCG_LPFLLDIV_LPFLLDIV1_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV1_MASK) >> SCG_LPFLLDIV_L…
44 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L…
45 #define SCG_LPFLLDIV_LPFLLDIV3_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV3_MASK) >> SCG_LPFLLDIV_L…
718 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV1(config->div1) | SCG_LPFLLDIV_LPFLLDIV2(config->div2) | in CLOCK_InitLpFll()
Dfsl_clock.h1306 uint32_t reg = SCG->LPFLLDIV; in CLOCK_SetLpFllAsyncClkDiv()
1318 SCG->LPFLLDIV = reg; in CLOCK_SetLpFllAsyncClkDiv()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/drivers/
Dfsl_clock.h1137 uint32_t reg = SCG->LPFLLDIV; in CLOCK_SetLpFllAsyncClkDiv()
1150 SCG->LPFLLDIV = reg; in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c32 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L…
762 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/drivers/
Dfsl_clock.h1133 uint32_t reg = SCG->LPFLLDIV; in CLOCK_SetLpFllAsyncClkDiv()
1146 SCG->LPFLLDIV = reg; in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c32 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L…
762 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/drivers/
Dfsl_clock.h1125 uint32_t reg = SCG->LPFLLDIV; in CLOCK_SetLpFllAsyncClkDiv()
1138 SCG->LPFLLDIV = reg; in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c32 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L…
762 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/drivers/
Dfsl_clock.h1162 uint32_t reg = SCG->LPFLLDIV; in CLOCK_SetLpFllAsyncClkDiv()
1175 SCG->LPFLLDIV = reg; in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c35 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L…
778 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/drivers/
Dfsl_clock.h1211 uint32_t reg = SCG->LPFLLDIV; in CLOCK_SetLpFllAsyncClkDiv()
1224 SCG->LPFLLDIV = reg; in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c34 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L…
782 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/drivers/
Dfsl_clock.h1211 uint32_t reg = SCG->LPFLLDIV; in CLOCK_SetLpFllAsyncClkDiv()
1224 SCG->LPFLLDIV = reg; in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c38 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L…
830 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/drivers/
Dfsl_clock.h1163 uint32_t reg = SCG->LPFLLDIV; in CLOCK_SetLpFllAsyncClkDiv()
1176 SCG->LPFLLDIV = reg; in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c35 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L…
778 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/drivers/
Dfsl_clock.h1219 uint32_t reg = SCG->LPFLLDIV; in CLOCK_SetLpFllAsyncClkDiv()
1232 SCG->LPFLLDIV = reg; in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c34 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L…
782 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/drivers/
Dfsl_clock.h1218 uint32_t reg = SCG->LPFLLDIV; in CLOCK_SetLpFllAsyncClkDiv()
1231 SCG->LPFLLDIV = reg; in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c38 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L…
830 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z7/drivers/
Dfsl_clock.h1160 uint32_t reg = SCG->LPFLLDIV; in CLOCK_SetLpFllAsyncClkDiv()
1173 SCG->LPFLLDIV = reg; in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c38 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L…
784 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/drivers/
Dfsl_clock.h1218 uint32_t reg = SCG->LPFLLDIV; in CLOCK_SetLpFllAsyncClkDiv()
1231 SCG->LPFLLDIV = reg; in CLOCK_SetLpFllAsyncClkDiv()
Dfsl_clock.c34 #define SCG_LPFLLDIV_LPFLLDIV2_VAL ((SCG->LPFLLDIV & SCG_LPFLLDIV_LPFLLDIV2_MASK) >> SCG_LPFLLDIV_L…
782 SCG->LPFLLDIV = SCG_LPFLLDIV_LPFLLDIV2(config->div2); in CLOCK_InitLpFll()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/
DMKE14Z4.h9637 …__IO uint32_t LPFLLDIV; /**< Low Power FLL Divide Register, offset: 0x504… member

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