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Searched refs:LPFLLCSR (Results 1 – 25 of 37) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/drivers/
Dfsl_clock.c800 SCG->LPFLLCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitLpFll()
802 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLERR_MASK) != 0UL) in CLOCK_InitLpFll()
809 SCG->LPFLLCSR |= ((uint32_t)SCG_LPFLLCSR_LPFLLEN_MASK | config->enableMode); in CLOCK_InitLpFll()
812 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK)) in CLOCK_InitLpFll()
819 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK)) in CLOCK_InitLpFll()
840 uint32_t reg = SCG->LPFLLCSR; in CLOCK_DeinitLpFll()
855 SCG->LPFLLCSR = SCG_LPFLLCSR_LPFLLERR_MASK; in CLOCK_DeinitLpFll()
878 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK) != 0UL) /* LPFLL is valid. */ in CLOCK_GetLpFllFreq()
Dfsl_clock.h1249 return (bool)(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK); in CLOCK_IsLpFllValid()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/drivers/
Dfsl_clock.c737 SCG->LPFLLCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitLpFll()
739 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLERR_MASK) != 0UL) in CLOCK_InitLpFll()
746 SCG->LPFLLCSR |= ((uint32_t)SCG_LPFLLCSR_LPFLLEN_MASK | (uint32_t)config->enableMode); in CLOCK_InitLpFll()
749 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK)) in CLOCK_InitLpFll()
756 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK)) in CLOCK_InitLpFll()
777 uint32_t reg = SCG->LPFLLCSR; in CLOCK_DeinitLpFll()
791 SCG->LPFLLCSR = SCG_LPFLLCSR_LPFLLERR_MASK; in CLOCK_DeinitLpFll()
810 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK) != 0UL) /* LPFLL is valid. */ in CLOCK_GetLpFllFreq()
Dfsl_clock.h1343 return (bool)(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK); in CLOCK_IsLpFllValid()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/drivers/
Dfsl_clock.c780 SCG->LPFLLCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitLpFll()
782 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLERR_MASK) != 0UL) in CLOCK_InitLpFll()
789 SCG->LPFLLCSR |= ((uint32_t)SCG_LPFLLCSR_LPFLLEN_MASK | config->enableMode); in CLOCK_InitLpFll()
792 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK)) in CLOCK_InitLpFll()
799 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK)) in CLOCK_InitLpFll()
820 uint32_t reg = SCG->LPFLLCSR; in CLOCK_DeinitLpFll()
835 SCG->LPFLLCSR = SCG_LPFLLCSR_LPFLLERR_MASK; in CLOCK_DeinitLpFll()
855 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK) != 0UL) /* LPFLL is valid. */ in CLOCK_GetLpFllFreq()
Dfsl_clock.h1163 return (bool)(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK); in CLOCK_IsLpFllValid()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/drivers/
Dfsl_clock.c796 SCG->LPFLLCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitLpFll()
798 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLERR_MASK) != 0UL) in CLOCK_InitLpFll()
805 SCG->LPFLLCSR |= ((uint32_t)SCG_LPFLLCSR_LPFLLEN_MASK | config->enableMode); in CLOCK_InitLpFll()
808 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK)) in CLOCK_InitLpFll()
815 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK)) in CLOCK_InitLpFll()
836 uint32_t reg = SCG->LPFLLCSR; in CLOCK_DeinitLpFll()
851 SCG->LPFLLCSR = SCG_LPFLLCSR_LPFLLERR_MASK; in CLOCK_DeinitLpFll()
872 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK) != 0UL) /* LPFLL is valid. */ in CLOCK_GetLpFllFreq()
Dfsl_clock.h1201 return (bool)(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK); in CLOCK_IsLpFllValid()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/drivers/
Dfsl_clock.c800 SCG->LPFLLCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitLpFll()
802 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLERR_MASK) != 0UL) in CLOCK_InitLpFll()
809 SCG->LPFLLCSR |= ((uint32_t)SCG_LPFLLCSR_LPFLLEN_MASK | config->enableMode); in CLOCK_InitLpFll()
812 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK)) in CLOCK_InitLpFll()
819 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK)) in CLOCK_InitLpFll()
840 uint32_t reg = SCG->LPFLLCSR; in CLOCK_DeinitLpFll()
855 SCG->LPFLLCSR = SCG_LPFLLCSR_LPFLLERR_MASK; in CLOCK_DeinitLpFll()
878 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK) != 0UL) /* LPFLL is valid. */ in CLOCK_GetLpFllFreq()
Dfsl_clock.h1257 return (bool)(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK); in CLOCK_IsLpFllValid()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/drivers/
Dfsl_clock.c796 SCG->LPFLLCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitLpFll()
798 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLERR_MASK) != 0UL) in CLOCK_InitLpFll()
805 SCG->LPFLLCSR |= ((uint32_t)SCG_LPFLLCSR_LPFLLEN_MASK | config->enableMode); in CLOCK_InitLpFll()
808 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK)) in CLOCK_InitLpFll()
815 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK)) in CLOCK_InitLpFll()
836 uint32_t reg = SCG->LPFLLCSR; in CLOCK_DeinitLpFll()
851 SCG->LPFLLCSR = SCG_LPFLLCSR_LPFLLERR_MASK; in CLOCK_DeinitLpFll()
872 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK) != 0UL) /* LPFLL is valid. */ in CLOCK_GetLpFllFreq()
Dfsl_clock.h1200 return (bool)(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK); in CLOCK_IsLpFllValid()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/drivers/
Dfsl_clock.c800 SCG->LPFLLCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitLpFll()
802 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLERR_MASK) != 0UL) in CLOCK_InitLpFll()
809 SCG->LPFLLCSR |= ((uint32_t)SCG_LPFLLCSR_LPFLLEN_MASK | config->enableMode); in CLOCK_InitLpFll()
812 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK)) in CLOCK_InitLpFll()
819 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK)) in CLOCK_InitLpFll()
840 uint32_t reg = SCG->LPFLLCSR; in CLOCK_DeinitLpFll()
855 SCG->LPFLLCSR = SCG_LPFLLCSR_LPFLLERR_MASK; in CLOCK_DeinitLpFll()
878 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK) != 0UL) /* LPFLL is valid. */ in CLOCK_GetLpFllFreq()
Dfsl_clock.h1256 return (bool)(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK); in CLOCK_IsLpFllValid()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/drivers/
Dfsl_clock.c780 SCG->LPFLLCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitLpFll()
782 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLERR_MASK) != 0UL) in CLOCK_InitLpFll()
789 SCG->LPFLLCSR |= ((uint32_t)SCG_LPFLLCSR_LPFLLEN_MASK | config->enableMode); in CLOCK_InitLpFll()
792 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK)) in CLOCK_InitLpFll()
799 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK)) in CLOCK_InitLpFll()
820 uint32_t reg = SCG->LPFLLCSR; in CLOCK_DeinitLpFll()
835 SCG->LPFLLCSR = SCG_LPFLLCSR_LPFLLERR_MASK; in CLOCK_DeinitLpFll()
855 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK) != 0UL) /* LPFLL is valid. */ in CLOCK_GetLpFllFreq()
Dfsl_clock.h1171 return (bool)(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK); in CLOCK_IsLpFllValid()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/drivers/
Dfsl_clock.c780 SCG->LPFLLCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitLpFll()
782 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLERR_MASK) != 0UL) in CLOCK_InitLpFll()
789 SCG->LPFLLCSR |= ((uint32_t)SCG_LPFLLCSR_LPFLLEN_MASK | config->enableMode); in CLOCK_InitLpFll()
792 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK)) in CLOCK_InitLpFll()
799 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK)) in CLOCK_InitLpFll()
820 uint32_t reg = SCG->LPFLLCSR; in CLOCK_DeinitLpFll()
835 SCG->LPFLLCSR = SCG_LPFLLCSR_LPFLLERR_MASK; in CLOCK_DeinitLpFll()
855 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK) != 0UL) /* LPFLL is valid. */ in CLOCK_GetLpFllFreq()
Dfsl_clock.h1175 return (bool)(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK); in CLOCK_IsLpFllValid()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z7/drivers/
Dfsl_clock.c802 SCG->LPFLLCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitLpFll()
804 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLERR_MASK) != 0UL) in CLOCK_InitLpFll()
811 SCG->LPFLLCSR |= ((uint32_t)SCG_LPFLLCSR_LPFLLEN_MASK | config->enableMode); in CLOCK_InitLpFll()
814 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK)) in CLOCK_InitLpFll()
821 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK)) in CLOCK_InitLpFll()
842 uint32_t reg = SCG->LPFLLCSR; in CLOCK_DeinitLpFll()
857 SCG->LPFLLCSR = SCG_LPFLLCSR_LPFLLERR_MASK; in CLOCK_DeinitLpFll()
880 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK) != 0UL) /* LPFLL is valid. */ in CLOCK_GetLpFllFreq()
Dfsl_clock.h1198 return (bool)(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK); in CLOCK_IsLpFllValid()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/drivers/
Dfsl_clock.c848 SCG->LPFLLCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitLpFll()
850 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLERR_MASK) != 0UL) in CLOCK_InitLpFll()
857 SCG->LPFLLCSR |= ((uint32_t)SCG_LPFLLCSR_LPFLLEN_MASK | config->enableMode); in CLOCK_InitLpFll()
860 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK)) in CLOCK_InitLpFll()
867 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK)) in CLOCK_InitLpFll()
888 uint32_t reg = SCG->LPFLLCSR; in CLOCK_DeinitLpFll()
903 SCG->LPFLLCSR = SCG_LPFLLCSR_LPFLLERR_MASK; in CLOCK_DeinitLpFll()
926 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK) != 0UL) /* LPFLL is valid. */ in CLOCK_GetLpFllFreq()
Dfsl_clock.h1256 return (bool)(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK); in CLOCK_IsLpFllValid()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/drivers/
Dfsl_clock.c848 SCG->LPFLLCSR = (uint32_t)(config->trimConfig->trimMode); in CLOCK_InitLpFll()
850 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLERR_MASK) != 0UL) in CLOCK_InitLpFll()
857 SCG->LPFLLCSR |= ((uint32_t)SCG_LPFLLCSR_LPFLLEN_MASK | config->enableMode); in CLOCK_InitLpFll()
860 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK)) in CLOCK_InitLpFll()
867 while (0UL == (SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLTRMLOCK_MASK)) in CLOCK_InitLpFll()
888 uint32_t reg = SCG->LPFLLCSR; in CLOCK_DeinitLpFll()
903 SCG->LPFLLCSR = SCG_LPFLLCSR_LPFLLERR_MASK; in CLOCK_DeinitLpFll()
926 if ((SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK) != 0UL) /* LPFLL is valid. */ in CLOCK_GetLpFllFreq()
Dfsl_clock.h1249 return (bool)(SCG->LPFLLCSR & SCG_LPFLLCSR_LPFLLVLD_MASK); in CLOCK_IsLpFllValid()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/
DMKE14Z4.h9636 …__IO uint32_t LPFLLCSR; /**< Low Power FLL Control Status Register, offse… member

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