1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_LPCMP.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_LPCMP 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_LPCMP_H_) /* Check if memory map has not been already included */ 58 #define S32K344_LPCMP_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- LPCMP Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup LPCMP_Peripheral_Access_Layer LPCMP Peripheral Access Layer 68 * @{ 69 */ 70 71 /** LPCMP - Register Layout Typedef */ 72 typedef struct { 73 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ 74 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ 75 __IO uint32_t CCR0; /**< Comparator Control Register 0, offset: 0x8 */ 76 __IO uint32_t CCR1; /**< Comparator Control Register 1, offset: 0xC */ 77 __IO uint32_t CCR2; /**< Comparator Control Register 2, offset: 0x10 */ 78 uint8_t RESERVED_0[4]; 79 __IO uint32_t DCR; /**< DAC Control Register, offset: 0x18 */ 80 __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x1C */ 81 __IO uint32_t CSR; /**< Comparator Status Register, offset: 0x20 */ 82 __IO uint32_t RRCR0; /**< Round Robin Control Register 0, offset: 0x24 */ 83 __IO uint32_t RRCR1; /**< Round Robin Control Register 1, offset: 0x28 */ 84 __IO uint32_t RRCSR; /**< Round Robin Control and Status Register, offset: 0x2C */ 85 __IO uint32_t RRSR; /**< Round Robin Status Register, offset: 0x30 */ 86 } LPCMP_Type, *LPCMP_MemMapPtr; 87 88 /** Number of instances of the LPCMP module. */ 89 #define LPCMP_INSTANCE_COUNT (3u) 90 91 /* LPCMP - Peripheral instance base addresses */ 92 /** Peripheral LPCMP_0 base address */ 93 #define IP_LPCMP_0_BASE (0x40370000u) 94 /** Peripheral LPCMP_0 base pointer */ 95 #define IP_LPCMP_0 ((LPCMP_Type *)IP_LPCMP_0_BASE) 96 /** Peripheral LPCMP_1 base address */ 97 #define IP_LPCMP_1_BASE (0x40374000u) 98 /** Peripheral LPCMP_1 base pointer */ 99 #define IP_LPCMP_1 ((LPCMP_Type *)IP_LPCMP_1_BASE) 100 /** Peripheral LPCMP_2 base address */ 101 #define IP_LPCMP_2_BASE (0x404E8000u) 102 /** Peripheral LPCMP_2 base pointer */ 103 #define IP_LPCMP_2 ((LPCMP_Type *)IP_LPCMP_2_BASE) 104 /** Array initializer of LPCMP peripheral base addresses */ 105 #define IP_LPCMP_BASE_ADDRS { IP_LPCMP_0_BASE, IP_LPCMP_1_BASE, IP_LPCMP_2_BASE } 106 /** Array initializer of LPCMP peripheral base pointers */ 107 #define IP_LPCMP_BASE_PTRS { IP_LPCMP_0, IP_LPCMP_1, IP_LPCMP_2 } 108 109 /* ---------------------------------------------------------------------------- 110 -- LPCMP Register Masks 111 ---------------------------------------------------------------------------- */ 112 113 /*! 114 * @addtogroup LPCMP_Register_Masks LPCMP Register Masks 115 * @{ 116 */ 117 118 /*! @name VERID - Version ID Register */ 119 /*! @{ */ 120 121 #define LPCMP_VERID_FEATURE_MASK (0xFFFFU) 122 #define LPCMP_VERID_FEATURE_SHIFT (0U) 123 #define LPCMP_VERID_FEATURE_WIDTH (16U) 124 #define LPCMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_FEATURE_SHIFT)) & LPCMP_VERID_FEATURE_MASK) 125 126 #define LPCMP_VERID_MINOR_MASK (0xFF0000U) 127 #define LPCMP_VERID_MINOR_SHIFT (16U) 128 #define LPCMP_VERID_MINOR_WIDTH (8U) 129 #define LPCMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MINOR_SHIFT)) & LPCMP_VERID_MINOR_MASK) 130 131 #define LPCMP_VERID_MAJOR_MASK (0xFF000000U) 132 #define LPCMP_VERID_MAJOR_SHIFT (24U) 133 #define LPCMP_VERID_MAJOR_WIDTH (8U) 134 #define LPCMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_VERID_MAJOR_SHIFT)) & LPCMP_VERID_MAJOR_MASK) 135 /*! @} */ 136 137 /*! @name PARAM - Parameter Register */ 138 /*! @{ */ 139 140 #define LPCMP_PARAM_DAC_RES_MASK (0xFU) 141 #define LPCMP_PARAM_DAC_RES_SHIFT (0U) 142 #define LPCMP_PARAM_DAC_RES_WIDTH (4U) 143 #define LPCMP_PARAM_DAC_RES(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_PARAM_DAC_RES_SHIFT)) & LPCMP_PARAM_DAC_RES_MASK) 144 /*! @} */ 145 146 /*! @name CCR0 - Comparator Control Register 0 */ 147 /*! @{ */ 148 149 #define LPCMP_CCR0_CMP_EN_MASK (0x1U) 150 #define LPCMP_CCR0_CMP_EN_SHIFT (0U) 151 #define LPCMP_CCR0_CMP_EN_WIDTH (1U) 152 #define LPCMP_CCR0_CMP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_EN_SHIFT)) & LPCMP_CCR0_CMP_EN_MASK) 153 154 #define LPCMP_CCR0_CMP_STOP_EN_MASK (0x2U) 155 #define LPCMP_CCR0_CMP_STOP_EN_SHIFT (1U) 156 #define LPCMP_CCR0_CMP_STOP_EN_WIDTH (1U) 157 #define LPCMP_CCR0_CMP_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_CMP_STOP_EN_SHIFT)) & LPCMP_CCR0_CMP_STOP_EN_MASK) 158 159 #define LPCMP_CCR0_LINKEN_MASK (0x4U) 160 #define LPCMP_CCR0_LINKEN_SHIFT (2U) 161 #define LPCMP_CCR0_LINKEN_WIDTH (1U) 162 #define LPCMP_CCR0_LINKEN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR0_LINKEN_SHIFT)) & LPCMP_CCR0_LINKEN_MASK) 163 /*! @} */ 164 165 /*! @name CCR1 - Comparator Control Register 1 */ 166 /*! @{ */ 167 168 #define LPCMP_CCR1_WINDOW_EN_MASK (0x1U) 169 #define LPCMP_CCR1_WINDOW_EN_SHIFT (0U) 170 #define LPCMP_CCR1_WINDOW_EN_WIDTH (1U) 171 #define LPCMP_CCR1_WINDOW_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_EN_SHIFT)) & LPCMP_CCR1_WINDOW_EN_MASK) 172 173 #define LPCMP_CCR1_SAMPLE_EN_MASK (0x2U) 174 #define LPCMP_CCR1_SAMPLE_EN_SHIFT (1U) 175 #define LPCMP_CCR1_SAMPLE_EN_WIDTH (1U) 176 #define LPCMP_CCR1_SAMPLE_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_SAMPLE_EN_SHIFT)) & LPCMP_CCR1_SAMPLE_EN_MASK) 177 178 #define LPCMP_CCR1_DMA_EN_MASK (0x4U) 179 #define LPCMP_CCR1_DMA_EN_SHIFT (2U) 180 #define LPCMP_CCR1_DMA_EN_WIDTH (1U) 181 #define LPCMP_CCR1_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_DMA_EN_SHIFT)) & LPCMP_CCR1_DMA_EN_MASK) 182 183 #define LPCMP_CCR1_COUT_INV_MASK (0x8U) 184 #define LPCMP_CCR1_COUT_INV_SHIFT (3U) 185 #define LPCMP_CCR1_COUT_INV_WIDTH (1U) 186 #define LPCMP_CCR1_COUT_INV(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_INV_SHIFT)) & LPCMP_CCR1_COUT_INV_MASK) 187 188 #define LPCMP_CCR1_COUT_SEL_MASK (0x10U) 189 #define LPCMP_CCR1_COUT_SEL_SHIFT (4U) 190 #define LPCMP_CCR1_COUT_SEL_WIDTH (1U) 191 #define LPCMP_CCR1_COUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_SEL_SHIFT)) & LPCMP_CCR1_COUT_SEL_MASK) 192 193 #define LPCMP_CCR1_COUT_PEN_MASK (0x20U) 194 #define LPCMP_CCR1_COUT_PEN_SHIFT (5U) 195 #define LPCMP_CCR1_COUT_PEN_WIDTH (1U) 196 #define LPCMP_CCR1_COUT_PEN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUT_PEN_SHIFT)) & LPCMP_CCR1_COUT_PEN_MASK) 197 198 #define LPCMP_CCR1_COUTA_OWEN_MASK (0x40U) 199 #define LPCMP_CCR1_COUTA_OWEN_SHIFT (6U) 200 #define LPCMP_CCR1_COUTA_OWEN_WIDTH (1U) 201 #define LPCMP_CCR1_COUTA_OWEN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OWEN_SHIFT)) & LPCMP_CCR1_COUTA_OWEN_MASK) 202 203 #define LPCMP_CCR1_COUTA_OW_MASK (0x80U) 204 #define LPCMP_CCR1_COUTA_OW_SHIFT (7U) 205 #define LPCMP_CCR1_COUTA_OW_WIDTH (1U) 206 #define LPCMP_CCR1_COUTA_OW(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_COUTA_OW_SHIFT)) & LPCMP_CCR1_COUTA_OW_MASK) 207 208 #define LPCMP_CCR1_WINDOW_INV_MASK (0x100U) 209 #define LPCMP_CCR1_WINDOW_INV_SHIFT (8U) 210 #define LPCMP_CCR1_WINDOW_INV_WIDTH (1U) 211 #define LPCMP_CCR1_WINDOW_INV(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_INV_SHIFT)) & LPCMP_CCR1_WINDOW_INV_MASK) 212 213 #define LPCMP_CCR1_WINDOW_CLS_MASK (0x200U) 214 #define LPCMP_CCR1_WINDOW_CLS_SHIFT (9U) 215 #define LPCMP_CCR1_WINDOW_CLS_WIDTH (1U) 216 #define LPCMP_CCR1_WINDOW_CLS(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_WINDOW_CLS_SHIFT)) & LPCMP_CCR1_WINDOW_CLS_MASK) 217 218 #define LPCMP_CCR1_EVT_SEL_MASK (0xC00U) 219 #define LPCMP_CCR1_EVT_SEL_SHIFT (10U) 220 #define LPCMP_CCR1_EVT_SEL_WIDTH (2U) 221 #define LPCMP_CCR1_EVT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_EVT_SEL_SHIFT)) & LPCMP_CCR1_EVT_SEL_MASK) 222 223 #define LPCMP_CCR1_FILT_CNT_MASK (0x70000U) 224 #define LPCMP_CCR1_FILT_CNT_SHIFT (16U) 225 #define LPCMP_CCR1_FILT_CNT_WIDTH (3U) 226 #define LPCMP_CCR1_FILT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_CNT_SHIFT)) & LPCMP_CCR1_FILT_CNT_MASK) 227 228 #define LPCMP_CCR1_FILT_PER_MASK (0xFF000000U) 229 #define LPCMP_CCR1_FILT_PER_SHIFT (24U) 230 #define LPCMP_CCR1_FILT_PER_WIDTH (8U) 231 #define LPCMP_CCR1_FILT_PER(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR1_FILT_PER_SHIFT)) & LPCMP_CCR1_FILT_PER_MASK) 232 /*! @} */ 233 234 /*! @name CCR2 - Comparator Control Register 2 */ 235 /*! @{ */ 236 237 #define LPCMP_CCR2_CMP_HPMD_MASK (0x1U) 238 #define LPCMP_CCR2_CMP_HPMD_SHIFT (0U) 239 #define LPCMP_CCR2_CMP_HPMD_WIDTH (1U) 240 #define LPCMP_CCR2_CMP_HPMD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_CMP_HPMD_SHIFT)) & LPCMP_CCR2_CMP_HPMD_MASK) 241 242 #define LPCMP_CCR2_OFFSET_MASK (0x4U) 243 #define LPCMP_CCR2_OFFSET_SHIFT (2U) 244 #define LPCMP_CCR2_OFFSET_WIDTH (1U) 245 #define LPCMP_CCR2_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_OFFSET_SHIFT)) & LPCMP_CCR2_OFFSET_MASK) 246 247 #define LPCMP_CCR2_HYSTCTR_MASK (0x30U) 248 #define LPCMP_CCR2_HYSTCTR_SHIFT (4U) 249 #define LPCMP_CCR2_HYSTCTR_WIDTH (2U) 250 #define LPCMP_CCR2_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_HYSTCTR_SHIFT)) & LPCMP_CCR2_HYSTCTR_MASK) 251 252 #define LPCMP_CCR2_PSEL_MASK (0x70000U) 253 #define LPCMP_CCR2_PSEL_SHIFT (16U) 254 #define LPCMP_CCR2_PSEL_WIDTH (3U) 255 #define LPCMP_CCR2_PSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_PSEL_SHIFT)) & LPCMP_CCR2_PSEL_MASK) 256 257 #define LPCMP_CCR2_MSEL_MASK (0x700000U) 258 #define LPCMP_CCR2_MSEL_SHIFT (20U) 259 #define LPCMP_CCR2_MSEL_WIDTH (3U) 260 #define LPCMP_CCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_MSEL_SHIFT)) & LPCMP_CCR2_MSEL_MASK) 261 262 #define LPCMP_CCR2_INPSEL_MASK (0x3000000U) 263 #define LPCMP_CCR2_INPSEL_SHIFT (24U) 264 #define LPCMP_CCR2_INPSEL_WIDTH (2U) 265 #define LPCMP_CCR2_INPSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_INPSEL_SHIFT)) & LPCMP_CCR2_INPSEL_MASK) 266 267 #define LPCMP_CCR2_INMSEL_MASK (0x30000000U) 268 #define LPCMP_CCR2_INMSEL_SHIFT (28U) 269 #define LPCMP_CCR2_INMSEL_WIDTH (2U) 270 #define LPCMP_CCR2_INMSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CCR2_INMSEL_SHIFT)) & LPCMP_CCR2_INMSEL_MASK) 271 /*! @} */ 272 273 /*! @name DCR - DAC Control Register */ 274 /*! @{ */ 275 276 #define LPCMP_DCR_DAC_EN_MASK (0x1U) 277 #define LPCMP_DCR_DAC_EN_SHIFT (0U) 278 #define LPCMP_DCR_DAC_EN_WIDTH (1U) 279 #define LPCMP_DCR_DAC_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_EN_SHIFT)) & LPCMP_DCR_DAC_EN_MASK) 280 281 #define LPCMP_DCR_VRSEL_MASK (0x100U) 282 #define LPCMP_DCR_VRSEL_SHIFT (8U) 283 #define LPCMP_DCR_VRSEL_WIDTH (1U) 284 #define LPCMP_DCR_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_VRSEL_SHIFT)) & LPCMP_DCR_VRSEL_MASK) 285 286 #define LPCMP_DCR_DAC_DATA_MASK (0xFF0000U) 287 #define LPCMP_DCR_DAC_DATA_SHIFT (16U) 288 #define LPCMP_DCR_DAC_DATA_WIDTH (8U) 289 #define LPCMP_DCR_DAC_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_DCR_DAC_DATA_SHIFT)) & LPCMP_DCR_DAC_DATA_MASK) 290 /*! @} */ 291 292 /*! @name IER - Interrupt Enable Register */ 293 /*! @{ */ 294 295 #define LPCMP_IER_CFR_IE_MASK (0x1U) 296 #define LPCMP_IER_CFR_IE_SHIFT (0U) 297 #define LPCMP_IER_CFR_IE_WIDTH (1U) 298 #define LPCMP_IER_CFR_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFR_IE_SHIFT)) & LPCMP_IER_CFR_IE_MASK) 299 300 #define LPCMP_IER_CFF_IE_MASK (0x2U) 301 #define LPCMP_IER_CFF_IE_SHIFT (1U) 302 #define LPCMP_IER_CFF_IE_WIDTH (1U) 303 #define LPCMP_IER_CFF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_CFF_IE_SHIFT)) & LPCMP_IER_CFF_IE_MASK) 304 305 #define LPCMP_IER_RRF_IE_MASK (0x4U) 306 #define LPCMP_IER_RRF_IE_SHIFT (2U) 307 #define LPCMP_IER_RRF_IE_WIDTH (1U) 308 #define LPCMP_IER_RRF_IE(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_IER_RRF_IE_SHIFT)) & LPCMP_IER_RRF_IE_MASK) 309 /*! @} */ 310 311 /*! @name CSR - Comparator Status Register */ 312 /*! @{ */ 313 314 #define LPCMP_CSR_CFR_MASK (0x1U) 315 #define LPCMP_CSR_CFR_SHIFT (0U) 316 #define LPCMP_CSR_CFR_WIDTH (1U) 317 #define LPCMP_CSR_CFR(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFR_SHIFT)) & LPCMP_CSR_CFR_MASK) 318 319 #define LPCMP_CSR_CFF_MASK (0x2U) 320 #define LPCMP_CSR_CFF_SHIFT (1U) 321 #define LPCMP_CSR_CFF_WIDTH (1U) 322 #define LPCMP_CSR_CFF(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_CFF_SHIFT)) & LPCMP_CSR_CFF_MASK) 323 324 #define LPCMP_CSR_RRF_MASK (0x4U) 325 #define LPCMP_CSR_RRF_SHIFT (2U) 326 #define LPCMP_CSR_RRF_WIDTH (1U) 327 #define LPCMP_CSR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_RRF_SHIFT)) & LPCMP_CSR_RRF_MASK) 328 329 #define LPCMP_CSR_COUT_MASK (0x100U) 330 #define LPCMP_CSR_COUT_SHIFT (8U) 331 #define LPCMP_CSR_COUT_WIDTH (1U) 332 #define LPCMP_CSR_COUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_CSR_COUT_SHIFT)) & LPCMP_CSR_COUT_MASK) 333 /*! @} */ 334 335 /*! @name RRCR0 - Round Robin Control Register 0 */ 336 /*! @{ */ 337 338 #define LPCMP_RRCR0_RR_EN_MASK (0x1U) 339 #define LPCMP_RRCR0_RR_EN_SHIFT (0U) 340 #define LPCMP_RRCR0_RR_EN_WIDTH (1U) 341 #define LPCMP_RRCR0_RR_EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_EN_SHIFT)) & LPCMP_RRCR0_RR_EN_MASK) 342 343 #define LPCMP_RRCR0_RR_NSAM_MASK (0x300U) 344 #define LPCMP_RRCR0_RR_NSAM_SHIFT (8U) 345 #define LPCMP_RRCR0_RR_NSAM_WIDTH (2U) 346 #define LPCMP_RRCR0_RR_NSAM(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_NSAM_SHIFT)) & LPCMP_RRCR0_RR_NSAM_MASK) 347 348 #define LPCMP_RRCR0_RR_INITMOD_MASK (0x3F0000U) 349 #define LPCMP_RRCR0_RR_INITMOD_SHIFT (16U) 350 #define LPCMP_RRCR0_RR_INITMOD_WIDTH (6U) 351 #define LPCMP_RRCR0_RR_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR0_RR_INITMOD_SHIFT)) & LPCMP_RRCR0_RR_INITMOD_MASK) 352 /*! @} */ 353 354 /*! @name RRCR1 - Round Robin Control Register 1 */ 355 /*! @{ */ 356 357 #define LPCMP_RRCR1_RR_CH0EN_MASK (0x1U) 358 #define LPCMP_RRCR1_RR_CH0EN_SHIFT (0U) 359 #define LPCMP_RRCR1_RR_CH0EN_WIDTH (1U) 360 #define LPCMP_RRCR1_RR_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH0EN_SHIFT)) & LPCMP_RRCR1_RR_CH0EN_MASK) 361 362 #define LPCMP_RRCR1_RR_CH1EN_MASK (0x2U) 363 #define LPCMP_RRCR1_RR_CH1EN_SHIFT (1U) 364 #define LPCMP_RRCR1_RR_CH1EN_WIDTH (1U) 365 #define LPCMP_RRCR1_RR_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH1EN_SHIFT)) & LPCMP_RRCR1_RR_CH1EN_MASK) 366 367 #define LPCMP_RRCR1_RR_CH2EN_MASK (0x4U) 368 #define LPCMP_RRCR1_RR_CH2EN_SHIFT (2U) 369 #define LPCMP_RRCR1_RR_CH2EN_WIDTH (1U) 370 #define LPCMP_RRCR1_RR_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH2EN_SHIFT)) & LPCMP_RRCR1_RR_CH2EN_MASK) 371 372 #define LPCMP_RRCR1_RR_CH3EN_MASK (0x8U) 373 #define LPCMP_RRCR1_RR_CH3EN_SHIFT (3U) 374 #define LPCMP_RRCR1_RR_CH3EN_WIDTH (1U) 375 #define LPCMP_RRCR1_RR_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH3EN_SHIFT)) & LPCMP_RRCR1_RR_CH3EN_MASK) 376 377 #define LPCMP_RRCR1_RR_CH4EN_MASK (0x10U) 378 #define LPCMP_RRCR1_RR_CH4EN_SHIFT (4U) 379 #define LPCMP_RRCR1_RR_CH4EN_WIDTH (1U) 380 #define LPCMP_RRCR1_RR_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH4EN_SHIFT)) & LPCMP_RRCR1_RR_CH4EN_MASK) 381 382 #define LPCMP_RRCR1_RR_CH5EN_MASK (0x20U) 383 #define LPCMP_RRCR1_RR_CH5EN_SHIFT (5U) 384 #define LPCMP_RRCR1_RR_CH5EN_WIDTH (1U) 385 #define LPCMP_RRCR1_RR_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH5EN_SHIFT)) & LPCMP_RRCR1_RR_CH5EN_MASK) 386 387 #define LPCMP_RRCR1_RR_CH6EN_MASK (0x40U) 388 #define LPCMP_RRCR1_RR_CH6EN_SHIFT (6U) 389 #define LPCMP_RRCR1_RR_CH6EN_WIDTH (1U) 390 #define LPCMP_RRCR1_RR_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH6EN_SHIFT)) & LPCMP_RRCR1_RR_CH6EN_MASK) 391 392 #define LPCMP_RRCR1_RR_CH7EN_MASK (0x80U) 393 #define LPCMP_RRCR1_RR_CH7EN_SHIFT (7U) 394 #define LPCMP_RRCR1_RR_CH7EN_WIDTH (1U) 395 #define LPCMP_RRCR1_RR_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_RR_CH7EN_SHIFT)) & LPCMP_RRCR1_RR_CH7EN_MASK) 396 397 #define LPCMP_RRCR1_FIXP_MASK (0x10000U) 398 #define LPCMP_RRCR1_FIXP_SHIFT (16U) 399 #define LPCMP_RRCR1_FIXP_WIDTH (1U) 400 #define LPCMP_RRCR1_FIXP(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXP_SHIFT)) & LPCMP_RRCR1_FIXP_MASK) 401 402 #define LPCMP_RRCR1_FIXCH_MASK (0x700000U) 403 #define LPCMP_RRCR1_FIXCH_SHIFT (20U) 404 #define LPCMP_RRCR1_FIXCH_WIDTH (3U) 405 #define LPCMP_RRCR1_FIXCH(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCR1_FIXCH_SHIFT)) & LPCMP_RRCR1_FIXCH_MASK) 406 /*! @} */ 407 408 /*! @name RRCSR - Round Robin Control and Status Register */ 409 /*! @{ */ 410 411 #define LPCMP_RRCSR_RR_CH0OUT_MASK (0x1U) 412 #define LPCMP_RRCSR_RR_CH0OUT_SHIFT (0U) 413 #define LPCMP_RRCSR_RR_CH0OUT_WIDTH (1U) 414 #define LPCMP_RRCSR_RR_CH0OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH0OUT_SHIFT)) & LPCMP_RRCSR_RR_CH0OUT_MASK) 415 416 #define LPCMP_RRCSR_RR_CH1OUT_MASK (0x2U) 417 #define LPCMP_RRCSR_RR_CH1OUT_SHIFT (1U) 418 #define LPCMP_RRCSR_RR_CH1OUT_WIDTH (1U) 419 #define LPCMP_RRCSR_RR_CH1OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH1OUT_SHIFT)) & LPCMP_RRCSR_RR_CH1OUT_MASK) 420 421 #define LPCMP_RRCSR_RR_CH2OUT_MASK (0x4U) 422 #define LPCMP_RRCSR_RR_CH2OUT_SHIFT (2U) 423 #define LPCMP_RRCSR_RR_CH2OUT_WIDTH (1U) 424 #define LPCMP_RRCSR_RR_CH2OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH2OUT_SHIFT)) & LPCMP_RRCSR_RR_CH2OUT_MASK) 425 426 #define LPCMP_RRCSR_RR_CH3OUT_MASK (0x8U) 427 #define LPCMP_RRCSR_RR_CH3OUT_SHIFT (3U) 428 #define LPCMP_RRCSR_RR_CH3OUT_WIDTH (1U) 429 #define LPCMP_RRCSR_RR_CH3OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH3OUT_SHIFT)) & LPCMP_RRCSR_RR_CH3OUT_MASK) 430 431 #define LPCMP_RRCSR_RR_CH4OUT_MASK (0x10U) 432 #define LPCMP_RRCSR_RR_CH4OUT_SHIFT (4U) 433 #define LPCMP_RRCSR_RR_CH4OUT_WIDTH (1U) 434 #define LPCMP_RRCSR_RR_CH4OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH4OUT_SHIFT)) & LPCMP_RRCSR_RR_CH4OUT_MASK) 435 436 #define LPCMP_RRCSR_RR_CH5OUT_MASK (0x20U) 437 #define LPCMP_RRCSR_RR_CH5OUT_SHIFT (5U) 438 #define LPCMP_RRCSR_RR_CH5OUT_WIDTH (1U) 439 #define LPCMP_RRCSR_RR_CH5OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH5OUT_SHIFT)) & LPCMP_RRCSR_RR_CH5OUT_MASK) 440 441 #define LPCMP_RRCSR_RR_CH6OUT_MASK (0x40U) 442 #define LPCMP_RRCSR_RR_CH6OUT_SHIFT (6U) 443 #define LPCMP_RRCSR_RR_CH6OUT_WIDTH (1U) 444 #define LPCMP_RRCSR_RR_CH6OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH6OUT_SHIFT)) & LPCMP_RRCSR_RR_CH6OUT_MASK) 445 446 #define LPCMP_RRCSR_RR_CH7OUT_MASK (0x80U) 447 #define LPCMP_RRCSR_RR_CH7OUT_SHIFT (7U) 448 #define LPCMP_RRCSR_RR_CH7OUT_WIDTH (1U) 449 #define LPCMP_RRCSR_RR_CH7OUT(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRCSR_RR_CH7OUT_SHIFT)) & LPCMP_RRCSR_RR_CH7OUT_MASK) 450 /*! @} */ 451 452 /*! @name RRSR - Round Robin Status Register */ 453 /*! @{ */ 454 455 #define LPCMP_RRSR_RR_CH0F_MASK (0x1U) 456 #define LPCMP_RRSR_RR_CH0F_SHIFT (0U) 457 #define LPCMP_RRSR_RR_CH0F_WIDTH (1U) 458 #define LPCMP_RRSR_RR_CH0F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH0F_SHIFT)) & LPCMP_RRSR_RR_CH0F_MASK) 459 460 #define LPCMP_RRSR_RR_CH1F_MASK (0x2U) 461 #define LPCMP_RRSR_RR_CH1F_SHIFT (1U) 462 #define LPCMP_RRSR_RR_CH1F_WIDTH (1U) 463 #define LPCMP_RRSR_RR_CH1F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH1F_SHIFT)) & LPCMP_RRSR_RR_CH1F_MASK) 464 465 #define LPCMP_RRSR_RR_CH2F_MASK (0x4U) 466 #define LPCMP_RRSR_RR_CH2F_SHIFT (2U) 467 #define LPCMP_RRSR_RR_CH2F_WIDTH (1U) 468 #define LPCMP_RRSR_RR_CH2F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH2F_SHIFT)) & LPCMP_RRSR_RR_CH2F_MASK) 469 470 #define LPCMP_RRSR_RR_CH3F_MASK (0x8U) 471 #define LPCMP_RRSR_RR_CH3F_SHIFT (3U) 472 #define LPCMP_RRSR_RR_CH3F_WIDTH (1U) 473 #define LPCMP_RRSR_RR_CH3F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH3F_SHIFT)) & LPCMP_RRSR_RR_CH3F_MASK) 474 475 #define LPCMP_RRSR_RR_CH4F_MASK (0x10U) 476 #define LPCMP_RRSR_RR_CH4F_SHIFT (4U) 477 #define LPCMP_RRSR_RR_CH4F_WIDTH (1U) 478 #define LPCMP_RRSR_RR_CH4F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH4F_SHIFT)) & LPCMP_RRSR_RR_CH4F_MASK) 479 480 #define LPCMP_RRSR_RR_CH5F_MASK (0x20U) 481 #define LPCMP_RRSR_RR_CH5F_SHIFT (5U) 482 #define LPCMP_RRSR_RR_CH5F_WIDTH (1U) 483 #define LPCMP_RRSR_RR_CH5F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH5F_SHIFT)) & LPCMP_RRSR_RR_CH5F_MASK) 484 485 #define LPCMP_RRSR_RR_CH6F_MASK (0x40U) 486 #define LPCMP_RRSR_RR_CH6F_SHIFT (6U) 487 #define LPCMP_RRSR_RR_CH6F_WIDTH (1U) 488 #define LPCMP_RRSR_RR_CH6F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH6F_SHIFT)) & LPCMP_RRSR_RR_CH6F_MASK) 489 490 #define LPCMP_RRSR_RR_CH7F_MASK (0x80U) 491 #define LPCMP_RRSR_RR_CH7F_SHIFT (7U) 492 #define LPCMP_RRSR_RR_CH7F_WIDTH (1U) 493 #define LPCMP_RRSR_RR_CH7F(x) (((uint32_t)(((uint32_t)(x)) << LPCMP_RRSR_RR_CH7F_SHIFT)) & LPCMP_RRSR_RR_CH7F_MASK) 494 /*! @} */ 495 496 /*! 497 * @} 498 */ /* end of group LPCMP_Register_Masks */ 499 500 /*! 501 * @} 502 */ /* end of group LPCMP_Peripheral_Access_Layer */ 503 504 #endif /* #if !defined(S32K344_LPCMP_H_) */ 505
