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Searched refs:LMEM_PCCSAR_PHYADDR_MASK (Results 1 – 25 of 62) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/cm4/
Dfsl_cache.c97 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_InvalidateCodeCacheByRange()
149 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_CleanCodeCacheByRange()
202 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_CleanInvalidateCodeCacheByRange()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/cm4/
Dfsl_cache.c97 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_InvalidateCodeCacheByRange()
149 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_CleanCodeCacheByRange()
202 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_CleanInvalidateCodeCacheByRange()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/cm4/
Dfsl_cache.c97 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_InvalidateCodeCacheByRange()
149 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_CleanCodeCacheByRange()
202 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_CleanInvalidateCodeCacheByRange()
/hal_nxp-latest/mcux/mcux-sdk/drivers/cache/lmem/
Dfsl_cache.c97 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_InvalidateCodeCacheByRange()
149 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_CleanCodeCacheByRange()
202 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_CleanInvalidateCodeCacheByRange()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/cm4/
Dfsl_cache.c97 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_InvalidateCodeCacheByRange()
149 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_CleanCodeCacheByRange()
202 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_CleanInvalidateCodeCacheByRange()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/cm4/
Dfsl_cache.c97 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_InvalidateCodeCacheByRange()
149 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_CleanCodeCacheByRange()
202 LMEM->PCCSAR = (startAddr & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in L1CACHE_CleanInvalidateCodeCacheByRange()
/hal_nxp-latest/mcux/mcux-sdk/drivers/lmem/
Dfsl_lmem_cache.c158 base->PCCSAR = (address & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in LMEM_CodeCacheInvalidateLine()
227 base->PCCSAR = (address & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in LMEM_CodeCachePushLine()
298 base->PCCSAR = (address & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in LMEM_CodeCacheClearLine()
/hal_nxp-latest/imx/drivers/
Dlmem.c259 LMEM_PCCSAR_REG(base) = ((uint32_t)address & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in LMEM_FlushCodeCacheLine()
317 LMEM_PCCSAR_REG(base) = ((uint32_t)address & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; in LMEM_InvalidateCodeCacheLine()
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K142_LMEM.h209 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) macro
212 … (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
DS32K148_LMEM.h209 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) macro
212 … (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
DS32K118_LMEM.h209 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) macro
212 … (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
DS32K116_LMEM.h209 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) macro
212 … (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
DS32K142W_LMEM.h209 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) macro
212 … (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
DS32K146_LMEM.h209 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) macro
212 … (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
DS32K144W_LMEM.h209 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) macro
212 … (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
DS32K144_LMEM.h209 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) macro
212 … (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/
DMKE14F16.h8307 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) macro
8311 … (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/
DMKE18F16.h9311 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) macro
9315 … (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/
DMKE16F16.h9306 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) macro
9310 … (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h14924 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) macro
14926 … (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h14918 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) macro
14920 … (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h14365 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) macro
14367 … (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h14363 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) macro
14365 … (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK26F18/
DMK26F18.h17044 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) macro
17048 … (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK65F18/
DMK65F18.h18861 #define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU) macro
18865 … (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)

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