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Searched refs:LCKCR (Results 1 – 25 of 33) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/qspi/
Dfsl_qspi.c248 base->LCKCR = 0x2U; in QSPI_SetFlashConfig()
254 base->LCKCR = 0x1U; in QSPI_SetFlashConfig()
437 base->LCKCR = 0x2U; in QSPI_UpdateLUT()
448 base->LCKCR = 0x1U; in QSPI_UpdateLUT()
/hal_nxp-latest/s32/drivers/s32k3/Fls/src/
DQspi_Ip_Controller.c2002 BaseAddr->LCKCR = (uint32)0x00000002UL; in Qspi_Ip_ResetAllRegisters()
2057 BaseAddr->LCKCR = (uint32)0x00000002UL; in Qspi_Ip_ResetAllRegisters()
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K148_QUADSPI.h115 …__IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x3… member
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_QUADSPI.h120 …__IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x3… member
/hal_nxp-latest/mcux/mcux-sdk/drivers/xspi/
Dfsl_xspi.c461 base->LCKCR = 0x02; in XSPI_UpdateLUT()
471 base->LCKCR = 0x01; in XSPI_UpdateLUT()
/hal_nxp-latest/s32/drivers/s32ze/Mem_EXFLS/src/
DQspi_Ip_Controller.c2340 BaseAddr->LCKCR = (uint32)0x00000002UL; in Qspi_Ip_ResetAllRegisters()
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_QUADSPI.h133 …__IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x3… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK80F25615/
DMK80F25615.h18294 …__IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x3… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/
DMK82F25615.h19267 …__IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x3… member
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h30451 …__IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offse… member
30494 #define QuadSPI_LCKCR_REG(base) ((base)->LCKCR)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK28FA15/
DMK28FA15.h17798 …__IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x3… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK27FA15/
DMK27FA15.h17796 …__IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x3… member
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h37649 …__IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offse… member
37692 #define QuadSPI_LCKCR_REG(base) ((base)->LCKCR)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h27242 …__IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x3… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h27243 …__IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x3… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h63508 __IO uint32_t LCKCR; /**< LUT Lock Configuration, offset: 0x304 */ member
DMIMXRT735S_cm33_core1.h63577 __IO uint32_t LCKCR; /**< LUT Lock Configuration, offset: 0x304 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h44025 …__IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x3… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h66800 __IO uint32_t LCKCR; /**< LUT Lock Configuration, offset: 0x304 */ member
DMIMXRT758S_hifi1.h66729 __IO uint32_t LCKCR; /**< LUT Lock Configuration, offset: 0x304 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h46198 …__IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x3… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h46198 …__IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x3… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h66729 __IO uint32_t LCKCR; /**< LUT Lock Configuration, offset: 0x304 */ member
DMIMXRT798S_cm33_core1.h66800 __IO uint32_t LCKCR; /**< LUT Lock Configuration, offset: 0x304 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h46198 …__IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x3… member

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