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Searched refs:LCDIF_VDCTRL3_RSRVD0_MASK (Results 1 – 25 of 49) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h11620 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
11622 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h11621 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
11623 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h28373 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
28375 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h28895 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
28897 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h39054 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
39056 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h39052 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
39054 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h39052 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
39054 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h39054 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
39056 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h30425 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
30427 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h39054 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
39056 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_cm7.h39052 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
39054 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
DMIMX8MN6_ca53.h39066 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
39068 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h37864 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
37866 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h30417 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
30419 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h37864 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
37866 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h37864 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
37866 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h24801 #define LCDIF_VDCTRL3_RSRVD0_MASK 0xC0000000u macro
24803 … (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL3_RSRVD0_SHIFT))&LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h37864 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
37866 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h37864 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
37866 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h28941 #define LCDIF_VDCTRL3_RSRVD0_MASK 0xC0000000u macro
28943 … (((uint32_t)(((uint32_t)(x))<<LCDIF_VDCTRL3_RSRVD0_SHIFT))&LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM3/
DMIMX8MM3_cm4.h39755 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
39757 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h54815 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
54817 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM5/
DMIMX8MM5_cm4.h39755 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
39757 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM6/
DMIMX8MM6_cm4.h39755 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
39757 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM1/
DMIMX8MM1_cm4.h39755 #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) macro
39757 … (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)

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