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Searched refs:LCDIF_CTRL2_TOG_RSRVD5_MASK (Results 1 – 25 of 49) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h11308 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
11310 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h11309 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
11311 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h28093 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
28095 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h28615 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
28617 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h38722 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
38724 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h38720 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
38722 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h38720 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
38722 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h38722 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
38724 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h30145 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
30147 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h38722 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
38724 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_cm7.h38720 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
38722 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
DMIMX8MN6_ca53.h38734 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
38736 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h37532 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
37534 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h30137 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
30139 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h37532 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
37534 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h37532 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
37534 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h24628 #define LCDIF_CTRL2_TOG_RSRVD5_MASK 0xFF000000u macro
24630 … (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_RSRVD5_SHIFT))&LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h37532 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
37534 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h37532 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
37534 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h28768 #define LCDIF_CTRL2_TOG_RSRVD5_MASK 0xFF000000u macro
28770 … (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL2_TOG_RSRVD5_SHIFT))&LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM3/
DMIMX8MM3_cm4.h39423 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
39425 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h54503 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
54505 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM5/
DMIMX8MM5_cm4.h39423 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
39425 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM6/
DMIMX8MM6_cm4.h39423 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
39425 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM1/
DMIMX8MM1_cm4.h39423 #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) macro
39425 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)

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