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Searched refs:LCDIF_CTRL1_CLR_RSRVD0_MASK (Results 1 – 25 of 49) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h10888 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
10890 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h10889 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
10891 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h27665 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
27667 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h28187 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
28189 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h38166 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
38168 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h38164 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
38166 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h38164 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
38166 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h38166 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
38168 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h29717 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
29719 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h38166 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
38168 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_cm7.h38164 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
38166 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
DMIMX8MN6_ca53.h38178 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
38180 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h36976 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
36978 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h29709 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
29711 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h36976 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
36978 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h36976 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
36978 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h24394 #define LCDIF_CTRL1_CLR_RSRVD0_MASK 0xF8u macro
24396 … (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_CLR_RSRVD0_SHIFT))&LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h36976 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
36978 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h36976 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
36978 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h28534 #define LCDIF_CTRL1_CLR_RSRVD0_MASK 0xF8u macro
28536 … (((uint32_t)(((uint32_t)(x))<<LCDIF_CTRL1_CLR_RSRVD0_SHIFT))&LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM3/
DMIMX8MM3_cm4.h38867 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
38869 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h54075 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
54077 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM5/
DMIMX8MM5_cm4.h38867 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
38869 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM6/
DMIMX8MM6_cm4.h38867 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
38869 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM1/
DMIMX8MM1_cm4.h38867 #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) macro
38869 … (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)

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