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Searched refs:ITARGETSR (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core_AArch64/Include/
Dgic_v3.h131 …__IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers …
344 uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U)); in GIC_SetTarget()
345 GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U)); in GIC_SetTarget()
372 cpu_target = (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL; in GIC_GetTarget()
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_GIC.h323 … volatile uint32 ITARGETSR[248]; /* +0x0800 - RW - Interrupt Processor Targets Registers */ member