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Searched refs:ISR_STATE_MASK (Results 1 – 19 of 19) sorted by relevance

/hal_nxp-latest/s32/drivers/s32k3/Rte/src/
DSchM_Mcu.c52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */ macro
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
74 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
76 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
78 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
82 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
[all …]
DSchM_Fls.c52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */ macro
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
74 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
76 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
78 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
82 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
[all …]
DSchM_Pwm.c52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */ macro
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
74 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
76 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
78 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
82 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
[all …]
DSchM_Icu.c52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */ macro
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
74 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
76 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
78 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
82 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
[all …]
DSchM_Mcl.c52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */ macro
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
74 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
76 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
78 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
82 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
[all …]
DSchM_Adc.c52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */ macro
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
74 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
76 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
78 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
82 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
[all …]
/hal_nxp-latest/s32/drivers/s32k1/Rte/src/
DSchM_Mcu.c52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */ macro
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
74 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
76 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
78 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
82 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
[all …]
/hal_nxp-latest/s32/drivers/s32ze/Rte/src/
DSchM_Mcu.c52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */ macro
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
74 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
76 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
78 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
82 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
[all …]
DSchM_Mem_43_EXFLS.c52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */ macro
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
74 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
76 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
78 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
82 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
[all …]
DSchM_Platform.c52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */ macro
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
74 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
76 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
78 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
82 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
[all …]
DSchM_Spi.c52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */ macro
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
74 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
76 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
78 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
82 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
[all …]
DSchM_Uart.c52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */ macro
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
74 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
76 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
78 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
82 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
[all …]
DSchM_Can_43_CANEXCEL.c52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */ macro
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
74 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
76 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
78 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
82 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
[all …]
DSchM_Eth_43_NETC.c52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */ macro
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
74 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
76 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
78 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
82 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
[all …]
DSchM_Icu.c52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */ macro
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
74 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
76 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
78 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
82 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
[all …]
DSchM_Mcl.c52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */ macro
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
74 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
76 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
78 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
82 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
[all …]
DSchM_Pwm.c52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */ macro
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
74 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
76 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
78 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
82 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
[all …]
DSchM_EthSwt_43_NETC.c52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */ macro
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
74 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
76 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
78 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
82 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
[all …]
DSchM_Adc.c52 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */ macro
54 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
57 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
59 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
64 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
66 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
74 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
76 …_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK…
78 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
82 … #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
[all …]