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Searched refs:IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_cm4_core1.h71124 #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK (0x7FFF0000U) macro
71128 …)) << IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK)
DMIMX8QM6_cm4_core0.h71124 #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK (0x7FFF0000U) macro
71128 …)) << IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX3/
DMIMX8QX3_cm4.h94872 #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK (0x7FFF0000U) macro
94876 …)) << IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX4/
DMIMX8DX4_cm4.h94872 #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK (0x7FFF0000U) macro
94876 …)) << IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX3/
DMIMX8DX3_cm4.h94872 #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK (0x7FFF0000U) macro
94876 …)) << IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX6/
DMIMX8QX6_dsp.h98149 #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK (0x7FFF0000U) macro
98152 …)) << IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK)
DMIMX8QX6_cm4.h94874 #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK (0x7FFF0000U) macro
94878 …)) << IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX6/
DMIMX8DX6_cm4.h94874 #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK (0x7FFF0000U) macro
94878 …)) << IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX5/
DMIMX8QX5_cm4.h94873 #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK (0x7FFF0000U) macro
94877 …)) << IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX5/
DMIMX8DX5_cm4.h94874 #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK (0x7FFF0000U) macro
94878 …)) << IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX6/
DMIMX8UX6_cm4.h94875 #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK (0x7FFF0000U) macro
94879 …)) << IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX5/
DMIMX8UX5_cm4.h94875 #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK (0x7FFF0000U) macro
94879 …)) << IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX4/
DMIMX8QX4_cm4.h94871 #define IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK (0x7FFF0000U) macro
94875 …)) << IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_SHIFT)) & IRIS_MVPL_TCON1_SPG10POSON_SPGPSON_X10_MASK)