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Searched refs:IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_cm4_core1.h68897 #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT (17U) macro
68900 …N1_FGSRCR1_SREpOff(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT)…
DMIMX8QM6_cm4_core0.h68897 #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT (17U) macro
68900 …N1_FGSRCR1_SREpOff(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT)…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX3/
DMIMX8QX3_cm4.h92645 #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT (17U) macro
92648 …N1_FGSRCR1_SREpOff(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT)…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX4/
DMIMX8DX4_cm4.h92645 #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT (17U) macro
92648 …N1_FGSRCR1_SREpOff(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT)…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX3/
DMIMX8DX3_cm4.h92645 #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT (17U) macro
92648 …N1_FGSRCR1_SREpOff(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT)…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX6/
DMIMX8QX6_dsp.h95814 #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT (17U) macro
95816 …N1_FGSRCR1_SREpOff(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT)…
DMIMX8QX6_cm4.h92647 #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT (17U) macro
92650 …N1_FGSRCR1_SREpOff(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT)…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX6/
DMIMX8DX6_cm4.h92647 #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT (17U) macro
92650 …N1_FGSRCR1_SREpOff(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT)…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX5/
DMIMX8QX5_cm4.h92646 #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT (17U) macro
92649 …N1_FGSRCR1_SREpOff(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT)…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX5/
DMIMX8DX5_cm4.h92647 #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT (17U) macro
92650 …N1_FGSRCR1_SREpOff(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT)…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX6/
DMIMX8UX6_cm4.h92648 #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT (17U) macro
92651 …N1_FGSRCR1_SREpOff(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT)…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX5/
DMIMX8UX5_cm4.h92648 #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT (17U) macro
92651 …N1_FGSRCR1_SREpOff(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT)…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX4/
DMIMX8QX4_cm4.h92644 #define IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT (17U) macro
92647 …N1_FGSRCR1_SREpOff(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FRAMEGEN1_FGSRCR1_SREpOff_SHIFT)…