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Searched refs:IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_MASK (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_cm4_core1.h48955 #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_MASK (0x1F00U) macro
48962 …BUFFERMANAGEMENT_1_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurst…
DMIMX8QM6_cm4_core0.h48955 #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_MASK (0x1F00U) macro
48962 …BUFFERMANAGEMENT_1_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurst…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX3/
DMIMX8QX3_cm4.h72703 #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_MASK (0x1F00U) macro
72710 …BUFFERMANAGEMENT_1_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurst…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX4/
DMIMX8DX4_cm4.h72703 #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_MASK (0x1F00U) macro
72710 …BUFFERMANAGEMENT_1_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurst…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX3/
DMIMX8DX3_cm4.h72703 #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_MASK (0x1F00U) macro
72710 …BUFFERMANAGEMENT_1_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurst…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX6/
DMIMX8QX6_dsp.h75184 #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_MASK (0x1F00U) macro
75191 …BUFFERMANAGEMENT_1_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurst…
DMIMX8QX6_cm4.h72705 #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_MASK (0x1F00U) macro
72712 …BUFFERMANAGEMENT_1_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurst…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX6/
DMIMX8DX6_cm4.h72705 #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_MASK (0x1F00U) macro
72712 …BUFFERMANAGEMENT_1_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurst…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX5/
DMIMX8QX5_cm4.h72704 #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_MASK (0x1F00U) macro
72711 …BUFFERMANAGEMENT_1_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurst…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX5/
DMIMX8DX5_cm4.h72705 #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_MASK (0x1F00U) macro
72712 …BUFFERMANAGEMENT_1_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurst…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX6/
DMIMX8UX6_cm4.h72706 #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_MASK (0x1F00U) macro
72713 …BUFFERMANAGEMENT_1_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurst…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX5/
DMIMX8UX5_cm4.h72706 #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_MASK (0x1F00U) macro
72713 …BUFFERMANAGEMENT_1_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurst…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX4/
DMIMX8QX4_cm4.h72702 #define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_MASK (0x1F00U) macro
72709 …BUFFERMANAGEMENT_1_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurst…