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Searched refs:IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_MASK (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_cm4_core1.h45651 #define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_MASK (0xFFFFFFFFU) macro
45658 …TRL_INTERRUPTENABLE0_InterruptEnable0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable…
DMIMX8QM6_cm4_core0.h45651 #define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_MASK (0xFFFFFFFFU) macro
45658 …TRL_INTERRUPTENABLE0_InterruptEnable0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX3/
DMIMX8QX3_cm4.h69399 #define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_MASK (0xFFFFFFFFU) macro
69406 …TRL_INTERRUPTENABLE0_InterruptEnable0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX4/
DMIMX8DX4_cm4.h69399 #define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_MASK (0xFFFFFFFFU) macro
69406 …TRL_INTERRUPTENABLE0_InterruptEnable0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX3/
DMIMX8DX3_cm4.h69399 #define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_MASK (0xFFFFFFFFU) macro
69406 …TRL_INTERRUPTENABLE0_InterruptEnable0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX6/
DMIMX8QX6_dsp.h71705 #define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_MASK (0xFFFFFFFFU) macro
71712 …TRL_INTERRUPTENABLE0_InterruptEnable0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable…
DMIMX8QX6_cm4.h69401 #define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_MASK (0xFFFFFFFFU) macro
69408 …TRL_INTERRUPTENABLE0_InterruptEnable0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX6/
DMIMX8DX6_cm4.h69401 #define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_MASK (0xFFFFFFFFU) macro
69408 …TRL_INTERRUPTENABLE0_InterruptEnable0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX5/
DMIMX8QX5_cm4.h69400 #define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_MASK (0xFFFFFFFFU) macro
69407 …TRL_INTERRUPTENABLE0_InterruptEnable0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX5/
DMIMX8DX5_cm4.h69401 #define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_MASK (0xFFFFFFFFU) macro
69408 …TRL_INTERRUPTENABLE0_InterruptEnable0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX6/
DMIMX8UX6_cm4.h69402 #define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_MASK (0xFFFFFFFFU) macro
69409 …TRL_INTERRUPTENABLE0_InterruptEnable0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX5/
DMIMX8UX5_cm4.h69402 #define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_MASK (0xFFFFFFFFU) macro
69409 …TRL_INTERRUPTENABLE0_InterruptEnable0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX4/
DMIMX8QX4_cm4.h69398 #define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_MASK (0xFFFFFFFFU) macro
69405 …TRL_INTERRUPTENABLE0_InterruptEnable0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable…