1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_SMU_SEMA42.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_SMU_SEMA42 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_SMU_SEMA42_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_SMU_SEMA42_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SMU_SEMA42 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SMU_SEMA42_Peripheral_Access_Layer SMU_SEMA42 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SMU_SEMA42 - Size of Registers Arrays */ 72 #define SMU_SEMA42_GATE_COUNT 16u 73 74 /** SMU_SEMA42 - Register Layout Typedef */ 75 typedef struct { 76 __IO uint8_t GATE[SMU_SEMA42_GATE_COUNT]; /**< Gate, array offset: 0x0, array step: 0x1 */ 77 uint8_t RESERVED_0[50]; 78 union { /* offset: 0x42 */ 79 __I uint16_t R; /**< Reset Gate Read, offset: 0x42 */ 80 __O uint16_t W; /**< Reset Gate Write, offset: 0x42 */ 81 } RSTGT; 82 } SMU_SEMA42_Type, *SMU_SEMA42_MemMapPtr; 83 84 /** Number of instances of the SMU_SEMA42 module. */ 85 #define SMU_SEMA42_INSTANCE_COUNT (1u) 86 87 /* SMU_SEMA42 - Peripheral instance base addresses */ 88 /** Peripheral SMU__SEMA42 base address */ 89 #define IP_SMU__SEMA42_BASE (0x45230000u) 90 /** Peripheral SMU__SEMA42 base pointer */ 91 #define IP_SMU__SEMA42 ((SMU_SEMA42_Type *)IP_SMU__SEMA42_BASE) 92 /** Array initializer of SMU_SEMA42 peripheral base addresses */ 93 #define IP_SMU_SEMA42_BASE_ADDRS { IP_SMU__SEMA42_BASE } 94 /** Array initializer of SMU_SEMA42 peripheral base pointers */ 95 #define IP_SMU_SEMA42_BASE_PTRS { IP_SMU__SEMA42 } 96 97 /* ---------------------------------------------------------------------------- 98 -- SMU_SEMA42 Register Masks 99 ---------------------------------------------------------------------------- */ 100 101 /*! 102 * @addtogroup SMU_SEMA42_Register_Masks SMU_SEMA42 Register Masks 103 * @{ 104 */ 105 106 /*! @name GATE - Gate */ 107 /*! @{ */ 108 109 #define SMU_SEMA42_GATE_GTFSM_MASK (0xFU) 110 #define SMU_SEMA42_GATE_GTFSM_SHIFT (0U) 111 #define SMU_SEMA42_GATE_GTFSM_WIDTH (4U) 112 #define SMU_SEMA42_GATE_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SMU_SEMA42_GATE_GTFSM_SHIFT)) & SMU_SEMA42_GATE_GTFSM_MASK) 113 /*! @} */ 114 115 /*! @name R - Reset Gate Read */ 116 /*! @{ */ 117 118 #define SMU_SEMA42_R_RSTGTN_MASK (0xFFU) 119 #define SMU_SEMA42_R_RSTGTN_SHIFT (0U) 120 #define SMU_SEMA42_R_RSTGTN_WIDTH (8U) 121 #define SMU_SEMA42_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SMU_SEMA42_R_RSTGTN_SHIFT)) & SMU_SEMA42_R_RSTGTN_MASK) 122 123 #define SMU_SEMA42_R_RSTGMS_MASK (0xF00U) 124 #define SMU_SEMA42_R_RSTGMS_SHIFT (8U) 125 #define SMU_SEMA42_R_RSTGMS_WIDTH (4U) 126 #define SMU_SEMA42_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << SMU_SEMA42_R_RSTGMS_SHIFT)) & SMU_SEMA42_R_RSTGMS_MASK) 127 128 #define SMU_SEMA42_R_RSTGSM_MASK (0x3000U) 129 #define SMU_SEMA42_R_RSTGSM_SHIFT (12U) 130 #define SMU_SEMA42_R_RSTGSM_WIDTH (2U) 131 #define SMU_SEMA42_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << SMU_SEMA42_R_RSTGSM_SHIFT)) & SMU_SEMA42_R_RSTGSM_MASK) 132 /*! @} */ 133 134 /*! @name W - Reset Gate Write */ 135 /*! @{ */ 136 137 #define SMU_SEMA42_W_RSTGTN_MASK (0xFFU) 138 #define SMU_SEMA42_W_RSTGTN_SHIFT (0U) 139 #define SMU_SEMA42_W_RSTGTN_WIDTH (8U) 140 #define SMU_SEMA42_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SMU_SEMA42_W_RSTGTN_SHIFT)) & SMU_SEMA42_W_RSTGTN_MASK) 141 142 #define SMU_SEMA42_W_RSTGDP_MASK (0xFF00U) 143 #define SMU_SEMA42_W_RSTGDP_SHIFT (8U) 144 #define SMU_SEMA42_W_RSTGDP_WIDTH (8U) 145 #define SMU_SEMA42_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SMU_SEMA42_W_RSTGDP_SHIFT)) & SMU_SEMA42_W_RSTGDP_MASK) 146 /*! @} */ 147 148 /*! 149 * @} 150 */ /* end of group SMU_SEMA42_Register_Masks */ 151 152 /*! 153 * @} 154 */ /* end of group SMU_SEMA42_Peripheral_Access_Layer */ 155 156 #endif /* #if !defined(S32Z2_SMU_SEMA42_H_) */ 157
