1 /*
2  * Copyright 1997-2016 Freescale Semiconductor, Inc.
3  * Copyright 2016-2024 NXP
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*!
9  * @file S32Z2_RTU_GPR.h
10  * @version 2.3
11  * @date 2024-05-03
12  * @brief Peripheral Access Layer for S32Z2_RTU_GPR
13  *
14  * This file contains register definitions and macros for easy access to their
15  * bit fields.
16  *
17  * This file assumes LITTLE endian system.
18  */
19 
20 /**
21 * @page misra_violations MISRA-C:2012 violations
22 *
23 * @section [global]
24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
25 * The SoC header defines typedef for all modules.
26 *
27 * @section [global]
28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
29 * The SoC header defines macros for all modules and registers.
30 *
31 * @section [global]
32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
33 * These are generated macros used for accessing the bit-fields from registers.
34 *
35 * @section [global]
36 * Violates MISRA 2012 Required Rule 5.1, identifier clash
37 * The supported compilers use more than 31 significant characters for identifiers.
38 *
39 * @section [global]
40 * Violates MISRA 2012 Required Rule 5.2, identifier clash
41 * The supported compilers use more than 31 significant characters for identifiers.
42 *
43 * @section [global]
44 * Violates MISRA 2012 Required Rule 5.4, identifier clash
45 * The supported compilers use more than 31 significant characters for identifiers.
46 *
47 * @section [global]
48 * Violates MISRA 2012 Required Rule 5.5, identifier clash
49 * The supported compilers use more than 31 significant characters for identifiers.
50 *
51 * @section [global]
52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
53 * This type qualifier is needed to ensure correct I/O access and addressing.
54 */
55 
56 /* Prevention from multiple including the same memory map */
57 #if !defined(S32Z2_RTU_GPR_H_)  /* Check if memory map has not been already included */
58 #define S32Z2_RTU_GPR_H_
59 
60 #include "S32Z2_COMMON.h"
61 
62 /* ----------------------------------------------------------------------------
63    -- RTU_GPR Peripheral Access Layer
64    ---------------------------------------------------------------------------- */
65 
66 /*!
67  * @addtogroup RTU_GPR_Peripheral_Access_Layer RTU_GPR Peripheral Access Layer
68  * @{
69  */
70 
71 /** RTU_GPR - Register Layout Typedef */
72 typedef struct {
73   __IO uint32_t CFG_CORE;                          /**< Core Configuration, offset: 0x0 */
74   __IO uint32_t CFG_BUPERR_DIS0;                   /**< Bus Parity Error Disable Group0, offset: 0x4 */
75   __IO uint32_t CFG_BUPERR_DIS1;                   /**< Bus Parity Error Disable Group0, offset: 0x8 */
76   __IO uint32_t CFG_FD;                            /**< Core Fence and Drain Configuration, offset: 0xC */
77   __IO uint32_t CFG_CNTDV;                         /**< Generic Timer Count Divider Control, offset: 0x10 */
78   __IO uint32_t CFG_HALT;                          /**< Core Halt Control, offset: 0x14 */
79   uint8_t RESERVED_0[4];
80   __I  uint32_t STAT_FD;                           /**< Core Fence and Drain Status, offset: 0x1C */
81   uint8_t RESERVED_1[16];
82   __I  uint32_t STAT_WFI;                          /**< Core STANDBYWFI Status, offset: 0x30 */
83   __I  uint32_t STAT_WFE;                          /**< Core STANDBYWFE Status, offset: 0x34 */
84   __I  uint32_t STAT_WRSTREQ;                      /**< Core WARMRSTREQ Status, offset: 0x38 */
85   uint8_t RESERVED_2[4];
86   __I  uint32_t STAT_EVC0;                         /**< Core0 External Event Status, offset: 0x40 */
87   __I  uint32_t STAT_EVC1;                         /**< Core1 External Event Status, offset: 0x44 */
88   __I  uint32_t STAT_EVC2;                         /**< Core2 External Event Status, offset: 0x48 */
89   __I  uint32_t STAT_EVC3;                         /**< Core3 External Event Status, offset: 0x4C */
90   __I  uint32_t STAT_MERRPM0;                      /**< Primary Error Interface Memory Identifier Core0, offset: 0x50 */
91   __I  uint32_t STAT_MERRPX0;                      /**< Primary Error Interface Index Core0, offset: 0x54 */
92   __I  uint32_t STAT_MERRSM0;                      /**< Secondary Error Interface Memory Identifier Core0, offset: 0x58 */
93   __I  uint32_t STAT_MERRSX0;                      /**< Secondary Error Interface Index Core0, offset: 0x5C */
94   __I  uint32_t STAT_MERRPM1;                      /**< Primary Error Interface Memory Identifier Core1, offset: 0x60 */
95   __I  uint32_t STAT_MERRPX1;                      /**< Primary Error Interface Index Core1, offset: 0x64 */
96   __I  uint32_t STAT_MERRSM1;                      /**< Secondary Error Interface Memory Identifier Core1, offset: 0x68 */
97   __I  uint32_t STAT_MERRSX1;                      /**< Secondary Error Interface Index Core1, offset: 0x6C */
98   __I  uint32_t STAT_MERRPM2;                      /**< Primary Error Interface Memory Identifier Core2, offset: 0x70 */
99   __I  uint32_t STAT_MERRPX2;                      /**< Primary Error Interface Index Core2, offset: 0x74 */
100   __I  uint32_t STAT_MERRSM2;                      /**< Secondary Error Interface Memory Identifier Core2, offset: 0x78 */
101   __I  uint32_t STAT_MERRSX2;                      /**< Secondary Error Interface Index Core2, offset: 0x7C */
102   __I  uint32_t STAT_MERRPM3;                      /**< Primary Error Interface Memory Identifier Core3, offset: 0x80 */
103   __I  uint32_t STAT_MERRPX3;                      /**< Primary Error Interface Index Core3, offset: 0x84 */
104   __I  uint32_t STAT_MERRSM3;                      /**< Secondary Error Interface Memory Identifier Core3, offset: 0x88 */
105   __I  uint32_t STAT_MERRSX3;                      /**< Secondary Error Interface Index Core3, offset: 0x8C */
106   __I  uint32_t STAT_PMU0EV0;                      /**< PMU Event Core0 Group0, offset: 0x90 */
107   __I  uint32_t STAT_PMU1EV0;                      /**< PMU Event Core0 Group1, offset: 0x94 */
108   __I  uint32_t STAT_PMU0EV1;                      /**< PMU Event Core1 Group0, offset: 0x98 */
109   __I  uint32_t STAT_PMU1EV1;                      /**< PMU Event Core1 Group1, offset: 0x9C */
110   __I  uint32_t STAT_PMU0EV2;                      /**< PMU Event Core2 Group0, offset: 0xA0 */
111   __I  uint32_t STAT_PMU1EV2;                      /**< PMU Event Core2 Group1, offset: 0xA4 */
112   __I  uint32_t STAT_PMU0EV3;                      /**< PMU Event Core3 Group0, offset: 0xA8 */
113   __I  uint32_t STAT_PMU1EV3;                      /**< PMU Event Core3 Group1, offset: 0xAC */
114 } RTU_GPR_Type, *RTU_GPR_MemMapPtr;
115 
116 /** Number of instances of the RTU_GPR module. */
117 #define RTU_GPR_INSTANCE_COUNT                   (2u)
118 
119 /* RTU_GPR - Peripheral instance base addresses */
120 /** Peripheral RTU0__GPR base address */
121 #define IP_RTU0__GPR_BASE                        (0x76120000u)
122 /** Peripheral RTU0__GPR base pointer */
123 #define IP_RTU0__GPR                             ((RTU_GPR_Type *)IP_RTU0__GPR_BASE)
124 /** Peripheral RTU1__GPR base address */
125 #define IP_RTU1__GPR_BASE                        (0x76920000u)
126 /** Peripheral RTU1__GPR base pointer */
127 #define IP_RTU1__GPR                             ((RTU_GPR_Type *)IP_RTU1__GPR_BASE)
128 /** Array initializer of RTU_GPR peripheral base addresses */
129 #define IP_RTU_GPR_BASE_ADDRS                    { IP_RTU0__GPR_BASE, IP_RTU1__GPR_BASE }
130 /** Array initializer of RTU_GPR peripheral base pointers */
131 #define IP_RTU_GPR_BASE_PTRS                     { IP_RTU0__GPR, IP_RTU1__GPR }
132 
133 /* ----------------------------------------------------------------------------
134    -- RTU_GPR Register Masks
135    ---------------------------------------------------------------------------- */
136 
137 /*!
138  * @addtogroup RTU_GPR_Register_Masks RTU_GPR Register Masks
139  * @{
140  */
141 
142 /*! @name CFG_CORE - Core Configuration */
143 /*! @{ */
144 
145 #define RTU_GPR_CFG_CORE_SPLT_LCK_MASK           (0x1U)
146 #define RTU_GPR_CFG_CORE_SPLT_LCK_SHIFT          (0U)
147 #define RTU_GPR_CFG_CORE_SPLT_LCK_WIDTH          (1U)
148 #define RTU_GPR_CFG_CORE_SPLT_LCK(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_CORE_SPLT_LCK_SHIFT)) & RTU_GPR_CFG_CORE_SPLT_LCK_MASK)
149 
150 #define RTU_GPR_CFG_CORE_TCM_BT_MASK             (0x2U)
151 #define RTU_GPR_CFG_CORE_TCM_BT_SHIFT            (1U)
152 #define RTU_GPR_CFG_CORE_TCM_BT_WIDTH            (1U)
153 #define RTU_GPR_CFG_CORE_TCM_BT(x)               (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_CORE_TCM_BT_SHIFT)) & RTU_GPR_CFG_CORE_TCM_BT_MASK)
154 
155 #define RTU_GPR_CFG_CORE_THUMB_MASK              (0x4U)
156 #define RTU_GPR_CFG_CORE_THUMB_SHIFT             (2U)
157 #define RTU_GPR_CFG_CORE_THUMB_WIDTH             (1U)
158 #define RTU_GPR_CFG_CORE_THUMB(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_CORE_THUMB_SHIFT)) & RTU_GPR_CFG_CORE_THUMB_MASK)
159 
160 #define RTU_GPR_CFG_CORE_CAINV_MASK              (0x8U)
161 #define RTU_GPR_CFG_CORE_CAINV_SHIFT             (3U)
162 #define RTU_GPR_CFG_CORE_CAINV_WIDTH             (1U)
163 #define RTU_GPR_CFG_CORE_CAINV(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_CORE_CAINV_SHIFT)) & RTU_GPR_CFG_CORE_CAINV_MASK)
164 
165 #define RTU_GPR_CFG_CORE_INITREG_MASK            (0x10U)
166 #define RTU_GPR_CFG_CORE_INITREG_SHIFT           (4U)
167 #define RTU_GPR_CFG_CORE_INITREG_WIDTH           (1U)
168 #define RTU_GPR_CFG_CORE_INITREG(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_CORE_INITREG_SHIFT)) & RTU_GPR_CFG_CORE_INITREG_MASK)
169 
170 #define RTU_GPR_CFG_CORE_PMC_DIS_MASK            (0x100U)
171 #define RTU_GPR_CFG_CORE_PMC_DIS_SHIFT           (8U)
172 #define RTU_GPR_CFG_CORE_PMC_DIS_WIDTH           (1U)
173 #define RTU_GPR_CFG_CORE_PMC_DIS(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_CORE_PMC_DIS_SHIFT)) & RTU_GPR_CFG_CORE_PMC_DIS_MASK)
174 /*! @} */
175 
176 /*! @name CFG_BUPERR_DIS0 - Bus Parity Error Disable Group0 */
177 /*! @{ */
178 
179 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR0_MASK     (0x1U)
180 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR0_SHIFT    (0U)
181 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR0_WIDTH    (1U)
182 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR0(x)       (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR0_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR0_MASK)
183 
184 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR1_MASK     (0x2U)
185 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR1_SHIFT    (1U)
186 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR1_WIDTH    (1U)
187 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR1(x)       (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR1_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR1_MASK)
188 
189 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR2_MASK     (0x4U)
190 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR2_SHIFT    (2U)
191 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR2_WIDTH    (1U)
192 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR2(x)       (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR2_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR2_MASK)
193 
194 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR3_MASK     (0x8U)
195 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR3_SHIFT    (3U)
196 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR3_WIDTH    (1U)
197 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR3(x)       (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR3_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR3_MASK)
198 
199 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR4_MASK     (0x10U)
200 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR4_SHIFT    (4U)
201 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR4_WIDTH    (1U)
202 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR4(x)       (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR4_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR4_MASK)
203 
204 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR5_MASK     (0x20U)
205 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR5_SHIFT    (5U)
206 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR5_WIDTH    (1U)
207 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR5(x)       (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR5_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR5_MASK)
208 
209 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR6_MASK     (0x40U)
210 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR6_SHIFT    (6U)
211 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR6_WIDTH    (1U)
212 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR6(x)       (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR6_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR6_MASK)
213 
214 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR7_MASK     (0x80U)
215 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR7_SHIFT    (7U)
216 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR7_WIDTH    (1U)
217 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR7(x)       (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR7_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR7_MASK)
218 
219 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR8_MASK     (0x100U)
220 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR8_SHIFT    (8U)
221 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR8_WIDTH    (1U)
222 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR8(x)       (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR8_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR8_MASK)
223 
224 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR9_MASK     (0x200U)
225 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR9_SHIFT    (9U)
226 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR9_WIDTH    (1U)
227 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR9(x)       (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR9_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR9_MASK)
228 
229 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR10_MASK    (0x400U)
230 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR10_SHIFT   (10U)
231 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR10_WIDTH   (1U)
232 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR10(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR10_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR10_MASK)
233 
234 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR11_MASK    (0x800U)
235 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR11_SHIFT   (11U)
236 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR11_WIDTH   (1U)
237 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR11(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR11_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR11_MASK)
238 
239 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR12_MASK    (0x1000U)
240 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR12_SHIFT   (12U)
241 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR12_WIDTH   (1U)
242 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR12(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR12_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR12_MASK)
243 
244 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR13_MASK    (0x2000U)
245 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR13_SHIFT   (13U)
246 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR13_WIDTH   (1U)
247 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR13(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR13_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR13_MASK)
248 
249 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR14_MASK    (0x4000U)
250 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR14_SHIFT   (14U)
251 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR14_WIDTH   (1U)
252 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR14(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR14_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR14_MASK)
253 
254 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR15_MASK    (0x8000U)
255 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR15_SHIFT   (15U)
256 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR15_WIDTH   (1U)
257 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR15(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR15_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR15_MASK)
258 
259 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR16_MASK    (0x10000U)
260 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR16_SHIFT   (16U)
261 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR16_WIDTH   (1U)
262 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR16(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR16_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR16_MASK)
263 
264 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR17_MASK    (0x20000U)
265 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR17_SHIFT   (17U)
266 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR17_WIDTH   (1U)
267 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR17(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR17_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR17_MASK)
268 
269 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR18_MASK    (0x40000U)
270 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR18_SHIFT   (18U)
271 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR18_WIDTH   (1U)
272 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR18(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR18_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR18_MASK)
273 
274 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR19_MASK    (0x80000U)
275 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR19_SHIFT   (19U)
276 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR19_WIDTH   (1U)
277 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR19(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR19_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR19_MASK)
278 
279 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR20_MASK    (0x100000U)
280 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR20_SHIFT   (20U)
281 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR20_WIDTH   (1U)
282 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR20(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR20_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR20_MASK)
283 
284 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR21_MASK    (0x200000U)
285 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR21_SHIFT   (21U)
286 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR21_WIDTH   (1U)
287 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR21(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR21_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR21_MASK)
288 
289 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR22_MASK    (0x400000U)
290 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR22_SHIFT   (22U)
291 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR22_WIDTH   (1U)
292 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR22(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR22_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR22_MASK)
293 
294 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR23_MASK    (0x800000U)
295 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR23_SHIFT   (23U)
296 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR23_WIDTH   (1U)
297 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR23(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR23_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR23_MASK)
298 
299 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR24_MASK    (0x1000000U)
300 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR24_SHIFT   (24U)
301 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR24_WIDTH   (1U)
302 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR24(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR24_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR24_MASK)
303 
304 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR25_MASK    (0x2000000U)
305 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR25_SHIFT   (25U)
306 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR25_WIDTH   (1U)
307 #define RTU_GPR_CFG_BUPERR_DIS0_BUPERR25(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS0_BUPERR25_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS0_BUPERR25_MASK)
308 /*! @} */
309 
310 /*! @name CFG_BUPERR_DIS1 - Bus Parity Error Disable Group0 */
311 /*! @{ */
312 
313 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR0_MASK     (0x1U)
314 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR0_SHIFT    (0U)
315 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR0_WIDTH    (1U)
316 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR0(x)       (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR0_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR0_MASK)
317 
318 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR1_MASK     (0x2U)
319 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR1_SHIFT    (1U)
320 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR1_WIDTH    (1U)
321 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR1(x)       (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR1_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR1_MASK)
322 
323 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR2_MASK     (0x4U)
324 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR2_SHIFT    (2U)
325 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR2_WIDTH    (1U)
326 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR2(x)       (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR2_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR2_MASK)
327 
328 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR3_MASK     (0x8U)
329 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR3_SHIFT    (3U)
330 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR3_WIDTH    (1U)
331 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR3(x)       (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR3_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR3_MASK)
332 
333 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR4_MASK     (0x10U)
334 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR4_SHIFT    (4U)
335 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR4_WIDTH    (1U)
336 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR4(x)       (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR4_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR4_MASK)
337 
338 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR5_MASK     (0x20U)
339 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR5_SHIFT    (5U)
340 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR5_WIDTH    (1U)
341 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR5(x)       (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR5_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR5_MASK)
342 
343 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR6_MASK     (0x40U)
344 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR6_SHIFT    (6U)
345 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR6_WIDTH    (1U)
346 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR6(x)       (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR6_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR6_MASK)
347 
348 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR7_MASK     (0x80U)
349 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR7_SHIFT    (7U)
350 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR7_WIDTH    (1U)
351 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR7(x)       (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR7_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR7_MASK)
352 
353 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR8_MASK     (0x100U)
354 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR8_SHIFT    (8U)
355 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR8_WIDTH    (1U)
356 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR8(x)       (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR8_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR8_MASK)
357 
358 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR9_MASK     (0x200U)
359 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR9_SHIFT    (9U)
360 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR9_WIDTH    (1U)
361 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR9(x)       (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR9_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR9_MASK)
362 
363 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR10_MASK    (0x400U)
364 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR10_SHIFT   (10U)
365 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR10_WIDTH   (1U)
366 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR10(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR10_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR10_MASK)
367 
368 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR11_MASK    (0x800U)
369 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR11_SHIFT   (11U)
370 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR11_WIDTH   (1U)
371 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR11(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR11_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR11_MASK)
372 
373 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR12_MASK    (0x1000U)
374 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR12_SHIFT   (12U)
375 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR12_WIDTH   (1U)
376 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR12(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR12_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR12_MASK)
377 
378 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR13_MASK    (0x2000U)
379 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR13_SHIFT   (13U)
380 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR13_WIDTH   (1U)
381 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR13(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR13_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR13_MASK)
382 
383 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR14_MASK    (0x4000U)
384 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR14_SHIFT   (14U)
385 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR14_WIDTH   (1U)
386 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR14(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR14_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR14_MASK)
387 
388 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR15_MASK    (0x8000U)
389 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR15_SHIFT   (15U)
390 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR15_WIDTH   (1U)
391 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR15(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR15_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR15_MASK)
392 
393 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR16_MASK    (0x10000U)
394 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR16_SHIFT   (16U)
395 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR16_WIDTH   (1U)
396 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR16(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR16_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR16_MASK)
397 
398 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR17_MASK    (0x20000U)
399 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR17_SHIFT   (17U)
400 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR17_WIDTH   (1U)
401 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR17(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR17_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR17_MASK)
402 
403 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR18_MASK    (0x40000U)
404 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR18_SHIFT   (18U)
405 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR18_WIDTH   (1U)
406 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR18(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR18_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR18_MASK)
407 
408 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR19_MASK    (0x80000U)
409 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR19_SHIFT   (19U)
410 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR19_WIDTH   (1U)
411 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR19(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR19_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR19_MASK)
412 
413 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR20_MASK    (0x100000U)
414 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR20_SHIFT   (20U)
415 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR20_WIDTH   (1U)
416 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR20(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR20_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR20_MASK)
417 
418 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR21_MASK    (0x200000U)
419 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR21_SHIFT   (21U)
420 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR21_WIDTH   (1U)
421 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR21(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR21_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR21_MASK)
422 
423 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR22_MASK    (0x400000U)
424 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR22_SHIFT   (22U)
425 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR22_WIDTH   (1U)
426 #define RTU_GPR_CFG_BUPERR_DIS1_BUPERR22(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_BUPERR_DIS1_BUPERR22_SHIFT)) & RTU_GPR_CFG_BUPERR_DIS1_BUPERR22_MASK)
427 /*! @} */
428 
429 /*! @name CFG_FD - Core Fence and Drain Configuration */
430 /*! @{ */
431 
432 #define RTU_GPR_CFG_FD_MFDEN0_MASK               (0x1U)
433 #define RTU_GPR_CFG_FD_MFDEN0_SHIFT              (0U)
434 #define RTU_GPR_CFG_FD_MFDEN0_WIDTH              (1U)
435 #define RTU_GPR_CFG_FD_MFDEN0(x)                 (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_FD_MFDEN0_SHIFT)) & RTU_GPR_CFG_FD_MFDEN0_MASK)
436 
437 #define RTU_GPR_CFG_FD_MFDEN1_MASK               (0x2U)
438 #define RTU_GPR_CFG_FD_MFDEN1_SHIFT              (1U)
439 #define RTU_GPR_CFG_FD_MFDEN1_WIDTH              (1U)
440 #define RTU_GPR_CFG_FD_MFDEN1(x)                 (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_FD_MFDEN1_SHIFT)) & RTU_GPR_CFG_FD_MFDEN1_MASK)
441 
442 #define RTU_GPR_CFG_FD_MFDEN2_MASK               (0x4U)
443 #define RTU_GPR_CFG_FD_MFDEN2_SHIFT              (2U)
444 #define RTU_GPR_CFG_FD_MFDEN2_WIDTH              (1U)
445 #define RTU_GPR_CFG_FD_MFDEN2(x)                 (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_FD_MFDEN2_SHIFT)) & RTU_GPR_CFG_FD_MFDEN2_MASK)
446 
447 #define RTU_GPR_CFG_FD_MFDEN3_MASK               (0x8U)
448 #define RTU_GPR_CFG_FD_MFDEN3_SHIFT              (3U)
449 #define RTU_GPR_CFG_FD_MFDEN3_WIDTH              (1U)
450 #define RTU_GPR_CFG_FD_MFDEN3(x)                 (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_FD_MFDEN3_SHIFT)) & RTU_GPR_CFG_FD_MFDEN3_MASK)
451 
452 #define RTU_GPR_CFG_FD_FFDEN0_MASK               (0x10U)
453 #define RTU_GPR_CFG_FD_FFDEN0_SHIFT              (4U)
454 #define RTU_GPR_CFG_FD_FFDEN0_WIDTH              (1U)
455 #define RTU_GPR_CFG_FD_FFDEN0(x)                 (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_FD_FFDEN0_SHIFT)) & RTU_GPR_CFG_FD_FFDEN0_MASK)
456 
457 #define RTU_GPR_CFG_FD_FFDEN1_MASK               (0x20U)
458 #define RTU_GPR_CFG_FD_FFDEN1_SHIFT              (5U)
459 #define RTU_GPR_CFG_FD_FFDEN1_WIDTH              (1U)
460 #define RTU_GPR_CFG_FD_FFDEN1(x)                 (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_FD_FFDEN1_SHIFT)) & RTU_GPR_CFG_FD_FFDEN1_MASK)
461 
462 #define RTU_GPR_CFG_FD_FFDEN2_MASK               (0x40U)
463 #define RTU_GPR_CFG_FD_FFDEN2_SHIFT              (6U)
464 #define RTU_GPR_CFG_FD_FFDEN2_WIDTH              (1U)
465 #define RTU_GPR_CFG_FD_FFDEN2(x)                 (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_FD_FFDEN2_SHIFT)) & RTU_GPR_CFG_FD_FFDEN2_MASK)
466 
467 #define RTU_GPR_CFG_FD_FFDEN3_MASK               (0x80U)
468 #define RTU_GPR_CFG_FD_FFDEN3_SHIFT              (7U)
469 #define RTU_GPR_CFG_FD_FFDEN3_WIDTH              (1U)
470 #define RTU_GPR_CFG_FD_FFDEN3(x)                 (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_FD_FFDEN3_SHIFT)) & RTU_GPR_CFG_FD_FFDEN3_MASK)
471 
472 #define RTU_GPR_CFG_FD_LFDEN0_MASK               (0x100U)
473 #define RTU_GPR_CFG_FD_LFDEN0_SHIFT              (8U)
474 #define RTU_GPR_CFG_FD_LFDEN0_WIDTH              (1U)
475 #define RTU_GPR_CFG_FD_LFDEN0(x)                 (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_FD_LFDEN0_SHIFT)) & RTU_GPR_CFG_FD_LFDEN0_MASK)
476 
477 #define RTU_GPR_CFG_FD_LFDEN1_MASK               (0x200U)
478 #define RTU_GPR_CFG_FD_LFDEN1_SHIFT              (9U)
479 #define RTU_GPR_CFG_FD_LFDEN1_WIDTH              (1U)
480 #define RTU_GPR_CFG_FD_LFDEN1(x)                 (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_FD_LFDEN1_SHIFT)) & RTU_GPR_CFG_FD_LFDEN1_MASK)
481 
482 #define RTU_GPR_CFG_FD_LFDEN2_MASK               (0x400U)
483 #define RTU_GPR_CFG_FD_LFDEN2_SHIFT              (10U)
484 #define RTU_GPR_CFG_FD_LFDEN2_WIDTH              (1U)
485 #define RTU_GPR_CFG_FD_LFDEN2(x)                 (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_FD_LFDEN2_SHIFT)) & RTU_GPR_CFG_FD_LFDEN2_MASK)
486 
487 #define RTU_GPR_CFG_FD_LFDEN3_MASK               (0x800U)
488 #define RTU_GPR_CFG_FD_LFDEN3_SHIFT              (11U)
489 #define RTU_GPR_CFG_FD_LFDEN3_WIDTH              (1U)
490 #define RTU_GPR_CFG_FD_LFDEN3(x)                 (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_FD_LFDEN3_SHIFT)) & RTU_GPR_CFG_FD_LFDEN3_MASK)
491 
492 #define RTU_GPR_CFG_FD_SFDEN_MASK                (0x10000U)
493 #define RTU_GPR_CFG_FD_SFDEN_SHIFT               (16U)
494 #define RTU_GPR_CFG_FD_SFDEN_WIDTH               (1U)
495 #define RTU_GPR_CFG_FD_SFDEN(x)                  (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_FD_SFDEN_SHIFT)) & RTU_GPR_CFG_FD_SFDEN_MASK)
496 
497 #define RTU_GPR_CFG_FD_ISOLEN0_MASK              (0x10000000U)
498 #define RTU_GPR_CFG_FD_ISOLEN0_SHIFT             (28U)
499 #define RTU_GPR_CFG_FD_ISOLEN0_WIDTH             (1U)
500 #define RTU_GPR_CFG_FD_ISOLEN0(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_FD_ISOLEN0_SHIFT)) & RTU_GPR_CFG_FD_ISOLEN0_MASK)
501 
502 #define RTU_GPR_CFG_FD_ISOLEN1_MASK              (0x20000000U)
503 #define RTU_GPR_CFG_FD_ISOLEN1_SHIFT             (29U)
504 #define RTU_GPR_CFG_FD_ISOLEN1_WIDTH             (1U)
505 #define RTU_GPR_CFG_FD_ISOLEN1(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_FD_ISOLEN1_SHIFT)) & RTU_GPR_CFG_FD_ISOLEN1_MASK)
506 
507 #define RTU_GPR_CFG_FD_ISOLEN2_MASK              (0x40000000U)
508 #define RTU_GPR_CFG_FD_ISOLEN2_SHIFT             (30U)
509 #define RTU_GPR_CFG_FD_ISOLEN2_WIDTH             (1U)
510 #define RTU_GPR_CFG_FD_ISOLEN2(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_FD_ISOLEN2_SHIFT)) & RTU_GPR_CFG_FD_ISOLEN2_MASK)
511 
512 #define RTU_GPR_CFG_FD_ISOLEN3_MASK              (0x80000000U)
513 #define RTU_GPR_CFG_FD_ISOLEN3_SHIFT             (31U)
514 #define RTU_GPR_CFG_FD_ISOLEN3_WIDTH             (1U)
515 #define RTU_GPR_CFG_FD_ISOLEN3(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_FD_ISOLEN3_SHIFT)) & RTU_GPR_CFG_FD_ISOLEN3_MASK)
516 /*! @} */
517 
518 /*! @name CFG_CNTDV - Generic Timer Count Divider Control */
519 /*! @{ */
520 
521 #define RTU_GPR_CFG_CNTDV_CNTDV_MASK             (0x7U)
522 #define RTU_GPR_CFG_CNTDV_CNTDV_SHIFT            (0U)
523 #define RTU_GPR_CFG_CNTDV_CNTDV_WIDTH            (3U)
524 #define RTU_GPR_CFG_CNTDV_CNTDV(x)               (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_CNTDV_CNTDV_SHIFT)) & RTU_GPR_CFG_CNTDV_CNTDV_MASK)
525 /*! @} */
526 
527 /*! @name CFG_HALT - Core Halt Control */
528 /*! @{ */
529 
530 #define RTU_GPR_CFG_HALT_HALT0_MASK              (0x1U)
531 #define RTU_GPR_CFG_HALT_HALT0_SHIFT             (0U)
532 #define RTU_GPR_CFG_HALT_HALT0_WIDTH             (1U)
533 #define RTU_GPR_CFG_HALT_HALT0(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_HALT_HALT0_SHIFT)) & RTU_GPR_CFG_HALT_HALT0_MASK)
534 
535 #define RTU_GPR_CFG_HALT_HALT1_MASK              (0x2U)
536 #define RTU_GPR_CFG_HALT_HALT1_SHIFT             (1U)
537 #define RTU_GPR_CFG_HALT_HALT1_WIDTH             (1U)
538 #define RTU_GPR_CFG_HALT_HALT1(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_HALT_HALT1_SHIFT)) & RTU_GPR_CFG_HALT_HALT1_MASK)
539 
540 #define RTU_GPR_CFG_HALT_HALT2_MASK              (0x4U)
541 #define RTU_GPR_CFG_HALT_HALT2_SHIFT             (2U)
542 #define RTU_GPR_CFG_HALT_HALT2_WIDTH             (1U)
543 #define RTU_GPR_CFG_HALT_HALT2(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_HALT_HALT2_SHIFT)) & RTU_GPR_CFG_HALT_HALT2_MASK)
544 
545 #define RTU_GPR_CFG_HALT_HALT3_MASK              (0x8U)
546 #define RTU_GPR_CFG_HALT_HALT3_SHIFT             (3U)
547 #define RTU_GPR_CFG_HALT_HALT3_WIDTH             (1U)
548 #define RTU_GPR_CFG_HALT_HALT3(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_CFG_HALT_HALT3_SHIFT)) & RTU_GPR_CFG_HALT_HALT3_MASK)
549 /*! @} */
550 
551 /*! @name STAT_FD - Core Fence and Drain Status */
552 /*! @{ */
553 
554 #define RTU_GPR_STAT_FD_MFDID0_MASK              (0x1U)
555 #define RTU_GPR_STAT_FD_MFDID0_SHIFT             (0U)
556 #define RTU_GPR_STAT_FD_MFDID0_WIDTH             (1U)
557 #define RTU_GPR_STAT_FD_MFDID0(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_FD_MFDID0_SHIFT)) & RTU_GPR_STAT_FD_MFDID0_MASK)
558 
559 #define RTU_GPR_STAT_FD_MFDID1_MASK              (0x2U)
560 #define RTU_GPR_STAT_FD_MFDID1_SHIFT             (1U)
561 #define RTU_GPR_STAT_FD_MFDID1_WIDTH             (1U)
562 #define RTU_GPR_STAT_FD_MFDID1(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_FD_MFDID1_SHIFT)) & RTU_GPR_STAT_FD_MFDID1_MASK)
563 
564 #define RTU_GPR_STAT_FD_MFDID2_MASK              (0x4U)
565 #define RTU_GPR_STAT_FD_MFDID2_SHIFT             (2U)
566 #define RTU_GPR_STAT_FD_MFDID2_WIDTH             (1U)
567 #define RTU_GPR_STAT_FD_MFDID2(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_FD_MFDID2_SHIFT)) & RTU_GPR_STAT_FD_MFDID2_MASK)
568 
569 #define RTU_GPR_STAT_FD_MFDID3_MASK              (0x8U)
570 #define RTU_GPR_STAT_FD_MFDID3_SHIFT             (3U)
571 #define RTU_GPR_STAT_FD_MFDID3_WIDTH             (1U)
572 #define RTU_GPR_STAT_FD_MFDID3(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_FD_MFDID3_SHIFT)) & RTU_GPR_STAT_FD_MFDID3_MASK)
573 
574 #define RTU_GPR_STAT_FD_FFDID0_MASK              (0x10U)
575 #define RTU_GPR_STAT_FD_FFDID0_SHIFT             (4U)
576 #define RTU_GPR_STAT_FD_FFDID0_WIDTH             (1U)
577 #define RTU_GPR_STAT_FD_FFDID0(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_FD_FFDID0_SHIFT)) & RTU_GPR_STAT_FD_FFDID0_MASK)
578 
579 #define RTU_GPR_STAT_FD_FFDID1_MASK              (0x20U)
580 #define RTU_GPR_STAT_FD_FFDID1_SHIFT             (5U)
581 #define RTU_GPR_STAT_FD_FFDID1_WIDTH             (1U)
582 #define RTU_GPR_STAT_FD_FFDID1(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_FD_FFDID1_SHIFT)) & RTU_GPR_STAT_FD_FFDID1_MASK)
583 
584 #define RTU_GPR_STAT_FD_FFDID2_MASK              (0x40U)
585 #define RTU_GPR_STAT_FD_FFDID2_SHIFT             (6U)
586 #define RTU_GPR_STAT_FD_FFDID2_WIDTH             (1U)
587 #define RTU_GPR_STAT_FD_FFDID2(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_FD_FFDID2_SHIFT)) & RTU_GPR_STAT_FD_FFDID2_MASK)
588 
589 #define RTU_GPR_STAT_FD_FFDID3_MASK              (0x80U)
590 #define RTU_GPR_STAT_FD_FFDID3_SHIFT             (7U)
591 #define RTU_GPR_STAT_FD_FFDID3_WIDTH             (1U)
592 #define RTU_GPR_STAT_FD_FFDID3(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_FD_FFDID3_SHIFT)) & RTU_GPR_STAT_FD_FFDID3_MASK)
593 
594 #define RTU_GPR_STAT_FD_LFDID0_MASK              (0x100U)
595 #define RTU_GPR_STAT_FD_LFDID0_SHIFT             (8U)
596 #define RTU_GPR_STAT_FD_LFDID0_WIDTH             (1U)
597 #define RTU_GPR_STAT_FD_LFDID0(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_FD_LFDID0_SHIFT)) & RTU_GPR_STAT_FD_LFDID0_MASK)
598 
599 #define RTU_GPR_STAT_FD_LFDID1_MASK              (0x200U)
600 #define RTU_GPR_STAT_FD_LFDID1_SHIFT             (9U)
601 #define RTU_GPR_STAT_FD_LFDID1_WIDTH             (1U)
602 #define RTU_GPR_STAT_FD_LFDID1(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_FD_LFDID1_SHIFT)) & RTU_GPR_STAT_FD_LFDID1_MASK)
603 
604 #define RTU_GPR_STAT_FD_LFDID2_MASK              (0x400U)
605 #define RTU_GPR_STAT_FD_LFDID2_SHIFT             (10U)
606 #define RTU_GPR_STAT_FD_LFDID2_WIDTH             (1U)
607 #define RTU_GPR_STAT_FD_LFDID2(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_FD_LFDID2_SHIFT)) & RTU_GPR_STAT_FD_LFDID2_MASK)
608 
609 #define RTU_GPR_STAT_FD_LFDID3_MASK              (0x800U)
610 #define RTU_GPR_STAT_FD_LFDID3_SHIFT             (11U)
611 #define RTU_GPR_STAT_FD_LFDID3_WIDTH             (1U)
612 #define RTU_GPR_STAT_FD_LFDID3(x)                (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_FD_LFDID3_SHIFT)) & RTU_GPR_STAT_FD_LFDID3_MASK)
613 
614 #define RTU_GPR_STAT_FD_SFDID_MASK               (0x10000U)
615 #define RTU_GPR_STAT_FD_SFDID_SHIFT              (16U)
616 #define RTU_GPR_STAT_FD_SFDID_WIDTH              (1U)
617 #define RTU_GPR_STAT_FD_SFDID(x)                 (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_FD_SFDID_SHIFT)) & RTU_GPR_STAT_FD_SFDID_MASK)
618 /*! @} */
619 
620 /*! @name STAT_WFI - Core STANDBYWFI Status */
621 /*! @{ */
622 
623 #define RTU_GPR_STAT_WFI_WFI0_MASK               (0x1U)
624 #define RTU_GPR_STAT_WFI_WFI0_SHIFT              (0U)
625 #define RTU_GPR_STAT_WFI_WFI0_WIDTH              (1U)
626 #define RTU_GPR_STAT_WFI_WFI0(x)                 (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_WFI_WFI0_SHIFT)) & RTU_GPR_STAT_WFI_WFI0_MASK)
627 
628 #define RTU_GPR_STAT_WFI_WFI1_MASK               (0x2U)
629 #define RTU_GPR_STAT_WFI_WFI1_SHIFT              (1U)
630 #define RTU_GPR_STAT_WFI_WFI1_WIDTH              (1U)
631 #define RTU_GPR_STAT_WFI_WFI1(x)                 (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_WFI_WFI1_SHIFT)) & RTU_GPR_STAT_WFI_WFI1_MASK)
632 
633 #define RTU_GPR_STAT_WFI_WFI2_MASK               (0x4U)
634 #define RTU_GPR_STAT_WFI_WFI2_SHIFT              (2U)
635 #define RTU_GPR_STAT_WFI_WFI2_WIDTH              (1U)
636 #define RTU_GPR_STAT_WFI_WFI2(x)                 (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_WFI_WFI2_SHIFT)) & RTU_GPR_STAT_WFI_WFI2_MASK)
637 
638 #define RTU_GPR_STAT_WFI_WFI3_MASK               (0x8U)
639 #define RTU_GPR_STAT_WFI_WFI3_SHIFT              (3U)
640 #define RTU_GPR_STAT_WFI_WFI3_WIDTH              (1U)
641 #define RTU_GPR_STAT_WFI_WFI3(x)                 (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_WFI_WFI3_SHIFT)) & RTU_GPR_STAT_WFI_WFI3_MASK)
642 /*! @} */
643 
644 /*! @name STAT_WFE - Core STANDBYWFE Status */
645 /*! @{ */
646 
647 #define RTU_GPR_STAT_WFE_WFE0_MASK               (0x1U)
648 #define RTU_GPR_STAT_WFE_WFE0_SHIFT              (0U)
649 #define RTU_GPR_STAT_WFE_WFE0_WIDTH              (1U)
650 #define RTU_GPR_STAT_WFE_WFE0(x)                 (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_WFE_WFE0_SHIFT)) & RTU_GPR_STAT_WFE_WFE0_MASK)
651 
652 #define RTU_GPR_STAT_WFE_WFE1_MASK               (0x2U)
653 #define RTU_GPR_STAT_WFE_WFE1_SHIFT              (1U)
654 #define RTU_GPR_STAT_WFE_WFE1_WIDTH              (1U)
655 #define RTU_GPR_STAT_WFE_WFE1(x)                 (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_WFE_WFE1_SHIFT)) & RTU_GPR_STAT_WFE_WFE1_MASK)
656 
657 #define RTU_GPR_STAT_WFE_WFE2_MASK               (0x4U)
658 #define RTU_GPR_STAT_WFE_WFE2_SHIFT              (2U)
659 #define RTU_GPR_STAT_WFE_WFE2_WIDTH              (1U)
660 #define RTU_GPR_STAT_WFE_WFE2(x)                 (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_WFE_WFE2_SHIFT)) & RTU_GPR_STAT_WFE_WFE2_MASK)
661 
662 #define RTU_GPR_STAT_WFE_WFE3_MASK               (0x8U)
663 #define RTU_GPR_STAT_WFE_WFE3_SHIFT              (3U)
664 #define RTU_GPR_STAT_WFE_WFE3_WIDTH              (1U)
665 #define RTU_GPR_STAT_WFE_WFE3(x)                 (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_WFE_WFE3_SHIFT)) & RTU_GPR_STAT_WFE_WFE3_MASK)
666 /*! @} */
667 
668 /*! @name STAT_WRSTREQ - Core WARMRSTREQ Status */
669 /*! @{ */
670 
671 #define RTU_GPR_STAT_WRSTREQ_WARMRSTREQ0_MASK    (0x1U)
672 #define RTU_GPR_STAT_WRSTREQ_WARMRSTREQ0_SHIFT   (0U)
673 #define RTU_GPR_STAT_WRSTREQ_WARMRSTREQ0_WIDTH   (1U)
674 #define RTU_GPR_STAT_WRSTREQ_WARMRSTREQ0(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_WRSTREQ_WARMRSTREQ0_SHIFT)) & RTU_GPR_STAT_WRSTREQ_WARMRSTREQ0_MASK)
675 
676 #define RTU_GPR_STAT_WRSTREQ_WARMRSTREQ1_MASK    (0x2U)
677 #define RTU_GPR_STAT_WRSTREQ_WARMRSTREQ1_SHIFT   (1U)
678 #define RTU_GPR_STAT_WRSTREQ_WARMRSTREQ1_WIDTH   (1U)
679 #define RTU_GPR_STAT_WRSTREQ_WARMRSTREQ1(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_WRSTREQ_WARMRSTREQ1_SHIFT)) & RTU_GPR_STAT_WRSTREQ_WARMRSTREQ1_MASK)
680 
681 #define RTU_GPR_STAT_WRSTREQ_WARMRSTREQ2_MASK    (0x4U)
682 #define RTU_GPR_STAT_WRSTREQ_WARMRSTREQ2_SHIFT   (2U)
683 #define RTU_GPR_STAT_WRSTREQ_WARMRSTREQ2_WIDTH   (1U)
684 #define RTU_GPR_STAT_WRSTREQ_WARMRSTREQ2(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_WRSTREQ_WARMRSTREQ2_SHIFT)) & RTU_GPR_STAT_WRSTREQ_WARMRSTREQ2_MASK)
685 
686 #define RTU_GPR_STAT_WRSTREQ_WARMRSTREQ3_MASK    (0x8U)
687 #define RTU_GPR_STAT_WRSTREQ_WARMRSTREQ3_SHIFT   (3U)
688 #define RTU_GPR_STAT_WRSTREQ_WARMRSTREQ3_WIDTH   (1U)
689 #define RTU_GPR_STAT_WRSTREQ_WARMRSTREQ3(x)      (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_WRSTREQ_WARMRSTREQ3_SHIFT)) & RTU_GPR_STAT_WRSTREQ_WARMRSTREQ3_MASK)
690 /*! @} */
691 
692 /*! @name STAT_EVC0 - Core0 External Event Status */
693 /*! @{ */
694 
695 #define RTU_GPR_STAT_EVC0_C0_EV0_MASK            (0x1U)
696 #define RTU_GPR_STAT_EVC0_C0_EV0_SHIFT           (0U)
697 #define RTU_GPR_STAT_EVC0_C0_EV0_WIDTH           (1U)
698 #define RTU_GPR_STAT_EVC0_C0_EV0(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV0_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV0_MASK)
699 
700 #define RTU_GPR_STAT_EVC0_C0_EV1_MASK            (0x2U)
701 #define RTU_GPR_STAT_EVC0_C0_EV1_SHIFT           (1U)
702 #define RTU_GPR_STAT_EVC0_C0_EV1_WIDTH           (1U)
703 #define RTU_GPR_STAT_EVC0_C0_EV1(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV1_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV1_MASK)
704 
705 #define RTU_GPR_STAT_EVC0_C0_EV2_MASK            (0x4U)
706 #define RTU_GPR_STAT_EVC0_C0_EV2_SHIFT           (2U)
707 #define RTU_GPR_STAT_EVC0_C0_EV2_WIDTH           (1U)
708 #define RTU_GPR_STAT_EVC0_C0_EV2(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV2_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV2_MASK)
709 
710 #define RTU_GPR_STAT_EVC0_C0_EV3_MASK            (0x8U)
711 #define RTU_GPR_STAT_EVC0_C0_EV3_SHIFT           (3U)
712 #define RTU_GPR_STAT_EVC0_C0_EV3_WIDTH           (1U)
713 #define RTU_GPR_STAT_EVC0_C0_EV3(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV3_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV3_MASK)
714 
715 #define RTU_GPR_STAT_EVC0_C0_EV4_MASK            (0x10U)
716 #define RTU_GPR_STAT_EVC0_C0_EV4_SHIFT           (4U)
717 #define RTU_GPR_STAT_EVC0_C0_EV4_WIDTH           (1U)
718 #define RTU_GPR_STAT_EVC0_C0_EV4(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV4_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV4_MASK)
719 
720 #define RTU_GPR_STAT_EVC0_C0_EV5_MASK            (0x20U)
721 #define RTU_GPR_STAT_EVC0_C0_EV5_SHIFT           (5U)
722 #define RTU_GPR_STAT_EVC0_C0_EV5_WIDTH           (1U)
723 #define RTU_GPR_STAT_EVC0_C0_EV5(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV5_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV5_MASK)
724 
725 #define RTU_GPR_STAT_EVC0_C0_EV6_MASK            (0x40U)
726 #define RTU_GPR_STAT_EVC0_C0_EV6_SHIFT           (6U)
727 #define RTU_GPR_STAT_EVC0_C0_EV6_WIDTH           (1U)
728 #define RTU_GPR_STAT_EVC0_C0_EV6(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV6_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV6_MASK)
729 
730 #define RTU_GPR_STAT_EVC0_C0_EV7_MASK            (0x80U)
731 #define RTU_GPR_STAT_EVC0_C0_EV7_SHIFT           (7U)
732 #define RTU_GPR_STAT_EVC0_C0_EV7_WIDTH           (1U)
733 #define RTU_GPR_STAT_EVC0_C0_EV7(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV7_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV7_MASK)
734 
735 #define RTU_GPR_STAT_EVC0_C0_EV8_MASK            (0x100U)
736 #define RTU_GPR_STAT_EVC0_C0_EV8_SHIFT           (8U)
737 #define RTU_GPR_STAT_EVC0_C0_EV8_WIDTH           (1U)
738 #define RTU_GPR_STAT_EVC0_C0_EV8(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV8_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV8_MASK)
739 
740 #define RTU_GPR_STAT_EVC0_C0_EV9_MASK            (0x200U)
741 #define RTU_GPR_STAT_EVC0_C0_EV9_SHIFT           (9U)
742 #define RTU_GPR_STAT_EVC0_C0_EV9_WIDTH           (1U)
743 #define RTU_GPR_STAT_EVC0_C0_EV9(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV9_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV9_MASK)
744 
745 #define RTU_GPR_STAT_EVC0_C0_EV10_MASK           (0x400U)
746 #define RTU_GPR_STAT_EVC0_C0_EV10_SHIFT          (10U)
747 #define RTU_GPR_STAT_EVC0_C0_EV10_WIDTH          (1U)
748 #define RTU_GPR_STAT_EVC0_C0_EV10(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV10_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV10_MASK)
749 
750 #define RTU_GPR_STAT_EVC0_C0_EV11_MASK           (0x800U)
751 #define RTU_GPR_STAT_EVC0_C0_EV11_SHIFT          (11U)
752 #define RTU_GPR_STAT_EVC0_C0_EV11_WIDTH          (1U)
753 #define RTU_GPR_STAT_EVC0_C0_EV11(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV11_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV11_MASK)
754 
755 #define RTU_GPR_STAT_EVC0_C0_EV12_MASK           (0x1000U)
756 #define RTU_GPR_STAT_EVC0_C0_EV12_SHIFT          (12U)
757 #define RTU_GPR_STAT_EVC0_C0_EV12_WIDTH          (1U)
758 #define RTU_GPR_STAT_EVC0_C0_EV12(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV12_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV12_MASK)
759 
760 #define RTU_GPR_STAT_EVC0_C0_EV13_MASK           (0x2000U)
761 #define RTU_GPR_STAT_EVC0_C0_EV13_SHIFT          (13U)
762 #define RTU_GPR_STAT_EVC0_C0_EV13_WIDTH          (1U)
763 #define RTU_GPR_STAT_EVC0_C0_EV13(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV13_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV13_MASK)
764 
765 #define RTU_GPR_STAT_EVC0_C0_EV14_MASK           (0x4000U)
766 #define RTU_GPR_STAT_EVC0_C0_EV14_SHIFT          (14U)
767 #define RTU_GPR_STAT_EVC0_C0_EV14_WIDTH          (1U)
768 #define RTU_GPR_STAT_EVC0_C0_EV14(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV14_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV14_MASK)
769 
770 #define RTU_GPR_STAT_EVC0_C0_EV15_MASK           (0x8000U)
771 #define RTU_GPR_STAT_EVC0_C0_EV15_SHIFT          (15U)
772 #define RTU_GPR_STAT_EVC0_C0_EV15_WIDTH          (1U)
773 #define RTU_GPR_STAT_EVC0_C0_EV15(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV15_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV15_MASK)
774 
775 #define RTU_GPR_STAT_EVC0_C0_EV16_MASK           (0x10000U)
776 #define RTU_GPR_STAT_EVC0_C0_EV16_SHIFT          (16U)
777 #define RTU_GPR_STAT_EVC0_C0_EV16_WIDTH          (1U)
778 #define RTU_GPR_STAT_EVC0_C0_EV16(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV16_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV16_MASK)
779 
780 #define RTU_GPR_STAT_EVC0_C0_EV17_MASK           (0x20000U)
781 #define RTU_GPR_STAT_EVC0_C0_EV17_SHIFT          (17U)
782 #define RTU_GPR_STAT_EVC0_C0_EV17_WIDTH          (1U)
783 #define RTU_GPR_STAT_EVC0_C0_EV17(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV17_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV17_MASK)
784 
785 #define RTU_GPR_STAT_EVC0_C0_EV18_MASK           (0x40000U)
786 #define RTU_GPR_STAT_EVC0_C0_EV18_SHIFT          (18U)
787 #define RTU_GPR_STAT_EVC0_C0_EV18_WIDTH          (1U)
788 #define RTU_GPR_STAT_EVC0_C0_EV18(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV18_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV18_MASK)
789 
790 #define RTU_GPR_STAT_EVC0_C0_EV19_MASK           (0x80000U)
791 #define RTU_GPR_STAT_EVC0_C0_EV19_SHIFT          (19U)
792 #define RTU_GPR_STAT_EVC0_C0_EV19_WIDTH          (1U)
793 #define RTU_GPR_STAT_EVC0_C0_EV19(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV19_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV19_MASK)
794 
795 #define RTU_GPR_STAT_EVC0_C0_EV20_MASK           (0x100000U)
796 #define RTU_GPR_STAT_EVC0_C0_EV20_SHIFT          (20U)
797 #define RTU_GPR_STAT_EVC0_C0_EV20_WIDTH          (1U)
798 #define RTU_GPR_STAT_EVC0_C0_EV20(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV20_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV20_MASK)
799 
800 #define RTU_GPR_STAT_EVC0_C0_EV21_MASK           (0x200000U)
801 #define RTU_GPR_STAT_EVC0_C0_EV21_SHIFT          (21U)
802 #define RTU_GPR_STAT_EVC0_C0_EV21_WIDTH          (1U)
803 #define RTU_GPR_STAT_EVC0_C0_EV21(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV21_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV21_MASK)
804 
805 #define RTU_GPR_STAT_EVC0_C0_EV22_MASK           (0x400000U)
806 #define RTU_GPR_STAT_EVC0_C0_EV22_SHIFT          (22U)
807 #define RTU_GPR_STAT_EVC0_C0_EV22_WIDTH          (1U)
808 #define RTU_GPR_STAT_EVC0_C0_EV22(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV22_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV22_MASK)
809 
810 #define RTU_GPR_STAT_EVC0_C0_EV23_MASK           (0x800000U)
811 #define RTU_GPR_STAT_EVC0_C0_EV23_SHIFT          (23U)
812 #define RTU_GPR_STAT_EVC0_C0_EV23_WIDTH          (1U)
813 #define RTU_GPR_STAT_EVC0_C0_EV23(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV23_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV23_MASK)
814 
815 #define RTU_GPR_STAT_EVC0_C0_EV24_MASK           (0x1000000U)
816 #define RTU_GPR_STAT_EVC0_C0_EV24_SHIFT          (24U)
817 #define RTU_GPR_STAT_EVC0_C0_EV24_WIDTH          (1U)
818 #define RTU_GPR_STAT_EVC0_C0_EV24(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV24_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV24_MASK)
819 
820 #define RTU_GPR_STAT_EVC0_C0_EV25_MASK           (0x2000000U)
821 #define RTU_GPR_STAT_EVC0_C0_EV25_SHIFT          (25U)
822 #define RTU_GPR_STAT_EVC0_C0_EV25_WIDTH          (1U)
823 #define RTU_GPR_STAT_EVC0_C0_EV25(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC0_C0_EV25_SHIFT)) & RTU_GPR_STAT_EVC0_C0_EV25_MASK)
824 /*! @} */
825 
826 /*! @name STAT_EVC1 - Core1 External Event Status */
827 /*! @{ */
828 
829 #define RTU_GPR_STAT_EVC1_C1_EV0_MASK            (0x1U)
830 #define RTU_GPR_STAT_EVC1_C1_EV0_SHIFT           (0U)
831 #define RTU_GPR_STAT_EVC1_C1_EV0_WIDTH           (1U)
832 #define RTU_GPR_STAT_EVC1_C1_EV0(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV0_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV0_MASK)
833 
834 #define RTU_GPR_STAT_EVC1_C1_EV1_MASK            (0x2U)
835 #define RTU_GPR_STAT_EVC1_C1_EV1_SHIFT           (1U)
836 #define RTU_GPR_STAT_EVC1_C1_EV1_WIDTH           (1U)
837 #define RTU_GPR_STAT_EVC1_C1_EV1(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV1_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV1_MASK)
838 
839 #define RTU_GPR_STAT_EVC1_C1_EV2_MASK            (0x4U)
840 #define RTU_GPR_STAT_EVC1_C1_EV2_SHIFT           (2U)
841 #define RTU_GPR_STAT_EVC1_C1_EV2_WIDTH           (1U)
842 #define RTU_GPR_STAT_EVC1_C1_EV2(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV2_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV2_MASK)
843 
844 #define RTU_GPR_STAT_EVC1_C1_EV3_MASK            (0x8U)
845 #define RTU_GPR_STAT_EVC1_C1_EV3_SHIFT           (3U)
846 #define RTU_GPR_STAT_EVC1_C1_EV3_WIDTH           (1U)
847 #define RTU_GPR_STAT_EVC1_C1_EV3(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV3_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV3_MASK)
848 
849 #define RTU_GPR_STAT_EVC1_C1_EV4_MASK            (0x10U)
850 #define RTU_GPR_STAT_EVC1_C1_EV4_SHIFT           (4U)
851 #define RTU_GPR_STAT_EVC1_C1_EV4_WIDTH           (1U)
852 #define RTU_GPR_STAT_EVC1_C1_EV4(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV4_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV4_MASK)
853 
854 #define RTU_GPR_STAT_EVC1_C1_EV5_MASK            (0x20U)
855 #define RTU_GPR_STAT_EVC1_C1_EV5_SHIFT           (5U)
856 #define RTU_GPR_STAT_EVC1_C1_EV5_WIDTH           (1U)
857 #define RTU_GPR_STAT_EVC1_C1_EV5(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV5_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV5_MASK)
858 
859 #define RTU_GPR_STAT_EVC1_C1_EV6_MASK            (0x40U)
860 #define RTU_GPR_STAT_EVC1_C1_EV6_SHIFT           (6U)
861 #define RTU_GPR_STAT_EVC1_C1_EV6_WIDTH           (1U)
862 #define RTU_GPR_STAT_EVC1_C1_EV6(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV6_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV6_MASK)
863 
864 #define RTU_GPR_STAT_EVC1_C1_EV7_MASK            (0x80U)
865 #define RTU_GPR_STAT_EVC1_C1_EV7_SHIFT           (7U)
866 #define RTU_GPR_STAT_EVC1_C1_EV7_WIDTH           (1U)
867 #define RTU_GPR_STAT_EVC1_C1_EV7(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV7_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV7_MASK)
868 
869 #define RTU_GPR_STAT_EVC1_C1_EV8_MASK            (0x100U)
870 #define RTU_GPR_STAT_EVC1_C1_EV8_SHIFT           (8U)
871 #define RTU_GPR_STAT_EVC1_C1_EV8_WIDTH           (1U)
872 #define RTU_GPR_STAT_EVC1_C1_EV8(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV8_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV8_MASK)
873 
874 #define RTU_GPR_STAT_EVC1_C1_EV9_MASK            (0x200U)
875 #define RTU_GPR_STAT_EVC1_C1_EV9_SHIFT           (9U)
876 #define RTU_GPR_STAT_EVC1_C1_EV9_WIDTH           (1U)
877 #define RTU_GPR_STAT_EVC1_C1_EV9(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV9_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV9_MASK)
878 
879 #define RTU_GPR_STAT_EVC1_C1_EV10_MASK           (0x400U)
880 #define RTU_GPR_STAT_EVC1_C1_EV10_SHIFT          (10U)
881 #define RTU_GPR_STAT_EVC1_C1_EV10_WIDTH          (1U)
882 #define RTU_GPR_STAT_EVC1_C1_EV10(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV10_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV10_MASK)
883 
884 #define RTU_GPR_STAT_EVC1_C1_EV11_MASK           (0x800U)
885 #define RTU_GPR_STAT_EVC1_C1_EV11_SHIFT          (11U)
886 #define RTU_GPR_STAT_EVC1_C1_EV11_WIDTH          (1U)
887 #define RTU_GPR_STAT_EVC1_C1_EV11(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV11_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV11_MASK)
888 
889 #define RTU_GPR_STAT_EVC1_C1_EV12_MASK           (0x1000U)
890 #define RTU_GPR_STAT_EVC1_C1_EV12_SHIFT          (12U)
891 #define RTU_GPR_STAT_EVC1_C1_EV12_WIDTH          (1U)
892 #define RTU_GPR_STAT_EVC1_C1_EV12(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV12_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV12_MASK)
893 
894 #define RTU_GPR_STAT_EVC1_C1_EV13_MASK           (0x2000U)
895 #define RTU_GPR_STAT_EVC1_C1_EV13_SHIFT          (13U)
896 #define RTU_GPR_STAT_EVC1_C1_EV13_WIDTH          (1U)
897 #define RTU_GPR_STAT_EVC1_C1_EV13(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV13_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV13_MASK)
898 
899 #define RTU_GPR_STAT_EVC1_C1_EV14_MASK           (0x4000U)
900 #define RTU_GPR_STAT_EVC1_C1_EV14_SHIFT          (14U)
901 #define RTU_GPR_STAT_EVC1_C1_EV14_WIDTH          (1U)
902 #define RTU_GPR_STAT_EVC1_C1_EV14(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV14_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV14_MASK)
903 
904 #define RTU_GPR_STAT_EVC1_C1_EV15_MASK           (0x8000U)
905 #define RTU_GPR_STAT_EVC1_C1_EV15_SHIFT          (15U)
906 #define RTU_GPR_STAT_EVC1_C1_EV15_WIDTH          (1U)
907 #define RTU_GPR_STAT_EVC1_C1_EV15(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV15_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV15_MASK)
908 
909 #define RTU_GPR_STAT_EVC1_C1_EV16_MASK           (0x10000U)
910 #define RTU_GPR_STAT_EVC1_C1_EV16_SHIFT          (16U)
911 #define RTU_GPR_STAT_EVC1_C1_EV16_WIDTH          (1U)
912 #define RTU_GPR_STAT_EVC1_C1_EV16(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV16_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV16_MASK)
913 
914 #define RTU_GPR_STAT_EVC1_C1_EV17_MASK           (0x20000U)
915 #define RTU_GPR_STAT_EVC1_C1_EV17_SHIFT          (17U)
916 #define RTU_GPR_STAT_EVC1_C1_EV17_WIDTH          (1U)
917 #define RTU_GPR_STAT_EVC1_C1_EV17(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV17_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV17_MASK)
918 
919 #define RTU_GPR_STAT_EVC1_C1_EV18_MASK           (0x40000U)
920 #define RTU_GPR_STAT_EVC1_C1_EV18_SHIFT          (18U)
921 #define RTU_GPR_STAT_EVC1_C1_EV18_WIDTH          (1U)
922 #define RTU_GPR_STAT_EVC1_C1_EV18(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV18_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV18_MASK)
923 
924 #define RTU_GPR_STAT_EVC1_C1_EV19_MASK           (0x80000U)
925 #define RTU_GPR_STAT_EVC1_C1_EV19_SHIFT          (19U)
926 #define RTU_GPR_STAT_EVC1_C1_EV19_WIDTH          (1U)
927 #define RTU_GPR_STAT_EVC1_C1_EV19(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV19_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV19_MASK)
928 
929 #define RTU_GPR_STAT_EVC1_C1_EV20_MASK           (0x100000U)
930 #define RTU_GPR_STAT_EVC1_C1_EV20_SHIFT          (20U)
931 #define RTU_GPR_STAT_EVC1_C1_EV20_WIDTH          (1U)
932 #define RTU_GPR_STAT_EVC1_C1_EV20(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV20_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV20_MASK)
933 
934 #define RTU_GPR_STAT_EVC1_C1_EV21_MASK           (0x200000U)
935 #define RTU_GPR_STAT_EVC1_C1_EV21_SHIFT          (21U)
936 #define RTU_GPR_STAT_EVC1_C1_EV21_WIDTH          (1U)
937 #define RTU_GPR_STAT_EVC1_C1_EV21(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV21_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV21_MASK)
938 
939 #define RTU_GPR_STAT_EVC1_C1_EV22_MASK           (0x400000U)
940 #define RTU_GPR_STAT_EVC1_C1_EV22_SHIFT          (22U)
941 #define RTU_GPR_STAT_EVC1_C1_EV22_WIDTH          (1U)
942 #define RTU_GPR_STAT_EVC1_C1_EV22(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV22_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV22_MASK)
943 
944 #define RTU_GPR_STAT_EVC1_C1_EV23_MASK           (0x800000U)
945 #define RTU_GPR_STAT_EVC1_C1_EV23_SHIFT          (23U)
946 #define RTU_GPR_STAT_EVC1_C1_EV23_WIDTH          (1U)
947 #define RTU_GPR_STAT_EVC1_C1_EV23(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV23_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV23_MASK)
948 
949 #define RTU_GPR_STAT_EVC1_C1_EV24_MASK           (0x1000000U)
950 #define RTU_GPR_STAT_EVC1_C1_EV24_SHIFT          (24U)
951 #define RTU_GPR_STAT_EVC1_C1_EV24_WIDTH          (1U)
952 #define RTU_GPR_STAT_EVC1_C1_EV24(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV24_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV24_MASK)
953 
954 #define RTU_GPR_STAT_EVC1_C1_EV25_MASK           (0x2000000U)
955 #define RTU_GPR_STAT_EVC1_C1_EV25_SHIFT          (25U)
956 #define RTU_GPR_STAT_EVC1_C1_EV25_WIDTH          (1U)
957 #define RTU_GPR_STAT_EVC1_C1_EV25(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC1_C1_EV25_SHIFT)) & RTU_GPR_STAT_EVC1_C1_EV25_MASK)
958 /*! @} */
959 
960 /*! @name STAT_EVC2 - Core2 External Event Status */
961 /*! @{ */
962 
963 #define RTU_GPR_STAT_EVC2_C2_EV0_MASK            (0x1U)
964 #define RTU_GPR_STAT_EVC2_C2_EV0_SHIFT           (0U)
965 #define RTU_GPR_STAT_EVC2_C2_EV0_WIDTH           (1U)
966 #define RTU_GPR_STAT_EVC2_C2_EV0(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV0_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV0_MASK)
967 
968 #define RTU_GPR_STAT_EVC2_C2_EV1_MASK            (0x2U)
969 #define RTU_GPR_STAT_EVC2_C2_EV1_SHIFT           (1U)
970 #define RTU_GPR_STAT_EVC2_C2_EV1_WIDTH           (1U)
971 #define RTU_GPR_STAT_EVC2_C2_EV1(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV1_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV1_MASK)
972 
973 #define RTU_GPR_STAT_EVC2_C2_EV2_MASK            (0x4U)
974 #define RTU_GPR_STAT_EVC2_C2_EV2_SHIFT           (2U)
975 #define RTU_GPR_STAT_EVC2_C2_EV2_WIDTH           (1U)
976 #define RTU_GPR_STAT_EVC2_C2_EV2(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV2_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV2_MASK)
977 
978 #define RTU_GPR_STAT_EVC2_C2_EV3_MASK            (0x8U)
979 #define RTU_GPR_STAT_EVC2_C2_EV3_SHIFT           (3U)
980 #define RTU_GPR_STAT_EVC2_C2_EV3_WIDTH           (1U)
981 #define RTU_GPR_STAT_EVC2_C2_EV3(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV3_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV3_MASK)
982 
983 #define RTU_GPR_STAT_EVC2_C2_EV4_MASK            (0x10U)
984 #define RTU_GPR_STAT_EVC2_C2_EV4_SHIFT           (4U)
985 #define RTU_GPR_STAT_EVC2_C2_EV4_WIDTH           (1U)
986 #define RTU_GPR_STAT_EVC2_C2_EV4(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV4_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV4_MASK)
987 
988 #define RTU_GPR_STAT_EVC2_C2_EV5_MASK            (0x20U)
989 #define RTU_GPR_STAT_EVC2_C2_EV5_SHIFT           (5U)
990 #define RTU_GPR_STAT_EVC2_C2_EV5_WIDTH           (1U)
991 #define RTU_GPR_STAT_EVC2_C2_EV5(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV5_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV5_MASK)
992 
993 #define RTU_GPR_STAT_EVC2_C2_EV6_MASK            (0x40U)
994 #define RTU_GPR_STAT_EVC2_C2_EV6_SHIFT           (6U)
995 #define RTU_GPR_STAT_EVC2_C2_EV6_WIDTH           (1U)
996 #define RTU_GPR_STAT_EVC2_C2_EV6(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV6_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV6_MASK)
997 
998 #define RTU_GPR_STAT_EVC2_C2_EV7_MASK            (0x80U)
999 #define RTU_GPR_STAT_EVC2_C2_EV7_SHIFT           (7U)
1000 #define RTU_GPR_STAT_EVC2_C2_EV7_WIDTH           (1U)
1001 #define RTU_GPR_STAT_EVC2_C2_EV7(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV7_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV7_MASK)
1002 
1003 #define RTU_GPR_STAT_EVC2_C2_EV8_MASK            (0x100U)
1004 #define RTU_GPR_STAT_EVC2_C2_EV8_SHIFT           (8U)
1005 #define RTU_GPR_STAT_EVC2_C2_EV8_WIDTH           (1U)
1006 #define RTU_GPR_STAT_EVC2_C2_EV8(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV8_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV8_MASK)
1007 
1008 #define RTU_GPR_STAT_EVC2_C2_EV9_MASK            (0x200U)
1009 #define RTU_GPR_STAT_EVC2_C2_EV9_SHIFT           (9U)
1010 #define RTU_GPR_STAT_EVC2_C2_EV9_WIDTH           (1U)
1011 #define RTU_GPR_STAT_EVC2_C2_EV9(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV9_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV9_MASK)
1012 
1013 #define RTU_GPR_STAT_EVC2_C2_EV10_MASK           (0x400U)
1014 #define RTU_GPR_STAT_EVC2_C2_EV10_SHIFT          (10U)
1015 #define RTU_GPR_STAT_EVC2_C2_EV10_WIDTH          (1U)
1016 #define RTU_GPR_STAT_EVC2_C2_EV10(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV10_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV10_MASK)
1017 
1018 #define RTU_GPR_STAT_EVC2_C2_EV11_MASK           (0x800U)
1019 #define RTU_GPR_STAT_EVC2_C2_EV11_SHIFT          (11U)
1020 #define RTU_GPR_STAT_EVC2_C2_EV11_WIDTH          (1U)
1021 #define RTU_GPR_STAT_EVC2_C2_EV11(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV11_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV11_MASK)
1022 
1023 #define RTU_GPR_STAT_EVC2_C2_EV12_MASK           (0x1000U)
1024 #define RTU_GPR_STAT_EVC2_C2_EV12_SHIFT          (12U)
1025 #define RTU_GPR_STAT_EVC2_C2_EV12_WIDTH          (1U)
1026 #define RTU_GPR_STAT_EVC2_C2_EV12(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV12_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV12_MASK)
1027 
1028 #define RTU_GPR_STAT_EVC2_C2_EV13_MASK           (0x2000U)
1029 #define RTU_GPR_STAT_EVC2_C2_EV13_SHIFT          (13U)
1030 #define RTU_GPR_STAT_EVC2_C2_EV13_WIDTH          (1U)
1031 #define RTU_GPR_STAT_EVC2_C2_EV13(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV13_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV13_MASK)
1032 
1033 #define RTU_GPR_STAT_EVC2_C2_EV14_MASK           (0x4000U)
1034 #define RTU_GPR_STAT_EVC2_C2_EV14_SHIFT          (14U)
1035 #define RTU_GPR_STAT_EVC2_C2_EV14_WIDTH          (1U)
1036 #define RTU_GPR_STAT_EVC2_C2_EV14(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV14_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV14_MASK)
1037 
1038 #define RTU_GPR_STAT_EVC2_C2_EV15_MASK           (0x8000U)
1039 #define RTU_GPR_STAT_EVC2_C2_EV15_SHIFT          (15U)
1040 #define RTU_GPR_STAT_EVC2_C2_EV15_WIDTH          (1U)
1041 #define RTU_GPR_STAT_EVC2_C2_EV15(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV15_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV15_MASK)
1042 
1043 #define RTU_GPR_STAT_EVC2_C2_EV16_MASK           (0x10000U)
1044 #define RTU_GPR_STAT_EVC2_C2_EV16_SHIFT          (16U)
1045 #define RTU_GPR_STAT_EVC2_C2_EV16_WIDTH          (1U)
1046 #define RTU_GPR_STAT_EVC2_C2_EV16(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV16_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV16_MASK)
1047 
1048 #define RTU_GPR_STAT_EVC2_C2_EV17_MASK           (0x20000U)
1049 #define RTU_GPR_STAT_EVC2_C2_EV17_SHIFT          (17U)
1050 #define RTU_GPR_STAT_EVC2_C2_EV17_WIDTH          (1U)
1051 #define RTU_GPR_STAT_EVC2_C2_EV17(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV17_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV17_MASK)
1052 
1053 #define RTU_GPR_STAT_EVC2_C2_EV18_MASK           (0x40000U)
1054 #define RTU_GPR_STAT_EVC2_C2_EV18_SHIFT          (18U)
1055 #define RTU_GPR_STAT_EVC2_C2_EV18_WIDTH          (1U)
1056 #define RTU_GPR_STAT_EVC2_C2_EV18(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV18_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV18_MASK)
1057 
1058 #define RTU_GPR_STAT_EVC2_C2_EV19_MASK           (0x80000U)
1059 #define RTU_GPR_STAT_EVC2_C2_EV19_SHIFT          (19U)
1060 #define RTU_GPR_STAT_EVC2_C2_EV19_WIDTH          (1U)
1061 #define RTU_GPR_STAT_EVC2_C2_EV19(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV19_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV19_MASK)
1062 
1063 #define RTU_GPR_STAT_EVC2_C2_EV20_MASK           (0x100000U)
1064 #define RTU_GPR_STAT_EVC2_C2_EV20_SHIFT          (20U)
1065 #define RTU_GPR_STAT_EVC2_C2_EV20_WIDTH          (1U)
1066 #define RTU_GPR_STAT_EVC2_C2_EV20(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV20_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV20_MASK)
1067 
1068 #define RTU_GPR_STAT_EVC2_C2_EV21_MASK           (0x200000U)
1069 #define RTU_GPR_STAT_EVC2_C2_EV21_SHIFT          (21U)
1070 #define RTU_GPR_STAT_EVC2_C2_EV21_WIDTH          (1U)
1071 #define RTU_GPR_STAT_EVC2_C2_EV21(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV21_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV21_MASK)
1072 
1073 #define RTU_GPR_STAT_EVC2_C2_EV22_MASK           (0x400000U)
1074 #define RTU_GPR_STAT_EVC2_C2_EV22_SHIFT          (22U)
1075 #define RTU_GPR_STAT_EVC2_C2_EV22_WIDTH          (1U)
1076 #define RTU_GPR_STAT_EVC2_C2_EV22(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV22_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV22_MASK)
1077 
1078 #define RTU_GPR_STAT_EVC2_C2_EV23_MASK           (0x800000U)
1079 #define RTU_GPR_STAT_EVC2_C2_EV23_SHIFT          (23U)
1080 #define RTU_GPR_STAT_EVC2_C2_EV23_WIDTH          (1U)
1081 #define RTU_GPR_STAT_EVC2_C2_EV23(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV23_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV23_MASK)
1082 
1083 #define RTU_GPR_STAT_EVC2_C2_EV24_MASK           (0x1000000U)
1084 #define RTU_GPR_STAT_EVC2_C2_EV24_SHIFT          (24U)
1085 #define RTU_GPR_STAT_EVC2_C2_EV24_WIDTH          (1U)
1086 #define RTU_GPR_STAT_EVC2_C2_EV24(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV24_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV24_MASK)
1087 
1088 #define RTU_GPR_STAT_EVC2_C2_EV25_MASK           (0x2000000U)
1089 #define RTU_GPR_STAT_EVC2_C2_EV25_SHIFT          (25U)
1090 #define RTU_GPR_STAT_EVC2_C2_EV25_WIDTH          (1U)
1091 #define RTU_GPR_STAT_EVC2_C2_EV25(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC2_C2_EV25_SHIFT)) & RTU_GPR_STAT_EVC2_C2_EV25_MASK)
1092 /*! @} */
1093 
1094 /*! @name STAT_EVC3 - Core3 External Event Status */
1095 /*! @{ */
1096 
1097 #define RTU_GPR_STAT_EVC3_C3_EV0_MASK            (0x1U)
1098 #define RTU_GPR_STAT_EVC3_C3_EV0_SHIFT           (0U)
1099 #define RTU_GPR_STAT_EVC3_C3_EV0_WIDTH           (1U)
1100 #define RTU_GPR_STAT_EVC3_C3_EV0(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV0_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV0_MASK)
1101 
1102 #define RTU_GPR_STAT_EVC3_C3_EV1_MASK            (0x2U)
1103 #define RTU_GPR_STAT_EVC3_C3_EV1_SHIFT           (1U)
1104 #define RTU_GPR_STAT_EVC3_C3_EV1_WIDTH           (1U)
1105 #define RTU_GPR_STAT_EVC3_C3_EV1(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV1_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV1_MASK)
1106 
1107 #define RTU_GPR_STAT_EVC3_C3_EV2_MASK            (0x4U)
1108 #define RTU_GPR_STAT_EVC3_C3_EV2_SHIFT           (2U)
1109 #define RTU_GPR_STAT_EVC3_C3_EV2_WIDTH           (1U)
1110 #define RTU_GPR_STAT_EVC3_C3_EV2(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV2_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV2_MASK)
1111 
1112 #define RTU_GPR_STAT_EVC3_C3_EV3_MASK            (0x8U)
1113 #define RTU_GPR_STAT_EVC3_C3_EV3_SHIFT           (3U)
1114 #define RTU_GPR_STAT_EVC3_C3_EV3_WIDTH           (1U)
1115 #define RTU_GPR_STAT_EVC3_C3_EV3(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV3_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV3_MASK)
1116 
1117 #define RTU_GPR_STAT_EVC3_C3_EV4_MASK            (0x10U)
1118 #define RTU_GPR_STAT_EVC3_C3_EV4_SHIFT           (4U)
1119 #define RTU_GPR_STAT_EVC3_C3_EV4_WIDTH           (1U)
1120 #define RTU_GPR_STAT_EVC3_C3_EV4(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV4_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV4_MASK)
1121 
1122 #define RTU_GPR_STAT_EVC3_C3_EV5_MASK            (0x20U)
1123 #define RTU_GPR_STAT_EVC3_C3_EV5_SHIFT           (5U)
1124 #define RTU_GPR_STAT_EVC3_C3_EV5_WIDTH           (1U)
1125 #define RTU_GPR_STAT_EVC3_C3_EV5(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV5_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV5_MASK)
1126 
1127 #define RTU_GPR_STAT_EVC3_C3_EV6_MASK            (0x40U)
1128 #define RTU_GPR_STAT_EVC3_C3_EV6_SHIFT           (6U)
1129 #define RTU_GPR_STAT_EVC3_C3_EV6_WIDTH           (1U)
1130 #define RTU_GPR_STAT_EVC3_C3_EV6(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV6_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV6_MASK)
1131 
1132 #define RTU_GPR_STAT_EVC3_C3_EV7_MASK            (0x80U)
1133 #define RTU_GPR_STAT_EVC3_C3_EV7_SHIFT           (7U)
1134 #define RTU_GPR_STAT_EVC3_C3_EV7_WIDTH           (1U)
1135 #define RTU_GPR_STAT_EVC3_C3_EV7(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV7_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV7_MASK)
1136 
1137 #define RTU_GPR_STAT_EVC3_C3_EV8_MASK            (0x100U)
1138 #define RTU_GPR_STAT_EVC3_C3_EV8_SHIFT           (8U)
1139 #define RTU_GPR_STAT_EVC3_C3_EV8_WIDTH           (1U)
1140 #define RTU_GPR_STAT_EVC3_C3_EV8(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV8_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV8_MASK)
1141 
1142 #define RTU_GPR_STAT_EVC3_C3_EV9_MASK            (0x200U)
1143 #define RTU_GPR_STAT_EVC3_C3_EV9_SHIFT           (9U)
1144 #define RTU_GPR_STAT_EVC3_C3_EV9_WIDTH           (1U)
1145 #define RTU_GPR_STAT_EVC3_C3_EV9(x)              (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV9_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV9_MASK)
1146 
1147 #define RTU_GPR_STAT_EVC3_C3_EV10_MASK           (0x400U)
1148 #define RTU_GPR_STAT_EVC3_C3_EV10_SHIFT          (10U)
1149 #define RTU_GPR_STAT_EVC3_C3_EV10_WIDTH          (1U)
1150 #define RTU_GPR_STAT_EVC3_C3_EV10(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV10_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV10_MASK)
1151 
1152 #define RTU_GPR_STAT_EVC3_C3_EV11_MASK           (0x800U)
1153 #define RTU_GPR_STAT_EVC3_C3_EV11_SHIFT          (11U)
1154 #define RTU_GPR_STAT_EVC3_C3_EV11_WIDTH          (1U)
1155 #define RTU_GPR_STAT_EVC3_C3_EV11(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV11_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV11_MASK)
1156 
1157 #define RTU_GPR_STAT_EVC3_C3_EV12_MASK           (0x1000U)
1158 #define RTU_GPR_STAT_EVC3_C3_EV12_SHIFT          (12U)
1159 #define RTU_GPR_STAT_EVC3_C3_EV12_WIDTH          (1U)
1160 #define RTU_GPR_STAT_EVC3_C3_EV12(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV12_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV12_MASK)
1161 
1162 #define RTU_GPR_STAT_EVC3_C3_EV13_MASK           (0x2000U)
1163 #define RTU_GPR_STAT_EVC3_C3_EV13_SHIFT          (13U)
1164 #define RTU_GPR_STAT_EVC3_C3_EV13_WIDTH          (1U)
1165 #define RTU_GPR_STAT_EVC3_C3_EV13(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV13_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV13_MASK)
1166 
1167 #define RTU_GPR_STAT_EVC3_C3_EV14_MASK           (0x4000U)
1168 #define RTU_GPR_STAT_EVC3_C3_EV14_SHIFT          (14U)
1169 #define RTU_GPR_STAT_EVC3_C3_EV14_WIDTH          (1U)
1170 #define RTU_GPR_STAT_EVC3_C3_EV14(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV14_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV14_MASK)
1171 
1172 #define RTU_GPR_STAT_EVC3_C3_EV15_MASK           (0x8000U)
1173 #define RTU_GPR_STAT_EVC3_C3_EV15_SHIFT          (15U)
1174 #define RTU_GPR_STAT_EVC3_C3_EV15_WIDTH          (1U)
1175 #define RTU_GPR_STAT_EVC3_C3_EV15(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV15_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV15_MASK)
1176 
1177 #define RTU_GPR_STAT_EVC3_C3_EV16_MASK           (0x10000U)
1178 #define RTU_GPR_STAT_EVC3_C3_EV16_SHIFT          (16U)
1179 #define RTU_GPR_STAT_EVC3_C3_EV16_WIDTH          (1U)
1180 #define RTU_GPR_STAT_EVC3_C3_EV16(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV16_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV16_MASK)
1181 
1182 #define RTU_GPR_STAT_EVC3_C3_EV17_MASK           (0x20000U)
1183 #define RTU_GPR_STAT_EVC3_C3_EV17_SHIFT          (17U)
1184 #define RTU_GPR_STAT_EVC3_C3_EV17_WIDTH          (1U)
1185 #define RTU_GPR_STAT_EVC3_C3_EV17(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV17_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV17_MASK)
1186 
1187 #define RTU_GPR_STAT_EVC3_C3_EV18_MASK           (0x40000U)
1188 #define RTU_GPR_STAT_EVC3_C3_EV18_SHIFT          (18U)
1189 #define RTU_GPR_STAT_EVC3_C3_EV18_WIDTH          (1U)
1190 #define RTU_GPR_STAT_EVC3_C3_EV18(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV18_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV18_MASK)
1191 
1192 #define RTU_GPR_STAT_EVC3_C3_EV19_MASK           (0x80000U)
1193 #define RTU_GPR_STAT_EVC3_C3_EV19_SHIFT          (19U)
1194 #define RTU_GPR_STAT_EVC3_C3_EV19_WIDTH          (1U)
1195 #define RTU_GPR_STAT_EVC3_C3_EV19(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV19_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV19_MASK)
1196 
1197 #define RTU_GPR_STAT_EVC3_C3_EV20_MASK           (0x100000U)
1198 #define RTU_GPR_STAT_EVC3_C3_EV20_SHIFT          (20U)
1199 #define RTU_GPR_STAT_EVC3_C3_EV20_WIDTH          (1U)
1200 #define RTU_GPR_STAT_EVC3_C3_EV20(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV20_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV20_MASK)
1201 
1202 #define RTU_GPR_STAT_EVC3_C3_EV21_MASK           (0x200000U)
1203 #define RTU_GPR_STAT_EVC3_C3_EV21_SHIFT          (21U)
1204 #define RTU_GPR_STAT_EVC3_C3_EV21_WIDTH          (1U)
1205 #define RTU_GPR_STAT_EVC3_C3_EV21(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV21_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV21_MASK)
1206 
1207 #define RTU_GPR_STAT_EVC3_C3_EV22_MASK           (0x400000U)
1208 #define RTU_GPR_STAT_EVC3_C3_EV22_SHIFT          (22U)
1209 #define RTU_GPR_STAT_EVC3_C3_EV22_WIDTH          (1U)
1210 #define RTU_GPR_STAT_EVC3_C3_EV22(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV22_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV22_MASK)
1211 
1212 #define RTU_GPR_STAT_EVC3_C3_EV23_MASK           (0x800000U)
1213 #define RTU_GPR_STAT_EVC3_C3_EV23_SHIFT          (23U)
1214 #define RTU_GPR_STAT_EVC3_C3_EV23_WIDTH          (1U)
1215 #define RTU_GPR_STAT_EVC3_C3_EV23(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV23_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV23_MASK)
1216 
1217 #define RTU_GPR_STAT_EVC3_C3_EV24_MASK           (0x1000000U)
1218 #define RTU_GPR_STAT_EVC3_C3_EV24_SHIFT          (24U)
1219 #define RTU_GPR_STAT_EVC3_C3_EV24_WIDTH          (1U)
1220 #define RTU_GPR_STAT_EVC3_C3_EV24(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV24_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV24_MASK)
1221 
1222 #define RTU_GPR_STAT_EVC3_C3_EV25_MASK           (0x2000000U)
1223 #define RTU_GPR_STAT_EVC3_C3_EV25_SHIFT          (25U)
1224 #define RTU_GPR_STAT_EVC3_C3_EV25_WIDTH          (1U)
1225 #define RTU_GPR_STAT_EVC3_C3_EV25(x)             (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_EVC3_C3_EV25_SHIFT)) & RTU_GPR_STAT_EVC3_C3_EV25_MASK)
1226 /*! @} */
1227 
1228 /*! @name STAT_MERRPM0 - Primary Error Interface Memory Identifier Core0 */
1229 /*! @{ */
1230 
1231 #define RTU_GPR_STAT_MERRPM0_PRIMEMERRMEM0_MASK  (0x7FFFU)
1232 #define RTU_GPR_STAT_MERRPM0_PRIMEMERRMEM0_SHIFT (0U)
1233 #define RTU_GPR_STAT_MERRPM0_PRIMEMERRMEM0_WIDTH (15U)
1234 #define RTU_GPR_STAT_MERRPM0_PRIMEMERRMEM0(x)    (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRPM0_PRIMEMERRMEM0_SHIFT)) & RTU_GPR_STAT_MERRPM0_PRIMEMERRMEM0_MASK)
1235 
1236 #define RTU_GPR_STAT_MERRPM0_PRIMEMERRMEMV0_MASK (0x80000000U)
1237 #define RTU_GPR_STAT_MERRPM0_PRIMEMERRMEMV0_SHIFT (31U)
1238 #define RTU_GPR_STAT_MERRPM0_PRIMEMERRMEMV0_WIDTH (1U)
1239 #define RTU_GPR_STAT_MERRPM0_PRIMEMERRMEMV0(x)   (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRPM0_PRIMEMERRMEMV0_SHIFT)) & RTU_GPR_STAT_MERRPM0_PRIMEMERRMEMV0_MASK)
1240 /*! @} */
1241 
1242 /*! @name STAT_MERRPX0 - Primary Error Interface Index Core0 */
1243 /*! @{ */
1244 
1245 #define RTU_GPR_STAT_MERRPX0_PRIMEMERRMEIDX0_MASK (0x1FFFFFFU)
1246 #define RTU_GPR_STAT_MERRPX0_PRIMEMERRMEIDX0_SHIFT (0U)
1247 #define RTU_GPR_STAT_MERRPX0_PRIMEMERRMEIDX0_WIDTH (25U)
1248 #define RTU_GPR_STAT_MERRPX0_PRIMEMERRMEIDX0(x)  (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRPX0_PRIMEMERRMEIDX0_SHIFT)) & RTU_GPR_STAT_MERRPX0_PRIMEMERRMEIDX0_MASK)
1249 /*! @} */
1250 
1251 /*! @name STAT_MERRSM0 - Secondary Error Interface Memory Identifier Core0 */
1252 /*! @{ */
1253 
1254 #define RTU_GPR_STAT_MERRSM0_SECMEMERRMEM0_MASK  (0x7FFFU)
1255 #define RTU_GPR_STAT_MERRSM0_SECMEMERRMEM0_SHIFT (0U)
1256 #define RTU_GPR_STAT_MERRSM0_SECMEMERRMEM0_WIDTH (15U)
1257 #define RTU_GPR_STAT_MERRSM0_SECMEMERRMEM0(x)    (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRSM0_SECMEMERRMEM0_SHIFT)) & RTU_GPR_STAT_MERRSM0_SECMEMERRMEM0_MASK)
1258 
1259 #define RTU_GPR_STAT_MERRSM0_SECMEMERRMEMV0_MASK (0x80000000U)
1260 #define RTU_GPR_STAT_MERRSM0_SECMEMERRMEMV0_SHIFT (31U)
1261 #define RTU_GPR_STAT_MERRSM0_SECMEMERRMEMV0_WIDTH (1U)
1262 #define RTU_GPR_STAT_MERRSM0_SECMEMERRMEMV0(x)   (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRSM0_SECMEMERRMEMV0_SHIFT)) & RTU_GPR_STAT_MERRSM0_SECMEMERRMEMV0_MASK)
1263 /*! @} */
1264 
1265 /*! @name STAT_MERRSX0 - Secondary Error Interface Index Core0 */
1266 /*! @{ */
1267 
1268 #define RTU_GPR_STAT_MERRSX0_SECMEMERRMEIDX0_MASK (0x1FFFFFFU)
1269 #define RTU_GPR_STAT_MERRSX0_SECMEMERRMEIDX0_SHIFT (0U)
1270 #define RTU_GPR_STAT_MERRSX0_SECMEMERRMEIDX0_WIDTH (25U)
1271 #define RTU_GPR_STAT_MERRSX0_SECMEMERRMEIDX0(x)  (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRSX0_SECMEMERRMEIDX0_SHIFT)) & RTU_GPR_STAT_MERRSX0_SECMEMERRMEIDX0_MASK)
1272 /*! @} */
1273 
1274 /*! @name STAT_MERRPM1 - Primary Error Interface Memory Identifier Core1 */
1275 /*! @{ */
1276 
1277 #define RTU_GPR_STAT_MERRPM1_PRIMEMERRMEM1_MASK  (0x7FFFU)
1278 #define RTU_GPR_STAT_MERRPM1_PRIMEMERRMEM1_SHIFT (0U)
1279 #define RTU_GPR_STAT_MERRPM1_PRIMEMERRMEM1_WIDTH (15U)
1280 #define RTU_GPR_STAT_MERRPM1_PRIMEMERRMEM1(x)    (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRPM1_PRIMEMERRMEM1_SHIFT)) & RTU_GPR_STAT_MERRPM1_PRIMEMERRMEM1_MASK)
1281 
1282 #define RTU_GPR_STAT_MERRPM1_PRIMEMERRMEMV1_MASK (0x80000000U)
1283 #define RTU_GPR_STAT_MERRPM1_PRIMEMERRMEMV1_SHIFT (31U)
1284 #define RTU_GPR_STAT_MERRPM1_PRIMEMERRMEMV1_WIDTH (1U)
1285 #define RTU_GPR_STAT_MERRPM1_PRIMEMERRMEMV1(x)   (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRPM1_PRIMEMERRMEMV1_SHIFT)) & RTU_GPR_STAT_MERRPM1_PRIMEMERRMEMV1_MASK)
1286 /*! @} */
1287 
1288 /*! @name STAT_MERRPX1 - Primary Error Interface Index Core1 */
1289 /*! @{ */
1290 
1291 #define RTU_GPR_STAT_MERRPX1_PRIMEMERRMEIDX1_MASK (0x1FFFFFFU)
1292 #define RTU_GPR_STAT_MERRPX1_PRIMEMERRMEIDX1_SHIFT (0U)
1293 #define RTU_GPR_STAT_MERRPX1_PRIMEMERRMEIDX1_WIDTH (25U)
1294 #define RTU_GPR_STAT_MERRPX1_PRIMEMERRMEIDX1(x)  (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRPX1_PRIMEMERRMEIDX1_SHIFT)) & RTU_GPR_STAT_MERRPX1_PRIMEMERRMEIDX1_MASK)
1295 /*! @} */
1296 
1297 /*! @name STAT_MERRSM1 - Secondary Error Interface Memory Identifier Core1 */
1298 /*! @{ */
1299 
1300 #define RTU_GPR_STAT_MERRSM1_SECMEMERRMEM1_MASK  (0x7FFFU)
1301 #define RTU_GPR_STAT_MERRSM1_SECMEMERRMEM1_SHIFT (0U)
1302 #define RTU_GPR_STAT_MERRSM1_SECMEMERRMEM1_WIDTH (15U)
1303 #define RTU_GPR_STAT_MERRSM1_SECMEMERRMEM1(x)    (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRSM1_SECMEMERRMEM1_SHIFT)) & RTU_GPR_STAT_MERRSM1_SECMEMERRMEM1_MASK)
1304 
1305 #define RTU_GPR_STAT_MERRSM1_SECMEMERRMEMV1_MASK (0x80000000U)
1306 #define RTU_GPR_STAT_MERRSM1_SECMEMERRMEMV1_SHIFT (31U)
1307 #define RTU_GPR_STAT_MERRSM1_SECMEMERRMEMV1_WIDTH (1U)
1308 #define RTU_GPR_STAT_MERRSM1_SECMEMERRMEMV1(x)   (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRSM1_SECMEMERRMEMV1_SHIFT)) & RTU_GPR_STAT_MERRSM1_SECMEMERRMEMV1_MASK)
1309 /*! @} */
1310 
1311 /*! @name STAT_MERRSX1 - Secondary Error Interface Index Core1 */
1312 /*! @{ */
1313 
1314 #define RTU_GPR_STAT_MERRSX1_SECMEMERRMEIDX1_MASK (0x1FFFFFFU)
1315 #define RTU_GPR_STAT_MERRSX1_SECMEMERRMEIDX1_SHIFT (0U)
1316 #define RTU_GPR_STAT_MERRSX1_SECMEMERRMEIDX1_WIDTH (25U)
1317 #define RTU_GPR_STAT_MERRSX1_SECMEMERRMEIDX1(x)  (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRSX1_SECMEMERRMEIDX1_SHIFT)) & RTU_GPR_STAT_MERRSX1_SECMEMERRMEIDX1_MASK)
1318 /*! @} */
1319 
1320 /*! @name STAT_MERRPM2 - Primary Error Interface Memory Identifier Core2 */
1321 /*! @{ */
1322 
1323 #define RTU_GPR_STAT_MERRPM2_PRIMEMERRMEM2_MASK  (0x7FFFU)
1324 #define RTU_GPR_STAT_MERRPM2_PRIMEMERRMEM2_SHIFT (0U)
1325 #define RTU_GPR_STAT_MERRPM2_PRIMEMERRMEM2_WIDTH (15U)
1326 #define RTU_GPR_STAT_MERRPM2_PRIMEMERRMEM2(x)    (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRPM2_PRIMEMERRMEM2_SHIFT)) & RTU_GPR_STAT_MERRPM2_PRIMEMERRMEM2_MASK)
1327 
1328 #define RTU_GPR_STAT_MERRPM2_PRIMEMERRMEMV2_MASK (0x80000000U)
1329 #define RTU_GPR_STAT_MERRPM2_PRIMEMERRMEMV2_SHIFT (31U)
1330 #define RTU_GPR_STAT_MERRPM2_PRIMEMERRMEMV2_WIDTH (1U)
1331 #define RTU_GPR_STAT_MERRPM2_PRIMEMERRMEMV2(x)   (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRPM2_PRIMEMERRMEMV2_SHIFT)) & RTU_GPR_STAT_MERRPM2_PRIMEMERRMEMV2_MASK)
1332 /*! @} */
1333 
1334 /*! @name STAT_MERRPX2 - Primary Error Interface Index Core2 */
1335 /*! @{ */
1336 
1337 #define RTU_GPR_STAT_MERRPX2_PRIMEMERRMEIDX2_MASK (0x1FFFFFFU)
1338 #define RTU_GPR_STAT_MERRPX2_PRIMEMERRMEIDX2_SHIFT (0U)
1339 #define RTU_GPR_STAT_MERRPX2_PRIMEMERRMEIDX2_WIDTH (25U)
1340 #define RTU_GPR_STAT_MERRPX2_PRIMEMERRMEIDX2(x)  (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRPX2_PRIMEMERRMEIDX2_SHIFT)) & RTU_GPR_STAT_MERRPX2_PRIMEMERRMEIDX2_MASK)
1341 /*! @} */
1342 
1343 /*! @name STAT_MERRSM2 - Secondary Error Interface Memory Identifier Core2 */
1344 /*! @{ */
1345 
1346 #define RTU_GPR_STAT_MERRSM2_SECMEMERRMEM2_MASK  (0x7FFFU)
1347 #define RTU_GPR_STAT_MERRSM2_SECMEMERRMEM2_SHIFT (0U)
1348 #define RTU_GPR_STAT_MERRSM2_SECMEMERRMEM2_WIDTH (15U)
1349 #define RTU_GPR_STAT_MERRSM2_SECMEMERRMEM2(x)    (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRSM2_SECMEMERRMEM2_SHIFT)) & RTU_GPR_STAT_MERRSM2_SECMEMERRMEM2_MASK)
1350 
1351 #define RTU_GPR_STAT_MERRSM2_SECMEMERRMEMV2_MASK (0x80000000U)
1352 #define RTU_GPR_STAT_MERRSM2_SECMEMERRMEMV2_SHIFT (31U)
1353 #define RTU_GPR_STAT_MERRSM2_SECMEMERRMEMV2_WIDTH (1U)
1354 #define RTU_GPR_STAT_MERRSM2_SECMEMERRMEMV2(x)   (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRSM2_SECMEMERRMEMV2_SHIFT)) & RTU_GPR_STAT_MERRSM2_SECMEMERRMEMV2_MASK)
1355 /*! @} */
1356 
1357 /*! @name STAT_MERRSX2 - Secondary Error Interface Index Core2 */
1358 /*! @{ */
1359 
1360 #define RTU_GPR_STAT_MERRSX2_SECMEMERRMEIDX2_MASK (0x1FFFFFFU)
1361 #define RTU_GPR_STAT_MERRSX2_SECMEMERRMEIDX2_SHIFT (0U)
1362 #define RTU_GPR_STAT_MERRSX2_SECMEMERRMEIDX2_WIDTH (25U)
1363 #define RTU_GPR_STAT_MERRSX2_SECMEMERRMEIDX2(x)  (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRSX2_SECMEMERRMEIDX2_SHIFT)) & RTU_GPR_STAT_MERRSX2_SECMEMERRMEIDX2_MASK)
1364 /*! @} */
1365 
1366 /*! @name STAT_MERRPM3 - Primary Error Interface Memory Identifier Core3 */
1367 /*! @{ */
1368 
1369 #define RTU_GPR_STAT_MERRPM3_PRIMEMERRMEM3_MASK  (0x7FFFU)
1370 #define RTU_GPR_STAT_MERRPM3_PRIMEMERRMEM3_SHIFT (0U)
1371 #define RTU_GPR_STAT_MERRPM3_PRIMEMERRMEM3_WIDTH (15U)
1372 #define RTU_GPR_STAT_MERRPM3_PRIMEMERRMEM3(x)    (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRPM3_PRIMEMERRMEM3_SHIFT)) & RTU_GPR_STAT_MERRPM3_PRIMEMERRMEM3_MASK)
1373 
1374 #define RTU_GPR_STAT_MERRPM3_PRIMEMERRMEMV3_MASK (0x80000000U)
1375 #define RTU_GPR_STAT_MERRPM3_PRIMEMERRMEMV3_SHIFT (31U)
1376 #define RTU_GPR_STAT_MERRPM3_PRIMEMERRMEMV3_WIDTH (1U)
1377 #define RTU_GPR_STAT_MERRPM3_PRIMEMERRMEMV3(x)   (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRPM3_PRIMEMERRMEMV3_SHIFT)) & RTU_GPR_STAT_MERRPM3_PRIMEMERRMEMV3_MASK)
1378 /*! @} */
1379 
1380 /*! @name STAT_MERRPX3 - Primary Error Interface Index Core3 */
1381 /*! @{ */
1382 
1383 #define RTU_GPR_STAT_MERRPX3_PRIMEMERRMEIDX3_MASK (0x1FFFFFFU)
1384 #define RTU_GPR_STAT_MERRPX3_PRIMEMERRMEIDX3_SHIFT (0U)
1385 #define RTU_GPR_STAT_MERRPX3_PRIMEMERRMEIDX3_WIDTH (25U)
1386 #define RTU_GPR_STAT_MERRPX3_PRIMEMERRMEIDX3(x)  (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRPX3_PRIMEMERRMEIDX3_SHIFT)) & RTU_GPR_STAT_MERRPX3_PRIMEMERRMEIDX3_MASK)
1387 /*! @} */
1388 
1389 /*! @name STAT_MERRSM3 - Secondary Error Interface Memory Identifier Core3 */
1390 /*! @{ */
1391 
1392 #define RTU_GPR_STAT_MERRSM3_SECMEMERRMEM3_MASK  (0x7FFFU)
1393 #define RTU_GPR_STAT_MERRSM3_SECMEMERRMEM3_SHIFT (0U)
1394 #define RTU_GPR_STAT_MERRSM3_SECMEMERRMEM3_WIDTH (15U)
1395 #define RTU_GPR_STAT_MERRSM3_SECMEMERRMEM3(x)    (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRSM3_SECMEMERRMEM3_SHIFT)) & RTU_GPR_STAT_MERRSM3_SECMEMERRMEM3_MASK)
1396 
1397 #define RTU_GPR_STAT_MERRSM3_SECMEMERRMEMV3_MASK (0x80000000U)
1398 #define RTU_GPR_STAT_MERRSM3_SECMEMERRMEMV3_SHIFT (31U)
1399 #define RTU_GPR_STAT_MERRSM3_SECMEMERRMEMV3_WIDTH (1U)
1400 #define RTU_GPR_STAT_MERRSM3_SECMEMERRMEMV3(x)   (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRSM3_SECMEMERRMEMV3_SHIFT)) & RTU_GPR_STAT_MERRSM3_SECMEMERRMEMV3_MASK)
1401 /*! @} */
1402 
1403 /*! @name STAT_MERRSX3 - Secondary Error Interface Index Core3 */
1404 /*! @{ */
1405 
1406 #define RTU_GPR_STAT_MERRSX3_SECMEMERRMEIDX3_MASK (0x1FFFFFFU)
1407 #define RTU_GPR_STAT_MERRSX3_SECMEMERRMEIDX3_SHIFT (0U)
1408 #define RTU_GPR_STAT_MERRSX3_SECMEMERRMEIDX3_WIDTH (25U)
1409 #define RTU_GPR_STAT_MERRSX3_SECMEMERRMEIDX3(x)  (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_MERRSX3_SECMEMERRMEIDX3_SHIFT)) & RTU_GPR_STAT_MERRSX3_SECMEMERRMEIDX3_MASK)
1410 /*! @} */
1411 
1412 /*! @name STAT_PMU0EV0 - PMU Event Core0 Group0 */
1413 /*! @{ */
1414 
1415 #define RTU_GPR_STAT_PMU0EV0_PMUEVENT0_MASK      (0xFFFFFFFFU)
1416 #define RTU_GPR_STAT_PMU0EV0_PMUEVENT0_SHIFT     (0U)
1417 #define RTU_GPR_STAT_PMU0EV0_PMUEVENT0_WIDTH     (32U)
1418 #define RTU_GPR_STAT_PMU0EV0_PMUEVENT0(x)        (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_PMU0EV0_PMUEVENT0_SHIFT)) & RTU_GPR_STAT_PMU0EV0_PMUEVENT0_MASK)
1419 /*! @} */
1420 
1421 /*! @name STAT_PMU1EV0 - PMU Event Core0 Group1 */
1422 /*! @{ */
1423 
1424 #define RTU_GPR_STAT_PMU1EV0_PMUEVENT0_MASK      (0xFU)
1425 #define RTU_GPR_STAT_PMU1EV0_PMUEVENT0_SHIFT     (0U)
1426 #define RTU_GPR_STAT_PMU1EV0_PMUEVENT0_WIDTH     (4U)
1427 #define RTU_GPR_STAT_PMU1EV0_PMUEVENT0(x)        (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_PMU1EV0_PMUEVENT0_SHIFT)) & RTU_GPR_STAT_PMU1EV0_PMUEVENT0_MASK)
1428 /*! @} */
1429 
1430 /*! @name STAT_PMU0EV1 - PMU Event Core1 Group0 */
1431 /*! @{ */
1432 
1433 #define RTU_GPR_STAT_PMU0EV1_PMUEVENT1_MASK      (0xFFFFFFFFU)
1434 #define RTU_GPR_STAT_PMU0EV1_PMUEVENT1_SHIFT     (0U)
1435 #define RTU_GPR_STAT_PMU0EV1_PMUEVENT1_WIDTH     (32U)
1436 #define RTU_GPR_STAT_PMU0EV1_PMUEVENT1(x)        (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_PMU0EV1_PMUEVENT1_SHIFT)) & RTU_GPR_STAT_PMU0EV1_PMUEVENT1_MASK)
1437 /*! @} */
1438 
1439 /*! @name STAT_PMU1EV1 - PMU Event Core1 Group1 */
1440 /*! @{ */
1441 
1442 #define RTU_GPR_STAT_PMU1EV1_PMUEVENT1_MASK      (0xFU)
1443 #define RTU_GPR_STAT_PMU1EV1_PMUEVENT1_SHIFT     (0U)
1444 #define RTU_GPR_STAT_PMU1EV1_PMUEVENT1_WIDTH     (4U)
1445 #define RTU_GPR_STAT_PMU1EV1_PMUEVENT1(x)        (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_PMU1EV1_PMUEVENT1_SHIFT)) & RTU_GPR_STAT_PMU1EV1_PMUEVENT1_MASK)
1446 /*! @} */
1447 
1448 /*! @name STAT_PMU0EV2 - PMU Event Core2 Group0 */
1449 /*! @{ */
1450 
1451 #define RTU_GPR_STAT_PMU0EV2_PMUEVENT2_MASK      (0xFFFFFFFFU)
1452 #define RTU_GPR_STAT_PMU0EV2_PMUEVENT2_SHIFT     (0U)
1453 #define RTU_GPR_STAT_PMU0EV2_PMUEVENT2_WIDTH     (32U)
1454 #define RTU_GPR_STAT_PMU0EV2_PMUEVENT2(x)        (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_PMU0EV2_PMUEVENT2_SHIFT)) & RTU_GPR_STAT_PMU0EV2_PMUEVENT2_MASK)
1455 /*! @} */
1456 
1457 /*! @name STAT_PMU1EV2 - PMU Event Core2 Group1 */
1458 /*! @{ */
1459 
1460 #define RTU_GPR_STAT_PMU1EV2_PMUEVENT2_MASK      (0xFU)
1461 #define RTU_GPR_STAT_PMU1EV2_PMUEVENT2_SHIFT     (0U)
1462 #define RTU_GPR_STAT_PMU1EV2_PMUEVENT2_WIDTH     (4U)
1463 #define RTU_GPR_STAT_PMU1EV2_PMUEVENT2(x)        (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_PMU1EV2_PMUEVENT2_SHIFT)) & RTU_GPR_STAT_PMU1EV2_PMUEVENT2_MASK)
1464 /*! @} */
1465 
1466 /*! @name STAT_PMU0EV3 - PMU Event Core3 Group0 */
1467 /*! @{ */
1468 
1469 #define RTU_GPR_STAT_PMU0EV3_PMUEVENT3_MASK      (0xFFFFFFFFU)
1470 #define RTU_GPR_STAT_PMU0EV3_PMUEVENT3_SHIFT     (0U)
1471 #define RTU_GPR_STAT_PMU0EV3_PMUEVENT3_WIDTH     (32U)
1472 #define RTU_GPR_STAT_PMU0EV3_PMUEVENT3(x)        (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_PMU0EV3_PMUEVENT3_SHIFT)) & RTU_GPR_STAT_PMU0EV3_PMUEVENT3_MASK)
1473 /*! @} */
1474 
1475 /*! @name STAT_PMU1EV3 - PMU Event Core3 Group1 */
1476 /*! @{ */
1477 
1478 #define RTU_GPR_STAT_PMU1EV3_PMUEVENT3_MASK      (0xFU)
1479 #define RTU_GPR_STAT_PMU1EV3_PMUEVENT3_SHIFT     (0U)
1480 #define RTU_GPR_STAT_PMU1EV3_PMUEVENT3_WIDTH     (4U)
1481 #define RTU_GPR_STAT_PMU1EV3_PMUEVENT3(x)        (((uint32_t)(((uint32_t)(x)) << RTU_GPR_STAT_PMU1EV3_PMUEVENT3_SHIFT)) & RTU_GPR_STAT_PMU1EV3_PMUEVENT3_MASK)
1482 /*! @} */
1483 
1484 /*!
1485  * @}
1486  */ /* end of group RTU_GPR_Register_Masks */
1487 
1488 /*!
1489  * @}
1490  */ /* end of group RTU_GPR_Peripheral_Access_Layer */
1491 
1492 #endif  /* #if !defined(S32Z2_RTU_GPR_H_) */
1493