1 /*
2  * Copyright 1997-2016 Freescale Semiconductor, Inc.
3  * Copyright 2016-2024 NXP
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*!
9  * @file S32Z2_RTT.h
10  * @version 2.3
11  * @date 2024-05-03
12  * @brief Peripheral Access Layer for S32Z2_RTT
13  *
14  * This file contains register definitions and macros for easy access to their
15  * bit fields.
16  *
17  * This file assumes LITTLE endian system.
18  */
19 
20 /**
21 * @page misra_violations MISRA-C:2012 violations
22 *
23 * @section [global]
24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
25 * The SoC header defines typedef for all modules.
26 *
27 * @section [global]
28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
29 * The SoC header defines macros for all modules and registers.
30 *
31 * @section [global]
32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
33 * These are generated macros used for accessing the bit-fields from registers.
34 *
35 * @section [global]
36 * Violates MISRA 2012 Required Rule 5.1, identifier clash
37 * The supported compilers use more than 31 significant characters for identifiers.
38 *
39 * @section [global]
40 * Violates MISRA 2012 Required Rule 5.2, identifier clash
41 * The supported compilers use more than 31 significant characters for identifiers.
42 *
43 * @section [global]
44 * Violates MISRA 2012 Required Rule 5.4, identifier clash
45 * The supported compilers use more than 31 significant characters for identifiers.
46 *
47 * @section [global]
48 * Violates MISRA 2012 Required Rule 5.5, identifier clash
49 * The supported compilers use more than 31 significant characters for identifiers.
50 *
51 * @section [global]
52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
53 * This type qualifier is needed to ensure correct I/O access and addressing.
54 */
55 
56 /* Prevention from multiple including the same memory map */
57 #if !defined(S32Z2_RTT_H_)  /* Check if memory map has not been already included */
58 #define S32Z2_RTT_H_
59 
60 #include "S32Z2_COMMON.h"
61 
62 /* ----------------------------------------------------------------------------
63    -- RTT Peripheral Access Layer
64    ---------------------------------------------------------------------------- */
65 
66 /*!
67  * @addtogroup RTT_Peripheral_Access_Layer RTT Peripheral Access Layer
68  * @{
69  */
70 
71 /** RTT - Register Layout Typedef */
72 typedef struct {
73   __IO uint32_t MODE;                              /**< MODE Register, offset: 0x0 */
74 } RTT_Type, *RTT_MemMapPtr;
75 
76 /** Number of instances of the RTT module. */
77 #define RTT_INSTANCE_COUNT                       (1u)
78 
79 /* RTT - Peripheral instance base addresses */
80 /** Peripheral CEVA_SPF2__RTT base address */
81 #define IP_CEVA_SPF2__RTT_BASE                   (0x24400180u)
82 /** Peripheral CEVA_SPF2__RTT base pointer */
83 #define IP_CEVA_SPF2__RTT                        ((RTT_Type *)IP_CEVA_SPF2__RTT_BASE)
84 /** Array initializer of RTT peripheral base addresses */
85 #define IP_RTT_BASE_ADDRS                        { IP_CEVA_SPF2__RTT_BASE }
86 /** Array initializer of RTT peripheral base pointers */
87 #define IP_RTT_BASE_PTRS                         { IP_CEVA_SPF2__RTT }
88 
89 /* ----------------------------------------------------------------------------
90    -- RTT Register Masks
91    ---------------------------------------------------------------------------- */
92 
93 /*!
94  * @addtogroup RTT_Register_Masks RTT Register Masks
95  * @{
96  */
97 
98 /*! @name MODE - MODE Register */
99 /*! @{ */
100 
101 #define RTT_MODE_WR_EN_MASK                      (0x40U)
102 #define RTT_MODE_WR_EN_SHIFT                     (6U)
103 #define RTT_MODE_WR_EN_WIDTH                     (1U)
104 #define RTT_MODE_WR_EN(x)                        (((uint32_t)(((uint32_t)(x)) << RTT_MODE_WR_EN_SHIFT)) & RTT_MODE_WR_EN_MASK)
105 
106 #define RTT_MODE_WR_RESET_MASK                   (0x80U)
107 #define RTT_MODE_WR_RESET_SHIFT                  (7U)
108 #define RTT_MODE_WR_RESET_WIDTH                  (1U)
109 #define RTT_MODE_WR_RESET(x)                     (((uint32_t)(((uint32_t)(x)) << RTT_MODE_WR_RESET_SHIFT)) & RTT_MODE_WR_RESET_MASK)
110 
111 #define RTT_MODE_BR_ALL_MASK                     (0x400U)
112 #define RTT_MODE_BR_ALL_SHIFT                    (10U)
113 #define RTT_MODE_BR_ALL_WIDTH                    (1U)
114 #define RTT_MODE_BR_ALL(x)                       (((uint32_t)(((uint32_t)(x)) << RTT_MODE_BR_ALL_SHIFT)) & RTT_MODE_BR_ALL_MASK)
115 /*! @} */
116 
117 /*!
118  * @}
119  */ /* end of group RTT_Register_Masks */
120 
121 /*!
122  * @}
123  */ /* end of group RTT_Peripheral_Access_Layer */
124 
125 #endif  /* #if !defined(S32Z2_RTT_H_) */
126