1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_QMAN_CNTRL.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_QMAN_CNTRL 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_QMAN_CNTRL_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_QMAN_CNTRL_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- QMAN_CNTRL Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup QMAN_CNTRL_Peripheral_Access_Layer QMAN_CNTRL Peripheral Access Layer 68 * @{ 69 */ 70 71 /** QMAN_CNTRL - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t QMAN_IDM_CROSS; /**< QMAN IDM CROSS, offset: 0x0 */ 74 __I uint32_t QMAN_ACTIVE; /**< QMAN ACTIVE, offset: 0x4 */ 75 uint8_t RESERVED_0[12]; 76 __IO uint32_t QMAN_VI_MASK; /**< QMAN VI MASK, offset: 0x14 */ 77 __IO uint32_t QMAN_IRQ_STATUS; /**< QMAN IRQ STATUS, offset: 0x18 */ 78 __IO uint32_t QMAN_RST; /**< QMAN RST, offset: 0x1C */ 79 uint8_t RESERVED_1[4]; 80 __IO uint32_t QMAN_QFULL; /**< QMAN QFULL, offset: 0x24 */ 81 __IO uint32_t QMAN_QFULL_MASK; /**< QMAN QFULL MASK, offset: 0x28 */ 82 uint8_t RESERVED_2[4]; 83 __IO uint32_t QMAN_PAUSE; /**< QMAN PAUSE, offset: 0x30 */ 84 } QMAN_CNTRL_Type, *QMAN_CNTRL_MemMapPtr; 85 86 /** Number of instances of the QMAN_CNTRL module. */ 87 #define QMAN_CNTRL_INSTANCE_COUNT (1u) 88 89 /* QMAN_CNTRL - Peripheral instance base addresses */ 90 /** Peripheral CEVA_SPF2__QMAN_CNTRL base address */ 91 #define IP_CEVA_SPF2__QMAN_CNTRL_BASE (0x24401180u) 92 /** Peripheral CEVA_SPF2__QMAN_CNTRL base pointer */ 93 #define IP_CEVA_SPF2__QMAN_CNTRL ((QMAN_CNTRL_Type *)IP_CEVA_SPF2__QMAN_CNTRL_BASE) 94 /** Array initializer of QMAN_CNTRL peripheral base addresses */ 95 #define IP_QMAN_CNTRL_BASE_ADDRS { IP_CEVA_SPF2__QMAN_CNTRL_BASE } 96 /** Array initializer of QMAN_CNTRL peripheral base pointers */ 97 #define IP_QMAN_CNTRL_BASE_PTRS { IP_CEVA_SPF2__QMAN_CNTRL } 98 99 /* ---------------------------------------------------------------------------- 100 -- QMAN_CNTRL Register Masks 101 ---------------------------------------------------------------------------- */ 102 103 /*! 104 * @addtogroup QMAN_CNTRL_Register_Masks QMAN_CNTRL Register Masks 105 * @{ 106 */ 107 108 /*! @name QMAN_IDM_CROSS - QMAN IDM CROSS */ 109 /*! @{ */ 110 111 #define QMAN_CNTRL_QMAN_IDM_CROSS_Q0_IDM_CROS_MASK (0x1U) 112 #define QMAN_CNTRL_QMAN_IDM_CROSS_Q0_IDM_CROS_SHIFT (0U) 113 #define QMAN_CNTRL_QMAN_IDM_CROSS_Q0_IDM_CROS_WIDTH (1U) 114 #define QMAN_CNTRL_QMAN_IDM_CROSS_Q0_IDM_CROS(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_IDM_CROSS_Q0_IDM_CROS_SHIFT)) & QMAN_CNTRL_QMAN_IDM_CROSS_Q0_IDM_CROS_MASK) 115 116 #define QMAN_CNTRL_QMAN_IDM_CROSS_Q1_IDM_CROS_MASK (0x2U) 117 #define QMAN_CNTRL_QMAN_IDM_CROSS_Q1_IDM_CROS_SHIFT (1U) 118 #define QMAN_CNTRL_QMAN_IDM_CROSS_Q1_IDM_CROS_WIDTH (1U) 119 #define QMAN_CNTRL_QMAN_IDM_CROSS_Q1_IDM_CROS(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_IDM_CROSS_Q1_IDM_CROS_SHIFT)) & QMAN_CNTRL_QMAN_IDM_CROSS_Q1_IDM_CROS_MASK) 120 121 #define QMAN_CNTRL_QMAN_IDM_CROSS_Q2_IDM_CROS_MASK (0x4U) 122 #define QMAN_CNTRL_QMAN_IDM_CROSS_Q2_IDM_CROS_SHIFT (2U) 123 #define QMAN_CNTRL_QMAN_IDM_CROSS_Q2_IDM_CROS_WIDTH (1U) 124 #define QMAN_CNTRL_QMAN_IDM_CROSS_Q2_IDM_CROS(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_IDM_CROSS_Q2_IDM_CROS_SHIFT)) & QMAN_CNTRL_QMAN_IDM_CROSS_Q2_IDM_CROS_MASK) 125 126 #define QMAN_CNTRL_QMAN_IDM_CROSS_Q3_IDM_CROS_MASK (0x8U) 127 #define QMAN_CNTRL_QMAN_IDM_CROSS_Q3_IDM_CROS_SHIFT (3U) 128 #define QMAN_CNTRL_QMAN_IDM_CROSS_Q3_IDM_CROS_WIDTH (1U) 129 #define QMAN_CNTRL_QMAN_IDM_CROSS_Q3_IDM_CROS(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_IDM_CROSS_Q3_IDM_CROS_SHIFT)) & QMAN_CNTRL_QMAN_IDM_CROSS_Q3_IDM_CROS_MASK) 130 /*! @} */ 131 132 /*! @name QMAN_ACTIVE - QMAN ACTIVE */ 133 /*! @{ */ 134 135 #define QMAN_CNTRL_QMAN_ACTIVE_Q0_ACTIVE_MASK (0x1U) 136 #define QMAN_CNTRL_QMAN_ACTIVE_Q0_ACTIVE_SHIFT (0U) 137 #define QMAN_CNTRL_QMAN_ACTIVE_Q0_ACTIVE_WIDTH (1U) 138 #define QMAN_CNTRL_QMAN_ACTIVE_Q0_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_ACTIVE_Q0_ACTIVE_SHIFT)) & QMAN_CNTRL_QMAN_ACTIVE_Q0_ACTIVE_MASK) 139 140 #define QMAN_CNTRL_QMAN_ACTIVE_Q1_ACTIVE_MASK (0x2U) 141 #define QMAN_CNTRL_QMAN_ACTIVE_Q1_ACTIVE_SHIFT (1U) 142 #define QMAN_CNTRL_QMAN_ACTIVE_Q1_ACTIVE_WIDTH (1U) 143 #define QMAN_CNTRL_QMAN_ACTIVE_Q1_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_ACTIVE_Q1_ACTIVE_SHIFT)) & QMAN_CNTRL_QMAN_ACTIVE_Q1_ACTIVE_MASK) 144 145 #define QMAN_CNTRL_QMAN_ACTIVE_Q2_ACTIVE_MASK (0x4U) 146 #define QMAN_CNTRL_QMAN_ACTIVE_Q2_ACTIVE_SHIFT (2U) 147 #define QMAN_CNTRL_QMAN_ACTIVE_Q2_ACTIVE_WIDTH (1U) 148 #define QMAN_CNTRL_QMAN_ACTIVE_Q2_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_ACTIVE_Q2_ACTIVE_SHIFT)) & QMAN_CNTRL_QMAN_ACTIVE_Q2_ACTIVE_MASK) 149 150 #define QMAN_CNTRL_QMAN_ACTIVE_Q3_ACTIVE_MASK (0x8U) 151 #define QMAN_CNTRL_QMAN_ACTIVE_Q3_ACTIVE_SHIFT (3U) 152 #define QMAN_CNTRL_QMAN_ACTIVE_Q3_ACTIVE_WIDTH (1U) 153 #define QMAN_CNTRL_QMAN_ACTIVE_Q3_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_ACTIVE_Q3_ACTIVE_SHIFT)) & QMAN_CNTRL_QMAN_ACTIVE_Q3_ACTIVE_MASK) 154 /*! @} */ 155 156 /*! @name QMAN_VI_MASK - QMAN VI MASK */ 157 /*! @{ */ 158 159 #define QMAN_CNTRL_QMAN_VI_MASK_FNUM_VI_MASK_MASK (0x80000000U) 160 #define QMAN_CNTRL_QMAN_VI_MASK_FNUM_VI_MASK_SHIFT (31U) 161 #define QMAN_CNTRL_QMAN_VI_MASK_FNUM_VI_MASK_WIDTH (1U) 162 #define QMAN_CNTRL_QMAN_VI_MASK_FNUM_VI_MASK(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_VI_MASK_FNUM_VI_MASK_SHIFT)) & QMAN_CNTRL_QMAN_VI_MASK_FNUM_VI_MASK_MASK) 163 /*! @} */ 164 165 /*! @name QMAN_IRQ_STATUS - QMAN IRQ STATUS */ 166 /*! @{ */ 167 168 #define QMAN_CNTRL_QMAN_IRQ_STATUS_Q0_EMPTY_VI_MASK (0x1U) 169 #define QMAN_CNTRL_QMAN_IRQ_STATUS_Q0_EMPTY_VI_SHIFT (0U) 170 #define QMAN_CNTRL_QMAN_IRQ_STATUS_Q0_EMPTY_VI_WIDTH (1U) 171 #define QMAN_CNTRL_QMAN_IRQ_STATUS_Q0_EMPTY_VI(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_IRQ_STATUS_Q0_EMPTY_VI_SHIFT)) & QMAN_CNTRL_QMAN_IRQ_STATUS_Q0_EMPTY_VI_MASK) 172 173 #define QMAN_CNTRL_QMAN_IRQ_STATUS_Q1_EMPTY_VI_MASK (0x2U) 174 #define QMAN_CNTRL_QMAN_IRQ_STATUS_Q1_EMPTY_VI_SHIFT (1U) 175 #define QMAN_CNTRL_QMAN_IRQ_STATUS_Q1_EMPTY_VI_WIDTH (1U) 176 #define QMAN_CNTRL_QMAN_IRQ_STATUS_Q1_EMPTY_VI(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_IRQ_STATUS_Q1_EMPTY_VI_SHIFT)) & QMAN_CNTRL_QMAN_IRQ_STATUS_Q1_EMPTY_VI_MASK) 177 178 #define QMAN_CNTRL_QMAN_IRQ_STATUS_Q2_EMPTY_VI_MASK (0x4U) 179 #define QMAN_CNTRL_QMAN_IRQ_STATUS_Q2_EMPTY_VI_SHIFT (2U) 180 #define QMAN_CNTRL_QMAN_IRQ_STATUS_Q2_EMPTY_VI_WIDTH (1U) 181 #define QMAN_CNTRL_QMAN_IRQ_STATUS_Q2_EMPTY_VI(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_IRQ_STATUS_Q2_EMPTY_VI_SHIFT)) & QMAN_CNTRL_QMAN_IRQ_STATUS_Q2_EMPTY_VI_MASK) 182 183 #define QMAN_CNTRL_QMAN_IRQ_STATUS_Q3_EMPTY_VI_MASK (0x8U) 184 #define QMAN_CNTRL_QMAN_IRQ_STATUS_Q3_EMPTY_VI_SHIFT (3U) 185 #define QMAN_CNTRL_QMAN_IRQ_STATUS_Q3_EMPTY_VI_WIDTH (1U) 186 #define QMAN_CNTRL_QMAN_IRQ_STATUS_Q3_EMPTY_VI(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_IRQ_STATUS_Q3_EMPTY_VI_SHIFT)) & QMAN_CNTRL_QMAN_IRQ_STATUS_Q3_EMPTY_VI_MASK) 187 188 #define QMAN_CNTRL_QMAN_IRQ_STATUS_FNUM_VI_MASK (0x80000000U) 189 #define QMAN_CNTRL_QMAN_IRQ_STATUS_FNUM_VI_SHIFT (31U) 190 #define QMAN_CNTRL_QMAN_IRQ_STATUS_FNUM_VI_WIDTH (1U) 191 #define QMAN_CNTRL_QMAN_IRQ_STATUS_FNUM_VI(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_IRQ_STATUS_FNUM_VI_SHIFT)) & QMAN_CNTRL_QMAN_IRQ_STATUS_FNUM_VI_MASK) 192 /*! @} */ 193 194 /*! @name QMAN_RST - QMAN RST */ 195 /*! @{ */ 196 197 #define QMAN_CNTRL_QMAN_RST_Q0_RST_MASK (0x1U) 198 #define QMAN_CNTRL_QMAN_RST_Q0_RST_SHIFT (0U) 199 #define QMAN_CNTRL_QMAN_RST_Q0_RST_WIDTH (1U) 200 #define QMAN_CNTRL_QMAN_RST_Q0_RST(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_RST_Q0_RST_SHIFT)) & QMAN_CNTRL_QMAN_RST_Q0_RST_MASK) 201 202 #define QMAN_CNTRL_QMAN_RST_Q1_RST_MASK (0x2U) 203 #define QMAN_CNTRL_QMAN_RST_Q1_RST_SHIFT (1U) 204 #define QMAN_CNTRL_QMAN_RST_Q1_RST_WIDTH (1U) 205 #define QMAN_CNTRL_QMAN_RST_Q1_RST(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_RST_Q1_RST_SHIFT)) & QMAN_CNTRL_QMAN_RST_Q1_RST_MASK) 206 207 #define QMAN_CNTRL_QMAN_RST_Q2_RST_MASK (0x4U) 208 #define QMAN_CNTRL_QMAN_RST_Q2_RST_SHIFT (2U) 209 #define QMAN_CNTRL_QMAN_RST_Q2_RST_WIDTH (1U) 210 #define QMAN_CNTRL_QMAN_RST_Q2_RST(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_RST_Q2_RST_SHIFT)) & QMAN_CNTRL_QMAN_RST_Q2_RST_MASK) 211 212 #define QMAN_CNTRL_QMAN_RST_Q3_RST_MASK (0x8U) 213 #define QMAN_CNTRL_QMAN_RST_Q3_RST_SHIFT (3U) 214 #define QMAN_CNTRL_QMAN_RST_Q3_RST_WIDTH (1U) 215 #define QMAN_CNTRL_QMAN_RST_Q3_RST(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_RST_Q3_RST_SHIFT)) & QMAN_CNTRL_QMAN_RST_Q3_RST_MASK) 216 /*! @} */ 217 218 /*! @name QMAN_QFULL - QMAN QFULL */ 219 /*! @{ */ 220 221 #define QMAN_CNTRL_QMAN_QFULL_Q0_FULL_MASK (0x1U) 222 #define QMAN_CNTRL_QMAN_QFULL_Q0_FULL_SHIFT (0U) 223 #define QMAN_CNTRL_QMAN_QFULL_Q0_FULL_WIDTH (1U) 224 #define QMAN_CNTRL_QMAN_QFULL_Q0_FULL(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_QFULL_Q0_FULL_SHIFT)) & QMAN_CNTRL_QMAN_QFULL_Q0_FULL_MASK) 225 226 #define QMAN_CNTRL_QMAN_QFULL_Q1_FULL_MASK (0x2U) 227 #define QMAN_CNTRL_QMAN_QFULL_Q1_FULL_SHIFT (1U) 228 #define QMAN_CNTRL_QMAN_QFULL_Q1_FULL_WIDTH (1U) 229 #define QMAN_CNTRL_QMAN_QFULL_Q1_FULL(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_QFULL_Q1_FULL_SHIFT)) & QMAN_CNTRL_QMAN_QFULL_Q1_FULL_MASK) 230 231 #define QMAN_CNTRL_QMAN_QFULL_Q2_FULL_MASK (0x4U) 232 #define QMAN_CNTRL_QMAN_QFULL_Q2_FULL_SHIFT (2U) 233 #define QMAN_CNTRL_QMAN_QFULL_Q2_FULL_WIDTH (1U) 234 #define QMAN_CNTRL_QMAN_QFULL_Q2_FULL(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_QFULL_Q2_FULL_SHIFT)) & QMAN_CNTRL_QMAN_QFULL_Q2_FULL_MASK) 235 236 #define QMAN_CNTRL_QMAN_QFULL_Q3_FULL_MASK (0x8U) 237 #define QMAN_CNTRL_QMAN_QFULL_Q3_FULL_SHIFT (3U) 238 #define QMAN_CNTRL_QMAN_QFULL_Q3_FULL_WIDTH (1U) 239 #define QMAN_CNTRL_QMAN_QFULL_Q3_FULL(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_QFULL_Q3_FULL_SHIFT)) & QMAN_CNTRL_QMAN_QFULL_Q3_FULL_MASK) 240 /*! @} */ 241 242 /*! @name QMAN_QFULL_MASK - QMAN QFULL MASK */ 243 /*! @{ */ 244 245 #define QMAN_CNTRL_QMAN_QFULL_MASK_Q0_QFULL_MASK_MASK (0x1U) 246 #define QMAN_CNTRL_QMAN_QFULL_MASK_Q0_QFULL_MASK_SHIFT (0U) 247 #define QMAN_CNTRL_QMAN_QFULL_MASK_Q0_QFULL_MASK_WIDTH (1U) 248 #define QMAN_CNTRL_QMAN_QFULL_MASK_Q0_QFULL_MASK(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_QFULL_MASK_Q0_QFULL_MASK_SHIFT)) & QMAN_CNTRL_QMAN_QFULL_MASK_Q0_QFULL_MASK_MASK) 249 250 #define QMAN_CNTRL_QMAN_QFULL_MASK_Q1_QFULL_MASK_MASK (0x2U) 251 #define QMAN_CNTRL_QMAN_QFULL_MASK_Q1_QFULL_MASK_SHIFT (1U) 252 #define QMAN_CNTRL_QMAN_QFULL_MASK_Q1_QFULL_MASK_WIDTH (1U) 253 #define QMAN_CNTRL_QMAN_QFULL_MASK_Q1_QFULL_MASK(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_QFULL_MASK_Q1_QFULL_MASK_SHIFT)) & QMAN_CNTRL_QMAN_QFULL_MASK_Q1_QFULL_MASK_MASK) 254 255 #define QMAN_CNTRL_QMAN_QFULL_MASK_Q2_QFULL_MASK_MASK (0x4U) 256 #define QMAN_CNTRL_QMAN_QFULL_MASK_Q2_QFULL_MASK_SHIFT (2U) 257 #define QMAN_CNTRL_QMAN_QFULL_MASK_Q2_QFULL_MASK_WIDTH (1U) 258 #define QMAN_CNTRL_QMAN_QFULL_MASK_Q2_QFULL_MASK(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_QFULL_MASK_Q2_QFULL_MASK_SHIFT)) & QMAN_CNTRL_QMAN_QFULL_MASK_Q2_QFULL_MASK_MASK) 259 260 #define QMAN_CNTRL_QMAN_QFULL_MASK_Q3_QFULL_MASK_MASK (0x8U) 261 #define QMAN_CNTRL_QMAN_QFULL_MASK_Q3_QFULL_MASK_SHIFT (3U) 262 #define QMAN_CNTRL_QMAN_QFULL_MASK_Q3_QFULL_MASK_WIDTH (1U) 263 #define QMAN_CNTRL_QMAN_QFULL_MASK_Q3_QFULL_MASK(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_QFULL_MASK_Q3_QFULL_MASK_SHIFT)) & QMAN_CNTRL_QMAN_QFULL_MASK_Q3_QFULL_MASK_MASK) 264 /*! @} */ 265 266 /*! @name QMAN_PAUSE - QMAN PAUSE */ 267 /*! @{ */ 268 269 #define QMAN_CNTRL_QMAN_PAUSE_QMAN_PAUSE_MASK (0x1U) 270 #define QMAN_CNTRL_QMAN_PAUSE_QMAN_PAUSE_SHIFT (0U) 271 #define QMAN_CNTRL_QMAN_PAUSE_QMAN_PAUSE_WIDTH (1U) 272 #define QMAN_CNTRL_QMAN_PAUSE_QMAN_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_PAUSE_QMAN_PAUSE_SHIFT)) & QMAN_CNTRL_QMAN_PAUSE_QMAN_PAUSE_MASK) 273 274 #define QMAN_CNTRL_QMAN_PAUSE_QMAN_PAUSE_STATUS_MASK (0x2U) 275 #define QMAN_CNTRL_QMAN_PAUSE_QMAN_PAUSE_STATUS_SHIFT (1U) 276 #define QMAN_CNTRL_QMAN_PAUSE_QMAN_PAUSE_STATUS_WIDTH (1U) 277 #define QMAN_CNTRL_QMAN_PAUSE_QMAN_PAUSE_STATUS(x) (((uint32_t)(((uint32_t)(x)) << QMAN_CNTRL_QMAN_PAUSE_QMAN_PAUSE_STATUS_SHIFT)) & QMAN_CNTRL_QMAN_PAUSE_QMAN_PAUSE_STATUS_MASK) 278 /*! @} */ 279 280 /*! 281 * @} 282 */ /* end of group QMAN_CNTRL_Register_Masks */ 283 284 /*! 285 * @} 286 */ /* end of group QMAN_CNTRL_Peripheral_Access_Layer */ 287 288 #endif /* #if !defined(S32Z2_QMAN_CNTRL_H_) */ 289
