1 /*
2  * Copyright 1997-2016 Freescale Semiconductor, Inc.
3  * Copyright 2016-2024 NXP
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*!
9  * @file S32Z2_POWER_SCALING_UNIT.h
10  * @version 2.3
11  * @date 2024-05-03
12  * @brief Peripheral Access Layer for S32Z2_POWER_SCALING_UNIT
13  *
14  * This file contains register definitions and macros for easy access to their
15  * bit fields.
16  *
17  * This file assumes LITTLE endian system.
18  */
19 
20 /**
21 * @page misra_violations MISRA-C:2012 violations
22 *
23 * @section [global]
24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced
25 * The SoC header defines typedef for all modules.
26 *
27 * @section [global]
28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced
29 * The SoC header defines macros for all modules and registers.
30 *
31 * @section [global]
32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro
33 * These are generated macros used for accessing the bit-fields from registers.
34 *
35 * @section [global]
36 * Violates MISRA 2012 Required Rule 5.1, identifier clash
37 * The supported compilers use more than 31 significant characters for identifiers.
38 *
39 * @section [global]
40 * Violates MISRA 2012 Required Rule 5.2, identifier clash
41 * The supported compilers use more than 31 significant characters for identifiers.
42 *
43 * @section [global]
44 * Violates MISRA 2012 Required Rule 5.4, identifier clash
45 * The supported compilers use more than 31 significant characters for identifiers.
46 *
47 * @section [global]
48 * Violates MISRA 2012 Required Rule 5.5, identifier clash
49 * The supported compilers use more than 31 significant characters for identifiers.
50 *
51 * @section [global]
52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler
53 * This type qualifier is needed to ensure correct I/O access and addressing.
54 */
55 
56 /* Prevention from multiple including the same memory map */
57 #if !defined(S32Z2_POWER_SCALING_UNIT_H_)  /* Check if memory map has not been already included */
58 #define S32Z2_POWER_SCALING_UNIT_H_
59 
60 #include "S32Z2_COMMON.h"
61 
62 /* ----------------------------------------------------------------------------
63    -- POWER_SCALING_UNIT Peripheral Access Layer
64    ---------------------------------------------------------------------------- */
65 
66 /*!
67  * @addtogroup POWER_SCALING_UNIT_Peripheral_Access_Layer POWER_SCALING_UNIT Peripheral Access Layer
68  * @{
69  */
70 
71 /** POWER_SCALING_UNIT - Register Layout Typedef */
72 typedef struct {
73   __IO uint32_t PSVM;                              /**< PSU Power Save Mode Register, offset: 0x0 */
74   __IO uint32_t PGR;                               /**< PSU General Register, offset: 0x4 */
75 } POWER_SCALING_UNIT_Type, *POWER_SCALING_UNIT_MemMapPtr;
76 
77 /** Number of instances of the POWER_SCALING_UNIT module. */
78 #define POWER_SCALING_UNIT_INSTANCE_COUNT        (1u)
79 
80 /* POWER_SCALING_UNIT - Peripheral instance base addresses */
81 /** Peripheral CEVA_SPF2__POWER_SCALING_UNIT base address */
82 #define IP_CEVA_SPF2__POWER_SCALING_UNIT_BASE    (0x24400E50u)
83 /** Peripheral CEVA_SPF2__POWER_SCALING_UNIT base pointer */
84 #define IP_CEVA_SPF2__POWER_SCALING_UNIT         ((POWER_SCALING_UNIT_Type *)IP_CEVA_SPF2__POWER_SCALING_UNIT_BASE)
85 /** Array initializer of POWER_SCALING_UNIT peripheral base addresses */
86 #define IP_POWER_SCALING_UNIT_BASE_ADDRS         { IP_CEVA_SPF2__POWER_SCALING_UNIT_BASE }
87 /** Array initializer of POWER_SCALING_UNIT peripheral base pointers */
88 #define IP_POWER_SCALING_UNIT_BASE_PTRS          { IP_CEVA_SPF2__POWER_SCALING_UNIT }
89 
90 /* ----------------------------------------------------------------------------
91    -- POWER_SCALING_UNIT Register Masks
92    ---------------------------------------------------------------------------- */
93 
94 /*!
95  * @addtogroup POWER_SCALING_UNIT_Register_Masks POWER_SCALING_UNIT Register Masks
96  * @{
97  */
98 
99 /*! @name PSVM - PSU Power Save Mode Register */
100 /*! @{ */
101 
102 #define POWER_SCALING_UNIT_PSVM_PMOD_MASK        (0x3U)
103 #define POWER_SCALING_UNIT_PSVM_PMOD_SHIFT       (0U)
104 #define POWER_SCALING_UNIT_PSVM_PMOD_WIDTH       (2U)
105 #define POWER_SCALING_UNIT_PSVM_PMOD(x)          (((uint32_t)(((uint32_t)(x)) << POWER_SCALING_UNIT_PSVM_PMOD_SHIFT)) & POWER_SCALING_UNIT_PSVM_PMOD_MASK)
106 
107 #define POWER_SCALING_UNIT_PSVM_DBC_MASK         (0x4U)
108 #define POWER_SCALING_UNIT_PSVM_DBC_SHIFT        (2U)
109 #define POWER_SCALING_UNIT_PSVM_DBC_WIDTH        (1U)
110 #define POWER_SCALING_UNIT_PSVM_DBC(x)           (((uint32_t)(((uint32_t)(x)) << POWER_SCALING_UNIT_PSVM_DBC_SHIFT)) & POWER_SCALING_UNIT_PSVM_DBC_MASK)
111 /*! @} */
112 
113 /*! @name PGR - PSU General Register */
114 /*! @{ */
115 
116 #define POWER_SCALING_UNIT_PGR_MSS_AE_MASK       (0x4U)
117 #define POWER_SCALING_UNIT_PGR_MSS_AE_SHIFT      (2U)
118 #define POWER_SCALING_UNIT_PGR_MSS_AE_WIDTH      (1U)
119 #define POWER_SCALING_UNIT_PGR_MSS_AE(x)         (((uint32_t)(((uint32_t)(x)) << POWER_SCALING_UNIT_PGR_MSS_AE_SHIFT)) & POWER_SCALING_UNIT_PGR_MSS_AE_MASK)
120 
121 #define POWER_SCALING_UNIT_PGR_EDAP_AE_MASK      (0x8U)
122 #define POWER_SCALING_UNIT_PGR_EDAP_AE_SHIFT     (3U)
123 #define POWER_SCALING_UNIT_PGR_EDAP_AE_WIDTH     (1U)
124 #define POWER_SCALING_UNIT_PGR_EDAP_AE(x)        (((uint32_t)(((uint32_t)(x)) << POWER_SCALING_UNIT_PGR_EDAP_AE_SHIFT)) & POWER_SCALING_UNIT_PGR_EDAP_AE_MASK)
125 
126 #define POWER_SCALING_UNIT_PGR_QMAN_AE_MASK      (0x80U)
127 #define POWER_SCALING_UNIT_PGR_QMAN_AE_SHIFT     (7U)
128 #define POWER_SCALING_UNIT_PGR_QMAN_AE_WIDTH     (1U)
129 #define POWER_SCALING_UNIT_PGR_QMAN_AE(x)        (((uint32_t)(((uint32_t)(x)) << POWER_SCALING_UNIT_PGR_QMAN_AE_SHIFT)) & POWER_SCALING_UNIT_PGR_QMAN_AE_MASK)
130 /*! @} */
131 
132 /*!
133  * @}
134  */ /* end of group POWER_SCALING_UNIT_Register_Masks */
135 
136 /*!
137  * @}
138  */ /* end of group POWER_SCALING_UNIT_Peripheral_Access_Layer */
139 
140 #endif  /* #if !defined(S32Z2_POWER_SCALING_UNIT_H_) */
141