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Searched refs:IP_MC_CGM_4 (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-latest/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c2122 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK)… in Clock_Ip_Get_P4_SYS_CLK_Frequency()
2130 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK)… in Clock_Ip_Get_P4_SYS_DIV2_CLK_Frequency()
2139 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK)… in Clock_Ip_Get_HSE_SYS_DIV2_CLK_Frequency()
2259 …if (0U == ((IP_MC_CGM_4->MUX_2_CSS & MC_CGM_MUX_2_CSS_SELSTAT_MASK) >> MC_CGM_MUX_2_CSS_SELSTAT_SH… in Clock_Ip_Get_P4_PSI5_S_UTIL_CLK_Frequency()
2267 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_2_DC_3 & MC_CGM_MUX_2_DC_3_DE_MASK) >> … in Clock_Ip_Get_P4_PSI5_S_UTIL_CLK_Frequency()
2268 …Frequency /= (uint64)((((uint64)IP_MC_CGM_4->MUX_2_DC_3 & (uint64)MC_CGM_MUX_2_DC_3_DIV_MASK) >> (… in Clock_Ip_Get_P4_PSI5_S_UTIL_CLK_Frequency()
2410 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_0_CSS & MC_CGM_MUX_0_CSS_SELSTAT_MASK)… in Clock_Ip_Get_DMACRC4_CLK_Frequency()
2451 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_MC_CGM_4->MUX_1_CSS & MC_CGM_MUX_1_CSS_SELSTAT_MASK)… in Clock_Ip_Get_DMAMUX4_CLK_Frequency()
2452 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_4->MUX_1_DC_0 & MC_CGM_MUX_1_DC_0_DE_MASK) >> … in Clock_Ip_Get_DMAMUX4_CLK_Frequency()
2453 …Frequency /= (uint64)((((uint64)IP_MC_CGM_4->MUX_1_DC_0 & (uint64)MC_CGM_MUX_1_DC_0_DIV_MASK) >> (… in Clock_Ip_Get_DMAMUX4_CLK_Frequency()
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DClock_Ip_Data.c2739 { (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_0_CSC),
2740 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_1_CSC),
2741 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_2_CSC),
2742 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_3_CSC),
2743 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_4_CSC),
2744 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_5_CSC),
2745 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_6_CSC),
2746 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_7_CSC),
2747 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_8_CSC),
2748 (Clock_Ip_CgmMuxType*)(&IP_MC_CGM_4->MUX_9_CSC),
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/hal_nxp-latest/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Divider.c175 IP_MC_CGM_4->MUX_2_DC_2 &= ~MC_CGM_MUX_2_DC_2_DIV_FMT_MASK; in Clock_Ip_SetCgmXDeDivStatWithoutPhase()
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_MC_CGM.h209 #define IP_MC_CGM_4 ((MC_CGM_Type *)IP_MC_CGM_4_BASE) macro
221 … { IP_MC_CGM_0, IP_MC_CGM_1, IP_MC_CGM_2, IP_MC_CGM_3, IP_MC_CGM_4, IP_MC_CGM_5, I…