1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_MCM_CM7.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_MCM_CM7 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_MCM_CM7_H_) /* Check if memory map has not been already included */ 58 #define S32K344_MCM_CM7_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- MCM_CM7 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup MCM_CM7_Peripheral_Access_Layer MCM_CM7 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** MCM_CM7 - Size of Registers Arrays */ 72 #define MCM_CM7_LMEM_DESC__COUNT 5u 73 74 /** MCM_CM7 - Register Layout Typedef */ 75 typedef struct { 76 __I uint16_t PLREV; /**< SoC-defined Platform Revision, offset: 0x0 */ 77 __I uint16_t PCT; /**< Processor Core Type, offset: 0x2 */ 78 uint8_t RESERVED_0[8]; 79 __IO uint32_t CPCR; /**< Core Platform Control, offset: 0xC */ 80 __IO uint32_t ISCR; /**< Interrupt Status and Control, offset: 0x10 */ 81 uint8_t RESERVED_1[1004]; 82 __I uint32_t LMEM_DESC[MCM_CM7_LMEM_DESC__COUNT]; /**< Local Memory Descriptor 0..Local Memory Descriptor 4, array offset: 0x400, array step: 0x4 */ 83 } MCM_CM7_Type, *MCM_CM7_MemMapPtr; 84 85 /** Number of instances of the MCM_CM7 module. */ 86 #define MCM_CM7_INSTANCE_COUNT (1u) 87 88 /* MCM_CM7 - Peripheral instance base addresses */ 89 /** Peripheral MCM_0_CM7 base address */ 90 #define IP_MCM_0_CM7_BASE (0xE0080000u) 91 /** Peripheral MCM_0_CM7 base pointer */ 92 #define IP_MCM_0_CM7 ((MCM_CM7_Type *)IP_MCM_0_CM7_BASE) 93 /** Array initializer of MCM_CM7 peripheral base addresses */ 94 #define IP_MCM_CM7_BASE_ADDRS { IP_MCM_0_CM7_BASE } 95 /** Array initializer of MCM_CM7 peripheral base pointers */ 96 #define IP_MCM_CM7_BASE_PTRS { IP_MCM_0_CM7 } 97 98 /* ---------------------------------------------------------------------------- 99 -- MCM_CM7 Register Masks 100 ---------------------------------------------------------------------------- */ 101 102 /*! 103 * @addtogroup MCM_CM7_Register_Masks MCM_CM7 Register Masks 104 * @{ 105 */ 106 107 /*! @name PLREV - SoC-defined Platform Revision */ 108 /*! @{ */ 109 110 #define MCM_CM7_PLREV_PLREV_MASK (0xFFFFU) 111 #define MCM_CM7_PLREV_PLREV_SHIFT (0U) 112 #define MCM_CM7_PLREV_PLREV_WIDTH (16U) 113 #define MCM_CM7_PLREV_PLREV(x) (((uint16_t)(((uint16_t)(x)) << MCM_CM7_PLREV_PLREV_SHIFT)) & MCM_CM7_PLREV_PLREV_MASK) 114 /*! @} */ 115 116 /*! @name PCT - Processor Core Type */ 117 /*! @{ */ 118 119 #define MCM_CM7_PCT_PCT_MASK (0xFFFFU) 120 #define MCM_CM7_PCT_PCT_SHIFT (0U) 121 #define MCM_CM7_PCT_PCT_WIDTH (16U) 122 #define MCM_CM7_PCT_PCT(x) (((uint16_t)(((uint16_t)(x)) << MCM_CM7_PCT_PCT_SHIFT)) & MCM_CM7_PCT_PCT_MASK) 123 /*! @} */ 124 125 /*! @name CPCR - Core Platform Control */ 126 /*! @{ */ 127 128 #define MCM_CM7_CPCR_CM7_AHBSPRI_MASK (0x8000000U) 129 #define MCM_CM7_CPCR_CM7_AHBSPRI_SHIFT (27U) 130 #define MCM_CM7_CPCR_CM7_AHBSPRI_WIDTH (1U) 131 #define MCM_CM7_CPCR_CM7_AHBSPRI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_CPCR_CM7_AHBSPRI_SHIFT)) & MCM_CM7_CPCR_CM7_AHBSPRI_MASK) 132 /*! @} */ 133 134 /*! @name ISCR - Interrupt Status and Control */ 135 /*! @{ */ 136 137 #define MCM_CM7_ISCR_WABS_MASK (0x20U) 138 #define MCM_CM7_ISCR_WABS_SHIFT (5U) 139 #define MCM_CM7_ISCR_WABS_WIDTH (1U) 140 #define MCM_CM7_ISCR_WABS(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_ISCR_WABS_SHIFT)) & MCM_CM7_ISCR_WABS_MASK) 141 142 #define MCM_CM7_ISCR_WABSO_MASK (0x40U) 143 #define MCM_CM7_ISCR_WABSO_SHIFT (6U) 144 #define MCM_CM7_ISCR_WABSO_WIDTH (1U) 145 #define MCM_CM7_ISCR_WABSO(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_ISCR_WABSO_SHIFT)) & MCM_CM7_ISCR_WABSO_MASK) 146 147 #define MCM_CM7_ISCR_FIOC_MASK (0x100U) 148 #define MCM_CM7_ISCR_FIOC_SHIFT (8U) 149 #define MCM_CM7_ISCR_FIOC_WIDTH (1U) 150 #define MCM_CM7_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_ISCR_FIOC_SHIFT)) & MCM_CM7_ISCR_FIOC_MASK) 151 152 #define MCM_CM7_ISCR_FDZC_MASK (0x200U) 153 #define MCM_CM7_ISCR_FDZC_SHIFT (9U) 154 #define MCM_CM7_ISCR_FDZC_WIDTH (1U) 155 #define MCM_CM7_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_ISCR_FDZC_SHIFT)) & MCM_CM7_ISCR_FDZC_MASK) 156 157 #define MCM_CM7_ISCR_FOFC_MASK (0x400U) 158 #define MCM_CM7_ISCR_FOFC_SHIFT (10U) 159 #define MCM_CM7_ISCR_FOFC_WIDTH (1U) 160 #define MCM_CM7_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_ISCR_FOFC_SHIFT)) & MCM_CM7_ISCR_FOFC_MASK) 161 162 #define MCM_CM7_ISCR_FUFC_MASK (0x800U) 163 #define MCM_CM7_ISCR_FUFC_SHIFT (11U) 164 #define MCM_CM7_ISCR_FUFC_WIDTH (1U) 165 #define MCM_CM7_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_ISCR_FUFC_SHIFT)) & MCM_CM7_ISCR_FUFC_MASK) 166 167 #define MCM_CM7_ISCR_FIXC_MASK (0x1000U) 168 #define MCM_CM7_ISCR_FIXC_SHIFT (12U) 169 #define MCM_CM7_ISCR_FIXC_WIDTH (1U) 170 #define MCM_CM7_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_ISCR_FIXC_SHIFT)) & MCM_CM7_ISCR_FIXC_MASK) 171 172 #define MCM_CM7_ISCR_FIDC_MASK (0x8000U) 173 #define MCM_CM7_ISCR_FIDC_SHIFT (15U) 174 #define MCM_CM7_ISCR_FIDC_WIDTH (1U) 175 #define MCM_CM7_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_ISCR_FIDC_SHIFT)) & MCM_CM7_ISCR_FIDC_MASK) 176 177 #define MCM_CM7_ISCR_WABE_MASK (0x200000U) 178 #define MCM_CM7_ISCR_WABE_SHIFT (21U) 179 #define MCM_CM7_ISCR_WABE_WIDTH (1U) 180 #define MCM_CM7_ISCR_WABE(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_ISCR_WABE_SHIFT)) & MCM_CM7_ISCR_WABE_MASK) 181 182 #define MCM_CM7_ISCR_FIOCE_MASK (0x1000000U) 183 #define MCM_CM7_ISCR_FIOCE_SHIFT (24U) 184 #define MCM_CM7_ISCR_FIOCE_WIDTH (1U) 185 #define MCM_CM7_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_ISCR_FIOCE_SHIFT)) & MCM_CM7_ISCR_FIOCE_MASK) 186 187 #define MCM_CM7_ISCR_FDZCE_MASK (0x2000000U) 188 #define MCM_CM7_ISCR_FDZCE_SHIFT (25U) 189 #define MCM_CM7_ISCR_FDZCE_WIDTH (1U) 190 #define MCM_CM7_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_ISCR_FDZCE_SHIFT)) & MCM_CM7_ISCR_FDZCE_MASK) 191 192 #define MCM_CM7_ISCR_FOFCE_MASK (0x4000000U) 193 #define MCM_CM7_ISCR_FOFCE_SHIFT (26U) 194 #define MCM_CM7_ISCR_FOFCE_WIDTH (1U) 195 #define MCM_CM7_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_ISCR_FOFCE_SHIFT)) & MCM_CM7_ISCR_FOFCE_MASK) 196 197 #define MCM_CM7_ISCR_FUFCE_MASK (0x8000000U) 198 #define MCM_CM7_ISCR_FUFCE_SHIFT (27U) 199 #define MCM_CM7_ISCR_FUFCE_WIDTH (1U) 200 #define MCM_CM7_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_ISCR_FUFCE_SHIFT)) & MCM_CM7_ISCR_FUFCE_MASK) 201 202 #define MCM_CM7_ISCR_FIXCE_MASK (0x10000000U) 203 #define MCM_CM7_ISCR_FIXCE_SHIFT (28U) 204 #define MCM_CM7_ISCR_FIXCE_WIDTH (1U) 205 #define MCM_CM7_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_ISCR_FIXCE_SHIFT)) & MCM_CM7_ISCR_FIXCE_MASK) 206 207 #define MCM_CM7_ISCR_FIDCE_MASK (0x80000000U) 208 #define MCM_CM7_ISCR_FIDCE_SHIFT (31U) 209 #define MCM_CM7_ISCR_FIDCE_WIDTH (1U) 210 #define MCM_CM7_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_ISCR_FIDCE_SHIFT)) & MCM_CM7_ISCR_FIDCE_MASK) 211 /*! @} */ 212 213 /*! @name LMEM_DESC - Local Memory Descriptor 0..Local Memory Descriptor 4 */ 214 /*! @{ */ 215 216 #define MCM_CM7_LMEM_DESC_MT_MASK (0xE000U) 217 #define MCM_CM7_LMEM_DESC_MT_SHIFT (13U) 218 #define MCM_CM7_LMEM_DESC_MT_WIDTH (3U) 219 #define MCM_CM7_LMEM_DESC_MT(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_LMEM_DESC_MT_SHIFT)) & MCM_CM7_LMEM_DESC_MT_MASK) 220 221 #define MCM_CM7_LMEM_DESC_DPW_MASK (0xE0000U) 222 #define MCM_CM7_LMEM_DESC_DPW_SHIFT (17U) 223 #define MCM_CM7_LMEM_DESC_DPW_WIDTH (3U) 224 #define MCM_CM7_LMEM_DESC_DPW(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_LMEM_DESC_DPW_SHIFT)) & MCM_CM7_LMEM_DESC_DPW_MASK) 225 226 #define MCM_CM7_LMEM_DESC_WY_MASK (0xF00000U) 227 #define MCM_CM7_LMEM_DESC_WY_SHIFT (20U) 228 #define MCM_CM7_LMEM_DESC_WY_WIDTH (4U) 229 #define MCM_CM7_LMEM_DESC_WY(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_LMEM_DESC_WY_SHIFT)) & MCM_CM7_LMEM_DESC_WY_MASK) 230 231 #define MCM_CM7_LMEM_DESC_LMSZ_MASK (0xF000000U) 232 #define MCM_CM7_LMEM_DESC_LMSZ_SHIFT (24U) 233 #define MCM_CM7_LMEM_DESC_LMSZ_WIDTH (4U) 234 #define MCM_CM7_LMEM_DESC_LMSZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_LMEM_DESC_LMSZ_SHIFT)) & MCM_CM7_LMEM_DESC_LMSZ_MASK) 235 236 #define MCM_CM7_LMEM_DESC_LMSZH_MASK (0x10000000U) 237 #define MCM_CM7_LMEM_DESC_LMSZH_SHIFT (28U) 238 #define MCM_CM7_LMEM_DESC_LMSZH_WIDTH (1U) 239 #define MCM_CM7_LMEM_DESC_LMSZH(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_LMEM_DESC_LMSZH_SHIFT)) & MCM_CM7_LMEM_DESC_LMSZH_MASK) 240 241 #define MCM_CM7_LMEM_DESC_LMV_MASK (0x80000000U) 242 #define MCM_CM7_LMEM_DESC_LMV_SHIFT (31U) 243 #define MCM_CM7_LMEM_DESC_LMV_WIDTH (1U) 244 #define MCM_CM7_LMEM_DESC_LMV(x) (((uint32_t)(((uint32_t)(x)) << MCM_CM7_LMEM_DESC_LMV_SHIFT)) & MCM_CM7_LMEM_DESC_LMV_MASK) 245 /*! @} */ 246 247 /*! 248 * @} 249 */ /* end of group MCM_CM7_Register_Masks */ 250 251 /*! 252 * @} 253 */ /* end of group MCM_CM7_Peripheral_Access_Layer */ 254 255 #endif /* #if !defined(S32K344_MCM_CM7_H_) */ 256
