1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_GTMSS.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_GTMSS 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_GTMSS_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_GTMSS_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- GTMSS Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup GTMSS_Peripheral_Access_Layer GTMSS Peripheral Access Layer 68 * @{ 69 */ 70 71 /** GTMSS - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t IRQ_CFG0; /**< IRQ Configuration Register for Cluster 0, offset: 0x0 */ 74 __IO uint32_t IRQ_CFG1; /**< IRQ Confoguration Register for Cluster 1, offset: 0x4 */ 75 __IO uint32_t IRQ_CFG2; /**< IRQ Confoguration Register for Cluster 2, offset: 0x8 */ 76 __IO uint32_t IRQ_CFG3; /**< IRQ Confoguration Register for Cluster 3, offset: 0xC */ 77 uint8_t RESERVED_0[8176]; 78 __IO uint32_t DBG_DID; /**< Debug domain ID register, offset: 0x2000 */ 79 } GTMSS_Type, *GTMSS_MemMapPtr; 80 81 /** Number of instances of the GTMSS module. */ 82 #define GTMSS_INSTANCE_COUNT (1u) 83 84 /* GTMSS - Peripheral instance base addresses */ 85 /** Peripheral GTMSS base address */ 86 #define IP_GTMSS_BASE (0x4037C000u) 87 /** Peripheral GTMSS base pointer */ 88 #define IP_GTMSS ((GTMSS_Type *)IP_GTMSS_BASE) 89 /** Array initializer of GTMSS peripheral base addresses */ 90 #define IP_GTMSS_BASE_ADDRS { IP_GTMSS_BASE } 91 /** Array initializer of GTMSS peripheral base pointers */ 92 #define IP_GTMSS_BASE_PTRS { IP_GTMSS } 93 94 /* ---------------------------------------------------------------------------- 95 -- GTMSS Register Masks 96 ---------------------------------------------------------------------------- */ 97 98 /*! 99 * @addtogroup GTMSS_Register_Masks GTMSS Register Masks 100 * @{ 101 */ 102 103 /*! @name IRQ_CFG0 - IRQ Configuration Register for Cluster 0 */ 104 /*! @{ */ 105 106 #define GTMSS_IRQ_CFG0_FIFO0_MASK (0x10U) 107 #define GTMSS_IRQ_CFG0_FIFO0_SHIFT (4U) 108 #define GTMSS_IRQ_CFG0_FIFO0_WIDTH (1U) 109 #define GTMSS_IRQ_CFG0_FIFO0(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG0_FIFO0_SHIFT)) & GTMSS_IRQ_CFG0_FIFO0_MASK) 110 111 #define GTMSS_IRQ_CFG0_FIFO1_MASK (0x20U) 112 #define GTMSS_IRQ_CFG0_FIFO1_SHIFT (5U) 113 #define GTMSS_IRQ_CFG0_FIFO1_WIDTH (1U) 114 #define GTMSS_IRQ_CFG0_FIFO1(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG0_FIFO1_SHIFT)) & GTMSS_IRQ_CFG0_FIFO1_MASK) 115 116 #define GTMSS_IRQ_CFG0_FIFO2_MASK (0x40U) 117 #define GTMSS_IRQ_CFG0_FIFO2_SHIFT (6U) 118 #define GTMSS_IRQ_CFG0_FIFO2_WIDTH (1U) 119 #define GTMSS_IRQ_CFG0_FIFO2(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG0_FIFO2_SHIFT)) & GTMSS_IRQ_CFG0_FIFO2_MASK) 120 121 #define GTMSS_IRQ_CFG0_FIFO3_MASK (0x80U) 122 #define GTMSS_IRQ_CFG0_FIFO3_SHIFT (7U) 123 #define GTMSS_IRQ_CFG0_FIFO3_WIDTH (1U) 124 #define GTMSS_IRQ_CFG0_FIFO3(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG0_FIFO3_SHIFT)) & GTMSS_IRQ_CFG0_FIFO3_MASK) 125 126 #define GTMSS_IRQ_CFG0_TIM6_MASK (0x100U) 127 #define GTMSS_IRQ_CFG0_TIM6_SHIFT (8U) 128 #define GTMSS_IRQ_CFG0_TIM6_WIDTH (1U) 129 #define GTMSS_IRQ_CFG0_TIM6(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG0_TIM6_SHIFT)) & GTMSS_IRQ_CFG0_TIM6_MASK) 130 131 #define GTMSS_IRQ_CFG0_TIM7_MASK (0x200U) 132 #define GTMSS_IRQ_CFG0_TIM7_SHIFT (9U) 133 #define GTMSS_IRQ_CFG0_TIM7_WIDTH (1U) 134 #define GTMSS_IRQ_CFG0_TIM7(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG0_TIM7_SHIFT)) & GTMSS_IRQ_CFG0_TIM7_MASK) 135 136 #define GTMSS_IRQ_CFG0_ATOM1_MASK (0x1000U) 137 #define GTMSS_IRQ_CFG0_ATOM1_SHIFT (12U) 138 #define GTMSS_IRQ_CFG0_ATOM1_WIDTH (1U) 139 #define GTMSS_IRQ_CFG0_ATOM1(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG0_ATOM1_SHIFT)) & GTMSS_IRQ_CFG0_ATOM1_MASK) 140 141 #define GTMSS_IRQ_CFG0_ATOM3_MASK (0x2000U) 142 #define GTMSS_IRQ_CFG0_ATOM3_SHIFT (13U) 143 #define GTMSS_IRQ_CFG0_ATOM3_WIDTH (1U) 144 #define GTMSS_IRQ_CFG0_ATOM3(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG0_ATOM3_SHIFT)) & GTMSS_IRQ_CFG0_ATOM3_MASK) 145 146 #define GTMSS_IRQ_CFG0_MCS0_MASK (0x10000U) 147 #define GTMSS_IRQ_CFG0_MCS0_SHIFT (16U) 148 #define GTMSS_IRQ_CFG0_MCS0_WIDTH (1U) 149 #define GTMSS_IRQ_CFG0_MCS0(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG0_MCS0_SHIFT)) & GTMSS_IRQ_CFG0_MCS0_MASK) 150 151 #define GTMSS_IRQ_CFG0_MCS1_MASK (0x20000U) 152 #define GTMSS_IRQ_CFG0_MCS1_SHIFT (17U) 153 #define GTMSS_IRQ_CFG0_MCS1_WIDTH (1U) 154 #define GTMSS_IRQ_CFG0_MCS1(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG0_MCS1_SHIFT)) & GTMSS_IRQ_CFG0_MCS1_MASK) 155 156 #define GTMSS_IRQ_CFG0_MCS2_MASK (0x40000U) 157 #define GTMSS_IRQ_CFG0_MCS2_SHIFT (18U) 158 #define GTMSS_IRQ_CFG0_MCS2_WIDTH (1U) 159 #define GTMSS_IRQ_CFG0_MCS2(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG0_MCS2_SHIFT)) & GTMSS_IRQ_CFG0_MCS2_MASK) 160 161 #define GTMSS_IRQ_CFG0_MCS3_MASK (0x80000U) 162 #define GTMSS_IRQ_CFG0_MCS3_SHIFT (19U) 163 #define GTMSS_IRQ_CFG0_MCS3_WIDTH (1U) 164 #define GTMSS_IRQ_CFG0_MCS3(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG0_MCS3_SHIFT)) & GTMSS_IRQ_CFG0_MCS3_MASK) 165 166 #define GTMSS_IRQ_CFG0_LCK_MASK (0x80000000U) 167 #define GTMSS_IRQ_CFG0_LCK_SHIFT (31U) 168 #define GTMSS_IRQ_CFG0_LCK_WIDTH (1U) 169 #define GTMSS_IRQ_CFG0_LCK(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG0_LCK_SHIFT)) & GTMSS_IRQ_CFG0_LCK_MASK) 170 /*! @} */ 171 172 /*! @name IRQ_CFG1 - IRQ Confoguration Register for Cluster 1 */ 173 /*! @{ */ 174 175 #define GTMSS_IRQ_CFG1_TIO3_MASK (0x1U) 176 #define GTMSS_IRQ_CFG1_TIO3_SHIFT (0U) 177 #define GTMSS_IRQ_CFG1_TIO3_WIDTH (1U) 178 #define GTMSS_IRQ_CFG1_TIO3(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG1_TIO3_SHIFT)) & GTMSS_IRQ_CFG1_TIO3_MASK) 179 180 #define GTMSS_IRQ_CFG1_TIO5_MASK (0x2U) 181 #define GTMSS_IRQ_CFG1_TIO5_SHIFT (1U) 182 #define GTMSS_IRQ_CFG1_TIO5_WIDTH (1U) 183 #define GTMSS_IRQ_CFG1_TIO5(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG1_TIO5_SHIFT)) & GTMSS_IRQ_CFG1_TIO5_MASK) 184 185 #define GTMSS_IRQ_CFG1_TIO7_MASK (0x4U) 186 #define GTMSS_IRQ_CFG1_TIO7_SHIFT (2U) 187 #define GTMSS_IRQ_CFG1_TIO7_WIDTH (1U) 188 #define GTMSS_IRQ_CFG1_TIO7(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG1_TIO7_SHIFT)) & GTMSS_IRQ_CFG1_TIO7_MASK) 189 190 #define GTMSS_IRQ_CFG1_TIM6_MASK (0x100U) 191 #define GTMSS_IRQ_CFG1_TIM6_SHIFT (8U) 192 #define GTMSS_IRQ_CFG1_TIM6_WIDTH (1U) 193 #define GTMSS_IRQ_CFG1_TIM6(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG1_TIM6_SHIFT)) & GTMSS_IRQ_CFG1_TIM6_MASK) 194 195 #define GTMSS_IRQ_CFG1_TIM7_MASK (0x200U) 196 #define GTMSS_IRQ_CFG1_TIM7_SHIFT (9U) 197 #define GTMSS_IRQ_CFG1_TIM7_WIDTH (1U) 198 #define GTMSS_IRQ_CFG1_TIM7(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG1_TIM7_SHIFT)) & GTMSS_IRQ_CFG1_TIM7_MASK) 199 200 #define GTMSS_IRQ_CFG1_ATOM1_MASK (0x1000U) 201 #define GTMSS_IRQ_CFG1_ATOM1_SHIFT (12U) 202 #define GTMSS_IRQ_CFG1_ATOM1_WIDTH (1U) 203 #define GTMSS_IRQ_CFG1_ATOM1(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG1_ATOM1_SHIFT)) & GTMSS_IRQ_CFG1_ATOM1_MASK) 204 205 #define GTMSS_IRQ_CFG1_ATOM3_MASK (0x2000U) 206 #define GTMSS_IRQ_CFG1_ATOM3_SHIFT (13U) 207 #define GTMSS_IRQ_CFG1_ATOM3_WIDTH (1U) 208 #define GTMSS_IRQ_CFG1_ATOM3(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG1_ATOM3_SHIFT)) & GTMSS_IRQ_CFG1_ATOM3_MASK) 209 210 #define GTMSS_IRQ_CFG1_MCS0_MASK (0x10000U) 211 #define GTMSS_IRQ_CFG1_MCS0_SHIFT (16U) 212 #define GTMSS_IRQ_CFG1_MCS0_WIDTH (1U) 213 #define GTMSS_IRQ_CFG1_MCS0(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG1_MCS0_SHIFT)) & GTMSS_IRQ_CFG1_MCS0_MASK) 214 215 #define GTMSS_IRQ_CFG1_MCS1_MASK (0x20000U) 216 #define GTMSS_IRQ_CFG1_MCS1_SHIFT (17U) 217 #define GTMSS_IRQ_CFG1_MCS1_WIDTH (1U) 218 #define GTMSS_IRQ_CFG1_MCS1(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG1_MCS1_SHIFT)) & GTMSS_IRQ_CFG1_MCS1_MASK) 219 220 #define GTMSS_IRQ_CFG1_MCS2_MASK (0x40000U) 221 #define GTMSS_IRQ_CFG1_MCS2_SHIFT (18U) 222 #define GTMSS_IRQ_CFG1_MCS2_WIDTH (1U) 223 #define GTMSS_IRQ_CFG1_MCS2(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG1_MCS2_SHIFT)) & GTMSS_IRQ_CFG1_MCS2_MASK) 224 225 #define GTMSS_IRQ_CFG1_MCS3_MASK (0x80000U) 226 #define GTMSS_IRQ_CFG1_MCS3_SHIFT (19U) 227 #define GTMSS_IRQ_CFG1_MCS3_WIDTH (1U) 228 #define GTMSS_IRQ_CFG1_MCS3(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG1_MCS3_SHIFT)) & GTMSS_IRQ_CFG1_MCS3_MASK) 229 230 #define GTMSS_IRQ_CFG1_LCK_MASK (0x80000000U) 231 #define GTMSS_IRQ_CFG1_LCK_SHIFT (31U) 232 #define GTMSS_IRQ_CFG1_LCK_WIDTH (1U) 233 #define GTMSS_IRQ_CFG1_LCK(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG1_LCK_SHIFT)) & GTMSS_IRQ_CFG1_LCK_MASK) 234 /*! @} */ 235 236 /*! @name IRQ_CFG2 - IRQ Confoguration Register for Cluster 2 */ 237 /*! @{ */ 238 239 #define GTMSS_IRQ_CFG2_TIO3_MASK (0x1U) 240 #define GTMSS_IRQ_CFG2_TIO3_SHIFT (0U) 241 #define GTMSS_IRQ_CFG2_TIO3_WIDTH (1U) 242 #define GTMSS_IRQ_CFG2_TIO3(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG2_TIO3_SHIFT)) & GTMSS_IRQ_CFG2_TIO3_MASK) 243 244 #define GTMSS_IRQ_CFG2_TIO5_MASK (0x2U) 245 #define GTMSS_IRQ_CFG2_TIO5_SHIFT (1U) 246 #define GTMSS_IRQ_CFG2_TIO5_WIDTH (1U) 247 #define GTMSS_IRQ_CFG2_TIO5(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG2_TIO5_SHIFT)) & GTMSS_IRQ_CFG2_TIO5_MASK) 248 249 #define GTMSS_IRQ_CFG2_TIO7_MASK (0x4U) 250 #define GTMSS_IRQ_CFG2_TIO7_SHIFT (2U) 251 #define GTMSS_IRQ_CFG2_TIO7_WIDTH (1U) 252 #define GTMSS_IRQ_CFG2_TIO7(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG2_TIO7_SHIFT)) & GTMSS_IRQ_CFG2_TIO7_MASK) 253 254 #define GTMSS_IRQ_CFG2_TIM6_MASK (0x100U) 255 #define GTMSS_IRQ_CFG2_TIM6_SHIFT (8U) 256 #define GTMSS_IRQ_CFG2_TIM6_WIDTH (1U) 257 #define GTMSS_IRQ_CFG2_TIM6(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG2_TIM6_SHIFT)) & GTMSS_IRQ_CFG2_TIM6_MASK) 258 259 #define GTMSS_IRQ_CFG2_TIM7_MASK (0x200U) 260 #define GTMSS_IRQ_CFG2_TIM7_SHIFT (9U) 261 #define GTMSS_IRQ_CFG2_TIM7_WIDTH (1U) 262 #define GTMSS_IRQ_CFG2_TIM7(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG2_TIM7_SHIFT)) & GTMSS_IRQ_CFG2_TIM7_MASK) 263 264 #define GTMSS_IRQ_CFG2_ATOM1_MASK (0x1000U) 265 #define GTMSS_IRQ_CFG2_ATOM1_SHIFT (12U) 266 #define GTMSS_IRQ_CFG2_ATOM1_WIDTH (1U) 267 #define GTMSS_IRQ_CFG2_ATOM1(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG2_ATOM1_SHIFT)) & GTMSS_IRQ_CFG2_ATOM1_MASK) 268 269 #define GTMSS_IRQ_CFG2_ATOM3_MASK (0x2000U) 270 #define GTMSS_IRQ_CFG2_ATOM3_SHIFT (13U) 271 #define GTMSS_IRQ_CFG2_ATOM3_WIDTH (1U) 272 #define GTMSS_IRQ_CFG2_ATOM3(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG2_ATOM3_SHIFT)) & GTMSS_IRQ_CFG2_ATOM3_MASK) 273 274 #define GTMSS_IRQ_CFG2_MCS0_MASK (0x10000U) 275 #define GTMSS_IRQ_CFG2_MCS0_SHIFT (16U) 276 #define GTMSS_IRQ_CFG2_MCS0_WIDTH (1U) 277 #define GTMSS_IRQ_CFG2_MCS0(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG2_MCS0_SHIFT)) & GTMSS_IRQ_CFG2_MCS0_MASK) 278 279 #define GTMSS_IRQ_CFG2_MCS1_MASK (0x20000U) 280 #define GTMSS_IRQ_CFG2_MCS1_SHIFT (17U) 281 #define GTMSS_IRQ_CFG2_MCS1_WIDTH (1U) 282 #define GTMSS_IRQ_CFG2_MCS1(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG2_MCS1_SHIFT)) & GTMSS_IRQ_CFG2_MCS1_MASK) 283 284 #define GTMSS_IRQ_CFG2_MCS2_MASK (0x40000U) 285 #define GTMSS_IRQ_CFG2_MCS2_SHIFT (18U) 286 #define GTMSS_IRQ_CFG2_MCS2_WIDTH (1U) 287 #define GTMSS_IRQ_CFG2_MCS2(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG2_MCS2_SHIFT)) & GTMSS_IRQ_CFG2_MCS2_MASK) 288 289 #define GTMSS_IRQ_CFG2_MCS3_MASK (0x80000U) 290 #define GTMSS_IRQ_CFG2_MCS3_SHIFT (19U) 291 #define GTMSS_IRQ_CFG2_MCS3_WIDTH (1U) 292 #define GTMSS_IRQ_CFG2_MCS3(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG2_MCS3_SHIFT)) & GTMSS_IRQ_CFG2_MCS3_MASK) 293 294 #define GTMSS_IRQ_CFG2_LCK_MASK (0x80000000U) 295 #define GTMSS_IRQ_CFG2_LCK_SHIFT (31U) 296 #define GTMSS_IRQ_CFG2_LCK_WIDTH (1U) 297 #define GTMSS_IRQ_CFG2_LCK(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG2_LCK_SHIFT)) & GTMSS_IRQ_CFG2_LCK_MASK) 298 /*! @} */ 299 300 /*! @name IRQ_CFG3 - IRQ Confoguration Register for Cluster 3 */ 301 /*! @{ */ 302 303 #define GTMSS_IRQ_CFG3_TIO3_MASK (0x1U) 304 #define GTMSS_IRQ_CFG3_TIO3_SHIFT (0U) 305 #define GTMSS_IRQ_CFG3_TIO3_WIDTH (1U) 306 #define GTMSS_IRQ_CFG3_TIO3(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG3_TIO3_SHIFT)) & GTMSS_IRQ_CFG3_TIO3_MASK) 307 308 #define GTMSS_IRQ_CFG3_TIO5_MASK (0x2U) 309 #define GTMSS_IRQ_CFG3_TIO5_SHIFT (1U) 310 #define GTMSS_IRQ_CFG3_TIO5_WIDTH (1U) 311 #define GTMSS_IRQ_CFG3_TIO5(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG3_TIO5_SHIFT)) & GTMSS_IRQ_CFG3_TIO5_MASK) 312 313 #define GTMSS_IRQ_CFG3_TIO7_MASK (0x4U) 314 #define GTMSS_IRQ_CFG3_TIO7_SHIFT (2U) 315 #define GTMSS_IRQ_CFG3_TIO7_WIDTH (1U) 316 #define GTMSS_IRQ_CFG3_TIO7(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG3_TIO7_SHIFT)) & GTMSS_IRQ_CFG3_TIO7_MASK) 317 318 #define GTMSS_IRQ_CFG3_ATOM1_MASK (0x1000U) 319 #define GTMSS_IRQ_CFG3_ATOM1_SHIFT (12U) 320 #define GTMSS_IRQ_CFG3_ATOM1_WIDTH (1U) 321 #define GTMSS_IRQ_CFG3_ATOM1(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG3_ATOM1_SHIFT)) & GTMSS_IRQ_CFG3_ATOM1_MASK) 322 323 #define GTMSS_IRQ_CFG3_ATOM3_MASK (0x2000U) 324 #define GTMSS_IRQ_CFG3_ATOM3_SHIFT (13U) 325 #define GTMSS_IRQ_CFG3_ATOM3_WIDTH (1U) 326 #define GTMSS_IRQ_CFG3_ATOM3(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG3_ATOM3_SHIFT)) & GTMSS_IRQ_CFG3_ATOM3_MASK) 327 328 #define GTMSS_IRQ_CFG3_MCS0_MASK (0x10000U) 329 #define GTMSS_IRQ_CFG3_MCS0_SHIFT (16U) 330 #define GTMSS_IRQ_CFG3_MCS0_WIDTH (1U) 331 #define GTMSS_IRQ_CFG3_MCS0(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG3_MCS0_SHIFT)) & GTMSS_IRQ_CFG3_MCS0_MASK) 332 333 #define GTMSS_IRQ_CFG3_MCS1_MASK (0x20000U) 334 #define GTMSS_IRQ_CFG3_MCS1_SHIFT (17U) 335 #define GTMSS_IRQ_CFG3_MCS1_WIDTH (1U) 336 #define GTMSS_IRQ_CFG3_MCS1(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG3_MCS1_SHIFT)) & GTMSS_IRQ_CFG3_MCS1_MASK) 337 338 #define GTMSS_IRQ_CFG3_MCS2_MASK (0x40000U) 339 #define GTMSS_IRQ_CFG3_MCS2_SHIFT (18U) 340 #define GTMSS_IRQ_CFG3_MCS2_WIDTH (1U) 341 #define GTMSS_IRQ_CFG3_MCS2(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG3_MCS2_SHIFT)) & GTMSS_IRQ_CFG3_MCS2_MASK) 342 343 #define GTMSS_IRQ_CFG3_MCS3_MASK (0x80000U) 344 #define GTMSS_IRQ_CFG3_MCS3_SHIFT (19U) 345 #define GTMSS_IRQ_CFG3_MCS3_WIDTH (1U) 346 #define GTMSS_IRQ_CFG3_MCS3(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG3_MCS3_SHIFT)) & GTMSS_IRQ_CFG3_MCS3_MASK) 347 348 #define GTMSS_IRQ_CFG3_LCK_MASK (0x80000000U) 349 #define GTMSS_IRQ_CFG3_LCK_SHIFT (31U) 350 #define GTMSS_IRQ_CFG3_LCK_WIDTH (1U) 351 #define GTMSS_IRQ_CFG3_LCK(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_IRQ_CFG3_LCK_SHIFT)) & GTMSS_IRQ_CFG3_LCK_MASK) 352 /*! @} */ 353 354 /*! @name DBG_DID - Debug domain ID register */ 355 /*! @{ */ 356 357 #define GTMSS_DBG_DID_DID_MASK (0x78U) 358 #define GTMSS_DBG_DID_DID_SHIFT (3U) 359 #define GTMSS_DBG_DID_DID_WIDTH (4U) 360 #define GTMSS_DBG_DID_DID(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_DBG_DID_DID_SHIFT)) & GTMSS_DBG_DID_DID_MASK) 361 362 #define GTMSS_DBG_DID_EN_MASK (0x40000000U) 363 #define GTMSS_DBG_DID_EN_SHIFT (30U) 364 #define GTMSS_DBG_DID_EN_WIDTH (1U) 365 #define GTMSS_DBG_DID_EN(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_DBG_DID_EN_SHIFT)) & GTMSS_DBG_DID_EN_MASK) 366 367 #define GTMSS_DBG_DID_LCK_MASK (0x80000000U) 368 #define GTMSS_DBG_DID_LCK_SHIFT (31U) 369 #define GTMSS_DBG_DID_LCK_WIDTH (1U) 370 #define GTMSS_DBG_DID_LCK(x) (((uint32_t)(((uint32_t)(x)) << GTMSS_DBG_DID_LCK_SHIFT)) & GTMSS_DBG_DID_LCK_MASK) 371 /*! @} */ 372 373 /*! 374 * @} 375 */ /* end of group GTMSS_Register_Masks */ 376 377 /*! 378 * @} 379 */ /* end of group GTMSS_Peripheral_Access_Layer */ 380 381 #endif /* #if !defined(S32Z2_GTMSS_H_) */ 382
