1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_GPR6.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_GPR6 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_GPR6_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_GPR6_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- GPR6 Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup GPR6_Peripheral_Access_Layer GPR6 Peripheral Access Layer 68 * @{ 69 */ 70 71 /** GPR6 - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t LVFCCUGD6; /**< VFCCU Global DID register 6, offset: 0x0 */ 74 __IO uint32_t LVFCCULD18; /**< VFCCU Local DID register 18, offset: 0x4 */ 75 __IO uint32_t LVFCCULD19; /**< VFCCU Local DID register 19, offset: 0x8 */ 76 __IO uint32_t LVFCCULD20; /**< VFCCU Local DID register 20, offset: 0xC */ 77 uint8_t RESERVED_0[4]; 78 __I uint32_t TARGTMS6; /**< NoC Target NIU Timeout Status, offset: 0x14 */ 79 __IO uint32_t TARGTMC6; /**< NoC Target NIU Timeout Control, offset: 0x18 */ 80 uint8_t RESERVED_1[28]; 81 __IO uint32_t XPAR5; /**< Interface parity control and status register, offset: 0x38 */ 82 } GPR6_Type, *GPR6_MemMapPtr; 83 84 /** Number of instances of the GPR6 module. */ 85 #define GPR6_INSTANCE_COUNT (1u) 86 87 /* GPR6 - Peripheral instance base addresses */ 88 /** Peripheral GPR6 base address */ 89 #define IP_GPR6_BASE (0x44060000u) 90 /** Peripheral GPR6 base pointer */ 91 #define IP_GPR6 ((GPR6_Type *)IP_GPR6_BASE) 92 /** Array initializer of GPR6 peripheral base addresses */ 93 #define IP_GPR6_BASE_ADDRS { IP_GPR6_BASE } 94 /** Array initializer of GPR6 peripheral base pointers */ 95 #define IP_GPR6_BASE_PTRS { IP_GPR6 } 96 97 /* ---------------------------------------------------------------------------- 98 -- GPR6 Register Masks 99 ---------------------------------------------------------------------------- */ 100 101 /*! 102 * @addtogroup GPR6_Register_Masks GPR6 Register Masks 103 * @{ 104 */ 105 106 /*! @name LVFCCUGD6 - VFCCU Global DID register 6 */ 107 /*! @{ */ 108 109 #define GPR6_LVFCCUGD6_FHID_MASK (0xFU) 110 #define GPR6_LVFCCUGD6_FHID_SHIFT (0U) 111 #define GPR6_LVFCCUGD6_FHID_WIDTH (4U) 112 #define GPR6_LVFCCUGD6_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR6_LVFCCUGD6_FHID_SHIFT)) & GPR6_LVFCCUGD6_FHID_MASK) 113 /*! @} */ 114 115 /*! @name LVFCCULD18 - VFCCU Local DID register 18 */ 116 /*! @{ */ 117 118 #define GPR6_LVFCCULD18_FHID_MASK (0xFFFFFFFFU) 119 #define GPR6_LVFCCULD18_FHID_SHIFT (0U) 120 #define GPR6_LVFCCULD18_FHID_WIDTH (32U) 121 #define GPR6_LVFCCULD18_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR6_LVFCCULD18_FHID_SHIFT)) & GPR6_LVFCCULD18_FHID_MASK) 122 /*! @} */ 123 124 /*! @name LVFCCULD19 - VFCCU Local DID register 19 */ 125 /*! @{ */ 126 127 #define GPR6_LVFCCULD19_FHID_MASK (0xFFFFFFFFU) 128 #define GPR6_LVFCCULD19_FHID_SHIFT (0U) 129 #define GPR6_LVFCCULD19_FHID_WIDTH (32U) 130 #define GPR6_LVFCCULD19_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR6_LVFCCULD19_FHID_SHIFT)) & GPR6_LVFCCULD19_FHID_MASK) 131 /*! @} */ 132 133 /*! @name LVFCCULD20 - VFCCU Local DID register 20 */ 134 /*! @{ */ 135 136 #define GPR6_LVFCCULD20_FHID_MASK (0xFFFFFFFFU) 137 #define GPR6_LVFCCULD20_FHID_SHIFT (0U) 138 #define GPR6_LVFCCULD20_FHID_WIDTH (32U) 139 #define GPR6_LVFCCULD20_FHID(x) (((uint32_t)(((uint32_t)(x)) << GPR6_LVFCCULD20_FHID_SHIFT)) & GPR6_LVFCCULD20_FHID_MASK) 140 /*! @} */ 141 142 /*! @name TARGTMS6 - NoC Target NIU Timeout Status */ 143 /*! @{ */ 144 145 #define GPR6_TARGTMS6_STAT_MASK (0xFFFFFFFFU) 146 #define GPR6_TARGTMS6_STAT_SHIFT (0U) 147 #define GPR6_TARGTMS6_STAT_WIDTH (32U) 148 #define GPR6_TARGTMS6_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPR6_TARGTMS6_STAT_SHIFT)) & GPR6_TARGTMS6_STAT_MASK) 149 /*! @} */ 150 151 /*! @name TARGTMC6 - NoC Target NIU Timeout Control */ 152 /*! @{ */ 153 154 #define GPR6_TARGTMC6_EN_MASK (0xFFFFFFFFU) 155 #define GPR6_TARGTMC6_EN_SHIFT (0U) 156 #define GPR6_TARGTMC6_EN_WIDTH (32U) 157 #define GPR6_TARGTMC6_EN(x) (((uint32_t)(((uint32_t)(x)) << GPR6_TARGTMC6_EN_SHIFT)) & GPR6_TARGTMC6_EN_MASK) 158 /*! @} */ 159 160 /*! @name XPAR5 - Interface parity control and status register */ 161 /*! @{ */ 162 163 #define GPR6_XPAR5_DIS_MASK (0x1U) 164 #define GPR6_XPAR5_DIS_SHIFT (0U) 165 #define GPR6_XPAR5_DIS_WIDTH (1U) 166 #define GPR6_XPAR5_DIS(x) (((uint32_t)(((uint32_t)(x)) << GPR6_XPAR5_DIS_SHIFT)) & GPR6_XPAR5_DIS_MASK) 167 168 #define GPR6_XPAR5_STAT_MASK (0x100U) 169 #define GPR6_XPAR5_STAT_SHIFT (8U) 170 #define GPR6_XPAR5_STAT_WIDTH (1U) 171 #define GPR6_XPAR5_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPR6_XPAR5_STAT_SHIFT)) & GPR6_XPAR5_STAT_MASK) 172 /*! @} */ 173 174 /*! 175 * @} 176 */ /* end of group GPR6_Register_Masks */ 177 178 /*! 179 * @} 180 */ /* end of group GPR6_Peripheral_Access_Layer */ 181 182 #endif /* #if !defined(S32Z2_GPR6_H_) */ 183
