1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_ERM_GTM.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_ERM_GTM 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_ERM_GTM_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_ERM_GTM_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- ERM_GTM Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup ERM_GTM_Peripheral_Access_Layer ERM_GTM Peripheral Access Layer 68 * @{ 69 */ 70 71 /** ERM_GTM - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t CR0; /**< ERM Configuration Register 0, offset: 0x0 */ 74 __IO uint32_t CR1; /**< ERM Configuration Register 1, offset: 0x4 */ 75 uint8_t RESERVED_0[8]; 76 __IO uint32_t SR0; /**< ERM Status Register 0, offset: 0x10 */ 77 __IO uint32_t SR1; /**< ERM Status Register 1, offset: 0x14 */ 78 uint8_t RESERVED_1[232]; 79 __I uint32_t EAR0; /**< ERM Memory 0 Error Address Register, offset: 0x100 */ 80 __I uint32_t SYN0; /**< ERM Memory 0 Syndrome Register, offset: 0x104 */ 81 __IO uint32_t CORR_ERR_CNT0; /**< ERM Memory 0 Correctable Error Count Register, offset: 0x108 */ 82 uint8_t RESERVED_2[4]; 83 __I uint32_t EAR1; /**< ERM Memory 1 Error Address Register, offset: 0x110 */ 84 __I uint32_t SYN1; /**< ERM Memory 1 Syndrome Register, offset: 0x114 */ 85 __IO uint32_t CORR_ERR_CNT1; /**< ERM Memory 1 Correctable Error Count Register, offset: 0x118 */ 86 uint8_t RESERVED_3[4]; 87 __I uint32_t EAR2; /**< ERM Memory 2 Error Address Register, offset: 0x120 */ 88 __I uint32_t SYN2; /**< ERM Memory 2 Syndrome Register, offset: 0x124 */ 89 __IO uint32_t CORR_ERR_CNT2; /**< ERM Memory 2 Correctable Error Count Register, offset: 0x128 */ 90 uint8_t RESERVED_4[4]; 91 __I uint32_t EAR3; /**< ERM Memory 3 Error Address Register, offset: 0x130 */ 92 __I uint32_t SYN3; /**< ERM Memory 3 Syndrome Register, offset: 0x134 */ 93 __IO uint32_t CORR_ERR_CNT3; /**< ERM Memory 3 Correctable Error Count Register, offset: 0x138 */ 94 uint8_t RESERVED_5[4]; 95 __I uint32_t EAR4; /**< ERM Memory 4 Error Address Register, offset: 0x140 */ 96 __I uint32_t SYN4; /**< ERM Memory 4 Syndrome Register, offset: 0x144 */ 97 __IO uint32_t CORR_ERR_CNT4; /**< ERM Memory 4 Correctable Error Count Register, offset: 0x148 */ 98 uint8_t RESERVED_6[4]; 99 __I uint32_t EAR5; /**< ERM Memory 5 Error Address Register, offset: 0x150 */ 100 __I uint32_t SYN5; /**< ERM Memory 5 Syndrome Register, offset: 0x154 */ 101 __IO uint32_t CORR_ERR_CNT5; /**< ERM Memory 5 Correctable Error Count Register, offset: 0x158 */ 102 uint8_t RESERVED_7[4]; 103 __I uint32_t EAR6; /**< ERM Memory 6 Error Address Register, offset: 0x160 */ 104 __I uint32_t SYN6; /**< ERM Memory 6 Syndrome Register, offset: 0x164 */ 105 __IO uint32_t CORR_ERR_CNT6; /**< ERM Memory 6 Correctable Error Count Register, offset: 0x168 */ 106 uint8_t RESERVED_8[4]; 107 __I uint32_t EAR7; /**< ERM Memory 7 Error Address Register, offset: 0x170 */ 108 __I uint32_t SYN7; /**< ERM Memory 7 Syndrome Register, offset: 0x174 */ 109 __IO uint32_t CORR_ERR_CNT7; /**< ERM Memory 7 Correctable Error Count Register, offset: 0x178 */ 110 uint8_t RESERVED_9[4]; 111 __I uint32_t EAR8; /**< ERM Memory 8 Error Address Register, offset: 0x180 */ 112 __I uint32_t SYN8; /**< ERM Memory 8 Syndrome Register, offset: 0x184 */ 113 __IO uint32_t CORR_ERR_CNT8; /**< ERM Memory 8 Correctable Error Count Register, offset: 0x188 */ 114 uint8_t RESERVED_10[4]; 115 __I uint32_t EAR9; /**< ERM Memory 9 Error Address Register, offset: 0x190 */ 116 __I uint32_t SYN9; /**< ERM Memory 9 Syndrome Register, offset: 0x194 */ 117 __IO uint32_t CORR_ERR_CNT9; /**< ERM Memory 9 Correctable Error Count Register, offset: 0x198 */ 118 uint8_t RESERVED_11[4]; 119 __I uint32_t EAR10; /**< ERM Memory 10 Error Address Register, offset: 0x1A0 */ 120 __I uint32_t SYN10; /**< ERM Memory 10 Syndrome Register, offset: 0x1A4 */ 121 __IO uint32_t CORR_ERR_CNT10; /**< ERM Memory 10 Correctable Error Count Register, offset: 0x1A8 */ 122 uint8_t RESERVED_12[4]; 123 __I uint32_t EAR11; /**< ERM Memory 11 Error Address Register, offset: 0x1B0 */ 124 __I uint32_t SYN11; /**< ERM Memory 11 Syndrome Register, offset: 0x1B4 */ 125 __IO uint32_t CORR_ERR_CNT11; /**< ERM Memory 11 Correctable Error Count Register, offset: 0x1B8 */ 126 } ERM_GTM_Type, *ERM_GTM_MemMapPtr; 127 128 /** Number of instances of the ERM_GTM module. */ 129 #define ERM_GTM_INSTANCE_COUNT (1u) 130 131 /* ERM_GTM - Peripheral instance base addresses */ 132 /** Peripheral ERM_GTM base address */ 133 #define IP_ERM_GTM_BASE (0x40374000u) 134 /** Peripheral ERM_GTM base pointer */ 135 #define IP_ERM_GTM ((ERM_GTM_Type *)IP_ERM_GTM_BASE) 136 /** Array initializer of ERM_GTM peripheral base addresses */ 137 #define IP_ERM_GTM_BASE_ADDRS { IP_ERM_GTM_BASE } 138 /** Array initializer of ERM_GTM peripheral base pointers */ 139 #define IP_ERM_GTM_BASE_PTRS { IP_ERM_GTM } 140 141 /* ---------------------------------------------------------------------------- 142 -- ERM_GTM Register Masks 143 ---------------------------------------------------------------------------- */ 144 145 /*! 146 * @addtogroup ERM_GTM_Register_Masks ERM_GTM Register Masks 147 * @{ 148 */ 149 150 /*! @name CR0 - ERM Configuration Register 0 */ 151 /*! @{ */ 152 153 #define ERM_GTM_CR0_ENCIE7_MASK (0x4U) 154 #define ERM_GTM_CR0_ENCIE7_SHIFT (2U) 155 #define ERM_GTM_CR0_ENCIE7_WIDTH (1U) 156 #define ERM_GTM_CR0_ENCIE7(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR0_ENCIE7_SHIFT)) & ERM_GTM_CR0_ENCIE7_MASK) 157 158 #define ERM_GTM_CR0_ESCIE7_MASK (0x8U) 159 #define ERM_GTM_CR0_ESCIE7_SHIFT (3U) 160 #define ERM_GTM_CR0_ESCIE7_WIDTH (1U) 161 #define ERM_GTM_CR0_ESCIE7(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR0_ESCIE7_SHIFT)) & ERM_GTM_CR0_ESCIE7_MASK) 162 163 #define ERM_GTM_CR0_ENCIE6_MASK (0x40U) 164 #define ERM_GTM_CR0_ENCIE6_SHIFT (6U) 165 #define ERM_GTM_CR0_ENCIE6_WIDTH (1U) 166 #define ERM_GTM_CR0_ENCIE6(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR0_ENCIE6_SHIFT)) & ERM_GTM_CR0_ENCIE6_MASK) 167 168 #define ERM_GTM_CR0_ESCIE6_MASK (0x80U) 169 #define ERM_GTM_CR0_ESCIE6_SHIFT (7U) 170 #define ERM_GTM_CR0_ESCIE6_WIDTH (1U) 171 #define ERM_GTM_CR0_ESCIE6(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR0_ESCIE6_SHIFT)) & ERM_GTM_CR0_ESCIE6_MASK) 172 173 #define ERM_GTM_CR0_ENCIE5_MASK (0x400U) 174 #define ERM_GTM_CR0_ENCIE5_SHIFT (10U) 175 #define ERM_GTM_CR0_ENCIE5_WIDTH (1U) 176 #define ERM_GTM_CR0_ENCIE5(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR0_ENCIE5_SHIFT)) & ERM_GTM_CR0_ENCIE5_MASK) 177 178 #define ERM_GTM_CR0_ESCIE5_MASK (0x800U) 179 #define ERM_GTM_CR0_ESCIE5_SHIFT (11U) 180 #define ERM_GTM_CR0_ESCIE5_WIDTH (1U) 181 #define ERM_GTM_CR0_ESCIE5(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR0_ESCIE5_SHIFT)) & ERM_GTM_CR0_ESCIE5_MASK) 182 183 #define ERM_GTM_CR0_ENCIE4_MASK (0x4000U) 184 #define ERM_GTM_CR0_ENCIE4_SHIFT (14U) 185 #define ERM_GTM_CR0_ENCIE4_WIDTH (1U) 186 #define ERM_GTM_CR0_ENCIE4(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR0_ENCIE4_SHIFT)) & ERM_GTM_CR0_ENCIE4_MASK) 187 188 #define ERM_GTM_CR0_ESCIE4_MASK (0x8000U) 189 #define ERM_GTM_CR0_ESCIE4_SHIFT (15U) 190 #define ERM_GTM_CR0_ESCIE4_WIDTH (1U) 191 #define ERM_GTM_CR0_ESCIE4(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR0_ESCIE4_SHIFT)) & ERM_GTM_CR0_ESCIE4_MASK) 192 193 #define ERM_GTM_CR0_ENCIE3_MASK (0x40000U) 194 #define ERM_GTM_CR0_ENCIE3_SHIFT (18U) 195 #define ERM_GTM_CR0_ENCIE3_WIDTH (1U) 196 #define ERM_GTM_CR0_ENCIE3(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR0_ENCIE3_SHIFT)) & ERM_GTM_CR0_ENCIE3_MASK) 197 198 #define ERM_GTM_CR0_ESCIE3_MASK (0x80000U) 199 #define ERM_GTM_CR0_ESCIE3_SHIFT (19U) 200 #define ERM_GTM_CR0_ESCIE3_WIDTH (1U) 201 #define ERM_GTM_CR0_ESCIE3(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR0_ESCIE3_SHIFT)) & ERM_GTM_CR0_ESCIE3_MASK) 202 203 #define ERM_GTM_CR0_ENCIE2_MASK (0x400000U) 204 #define ERM_GTM_CR0_ENCIE2_SHIFT (22U) 205 #define ERM_GTM_CR0_ENCIE2_WIDTH (1U) 206 #define ERM_GTM_CR0_ENCIE2(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR0_ENCIE2_SHIFT)) & ERM_GTM_CR0_ENCIE2_MASK) 207 208 #define ERM_GTM_CR0_ESCIE2_MASK (0x800000U) 209 #define ERM_GTM_CR0_ESCIE2_SHIFT (23U) 210 #define ERM_GTM_CR0_ESCIE2_WIDTH (1U) 211 #define ERM_GTM_CR0_ESCIE2(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR0_ESCIE2_SHIFT)) & ERM_GTM_CR0_ESCIE2_MASK) 212 213 #define ERM_GTM_CR0_ENCIE1_MASK (0x4000000U) 214 #define ERM_GTM_CR0_ENCIE1_SHIFT (26U) 215 #define ERM_GTM_CR0_ENCIE1_WIDTH (1U) 216 #define ERM_GTM_CR0_ENCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR0_ENCIE1_SHIFT)) & ERM_GTM_CR0_ENCIE1_MASK) 217 218 #define ERM_GTM_CR0_ESCIE1_MASK (0x8000000U) 219 #define ERM_GTM_CR0_ESCIE1_SHIFT (27U) 220 #define ERM_GTM_CR0_ESCIE1_WIDTH (1U) 221 #define ERM_GTM_CR0_ESCIE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR0_ESCIE1_SHIFT)) & ERM_GTM_CR0_ESCIE1_MASK) 222 223 #define ERM_GTM_CR0_ENCIE0_MASK (0x40000000U) 224 #define ERM_GTM_CR0_ENCIE0_SHIFT (30U) 225 #define ERM_GTM_CR0_ENCIE0_WIDTH (1U) 226 #define ERM_GTM_CR0_ENCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR0_ENCIE0_SHIFT)) & ERM_GTM_CR0_ENCIE0_MASK) 227 228 #define ERM_GTM_CR0_ESCIE0_MASK (0x80000000U) 229 #define ERM_GTM_CR0_ESCIE0_SHIFT (31U) 230 #define ERM_GTM_CR0_ESCIE0_WIDTH (1U) 231 #define ERM_GTM_CR0_ESCIE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR0_ESCIE0_SHIFT)) & ERM_GTM_CR0_ESCIE0_MASK) 232 /*! @} */ 233 234 /*! @name CR1 - ERM Configuration Register 1 */ 235 /*! @{ */ 236 237 #define ERM_GTM_CR1_ENCIE11_MASK (0x40000U) 238 #define ERM_GTM_CR1_ENCIE11_SHIFT (18U) 239 #define ERM_GTM_CR1_ENCIE11_WIDTH (1U) 240 #define ERM_GTM_CR1_ENCIE11(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR1_ENCIE11_SHIFT)) & ERM_GTM_CR1_ENCIE11_MASK) 241 242 #define ERM_GTM_CR1_ESCIE11_MASK (0x80000U) 243 #define ERM_GTM_CR1_ESCIE11_SHIFT (19U) 244 #define ERM_GTM_CR1_ESCIE11_WIDTH (1U) 245 #define ERM_GTM_CR1_ESCIE11(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR1_ESCIE11_SHIFT)) & ERM_GTM_CR1_ESCIE11_MASK) 246 247 #define ERM_GTM_CR1_ENCIE10_MASK (0x400000U) 248 #define ERM_GTM_CR1_ENCIE10_SHIFT (22U) 249 #define ERM_GTM_CR1_ENCIE10_WIDTH (1U) 250 #define ERM_GTM_CR1_ENCIE10(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR1_ENCIE10_SHIFT)) & ERM_GTM_CR1_ENCIE10_MASK) 251 252 #define ERM_GTM_CR1_ESCIE10_MASK (0x800000U) 253 #define ERM_GTM_CR1_ESCIE10_SHIFT (23U) 254 #define ERM_GTM_CR1_ESCIE10_WIDTH (1U) 255 #define ERM_GTM_CR1_ESCIE10(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR1_ESCIE10_SHIFT)) & ERM_GTM_CR1_ESCIE10_MASK) 256 257 #define ERM_GTM_CR1_ENCIE9_MASK (0x4000000U) 258 #define ERM_GTM_CR1_ENCIE9_SHIFT (26U) 259 #define ERM_GTM_CR1_ENCIE9_WIDTH (1U) 260 #define ERM_GTM_CR1_ENCIE9(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR1_ENCIE9_SHIFT)) & ERM_GTM_CR1_ENCIE9_MASK) 261 262 #define ERM_GTM_CR1_ESCIE9_MASK (0x8000000U) 263 #define ERM_GTM_CR1_ESCIE9_SHIFT (27U) 264 #define ERM_GTM_CR1_ESCIE9_WIDTH (1U) 265 #define ERM_GTM_CR1_ESCIE9(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR1_ESCIE9_SHIFT)) & ERM_GTM_CR1_ESCIE9_MASK) 266 267 #define ERM_GTM_CR1_ENCIE8_MASK (0x40000000U) 268 #define ERM_GTM_CR1_ENCIE8_SHIFT (30U) 269 #define ERM_GTM_CR1_ENCIE8_WIDTH (1U) 270 #define ERM_GTM_CR1_ENCIE8(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR1_ENCIE8_SHIFT)) & ERM_GTM_CR1_ENCIE8_MASK) 271 272 #define ERM_GTM_CR1_ESCIE8_MASK (0x80000000U) 273 #define ERM_GTM_CR1_ESCIE8_SHIFT (31U) 274 #define ERM_GTM_CR1_ESCIE8_WIDTH (1U) 275 #define ERM_GTM_CR1_ESCIE8(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CR1_ESCIE8_SHIFT)) & ERM_GTM_CR1_ESCIE8_MASK) 276 /*! @} */ 277 278 /*! @name SR0 - ERM Status Register 0 */ 279 /*! @{ */ 280 281 #define ERM_GTM_SR0_NCE7_MASK (0x4U) 282 #define ERM_GTM_SR0_NCE7_SHIFT (2U) 283 #define ERM_GTM_SR0_NCE7_WIDTH (1U) 284 #define ERM_GTM_SR0_NCE7(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR0_NCE7_SHIFT)) & ERM_GTM_SR0_NCE7_MASK) 285 286 #define ERM_GTM_SR0_SBC7_MASK (0x8U) 287 #define ERM_GTM_SR0_SBC7_SHIFT (3U) 288 #define ERM_GTM_SR0_SBC7_WIDTH (1U) 289 #define ERM_GTM_SR0_SBC7(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR0_SBC7_SHIFT)) & ERM_GTM_SR0_SBC7_MASK) 290 291 #define ERM_GTM_SR0_NCE6_MASK (0x40U) 292 #define ERM_GTM_SR0_NCE6_SHIFT (6U) 293 #define ERM_GTM_SR0_NCE6_WIDTH (1U) 294 #define ERM_GTM_SR0_NCE6(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR0_NCE6_SHIFT)) & ERM_GTM_SR0_NCE6_MASK) 295 296 #define ERM_GTM_SR0_SBC6_MASK (0x80U) 297 #define ERM_GTM_SR0_SBC6_SHIFT (7U) 298 #define ERM_GTM_SR0_SBC6_WIDTH (1U) 299 #define ERM_GTM_SR0_SBC6(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR0_SBC6_SHIFT)) & ERM_GTM_SR0_SBC6_MASK) 300 301 #define ERM_GTM_SR0_NCE5_MASK (0x400U) 302 #define ERM_GTM_SR0_NCE5_SHIFT (10U) 303 #define ERM_GTM_SR0_NCE5_WIDTH (1U) 304 #define ERM_GTM_SR0_NCE5(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR0_NCE5_SHIFT)) & ERM_GTM_SR0_NCE5_MASK) 305 306 #define ERM_GTM_SR0_SBC5_MASK (0x800U) 307 #define ERM_GTM_SR0_SBC5_SHIFT (11U) 308 #define ERM_GTM_SR0_SBC5_WIDTH (1U) 309 #define ERM_GTM_SR0_SBC5(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR0_SBC5_SHIFT)) & ERM_GTM_SR0_SBC5_MASK) 310 311 #define ERM_GTM_SR0_NCE4_MASK (0x4000U) 312 #define ERM_GTM_SR0_NCE4_SHIFT (14U) 313 #define ERM_GTM_SR0_NCE4_WIDTH (1U) 314 #define ERM_GTM_SR0_NCE4(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR0_NCE4_SHIFT)) & ERM_GTM_SR0_NCE4_MASK) 315 316 #define ERM_GTM_SR0_SBC4_MASK (0x8000U) 317 #define ERM_GTM_SR0_SBC4_SHIFT (15U) 318 #define ERM_GTM_SR0_SBC4_WIDTH (1U) 319 #define ERM_GTM_SR0_SBC4(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR0_SBC4_SHIFT)) & ERM_GTM_SR0_SBC4_MASK) 320 321 #define ERM_GTM_SR0_NCE3_MASK (0x40000U) 322 #define ERM_GTM_SR0_NCE3_SHIFT (18U) 323 #define ERM_GTM_SR0_NCE3_WIDTH (1U) 324 #define ERM_GTM_SR0_NCE3(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR0_NCE3_SHIFT)) & ERM_GTM_SR0_NCE3_MASK) 325 326 #define ERM_GTM_SR0_SBC3_MASK (0x80000U) 327 #define ERM_GTM_SR0_SBC3_SHIFT (19U) 328 #define ERM_GTM_SR0_SBC3_WIDTH (1U) 329 #define ERM_GTM_SR0_SBC3(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR0_SBC3_SHIFT)) & ERM_GTM_SR0_SBC3_MASK) 330 331 #define ERM_GTM_SR0_NCE2_MASK (0x400000U) 332 #define ERM_GTM_SR0_NCE2_SHIFT (22U) 333 #define ERM_GTM_SR0_NCE2_WIDTH (1U) 334 #define ERM_GTM_SR0_NCE2(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR0_NCE2_SHIFT)) & ERM_GTM_SR0_NCE2_MASK) 335 336 #define ERM_GTM_SR0_SBC2_MASK (0x800000U) 337 #define ERM_GTM_SR0_SBC2_SHIFT (23U) 338 #define ERM_GTM_SR0_SBC2_WIDTH (1U) 339 #define ERM_GTM_SR0_SBC2(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR0_SBC2_SHIFT)) & ERM_GTM_SR0_SBC2_MASK) 340 341 #define ERM_GTM_SR0_NCE1_MASK (0x4000000U) 342 #define ERM_GTM_SR0_NCE1_SHIFT (26U) 343 #define ERM_GTM_SR0_NCE1_WIDTH (1U) 344 #define ERM_GTM_SR0_NCE1(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR0_NCE1_SHIFT)) & ERM_GTM_SR0_NCE1_MASK) 345 346 #define ERM_GTM_SR0_SBC1_MASK (0x8000000U) 347 #define ERM_GTM_SR0_SBC1_SHIFT (27U) 348 #define ERM_GTM_SR0_SBC1_WIDTH (1U) 349 #define ERM_GTM_SR0_SBC1(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR0_SBC1_SHIFT)) & ERM_GTM_SR0_SBC1_MASK) 350 351 #define ERM_GTM_SR0_NCE0_MASK (0x40000000U) 352 #define ERM_GTM_SR0_NCE0_SHIFT (30U) 353 #define ERM_GTM_SR0_NCE0_WIDTH (1U) 354 #define ERM_GTM_SR0_NCE0(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR0_NCE0_SHIFT)) & ERM_GTM_SR0_NCE0_MASK) 355 356 #define ERM_GTM_SR0_SBC0_MASK (0x80000000U) 357 #define ERM_GTM_SR0_SBC0_SHIFT (31U) 358 #define ERM_GTM_SR0_SBC0_WIDTH (1U) 359 #define ERM_GTM_SR0_SBC0(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR0_SBC0_SHIFT)) & ERM_GTM_SR0_SBC0_MASK) 360 /*! @} */ 361 362 /*! @name SR1 - ERM Status Register 1 */ 363 /*! @{ */ 364 365 #define ERM_GTM_SR1_NCE11_MASK (0x40000U) 366 #define ERM_GTM_SR1_NCE11_SHIFT (18U) 367 #define ERM_GTM_SR1_NCE11_WIDTH (1U) 368 #define ERM_GTM_SR1_NCE11(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR1_NCE11_SHIFT)) & ERM_GTM_SR1_NCE11_MASK) 369 370 #define ERM_GTM_SR1_SBC11_MASK (0x80000U) 371 #define ERM_GTM_SR1_SBC11_SHIFT (19U) 372 #define ERM_GTM_SR1_SBC11_WIDTH (1U) 373 #define ERM_GTM_SR1_SBC11(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR1_SBC11_SHIFT)) & ERM_GTM_SR1_SBC11_MASK) 374 375 #define ERM_GTM_SR1_NCE10_MASK (0x400000U) 376 #define ERM_GTM_SR1_NCE10_SHIFT (22U) 377 #define ERM_GTM_SR1_NCE10_WIDTH (1U) 378 #define ERM_GTM_SR1_NCE10(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR1_NCE10_SHIFT)) & ERM_GTM_SR1_NCE10_MASK) 379 380 #define ERM_GTM_SR1_SBC10_MASK (0x800000U) 381 #define ERM_GTM_SR1_SBC10_SHIFT (23U) 382 #define ERM_GTM_SR1_SBC10_WIDTH (1U) 383 #define ERM_GTM_SR1_SBC10(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR1_SBC10_SHIFT)) & ERM_GTM_SR1_SBC10_MASK) 384 385 #define ERM_GTM_SR1_NCE9_MASK (0x4000000U) 386 #define ERM_GTM_SR1_NCE9_SHIFT (26U) 387 #define ERM_GTM_SR1_NCE9_WIDTH (1U) 388 #define ERM_GTM_SR1_NCE9(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR1_NCE9_SHIFT)) & ERM_GTM_SR1_NCE9_MASK) 389 390 #define ERM_GTM_SR1_SBC9_MASK (0x8000000U) 391 #define ERM_GTM_SR1_SBC9_SHIFT (27U) 392 #define ERM_GTM_SR1_SBC9_WIDTH (1U) 393 #define ERM_GTM_SR1_SBC9(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR1_SBC9_SHIFT)) & ERM_GTM_SR1_SBC9_MASK) 394 395 #define ERM_GTM_SR1_NCE8_MASK (0x40000000U) 396 #define ERM_GTM_SR1_NCE8_SHIFT (30U) 397 #define ERM_GTM_SR1_NCE8_WIDTH (1U) 398 #define ERM_GTM_SR1_NCE8(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR1_NCE8_SHIFT)) & ERM_GTM_SR1_NCE8_MASK) 399 400 #define ERM_GTM_SR1_SBC8_MASK (0x80000000U) 401 #define ERM_GTM_SR1_SBC8_SHIFT (31U) 402 #define ERM_GTM_SR1_SBC8_WIDTH (1U) 403 #define ERM_GTM_SR1_SBC8(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SR1_SBC8_SHIFT)) & ERM_GTM_SR1_SBC8_MASK) 404 /*! @} */ 405 406 /*! @name EAR0 - ERM Memory 0 Error Address Register */ 407 /*! @{ */ 408 409 #define ERM_GTM_EAR0_EAR_MASK (0xFFFFFFFFU) 410 #define ERM_GTM_EAR0_EAR_SHIFT (0U) 411 #define ERM_GTM_EAR0_EAR_WIDTH (32U) 412 #define ERM_GTM_EAR0_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_EAR0_EAR_SHIFT)) & ERM_GTM_EAR0_EAR_MASK) 413 /*! @} */ 414 415 /*! @name SYN0 - ERM Memory 0 Syndrome Register */ 416 /*! @{ */ 417 418 #define ERM_GTM_SYN0_SYNDROME_MASK (0xFF000000U) 419 #define ERM_GTM_SYN0_SYNDROME_SHIFT (24U) 420 #define ERM_GTM_SYN0_SYNDROME_WIDTH (8U) 421 #define ERM_GTM_SYN0_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SYN0_SYNDROME_SHIFT)) & ERM_GTM_SYN0_SYNDROME_MASK) 422 /*! @} */ 423 424 /*! @name CORR_ERR_CNT0 - ERM Memory 0 Correctable Error Count Register */ 425 /*! @{ */ 426 427 #define ERM_GTM_CORR_ERR_CNT0_COUNT_MASK (0xFFU) 428 #define ERM_GTM_CORR_ERR_CNT0_COUNT_SHIFT (0U) 429 #define ERM_GTM_CORR_ERR_CNT0_COUNT_WIDTH (8U) 430 #define ERM_GTM_CORR_ERR_CNT0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CORR_ERR_CNT0_COUNT_SHIFT)) & ERM_GTM_CORR_ERR_CNT0_COUNT_MASK) 431 /*! @} */ 432 433 /*! @name EAR1 - ERM Memory 1 Error Address Register */ 434 /*! @{ */ 435 436 #define ERM_GTM_EAR1_EAR_MASK (0xFFFFFFFFU) 437 #define ERM_GTM_EAR1_EAR_SHIFT (0U) 438 #define ERM_GTM_EAR1_EAR_WIDTH (32U) 439 #define ERM_GTM_EAR1_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_EAR1_EAR_SHIFT)) & ERM_GTM_EAR1_EAR_MASK) 440 /*! @} */ 441 442 /*! @name SYN1 - ERM Memory 1 Syndrome Register */ 443 /*! @{ */ 444 445 #define ERM_GTM_SYN1_SYNDROME_MASK (0xFF000000U) 446 #define ERM_GTM_SYN1_SYNDROME_SHIFT (24U) 447 #define ERM_GTM_SYN1_SYNDROME_WIDTH (8U) 448 #define ERM_GTM_SYN1_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SYN1_SYNDROME_SHIFT)) & ERM_GTM_SYN1_SYNDROME_MASK) 449 /*! @} */ 450 451 /*! @name CORR_ERR_CNT1 - ERM Memory 1 Correctable Error Count Register */ 452 /*! @{ */ 453 454 #define ERM_GTM_CORR_ERR_CNT1_COUNT_MASK (0xFFU) 455 #define ERM_GTM_CORR_ERR_CNT1_COUNT_SHIFT (0U) 456 #define ERM_GTM_CORR_ERR_CNT1_COUNT_WIDTH (8U) 457 #define ERM_GTM_CORR_ERR_CNT1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CORR_ERR_CNT1_COUNT_SHIFT)) & ERM_GTM_CORR_ERR_CNT1_COUNT_MASK) 458 /*! @} */ 459 460 /*! @name EAR2 - ERM Memory 2 Error Address Register */ 461 /*! @{ */ 462 463 #define ERM_GTM_EAR2_EAR_MASK (0xFFFFFFFFU) 464 #define ERM_GTM_EAR2_EAR_SHIFT (0U) 465 #define ERM_GTM_EAR2_EAR_WIDTH (32U) 466 #define ERM_GTM_EAR2_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_EAR2_EAR_SHIFT)) & ERM_GTM_EAR2_EAR_MASK) 467 /*! @} */ 468 469 /*! @name SYN2 - ERM Memory 2 Syndrome Register */ 470 /*! @{ */ 471 472 #define ERM_GTM_SYN2_SYNDROME_MASK (0xFF000000U) 473 #define ERM_GTM_SYN2_SYNDROME_SHIFT (24U) 474 #define ERM_GTM_SYN2_SYNDROME_WIDTH (8U) 475 #define ERM_GTM_SYN2_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SYN2_SYNDROME_SHIFT)) & ERM_GTM_SYN2_SYNDROME_MASK) 476 /*! @} */ 477 478 /*! @name CORR_ERR_CNT2 - ERM Memory 2 Correctable Error Count Register */ 479 /*! @{ */ 480 481 #define ERM_GTM_CORR_ERR_CNT2_COUNT_MASK (0xFFU) 482 #define ERM_GTM_CORR_ERR_CNT2_COUNT_SHIFT (0U) 483 #define ERM_GTM_CORR_ERR_CNT2_COUNT_WIDTH (8U) 484 #define ERM_GTM_CORR_ERR_CNT2_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CORR_ERR_CNT2_COUNT_SHIFT)) & ERM_GTM_CORR_ERR_CNT2_COUNT_MASK) 485 /*! @} */ 486 487 /*! @name EAR3 - ERM Memory 3 Error Address Register */ 488 /*! @{ */ 489 490 #define ERM_GTM_EAR3_EAR_MASK (0xFFFFFFFFU) 491 #define ERM_GTM_EAR3_EAR_SHIFT (0U) 492 #define ERM_GTM_EAR3_EAR_WIDTH (32U) 493 #define ERM_GTM_EAR3_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_EAR3_EAR_SHIFT)) & ERM_GTM_EAR3_EAR_MASK) 494 /*! @} */ 495 496 /*! @name SYN3 - ERM Memory 3 Syndrome Register */ 497 /*! @{ */ 498 499 #define ERM_GTM_SYN3_SYNDROME_MASK (0xFF000000U) 500 #define ERM_GTM_SYN3_SYNDROME_SHIFT (24U) 501 #define ERM_GTM_SYN3_SYNDROME_WIDTH (8U) 502 #define ERM_GTM_SYN3_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SYN3_SYNDROME_SHIFT)) & ERM_GTM_SYN3_SYNDROME_MASK) 503 /*! @} */ 504 505 /*! @name CORR_ERR_CNT3 - ERM Memory 3 Correctable Error Count Register */ 506 /*! @{ */ 507 508 #define ERM_GTM_CORR_ERR_CNT3_COUNT_MASK (0xFFU) 509 #define ERM_GTM_CORR_ERR_CNT3_COUNT_SHIFT (0U) 510 #define ERM_GTM_CORR_ERR_CNT3_COUNT_WIDTH (8U) 511 #define ERM_GTM_CORR_ERR_CNT3_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CORR_ERR_CNT3_COUNT_SHIFT)) & ERM_GTM_CORR_ERR_CNT3_COUNT_MASK) 512 /*! @} */ 513 514 /*! @name EAR4 - ERM Memory 4 Error Address Register */ 515 /*! @{ */ 516 517 #define ERM_GTM_EAR4_EAR_MASK (0xFFFFFFFFU) 518 #define ERM_GTM_EAR4_EAR_SHIFT (0U) 519 #define ERM_GTM_EAR4_EAR_WIDTH (32U) 520 #define ERM_GTM_EAR4_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_EAR4_EAR_SHIFT)) & ERM_GTM_EAR4_EAR_MASK) 521 /*! @} */ 522 523 /*! @name SYN4 - ERM Memory 4 Syndrome Register */ 524 /*! @{ */ 525 526 #define ERM_GTM_SYN4_SYNDROME_MASK (0xFF000000U) 527 #define ERM_GTM_SYN4_SYNDROME_SHIFT (24U) 528 #define ERM_GTM_SYN4_SYNDROME_WIDTH (8U) 529 #define ERM_GTM_SYN4_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SYN4_SYNDROME_SHIFT)) & ERM_GTM_SYN4_SYNDROME_MASK) 530 /*! @} */ 531 532 /*! @name CORR_ERR_CNT4 - ERM Memory 4 Correctable Error Count Register */ 533 /*! @{ */ 534 535 #define ERM_GTM_CORR_ERR_CNT4_COUNT_MASK (0xFFU) 536 #define ERM_GTM_CORR_ERR_CNT4_COUNT_SHIFT (0U) 537 #define ERM_GTM_CORR_ERR_CNT4_COUNT_WIDTH (8U) 538 #define ERM_GTM_CORR_ERR_CNT4_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CORR_ERR_CNT4_COUNT_SHIFT)) & ERM_GTM_CORR_ERR_CNT4_COUNT_MASK) 539 /*! @} */ 540 541 /*! @name EAR5 - ERM Memory 5 Error Address Register */ 542 /*! @{ */ 543 544 #define ERM_GTM_EAR5_EAR_MASK (0xFFFFFFFFU) 545 #define ERM_GTM_EAR5_EAR_SHIFT (0U) 546 #define ERM_GTM_EAR5_EAR_WIDTH (32U) 547 #define ERM_GTM_EAR5_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_EAR5_EAR_SHIFT)) & ERM_GTM_EAR5_EAR_MASK) 548 /*! @} */ 549 550 /*! @name SYN5 - ERM Memory 5 Syndrome Register */ 551 /*! @{ */ 552 553 #define ERM_GTM_SYN5_SYNDROME_MASK (0xFF000000U) 554 #define ERM_GTM_SYN5_SYNDROME_SHIFT (24U) 555 #define ERM_GTM_SYN5_SYNDROME_WIDTH (8U) 556 #define ERM_GTM_SYN5_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SYN5_SYNDROME_SHIFT)) & ERM_GTM_SYN5_SYNDROME_MASK) 557 /*! @} */ 558 559 /*! @name CORR_ERR_CNT5 - ERM Memory 5 Correctable Error Count Register */ 560 /*! @{ */ 561 562 #define ERM_GTM_CORR_ERR_CNT5_COUNT_MASK (0xFFU) 563 #define ERM_GTM_CORR_ERR_CNT5_COUNT_SHIFT (0U) 564 #define ERM_GTM_CORR_ERR_CNT5_COUNT_WIDTH (8U) 565 #define ERM_GTM_CORR_ERR_CNT5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CORR_ERR_CNT5_COUNT_SHIFT)) & ERM_GTM_CORR_ERR_CNT5_COUNT_MASK) 566 /*! @} */ 567 568 /*! @name EAR6 - ERM Memory 6 Error Address Register */ 569 /*! @{ */ 570 571 #define ERM_GTM_EAR6_EAR_MASK (0xFFFFFFFFU) 572 #define ERM_GTM_EAR6_EAR_SHIFT (0U) 573 #define ERM_GTM_EAR6_EAR_WIDTH (32U) 574 #define ERM_GTM_EAR6_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_EAR6_EAR_SHIFT)) & ERM_GTM_EAR6_EAR_MASK) 575 /*! @} */ 576 577 /*! @name SYN6 - ERM Memory 6 Syndrome Register */ 578 /*! @{ */ 579 580 #define ERM_GTM_SYN6_SYNDROME_MASK (0xFF000000U) 581 #define ERM_GTM_SYN6_SYNDROME_SHIFT (24U) 582 #define ERM_GTM_SYN6_SYNDROME_WIDTH (8U) 583 #define ERM_GTM_SYN6_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SYN6_SYNDROME_SHIFT)) & ERM_GTM_SYN6_SYNDROME_MASK) 584 /*! @} */ 585 586 /*! @name CORR_ERR_CNT6 - ERM Memory 6 Correctable Error Count Register */ 587 /*! @{ */ 588 589 #define ERM_GTM_CORR_ERR_CNT6_COUNT_MASK (0xFFU) 590 #define ERM_GTM_CORR_ERR_CNT6_COUNT_SHIFT (0U) 591 #define ERM_GTM_CORR_ERR_CNT6_COUNT_WIDTH (8U) 592 #define ERM_GTM_CORR_ERR_CNT6_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CORR_ERR_CNT6_COUNT_SHIFT)) & ERM_GTM_CORR_ERR_CNT6_COUNT_MASK) 593 /*! @} */ 594 595 /*! @name EAR7 - ERM Memory 7 Error Address Register */ 596 /*! @{ */ 597 598 #define ERM_GTM_EAR7_EAR_MASK (0xFFFFFFFFU) 599 #define ERM_GTM_EAR7_EAR_SHIFT (0U) 600 #define ERM_GTM_EAR7_EAR_WIDTH (32U) 601 #define ERM_GTM_EAR7_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_EAR7_EAR_SHIFT)) & ERM_GTM_EAR7_EAR_MASK) 602 /*! @} */ 603 604 /*! @name SYN7 - ERM Memory 7 Syndrome Register */ 605 /*! @{ */ 606 607 #define ERM_GTM_SYN7_SYNDROME_MASK (0xFF000000U) 608 #define ERM_GTM_SYN7_SYNDROME_SHIFT (24U) 609 #define ERM_GTM_SYN7_SYNDROME_WIDTH (8U) 610 #define ERM_GTM_SYN7_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SYN7_SYNDROME_SHIFT)) & ERM_GTM_SYN7_SYNDROME_MASK) 611 /*! @} */ 612 613 /*! @name CORR_ERR_CNT7 - ERM Memory 7 Correctable Error Count Register */ 614 /*! @{ */ 615 616 #define ERM_GTM_CORR_ERR_CNT7_COUNT_MASK (0xFFU) 617 #define ERM_GTM_CORR_ERR_CNT7_COUNT_SHIFT (0U) 618 #define ERM_GTM_CORR_ERR_CNT7_COUNT_WIDTH (8U) 619 #define ERM_GTM_CORR_ERR_CNT7_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CORR_ERR_CNT7_COUNT_SHIFT)) & ERM_GTM_CORR_ERR_CNT7_COUNT_MASK) 620 /*! @} */ 621 622 /*! @name EAR8 - ERM Memory 8 Error Address Register */ 623 /*! @{ */ 624 625 #define ERM_GTM_EAR8_EAR_MASK (0xFFFFFFFFU) 626 #define ERM_GTM_EAR8_EAR_SHIFT (0U) 627 #define ERM_GTM_EAR8_EAR_WIDTH (32U) 628 #define ERM_GTM_EAR8_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_EAR8_EAR_SHIFT)) & ERM_GTM_EAR8_EAR_MASK) 629 /*! @} */ 630 631 /*! @name SYN8 - ERM Memory 8 Syndrome Register */ 632 /*! @{ */ 633 634 #define ERM_GTM_SYN8_SYNDROME_MASK (0xFF000000U) 635 #define ERM_GTM_SYN8_SYNDROME_SHIFT (24U) 636 #define ERM_GTM_SYN8_SYNDROME_WIDTH (8U) 637 #define ERM_GTM_SYN8_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SYN8_SYNDROME_SHIFT)) & ERM_GTM_SYN8_SYNDROME_MASK) 638 /*! @} */ 639 640 /*! @name CORR_ERR_CNT8 - ERM Memory 8 Correctable Error Count Register */ 641 /*! @{ */ 642 643 #define ERM_GTM_CORR_ERR_CNT8_COUNT_MASK (0xFFU) 644 #define ERM_GTM_CORR_ERR_CNT8_COUNT_SHIFT (0U) 645 #define ERM_GTM_CORR_ERR_CNT8_COUNT_WIDTH (8U) 646 #define ERM_GTM_CORR_ERR_CNT8_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CORR_ERR_CNT8_COUNT_SHIFT)) & ERM_GTM_CORR_ERR_CNT8_COUNT_MASK) 647 /*! @} */ 648 649 /*! @name EAR9 - ERM Memory 9 Error Address Register */ 650 /*! @{ */ 651 652 #define ERM_GTM_EAR9_EAR_MASK (0xFFFFFFFFU) 653 #define ERM_GTM_EAR9_EAR_SHIFT (0U) 654 #define ERM_GTM_EAR9_EAR_WIDTH (32U) 655 #define ERM_GTM_EAR9_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_EAR9_EAR_SHIFT)) & ERM_GTM_EAR9_EAR_MASK) 656 /*! @} */ 657 658 /*! @name SYN9 - ERM Memory 9 Syndrome Register */ 659 /*! @{ */ 660 661 #define ERM_GTM_SYN9_SYNDROME_MASK (0xFF000000U) 662 #define ERM_GTM_SYN9_SYNDROME_SHIFT (24U) 663 #define ERM_GTM_SYN9_SYNDROME_WIDTH (8U) 664 #define ERM_GTM_SYN9_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SYN9_SYNDROME_SHIFT)) & ERM_GTM_SYN9_SYNDROME_MASK) 665 /*! @} */ 666 667 /*! @name CORR_ERR_CNT9 - ERM Memory 9 Correctable Error Count Register */ 668 /*! @{ */ 669 670 #define ERM_GTM_CORR_ERR_CNT9_COUNT_MASK (0xFFU) 671 #define ERM_GTM_CORR_ERR_CNT9_COUNT_SHIFT (0U) 672 #define ERM_GTM_CORR_ERR_CNT9_COUNT_WIDTH (8U) 673 #define ERM_GTM_CORR_ERR_CNT9_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CORR_ERR_CNT9_COUNT_SHIFT)) & ERM_GTM_CORR_ERR_CNT9_COUNT_MASK) 674 /*! @} */ 675 676 /*! @name EAR10 - ERM Memory 10 Error Address Register */ 677 /*! @{ */ 678 679 #define ERM_GTM_EAR10_EAR_MASK (0xFFFFFFFFU) 680 #define ERM_GTM_EAR10_EAR_SHIFT (0U) 681 #define ERM_GTM_EAR10_EAR_WIDTH (32U) 682 #define ERM_GTM_EAR10_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_EAR10_EAR_SHIFT)) & ERM_GTM_EAR10_EAR_MASK) 683 /*! @} */ 684 685 /*! @name SYN10 - ERM Memory 10 Syndrome Register */ 686 /*! @{ */ 687 688 #define ERM_GTM_SYN10_SYNDROME_MASK (0xFF000000U) 689 #define ERM_GTM_SYN10_SYNDROME_SHIFT (24U) 690 #define ERM_GTM_SYN10_SYNDROME_WIDTH (8U) 691 #define ERM_GTM_SYN10_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SYN10_SYNDROME_SHIFT)) & ERM_GTM_SYN10_SYNDROME_MASK) 692 /*! @} */ 693 694 /*! @name CORR_ERR_CNT10 - ERM Memory 10 Correctable Error Count Register */ 695 /*! @{ */ 696 697 #define ERM_GTM_CORR_ERR_CNT10_COUNT_MASK (0xFFU) 698 #define ERM_GTM_CORR_ERR_CNT10_COUNT_SHIFT (0U) 699 #define ERM_GTM_CORR_ERR_CNT10_COUNT_WIDTH (8U) 700 #define ERM_GTM_CORR_ERR_CNT10_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CORR_ERR_CNT10_COUNT_SHIFT)) & ERM_GTM_CORR_ERR_CNT10_COUNT_MASK) 701 /*! @} */ 702 703 /*! @name EAR11 - ERM Memory 11 Error Address Register */ 704 /*! @{ */ 705 706 #define ERM_GTM_EAR11_EAR_MASK (0xFFFFFFFFU) 707 #define ERM_GTM_EAR11_EAR_SHIFT (0U) 708 #define ERM_GTM_EAR11_EAR_WIDTH (32U) 709 #define ERM_GTM_EAR11_EAR(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_EAR11_EAR_SHIFT)) & ERM_GTM_EAR11_EAR_MASK) 710 /*! @} */ 711 712 /*! @name SYN11 - ERM Memory 11 Syndrome Register */ 713 /*! @{ */ 714 715 #define ERM_GTM_SYN11_SYNDROME_MASK (0xFF000000U) 716 #define ERM_GTM_SYN11_SYNDROME_SHIFT (24U) 717 #define ERM_GTM_SYN11_SYNDROME_WIDTH (8U) 718 #define ERM_GTM_SYN11_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_SYN11_SYNDROME_SHIFT)) & ERM_GTM_SYN11_SYNDROME_MASK) 719 /*! @} */ 720 721 /*! @name CORR_ERR_CNT11 - ERM Memory 11 Correctable Error Count Register */ 722 /*! @{ */ 723 724 #define ERM_GTM_CORR_ERR_CNT11_COUNT_MASK (0xFFU) 725 #define ERM_GTM_CORR_ERR_CNT11_COUNT_SHIFT (0U) 726 #define ERM_GTM_CORR_ERR_CNT11_COUNT_WIDTH (8U) 727 #define ERM_GTM_CORR_ERR_CNT11_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ERM_GTM_CORR_ERR_CNT11_COUNT_SHIFT)) & ERM_GTM_CORR_ERR_CNT11_COUNT_MASK) 728 /*! @} */ 729 730 /*! 731 * @} 732 */ /* end of group ERM_GTM_Register_Masks */ 733 734 /*! 735 * @} 736 */ /* end of group ERM_GTM_Peripheral_Access_Layer */ 737 738 #endif /* #if !defined(S32Z2_ERM_GTM_H_) */ 739
