1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_DMA_CRC.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_DMA_CRC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_DMA_CRC_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_DMA_CRC_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- DMA_CRC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup DMA_CRC_Peripheral_Access_Layer DMA_CRC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** DMA_CRC - Size of Registers Arrays */ 72 #define DMA_CRC_CONTROL_REGISTER_COUNT 8u 73 74 /** DMA_CRC - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t GEC; /**< Global Enable CRC Register, offset: 0x0 */ 77 uint8_t RESERVED_0[12]; 78 struct DMA_CRC_CONTROL_REGISTER { /* offset: 0x10, array step: 0x10 */ 79 __IO uint32_t CTL; /**< CRC Control Register, array offset: 0x10, array step: 0x10 */ 80 __IO uint32_t ICRC; /**< Initial CRC Value Register, array offset: 0x14, array step: 0x10 */ 81 __I uint32_t FCRC; /**< Final CRC Value Register, array offset: 0x18, array step: 0x10 */ 82 uint8_t RESERVED_0[4]; 83 } CONTROL_REGISTER[DMA_CRC_CONTROL_REGISTER_COUNT]; 84 } DMA_CRC_Type, *DMA_CRC_MemMapPtr; 85 86 /** Number of instances of the DMA_CRC module. */ 87 #define DMA_CRC_INSTANCE_COUNT (6u) 88 89 /* DMA_CRC - Peripheral instance base addresses */ 90 /** Peripheral CE_DMA_CRC base address */ 91 #define IP_CE_DMA_CRC_BASE (0x44E08000u) 92 /** Peripheral CE_DMA_CRC base pointer */ 93 #define IP_CE_DMA_CRC ((DMA_CRC_Type *)IP_CE_DMA_CRC_BASE) 94 /** Peripheral DMA_CRC_0 base address */ 95 #define IP_DMA_CRC_0_BASE (0x405E0000u) 96 /** Peripheral DMA_CRC_0 base pointer */ 97 #define IP_DMA_CRC_0 ((DMA_CRC_Type *)IP_DMA_CRC_0_BASE) 98 /** Peripheral DMA_CRC_1 base address */ 99 #define IP_DMA_CRC_1_BASE (0x40DE0000u) 100 /** Peripheral DMA_CRC_1 base pointer */ 101 #define IP_DMA_CRC_1 ((DMA_CRC_Type *)IP_DMA_CRC_1_BASE) 102 /** Peripheral DMA_CRC_3 base address */ 103 #define IP_DMA_CRC_3_BASE (0x41DE0000u) 104 /** Peripheral DMA_CRC_3 base pointer */ 105 #define IP_DMA_CRC_3 ((DMA_CRC_Type *)IP_DMA_CRC_3_BASE) 106 /** Peripheral DMA_CRC_4 base address */ 107 #define IP_DMA_CRC_4_BASE (0x425E0000u) 108 /** Peripheral DMA_CRC_4 base pointer */ 109 #define IP_DMA_CRC_4 ((DMA_CRC_Type *)IP_DMA_CRC_4_BASE) 110 /** Peripheral DMA_CRC_5 base address */ 111 #define IP_DMA_CRC_5_BASE (0x42DE0000u) 112 /** Peripheral DMA_CRC_5 base pointer */ 113 #define IP_DMA_CRC_5 ((DMA_CRC_Type *)IP_DMA_CRC_5_BASE) 114 /** Array initializer of DMA_CRC peripheral base addresses */ 115 #define IP_DMA_CRC_BASE_ADDRS { IP_CE_DMA_CRC_BASE, IP_DMA_CRC_0_BASE, IP_DMA_CRC_1_BASE, IP_DMA_CRC_3_BASE, IP_DMA_CRC_4_BASE, IP_DMA_CRC_5_BASE } 116 /** Array initializer of DMA_CRC peripheral base pointers */ 117 #define IP_DMA_CRC_BASE_PTRS { IP_CE_DMA_CRC, IP_DMA_CRC_0, IP_DMA_CRC_1, IP_DMA_CRC_3, IP_DMA_CRC_4, IP_DMA_CRC_5 } 118 119 /* ---------------------------------------------------------------------------- 120 -- DMA_CRC Register Masks 121 ---------------------------------------------------------------------------- */ 122 123 /*! 124 * @addtogroup DMA_CRC_Register_Masks DMA_CRC Register Masks 125 * @{ 126 */ 127 128 /*! @name GEC - Global Enable CRC Register */ 129 /*! @{ */ 130 131 #define DMA_CRC_GEC_GBL_EN_MASK (0x1U) 132 #define DMA_CRC_GEC_GBL_EN_SHIFT (0U) 133 #define DMA_CRC_GEC_GBL_EN_WIDTH (1U) 134 #define DMA_CRC_GEC_GBL_EN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CRC_GEC_GBL_EN_SHIFT)) & DMA_CRC_GEC_GBL_EN_MASK) 135 136 #define DMA_CRC_GEC_SWAP_BYTE_MASK (0x80U) 137 #define DMA_CRC_GEC_SWAP_BYTE_SHIFT (7U) 138 #define DMA_CRC_GEC_SWAP_BYTE_WIDTH (1U) 139 #define DMA_CRC_GEC_SWAP_BYTE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CRC_GEC_SWAP_BYTE_SHIFT)) & DMA_CRC_GEC_SWAP_BYTE_MASK) 140 /*! @} */ 141 142 /*! @name CTL - CRC Control Register */ 143 /*! @{ */ 144 145 #define DMA_CRC_CTL_CH_SEL_MASK (0x1FU) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ 146 #define DMA_CRC_CTL_CH_SEL_SHIFT (0U) 147 #define DMA_CRC_CTL_CH_SEL_WIDTH (5U) 148 #define DMA_CRC_CTL_CH_SEL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CRC_CTL_CH_SEL_SHIFT)) & DMA_CRC_CTL_CH_SEL_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ 149 150 #define DMA_CRC_CTL_POLY_SEL_MASK (0x700U) 151 #define DMA_CRC_CTL_POLY_SEL_SHIFT (8U) 152 #define DMA_CRC_CTL_POLY_SEL_WIDTH (3U) 153 #define DMA_CRC_CTL_POLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CRC_CTL_POLY_SEL_SHIFT)) & DMA_CRC_CTL_POLY_SEL_MASK) 154 155 #define DMA_CRC_CTL_CS_XOR_MASK (0x1000U) 156 #define DMA_CRC_CTL_CS_XOR_SHIFT (12U) 157 #define DMA_CRC_CTL_CS_XOR_WIDTH (1U) 158 #define DMA_CRC_CTL_CS_XOR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CRC_CTL_CS_XOR_SHIFT)) & DMA_CRC_CTL_CS_XOR_MASK) 159 160 #define DMA_CRC_CTL_CS_SWAP_MASK (0x2000U) 161 #define DMA_CRC_CTL_CS_SWAP_SHIFT (13U) 162 #define DMA_CRC_CTL_CS_SWAP_WIDTH (1U) 163 #define DMA_CRC_CTL_CS_SWAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CRC_CTL_CS_SWAP_SHIFT)) & DMA_CRC_CTL_CS_SWAP_MASK) 164 165 #define DMA_CRC_CTL_SWAP_BIT_MASK (0x4000U) 166 #define DMA_CRC_CTL_SWAP_BIT_SHIFT (14U) 167 #define DMA_CRC_CTL_SWAP_BIT_WIDTH (1U) 168 #define DMA_CRC_CTL_SWAP_BIT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CRC_CTL_SWAP_BIT_SHIFT)) & DMA_CRC_CTL_SWAP_BIT_MASK) 169 170 #define DMA_CRC_CTL_INIT_SEL_MASK (0x8000U) 171 #define DMA_CRC_CTL_INIT_SEL_SHIFT (15U) 172 #define DMA_CRC_CTL_INIT_SEL_WIDTH (1U) 173 #define DMA_CRC_CTL_INIT_SEL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CRC_CTL_INIT_SEL_SHIFT)) & DMA_CRC_CTL_INIT_SEL_MASK) 174 175 #define DMA_CRC_CTL_MODE_MASK (0x70000U) 176 #define DMA_CRC_CTL_MODE_SHIFT (16U) 177 #define DMA_CRC_CTL_MODE_WIDTH (3U) 178 #define DMA_CRC_CTL_MODE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CRC_CTL_MODE_SHIFT)) & DMA_CRC_CTL_MODE_MASK) 179 180 #define DMA_CRC_CTL_EN_MASK (0x80000000U) 181 #define DMA_CRC_CTL_EN_SHIFT (31U) 182 #define DMA_CRC_CTL_EN_WIDTH (1U) 183 #define DMA_CRC_CTL_EN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CRC_CTL_EN_SHIFT)) & DMA_CRC_CTL_EN_MASK) 184 /*! @} */ 185 186 /*! @name ICRC - Initial CRC Value Register */ 187 /*! @{ */ 188 189 #define DMA_CRC_ICRC_INI_CRC_VAL_MASK (0xFFFFFFFFU) 190 #define DMA_CRC_ICRC_INI_CRC_VAL_SHIFT (0U) 191 #define DMA_CRC_ICRC_INI_CRC_VAL_WIDTH (32U) 192 #define DMA_CRC_ICRC_INI_CRC_VAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CRC_ICRC_INI_CRC_VAL_SHIFT)) & DMA_CRC_ICRC_INI_CRC_VAL_MASK) 193 /*! @} */ 194 195 /*! @name FCRC - Final CRC Value Register */ 196 /*! @{ */ 197 198 #define DMA_CRC_FCRC_CHKSUM_VAL_MASK (0xFFFFFFFFU) 199 #define DMA_CRC_FCRC_CHKSUM_VAL_SHIFT (0U) 200 #define DMA_CRC_FCRC_CHKSUM_VAL_WIDTH (32U) 201 #define DMA_CRC_FCRC_CHKSUM_VAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CRC_FCRC_CHKSUM_VAL_SHIFT)) & DMA_CRC_FCRC_CHKSUM_VAL_MASK) 202 /*! @} */ 203 204 /*! 205 * @} 206 */ /* end of group DMA_CRC_Register_Masks */ 207 208 /*! 209 * @} 210 */ /* end of group DMA_CRC_Peripheral_Access_Layer */ 211 212 #endif /* #if !defined(S32Z2_DMA_CRC_H_) */ 213
