1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_DIPORTSD.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_DIPORTSD 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_DIPORTSD_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_DIPORTSD_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- DIPORTSD Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup DIPORTSD_Peripheral_Access_Layer DIPORTSD Peripheral Access Layer 68 * @{ 69 */ 70 71 /** DIPORTSD - Register Layout Typedef */ 72 typedef struct { 73 uint8_t RESERVED_0[256]; 74 __IO uint32_t ECR; /**< Error and Control Register, offset: 0x100 */ 75 __IO uint32_t SESR; /**< Error Status Register, offset: 0x104 */ 76 __IO uint32_t QOS; /**< Quality Of Service, offset: 0x108 */ 77 __IO uint32_t SIGEN; /**< Signaling Enable, offset: 0x10C */ 78 uint8_t RESERVED_1[8]; 79 uint32_t RSRV0; /**< Reserved 0, offset: 0x118 */ 80 uint8_t RESERVED_2[12]; 81 __IO uint32_t LAR0; /**< Logical Address Region 0, offset: 0x128 */ 82 __IO uint32_t PAR0; /**< Physical Address Region 0, offset: 0x12C */ 83 __IO uint32_t RS0; /**< Region Size 0, offset: 0x130 */ 84 __IO uint32_t LAR1; /**< Logical Address Region 1, offset: 0x134 */ 85 __IO uint32_t PAR1; /**< Physical Address Region 1, offset: 0x138 */ 86 __IO uint32_t RS1; /**< Region Size 1, offset: 0x13C */ 87 __IO uint32_t LAR2; /**< Logical Address Region 2, offset: 0x140 */ 88 __IO uint32_t PAR2; /**< Physical Address Region 2, offset: 0x144 */ 89 __IO uint32_t RS2; /**< Region Size 2, offset: 0x148 */ 90 __IO uint32_t LAR3; /**< Logical Address Region 3, offset: 0x14C */ 91 __IO uint32_t PAR3; /**< Physical Address Region 3, offset: 0x150 */ 92 __IO uint32_t RS3; /**< Region Size 3, offset: 0x154 */ 93 __IO uint32_t LAR4; /**< Logical Address Region 4, offset: 0x158 */ 94 __IO uint32_t PAR4; /**< Physical Address Region 4, offset: 0x15C */ 95 __IO uint32_t RS4; /**< Region Size 4, offset: 0x160 */ 96 __IO uint32_t LAR5; /**< Logical Address Region 5, offset: 0x164 */ 97 __IO uint32_t PAR5; /**< Physical Address Region 5, offset: 0x168 */ 98 __IO uint32_t RS5; /**< Region Size 5, offset: 0x16C */ 99 __IO uint32_t LAR6; /**< Logical Address Region 6, offset: 0x170 */ 100 __IO uint32_t PAR6; /**< Physical Address Region 6, offset: 0x174 */ 101 __IO uint32_t RS6; /**< Region Size 6, offset: 0x178 */ 102 __IO uint32_t LAR7; /**< Logical Address Region 7, offset: 0x17C */ 103 __IO uint32_t PAR7; /**< Physical Address Region 7, offset: 0x180 */ 104 __IO uint32_t RS7; /**< Region Size 7, offset: 0x184 */ 105 uint8_t RESERVED_3[120]; 106 uint32_t RSRV1; /**< Reserved 1, offset: 0x200 */ 107 uint32_t RSRV2; /**< Reserved 2, offset: 0x204 */ 108 uint32_t RSRV3; /**< Reserved 3, offset: 0x208 */ 109 uint32_t RSRV4; /**< Reserved 4, offset: 0x20C */ 110 uint32_t RSRV5; /**< Reserved 5, offset: 0x210 */ 111 } DIPORTSD_Type, *DIPORTSD_MemMapPtr; 112 113 /** Number of instances of the DIPORTSD module. */ 114 #define DIPORTSD_INSTANCE_COUNT (1u) 115 116 /* DIPORTSD - Peripheral instance base addresses */ 117 /** Peripheral DIPORTSD base address */ 118 #define IP_DIPORTSD_BASE (0x42960000u) 119 /** Peripheral DIPORTSD base pointer */ 120 #define IP_DIPORTSD ((DIPORTSD_Type *)IP_DIPORTSD_BASE) 121 /** Array initializer of DIPORTSD peripheral base addresses */ 122 #define IP_DIPORTSD_BASE_ADDRS { IP_DIPORTSD_BASE } 123 /** Array initializer of DIPORTSD peripheral base pointers */ 124 #define IP_DIPORTSD_BASE_PTRS { IP_DIPORTSD } 125 126 /* ---------------------------------------------------------------------------- 127 -- DIPORTSD Register Masks 128 ---------------------------------------------------------------------------- */ 129 130 /*! 131 * @addtogroup DIPORTSD_Register_Masks DIPORTSD Register Masks 132 * @{ 133 */ 134 135 /*! @name ECR - Error and Control Register */ 136 /*! @{ */ 137 138 #define DIPORTSD_ECR_NCRC_ERR_EN_MASK (0x1U) 139 #define DIPORTSD_ECR_NCRC_ERR_EN_SHIFT (0U) 140 #define DIPORTSD_ECR_NCRC_ERR_EN_WIDTH (1U) 141 #define DIPORTSD_ECR_NCRC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_ECR_NCRC_ERR_EN_SHIFT)) & DIPORTSD_ECR_NCRC_ERR_EN_MASK) 142 143 #define DIPORTSD_ECR_MFRM_ERR_EN_MASK (0x2U) 144 #define DIPORTSD_ECR_MFRM_ERR_EN_SHIFT (1U) 145 #define DIPORTSD_ECR_MFRM_ERR_EN_WIDTH (1U) 146 #define DIPORTSD_ECR_MFRM_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_ECR_MFRM_ERR_EN_SHIFT)) & DIPORTSD_ECR_MFRM_ERR_EN_MASK) 147 148 #define DIPORTSD_ECR_MID_ERR_EN_MASK (0x4U) 149 #define DIPORTSD_ECR_MID_ERR_EN_SHIFT (2U) 150 #define DIPORTSD_ECR_MID_ERR_EN_WIDTH (1U) 151 #define DIPORTSD_ECR_MID_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_ECR_MID_ERR_EN_SHIFT)) & DIPORTSD_ECR_MID_ERR_EN_MASK) 152 153 #define DIPORTSD_ECR_MPRC_ERR_EN_MASK (0x8U) 154 #define DIPORTSD_ECR_MPRC_ERR_EN_SHIFT (3U) 155 #define DIPORTSD_ECR_MPRC_ERR_EN_WIDTH (1U) 156 #define DIPORTSD_ECR_MPRC_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_ECR_MPRC_ERR_EN_SHIFT)) & DIPORTSD_ECR_MPRC_ERR_EN_MASK) 157 158 #define DIPORTSD_ECR_MADD_ERR_EN_MASK (0x10U) 159 #define DIPORTSD_ECR_MADD_ERR_EN_SHIFT (4U) 160 #define DIPORTSD_ECR_MADD_ERR_EN_WIDTH (1U) 161 #define DIPORTSD_ECR_MADD_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_ECR_MADD_ERR_EN_SHIFT)) & DIPORTSD_ECR_MADD_ERR_EN_MASK) 162 163 #define DIPORTSD_ECR_RSP_ERR_EN_MASK (0x20U) 164 #define DIPORTSD_ECR_RSP_ERR_EN_SHIFT (5U) 165 #define DIPORTSD_ECR_RSP_ERR_EN_WIDTH (1U) 166 #define DIPORTSD_ECR_RSP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_ECR_RSP_ERR_EN_SHIFT)) & DIPORTSD_ECR_RSP_ERR_EN_MASK) 167 168 #define DIPORTSD_ECR_REG_LOCK_MASK (0x80000000U) 169 #define DIPORTSD_ECR_REG_LOCK_SHIFT (31U) 170 #define DIPORTSD_ECR_REG_LOCK_WIDTH (1U) 171 #define DIPORTSD_ECR_REG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_ECR_REG_LOCK_SHIFT)) & DIPORTSD_ECR_REG_LOCK_MASK) 172 /*! @} */ 173 174 /*! @name SESR - Error Status Register */ 175 /*! @{ */ 176 177 #define DIPORTSD_SESR_NCRC_ERR_MASK (0x1U) 178 #define DIPORTSD_SESR_NCRC_ERR_SHIFT (0U) 179 #define DIPORTSD_SESR_NCRC_ERR_WIDTH (1U) 180 #define DIPORTSD_SESR_NCRC_ERR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_SESR_NCRC_ERR_SHIFT)) & DIPORTSD_SESR_NCRC_ERR_MASK) 181 182 #define DIPORTSD_SESR_MFRM_ERR_MASK (0x2U) 183 #define DIPORTSD_SESR_MFRM_ERR_SHIFT (1U) 184 #define DIPORTSD_SESR_MFRM_ERR_WIDTH (1U) 185 #define DIPORTSD_SESR_MFRM_ERR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_SESR_MFRM_ERR_SHIFT)) & DIPORTSD_SESR_MFRM_ERR_MASK) 186 187 #define DIPORTSD_SESR_MID_ERR_MASK (0x4U) 188 #define DIPORTSD_SESR_MID_ERR_SHIFT (2U) 189 #define DIPORTSD_SESR_MID_ERR_WIDTH (1U) 190 #define DIPORTSD_SESR_MID_ERR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_SESR_MID_ERR_SHIFT)) & DIPORTSD_SESR_MID_ERR_MASK) 191 192 #define DIPORTSD_SESR_MPRC_ERR_MASK (0x8U) 193 #define DIPORTSD_SESR_MPRC_ERR_SHIFT (3U) 194 #define DIPORTSD_SESR_MPRC_ERR_WIDTH (1U) 195 #define DIPORTSD_SESR_MPRC_ERR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_SESR_MPRC_ERR_SHIFT)) & DIPORTSD_SESR_MPRC_ERR_MASK) 196 197 #define DIPORTSD_SESR_MADD_ERR_MASK (0x10U) 198 #define DIPORTSD_SESR_MADD_ERR_SHIFT (4U) 199 #define DIPORTSD_SESR_MADD_ERR_WIDTH (1U) 200 #define DIPORTSD_SESR_MADD_ERR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_SESR_MADD_ERR_SHIFT)) & DIPORTSD_SESR_MADD_ERR_MASK) 201 202 #define DIPORTSD_SESR_RSP_ERR_MASK (0x20U) 203 #define DIPORTSD_SESR_RSP_ERR_SHIFT (5U) 204 #define DIPORTSD_SESR_RSP_ERR_WIDTH (1U) 205 #define DIPORTSD_SESR_RSP_ERR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_SESR_RSP_ERR_SHIFT)) & DIPORTSD_SESR_RSP_ERR_MASK) 206 /*! @} */ 207 208 /*! @name QOS - Quality Of Service */ 209 /*! @{ */ 210 211 #define DIPORTSD_QOS_SQOS_MASK (0x3U) 212 #define DIPORTSD_QOS_SQOS_SHIFT (0U) 213 #define DIPORTSD_QOS_SQOS_WIDTH (2U) 214 #define DIPORTSD_QOS_SQOS(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_QOS_SQOS_SHIFT)) & DIPORTSD_QOS_SQOS_MASK) 215 216 #define DIPORTSD_QOS_AABW_MASK (0x1F00U) 217 #define DIPORTSD_QOS_AABW_SHIFT (8U) 218 #define DIPORTSD_QOS_AABW_WIDTH (5U) 219 #define DIPORTSD_QOS_AABW(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_QOS_AABW_SHIFT)) & DIPORTSD_QOS_AABW_MASK) 220 /*! @} */ 221 222 /*! @name SIGEN - Signaling Enable */ 223 /*! @{ */ 224 225 #define DIPORTSD_SIGEN_SIGEN_MASK (0xFFU) 226 #define DIPORTSD_SIGEN_SIGEN_SHIFT (0U) 227 #define DIPORTSD_SIGEN_SIGEN_WIDTH (8U) 228 #define DIPORTSD_SIGEN_SIGEN(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_SIGEN_SIGEN_SHIFT)) & DIPORTSD_SIGEN_SIGEN_MASK) 229 /*! @} */ 230 231 /*! @name LAR0 - Logical Address Region 0 */ 232 /*! @{ */ 233 234 #define DIPORTSD_LAR0_START_ADDR_MASK (0xFFFFF000U) 235 #define DIPORTSD_LAR0_START_ADDR_SHIFT (12U) 236 #define DIPORTSD_LAR0_START_ADDR_WIDTH (20U) 237 #define DIPORTSD_LAR0_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_LAR0_START_ADDR_SHIFT)) & DIPORTSD_LAR0_START_ADDR_MASK) 238 /*! @} */ 239 240 /*! @name PAR0 - Physical Address Region 0 */ 241 /*! @{ */ 242 243 #define DIPORTSD_PAR0_START_ADDR_MASK (0xFFFFF000U) 244 #define DIPORTSD_PAR0_START_ADDR_SHIFT (12U) 245 #define DIPORTSD_PAR0_START_ADDR_WIDTH (20U) 246 #define DIPORTSD_PAR0_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_PAR0_START_ADDR_SHIFT)) & DIPORTSD_PAR0_START_ADDR_MASK) 247 /*! @} */ 248 249 /*! @name RS0 - Region Size 0 */ 250 /*! @{ */ 251 252 #define DIPORTSD_RS0_BLOCK_SIZE_MASK (0x1FU) 253 #define DIPORTSD_RS0_BLOCK_SIZE_SHIFT (0U) 254 #define DIPORTSD_RS0_BLOCK_SIZE_WIDTH (5U) 255 #define DIPORTSD_RS0_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_RS0_BLOCK_SIZE_SHIFT)) & DIPORTSD_RS0_BLOCK_SIZE_MASK) 256 /*! @} */ 257 258 /*! @name LAR1 - Logical Address Region 1 */ 259 /*! @{ */ 260 261 #define DIPORTSD_LAR1_START_ADDR_MASK (0xFFFFF000U) 262 #define DIPORTSD_LAR1_START_ADDR_SHIFT (12U) 263 #define DIPORTSD_LAR1_START_ADDR_WIDTH (20U) 264 #define DIPORTSD_LAR1_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_LAR1_START_ADDR_SHIFT)) & DIPORTSD_LAR1_START_ADDR_MASK) 265 /*! @} */ 266 267 /*! @name PAR1 - Physical Address Region 1 */ 268 /*! @{ */ 269 270 #define DIPORTSD_PAR1_START_ADDR_MASK (0xFFFFF000U) 271 #define DIPORTSD_PAR1_START_ADDR_SHIFT (12U) 272 #define DIPORTSD_PAR1_START_ADDR_WIDTH (20U) 273 #define DIPORTSD_PAR1_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_PAR1_START_ADDR_SHIFT)) & DIPORTSD_PAR1_START_ADDR_MASK) 274 /*! @} */ 275 276 /*! @name RS1 - Region Size 1 */ 277 /*! @{ */ 278 279 #define DIPORTSD_RS1_BLOCK_SIZE_MASK (0x1FU) 280 #define DIPORTSD_RS1_BLOCK_SIZE_SHIFT (0U) 281 #define DIPORTSD_RS1_BLOCK_SIZE_WIDTH (5U) 282 #define DIPORTSD_RS1_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_RS1_BLOCK_SIZE_SHIFT)) & DIPORTSD_RS1_BLOCK_SIZE_MASK) 283 /*! @} */ 284 285 /*! @name LAR2 - Logical Address Region 2 */ 286 /*! @{ */ 287 288 #define DIPORTSD_LAR2_START_ADDR_MASK (0xFFFFF000U) 289 #define DIPORTSD_LAR2_START_ADDR_SHIFT (12U) 290 #define DIPORTSD_LAR2_START_ADDR_WIDTH (20U) 291 #define DIPORTSD_LAR2_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_LAR2_START_ADDR_SHIFT)) & DIPORTSD_LAR2_START_ADDR_MASK) 292 /*! @} */ 293 294 /*! @name PAR2 - Physical Address Region 2 */ 295 /*! @{ */ 296 297 #define DIPORTSD_PAR2_START_ADDR_MASK (0xFFFFF000U) 298 #define DIPORTSD_PAR2_START_ADDR_SHIFT (12U) 299 #define DIPORTSD_PAR2_START_ADDR_WIDTH (20U) 300 #define DIPORTSD_PAR2_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_PAR2_START_ADDR_SHIFT)) & DIPORTSD_PAR2_START_ADDR_MASK) 301 /*! @} */ 302 303 /*! @name RS2 - Region Size 2 */ 304 /*! @{ */ 305 306 #define DIPORTSD_RS2_BLOCK_SIZE_MASK (0x1FU) 307 #define DIPORTSD_RS2_BLOCK_SIZE_SHIFT (0U) 308 #define DIPORTSD_RS2_BLOCK_SIZE_WIDTH (5U) 309 #define DIPORTSD_RS2_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_RS2_BLOCK_SIZE_SHIFT)) & DIPORTSD_RS2_BLOCK_SIZE_MASK) 310 /*! @} */ 311 312 /*! @name LAR3 - Logical Address Region 3 */ 313 /*! @{ */ 314 315 #define DIPORTSD_LAR3_START_ADDR_MASK (0xFFFFF000U) 316 #define DIPORTSD_LAR3_START_ADDR_SHIFT (12U) 317 #define DIPORTSD_LAR3_START_ADDR_WIDTH (20U) 318 #define DIPORTSD_LAR3_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_LAR3_START_ADDR_SHIFT)) & DIPORTSD_LAR3_START_ADDR_MASK) 319 /*! @} */ 320 321 /*! @name PAR3 - Physical Address Region 3 */ 322 /*! @{ */ 323 324 #define DIPORTSD_PAR3_START_ADDR_MASK (0xFFFFF000U) 325 #define DIPORTSD_PAR3_START_ADDR_SHIFT (12U) 326 #define DIPORTSD_PAR3_START_ADDR_WIDTH (20U) 327 #define DIPORTSD_PAR3_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_PAR3_START_ADDR_SHIFT)) & DIPORTSD_PAR3_START_ADDR_MASK) 328 /*! @} */ 329 330 /*! @name RS3 - Region Size 3 */ 331 /*! @{ */ 332 333 #define DIPORTSD_RS3_BLOCK_SIZE_MASK (0x1FU) 334 #define DIPORTSD_RS3_BLOCK_SIZE_SHIFT (0U) 335 #define DIPORTSD_RS3_BLOCK_SIZE_WIDTH (5U) 336 #define DIPORTSD_RS3_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_RS3_BLOCK_SIZE_SHIFT)) & DIPORTSD_RS3_BLOCK_SIZE_MASK) 337 /*! @} */ 338 339 /*! @name LAR4 - Logical Address Region 4 */ 340 /*! @{ */ 341 342 #define DIPORTSD_LAR4_START_ADDR_MASK (0xFFFFF000U) 343 #define DIPORTSD_LAR4_START_ADDR_SHIFT (12U) 344 #define DIPORTSD_LAR4_START_ADDR_WIDTH (20U) 345 #define DIPORTSD_LAR4_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_LAR4_START_ADDR_SHIFT)) & DIPORTSD_LAR4_START_ADDR_MASK) 346 /*! @} */ 347 348 /*! @name PAR4 - Physical Address Region 4 */ 349 /*! @{ */ 350 351 #define DIPORTSD_PAR4_START_ADDR_MASK (0xFFFFF000U) 352 #define DIPORTSD_PAR4_START_ADDR_SHIFT (12U) 353 #define DIPORTSD_PAR4_START_ADDR_WIDTH (20U) 354 #define DIPORTSD_PAR4_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_PAR4_START_ADDR_SHIFT)) & DIPORTSD_PAR4_START_ADDR_MASK) 355 /*! @} */ 356 357 /*! @name RS4 - Region Size 4 */ 358 /*! @{ */ 359 360 #define DIPORTSD_RS4_BLOCK_SIZE_MASK (0x1FU) 361 #define DIPORTSD_RS4_BLOCK_SIZE_SHIFT (0U) 362 #define DIPORTSD_RS4_BLOCK_SIZE_WIDTH (5U) 363 #define DIPORTSD_RS4_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_RS4_BLOCK_SIZE_SHIFT)) & DIPORTSD_RS4_BLOCK_SIZE_MASK) 364 /*! @} */ 365 366 /*! @name LAR5 - Logical Address Region 5 */ 367 /*! @{ */ 368 369 #define DIPORTSD_LAR5_START_ADDR_MASK (0xFFFFF000U) 370 #define DIPORTSD_LAR5_START_ADDR_SHIFT (12U) 371 #define DIPORTSD_LAR5_START_ADDR_WIDTH (20U) 372 #define DIPORTSD_LAR5_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_LAR5_START_ADDR_SHIFT)) & DIPORTSD_LAR5_START_ADDR_MASK) 373 /*! @} */ 374 375 /*! @name PAR5 - Physical Address Region 5 */ 376 /*! @{ */ 377 378 #define DIPORTSD_PAR5_START_ADDR_MASK (0xFFFFF000U) 379 #define DIPORTSD_PAR5_START_ADDR_SHIFT (12U) 380 #define DIPORTSD_PAR5_START_ADDR_WIDTH (20U) 381 #define DIPORTSD_PAR5_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_PAR5_START_ADDR_SHIFT)) & DIPORTSD_PAR5_START_ADDR_MASK) 382 /*! @} */ 383 384 /*! @name RS5 - Region Size 5 */ 385 /*! @{ */ 386 387 #define DIPORTSD_RS5_BLOCK_SIZE_MASK (0x1FU) 388 #define DIPORTSD_RS5_BLOCK_SIZE_SHIFT (0U) 389 #define DIPORTSD_RS5_BLOCK_SIZE_WIDTH (5U) 390 #define DIPORTSD_RS5_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_RS5_BLOCK_SIZE_SHIFT)) & DIPORTSD_RS5_BLOCK_SIZE_MASK) 391 /*! @} */ 392 393 /*! @name LAR6 - Logical Address Region 6 */ 394 /*! @{ */ 395 396 #define DIPORTSD_LAR6_START_ADDR_MASK (0xFFFFF000U) 397 #define DIPORTSD_LAR6_START_ADDR_SHIFT (12U) 398 #define DIPORTSD_LAR6_START_ADDR_WIDTH (20U) 399 #define DIPORTSD_LAR6_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_LAR6_START_ADDR_SHIFT)) & DIPORTSD_LAR6_START_ADDR_MASK) 400 /*! @} */ 401 402 /*! @name PAR6 - Physical Address Region 6 */ 403 /*! @{ */ 404 405 #define DIPORTSD_PAR6_START_ADDR_MASK (0xFFFFF000U) 406 #define DIPORTSD_PAR6_START_ADDR_SHIFT (12U) 407 #define DIPORTSD_PAR6_START_ADDR_WIDTH (20U) 408 #define DIPORTSD_PAR6_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_PAR6_START_ADDR_SHIFT)) & DIPORTSD_PAR6_START_ADDR_MASK) 409 /*! @} */ 410 411 /*! @name RS6 - Region Size 6 */ 412 /*! @{ */ 413 414 #define DIPORTSD_RS6_BLOCK_SIZE_MASK (0x1FU) 415 #define DIPORTSD_RS6_BLOCK_SIZE_SHIFT (0U) 416 #define DIPORTSD_RS6_BLOCK_SIZE_WIDTH (5U) 417 #define DIPORTSD_RS6_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_RS6_BLOCK_SIZE_SHIFT)) & DIPORTSD_RS6_BLOCK_SIZE_MASK) 418 /*! @} */ 419 420 /*! @name LAR7 - Logical Address Region 7 */ 421 /*! @{ */ 422 423 #define DIPORTSD_LAR7_START_ADDR_MASK (0xFFFFF000U) 424 #define DIPORTSD_LAR7_START_ADDR_SHIFT (12U) 425 #define DIPORTSD_LAR7_START_ADDR_WIDTH (20U) 426 #define DIPORTSD_LAR7_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_LAR7_START_ADDR_SHIFT)) & DIPORTSD_LAR7_START_ADDR_MASK) 427 /*! @} */ 428 429 /*! @name PAR7 - Physical Address Region 7 */ 430 /*! @{ */ 431 432 #define DIPORTSD_PAR7_START_ADDR_MASK (0xFFFFF000U) 433 #define DIPORTSD_PAR7_START_ADDR_SHIFT (12U) 434 #define DIPORTSD_PAR7_START_ADDR_WIDTH (20U) 435 #define DIPORTSD_PAR7_START_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_PAR7_START_ADDR_SHIFT)) & DIPORTSD_PAR7_START_ADDR_MASK) 436 /*! @} */ 437 438 /*! @name RS7 - Region Size 7 */ 439 /*! @{ */ 440 441 #define DIPORTSD_RS7_BLOCK_SIZE_MASK (0x1FU) 442 #define DIPORTSD_RS7_BLOCK_SIZE_SHIFT (0U) 443 #define DIPORTSD_RS7_BLOCK_SIZE_WIDTH (5U) 444 #define DIPORTSD_RS7_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DIPORTSD_RS7_BLOCK_SIZE_SHIFT)) & DIPORTSD_RS7_BLOCK_SIZE_MASK) 445 /*! @} */ 446 447 448 /*! 449 * @} 450 */ /* end of group DIPORTSD_Register_Masks */ 451 452 /*! 453 * @} 454 */ /* end of group DIPORTSD_Peripheral_Access_Layer */ 455 456 #endif /* #if !defined(S32Z2_DIPORTSD_H_) */ 457
