1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_CE_SRG_S.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_CE_SRG_S 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_CE_SRG_S_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_CE_SRG_S_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CE_SRG_S Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CE_SRG_S_Peripheral_Access_Layer CE_SRG_S Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CE_SRG_S - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t CR0; /**< Control 0, offset: 0x0 */ 74 uint8_t RESERVED_0[252]; 75 __IO uint32_t LCR0; /**< Lock Control 0, offset: 0x100 */ 76 __IO uint32_t LCR1; /**< Lock Control 1, offset: 0x104 */ 77 __IO uint32_t LCR2; /**< Lock Control 2, offset: 0x108 */ 78 __IO uint32_t LCR3; /**< Lock Control 3, offset: 0x10C */ 79 __IO uint32_t LCR4; /**< Lock Control 4, offset: 0x110 */ 80 uint8_t RESERVED_1[8]; 81 __IO uint32_t LCR7; /**< Lock Control 7, offset: 0x11C */ 82 uint8_t RESERVED_2[224]; 83 __IO uint32_t SR0; /**< Status 0, offset: 0x200 */ 84 } CE_SRG_S_Type, *CE_SRG_S_MemMapPtr; 85 86 /** Number of instances of the CE_SRG_S module. */ 87 #define CE_SRG_S_INSTANCE_COUNT (1u) 88 89 /* CE_SRG_S - Peripheral instance base addresses */ 90 /** Peripheral CE_SRG_S base address */ 91 #define IP_CE_SRG_S_BASE (0x44864000u) 92 /** Peripheral CE_SRG_S base pointer */ 93 #define IP_CE_SRG_S ((CE_SRG_S_Type *)IP_CE_SRG_S_BASE) 94 /** Array initializer of CE_SRG_S peripheral base addresses */ 95 #define IP_CE_SRG_S_BASE_ADDRS { IP_CE_SRG_S_BASE } 96 /** Array initializer of CE_SRG_S peripheral base pointers */ 97 #define IP_CE_SRG_S_BASE_PTRS { IP_CE_SRG_S } 98 99 /* ---------------------------------------------------------------------------- 100 -- CE_SRG_S Register Masks 101 ---------------------------------------------------------------------------- */ 102 103 /*! 104 * @addtogroup CE_SRG_S_Register_Masks CE_SRG_S Register Masks 105 * @{ 106 */ 107 108 /*! @name CR0 - Control 0 */ 109 /*! @{ */ 110 111 #define CE_SRG_S_CR0_MSTR0DOW_MASK (0x1U) 112 #define CE_SRG_S_CR0_MSTR0DOW_SHIFT (0U) 113 #define CE_SRG_S_CR0_MSTR0DOW_WIDTH (1U) 114 #define CE_SRG_S_CR0_MSTR0DOW(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_CR0_MSTR0DOW_SHIFT)) & CE_SRG_S_CR0_MSTR0DOW_MASK) 115 116 #define CE_SRG_S_CR0_C0CCMDOW_MASK (0x2U) 117 #define CE_SRG_S_CR0_C0CCMDOW_SHIFT (1U) 118 #define CE_SRG_S_CR0_C0CCMDOW_WIDTH (1U) 119 #define CE_SRG_S_CR0_C0CCMDOW(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_CR0_C0CCMDOW_SHIFT)) & CE_SRG_S_CR0_C0CCMDOW_MASK) 120 121 #define CE_SRG_S_CR0_C0CSMDOW_MASK (0x4U) 122 #define CE_SRG_S_CR0_C0CSMDOW_SHIFT (2U) 123 #define CE_SRG_S_CR0_C0CSMDOW_WIDTH (1U) 124 #define CE_SRG_S_CR0_C0CSMDOW(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_CR0_C0CSMDOW_SHIFT)) & CE_SRG_S_CR0_C0CSMDOW_MASK) 125 126 #define CE_SRG_S_CR0_DEDOW_MASK (0x8U) 127 #define CE_SRG_S_CR0_DEDOW_SHIFT (3U) 128 #define CE_SRG_S_CR0_DEDOW_WIDTH (1U) 129 #define CE_SRG_S_CR0_DEDOW(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_CR0_DEDOW_SHIFT)) & CE_SRG_S_CR0_DEDOW_MASK) 130 131 #define CE_SRG_S_CR0_C1CCMDOW_MASK (0x10U) 132 #define CE_SRG_S_CR0_C1CCMDOW_SHIFT (4U) 133 #define CE_SRG_S_CR0_C1CCMDOW_WIDTH (1U) 134 #define CE_SRG_S_CR0_C1CCMDOW(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_CR0_C1CCMDOW_SHIFT)) & CE_SRG_S_CR0_C1CCMDOW_MASK) 135 136 #define CE_SRG_S_CR0_C1CSMDOW_MASK (0x20U) 137 #define CE_SRG_S_CR0_C1CSMDOW_SHIFT (5U) 138 #define CE_SRG_S_CR0_C1CSMDOW_WIDTH (1U) 139 #define CE_SRG_S_CR0_C1CSMDOW(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_CR0_C1CSMDOW_SHIFT)) & CE_SRG_S_CR0_C1CSMDOW_MASK) 140 141 #define CE_SRG_S_CR0_MSTR0HPE_MASK (0x100U) 142 #define CE_SRG_S_CR0_MSTR0HPE_SHIFT (8U) 143 #define CE_SRG_S_CR0_MSTR0HPE_WIDTH (1U) 144 #define CE_SRG_S_CR0_MSTR0HPE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_CR0_MSTR0HPE_SHIFT)) & CE_SRG_S_CR0_MSTR0HPE_MASK) 145 146 #define CE_SRG_S_CR0_C0CCMHPE_MASK (0x200U) 147 #define CE_SRG_S_CR0_C0CCMHPE_SHIFT (9U) 148 #define CE_SRG_S_CR0_C0CCMHPE_WIDTH (1U) 149 #define CE_SRG_S_CR0_C0CCMHPE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_CR0_C0CCMHPE_SHIFT)) & CE_SRG_S_CR0_C0CCMHPE_MASK) 150 151 #define CE_SRG_S_CR0_C0CSMHPE_MASK (0x400U) 152 #define CE_SRG_S_CR0_C0CSMHPE_SHIFT (10U) 153 #define CE_SRG_S_CR0_C0CSMHPE_WIDTH (1U) 154 #define CE_SRG_S_CR0_C0CSMHPE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_CR0_C0CSMHPE_SHIFT)) & CE_SRG_S_CR0_C0CSMHPE_MASK) 155 156 #define CE_SRG_S_CR0_C1CCMHPE_MASK (0x1000U) 157 #define CE_SRG_S_CR0_C1CCMHPE_SHIFT (12U) 158 #define CE_SRG_S_CR0_C1CCMHPE_WIDTH (1U) 159 #define CE_SRG_S_CR0_C1CCMHPE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_CR0_C1CCMHPE_SHIFT)) & CE_SRG_S_CR0_C1CCMHPE_MASK) 160 161 #define CE_SRG_S_CR0_C1CSMHPE_MASK (0x2000U) 162 #define CE_SRG_S_CR0_C1CSMHPE_SHIFT (13U) 163 #define CE_SRG_S_CR0_C1CSMHPE_WIDTH (1U) 164 #define CE_SRG_S_CR0_C1CSMHPE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_CR0_C1CSMHPE_SHIFT)) & CE_SRG_S_CR0_C1CSMHPE_MASK) 165 166 #define CE_SRG_S_CR0_SLV0SBE_MASK (0x10000U) 167 #define CE_SRG_S_CR0_SLV0SBE_SHIFT (16U) 168 #define CE_SRG_S_CR0_SLV0SBE_WIDTH (1U) 169 #define CE_SRG_S_CR0_SLV0SBE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_CR0_SLV0SBE_SHIFT)) & CE_SRG_S_CR0_SLV0SBE_MASK) 170 171 #define CE_SRG_S_CR0_AIPS0SBE_MASK (0x20000U) 172 #define CE_SRG_S_CR0_AIPS0SBE_SHIFT (17U) 173 #define CE_SRG_S_CR0_AIPS0SBE_WIDTH (1U) 174 #define CE_SRG_S_CR0_AIPS0SBE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_CR0_AIPS0SBE_SHIFT)) & CE_SRG_S_CR0_AIPS0SBE_MASK) 175 176 #define CE_SRG_S_CR0_AIPS1SBE_MASK (0x40000U) 177 #define CE_SRG_S_CR0_AIPS1SBE_SHIFT (18U) 178 #define CE_SRG_S_CR0_AIPS1SBE_WIDTH (1U) 179 #define CE_SRG_S_CR0_AIPS1SBE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_CR0_AIPS1SBE_SHIFT)) & CE_SRG_S_CR0_AIPS1SBE_MASK) 180 181 #define CE_SRG_S_CR0_AIPS2SBE_MASK (0x80000U) 182 #define CE_SRG_S_CR0_AIPS2SBE_SHIFT (19U) 183 #define CE_SRG_S_CR0_AIPS2SBE_WIDTH (1U) 184 #define CE_SRG_S_CR0_AIPS2SBE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_CR0_AIPS2SBE_SHIFT)) & CE_SRG_S_CR0_AIPS2SBE_MASK) 185 186 #define CE_SRG_S_CR0_AIPS3SBE_MASK (0x100000U) 187 #define CE_SRG_S_CR0_AIPS3SBE_SHIFT (20U) 188 #define CE_SRG_S_CR0_AIPS3SBE_WIDTH (1U) 189 #define CE_SRG_S_CR0_AIPS3SBE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_CR0_AIPS3SBE_SHIFT)) & CE_SRG_S_CR0_AIPS3SBE_MASK) 190 /*! @} */ 191 192 /*! @name LCR0 - Lock Control 0 */ 193 /*! @{ */ 194 195 #define CE_SRG_S_LCR0_LNSMPU_MASK (0x10000U) 196 #define CE_SRG_S_LCR0_LNSMPU_SHIFT (16U) 197 #define CE_SRG_S_LCR0_LNSMPU_WIDTH (1U) 198 #define CE_SRG_S_LCR0_LNSMPU(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR0_LNSMPU_SHIFT)) & CE_SRG_S_LCR0_LNSMPU_MASK) 199 200 #define CE_SRG_S_LCR0_LNSVTOR_MASK (0x40000U) 201 #define CE_SRG_S_LCR0_LNSVTOR_SHIFT (18U) 202 #define CE_SRG_S_LCR0_LNSVTOR_WIDTH (1U) 203 #define CE_SRG_S_LCR0_LNSVTOR(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR0_LNSVTOR_SHIFT)) & CE_SRG_S_LCR0_LNSVTOR_MASK) 204 205 #define CE_SRG_S_LCR0_DID_MASK (0xF000000U) 206 #define CE_SRG_S_LCR0_DID_SHIFT (24U) 207 #define CE_SRG_S_LCR0_DID_WIDTH (4U) 208 #define CE_SRG_S_LCR0_DID(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR0_DID_SHIFT)) & CE_SRG_S_LCR0_DID_MASK) 209 210 #define CE_SRG_S_LCR0_LKR_MASK (0xC0000000U) 211 #define CE_SRG_S_LCR0_LKR_SHIFT (30U) 212 #define CE_SRG_S_LCR0_LKR_WIDTH (2U) 213 #define CE_SRG_S_LCR0_LKR(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR0_LKR_SHIFT)) & CE_SRG_S_LCR0_LKR_MASK) 214 /*! @} */ 215 216 /*! @name LCR1 - Lock Control 1 */ 217 /*! @{ */ 218 219 #define CE_SRG_S_LCR1_LNSMPU_MASK (0x10000U) 220 #define CE_SRG_S_LCR1_LNSMPU_SHIFT (16U) 221 #define CE_SRG_S_LCR1_LNSMPU_WIDTH (1U) 222 #define CE_SRG_S_LCR1_LNSMPU(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR1_LNSMPU_SHIFT)) & CE_SRG_S_LCR1_LNSMPU_MASK) 223 224 #define CE_SRG_S_LCR1_LNSVTOR_MASK (0x40000U) 225 #define CE_SRG_S_LCR1_LNSVTOR_SHIFT (18U) 226 #define CE_SRG_S_LCR1_LNSVTOR_WIDTH (1U) 227 #define CE_SRG_S_LCR1_LNSVTOR(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR1_LNSVTOR_SHIFT)) & CE_SRG_S_LCR1_LNSVTOR_MASK) 228 229 #define CE_SRG_S_LCR1_DID_MASK (0xF000000U) 230 #define CE_SRG_S_LCR1_DID_SHIFT (24U) 231 #define CE_SRG_S_LCR1_DID_WIDTH (4U) 232 #define CE_SRG_S_LCR1_DID(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR1_DID_SHIFT)) & CE_SRG_S_LCR1_DID_MASK) 233 234 #define CE_SRG_S_LCR1_LKR_MASK (0xC0000000U) 235 #define CE_SRG_S_LCR1_LKR_SHIFT (30U) 236 #define CE_SRG_S_LCR1_LKR_WIDTH (2U) 237 #define CE_SRG_S_LCR1_LKR(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR1_LKR_SHIFT)) & CE_SRG_S_LCR1_LKR_MASK) 238 /*! @} */ 239 240 /*! @name LCR2 - Lock Control 2 */ 241 /*! @{ */ 242 243 #define CE_SRG_S_LCR2_REMAP_EN_MASK (0x1U) 244 #define CE_SRG_S_LCR2_REMAP_EN_SHIFT (0U) 245 #define CE_SRG_S_LCR2_REMAP_EN_WIDTH (1U) 246 #define CE_SRG_S_LCR2_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR2_REMAP_EN_SHIFT)) & CE_SRG_S_LCR2_REMAP_EN_MASK) 247 248 #define CE_SRG_S_LCR2_REMAP0_MASK (0x100U) 249 #define CE_SRG_S_LCR2_REMAP0_SHIFT (8U) 250 #define CE_SRG_S_LCR2_REMAP0_WIDTH (1U) 251 #define CE_SRG_S_LCR2_REMAP0(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR2_REMAP0_SHIFT)) & CE_SRG_S_LCR2_REMAP0_MASK) 252 253 #define CE_SRG_S_LCR2_REMAP1_MASK (0x200U) 254 #define CE_SRG_S_LCR2_REMAP1_SHIFT (9U) 255 #define CE_SRG_S_LCR2_REMAP1_WIDTH (1U) 256 #define CE_SRG_S_LCR2_REMAP1(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR2_REMAP1_SHIFT)) & CE_SRG_S_LCR2_REMAP1_MASK) 257 258 #define CE_SRG_S_LCR2_REMAP2_MASK (0x400U) 259 #define CE_SRG_S_LCR2_REMAP2_SHIFT (10U) 260 #define CE_SRG_S_LCR2_REMAP2_WIDTH (1U) 261 #define CE_SRG_S_LCR2_REMAP2(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR2_REMAP2_SHIFT)) & CE_SRG_S_LCR2_REMAP2_MASK) 262 263 #define CE_SRG_S_LCR2_DID_MASK (0xF000000U) 264 #define CE_SRG_S_LCR2_DID_SHIFT (24U) 265 #define CE_SRG_S_LCR2_DID_WIDTH (4U) 266 #define CE_SRG_S_LCR2_DID(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR2_DID_SHIFT)) & CE_SRG_S_LCR2_DID_MASK) 267 268 #define CE_SRG_S_LCR2_LKR_MASK (0xC0000000U) 269 #define CE_SRG_S_LCR2_LKR_SHIFT (30U) 270 #define CE_SRG_S_LCR2_LKR_WIDTH (2U) 271 #define CE_SRG_S_LCR2_LKR(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR2_LKR_SHIFT)) & CE_SRG_S_LCR2_LKR_MASK) 272 /*! @} */ 273 274 /*! @name LCR3 - Lock Control 3 */ 275 /*! @{ */ 276 277 #define CE_SRG_S_LCR3_R0RO_MASK (0xF8U) 278 #define CE_SRG_S_LCR3_R0RO_SHIFT (3U) 279 #define CE_SRG_S_LCR3_R0RO_WIDTH (5U) 280 #define CE_SRG_S_LCR3_R0RO(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR3_R0RO_SHIFT)) & CE_SRG_S_LCR3_R0RO_MASK) 281 282 #define CE_SRG_S_LCR3_R1RO_MASK (0xF800U) 283 #define CE_SRG_S_LCR3_R1RO_SHIFT (11U) 284 #define CE_SRG_S_LCR3_R1RO_WIDTH (5U) 285 #define CE_SRG_S_LCR3_R1RO(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR3_R1RO_SHIFT)) & CE_SRG_S_LCR3_R1RO_MASK) 286 287 #define CE_SRG_S_LCR3_DID_MASK (0xF000000U) 288 #define CE_SRG_S_LCR3_DID_SHIFT (24U) 289 #define CE_SRG_S_LCR3_DID_WIDTH (4U) 290 #define CE_SRG_S_LCR3_DID(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR3_DID_SHIFT)) & CE_SRG_S_LCR3_DID_MASK) 291 292 #define CE_SRG_S_LCR3_LKR_MASK (0xC0000000U) 293 #define CE_SRG_S_LCR3_LKR_SHIFT (30U) 294 #define CE_SRG_S_LCR3_LKR_WIDTH (2U) 295 #define CE_SRG_S_LCR3_LKR(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR3_LKR_SHIFT)) & CE_SRG_S_LCR3_LKR_MASK) 296 /*! @} */ 297 298 /*! @name LCR4 - Lock Control 4 */ 299 /*! @{ */ 300 301 #define CE_SRG_S_LCR4_R2RO_MASK (0xF8U) 302 #define CE_SRG_S_LCR4_R2RO_SHIFT (3U) 303 #define CE_SRG_S_LCR4_R2RO_WIDTH (5U) 304 #define CE_SRG_S_LCR4_R2RO(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR4_R2RO_SHIFT)) & CE_SRG_S_LCR4_R2RO_MASK) 305 306 #define CE_SRG_S_LCR4_DID_MASK (0xF000000U) 307 #define CE_SRG_S_LCR4_DID_SHIFT (24U) 308 #define CE_SRG_S_LCR4_DID_WIDTH (4U) 309 #define CE_SRG_S_LCR4_DID(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR4_DID_SHIFT)) & CE_SRG_S_LCR4_DID_MASK) 310 311 #define CE_SRG_S_LCR4_LKR_MASK (0xC0000000U) 312 #define CE_SRG_S_LCR4_LKR_SHIFT (30U) 313 #define CE_SRG_S_LCR4_LKR_WIDTH (2U) 314 #define CE_SRG_S_LCR4_LKR(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR4_LKR_SHIFT)) & CE_SRG_S_LCR4_LKR_MASK) 315 /*! @} */ 316 317 /*! @name LCR7 - Lock Control 7 */ 318 /*! @{ */ 319 320 #define CE_SRG_S_LCR7_C0DBGSA_MASK (0x10000U) 321 #define CE_SRG_S_LCR7_C0DBGSA_SHIFT (16U) 322 #define CE_SRG_S_LCR7_C0DBGSA_WIDTH (1U) 323 #define CE_SRG_S_LCR7_C0DBGSA(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR7_C0DBGSA_SHIFT)) & CE_SRG_S_LCR7_C0DBGSA_MASK) 324 325 #define CE_SRG_S_LCR7_C1DBGSA_MASK (0x20000U) 326 #define CE_SRG_S_LCR7_C1DBGSA_SHIFT (17U) 327 #define CE_SRG_S_LCR7_C1DBGSA_WIDTH (1U) 328 #define CE_SRG_S_LCR7_C1DBGSA(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR7_C1DBGSA_SHIFT)) & CE_SRG_S_LCR7_C1DBGSA_MASK) 329 330 #define CE_SRG_S_LCR7_DID_MASK (0xF000000U) 331 #define CE_SRG_S_LCR7_DID_SHIFT (24U) 332 #define CE_SRG_S_LCR7_DID_WIDTH (4U) 333 #define CE_SRG_S_LCR7_DID(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR7_DID_SHIFT)) & CE_SRG_S_LCR7_DID_MASK) 334 335 #define CE_SRG_S_LCR7_LKR_MASK (0xC0000000U) 336 #define CE_SRG_S_LCR7_LKR_SHIFT (30U) 337 #define CE_SRG_S_LCR7_LKR_WIDTH (2U) 338 #define CE_SRG_S_LCR7_LKR(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_LCR7_LKR_SHIFT)) & CE_SRG_S_LCR7_LKR_MASK) 339 /*! @} */ 340 341 /*! @name SR0 - Status 0 */ 342 /*! @{ */ 343 344 #define CE_SRG_S_SR0_R0EA_MASK (0x1U) 345 #define CE_SRG_S_SR0_R0EA_SHIFT (0U) 346 #define CE_SRG_S_SR0_R0EA_WIDTH (1U) 347 #define CE_SRG_S_SR0_R0EA(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_R0EA_SHIFT)) & CE_SRG_S_SR0_R0EA_MASK) 348 349 #define CE_SRG_S_SR0_R1EA_MASK (0x2U) 350 #define CE_SRG_S_SR0_R1EA_SHIFT (1U) 351 #define CE_SRG_S_SR0_R1EA_WIDTH (1U) 352 #define CE_SRG_S_SR0_R1EA(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_R1EA_SHIFT)) & CE_SRG_S_SR0_R1EA_MASK) 353 354 #define CE_SRG_S_SR0_R2EA_MASK (0x4U) 355 #define CE_SRG_S_SR0_R2EA_SHIFT (2U) 356 #define CE_SRG_S_SR0_R2EA_WIDTH (1U) 357 #define CE_SRG_S_SR0_R2EA(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_R2EA_SHIFT)) & CE_SRG_S_SR0_R2EA_MASK) 358 359 #define CE_SRG_S_SR0_R0WEA_MASK (0x10U) 360 #define CE_SRG_S_SR0_R0WEA_SHIFT (4U) 361 #define CE_SRG_S_SR0_R0WEA_WIDTH (1U) 362 #define CE_SRG_S_SR0_R0WEA(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_R0WEA_SHIFT)) & CE_SRG_S_SR0_R0WEA_MASK) 363 364 #define CE_SRG_S_SR0_R1WEA_MASK (0x20U) 365 #define CE_SRG_S_SR0_R1WEA_SHIFT (5U) 366 #define CE_SRG_S_SR0_R1WEA_WIDTH (1U) 367 #define CE_SRG_S_SR0_R1WEA(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_R1WEA_SHIFT)) & CE_SRG_S_SR0_R1WEA_MASK) 368 369 #define CE_SRG_S_SR0_R2WEA_MASK (0x40U) 370 #define CE_SRG_S_SR0_R2WEA_SHIFT (6U) 371 #define CE_SRG_S_SR0_R2WEA_WIDTH (1U) 372 #define CE_SRG_S_SR0_R2WEA(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_R2WEA_SHIFT)) & CE_SRG_S_SR0_R2WEA_MASK) 373 374 #define CE_SRG_S_SR0_C0CTRE_MASK (0x100U) 375 #define CE_SRG_S_SR0_C0CTRE_SHIFT (8U) 376 #define CE_SRG_S_SR0_C0CTRE_WIDTH (1U) 377 #define CE_SRG_S_SR0_C0CTRE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_C0CTRE_SHIFT)) & CE_SRG_S_SR0_C0CTRE_MASK) 378 379 #define CE_SRG_S_SR0_C0CDRE_MASK (0x200U) 380 #define CE_SRG_S_SR0_C0CDRE_SHIFT (9U) 381 #define CE_SRG_S_SR0_C0CDRE_WIDTH (1U) 382 #define CE_SRG_S_SR0_C0CDRE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_C0CDRE_SHIFT)) & CE_SRG_S_SR0_C0CDRE_MASK) 383 384 #define CE_SRG_S_SR0_C0STRE_MASK (0x400U) 385 #define CE_SRG_S_SR0_C0STRE_SHIFT (10U) 386 #define CE_SRG_S_SR0_C0STRE_WIDTH (1U) 387 #define CE_SRG_S_SR0_C0STRE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_C0STRE_SHIFT)) & CE_SRG_S_SR0_C0STRE_MASK) 388 389 #define CE_SRG_S_SR0_C0SDRE_MASK (0x800U) 390 #define CE_SRG_S_SR0_C0SDRE_SHIFT (11U) 391 #define CE_SRG_S_SR0_C0SDRE_WIDTH (1U) 392 #define CE_SRG_S_SR0_C0SDRE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_C0SDRE_SHIFT)) & CE_SRG_S_SR0_C0SDRE_MASK) 393 394 #define CE_SRG_S_SR0_C1CTRE_MASK (0x1000U) 395 #define CE_SRG_S_SR0_C1CTRE_SHIFT (12U) 396 #define CE_SRG_S_SR0_C1CTRE_WIDTH (1U) 397 #define CE_SRG_S_SR0_C1CTRE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_C1CTRE_SHIFT)) & CE_SRG_S_SR0_C1CTRE_MASK) 398 399 #define CE_SRG_S_SR0_C1CDRE_MASK (0x2000U) 400 #define CE_SRG_S_SR0_C1CDRE_SHIFT (13U) 401 #define CE_SRG_S_SR0_C1CDRE_WIDTH (1U) 402 #define CE_SRG_S_SR0_C1CDRE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_C1CDRE_SHIFT)) & CE_SRG_S_SR0_C1CDRE_MASK) 403 404 #define CE_SRG_S_SR0_C1STRE_MASK (0x4000U) 405 #define CE_SRG_S_SR0_C1STRE_SHIFT (14U) 406 #define CE_SRG_S_SR0_C1STRE_WIDTH (1U) 407 #define CE_SRG_S_SR0_C1STRE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_C1STRE_SHIFT)) & CE_SRG_S_SR0_C1STRE_MASK) 408 409 #define CE_SRG_S_SR0_C1SDRE_MASK (0x8000U) 410 #define CE_SRG_S_SR0_C1SDRE_SHIFT (15U) 411 #define CE_SRG_S_SR0_C1SDRE_WIDTH (1U) 412 #define CE_SRG_S_SR0_C1SDRE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_C1SDRE_SHIFT)) & CE_SRG_S_SR0_C1SDRE_MASK) 413 414 #define CE_SRG_S_SR0_C0CCCMCRE_MASK (0x10000U) 415 #define CE_SRG_S_SR0_C0CCCMCRE_SHIFT (16U) 416 #define CE_SRG_S_SR0_C0CCCMCRE_WIDTH (1U) 417 #define CE_SRG_S_SR0_C0CCCMCRE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_C0CCCMCRE_SHIFT)) & CE_SRG_S_SR0_C0CCCMCRE_MASK) 418 419 #define CE_SRG_S_SR0_C0SCCMCRE_MASK (0x20000U) 420 #define CE_SRG_S_SR0_C0SCCMCRE_SHIFT (17U) 421 #define CE_SRG_S_SR0_C0SCCMCRE_WIDTH (1U) 422 #define CE_SRG_S_SR0_C0SCCMCRE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_C0SCCMCRE_SHIFT)) & CE_SRG_S_SR0_C0SCCMCRE_MASK) 423 424 #define CE_SRG_S_SR0_C1CCCMCRE_MASK (0x40000U) 425 #define CE_SRG_S_SR0_C1CCCMCRE_SHIFT (18U) 426 #define CE_SRG_S_SR0_C1CCCMCRE_WIDTH (1U) 427 #define CE_SRG_S_SR0_C1CCCMCRE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_C1CCCMCRE_SHIFT)) & CE_SRG_S_SR0_C1CCCMCRE_MASK) 428 429 #define CE_SRG_S_SR0_C1SCCMCRE_MASK (0x80000U) 430 #define CE_SRG_S_SR0_C1SCCMCRE_SHIFT (19U) 431 #define CE_SRG_S_SR0_C1SCCMCRE_WIDTH (1U) 432 #define CE_SRG_S_SR0_C1SCCMCRE(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_C1SCCMCRE_SHIFT)) & CE_SRG_S_SR0_C1SCCMCRE_MASK) 433 434 #define CE_SRG_S_SR0_CORE0H_MASK (0x100000U) 435 #define CE_SRG_S_SR0_CORE0H_SHIFT (20U) 436 #define CE_SRG_S_SR0_CORE0H_WIDTH (1U) 437 #define CE_SRG_S_SR0_CORE0H(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_CORE0H_SHIFT)) & CE_SRG_S_SR0_CORE0H_MASK) 438 439 #define CE_SRG_S_SR0_CORE0TU_MASK (0x200000U) 440 #define CE_SRG_S_SR0_CORE0TU_SHIFT (21U) 441 #define CE_SRG_S_SR0_CORE0TU_WIDTH (1U) 442 #define CE_SRG_S_SR0_CORE0TU(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_CORE0TU_SHIFT)) & CE_SRG_S_SR0_CORE0TU_MASK) 443 444 #define CE_SRG_S_SR0_CORE1H_MASK (0x400000U) 445 #define CE_SRG_S_SR0_CORE1H_SHIFT (22U) 446 #define CE_SRG_S_SR0_CORE1H_WIDTH (1U) 447 #define CE_SRG_S_SR0_CORE1H(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_CORE1H_SHIFT)) & CE_SRG_S_SR0_CORE1H_MASK) 448 449 #define CE_SRG_S_SR0_CORE1TU_MASK (0x800000U) 450 #define CE_SRG_S_SR0_CORE1TU_SHIFT (23U) 451 #define CE_SRG_S_SR0_CORE1TU_WIDTH (1U) 452 #define CE_SRG_S_SR0_CORE1TU(x) (((uint32_t)(((uint32_t)(x)) << CE_SRG_S_SR0_CORE1TU_SHIFT)) & CE_SRG_S_SR0_CORE1TU_MASK) 453 /*! @} */ 454 455 /*! 456 * @} 457 */ /* end of group CE_SRG_S_Register_Masks */ 458 459 /*! 460 * @} 461 */ /* end of group CE_SRG_S_Peripheral_Access_Layer */ 462 463 #endif /* #if !defined(S32Z2_CE_SRG_S_H_) */ 464
