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Searched refs:IPRXFSTS (Results 1 – 25 of 105) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/flexspi/
Dfsl_flexspi.h588 … *rxCount = (((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * 8U; in FLEXSPI_GetFifoCounts()
Dfsl_flexspi.c762 …while (size > ((((base->IPRXFSTS) & FLEXSPI_IPRXFSTS_FILL_MASK) >> FLEXSPI_IPRXFSTS_FILL_SHIFT) * … in FLEXSPI_ReadBlocking()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h7163 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ member
DMIMXRT685S_cm33.h13140 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h15940 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h13426 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h13140 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h13464 __I uint32_t IPRXFSTS; /**< IP Receive FIFO Status, offset: 0xF0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h13464 __I uint32_t IPRXFSTS; /**< IP Receive FIFO Status, offset: 0xF0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h13009 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h19279 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h19259 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h21388 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h20236 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h19603 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h21390 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h21021 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h21765 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h26878 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h26876 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_cm7.h26876 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ member
DMIMX8MN6_ca53.h26904 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h22551 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h22624 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h19606 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */ member

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