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Searched refs:IOMUXD_QSPI1A_SS1_B_PDRV_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QM6/
DMIMX8QM6_ca53.h49995 #define IOMUXD_QSPI1A_SS1_B_PDRV_MASK (0x1U) macro
50001 … (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS1_B_PDRV_SHIFT)) & IOMUXD_QSPI1A_SS1_B_PDRV_MASK)
DMIMX8QM6_dsp.h52833 #define IOMUXD_QSPI1A_SS1_B_PDRV_MASK (0x1U) macro
52839 … (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS1_B_PDRV_SHIFT)) & IOMUXD_QSPI1A_SS1_B_PDRV_MASK)
DMIMX8QM6_cm4_core1.h37983 #define IOMUXD_QSPI1A_SS1_B_PDRV_MASK (0x1U) macro
37985 … (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS1_B_PDRV_SHIFT)) & IOMUXD_QSPI1A_SS1_B_PDRV_MASK)
DMIMX8QM6_cm4_core0.h37983 #define IOMUXD_QSPI1A_SS1_B_PDRV_MASK (0x1U) macro
37985 … (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI1A_SS1_B_PDRV_SHIFT)) & IOMUXD_QSPI1A_SS1_B_PDRV_MASK)